gcc/config/i386/mmx.md

   1 ;; GCC machine description for MMX and 3dNOW! instructions
   2 ;; Copyright (C) 2005-2016 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; The MMX and 3dNOW! patterns are in the same file because they use
  21 ;; the same register file, and 3dNOW! adds a number of extensions to
  22 ;; the base integer MMX isa.
  23
  24 ;; Note!  Except for the basic move instructions, *all* of these
  25 ;; patterns are outside the normal optabs namespace.  This is because
  26 ;; use of these registers requires the insertion of emms or femms
  27 ;; instructions to return to normal fpu mode.  The compiler doesn't
  28 ;; know how to do that itself, which means it's up to the user.  Which
  29 ;; means that we should never use any of these patterns except at the
  30 ;; direction of the user via a builtin.
  31
  32 (define_c_enum "unspec" [
  33   UNSPEC_MOVNTQ
  34   UNSPEC_PFRCP
  35   UNSPEC_PFRCPIT1
  36   UNSPEC_PFRCPIT2
  37   UNSPEC_PFRSQRT
  38   UNSPEC_PFRSQIT1
  39 ])
  40
  41 (define_c_enum "unspecv" [
  42   UNSPECV_EMMS
  43   UNSPECV_FEMMS
  44 ])
  45
  46 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
  47 (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
  48 (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI])
  49
  50 ;; All 8-byte vector modes handled by MMX
  51 (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF])
  52
  53 ;; Mix-n-match
  54 (define_mode_iterator MMXMODE12 [V8QI V4HI])
  55 (define_mode_iterator MMXMODE24 [V4HI V2SI])
  56 (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
  57
  58 ;; Mapping from integer vector mode to mnemonic suffix
  59 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (V1DI "q")])
  60
  61 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  62 ;;
  63 ;; Move patterns
  64 ;;
  65 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  66
  67 ;; All of these patterns are enabled for MMX as well as 3dNOW.
  68 ;; This is essential for maintaining stable calling conventions.
  69
  70 (define_expand "mov<mode>"
  71   [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
  72         (match_operand:MMXMODE 1 "nonimmediate_operand"))]
  73   "TARGET_MMX"
  74 {
  75   ix86_expand_vector_move (<MODE>mode, operands);
  76   DONE;
  77 })
  78
  79 (define_insn "*mov<mode>_internal"
  80   [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
  81     "=r ,o ,r,r ,m ,?!y,!y,?!y,m  ,r   ,?!Ym,v,v,v,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi")
  82         (match_operand:MMXMODE 1 "vector_move_operand"
  83     "rCo,rC,C,rm,rC,C  ,!y,m  ,?!y,?!Yn,r   ,C,v,m,v,C ,*x,m ,*x,Yj,r ,*Yj,!Yn"))]
  84   "TARGET_MMX
  85    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  86 {
  87   switch (get_attr_type (insn))
  88     {
  89     case TYPE_MULTI:
  90       return "#";
  91
  92     case TYPE_IMOV:
  93       if (get_attr_mode (insn) == MODE_SI)
  94         return "mov{l}\t{%1, %k0|%k0, %1}";
  95       else
  96         return "mov{q}\t{%1, %0|%0, %1}";
  97
  98     case TYPE_MMX:
  99       return "pxor\t%0, %0";
 100
 101     case TYPE_MMXMOV:
 102       /* Handle broken assemblers that require movd instead of movq.  */
 103       if (!HAVE_AS_IX86_INTERUNIT_MOVQ
 104           && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
 105         return "movd\t{%1, %0|%0, %1}";
 106       return "movq\t{%1, %0|%0, %1}";
 107
 108     case TYPE_SSECVT:
 109       if (SSE_REG_P (operands[0]))
 110         return "movq2dq\t{%1, %0|%0, %1}";
 111       else
 112         return "movdq2q\t{%1, %0|%0, %1}";
 113
 114     case TYPE_SSELOG1:
 115       return standard_sse_constant_opcode (insn, operands[1]);
 116
 117     case TYPE_SSEMOV:
 118       switch (get_attr_mode (insn))
 119         {
 120         case MODE_DI:
 121           /* Handle broken assemblers that require movd instead of movq.  */
 122           if (!HAVE_AS_IX86_INTERUNIT_MOVQ
 123               && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
 124             return "%vmovd\t{%1, %0|%0, %1}";
 125           return "%vmovq\t{%1, %0|%0, %1}";
 126         case MODE_TI:
 127           return "%vmovdqa\t{%1, %0|%0, %1}";
 128         case MODE_XI:
 129           return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
 130
 131         case MODE_V2SF:
 132           if (TARGET_AVX && REG_P (operands[0]))
 133             return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
 134           return "%vmovlps\t{%1, %0|%0, %1}";
 135         case MODE_V4SF:
 136           return "%vmovaps\t{%1, %0|%0, %1}";
 137
 138         default:
 139           gcc_unreachable ();
 140         }
 141
 142     default:
 143       gcc_unreachable ();
 144     }
 145 }
 146   [(set (attr "isa")
 147      (cond [(eq_attr "alternative" "0,1")
 148               (const_string "nox64")
 149             (eq_attr "alternative" "2,3,4,9,10,11,12,13,14,19,20")
 150               (const_string "x64")
 151            ]
 152            (const_string "*")))
 153    (set (attr "type")
 154      (cond [(eq_attr "alternative" "0,1")
 155               (const_string "multi")
 156             (eq_attr "alternative" "2,3,4")
 157               (const_string "imov")
 158             (eq_attr "alternative" "5")
 159               (const_string "mmx")
 160             (eq_attr "alternative" "6,7,8,9,10")
 161               (const_string "mmxmov")
 162             (eq_attr "alternative" "11,15")
 163               (const_string "sselog1")
 164             (eq_attr "alternative" "21,22")
 165               (const_string "ssecvt")
 166            ]
 167            (const_string "ssemov")))
 168    (set (attr "prefix_rex")
 169      (if_then_else (eq_attr "alternative" "9,10,19,20")
 170        (const_string "1")
 171        (const_string "*")))
 172    (set (attr "prefix")
 173      (if_then_else (eq_attr "type" "sselog1,ssemov")
 174        (const_string "maybe_vex")
 175        (const_string "orig")))
 176    (set (attr "prefix_data16")
 177      (if_then_else
 178        (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
 179        (const_string "1")
 180        (const_string "*")))
 181    (set (attr "mode")
 182      (cond [(eq_attr "alternative" "2")
 183               (const_string "SI")
 184             (eq_attr "alternative" "11,12,15,16")
 185               (cond [(ior (match_operand 0 "ext_sse_reg_operand")
 186                           (match_operand 1 "ext_sse_reg_operand"))
 187                         (const_string "XI")
 188                      (match_test "<MODE>mode == V2SFmode")
 189                        (const_string "V4SF")
 190                      (ior (not (match_test "TARGET_SSE2"))
 191                           (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
 192                        (const_string "V4SF")
 193                      (match_test "TARGET_AVX")
 194                        (const_string "TI")
 195                      (match_test "optimize_function_for_size_p (cfun)")
 196                        (const_string "V4SF")
 197                     ]
 198                     (const_string "TI"))
 199
 200             (and (eq_attr "alternative" "13,14,17,18")
 201                  (ior (match_test "<MODE>mode == V2SFmode")
 202                       (not (match_test "TARGET_SSE2"))))
 203               (const_string "V2SF")
 204            ]
 205            (const_string "DI")))])
 206
 207 (define_split
 208   [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
 209         (match_operand:MMXMODE 1 "general_operand"))]
 210   "!TARGET_64BIT && reload_completed
 211    && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
 212    && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
 213   [(const_int 0)]
 214   "ix86_split_long_move (operands); DONE;")
 215
 216 (define_expand "movmisalign<mode>"
 217   [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
 218         (match_operand:MMXMODE 1 "nonimmediate_operand"))]
 219   "TARGET_MMX"
 220 {
 221   ix86_expand_vector_move (<MODE>mode, operands);
 222   DONE;
 223 })
 224
 225 (define_insn "sse_movntq"
 226   [(set (match_operand:DI 0 "memory_operand" "=m")
 227         (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
 228                    UNSPEC_MOVNTQ))]
 229   "TARGET_SSE || TARGET_3DNOW_A"
 230   "movntq\t{%1, %0|%0, %1}"
 231   [(set_attr "type" "mmxmov")
 232    (set_attr "mode" "DI")])
 233
 234 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 235 ;;
 236 ;; Parallel single-precision floating point arithmetic
 237 ;;
 238 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 239
 240 (define_expand "mmx_addv2sf3"
 241   [(set (match_operand:V2SF 0 "register_operand")
 242         (plus:V2SF
 243           (match_operand:V2SF 1 "nonimmediate_operand")
 244           (match_operand:V2SF 2 "nonimmediate_operand")))]
 245   "TARGET_3DNOW"
 246   "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
 247
 248 (define_insn "*mmx_addv2sf3"
 249   [(set (match_operand:V2SF 0 "register_operand" "=y")
 250         (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
 251                    (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 252   "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
 253   "pfadd\t{%2, %0|%0, %2}"
 254   [(set_attr "type" "mmxadd")
 255    (set_attr "prefix_extra" "1")
 256    (set_attr "mode" "V2SF")])
 257
 258 (define_expand "mmx_subv2sf3"
 259   [(set (match_operand:V2SF 0 "register_operand")
 260         (minus:V2SF (match_operand:V2SF 1 "register_operand")
 261                     (match_operand:V2SF 2 "nonimmediate_operand")))]
 262   "TARGET_3DNOW")
 263
 264 (define_expand "mmx_subrv2sf3"
 265   [(set (match_operand:V2SF 0 "register_operand")
 266         (minus:V2SF (match_operand:V2SF 2 "register_operand")
 267                     (match_operand:V2SF 1 "nonimmediate_operand")))]
 268   "TARGET_3DNOW")
 269
 270 (define_insn "*mmx_subv2sf3"
 271   [(set (match_operand:V2SF 0 "register_operand" "=y,y")
 272         (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
 273                     (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
 274   "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 275   "@
 276    pfsub\t{%2, %0|%0, %2}
 277    pfsubr\t{%1, %0|%0, %1}"
 278   [(set_attr "type" "mmxadd")
 279    (set_attr "prefix_extra" "1")
 280    (set_attr "mode" "V2SF")])
 281
 282 (define_expand "mmx_mulv2sf3"
 283   [(set (match_operand:V2SF 0 "register_operand")
 284         (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
 285                    (match_operand:V2SF 2 "nonimmediate_operand")))]
 286   "TARGET_3DNOW"
 287   "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
 288
 289 (define_insn "*mmx_mulv2sf3"
 290   [(set (match_operand:V2SF 0 "register_operand" "=y")
 291         (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
 292                    (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 293   "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
 294   "pfmul\t{%2, %0|%0, %2}"
 295   [(set_attr "type" "mmxmul")
 296    (set_attr "prefix_extra" "1")
 297    (set_attr "mode" "V2SF")])
 298
 299 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
 300 ;; isn't really correct, as those rtl operators aren't defined when
 301 ;; applied to NaNs.  Hopefully the optimizers won't get too smart on us.
 302
 303 (define_expand "mmx_<code>v2sf3"
 304   [(set (match_operand:V2SF 0 "register_operand")
 305         (smaxmin:V2SF
 306           (match_operand:V2SF 1 "nonimmediate_operand")
 307           (match_operand:V2SF 2 "nonimmediate_operand")))]
 308   "TARGET_3DNOW"
 309 {
 310   if (!flag_finite_math_only)
 311     operands[1] = force_reg (V2SFmode, operands[1]);
 312   ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
 313 })
 314
 315 (define_insn "*mmx_<code>v2sf3_finite"
 316   [(set (match_operand:V2SF 0 "register_operand" "=y")
 317         (smaxmin:V2SF
 318           (match_operand:V2SF 1 "nonimmediate_operand" "%0")
 319           (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 320   "TARGET_3DNOW && flag_finite_math_only
 321    && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
 322   "pf<maxmin_float>\t{%2, %0|%0, %2}"
 323   [(set_attr "type" "mmxadd")
 324    (set_attr "prefix_extra" "1")
 325    (set_attr "mode" "V2SF")])
 326
 327 (define_insn "*mmx_<code>v2sf3"
 328   [(set (match_operand:V2SF 0 "register_operand" "=y")
 329         (smaxmin:V2SF
 330           (match_operand:V2SF 1 "register_operand" "0")
 331           (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 332   "TARGET_3DNOW"
 333   "pf<maxmin_float>\t{%2, %0|%0, %2}"
 334   [(set_attr "type" "mmxadd")
 335    (set_attr "prefix_extra" "1")
 336    (set_attr "mode" "V2SF")])
 337
 338 (define_insn "mmx_rcpv2sf2"
 339   [(set (match_operand:V2SF 0 "register_operand" "=y")
 340         (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
 341                      UNSPEC_PFRCP))]
 342   "TARGET_3DNOW"
 343   "pfrcp\t{%1, %0|%0, %1}"
 344   [(set_attr "type" "mmx")
 345    (set_attr "prefix_extra" "1")
 346    (set_attr "mode" "V2SF")])
 347
 348 (define_insn "mmx_rcpit1v2sf3"
 349   [(set (match_operand:V2SF 0 "register_operand" "=y")
 350         (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
 351                       (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
 352                      UNSPEC_PFRCPIT1))]
 353   "TARGET_3DNOW"
 354   "pfrcpit1\t{%2, %0|%0, %2}"
 355   [(set_attr "type" "mmx")
 356    (set_attr "prefix_extra" "1")
 357    (set_attr "mode" "V2SF")])
 358
 359 (define_insn "mmx_rcpit2v2sf3"
 360   [(set (match_operand:V2SF 0 "register_operand" "=y")
 361         (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
 362                       (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
 363                      UNSPEC_PFRCPIT2))]
 364   "TARGET_3DNOW"
 365   "pfrcpit2\t{%2, %0|%0, %2}"
 366   [(set_attr "type" "mmx")
 367    (set_attr "prefix_extra" "1")
 368    (set_attr "mode" "V2SF")])
 369
 370 (define_insn "mmx_rsqrtv2sf2"
 371   [(set (match_operand:V2SF 0 "register_operand" "=y")
 372         (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
 373                      UNSPEC_PFRSQRT))]
 374   "TARGET_3DNOW"
 375   "pfrsqrt\t{%1, %0|%0, %1}"
 376   [(set_attr "type" "mmx")
 377    (set_attr "prefix_extra" "1")
 378    (set_attr "mode" "V2SF")])
 379
 380 (define_insn "mmx_rsqit1v2sf3"
 381   [(set (match_operand:V2SF 0 "register_operand" "=y")
 382         (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
 383                       (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
 384                      UNSPEC_PFRSQIT1))]
 385   "TARGET_3DNOW"
 386   "pfrsqit1\t{%2, %0|%0, %2}"
 387   [(set_attr "type" "mmx")
 388    (set_attr "prefix_extra" "1")
 389    (set_attr "mode" "V2SF")])
 390
 391 (define_insn "mmx_haddv2sf3"
 392   [(set (match_operand:V2SF 0 "register_operand" "=y")
 393         (vec_concat:V2SF
 394           (plus:SF
 395             (vec_select:SF
 396               (match_operand:V2SF 1 "register_operand" "0")
 397               (parallel [(const_int  0)]))
 398             (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
 399           (plus:SF
 400             (vec_select:SF
 401               (match_operand:V2SF 2 "nonimmediate_operand" "ym")
 402               (parallel [(const_int  0)]))
 403             (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
 404   "TARGET_3DNOW"
 405   "pfacc\t{%2, %0|%0, %2}"
 406   [(set_attr "type" "mmxadd")
 407    (set_attr "prefix_extra" "1")
 408    (set_attr "mode" "V2SF")])
 409
 410 (define_insn "mmx_hsubv2sf3"
 411   [(set (match_operand:V2SF 0 "register_operand" "=y")
 412         (vec_concat:V2SF
 413           (minus:SF
 414             (vec_select:SF
 415               (match_operand:V2SF 1 "register_operand" "0")
 416               (parallel [(const_int  0)]))
 417             (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
 418           (minus:SF
 419             (vec_select:SF
 420               (match_operand:V2SF 2 "nonimmediate_operand" "ym")
 421               (parallel [(const_int  0)]))
 422             (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
 423   "TARGET_3DNOW_A"
 424   "pfnacc\t{%2, %0|%0, %2}"
 425   [(set_attr "type" "mmxadd")
 426    (set_attr "prefix_extra" "1")
 427    (set_attr "mode" "V2SF")])
 428
 429 (define_insn "mmx_addsubv2sf3"
 430   [(set (match_operand:V2SF 0 "register_operand" "=y")
 431         (vec_merge:V2SF
 432           (plus:V2SF
 433             (match_operand:V2SF 1 "register_operand" "0")
 434             (match_operand:V2SF 2 "nonimmediate_operand" "ym"))
 435           (minus:V2SF (match_dup 1) (match_dup 2))
 436           (const_int 1)))]
 437   "TARGET_3DNOW_A"
 438   "pfpnacc\t{%2, %0|%0, %2}"
 439   [(set_attr "type" "mmxadd")
 440    (set_attr "prefix_extra" "1")
 441    (set_attr "mode" "V2SF")])
 442
 443 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 444 ;;
 445 ;; Parallel single-precision floating point comparisons
 446 ;;
 447 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 448
 449 (define_expand "mmx_eqv2sf3"
 450   [(set (match_operand:V2SI 0 "register_operand")
 451         (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand")
 452                  (match_operand:V2SF 2 "nonimmediate_operand")))]
 453   "TARGET_3DNOW"
 454   "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
 455
 456 (define_insn "*mmx_eqv2sf3"
 457   [(set (match_operand:V2SI 0 "register_operand" "=y")
 458         (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
 459                  (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 460   "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
 461   "pfcmpeq\t{%2, %0|%0, %2}"
 462   [(set_attr "type" "mmxcmp")
 463    (set_attr "prefix_extra" "1")
 464    (set_attr "mode" "V2SF")])
 465
 466 (define_insn "mmx_gtv2sf3"
 467   [(set (match_operand:V2SI 0 "register_operand" "=y")
 468         (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
 469                  (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 470   "TARGET_3DNOW"
 471   "pfcmpgt\t{%2, %0|%0, %2}"
 472   [(set_attr "type" "mmxcmp")
 473    (set_attr "prefix_extra" "1")
 474    (set_attr "mode" "V2SF")])
 475
 476 (define_insn "mmx_gev2sf3"
 477   [(set (match_operand:V2SI 0 "register_operand" "=y")
 478         (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
 479                  (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
 480   "TARGET_3DNOW"
 481   "pfcmpge\t{%2, %0|%0, %2}"
 482   [(set_attr "type" "mmxcmp")
 483    (set_attr "prefix_extra" "1")
 484    (set_attr "mode" "V2SF")])
 485
 486 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 487 ;;
 488 ;; Parallel single-precision floating point conversion operations
 489 ;;
 490 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 491
 492 (define_insn "mmx_pf2id"
 493   [(set (match_operand:V2SI 0 "register_operand" "=y")
 494         (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
 495   "TARGET_3DNOW"
 496   "pf2id\t{%1, %0|%0, %1}"
 497   [(set_attr "type" "mmxcvt")
 498    (set_attr "prefix_extra" "1")
 499    (set_attr "mode" "V2SF")])
 500
 501 (define_insn "mmx_pf2iw"
 502   [(set (match_operand:V2SI 0 "register_operand" "=y")
 503         (sign_extend:V2SI
 504           (ss_truncate:V2HI
 505             (fix:V2SI
 506               (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
 507   "TARGET_3DNOW_A"
 508   "pf2iw\t{%1, %0|%0, %1}"
 509   [(set_attr "type" "mmxcvt")
 510    (set_attr "prefix_extra" "1")
 511    (set_attr "mode" "V2SF")])
 512
 513 (define_insn "mmx_pi2fw"
 514   [(set (match_operand:V2SF 0 "register_operand" "=y")
 515         (float:V2SF
 516           (sign_extend:V2SI
 517             (truncate:V2HI
 518               (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
 519   "TARGET_3DNOW_A"
 520   "pi2fw\t{%1, %0|%0, %1}"
 521   [(set_attr "type" "mmxcvt")
 522    (set_attr "prefix_extra" "1")
 523    (set_attr "mode" "V2SF")])
 524
 525 (define_insn "mmx_floatv2si2"
 526   [(set (match_operand:V2SF 0 "register_operand" "=y")
 527         (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
 528   "TARGET_3DNOW"
 529   "pi2fd\t{%1, %0|%0, %1}"
 530   [(set_attr "type" "mmxcvt")
 531    (set_attr "prefix_extra" "1")
 532    (set_attr "mode" "V2SF")])
 533
 534 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 535 ;;
 536 ;; Parallel single-precision floating point element swizzling
 537 ;;
 538 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 539
 540 (define_insn "mmx_pswapdv2sf2"
 541   [(set (match_operand:V2SF 0 "register_operand" "=y")
 542         (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
 543                          (parallel [(const_int 1) (const_int 0)])))]
 544   "TARGET_3DNOW_A"
 545   "pswapd\t{%1, %0|%0, %1}"
 546   [(set_attr "type" "mmxcvt")
 547    (set_attr "prefix_extra" "1")
 548    (set_attr "mode" "V2SF")])
 549
 550 (define_insn "*vec_dupv2sf"
 551   [(set (match_operand:V2SF 0 "register_operand" "=y")
 552         (vec_duplicate:V2SF
 553           (match_operand:SF 1 "register_operand" "0")))]
 554   "TARGET_MMX"
 555   "punpckldq\t%0, %0"
 556   [(set_attr "type" "mmxcvt")
 557    (set_attr "mode" "DI")])
 558
 559 (define_insn "*mmx_concatv2sf"
 560   [(set (match_operand:V2SF 0 "register_operand"     "=y,y")
 561         (vec_concat:V2SF
 562           (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
 563           (match_operand:SF 2 "vector_move_operand"  "ym,C")))]
 564   "TARGET_MMX && !TARGET_SSE"
 565   "@
 566    punpckldq\t{%2, %0|%0, %2}
 567    movd\t{%1, %0|%0, %1}"
 568   [(set_attr "type" "mmxcvt,mmxmov")
 569    (set_attr "mode" "DI")])
 570
 571 (define_expand "vec_setv2sf"
 572   [(match_operand:V2SF 0 "register_operand")
 573    (match_operand:SF 1 "register_operand")
 574    (match_operand 2 "const_int_operand")]
 575   "TARGET_MMX"
 576 {
 577   ix86_expand_vector_set (false, operands[0], operands[1],
 578                           INTVAL (operands[2]));
 579   DONE;
 580 })
 581
 582 ;; Avoid combining registers from different units in a single alternative,
 583 ;; see comment above inline_secondary_memory_needed function in i386.c
 584 (define_insn_and_split "*vec_extractv2sf_0"
 585   [(set (match_operand:SF 0 "nonimmediate_operand"     "=x, m,y ,m,f,r")
 586         (vec_select:SF
 587           (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
 588           (parallel [(const_int 0)])))]
 589   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 590   "#"
 591   "&& reload_completed"
 592   [(set (match_dup 0) (match_dup 1))]
 593   "operands[1] = gen_lowpart (SFmode, operands[1]);")
 594
 595 ;; Avoid combining registers from different units in a single alternative,
 596 ;; see comment above inline_secondary_memory_needed function in i386.c
 597 (define_insn "*vec_extractv2sf_1"
 598   [(set (match_operand:SF 0 "nonimmediate_operand"     "=y,x,x,y,x,f,r")
 599         (vec_select:SF
 600           (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,x,o,o,o,o")
 601           (parallel [(const_int 1)])))]
 602   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 603   "@
 604    punpckhdq\t%0, %0
 605    %vmovshdup\t{%1, %0|%0, %1}
 606    shufps\t{$0xe5, %1, %0|%0, %1, 0xe5}
 607    #
 608    #
 609    #
 610    #"
 611   [(set_attr "isa" "*,sse3,noavx,*,*,*,*")
 612    (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov")
 613    (set_attr "length_immediate" "*,*,1,*,*,*,*")
 614    (set_attr "prefix_rep" "*,1,*,*,*,*,*")
 615    (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig")
 616    (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")])
 617
 618 (define_split
 619   [(set (match_operand:SF 0 "register_operand")
 620         (vec_select:SF
 621           (match_operand:V2SF 1 "memory_operand")
 622           (parallel [(const_int 1)])))]
 623   "TARGET_MMX && reload_completed"
 624   [(set (match_dup 0) (match_dup 1))]
 625   "operands[1] = adjust_address (operands[1], SFmode, 4);")
 626
 627 (define_expand "vec_extractv2sf"
 628   [(match_operand:SF 0 "register_operand")
 629    (match_operand:V2SF 1 "register_operand")
 630    (match_operand 2 "const_int_operand")]
 631   "TARGET_MMX"
 632 {
 633   ix86_expand_vector_extract (false, operands[0], operands[1],
 634                               INTVAL (operands[2]));
 635   DONE;
 636 })
 637
 638 (define_expand "vec_initv2sf"
 639   [(match_operand:V2SF 0 "register_operand")
 640    (match_operand 1)]
 641   "TARGET_SSE"
 642 {
 643   ix86_expand_vector_init (false, operands[0], operands[1]);
 644   DONE;
 645 })
 646
 647 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 648 ;;
 649 ;; Parallel integral arithmetic
 650 ;;
 651 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 652
 653 (define_expand "mmx_<plusminus_insn><mode>3"
 654   [(set (match_operand:MMXMODEI8 0 "register_operand")
 655         (plusminus:MMXMODEI8
 656           (match_operand:MMXMODEI8 1 "nonimmediate_operand")
 657           (match_operand:MMXMODEI8 2 "nonimmediate_operand")))]
 658   "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
 659   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 660
 661 (define_insn "*mmx_<plusminus_insn><mode>3"
 662   [(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
 663         (plusminus:MMXMODEI8
 664           (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0")
 665           (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
 666   "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))
 667    && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
 668   "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
 669   [(set_attr "type" "mmxadd")
 670    (set_attr "mode" "DI")])
 671
 672 (define_expand "mmx_<plusminus_insn><mode>3"
 673   [(set (match_operand:MMXMODE12 0 "register_operand")
 674         (sat_plusminus:MMXMODE12
 675           (match_operand:MMXMODE12 1 "nonimmediate_operand")
 676           (match_operand:MMXMODE12 2 "nonimmediate_operand")))]
 677   "TARGET_MMX"
 678   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 679
 680 (define_insn "*mmx_<plusminus_insn><mode>3"
 681   [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
 682         (sat_plusminus:MMXMODE12
 683           (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0")
 684           (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
 685   "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
 686   "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
 687   [(set_attr "type" "mmxadd")
 688    (set_attr "mode" "DI")])
 689
 690 (define_expand "mmx_mulv4hi3"
 691   [(set (match_operand:V4HI 0 "register_operand")
 692         (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand")
 693                    (match_operand:V4HI 2 "nonimmediate_operand")))]
 694   "TARGET_MMX"
 695   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 696
 697 (define_insn "*mmx_mulv4hi3"
 698   [(set (match_operand:V4HI 0 "register_operand" "=y")
 699         (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
 700                    (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
 701   "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
 702   "pmullw\t{%2, %0|%0, %2}"
 703   [(set_attr "type" "mmxmul")
 704    (set_attr "mode" "DI")])
 705
 706 (define_expand "mmx_smulv4hi3_highpart"
 707   [(set (match_operand:V4HI 0 "register_operand")
 708         (truncate:V4HI
 709           (lshiftrt:V4SI
 710             (mult:V4SI
 711               (sign_extend:V4SI
 712                 (match_operand:V4HI 1 "nonimmediate_operand"))
 713               (sign_extend:V4SI
 714                 (match_operand:V4HI 2 "nonimmediate_operand")))
 715             (const_int 16))))]
 716   "TARGET_MMX"
 717   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 718
 719 (define_insn "*mmx_smulv4hi3_highpart"
 720   [(set (match_operand:V4HI 0 "register_operand" "=y")
 721         (truncate:V4HI
 722           (lshiftrt:V4SI
 723             (mult:V4SI
 724               (sign_extend:V4SI
 725                 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
 726               (sign_extend:V4SI
 727                 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
 728             (const_int 16))))]
 729   "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
 730   "pmulhw\t{%2, %0|%0, %2}"
 731   [(set_attr "type" "mmxmul")
 732    (set_attr "mode" "DI")])
 733
 734 (define_expand "mmx_umulv4hi3_highpart"
 735   [(set (match_operand:V4HI 0 "register_operand")
 736         (truncate:V4HI
 737           (lshiftrt:V4SI
 738             (mult:V4SI
 739               (zero_extend:V4SI
 740                 (match_operand:V4HI 1 "nonimmediate_operand"))
 741               (zero_extend:V4SI
 742                 (match_operand:V4HI 2 "nonimmediate_operand")))
 743             (const_int 16))))]
 744   "TARGET_SSE || TARGET_3DNOW_A"
 745   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 746
 747 (define_insn "*mmx_umulv4hi3_highpart"
 748   [(set (match_operand:V4HI 0 "register_operand" "=y")
 749         (truncate:V4HI
 750           (lshiftrt:V4SI
 751             (mult:V4SI
 752               (zero_extend:V4SI
 753                 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
 754               (zero_extend:V4SI
 755                 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
 756           (const_int 16))))]
 757   "(TARGET_SSE || TARGET_3DNOW_A)
 758    && ix86_binary_operator_ok (MULT, V4HImode, operands)"
 759   "pmulhuw\t{%2, %0|%0, %2}"
 760   [(set_attr "type" "mmxmul")
 761    (set_attr "mode" "DI")])
 762
 763 (define_expand "mmx_pmaddwd"
 764   [(set (match_operand:V2SI 0 "register_operand")
 765         (plus:V2SI
 766           (mult:V2SI
 767             (sign_extend:V2SI
 768               (vec_select:V2HI
 769                 (match_operand:V4HI 1 "nonimmediate_operand")
 770                 (parallel [(const_int 0) (const_int 2)])))
 771             (sign_extend:V2SI
 772               (vec_select:V2HI
 773                 (match_operand:V4HI 2 "nonimmediate_operand")
 774                 (parallel [(const_int 0) (const_int 2)]))))
 775           (mult:V2SI
 776             (sign_extend:V2SI
 777               (vec_select:V2HI (match_dup 1)
 778                 (parallel [(const_int 1) (const_int 3)])))
 779             (sign_extend:V2SI
 780               (vec_select:V2HI (match_dup 2)
 781                 (parallel [(const_int 1) (const_int 3)]))))))]
 782   "TARGET_MMX"
 783   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 784
 785 (define_insn "*mmx_pmaddwd"
 786   [(set (match_operand:V2SI 0 "register_operand" "=y")
 787         (plus:V2SI
 788           (mult:V2SI
 789             (sign_extend:V2SI
 790               (vec_select:V2HI
 791                 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
 792                 (parallel [(const_int 0) (const_int 2)])))
 793             (sign_extend:V2SI
 794               (vec_select:V2HI
 795                 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
 796                 (parallel [(const_int 0) (const_int 2)]))))
 797           (mult:V2SI
 798             (sign_extend:V2SI
 799               (vec_select:V2HI (match_dup 1)
 800                 (parallel [(const_int 1) (const_int 3)])))
 801             (sign_extend:V2SI
 802               (vec_select:V2HI (match_dup 2)
 803                 (parallel [(const_int 1) (const_int 3)]))))))]
 804   "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
 805   "pmaddwd\t{%2, %0|%0, %2}"
 806   [(set_attr "type" "mmxmul")
 807    (set_attr "mode" "DI")])
 808
 809 (define_expand "mmx_pmulhrwv4hi3"
 810   [(set (match_operand:V4HI 0 "register_operand")
 811         (truncate:V4HI
 812           (lshiftrt:V4SI
 813             (plus:V4SI
 814               (mult:V4SI
 815                 (sign_extend:V4SI
 816                   (match_operand:V4HI 1 "nonimmediate_operand"))
 817                 (sign_extend:V4SI
 818                   (match_operand:V4HI 2 "nonimmediate_operand")))
 819               (const_vector:V4SI [(const_int 32768) (const_int 32768)
 820                                   (const_int 32768) (const_int 32768)]))
 821             (const_int 16))))]
 822   "TARGET_3DNOW"
 823   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 824
 825 (define_insn "*mmx_pmulhrwv4hi3"
 826   [(set (match_operand:V4HI 0 "register_operand" "=y")
 827         (truncate:V4HI
 828           (lshiftrt:V4SI
 829             (plus:V4SI
 830               (mult:V4SI
 831                 (sign_extend:V4SI
 832                   (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
 833                 (sign_extend:V4SI
 834                   (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
 835               (const_vector:V4SI [(const_int 32768) (const_int 32768)
 836                                   (const_int 32768) (const_int 32768)]))
 837             (const_int 16))))]
 838   "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
 839   "pmulhrw\t{%2, %0|%0, %2}"
 840   [(set_attr "type" "mmxmul")
 841    (set_attr "prefix_extra" "1")
 842    (set_attr "mode" "DI")])
 843
 844 (define_expand "sse2_umulv1siv1di3"
 845   [(set (match_operand:V1DI 0 "register_operand")
 846         (mult:V1DI
 847           (zero_extend:V1DI
 848             (vec_select:V1SI
 849               (match_operand:V2SI 1 "nonimmediate_operand")
 850               (parallel [(const_int 0)])))
 851           (zero_extend:V1DI
 852             (vec_select:V1SI
 853               (match_operand:V2SI 2 "nonimmediate_operand")
 854               (parallel [(const_int 0)])))))]
 855   "TARGET_SSE2"
 856   "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
 857
 858 (define_insn "*sse2_umulv1siv1di3"
 859   [(set (match_operand:V1DI 0 "register_operand" "=y")
 860         (mult:V1DI
 861           (zero_extend:V1DI
 862             (vec_select:V1SI
 863               (match_operand:V2SI 1 "nonimmediate_operand" "%0")
 864               (parallel [(const_int 0)])))
 865           (zero_extend:V1DI
 866             (vec_select:V1SI
 867               (match_operand:V2SI 2 "nonimmediate_operand" "ym")
 868               (parallel [(const_int 0)])))))]
 869   "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
 870   "pmuludq\t{%2, %0|%0, %2}"
 871   [(set_attr "type" "mmxmul")
 872    (set_attr "mode" "DI")])
 873
 874 (define_expand "mmx_<code>v4hi3"
 875   [(set (match_operand:V4HI 0 "register_operand")
 876         (smaxmin:V4HI
 877           (match_operand:V4HI 1 "nonimmediate_operand")
 878           (match_operand:V4HI 2 "nonimmediate_operand")))]
 879   "TARGET_SSE || TARGET_3DNOW_A"
 880   "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
 881
 882 (define_insn "*mmx_<code>v4hi3"
 883   [(set (match_operand:V4HI 0 "register_operand" "=y")
 884         (smaxmin:V4HI
 885           (match_operand:V4HI 1 "nonimmediate_operand" "%0")
 886           (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
 887   "(TARGET_SSE || TARGET_3DNOW_A)
 888    && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
 889   "p<maxmin_int>w\t{%2, %0|%0, %2}"
 890   [(set_attr "type" "mmxadd")
 891    (set_attr "mode" "DI")])
 892
 893 (define_expand "mmx_<code>v8qi3"
 894   [(set (match_operand:V8QI 0 "register_operand")
 895         (umaxmin:V8QI
 896           (match_operand:V8QI 1 "nonimmediate_operand")
 897           (match_operand:V8QI 2 "nonimmediate_operand")))]
 898   "TARGET_SSE || TARGET_3DNOW_A"
 899   "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
 900
 901 (define_insn "*mmx_<code>v8qi3"
 902   [(set (match_operand:V8QI 0 "register_operand" "=y")
 903         (umaxmin:V8QI
 904           (match_operand:V8QI 1 "nonimmediate_operand" "%0")
 905           (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
 906   "(TARGET_SSE || TARGET_3DNOW_A)
 907    && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
 908   "p<maxmin_int>b\t{%2, %0|%0, %2}"
 909   [(set_attr "type" "mmxadd")
 910    (set_attr "mode" "DI")])
 911
 912 (define_insn "mmx_ashr<mode>3"
 913   [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
 914         (ashiftrt:MMXMODE24
 915           (match_operand:MMXMODE24 1 "register_operand" "0")
 916           (match_operand:SI 2 "nonmemory_operand" "yN")))]
 917   "TARGET_MMX"
 918   "psra<mmxvecsize>\t{%2, %0|%0, %2}"
 919   [(set_attr "type" "mmxshft")
 920    (set (attr "length_immediate")
 921      (if_then_else (match_operand 2 "const_int_operand")
 922        (const_string "1")
 923        (const_string "0")))
 924    (set_attr "mode" "DI")])
 925
 926 (define_insn "mmx_<shift_insn><mode>3"
 927   [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
 928         (any_lshift:MMXMODE248
 929           (match_operand:MMXMODE248 1 "register_operand" "0")
 930           (match_operand:SI 2 "nonmemory_operand" "yN")))]
 931   "TARGET_MMX"
 932   "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
 933   [(set_attr "type" "mmxshft")
 934    (set (attr "length_immediate")
 935      (if_then_else (match_operand 2 "const_int_operand")
 936        (const_string "1")
 937        (const_string "0")))
 938    (set_attr "mode" "DI")])
 939
 940 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 941 ;;
 942 ;; Parallel integral comparisons
 943 ;;
 944 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 945
 946 (define_expand "mmx_eq<mode>3"
 947   [(set (match_operand:MMXMODEI 0 "register_operand")
 948         (eq:MMXMODEI
 949           (match_operand:MMXMODEI 1 "nonimmediate_operand")
 950           (match_operand:MMXMODEI 2 "nonimmediate_operand")))]
 951   "TARGET_MMX"
 952   "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
 953
 954 (define_insn "*mmx_eq<mode>3"
 955   [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
 956         (eq:MMXMODEI
 957           (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
 958           (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
 959   "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
 960   "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}"
 961   [(set_attr "type" "mmxcmp")
 962    (set_attr "mode" "DI")])
 963
 964 (define_insn "mmx_gt<mode>3"
 965   [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
 966         (gt:MMXMODEI
 967           (match_operand:MMXMODEI 1 "register_operand" "0")
 968           (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
 969   "TARGET_MMX"
 970   "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}"
 971   [(set_attr "type" "mmxcmp")
 972    (set_attr "mode" "DI")])
 973
 974 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 975 ;;
 976 ;; Parallel integral logical operations
 977 ;;
 978 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 979
 980 (define_insn "mmx_andnot<mode>3"
 981   [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
 982         (and:MMXMODEI
 983           (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
 984           (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
 985   "TARGET_MMX"
 986   "pandn\t{%2, %0|%0, %2}"
 987   [(set_attr "type" "mmxadd")
 988    (set_attr "mode" "DI")])
 989
 990 (define_expand "mmx_<code><mode>3"
 991   [(set (match_operand:MMXMODEI 0 "register_operand")
 992         (any_logic:MMXMODEI
 993           (match_operand:MMXMODEI 1 "nonimmediate_operand")
 994           (match_operand:MMXMODEI 2 "nonimmediate_operand")))]
 995   "TARGET_MMX"
 996   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
 997
 998 (define_insn "*mmx_<code><mode>3"
 999   [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
1000         (any_logic:MMXMODEI
1001           (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
1002           (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
1003   "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1004   "p<logic>\t{%2, %0|%0, %2}"
1005   [(set_attr "type" "mmxadd")
1006    (set_attr "mode" "DI")])
1007
1008 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1009 ;;
1010 ;; Parallel integral element swizzling
1011 ;;
1012 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1013
1014 (define_insn "mmx_packsswb"
1015   [(set (match_operand:V8QI 0 "register_operand" "=y")
1016         (vec_concat:V8QI
1017           (ss_truncate:V4QI
1018             (match_operand:V4HI 1 "register_operand" "0"))
1019           (ss_truncate:V4QI
1020             (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
1021   "TARGET_MMX"
1022   "packsswb\t{%2, %0|%0, %2}"
1023   [(set_attr "type" "mmxshft")
1024    (set_attr "mode" "DI")])
1025
1026 (define_insn "mmx_packssdw"
1027   [(set (match_operand:V4HI 0 "register_operand" "=y")
1028         (vec_concat:V4HI
1029           (ss_truncate:V2HI
1030             (match_operand:V2SI 1 "register_operand" "0"))
1031           (ss_truncate:V2HI
1032             (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))]
1033   "TARGET_MMX"
1034   "packssdw\t{%2, %0|%0, %2}"
1035   [(set_attr "type" "mmxshft")
1036    (set_attr "mode" "DI")])
1037
1038 (define_insn "mmx_packuswb"
1039   [(set (match_operand:V8QI 0 "register_operand" "=y")
1040         (vec_concat:V8QI
1041           (us_truncate:V4QI
1042             (match_operand:V4HI 1 "register_operand" "0"))
1043           (us_truncate:V4QI
1044             (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
1045   "TARGET_MMX"
1046   "packuswb\t{%2, %0|%0, %2}"
1047   [(set_attr "type" "mmxshft")
1048    (set_attr "mode" "DI")])
1049
1050 (define_insn "mmx_punpckhbw"
1051   [(set (match_operand:V8QI 0 "register_operand" "=y")
1052         (vec_select:V8QI
1053           (vec_concat:V16QI
1054             (match_operand:V8QI 1 "register_operand" "0")
1055             (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1056           (parallel [(const_int 4) (const_int 12)
1057                      (const_int 5) (const_int 13)
1058                      (const_int 6) (const_int 14)
1059                      (const_int 7) (const_int 15)])))]
1060   "TARGET_MMX"
1061   "punpckhbw\t{%2, %0|%0, %2}"
1062   [(set_attr "type" "mmxcvt")
1063    (set_attr "mode" "DI")])
1064
1065 (define_insn "mmx_punpcklbw"
1066   [(set (match_operand:V8QI 0 "register_operand" "=y")
1067         (vec_select:V8QI
1068           (vec_concat:V16QI
1069             (match_operand:V8QI 1 "register_operand" "0")
1070             (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1071           (parallel [(const_int 0) (const_int 8)
1072                      (const_int 1) (const_int 9)
1073                      (const_int 2) (const_int 10)
1074                      (const_int 3) (const_int 11)])))]
1075   "TARGET_MMX"
1076   "punpcklbw\t{%2, %0|%0, %k2}"
1077   [(set_attr "type" "mmxcvt")
1078    (set_attr "mode" "DI")])
1079
1080 (define_insn "mmx_punpckhwd"
1081   [(set (match_operand:V4HI 0 "register_operand" "=y")
1082         (vec_select:V4HI
1083           (vec_concat:V8HI
1084             (match_operand:V4HI 1 "register_operand" "0")
1085             (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1086           (parallel [(const_int 2) (const_int 6)
1087                      (const_int 3) (const_int 7)])))]
1088   "TARGET_MMX"
1089   "punpckhwd\t{%2, %0|%0, %2}"
1090   [(set_attr "type" "mmxcvt")
1091    (set_attr "mode" "DI")])
1092
1093 (define_insn "mmx_punpcklwd"
1094   [(set (match_operand:V4HI 0 "register_operand" "=y")
1095         (vec_select:V4HI
1096           (vec_concat:V8HI
1097             (match_operand:V4HI 1 "register_operand" "0")
1098             (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1099           (parallel [(const_int 0) (const_int 4)
1100                      (const_int 1) (const_int 5)])))]
1101   "TARGET_MMX"
1102   "punpcklwd\t{%2, %0|%0, %k2}"
1103   [(set_attr "type" "mmxcvt")
1104    (set_attr "mode" "DI")])
1105
1106 (define_insn "mmx_punpckhdq"
1107   [(set (match_operand:V2SI 0 "register_operand" "=y")
1108         (vec_select:V2SI
1109           (vec_concat:V4SI
1110             (match_operand:V2SI 1 "register_operand" "0")
1111             (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1112           (parallel [(const_int 1)
1113                      (const_int 3)])))]
1114   "TARGET_MMX"
1115   "punpckhdq\t{%2, %0|%0, %2}"
1116   [(set_attr "type" "mmxcvt")
1117    (set_attr "mode" "DI")])
1118
1119 (define_insn "mmx_punpckldq"
1120   [(set (match_operand:V2SI 0 "register_operand" "=y")
1121         (vec_select:V2SI
1122           (vec_concat:V4SI
1123             (match_operand:V2SI 1 "register_operand" "0")
1124             (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1125           (parallel [(const_int 0)
1126                      (const_int 2)])))]
1127   "TARGET_MMX"
1128   "punpckldq\t{%2, %0|%0, %k2}"
1129   [(set_attr "type" "mmxcvt")
1130    (set_attr "mode" "DI")])
1131
1132 (define_expand "mmx_pinsrw"
1133   [(set (match_operand:V4HI 0 "register_operand")
1134         (vec_merge:V4HI
1135           (vec_duplicate:V4HI
1136             (match_operand:SI 2 "nonimmediate_operand"))
1137           (match_operand:V4HI 1 "register_operand")
1138           (match_operand:SI 3 "const_0_to_3_operand")))]
1139   "TARGET_SSE || TARGET_3DNOW_A"
1140 {
1141   operands[2] = gen_lowpart (HImode, operands[2]);
1142   operands[3] = GEN_INT (1 << INTVAL (operands[3]));
1143 })
1144
1145 (define_insn "*mmx_pinsrw"
1146   [(set (match_operand:V4HI 0 "register_operand" "=y")
1147         (vec_merge:V4HI
1148           (vec_duplicate:V4HI
1149             (match_operand:HI 2 "nonimmediate_operand" "rm"))
1150           (match_operand:V4HI 1 "register_operand" "0")
1151           (match_operand:SI 3 "const_int_operand")))]
1152   "(TARGET_SSE || TARGET_3DNOW_A)
1153    && ((unsigned) exact_log2 (INTVAL (operands[3]))
1154        < GET_MODE_NUNITS (V4HImode))"
1155 {
1156   operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
1157   if (MEM_P (operands[2]))
1158     return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
1159   else
1160     return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
1161 }
1162   [(set_attr "type" "mmxcvt")
1163    (set_attr "length_immediate" "1")
1164    (set_attr "mode" "DI")])
1165
1166 (define_insn "mmx_pextrw"
1167   [(set (match_operand:SI 0 "register_operand" "=r")
1168         (zero_extend:SI
1169           (vec_select:HI
1170             (match_operand:V4HI 1 "register_operand" "y")
1171             (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
1172   "TARGET_SSE || TARGET_3DNOW_A"
1173   "pextrw\t{%2, %1, %0|%0, %1, %2}"
1174   [(set_attr "type" "mmxcvt")
1175    (set_attr "length_immediate" "1")
1176    (set_attr "mode" "DI")])
1177
1178 (define_expand "mmx_pshufw"
1179   [(match_operand:V4HI 0 "register_operand")
1180    (match_operand:V4HI 1 "nonimmediate_operand")
1181    (match_operand:SI 2 "const_int_operand")]
1182   "TARGET_SSE || TARGET_3DNOW_A"
1183 {
1184   int mask = INTVAL (operands[2]);
1185   emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1],
1186                                GEN_INT ((mask >> 0) & 3),
1187                                GEN_INT ((mask >> 2) & 3),
1188                                GEN_INT ((mask >> 4) & 3),
1189                                GEN_INT ((mask >> 6) & 3)));
1190   DONE;
1191 })
1192
1193 (define_insn "mmx_pshufw_1"
1194   [(set (match_operand:V4HI 0 "register_operand" "=y")
1195         (vec_select:V4HI
1196           (match_operand:V4HI 1 "nonimmediate_operand" "ym")
1197           (parallel [(match_operand 2 "const_0_to_3_operand")
1198                      (match_operand 3 "const_0_to_3_operand")
1199                      (match_operand 4 "const_0_to_3_operand")
1200                      (match_operand 5 "const_0_to_3_operand")])))]
1201   "TARGET_SSE || TARGET_3DNOW_A"
1202 {
1203   int mask = 0;
1204   mask |= INTVAL (operands[2]) << 0;
1205   mask |= INTVAL (operands[3]) << 2;
1206   mask |= INTVAL (operands[4]) << 4;
1207   mask |= INTVAL (operands[5]) << 6;
1208   operands[2] = GEN_INT (mask);
1209
1210   return "pshufw\t{%2, %1, %0|%0, %1, %2}";
1211 }
1212   [(set_attr "type" "mmxcvt")
1213    (set_attr "length_immediate" "1")
1214    (set_attr "mode" "DI")])
1215
1216 (define_insn "mmx_pswapdv2si2"
1217   [(set (match_operand:V2SI 0 "register_operand" "=y")
1218         (vec_select:V2SI
1219           (match_operand:V2SI 1 "nonimmediate_operand" "ym")
1220           (parallel [(const_int 1) (const_int 0)])))]
1221   "TARGET_3DNOW_A"
1222   "pswapd\t{%1, %0|%0, %1}"
1223   [(set_attr "type" "mmxcvt")
1224    (set_attr "prefix_extra" "1")
1225    (set_attr "mode" "DI")])
1226
1227 (define_insn "*vec_dupv4hi"
1228   [(set (match_operand:V4HI 0 "register_operand" "=y")
1229         (vec_duplicate:V4HI
1230           (truncate:HI
1231             (match_operand:SI 1 "register_operand" "0"))))]
1232   "TARGET_SSE || TARGET_3DNOW_A"
1233   "pshufw\t{$0, %0, %0|%0, %0, 0}"
1234   [(set_attr "type" "mmxcvt")
1235    (set_attr "length_immediate" "1")
1236    (set_attr "mode" "DI")])
1237
1238 (define_insn "*vec_dupv2si"
1239   [(set (match_operand:V2SI 0 "register_operand" "=y")
1240         (vec_duplicate:V2SI
1241           (match_operand:SI 1 "register_operand" "0")))]
1242   "TARGET_MMX"
1243   "punpckldq\t%0, %0"
1244   [(set_attr "type" "mmxcvt")
1245    (set_attr "mode" "DI")])
1246
1247 (define_insn "*mmx_concatv2si"
1248   [(set (match_operand:V2SI 0 "register_operand"     "=y,y")
1249         (vec_concat:V2SI
1250           (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
1251           (match_operand:SI 2 "vector_move_operand"  "ym,C")))]
1252   "TARGET_MMX && !TARGET_SSE"
1253   "@
1254    punpckldq\t{%2, %0|%0, %2}
1255    movd\t{%1, %0|%0, %1}"
1256   [(set_attr "type" "mmxcvt,mmxmov")
1257    (set_attr "mode" "DI")])
1258
1259 (define_expand "vec_setv2si"
1260   [(match_operand:V2SI 0 "register_operand")
1261    (match_operand:SI 1 "register_operand")
1262    (match_operand 2 "const_int_operand")]
1263   "TARGET_MMX"
1264 {
1265   ix86_expand_vector_set (false, operands[0], operands[1],
1266                           INTVAL (operands[2]));
1267   DONE;
1268 })
1269
1270 ;; Avoid combining registers from different units in a single alternative,
1271 ;; see comment above inline_secondary_memory_needed function in i386.c
1272 (define_insn_and_split "*vec_extractv2si_0"
1273   [(set (match_operand:SI 0 "nonimmediate_operand"     "=x,m,y, m,r")
1274         (vec_select:SI
1275           (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m")
1276           (parallel [(const_int 0)])))]
1277   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1278   "#"
1279   "&& reload_completed"
1280   [(set (match_dup 0) (match_dup 1))]
1281   "operands[1] = gen_lowpart (SImode, operands[1]);")
1282
1283 ;; Avoid combining registers from different units in a single alternative,
1284 ;; see comment above inline_secondary_memory_needed function in i386.c
1285 (define_insn "*vec_extractv2si_1"
1286   [(set (match_operand:SI 0 "nonimmediate_operand"     "=y,x,x,y,x,r")
1287         (vec_select:SI
1288           (match_operand:V2SI 1 "nonimmediate_operand" " 0,x,x,o,o,o")
1289           (parallel [(const_int 1)])))]
1290   "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1291   "@
1292    punpckhdq\t%0, %0
1293    %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
1294    shufps\t{$0xe5, %1, %0|%0, %1, 0xe5}
1295    #
1296    #
1297    #"
1298   [(set_attr "isa" "*,sse2,noavx,*,*,*")
1299    (set_attr "type" "mmxcvt,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
1300    (set_attr "length_immediate" "*,1,1,*,*,*")
1301    (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig")
1302    (set_attr "mode" "DI,TI,V4SF,SI,SI,SI")])
1303
1304 (define_split
1305   [(set (match_operand:SI 0 "register_operand")
1306         (vec_select:SI
1307           (match_operand:V2SI 1 "memory_operand")
1308           (parallel [(const_int 1)])))]
1309   "TARGET_MMX && reload_completed"
1310   [(set (match_dup 0) (match_dup 1))]
1311   "operands[1] = adjust_address (operands[1], SImode, 4);")
1312
1313 (define_insn_and_split "*vec_extractv2si_zext_mem"
1314   [(set (match_operand:DI 0 "register_operand" "=y,x,r")
1315         (zero_extend:DI
1316           (vec_select:SI
1317             (match_operand:V2SI 1 "memory_operand" "o,o,o")
1318             (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
1319   "TARGET_64BIT && TARGET_MMX"
1320   "#"
1321   "&& reload_completed"
1322   [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
1323 {
1324   operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
1325 })
1326
1327 (define_expand "vec_extractv2si"
1328   [(match_operand:SI 0 "register_operand")
1329    (match_operand:V2SI 1 "register_operand")
1330    (match_operand 2 "const_int_operand")]
1331   "TARGET_MMX"
1332 {
1333   ix86_expand_vector_extract (false, operands[0], operands[1],
1334                               INTVAL (operands[2]));
1335   DONE;
1336 })
1337
1338 (define_expand "vec_initv2si"
1339   [(match_operand:V2SI 0 "register_operand")
1340    (match_operand 1)]
1341   "TARGET_SSE"
1342 {
1343   ix86_expand_vector_init (false, operands[0], operands[1]);
1344   DONE;
1345 })
1346
1347 (define_expand "vec_setv4hi"
1348   [(match_operand:V4HI 0 "register_operand")
1349    (match_operand:HI 1 "register_operand")
1350    (match_operand 2 "const_int_operand")]
1351   "TARGET_MMX"
1352 {
1353   ix86_expand_vector_set (false, operands[0], operands[1],
1354                           INTVAL (operands[2]));
1355   DONE;
1356 })
1357
1358 (define_expand "vec_extractv4hi"
1359   [(match_operand:HI 0 "register_operand")
1360    (match_operand:V4HI 1 "register_operand")
1361    (match_operand 2 "const_int_operand")]
1362   "TARGET_MMX"
1363 {
1364   ix86_expand_vector_extract (false, operands[0], operands[1],
1365                               INTVAL (operands[2]));
1366   DONE;
1367 })
1368
1369 (define_expand "vec_initv4hi"
1370   [(match_operand:V4HI 0 "register_operand")
1371    (match_operand 1)]
1372   "TARGET_SSE"
1373 {
1374   ix86_expand_vector_init (false, operands[0], operands[1]);
1375   DONE;
1376 })
1377
1378 (define_expand "vec_setv8qi"
1379   [(match_operand:V8QI 0 "register_operand")
1380    (match_operand:QI 1 "register_operand")
1381    (match_operand 2 "const_int_operand")]
1382   "TARGET_MMX"
1383 {
1384   ix86_expand_vector_set (false, operands[0], operands[1],
1385                           INTVAL (operands[2]));
1386   DONE;
1387 })
1388
1389 (define_expand "vec_extractv8qi"
1390   [(match_operand:QI 0 "register_operand")
1391    (match_operand:V8QI 1 "register_operand")
1392    (match_operand 2 "const_int_operand")]
1393   "TARGET_MMX"
1394 {
1395   ix86_expand_vector_extract (false, operands[0], operands[1],
1396                               INTVAL (operands[2]));
1397   DONE;
1398 })
1399
1400 (define_expand "vec_initv8qi"
1401   [(match_operand:V8QI 0 "register_operand")
1402    (match_operand 1)]
1403   "TARGET_SSE"
1404 {
1405   ix86_expand_vector_init (false, operands[0], operands[1]);
1406   DONE;
1407 })
1408
1409 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1410 ;;
1411 ;; Miscellaneous
1412 ;;
1413 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1414
1415 (define_expand "mmx_uavgv8qi3"
1416   [(set (match_operand:V8QI 0 "register_operand")
1417         (truncate:V8QI
1418           (lshiftrt:V8HI
1419             (plus:V8HI
1420               (plus:V8HI
1421                 (zero_extend:V8HI
1422                   (match_operand:V8QI 1 "nonimmediate_operand"))
1423                 (zero_extend:V8HI
1424                   (match_operand:V8QI 2 "nonimmediate_operand")))
1425               (const_vector:V8HI [(const_int 1) (const_int 1)
1426                                   (const_int 1) (const_int 1)
1427                                   (const_int 1) (const_int 1)
1428                                   (const_int 1) (const_int 1)]))
1429             (const_int 1))))]
1430   "TARGET_SSE || TARGET_3DNOW"
1431   "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
1432
1433 (define_insn "*mmx_uavgv8qi3"
1434   [(set (match_operand:V8QI 0 "register_operand" "=y")
1435         (truncate:V8QI
1436           (lshiftrt:V8HI
1437             (plus:V8HI
1438               (plus:V8HI
1439                 (zero_extend:V8HI
1440                   (match_operand:V8QI 1 "nonimmediate_operand" "%0"))
1441                 (zero_extend:V8HI
1442                   (match_operand:V8QI 2 "nonimmediate_operand" "ym")))
1443               (const_vector:V8HI [(const_int 1) (const_int 1)
1444                                   (const_int 1) (const_int 1)
1445                                   (const_int 1) (const_int 1)
1446                                   (const_int 1) (const_int 1)]))
1447             (const_int 1))))]
1448   "(TARGET_SSE || TARGET_3DNOW)
1449    && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
1450 {
1451   /* These two instructions have the same operation, but their encoding
1452      is different.  Prefer the one that is de facto standard.  */
1453   if (TARGET_SSE || TARGET_3DNOW_A)
1454     return "pavgb\t{%2, %0|%0, %2}";
1455   else
1456     return "pavgusb\t{%2, %0|%0, %2}";
1457 }
1458   [(set_attr "type" "mmxshft")
1459    (set (attr "prefix_extra")
1460      (if_then_else
1461        (not (ior (match_test "TARGET_SSE")
1462                  (match_test "TARGET_3DNOW_A")))
1463        (const_string "1")
1464        (const_string "*")))
1465    (set_attr "mode" "DI")])
1466
1467 (define_expand "mmx_uavgv4hi3"
1468   [(set (match_operand:V4HI 0 "register_operand")
1469         (truncate:V4HI
1470           (lshiftrt:V4SI
1471             (plus:V4SI
1472               (plus:V4SI
1473                 (zero_extend:V4SI
1474                   (match_operand:V4HI 1 "nonimmediate_operand"))
1475                 (zero_extend:V4SI
1476                   (match_operand:V4HI 2 "nonimmediate_operand")))
1477               (const_vector:V4SI [(const_int 1) (const_int 1)
1478                                   (const_int 1) (const_int 1)]))
1479             (const_int 1))))]
1480   "TARGET_SSE || TARGET_3DNOW_A"
1481   "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);")
1482
1483 (define_insn "*mmx_uavgv4hi3"
1484   [(set (match_operand:V4HI 0 "register_operand" "=y")
1485         (truncate:V4HI
1486           (lshiftrt:V4SI
1487             (plus:V4SI
1488               (plus:V4SI
1489                 (zero_extend:V4SI
1490                   (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
1491                 (zero_extend:V4SI
1492                   (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
1493               (const_vector:V4SI [(const_int 1) (const_int 1)
1494                                   (const_int 1) (const_int 1)]))
1495             (const_int 1))))]
1496   "(TARGET_SSE || TARGET_3DNOW_A)
1497    && ix86_binary_operator_ok (PLUS, V4HImode, operands)"
1498   "pavgw\t{%2, %0|%0, %2}"
1499   [(set_attr "type" "mmxshft")
1500    (set_attr "mode" "DI")])
1501
1502 (define_insn "mmx_psadbw"
1503   [(set (match_operand:V1DI 0 "register_operand" "=y")
1504         (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0")
1505                       (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
1506                      UNSPEC_PSADBW))]
1507   "TARGET_SSE || TARGET_3DNOW_A"
1508   "psadbw\t{%2, %0|%0, %2}"
1509   [(set_attr "type" "mmxshft")
1510    (set_attr "mode" "DI")])
1511
1512 (define_insn "mmx_pmovmskb"
1513   [(set (match_operand:SI 0 "register_operand" "=r")
1514         (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
1515                    UNSPEC_MOVMSK))]
1516   "TARGET_SSE || TARGET_3DNOW_A"
1517   "pmovmskb\t{%1, %0|%0, %1}"
1518   [(set_attr "type" "mmxcvt")
1519    (set_attr "mode" "DI")])
1520
1521 (define_expand "mmx_maskmovq"
1522   [(set (match_operand:V8QI 0 "memory_operand")
1523         (unspec:V8QI [(match_operand:V8QI 1 "register_operand")
1524                       (match_operand:V8QI 2 "register_operand")
1525                       (match_dup 0)]
1526                      UNSPEC_MASKMOV))]
1527   "TARGET_SSE || TARGET_3DNOW_A")
1528
1529 (define_insn "*mmx_maskmovq"
1530   [(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
1531         (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1532                       (match_operand:V8QI 2 "register_operand" "y")
1533                       (mem:V8QI (match_dup 0))]
1534                      UNSPEC_MASKMOV))]
1535   "TARGET_SSE || TARGET_3DNOW_A"
1536   ;; @@@ check ordering of operands in intel/nonintel syntax
1537   "maskmovq\t{%2, %1|%1, %2}"
1538   [(set_attr "type" "mmxcvt")
1539    (set_attr "znver1_decode" "vector")
1540    (set_attr "mode" "DI")])
1541
1542 (define_expand "mmx_emms"
1543   [(match_par_dup 0 [(const_int 0)])]
1544   "TARGET_MMX"
1545 {
1546   int regno;
1547
1548   operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (17));
1549
1550   XVECEXP (operands[0], 0, 0)
1551     = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
1552                                UNSPECV_EMMS);
1553
1554   for (regno = 0; regno < 8; regno++)
1555     {
1556       XVECEXP (operands[0], 0, regno + 1)
1557         = gen_rtx_CLOBBER (VOIDmode,
1558                            gen_rtx_REG (XFmode, FIRST_STACK_REG + regno));
1559
1560       XVECEXP (operands[0], 0, regno + 9)
1561         = gen_rtx_CLOBBER (VOIDmode,
1562                            gen_rtx_REG (DImode, FIRST_MMX_REG + regno));
1563     }
1564 })
1565
1566 (define_insn "*mmx_emms"
1567   [(match_parallel 0 "emms_operation"
1568     [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)])]
1569   "TARGET_MMX"
1570   "emms"
1571   [(set_attr "type" "mmx")
1572    (set_attr "modrm" "0")
1573    (set_attr "memory" "none")])
1574
1575 (define_expand "mmx_femms"
1576   [(match_par_dup 0 [(const_int 0)])]
1577   "TARGET_3DNOW"
1578 {
1579   int regno;
1580
1581   operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (17));
1582
1583   XVECEXP (operands[0], 0, 0)
1584     = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
1585                                UNSPECV_FEMMS);
1586
1587   for (regno = 0; regno < 8; regno++)
1588     {
1589       XVECEXP (operands[0], 0, regno + 1)
1590         = gen_rtx_CLOBBER (VOIDmode,
1591                            gen_rtx_REG (XFmode, FIRST_STACK_REG + regno));
1592
1593       XVECEXP (operands[0], 0, regno + 9)
1594         = gen_rtx_CLOBBER (VOIDmode,
1595                            gen_rtx_REG (DImode, FIRST_MMX_REG + regno));
1596     }
1597 })
1598
1599 (define_insn "*mmx_femms"
1600   [(match_parallel 0 "emms_operation"
1601     [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)])]
1602   "TARGET_3DNOW"
1603   "femms"
1604   [(set_attr "type" "mmx")
1605    (set_attr "modrm" "0")
1606    (set_attr "memory" "none")])