1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
25 #undef HANDLE_SYSV_PRAGMA
29 #undef WCHAR_TYPE_SIZE
41 /* M32R/X overrides. */
42 /* Print subsidiary information on the compiler version in use. */
43 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
45 /* Additional flags for the preprocessor. */
46 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
47 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
48 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
51 /* Assembler switches. */
52 #define ASM_CPU_SPEC \
53 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
55 /* Use m32rx specific crt0/crtinit/crtfini files. */
56 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
57 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
59 /* Define this macro as a C expression for the initializer of an array of
60 strings to tell the driver program which options are defaults for this
61 target and thus do not need to be handled specially when using
62 `MULTILIB_OPTIONS'. */
63 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
65 /* Number of additional registers the subtarget defines. */
66 #define SUBTARGET_NUM_REGISTERS 1
68 /* 1 for registers that cannot be allocated. */
69 #define SUBTARGET_FIXED_REGISTERS , 1
71 /* 1 for registers that are not available across function calls. */
72 #define SUBTARGET_CALL_USED_REGISTERS , 1
74 /* Order to allocate model specific registers. */
75 #define SUBTARGET_REG_ALLOC_ORDER , 19
77 /* Registers which are accumulators. */
78 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
80 /* All registers added. */
81 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
83 /* Additional accumulator registers. */
84 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
86 /* Define additional register names. */
87 #define SUBTARGET_REGISTER_NAMES , "a1"
88 /* end M32R/X overrides. */
90 /* Print subsidiary information on the compiler version in use. */
91 #ifndef TARGET_VERSION
92 #define TARGET_VERSION fprintf (stderr, " (m32r)")
95 /* Names to predefine in the preprocessor for this target machine. */
96 /* __M32R__ is defined by the existing compiler so we use that. */
97 #define TARGET_CPU_CPP_BUILTINS() \
100 builtin_define ("__M32R__"); \
101 builtin_define ("__m32r__"); \
102 builtin_assert ("cpu=m32r"); \
103 builtin_assert ("machine=m32r"); \
104 builtin_define (TARGET_BIG_ENDIAN \
105 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
109 /* This macro defines names of additional specifications to put in the specs
110 that can be used in various specifications like CC1_SPEC. Its definition
111 is an initializer with a subgrouping for each command option.
113 Each subgrouping contains a string constant, that defines the
114 specification name, and a string constant that used by the GCC driver
117 Do not define this macro if it does not need to do anything. */
119 #ifndef SUBTARGET_EXTRA_SPECS
120 #define SUBTARGET_EXTRA_SPECS
124 #define ASM_CPU_SPEC ""
128 #define CPP_CPU_SPEC ""
132 #define CC1_CPU_SPEC ""
135 #ifndef LINK_CPU_SPEC
136 #define LINK_CPU_SPEC ""
139 #ifndef STARTFILE_CPU_SPEC
140 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
143 #ifndef ENDFILE_CPU_SPEC
144 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
148 #if 0 /* Not supported yet. */
149 #define RELAX_SPEC "%{mrelax:-relax}"
151 #define RELAX_SPEC ""
155 #define EXTRA_SPECS \
156 { "asm_cpu", ASM_CPU_SPEC }, \
157 { "cpp_cpu", CPP_CPU_SPEC }, \
158 { "cc1_cpu", CC1_CPU_SPEC }, \
159 { "link_cpu", LINK_CPU_SPEC }, \
160 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
161 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
162 { "relax", RELAX_SPEC }, \
163 SUBTARGET_EXTRA_SPECS
165 #define CPP_SPEC "%(cpp_cpu)"
168 #define CC1_SPEC "%{G*} %(cc1_cpu)"
170 /* Options to pass on to the assembler. */
172 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
174 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
176 #undef STARTFILE_SPEC
177 #define STARTFILE_SPEC "%(startfile_cpu)"
180 #define ENDFILE_SPEC "%(endfile_cpu)"
184 /* Run-time compilation parameters selecting different hardware subsets. */
186 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
188 #ifndef TARGET_LITTLE_ENDIAN
189 #define TARGET_LITTLE_ENDIAN 0
191 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
193 /* This defaults us to m32r. */
194 #ifndef TARGET_CPU_DEFAULT
195 #define TARGET_CPU_DEFAULT 0
200 Code models are used to select between two choices of two separate
201 possibilities (address space size, call insn to use):
203 small: addresses use 24 bits, use bl to make calls
204 medium: addresses use 32 bits, use bl to make calls (*1)
205 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
207 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
208 using this one doesn't make much sense.
210 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
211 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
213 Internally these are recorded as TARGET_ADDR{24,32} and
216 The __model__ attribute can be used to select the code model to use when
217 accessing particular objects. */
219 enum m32r_model
{ M32R_MODEL_SMALL
, M32R_MODEL_MEDIUM
, M32R_MODEL_LARGE
};
221 extern enum m32r_model m32r_model
;
222 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
223 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
224 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
225 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
226 #define TARGET_ADDR32 (! TARGET_ADDR24)
227 #define TARGET_CALL26 (! TARGET_CALL32)
228 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
230 /* The default is the small model. */
231 #ifndef M32R_MODEL_DEFAULT
232 #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL
237 The SDA consists of sections .sdata, .sbss, and .scommon.
238 .scommon isn't a real section, symbols in it have their section index
239 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
241 Two switches control the SDA:
243 -G NNN - specifies the maximum size of variable to go in the SDA
245 -msdata=foo - specifies how such variables are handled
247 -msdata=none - small data area is disabled
249 -msdata=sdata - small data goes in the SDA, special code isn't
250 generated to use it, and special relocs aren't
253 -msdata=use - small data goes in the SDA, special code is generated
254 to use the SDA and special relocs are generated
256 The SDA is not multilib'd, it isn't necessary.
257 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
258 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
259 -msdata=use will successfully link with them (references in header files
260 will cause the compiler to emit code that refers to library objects in
261 .data). ??? There can be a problem if the user passes a -G value greater
262 than the default and a library object in a header file is that size.
263 The default is 8 so this should be rare - if it occurs the user
264 is required to rebuild the libraries or use a smaller value for -G. */
266 /* Maximum size of variables that go in .sdata/.sbss.
267 The -msdata=foo switch also controls how small variables are handled. */
268 #ifndef SDATA_DEFAULT_SIZE
269 #define SDATA_DEFAULT_SIZE 8
272 enum m32r_sdata
{ M32R_SDATA_NONE
, M32R_SDATA_SDATA
, M32R_SDATA_USE
};
274 extern enum m32r_sdata m32r_sdata
;
275 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
276 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
277 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
279 /* Default is to disable the SDA
280 [for upward compatibility with previous toolchains]. */
281 #ifndef M32R_SDATA_DEFAULT
282 #define M32R_SDATA_DEFAULT M32R_SDATA_NONE
285 /* Define this macro as a C expression for the initializer of an array of
286 strings to tell the driver program which options are defaults for this
287 target and thus do not need to be handled specially when using
288 `MULTILIB_OPTIONS'. */
289 #ifndef SUBTARGET_MULTILIB_DEFAULTS
290 #define SUBTARGET_MULTILIB_DEFAULTS
293 #ifndef MULTILIB_DEFAULTS
294 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
297 #ifndef SUBTARGET_OVERRIDE_OPTIONS
298 #define SUBTARGET_OVERRIDE_OPTIONS
301 /* Target machine storage layout. */
303 /* Define this if most significant bit is lowest numbered
304 in instructions that operate on numbered bit-fields. */
305 #define BITS_BIG_ENDIAN 1
307 /* Define this if most significant byte of a word is the lowest numbered. */
308 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
310 /* Define this if most significant word of a multiword number is the lowest
312 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
314 /* Width of a word, in units (bytes). */
315 #define UNITS_PER_WORD 4
317 /* Define this macro if it is advisable to hold scalars in registers
318 in a wider mode than that declared by the program. In such cases,
319 the value is constrained to be within the bounds of the declared
320 type, but kept valid in the wider mode. The signedness of the
321 extension may differ from that of the type. */
322 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
323 if (GET_MODE_CLASS (MODE) == MODE_INT \
324 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
329 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
330 #define PARM_BOUNDARY 32
332 /* Boundary (in *bits*) on which stack pointer should be aligned. */
333 #define STACK_BOUNDARY 32
335 /* ALIGN FRAMES on word boundaries */
336 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
338 /* Allocation boundary (in *bits*) for the code of a function. */
339 #define FUNCTION_BOUNDARY 32
341 /* Alignment of field after `int : 0' in a structure. */
342 #define EMPTY_FIELD_BOUNDARY 32
344 /* Every structure's size must be a multiple of this. */
345 #define STRUCTURE_SIZE_BOUNDARY 8
347 /* A bit-field declared as `int' forces `int' alignment for the struct. */
348 #define PCC_BITFIELD_TYPE_MATTERS 1
350 /* No data type wants to be aligned rounder than this. */
351 #define BIGGEST_ALIGNMENT 32
353 /* The best alignment to use in cases where we have a choice. */
354 #define FASTEST_ALIGNMENT 32
356 /* Make strings word-aligned so strcpy from constants will be faster. */
357 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
358 ((TREE_CODE (EXP) == STRING_CST \
359 && (ALIGN) < FASTEST_ALIGNMENT) \
360 ? FASTEST_ALIGNMENT : (ALIGN))
362 /* Make arrays of chars word-aligned for the same reasons. */
363 #define DATA_ALIGNMENT(TYPE, ALIGN) \
364 (TREE_CODE (TYPE) == ARRAY_TYPE \
365 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
366 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
368 /* Set this nonzero if move instructions will actually fail to work
369 when given unaligned data. */
370 #define STRICT_ALIGNMENT 1
372 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
373 #define LABEL_ALIGN(insn) 2
375 /* Layout of source language data types. */
377 #define SHORT_TYPE_SIZE 16
378 #define INT_TYPE_SIZE 32
379 #define LONG_TYPE_SIZE 32
380 #define LONG_LONG_TYPE_SIZE 64
381 #define FLOAT_TYPE_SIZE 32
382 #define DOUBLE_TYPE_SIZE 64
383 #define LONG_DOUBLE_TYPE_SIZE 64
385 /* Define this as 1 if `char' should by default be signed; else as 0. */
386 #define DEFAULT_SIGNED_CHAR 1
388 #define SIZE_TYPE "long unsigned int"
389 #define PTRDIFF_TYPE "long int"
390 #define WCHAR_TYPE "short unsigned int"
391 #define WCHAR_TYPE_SIZE 16
393 /* Standard register usage. */
395 /* Number of actual hardware registers.
396 The hardware registers are assigned numbers for the compiler
397 from 0 to just below FIRST_PSEUDO_REGISTER.
398 All registers that the compiler knows about must be given numbers,
399 even those that are not normally considered general registers. */
401 #define M32R_NUM_REGISTERS 19
403 #ifndef SUBTARGET_NUM_REGISTERS
404 #define SUBTARGET_NUM_REGISTERS 0
407 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
409 /* 1 for registers that have pervasive standard uses
410 and are not available for the register allocator.
412 0-3 - arguments/results
413 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
415 7 - call used, static chain pointer
417 12 - call saved [reserved for global pointer]
419 14 - subroutine link register
424 19 - accumulator 1 in the m32r/x
425 By default, the extension registers are not available. */
427 #ifndef SUBTARGET_FIXED_REGISTERS
428 #define SUBTARGET_FIXED_REGISTERS
431 #define FIXED_REGISTERS \
433 0, 0, 0, 0, 0, 0, 0, 0, \
434 0, 0, 0, 0, 0, 0, 0, 1, \
436 SUBTARGET_FIXED_REGISTERS \
439 /* 1 for registers not available across function calls.
440 These must include the FIXED_REGISTERS and also any
441 registers that can be used without being saved.
442 The latter must include the registers where values are returned
443 and the register where structure-value addresses are passed.
444 Aside from that, you can include as many other registers as you like. */
446 #ifndef SUBTARGET_CALL_USED_REGISTERS
447 #define SUBTARGET_CALL_USED_REGISTERS
450 #define CALL_USED_REGISTERS \
452 1, 1, 1, 1, 1, 1, 1, 1, \
453 0, 0, 0, 0, 0, 0, 1, 1, \
455 SUBTARGET_CALL_USED_REGISTERS \
458 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
460 /* Zero or more C statements that may conditionally modify two variables
461 `fixed_regs' and `call_used_regs' (both of type `char []') after they
462 have been initialized from the two preceding macros.
464 This is necessary in case the fixed or call-clobbered registers depend
467 You need not define this macro if it has no work to do. */
469 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
470 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
472 #define CONDITIONAL_REGISTER_USAGE \
477 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
478 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
484 /* If defined, an initializer for a vector of integers, containing the
485 numbers of hard registers in the order in which GCC should
486 prefer to use them (from most preferred to least). */
488 #ifndef SUBTARGET_REG_ALLOC_ORDER
489 #define SUBTARGET_REG_ALLOC_ORDER
492 #if 1 /* Better for int code. */
493 #define REG_ALLOC_ORDER \
495 4, 5, 6, 7, 2, 3, 8, 9, 10, \
496 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
497 SUBTARGET_REG_ALLOC_ORDER \
500 #else /* Better for fp code at expense of int code. */
501 #define REG_ALLOC_ORDER \
503 0, 1, 2, 3, 4, 5, 6, 7, 8, \
504 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
505 SUBTARGET_REG_ALLOC_ORDER \
509 /* Return number of consecutive hard regs needed starting at reg REGNO
510 to hold something of mode MODE.
511 This is ordinarily the length in words of a value of mode MODE
512 but can be less for certain modes in special long registers. */
513 #define HARD_REGNO_NREGS(REGNO, MODE) \
514 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
516 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
517 extern const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
518 extern unsigned int m32r_mode_class
[];
519 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
520 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
522 /* A C expression that is nonzero if it is desirable to choose
523 register allocation so as to avoid move instructions between a
524 value of mode MODE1 and a value of mode MODE2.
526 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
527 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
528 MODE2)' must be zero. */
530 /* Tie QI/HI/SI modes together. */
531 #define MODES_TIEABLE_P(MODE1, MODE2) \
532 ( GET_MODE_CLASS (MODE1) == MODE_INT \
533 && GET_MODE_CLASS (MODE2) == MODE_INT \
534 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
535 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
537 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
538 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
540 /* Register classes and constants. */
542 /* Define the classes of registers for register constraints in the
543 machine description. Also define ranges of constants.
545 One of the classes must always be named ALL_REGS and include all hard regs.
546 If there is more than one class, another class must be named NO_REGS
547 and contain no registers.
549 The name GENERAL_REGS must be the name of a class (or an alias for
550 another name such as ALL_REGS). This is the class of registers
551 that is allowed by "g" or "r" in a register constraint.
552 Also, registers outside this class are allocated only when
553 instructions express preferences for them.
555 The classes must be numbered in nondecreasing order; that is,
556 a larger-numbered class must never be contained completely
557 in a smaller-numbered class.
559 For any two classes, it is very desirable that there be another
560 class that represents their union.
562 It is important that any condition codes have class NO_REGS.
563 See `register_operand'. */
567 NO_REGS
, CARRY_REG
, ACCUM_REGS
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
570 #define IRA_COVER_CLASSES \
572 ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \
575 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
577 /* Give names of register classes as strings for dump file. */
578 #define REG_CLASS_NAMES \
579 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
581 /* Define which registers fit in which classes.
582 This is an initializer for a vector of HARD_REG_SET
583 of length N_REG_CLASSES. */
585 #ifndef SUBTARGET_REG_CLASS_CARRY
586 #define SUBTARGET_REG_CLASS_CARRY 0
589 #ifndef SUBTARGET_REG_CLASS_ACCUM
590 #define SUBTARGET_REG_CLASS_ACCUM 0
593 #ifndef SUBTARGET_REG_CLASS_GENERAL
594 #define SUBTARGET_REG_CLASS_GENERAL 0
597 #ifndef SUBTARGET_REG_CLASS_ALL
598 #define SUBTARGET_REG_CLASS_ALL 0
601 #define REG_CLASS_CONTENTS \
604 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
605 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
606 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
607 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
610 /* The same information, inverted:
611 Return the class number of the smallest class containing
612 reg number REGNO. This could be a conditional expression
613 or could index an array. */
614 extern enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
615 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
617 /* The class value for index registers, and the one for base regs. */
618 #define INDEX_REG_CLASS GENERAL_REGS
619 #define BASE_REG_CLASS GENERAL_REGS
621 /* These assume that REGNO is a hard or pseudo reg number.
622 They give nonzero only if REGNO is a hard reg of the suitable class
623 or a pseudo reg currently allocated to a suitable hard reg.
624 Since they use reg_renumber, they are safe only once reg_renumber
625 has been allocated, which happens in local-alloc.c. */
626 #define REGNO_OK_FOR_BASE_P(REGNO) \
627 ((REGNO) < FIRST_PSEUDO_REGISTER \
628 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
629 : GPR_P (reg_renumber[REGNO]))
631 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
633 /* Return the maximum number of consecutive registers
634 needed to represent mode MODE in a register of class CLASS. */
635 #define CLASS_MAX_NREGS(CLASS, MODE) \
636 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
638 /* Return true if a value is inside a range. */
639 #define IN_RANGE_P(VALUE, LOW, HIGH) \
640 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
641 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
643 /* Some range macros. */
644 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
645 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
646 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
647 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
649 /* Stack layout and stack pointer usage. */
651 /* Define this macro if pushing a word onto the stack moves the stack
652 pointer to a smaller address. */
653 #define STACK_GROWS_DOWNWARD
655 /* Offset from frame pointer to start allocating local variables at.
656 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
657 first local allocated. Otherwise, it is the offset to the BEGINNING
658 of the first local allocated. */
659 /* The frame pointer points at the same place as the stack pointer, except if
660 alloca has been called. */
661 #define STARTING_FRAME_OFFSET \
662 M32R_STACK_ALIGN (crtl->outgoing_args_size)
664 /* Offset from the stack pointer register to the first location at which
665 outgoing arguments are placed. */
666 #define STACK_POINTER_OFFSET 0
668 /* Offset of first parameter from the argument pointer register value. */
669 #define FIRST_PARM_OFFSET(FNDECL) 0
671 /* Register to use for pushing function arguments. */
672 #define STACK_POINTER_REGNUM 15
674 /* Base register for access to local variables of the function. */
675 #define FRAME_POINTER_REGNUM 13
677 /* Base register for access to arguments of the function. */
678 #define ARG_POINTER_REGNUM 16
680 /* Register in which static-chain is passed to a function.
681 This must not be a register used by the prologue. */
682 #define STATIC_CHAIN_REGNUM 7
684 /* These aren't official macros. */
685 #define PROLOGUE_TMP_REGNUM 4
686 #define RETURN_ADDR_REGNUM 14
687 /* #define GP_REGNUM 12 */
688 #define CARRY_REGNUM 17
689 #define ACCUM_REGNUM 18
690 #define M32R_MAX_INT_REGS 16
692 #ifndef SUBTARGET_GPR_P
693 #define SUBTARGET_GPR_P(REGNO) 0
696 #ifndef SUBTARGET_ACCUM_P
697 #define SUBTARGET_ACCUM_P(REGNO) 0
700 #ifndef SUBTARGET_CARRY_P
701 #define SUBTARGET_CARRY_P(REGNO) 0
704 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
705 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
706 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
708 /* Eliminating the frame and arg pointers. */
711 /* C statement to store the difference between the frame pointer
712 and the stack pointer values immediately after the function prologue.
713 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
714 need not be defined. */
715 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
716 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
719 /* If defined, this macro specifies a table of register pairs used to
720 eliminate unneeded registers that point into the stack frame. If
721 it is not defined, the only elimination attempted by the compiler
722 is to replace references to the frame pointer with references to
725 Note that the elimination of the argument pointer with the stack
726 pointer is specified first since that is the preferred elimination. */
728 #define ELIMINABLE_REGS \
729 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
730 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
731 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
733 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
734 specifies the initial difference between the specified pair of
735 registers. This macro must be defined if `ELIMINABLE_REGS' is
738 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
741 int size = m32r_compute_frame_size (get_frame_size ()); \
743 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
745 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
746 (OFFSET) = size - crtl->args.pretend_args_size; \
747 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
748 (OFFSET) = size - crtl->args.pretend_args_size; \
750 gcc_unreachable (); \
754 /* Function argument passing. */
756 /* If defined, the maximum amount of space required for outgoing
757 arguments will be computed and placed into the variable
758 `crtl->outgoing_args_size'. No space will be pushed
759 onto the stack for each call; instead, the function prologue should
760 increase the stack frame size by this amount. */
761 #define ACCUMULATE_OUTGOING_ARGS 1
763 /* Define a data type for recording info about an argument list
764 during the scan of that argument list. This data type should
765 hold all necessary information about the function itself
766 and about the args processed so far, enough to enable macros
767 such as FUNCTION_ARG to determine where the next arg should go. */
768 #define CUMULATIVE_ARGS int
770 /* Initialize a variable CUM of type CUMULATIVE_ARGS
771 for a call to a function whose data type is FNTYPE.
772 For a library call, FNTYPE is 0. */
773 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
776 /* The number of registers used for parameter passing. Local to this file. */
777 #define M32R_MAX_PARM_REGS 4
779 /* 1 if N is a possible register number for function argument passing. */
780 #define FUNCTION_ARG_REGNO_P(N) \
781 ((unsigned) (N) < M32R_MAX_PARM_REGS)
784 /* Function results. */
786 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
787 #define DEFAULT_PCC_STRUCT_RETURN 0
789 /* Function entry and exit. */
791 /* Initialize data used by insn expanders. This is called from
792 init_emit, once for each function, before code is generated. */
793 #define INIT_EXPANDERS m32r_init_expanders ()
795 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
796 the stack pointer does not matter. The value is tested only in
797 functions that have frame pointers.
798 No definition is equivalent to always zero. */
799 #define EXIT_IGNORE_STACK 1
801 /* Output assembler code to FILE to increment profiler label # LABELNO
802 for profiling a function entry. */
803 #undef FUNCTION_PROFILER
804 #define FUNCTION_PROFILER(FILE, LABELNO) \
809 fprintf (FILE, "\tld24 r14,#mcount\n"); \
810 fprintf (FILE, "\tadd r14,r12\n"); \
811 fprintf (FILE, "\tld r14,@r14\n"); \
812 fprintf (FILE, "\tjl r14\n"); \
817 fprintf (FILE, "\tbl mcount\n"); \
820 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
821 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
822 fprintf (FILE, "\tjl r14\n"); \
825 fprintf (FILE, "\taddi sp,#4\n"); \
831 /* On the M32R, the trampoline is:
833 mv r7, lr -> bl L1 ; 178e 7e01
834 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
835 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
836 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
840 #ifndef CACHE_FLUSH_FUNC
841 #define CACHE_FLUSH_FUNC "_flush_cache"
843 #ifndef CACHE_FLUSH_TRAP
844 #define CACHE_FLUSH_TRAP 12
847 /* Length in bytes of the trampoline for entering a nested function. */
848 #define TRAMPOLINE_SIZE 24
851 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
853 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
855 /* Addressing modes, and classification of registers for them. */
857 /* Maximum number of registers that can appear in a valid memory address. */
858 #define MAX_REGS_PER_ADDRESS 1
860 /* We have post-inc load and pre-dec,pre-inc store,
861 but only for 4 byte vals. */
862 #define HAVE_PRE_DECREMENT 1
863 #define HAVE_PRE_INCREMENT 1
864 #define HAVE_POST_INCREMENT 1
866 /* Recognize any constant value that is a valid address. */
867 #define CONSTANT_ADDRESS_P(X) \
868 ( GET_CODE (X) == LABEL_REF \
869 || GET_CODE (X) == SYMBOL_REF \
871 || (GET_CODE (X) == CONST \
872 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
874 /* Nonzero if the constant value X is a legitimate general operand.
875 We don't allow (plus symbol large-constant) as the relocations can't
876 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
877 We allow all CONST_DOUBLE's as the md file patterns will force the
878 constant to memory if they can't handle them. */
880 #define LEGITIMATE_CONSTANT_P(X) \
881 (! (GET_CODE (X) == CONST \
882 && GET_CODE (XEXP (X, 0)) == PLUS \
883 && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \
884 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
885 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
887 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
888 and check its validity for a certain class.
889 We have two alternate definitions for each of them.
890 The usual definition accepts all pseudo regs; the other rejects
891 them unless they have been allocated suitable hard regs.
892 The symbol REG_OK_STRICT causes the latter definition to be used.
894 Most source files want to accept pseudo regs in the hope that
895 they will get allocated to the class that the insn wants them to be in.
896 Source files for reload pass need to be strict.
897 After reload, it makes no difference, since pseudo regs have
898 been eliminated by then. */
902 /* Nonzero if X is a hard reg that can be used as a base reg. */
903 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
904 /* Nonzero if X is a hard reg that can be used as an index. */
905 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
909 /* Nonzero if X is a hard reg that can be used as a base reg
910 or if it is a pseudo reg. */
911 #define REG_OK_FOR_BASE_P(X) \
913 || (REGNO (X)) == ARG_POINTER_REGNUM \
914 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
915 /* Nonzero if X is a hard reg that can be used as an index
916 or if it is a pseudo reg. */
917 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
921 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
922 that is a valid memory address for an instruction.
923 The MODE argument is the machine mode for the MEM expression
924 that wants to use this address. */
926 /* Local to this file. */
927 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
929 /* Local to this file. */
930 #define RTX_OK_FOR_OFFSET_P(X) \
931 (CONST_INT_P (X) && INT16_P (INTVAL (X)))
933 /* Local to this file. */
934 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
935 (GET_CODE (X) == PLUS \
936 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
937 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
939 /* Local to this file. */
940 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
941 since more than one instruction will be required. */
942 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
943 (GET_CODE (X) == LO_SUM \
944 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
945 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
946 && CONSTANT_P (XEXP (X, 1)))
948 /* Local to this file. */
949 /* Is this a load and increment operation. */
950 #define LOAD_POSTINC_P(MODE, X) \
951 (((MODE) == SImode || (MODE) == SFmode) \
952 && GET_CODE (X) == POST_INC \
953 && REG_P (XEXP (X, 0)) \
954 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
956 /* Local to this file. */
957 /* Is this an increment/decrement and store operation. */
958 #define STORE_PREINC_PREDEC_P(MODE, X) \
959 (((MODE) == SImode || (MODE) == SFmode) \
960 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
961 && REG_P (XEXP (X, 0)) \
962 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
964 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
967 if (RTX_OK_FOR_BASE_P (X)) \
969 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
971 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
973 if (LOAD_POSTINC_P ((MODE), (X))) \
975 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
980 /* Condition code usage. */
982 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
983 floating point inequality comparison. */
984 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
988 /* The cost of a branch insn. */
989 /* A value of 2 here causes GCC to avoid using branches in comparisons like
990 while (a < N && a). Branches aren't that expensive on the M32R so
991 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
992 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1)
994 /* Nonzero if access to memory by bytes is slow and undesirable.
995 For RISC chips, it means that access to memory by bytes is no
996 better than access by words when possible, so grab a whole word
997 and maybe make use of that. */
998 #define SLOW_BYTE_ACCESS 1
1000 /* Define this macro if it is as good or better to call a constant
1001 function address than to call an address kept in a register. */
1002 #define NO_FUNCTION_CSE
1004 /* Section selection. */
1006 #define TEXT_SECTION_ASM_OP "\t.section .text"
1007 #define DATA_SECTION_ASM_OP "\t.section .data"
1008 #define BSS_SECTION_ASM_OP "\t.section .bss"
1010 /* Define this macro if jump tables (for tablejump insns) should be
1011 output in the text section, along with the assembler instructions.
1012 Otherwise, the readonly data section is used.
1013 This macro is irrelevant if there is no separate readonly data section. */
1014 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1016 /* Position Independent Code. */
1018 /* The register number of the register used to address a table of static
1019 data addresses in memory. In some cases this register is defined by a
1020 processor's ``application binary interface'' (ABI). When this macro
1021 is defined, RTL is generated for this register once, as with the stack
1022 pointer and frame pointer registers. If this macro is not defined, it
1023 is up to the machine-dependent files to allocate such a register (if
1025 #define PIC_OFFSET_TABLE_REGNUM 12
1027 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1028 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1030 /* This register is call-saved on the M32R. */
1031 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1033 /* A C expression that is nonzero if X is a legitimate immediate
1034 operand on the target machine when generating position independent code.
1035 You can assume that X satisfies CONSTANT_P, so you need not
1036 check this. You can also assume `flag_pic' is true, so you need not
1037 check it either. You need not define this macro if all constants
1038 (including SYMBOL_REF) can be immediate operands when generating
1039 position independent code. */
1040 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1042 /* Control the assembler format that we output. */
1044 /* A C string constant describing how to begin a comment in the target
1045 assembler language. The compiler assumes that the comment will
1046 end at the end of the line. */
1047 #define ASM_COMMENT_START ";"
1049 /* Output to assembler file text saying following lines
1050 may contain character constants, extra white space, comments, etc. */
1051 #define ASM_APP_ON ""
1053 /* Output to assembler file text saying following lines
1054 no longer contain unusual constructs. */
1055 #define ASM_APP_OFF ""
1057 /* Globalizing directive for a label. */
1058 #define GLOBAL_ASM_OP "\t.global\t"
1060 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
1061 dbxout_stab_value_internal_label_diff here because
1062 we need to use .debugsym for the line label. */
1064 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
1067 const char * begin_label = \
1068 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \
1070 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
1072 dbxout_begin_stabn_sline (line); \
1073 assemble_name (file, label); \
1075 assemble_name (file, begin_label); \
1076 fputs ("\n\t.debugsym ", file); \
1077 assemble_name (file, label); \
1078 putc ('\n', file); \
1083 /* How to refer to registers in assembler output.
1084 This sequence is indexed by compiler's hard-register-number (see above). */
1085 #ifndef SUBTARGET_REGISTER_NAMES
1086 #define SUBTARGET_REGISTER_NAMES
1089 #define REGISTER_NAMES \
1091 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1092 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1093 "ap", "cbit", "a0" \
1094 SUBTARGET_REGISTER_NAMES \
1097 /* If defined, a C initializer for an array of structures containing
1098 a name and a register number. This macro defines additional names
1099 for hard registers, thus allowing the `asm' option in declarations
1100 to refer to registers using alternate names. */
1101 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1102 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1105 #define ADDITIONAL_REGISTER_NAMES \
1107 /*{ "gp", GP_REGNUM },*/ \
1108 { "r13", FRAME_POINTER_REGNUM }, \
1109 { "r14", RETURN_ADDR_REGNUM }, \
1110 { "r15", STACK_POINTER_REGNUM }, \
1111 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1114 /* If defined, C string expressions to be used for the `%R', `%L',
1115 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1116 are useful when a single `md' file must support multiple assembler
1117 formats. In that case, the various `tm.h' files can define these
1118 macros differently. */
1119 #define REGISTER_PREFIX ""
1120 #define LOCAL_LABEL_PREFIX ".L"
1121 #define USER_LABEL_PREFIX ""
1122 #define IMMEDIATE_PREFIX "#"
1124 /* This is how to output an element of a case-vector that is absolute. */
1125 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1129 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1130 fprintf (FILE, "\t.word\t"); \
1131 assemble_name (FILE, label); \
1132 fprintf (FILE, "\n"); \
1136 /* This is how to output an element of a case-vector that is relative. */
1137 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1141 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1142 fprintf (FILE, "\t.word\t"); \
1143 assemble_name (FILE, label); \
1144 fprintf (FILE, "-"); \
1145 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1146 assemble_name (FILE, label); \
1147 fprintf (FILE, "\n"); \
1151 /* The desired alignment for the location counter at the beginning
1153 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1154 if -malign-loops. */
1155 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1157 /* Define this to be the maximum number of insns to move around when moving
1158 a loop test from the top of a loop to the bottom
1159 and seeing whether to duplicate it. The default is thirty.
1161 Loop unrolling currently doesn't like this optimization, so
1162 disable doing if we are unrolling loops and saving space. */
1163 #define LOOP_TEST_THRESHOLD (optimize_size \
1164 && !flag_unroll_loops \
1165 && !flag_unroll_all_loops ? 2 : 30)
1167 /* This is how to output an assembler line
1168 that says to advance the location counter
1169 to a multiple of 2**LOG bytes. */
1170 /* .balign is used to avoid confusion. */
1171 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1175 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1179 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1180 separate, explicit argument. If you define this macro, it is used in
1181 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1182 handling the required alignment of the variable. The alignment is
1183 specified as the number of bits. */
1185 #define SCOMMON_ASM_OP "\t.scomm\t"
1187 #undef ASM_OUTPUT_ALIGNED_COMMON
1188 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1191 if (! TARGET_SDATA_NONE \
1193 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1194 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1196 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1197 assemble_name ((FILE), (NAME)); \
1198 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1202 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1205 if (! TARGET_SDATA_NONE \
1207 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1208 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
1210 switch_to_section (bss_section); \
1211 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1212 last_assemble_variable_decl = DECL; \
1213 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1214 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1218 /* Debugging information. */
1220 /* Generate DBX and DWARF debugging information. */
1221 #define DBX_DEBUGGING_INFO 1
1222 #define DWARF2_DEBUGGING_INFO 1
1224 /* Use DWARF2 debugging info by default. */
1225 #undef PREFERRED_DEBUGGING_TYPE
1226 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1228 /* Turn off splitting of long stabs. */
1229 #define DBX_CONTIN_LENGTH 0
1231 /* Miscellaneous. */
1233 /* Specify the machine mode that this machine uses
1234 for the index in the tablejump instruction. */
1235 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1237 /* Define if operations between registers always perform the operation
1238 on the full register even if a narrower mode is specified. */
1239 #define WORD_REGISTER_OPERATIONS
1241 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1242 will either zero-extend or sign-extend. The value of this macro should
1243 be the code that says which one of the two operations is implicitly
1244 done, UNKNOWN if none. */
1245 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1247 /* Max number of bytes we can move from memory
1248 to memory in one reasonably fast instruction. */
1251 /* Define this to be nonzero if shift instructions ignore all but the low-order
1253 #define SHIFT_COUNT_TRUNCATED 1
1255 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1256 is done just by pretending it is already truncated. */
1257 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1259 /* Specify the machine mode that pointers have.
1260 After generation of rtl, the compiler makes no further distinction
1261 between pointers and any other objects of this machine mode. */
1262 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has
1263 its own problems (you have to add extendpsisi2 and truncsipsi2).
1265 #define Pmode SImode
1267 /* A function address in a call instruction. */
1268 #define FUNCTION_MODE SImode
1270 /* M32R function types. */
1271 enum m32r_function_type
1273 M32R_FUNCTION_UNKNOWN
, M32R_FUNCTION_NORMAL
, M32R_FUNCTION_INTERRUPT
1276 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1278 /* The maximum number of bytes to copy using pairs of load/store instructions.
1279 If a block is larger than this then a loop will be generated to copy
1280 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
1281 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1282 string copy in it. */
1283 #define MAX_MOVE_BYTES 32