1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #define IN_TARGET_CODE 1
24 #include "coretypes.h"
28 #include "stringpool.h"
33 #include "fold-const.h"
35 #include "stor-layout.h"
38 #include "insn-config.h"
39 #include "conditions.h"
41 #include "insn-attr.h"
43 #include "diagnostic-core.h"
60 #include "cfgcleanup.h"
61 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
62 #include "sched-int.h"
63 #include "insn-codes.h"
70 /* This file should be included last. */
71 #include "target-def.h"
73 enum reg_class regno_reg_class
[] =
75 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
76 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
77 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
78 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
79 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
80 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
85 /* The minimum number of integer registers that we want to save with the
86 movem instruction. Using two movel instructions instead of a single
87 moveml is about 15% faster for the 68020 and 68030 at no expense in
89 #define MIN_MOVEM_REGS 3
91 /* The minimum number of floating point registers that we want to save
92 with the fmovem instruction. */
93 #define MIN_FMOVEM_REGS 1
95 /* Structure describing stack frame layout. */
98 /* Stack pointer to frame pointer offset. */
101 /* Offset of FPU registers. */
102 HOST_WIDE_INT foffset
;
104 /* Frame size in bytes (rounded up). */
107 /* Data and address register. */
109 unsigned int reg_mask
;
113 unsigned int fpu_mask
;
115 /* Offsets relative to ARG_POINTER. */
116 HOST_WIDE_INT frame_pointer_offset
;
117 HOST_WIDE_INT stack_pointer_offset
;
119 /* Function which the above information refers to. */
123 /* Current frame information calculated by m68k_compute_frame_layout(). */
124 static struct m68k_frame current_frame
;
126 /* Structure describing an m68k address.
128 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
129 with null fields evaluating to 0. Here:
131 - BASE satisfies m68k_legitimate_base_reg_p
132 - INDEX satisfies m68k_legitimate_index_reg_p
133 - OFFSET satisfies m68k_legitimate_constant_address_p
135 INDEX is either HImode or SImode. The other fields are SImode.
137 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
138 the address is (BASE)+. */
139 struct m68k_address
{
147 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
149 static int m68k_sched_issue_rate (void);
150 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
151 static void m68k_sched_md_init_global (FILE *, int, int);
152 static void m68k_sched_md_finish_global (FILE *, int);
153 static void m68k_sched_md_init (FILE *, int, int);
154 static void m68k_sched_dfa_pre_advance_cycle (void);
155 static void m68k_sched_dfa_post_advance_cycle (void);
156 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
158 static bool m68k_can_eliminate (const int, const int);
159 static void m68k_conditional_register_usage (void);
160 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
161 static void m68k_option_override (void);
162 static void m68k_override_options_after_change (void);
163 static rtx
find_addr_reg (rtx
);
164 static const char *singlemove_string (rtx
*);
165 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
166 HOST_WIDE_INT
, tree
);
167 static rtx
m68k_struct_value_rtx (tree
, int);
168 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
169 tree args
, int flags
,
171 static void m68k_compute_frame_layout (void);
172 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
173 static bool m68k_ok_for_sibcall_p (tree
, tree
);
174 static bool m68k_tls_symbol_p (rtx
);
175 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
176 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
177 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
178 static bool m68k_return_in_memory (const_tree
, const_tree
);
180 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
181 static void m68k_trampoline_init (rtx
, tree
, rtx
);
182 static poly_int64
m68k_return_pops_args (tree
, tree
, poly_int64
);
183 static rtx
m68k_delegitimize_address (rtx
);
184 static void m68k_function_arg_advance (cumulative_args_t
,
185 const function_arg_info
&);
186 static rtx
m68k_function_arg (cumulative_args_t
, const function_arg_info
&);
187 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
188 static bool m68k_output_addr_const_extra (FILE *, rtx
);
189 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
190 static enum flt_eval_method
191 m68k_excess_precision (enum excess_precision_type
);
192 static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode
);
193 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode
);
194 static bool m68k_modes_tieable_p (machine_mode
, machine_mode
);
195 static machine_mode
m68k_promote_function_mode (const_tree
, machine_mode
,
196 int *, const_tree
, int);
198 /* Initialize the GCC target structure. */
200 #if INT_OP_GROUP == INT_OP_DOT_WORD
201 #undef TARGET_ASM_ALIGNED_HI_OP
202 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
205 #if INT_OP_GROUP == INT_OP_NO_DOT
206 #undef TARGET_ASM_BYTE_OP
207 #define TARGET_ASM_BYTE_OP "\tbyte\t"
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
214 #if INT_OP_GROUP == INT_OP_DC
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
223 #undef TARGET_ASM_UNALIGNED_HI_OP
224 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
225 #undef TARGET_ASM_UNALIGNED_SI_OP
226 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
228 #undef TARGET_ASM_OUTPUT_MI_THUNK
229 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
230 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
231 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
233 #undef TARGET_ASM_FILE_START_APP_OFF
234 #define TARGET_ASM_FILE_START_APP_OFF true
236 #undef TARGET_LEGITIMIZE_ADDRESS
237 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
239 #undef TARGET_SCHED_ADJUST_COST
240 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
242 #undef TARGET_SCHED_ISSUE_RATE
243 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
245 #undef TARGET_SCHED_VARIABLE_ISSUE
246 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
248 #undef TARGET_SCHED_INIT_GLOBAL
249 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
251 #undef TARGET_SCHED_FINISH_GLOBAL
252 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
254 #undef TARGET_SCHED_INIT
255 #define TARGET_SCHED_INIT m68k_sched_md_init
257 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
258 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
260 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
261 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
263 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
264 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
265 m68k_sched_first_cycle_multipass_dfa_lookahead
267 #undef TARGET_OPTION_OVERRIDE
268 #define TARGET_OPTION_OVERRIDE m68k_option_override
270 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
271 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
273 #undef TARGET_RTX_COSTS
274 #define TARGET_RTX_COSTS m68k_rtx_costs
276 #undef TARGET_ATTRIBUTE_TABLE
277 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
279 #undef TARGET_PROMOTE_PROTOTYPES
280 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
282 #undef TARGET_STRUCT_VALUE_RTX
283 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
285 #undef TARGET_CANNOT_FORCE_CONST_MEM
286 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
288 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
289 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
291 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
292 #undef TARGET_RETURN_IN_MEMORY
293 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
297 #undef TARGET_HAVE_TLS
298 #define TARGET_HAVE_TLS (true)
300 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
301 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
305 #define TARGET_LRA_P hook_bool_void_false
307 #undef TARGET_LEGITIMATE_ADDRESS_P
308 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
310 #undef TARGET_CAN_ELIMINATE
311 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
313 #undef TARGET_CONDITIONAL_REGISTER_USAGE
314 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
316 #undef TARGET_TRAMPOLINE_INIT
317 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
319 #undef TARGET_RETURN_POPS_ARGS
320 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
322 #undef TARGET_DELEGITIMIZE_ADDRESS
323 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
325 #undef TARGET_FUNCTION_ARG
326 #define TARGET_FUNCTION_ARG m68k_function_arg
328 #undef TARGET_FUNCTION_ARG_ADVANCE
329 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
331 #undef TARGET_LEGITIMATE_CONSTANT_P
332 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
334 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
335 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
337 #undef TARGET_C_EXCESS_PRECISION
338 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
340 /* The value stored by TAS. */
341 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
342 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
344 #undef TARGET_HARD_REGNO_NREGS
345 #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
346 #undef TARGET_HARD_REGNO_MODE_OK
347 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
349 #undef TARGET_MODES_TIEABLE_P
350 #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
352 #undef TARGET_PROMOTE_FUNCTION_MODE
353 #define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode
355 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
356 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
358 static const struct attribute_spec m68k_attribute_table
[] =
360 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
361 affects_type_identity, handler, exclude } */
362 { "interrupt", 0, 0, true, false, false, false,
363 m68k_handle_fndecl_attribute
, NULL
},
364 { "interrupt_handler", 0, 0, true, false, false, false,
365 m68k_handle_fndecl_attribute
, NULL
},
366 { "interrupt_thread", 0, 0, true, false, false, false,
367 m68k_handle_fndecl_attribute
, NULL
},
368 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
371 struct gcc_target targetm
= TARGET_INITIALIZER
;
373 /* Base flags for 68k ISAs. */
374 #define FL_FOR_isa_00 FL_ISA_68000
375 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
376 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
377 generated 68881 code for 68020 and 68030 targets unless explicitly told
379 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
380 | FL_BITFIELD | FL_68881 | FL_CAS)
381 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
382 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
384 /* Base flags for ColdFire ISAs. */
385 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
386 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
387 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
388 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
389 /* ISA_C is not upwardly compatible with ISA_B. */
390 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
394 /* Traditional 68000 instruction sets. */
400 /* ColdFire instruction set variants. */
408 /* Information about one of the -march, -mcpu or -mtune arguments. */
409 struct m68k_target_selection
411 /* The argument being described. */
414 /* For -mcpu, this is the device selected by the option.
415 For -mtune and -march, it is a representative device
416 for the microarchitecture or ISA respectively. */
417 enum target_device device
;
419 /* The M68K_DEVICE fields associated with DEVICE. See the comment
420 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
422 enum uarch_type microarch
;
427 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
428 static const struct m68k_target_selection all_devices
[] =
430 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
431 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
432 #include "m68k-devices.def"
434 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
437 /* A list of all ISAs, mapping each one to a representative device.
438 Used for -march selection. */
439 static const struct m68k_target_selection all_isas
[] =
441 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
442 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
443 #include "m68k-isas.def"
445 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
448 /* A list of all microarchitectures, mapping each one to a representative
449 device. Used for -mtune selection. */
450 static const struct m68k_target_selection all_microarchs
[] =
452 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
453 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
454 #include "m68k-microarchs.def"
455 #undef M68K_MICROARCH
456 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
459 /* The entries associated with the -mcpu, -march and -mtune settings,
460 or null for options that have not been used. */
461 const struct m68k_target_selection
*m68k_cpu_entry
;
462 const struct m68k_target_selection
*m68k_arch_entry
;
463 const struct m68k_target_selection
*m68k_tune_entry
;
465 /* Which CPU we are generating code for. */
466 enum target_device m68k_cpu
;
468 /* Which microarchitecture to tune for. */
469 enum uarch_type m68k_tune
;
471 /* Which FPU to use. */
472 enum fpu_type m68k_fpu
;
474 /* The set of FL_* flags that apply to the target processor. */
475 unsigned int m68k_cpu_flags
;
477 /* The set of FL_* flags that apply to the processor to be tuned for. */
478 unsigned int m68k_tune_flags
;
480 /* Asm templates for calling or jumping to an arbitrary symbolic address,
481 or NULL if such calls or jumps are not supported. The address is held
483 const char *m68k_symbolic_call
;
484 const char *m68k_symbolic_jump
;
486 /* Enum variable that corresponds to m68k_symbolic_call values. */
487 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
490 /* Implement TARGET_OPTION_OVERRIDE. */
493 m68k_option_override (void)
495 const struct m68k_target_selection
*entry
;
496 unsigned long target_mask
;
498 if (global_options_set
.x_m68k_arch_option
)
499 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
501 if (global_options_set
.x_m68k_cpu_option
)
502 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
504 if (global_options_set
.x_m68k_tune_option
)
505 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
513 -march=ARCH should generate code that runs any processor
514 implementing architecture ARCH. -mcpu=CPU should override -march
515 and should generate code that runs on processor CPU, making free
516 use of any instructions that CPU understands. -mtune=UARCH applies
517 on top of -mcpu or -march and optimizes the code for UARCH. It does
518 not change the target architecture. */
521 /* Complain if the -march setting is for a different microarchitecture,
522 or includes flags that the -mcpu setting doesn't. */
524 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
525 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
526 warning (0, "%<-mcpu=%s%> conflicts with %<-march=%s%>",
527 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
529 entry
= m68k_cpu_entry
;
532 entry
= m68k_arch_entry
;
535 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
537 m68k_cpu_flags
= entry
->flags
;
539 /* Use the architecture setting to derive default values for
543 /* ColdFire is lenient about alignment. */
544 if (!TARGET_COLDFIRE
)
545 target_mask
|= MASK_STRICT_ALIGNMENT
;
547 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
548 target_mask
|= MASK_BITFIELD
;
549 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
550 target_mask
|= MASK_CF_HWDIV
;
551 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
552 target_mask
|= MASK_HARD_FLOAT
;
553 target_flags
|= target_mask
& ~target_flags_explicit
;
555 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
556 m68k_cpu
= entry
->device
;
559 m68k_tune
= m68k_tune_entry
->microarch
;
560 m68k_tune_flags
= m68k_tune_entry
->flags
;
562 #ifdef M68K_DEFAULT_TUNE
563 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
565 enum target_device dev
;
566 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
567 m68k_tune_flags
= all_devices
[dev
].flags
;
572 m68k_tune
= entry
->microarch
;
573 m68k_tune_flags
= entry
->flags
;
576 /* Set the type of FPU. */
577 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
578 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
581 /* Sanity check to ensure that msep-data and mid-sahred-library are not
582 * both specified together. Doing so simply doesn't make sense.
584 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
585 error ("cannot specify both %<-msep-data%> and %<-mid-shared-library%>");
587 /* If we're generating code for a separate A5 relative data segment,
588 * we've got to enable -fPIC as well. This might be relaxable to
589 * -fpic but it hasn't been tested properly.
591 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
594 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
595 error if the target does not support them. */
596 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
597 error ("%<-mpcrel%> %<-fPIC%> is not currently supported on selected cpu");
599 /* ??? A historic way of turning on pic, or is this intended to
600 be an embedded thing that doesn't have the same name binding
601 significance that it does on hosted ELF systems? */
602 if (TARGET_PCREL
&& flag_pic
== 0)
607 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
609 m68k_symbolic_jump
= "jra %a0";
611 else if (TARGET_ID_SHARED_LIBRARY
)
612 /* All addresses must be loaded from the GOT. */
614 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
617 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
619 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
622 /* No unconditional long branch */;
623 else if (TARGET_PCREL
)
624 m68k_symbolic_jump
= "bra%.l %c0";
626 m68k_symbolic_jump
= "bra%.l %p0";
627 /* Turn off function cse if we are doing PIC. We always want
628 function call to be done as `bsr foo@PLTPC'. */
629 /* ??? It's traditional to do this for -mpcrel too, but it isn't
630 clear how intentional that is. */
631 flag_no_function_cse
= 1;
634 switch (m68k_symbolic_call_var
)
636 case M68K_SYMBOLIC_CALL_JSR
:
637 m68k_symbolic_call
= "jsr %a0";
640 case M68K_SYMBOLIC_CALL_BSR_C
:
641 m68k_symbolic_call
= "bsr%.l %c0";
644 case M68K_SYMBOLIC_CALL_BSR_P
:
645 m68k_symbolic_call
= "bsr%.l %p0";
648 case M68K_SYMBOLIC_CALL_NONE
:
649 gcc_assert (m68k_symbolic_call
== NULL
);
656 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
657 parse_alignment_opts ();
658 int label_alignment
= align_labels
.levels
[0].get_value ();
659 if (label_alignment
> 2)
661 warning (0, "%<-falign-labels=%d%> is not supported", label_alignment
);
662 str_align_labels
= "1";
665 int loop_alignment
= align_loops
.levels
[0].get_value ();
666 if (loop_alignment
> 2)
668 warning (0, "%<-falign-loops=%d%> is not supported", loop_alignment
);
669 str_align_loops
= "1";
673 if ((opt_fstack_limit_symbol_arg
!= NULL
|| opt_fstack_limit_register_no
>= 0)
676 warning (0, "%<-fstack-limit-%> options are not supported on this cpu");
677 opt_fstack_limit_symbol_arg
= NULL
;
678 opt_fstack_limit_register_no
= -1;
681 SUBTARGET_OVERRIDE_OPTIONS
;
683 /* Setup scheduling options. */
685 m68k_sched_cpu
= CPU_CFV1
;
687 m68k_sched_cpu
= CPU_CFV2
;
689 m68k_sched_cpu
= CPU_CFV3
;
691 m68k_sched_cpu
= CPU_CFV4
;
694 m68k_sched_cpu
= CPU_UNKNOWN
;
695 flag_schedule_insns
= 0;
696 flag_schedule_insns_after_reload
= 0;
697 flag_modulo_sched
= 0;
698 flag_live_range_shrinkage
= 0;
701 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
703 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
704 m68k_sched_mac
= MAC_CF_EMAC
;
705 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
706 m68k_sched_mac
= MAC_CF_MAC
;
708 m68k_sched_mac
= MAC_NO
;
712 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
715 m68k_override_options_after_change (void)
717 if (m68k_sched_cpu
== CPU_UNKNOWN
)
719 flag_schedule_insns
= 0;
720 flag_schedule_insns_after_reload
= 0;
721 flag_modulo_sched
= 0;
722 flag_live_range_shrinkage
= 0;
726 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
727 given argument and NAME is the argument passed to -mcpu. Return NULL
728 if -mcpu was not passed. */
731 m68k_cpp_cpu_ident (const char *prefix
)
735 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
738 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
739 given argument and NAME is the name of the representative device for
740 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
743 m68k_cpp_cpu_family (const char *prefix
)
747 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
750 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
751 "interrupt_handler" attribute and interrupt_thread if FUNC has an
752 "interrupt_thread" attribute. Otherwise, return
753 m68k_fk_normal_function. */
755 enum m68k_function_kind
756 m68k_get_function_kind (tree func
)
760 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
762 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
764 return m68k_fk_interrupt_handler
;
766 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
768 return m68k_fk_interrupt_handler
;
770 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
772 return m68k_fk_interrupt_thread
;
774 return m68k_fk_normal_function
;
777 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
778 struct attribute_spec.handler. */
780 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
781 tree args ATTRIBUTE_UNUSED
,
782 int flags ATTRIBUTE_UNUSED
,
785 if (TREE_CODE (*node
) != FUNCTION_DECL
)
787 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
789 *no_add_attrs
= true;
792 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
794 error ("multiple interrupt attributes not allowed");
795 *no_add_attrs
= true;
799 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
801 error ("interrupt_thread is available only on fido");
802 *no_add_attrs
= true;
809 m68k_compute_frame_layout (void)
813 enum m68k_function_kind func_kind
=
814 m68k_get_function_kind (current_function_decl
);
815 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
816 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
818 /* Only compute the frame once per function.
819 Don't cache information until reload has been completed. */
820 if (current_frame
.funcdef_no
== current_function_funcdef_no
824 current_frame
.size
= (get_frame_size () + 3) & -4;
828 /* Interrupt thread does not need to save any register. */
829 if (!interrupt_thread
)
830 for (regno
= 0; regno
< 16; regno
++)
831 if (m68k_save_reg (regno
, interrupt_handler
))
833 mask
|= 1 << (regno
- D0_REG
);
836 current_frame
.offset
= saved
* 4;
837 current_frame
.reg_no
= saved
;
838 current_frame
.reg_mask
= mask
;
840 current_frame
.foffset
= 0;
842 if (TARGET_HARD_FLOAT
)
844 /* Interrupt thread does not need to save any register. */
845 if (!interrupt_thread
)
846 for (regno
= 16; regno
< 24; regno
++)
847 if (m68k_save_reg (regno
, interrupt_handler
))
849 mask
|= 1 << (regno
- FP0_REG
);
852 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
853 current_frame
.offset
+= current_frame
.foffset
;
855 current_frame
.fpu_no
= saved
;
856 current_frame
.fpu_mask
= mask
;
858 /* Remember what function this frame refers to. */
859 current_frame
.funcdef_no
= current_function_funcdef_no
;
862 /* Worker function for TARGET_CAN_ELIMINATE. */
865 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
867 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
871 m68k_initial_elimination_offset (int from
, int to
)
874 /* The arg pointer points 8 bytes before the start of the arguments,
875 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
876 frame pointer in most frames. */
877 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
878 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
879 return argptr_offset
;
881 m68k_compute_frame_layout ();
883 gcc_assert (to
== STACK_POINTER_REGNUM
);
886 case ARG_POINTER_REGNUM
:
887 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
888 case FRAME_POINTER_REGNUM
:
889 return current_frame
.offset
+ current_frame
.size
;
895 /* Refer to the array `regs_ever_live' to determine which registers
896 to save; `regs_ever_live[I]' is nonzero if register number I
897 is ever used in the function. This function is responsible for
898 knowing which registers should not be saved even if used.
899 Return true if we need to save REGNO. */
902 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
904 if (flag_pic
&& regno
== PIC_REG
)
906 if (crtl
->saves_all_registers
)
908 if (crtl
->uses_pic_offset_table
)
910 /* Reload may introduce constant pool references into a function
911 that thitherto didn't need a PIC register. Note that the test
912 above will not catch that case because we will only set
913 crtl->uses_pic_offset_table when emitting
914 the address reloads. */
915 if (crtl
->uses_const_pool
)
919 if (crtl
->calls_eh_return
)
924 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
925 if (test
== INVALID_REGNUM
)
932 /* Fixed regs we never touch. */
933 if (fixed_regs
[regno
])
936 /* The frame pointer (if it is such) is handled specially. */
937 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
940 /* Interrupt handlers must also save call_used_regs
941 if they are live or when calling nested functions. */
942 if (interrupt_handler
)
944 if (df_regs_ever_live_p (regno
))
947 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
951 /* Never need to save registers that aren't touched. */
952 if (!df_regs_ever_live_p (regno
))
955 /* Otherwise save everything that isn't call-clobbered. */
956 return !call_used_regs
[regno
];
959 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
960 the lowest memory address. COUNT is the number of registers to be
961 moved, with register REGNO + I being moved if bit I of MASK is set.
962 STORE_P specifies the direction of the move and ADJUST_STACK_P says
963 whether or not this is pre-decrement (if STORE_P) or post-increment
964 (if !STORE_P) operation. */
967 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
968 unsigned int count
, unsigned int regno
,
969 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
972 rtx body
, addr
, src
, operands
[2];
975 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
976 mode
= reg_raw_mode
[regno
];
981 src
= plus_constant (Pmode
, base
,
983 * GET_MODE_SIZE (mode
)
984 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
985 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
988 for (; mask
!= 0; mask
>>= 1, regno
++)
991 addr
= plus_constant (Pmode
, base
, offset
);
992 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
993 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
994 XVECEXP (body
, 0, i
++)
995 = gen_rtx_SET (operands
[0], operands
[1]);
996 offset
+= GET_MODE_SIZE (mode
);
998 gcc_assert (i
== XVECLEN (body
, 0));
1000 return emit_insn (body
);
1003 /* Make INSN a frame-related instruction. */
1006 m68k_set_frame_related (rtx_insn
*insn
)
1011 RTX_FRAME_RELATED_P (insn
) = 1;
1012 body
= PATTERN (insn
);
1013 if (GET_CODE (body
) == PARALLEL
)
1014 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1015 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1018 /* Emit RTL for the "prologue" define_expand. */
1021 m68k_expand_prologue (void)
1023 HOST_WIDE_INT fsize_with_regs
;
1024 rtx limit
, src
, dest
;
1026 m68k_compute_frame_layout ();
1028 if (flag_stack_usage_info
)
1029 current_function_static_stack_size
1030 = current_frame
.size
+ current_frame
.offset
;
1032 /* If the stack limit is a symbol, we can check it here,
1033 before actually allocating the space. */
1034 if (crtl
->limit_stack
1035 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1037 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1038 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1040 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1041 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1043 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1044 stack_pointer_rtx
, limit
),
1045 stack_pointer_rtx
, limit
,
1049 fsize_with_regs
= current_frame
.size
;
1050 if (TARGET_COLDFIRE
)
1052 /* ColdFire's move multiple instructions do not allow pre-decrement
1053 addressing. Add the size of movem saves to the initial stack
1054 allocation instead. */
1055 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1056 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1057 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1058 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1061 if (frame_pointer_needed
)
1063 if (fsize_with_regs
== 0 && TUNE_68040
)
1065 /* On the 68040, two separate moves are faster than link.w 0. */
1066 dest
= gen_frame_mem (Pmode
,
1067 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1068 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1069 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1070 stack_pointer_rtx
));
1072 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1073 m68k_set_frame_related
1074 (emit_insn (gen_link (frame_pointer_rtx
,
1075 GEN_INT (-4 - fsize_with_regs
))));
1078 m68k_set_frame_related
1079 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1080 m68k_set_frame_related
1081 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1083 GEN_INT (-fsize_with_regs
))));
1086 /* If the frame pointer is needed, emit a special barrier that
1087 will prevent the scheduler from moving stores to the frame
1088 before the stack adjustment. */
1089 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1091 else if (fsize_with_regs
!= 0)
1092 m68k_set_frame_related
1093 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1095 GEN_INT (-fsize_with_regs
))));
1097 if (current_frame
.fpu_mask
)
1099 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1101 m68k_set_frame_related
1102 (m68k_emit_movem (stack_pointer_rtx
,
1103 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1104 current_frame
.fpu_no
, FP0_REG
,
1105 current_frame
.fpu_mask
, true, true));
1110 /* If we're using moveml to save the integer registers,
1111 the stack pointer will point to the bottom of the moveml
1112 save area. Find the stack offset of the first FP register. */
1113 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1116 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1117 m68k_set_frame_related
1118 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1119 current_frame
.fpu_no
, FP0_REG
,
1120 current_frame
.fpu_mask
, true, false));
1124 /* If the stack limit is not a symbol, check it here.
1125 This has the disadvantage that it may be too late... */
1126 if (crtl
->limit_stack
)
1128 if (REG_P (stack_limit_rtx
))
1129 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1131 stack_pointer_rtx
, stack_limit_rtx
,
1134 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1135 warning (0, "stack limit expression is not supported");
1138 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1140 /* Store each register separately in the same order moveml does. */
1143 for (i
= 16; i
-- > 0; )
1144 if (current_frame
.reg_mask
& (1 << i
))
1146 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1147 dest
= gen_frame_mem (SImode
,
1148 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1149 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1154 if (TARGET_COLDFIRE
)
1155 /* The required register save space has already been allocated.
1156 The first register should be stored at (%sp). */
1157 m68k_set_frame_related
1158 (m68k_emit_movem (stack_pointer_rtx
, 0,
1159 current_frame
.reg_no
, D0_REG
,
1160 current_frame
.reg_mask
, true, false));
1162 m68k_set_frame_related
1163 (m68k_emit_movem (stack_pointer_rtx
,
1164 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1165 current_frame
.reg_no
, D0_REG
,
1166 current_frame
.reg_mask
, true, true));
1169 if (!TARGET_SEP_DATA
1170 && crtl
->uses_pic_offset_table
)
1171 emit_insn (gen_load_got (pic_offset_table_rtx
));
1174 /* Return true if a simple (return) instruction is sufficient for this
1175 instruction (i.e. if no epilogue is needed). */
1178 m68k_use_return_insn (void)
1180 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1183 m68k_compute_frame_layout ();
1184 return current_frame
.offset
== 0;
1187 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1188 SIBCALL_P says which.
1190 The function epilogue should not depend on the current stack pointer!
1191 It should use the frame pointer only, if there is a frame pointer.
1192 This is mandatory because of alloca; we also take advantage of it to
1193 omit stack adjustments before returning. */
1196 m68k_expand_epilogue (bool sibcall_p
)
1198 HOST_WIDE_INT fsize
, fsize_with_regs
;
1199 bool big
, restore_from_sp
;
1201 m68k_compute_frame_layout ();
1203 fsize
= current_frame
.size
;
1205 restore_from_sp
= false;
1207 /* FIXME : crtl->is_leaf below is too strong.
1208 What we really need to know there is if there could be pending
1209 stack adjustment needed at that point. */
1210 restore_from_sp
= (!frame_pointer_needed
1211 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1213 /* fsize_with_regs is the size we need to adjust the sp when
1214 popping the frame. */
1215 fsize_with_regs
= fsize
;
1216 if (TARGET_COLDFIRE
&& restore_from_sp
)
1218 /* ColdFire's move multiple instructions do not allow post-increment
1219 addressing. Add the size of movem loads to the final deallocation
1221 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1222 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1223 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1224 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1227 if (current_frame
.offset
+ fsize
>= 0x8000
1229 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1232 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1233 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1235 /* ColdFire's move multiple instructions do not support the
1236 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1237 stack-based restore. */
1238 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1239 GEN_INT (-(current_frame
.offset
+ fsize
)));
1240 emit_insn (gen_blockage ());
1241 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1242 gen_rtx_REG (Pmode
, A1_REG
),
1243 frame_pointer_rtx
));
1244 restore_from_sp
= true;
1248 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1254 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1256 /* Restore each register separately in the same order moveml does. */
1258 HOST_WIDE_INT offset
;
1260 offset
= current_frame
.offset
+ fsize
;
1261 for (i
= 0; i
< 16; i
++)
1262 if (current_frame
.reg_mask
& (1 << i
))
1268 /* Generate the address -OFFSET(%fp,%a1.l). */
1269 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1270 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1271 addr
= plus_constant (Pmode
, addr
, -offset
);
1273 else if (restore_from_sp
)
1274 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1276 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1277 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1278 gen_frame_mem (SImode
, addr
));
1279 offset
-= GET_MODE_SIZE (SImode
);
1282 else if (current_frame
.reg_mask
)
1285 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1286 gen_rtx_REG (Pmode
, A1_REG
),
1288 -(current_frame
.offset
+ fsize
),
1289 current_frame
.reg_no
, D0_REG
,
1290 current_frame
.reg_mask
, false, false);
1291 else if (restore_from_sp
)
1292 m68k_emit_movem (stack_pointer_rtx
, 0,
1293 current_frame
.reg_no
, D0_REG
,
1294 current_frame
.reg_mask
, false,
1297 m68k_emit_movem (frame_pointer_rtx
,
1298 -(current_frame
.offset
+ fsize
),
1299 current_frame
.reg_no
, D0_REG
,
1300 current_frame
.reg_mask
, false, false);
1303 if (current_frame
.fpu_no
> 0)
1306 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1307 gen_rtx_REG (Pmode
, A1_REG
),
1309 -(current_frame
.foffset
+ fsize
),
1310 current_frame
.fpu_no
, FP0_REG
,
1311 current_frame
.fpu_mask
, false, false);
1312 else if (restore_from_sp
)
1314 if (TARGET_COLDFIRE
)
1318 /* If we used moveml to restore the integer registers, the
1319 stack pointer will still point to the bottom of the moveml
1320 save area. Find the stack offset of the first FP
1322 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1325 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1326 m68k_emit_movem (stack_pointer_rtx
, offset
,
1327 current_frame
.fpu_no
, FP0_REG
,
1328 current_frame
.fpu_mask
, false, false);
1331 m68k_emit_movem (stack_pointer_rtx
, 0,
1332 current_frame
.fpu_no
, FP0_REG
,
1333 current_frame
.fpu_mask
, false, true);
1336 m68k_emit_movem (frame_pointer_rtx
,
1337 -(current_frame
.foffset
+ fsize
),
1338 current_frame
.fpu_no
, FP0_REG
,
1339 current_frame
.fpu_mask
, false, false);
1342 emit_insn (gen_blockage ());
1343 if (frame_pointer_needed
)
1344 emit_insn (gen_unlink (frame_pointer_rtx
));
1345 else if (fsize_with_regs
)
1346 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1348 GEN_INT (fsize_with_regs
)));
1350 if (crtl
->calls_eh_return
)
1351 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1353 EH_RETURN_STACKADJ_RTX
));
1356 emit_jump_insn (ret_rtx
);
1359 /* Return true if X is a valid comparison operator for the dbcc
1362 Note it rejects floating point comparison operators.
1363 (In the future we could use Fdbcc).
1365 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1368 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1370 switch (GET_CODE (x
))
1372 case EQ
: case NE
: case GTU
: case LTU
:
1376 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1378 case GT
: case LT
: case GE
: case LE
:
1379 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1385 /* Return nonzero if flags are currently in the 68881 flag register. */
1387 flags_in_68881 (void)
1389 /* We could add support for these in the future */
1390 return cc_status
.flags
& CC_IN_68881
;
1393 /* Return true if PARALLEL contains register REGNO. */
1395 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1399 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1402 if (GET_CODE (parallel
) != PARALLEL
)
1405 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1409 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1410 if (REG_P (x
) && REGNO (x
) == regno
)
1417 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1420 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1422 enum m68k_function_kind kind
;
1424 /* We cannot use sibcalls for nested functions because we use the
1425 static chain register for indirect calls. */
1426 if (CALL_EXPR_STATIC_CHAIN (exp
))
1429 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1431 /* Check that the return value locations are the same. For
1432 example that we aren't returning a value from the sibling in
1433 a D0 register but then need to transfer it to a A0 register. */
1437 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1439 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1441 /* Check that the values are equal or that the result the callee
1442 function returns is superset of what the current function returns. */
1443 if (!(rtx_equal_p (cfun_value
, call_value
)
1444 || (REG_P (cfun_value
)
1445 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1449 kind
= m68k_get_function_kind (current_function_decl
);
1450 if (kind
== m68k_fk_normal_function
)
1451 /* We can always sibcall from a normal function, because it's
1452 undefined if it is calling an interrupt function. */
1455 /* Otherwise we can only sibcall if the function kind is known to be
1457 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1463 /* On the m68k all args are always pushed. */
1466 m68k_function_arg (cumulative_args_t
, const function_arg_info
&)
1472 m68k_function_arg_advance (cumulative_args_t cum_v
,
1473 const function_arg_info
&arg
)
1475 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1477 *cum
+= (arg
.promoted_size_in_bytes () + 3) & ~3;
1480 /* Convert X to a legitimate function call memory reference and return the
1484 m68k_legitimize_call_address (rtx x
)
1486 gcc_assert (MEM_P (x
));
1487 if (call_operand (XEXP (x
, 0), VOIDmode
))
1489 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1492 /* Likewise for sibling calls. */
1495 m68k_legitimize_sibcall_address (rtx x
)
1497 gcc_assert (MEM_P (x
));
1498 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1501 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1502 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1505 /* Convert X to a legitimate address and return it if successful. Otherwise
1508 For the 68000, we handle X+REG by loading X into a register R and
1509 using R+REG. R will go in an address reg and indexing will be used.
1510 However, if REG is a broken-out memory address or multiplication,
1511 nothing needs to be done because REG can certainly go in an address reg. */
1514 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1516 if (m68k_tls_symbol_p (x
))
1517 return m68k_legitimize_tls_address (x
);
1519 if (GET_CODE (x
) == PLUS
)
1521 int ch
= (x
) != (oldx
);
1524 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1526 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1529 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1531 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1534 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1538 if (GET_CODE (XEXP (x
, 1)) == REG
1539 && GET_CODE (XEXP (x
, 0)) == REG
)
1541 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1544 x
= force_operand (x
, 0);
1548 if (memory_address_p (mode
, x
))
1551 if (GET_CODE (XEXP (x
, 0)) == REG
1552 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1553 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1554 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1556 rtx temp
= gen_reg_rtx (Pmode
);
1557 rtx val
= force_operand (XEXP (x
, 1), 0);
1558 emit_move_insn (temp
, val
);
1561 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1562 && GET_CODE (XEXP (x
, 0)) == REG
)
1563 x
= force_operand (x
, 0);
1565 else if (GET_CODE (XEXP (x
, 1)) == REG
1566 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1567 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1568 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1570 rtx temp
= gen_reg_rtx (Pmode
);
1571 rtx val
= force_operand (XEXP (x
, 0), 0);
1572 emit_move_insn (temp
, val
);
1575 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1576 && GET_CODE (XEXP (x
, 1)) == REG
)
1577 x
= force_operand (x
, 0);
1585 /* Output a dbCC; jCC sequence. Note we do not handle the
1586 floating point version of this sequence (Fdbcc). We also
1587 do not handle alternative conditions when CC_NO_OVERFLOW is
1588 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1589 kick those out before we get here. */
1592 output_dbcc_and_branch (rtx
*operands
)
1594 switch (GET_CODE (operands
[3]))
1597 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1601 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1605 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1609 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1613 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1617 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1621 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1625 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1629 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1633 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1640 /* If the decrement is to be done in SImode, then we have
1641 to compensate for the fact that dbcc decrements in HImode. */
1642 switch (GET_MODE (operands
[0]))
1645 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1657 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1660 enum rtx_code op_code
= GET_CODE (op
);
1662 /* This does not produce a useful cc. */
1665 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1666 below. Swap the operands and change the op if these requirements
1667 are not fulfilled. */
1668 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1672 operand1
= operand2
;
1674 op_code
= swap_condition (op_code
);
1676 loperands
[0] = operand1
;
1677 if (GET_CODE (operand1
) == REG
)
1678 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1680 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1681 if (operand2
!= const0_rtx
)
1683 loperands
[2] = operand2
;
1684 if (GET_CODE (operand2
) == REG
)
1685 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1687 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1689 loperands
[4] = gen_label_rtx ();
1690 if (operand2
!= const0_rtx
)
1691 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1694 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1695 output_asm_insn ("tst%.l %0", loperands
);
1697 output_asm_insn ("cmp%.w #0,%0", loperands
);
1699 output_asm_insn ("jne %l4", loperands
);
1701 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1702 output_asm_insn ("tst%.l %1", loperands
);
1704 output_asm_insn ("cmp%.w #0,%1", loperands
);
1707 loperands
[5] = dest
;
1712 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1713 CODE_LABEL_NUMBER (loperands
[4]));
1714 output_asm_insn ("seq %5", loperands
);
1718 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1719 CODE_LABEL_NUMBER (loperands
[4]));
1720 output_asm_insn ("sne %5", loperands
);
1724 loperands
[6] = gen_label_rtx ();
1725 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1726 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1727 CODE_LABEL_NUMBER (loperands
[4]));
1728 output_asm_insn ("sgt %5", loperands
);
1729 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1730 CODE_LABEL_NUMBER (loperands
[6]));
1734 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1735 CODE_LABEL_NUMBER (loperands
[4]));
1736 output_asm_insn ("shi %5", loperands
);
1740 loperands
[6] = gen_label_rtx ();
1741 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1742 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1743 CODE_LABEL_NUMBER (loperands
[4]));
1744 output_asm_insn ("slt %5", loperands
);
1745 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1746 CODE_LABEL_NUMBER (loperands
[6]));
1750 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1751 CODE_LABEL_NUMBER (loperands
[4]));
1752 output_asm_insn ("scs %5", loperands
);
1756 loperands
[6] = gen_label_rtx ();
1757 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1758 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1759 CODE_LABEL_NUMBER (loperands
[4]));
1760 output_asm_insn ("sge %5", loperands
);
1761 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1762 CODE_LABEL_NUMBER (loperands
[6]));
1766 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1767 CODE_LABEL_NUMBER (loperands
[4]));
1768 output_asm_insn ("scc %5", loperands
);
1772 loperands
[6] = gen_label_rtx ();
1773 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1774 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1775 CODE_LABEL_NUMBER (loperands
[4]));
1776 output_asm_insn ("sle %5", loperands
);
1777 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1778 CODE_LABEL_NUMBER (loperands
[6]));
1782 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1783 CODE_LABEL_NUMBER (loperands
[4]));
1784 output_asm_insn ("sls %5", loperands
);
1794 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1796 operands
[0] = countop
;
1797 operands
[1] = dataop
;
1799 if (GET_CODE (countop
) == CONST_INT
)
1801 register int count
= INTVAL (countop
);
1802 /* If COUNT is bigger than size of storage unit in use,
1803 advance to the containing unit of same size. */
1804 if (count
> signpos
)
1806 int offset
= (count
& ~signpos
) / 8;
1807 count
= count
& signpos
;
1808 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1810 if (count
== signpos
)
1811 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1813 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1815 /* These three statements used to use next_insns_test_no...
1816 but it appears that this should do the same job. */
1818 && next_insn_tests_no_inequality (insn
))
1821 && next_insn_tests_no_inequality (insn
))
1824 && next_insn_tests_no_inequality (insn
))
1826 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1827 On some m68k variants unfortunately that's slower than btst.
1828 On 68000 and higher, that should also work for all HImode operands. */
1829 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1831 if (count
== 3 && DATA_REG_P (operands
[1])
1832 && next_insn_tests_no_inequality (insn
))
1834 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1835 return "move%.w %1,%%ccr";
1837 if (count
== 2 && DATA_REG_P (operands
[1])
1838 && next_insn_tests_no_inequality (insn
))
1840 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1841 return "move%.w %1,%%ccr";
1843 /* count == 1 followed by bvc/bvs and
1844 count == 0 followed by bcc/bcs are also possible, but need
1845 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1848 cc_status
.flags
= CC_NOT_NEGATIVE
;
1850 return "btst %0,%1";
1853 /* Return true if X is a legitimate base register. STRICT_P says
1854 whether we need strict checking. */
1857 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1859 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1860 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1865 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1866 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1869 /* Return true if X is a legitimate index register. STRICT_P says
1870 whether we need strict checking. */
1873 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1875 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1880 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1881 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1884 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1885 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1886 ADDRESS if so. STRICT_P says whether we need strict checking. */
1889 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1893 /* Check for a scale factor. */
1895 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1896 && GET_CODE (x
) == MULT
1897 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1898 && (INTVAL (XEXP (x
, 1)) == 2
1899 || INTVAL (XEXP (x
, 1)) == 4
1900 || (INTVAL (XEXP (x
, 1)) == 8
1901 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1903 scale
= INTVAL (XEXP (x
, 1));
1907 /* Check for a word extension. */
1908 if (!TARGET_COLDFIRE
1909 && GET_CODE (x
) == SIGN_EXTEND
1910 && GET_MODE (XEXP (x
, 0)) == HImode
)
1913 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1915 address
->scale
= scale
;
1923 /* Return true if X is an illegitimate symbolic constant. */
1926 m68k_illegitimate_symbolic_constant_p (rtx x
)
1930 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1932 split_const (x
, &base
, &offset
);
1933 if (GET_CODE (base
) == SYMBOL_REF
1934 && !offset_within_block_p (base
, INTVAL (offset
)))
1937 return m68k_tls_reference_p (x
, false);
1940 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1943 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1945 return m68k_illegitimate_symbolic_constant_p (x
);
1948 /* Return true if X is a legitimate constant address that can reach
1949 bytes in the range [X, X + REACH). STRICT_P says whether we need
1953 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1957 if (!CONSTANT_ADDRESS_P (x
))
1961 && !(strict_p
&& TARGET_PCREL
)
1962 && symbolic_operand (x
, VOIDmode
))
1965 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1967 split_const (x
, &base
, &offset
);
1968 if (GET_CODE (base
) == SYMBOL_REF
1969 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1973 return !m68k_tls_reference_p (x
, false);
1976 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1977 labels will become jump tables. */
1980 m68k_jump_table_ref_p (rtx x
)
1982 if (GET_CODE (x
) != LABEL_REF
)
1985 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1986 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1989 insn
= next_nonnote_insn (insn
);
1990 return insn
&& JUMP_TABLE_DATA_P (insn
);
1993 /* Return true if X is a legitimate address for values of mode MODE.
1994 STRICT_P says whether strict checking is needed. If the address
1995 is valid, describe its components in *ADDRESS. */
1998 m68k_decompose_address (machine_mode mode
, rtx x
,
1999 bool strict_p
, struct m68k_address
*address
)
2003 memset (address
, 0, sizeof (*address
));
2005 if (mode
== BLKmode
)
2008 reach
= GET_MODE_SIZE (mode
);
2010 /* Check for (An) (mode 2). */
2011 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2017 /* Check for -(An) and (An)+ (modes 3 and 4). */
2018 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2019 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2021 address
->code
= GET_CODE (x
);
2022 address
->base
= XEXP (x
, 0);
2026 /* Check for (d16,An) (mode 5). */
2027 if (GET_CODE (x
) == PLUS
2028 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2029 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2030 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2032 address
->base
= XEXP (x
, 0);
2033 address
->offset
= XEXP (x
, 1);
2037 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2038 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2040 if (GET_CODE (x
) == PLUS
2041 && XEXP (x
, 0) == pic_offset_table_rtx
)
2043 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2044 they are invalid in this context. */
2045 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2047 address
->base
= XEXP (x
, 0);
2048 address
->offset
= XEXP (x
, 1);
2053 /* The ColdFire FPU only accepts addressing modes 2-5. */
2054 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2057 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2058 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2059 All these modes are variations of mode 7. */
2060 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2062 address
->offset
= x
;
2066 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2069 ??? do_tablejump creates these addresses before placing the target
2070 label, so we have to assume that unplaced labels are jump table
2071 references. It seems unlikely that we would ever generate indexed
2072 accesses to unplaced labels in other cases. */
2073 if (GET_CODE (x
) == PLUS
2074 && m68k_jump_table_ref_p (XEXP (x
, 1))
2075 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2077 address
->offset
= XEXP (x
, 1);
2081 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2082 (bd,An,Xn.SIZE*SCALE) addresses. */
2086 /* Check for a nonzero base displacement. */
2087 if (GET_CODE (x
) == PLUS
2088 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2090 address
->offset
= XEXP (x
, 1);
2094 /* Check for a suppressed index register. */
2095 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2101 /* Check for a suppressed base register. Do not allow this case
2102 for non-symbolic offsets as it effectively gives gcc freedom
2103 to treat data registers as base registers, which can generate
2106 && symbolic_operand (address
->offset
, VOIDmode
)
2107 && m68k_decompose_index (x
, strict_p
, address
))
2112 /* Check for a nonzero base displacement. */
2113 if (GET_CODE (x
) == PLUS
2114 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2115 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2117 address
->offset
= XEXP (x
, 1);
2122 /* We now expect the sum of a base and an index. */
2123 if (GET_CODE (x
) == PLUS
)
2125 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2126 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2128 address
->base
= XEXP (x
, 0);
2132 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2133 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2135 address
->base
= XEXP (x
, 1);
2142 /* Return true if X is a legitimate address for values of mode MODE.
2143 STRICT_P says whether strict checking is needed. */
2146 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2148 struct m68k_address address
;
2150 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2153 /* Return true if X is a memory, describing its address in ADDRESS if so.
2154 Apply strict checking if called during or after reload. */
2157 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2160 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2161 reload_in_progress
|| reload_completed
,
2165 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2168 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2170 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2173 /* Return true if X matches the 'Q' constraint. It must be a memory
2174 with a base address and no constant offset or index. */
2177 m68k_matches_q_p (rtx x
)
2179 struct m68k_address address
;
2181 return (m68k_legitimate_mem_p (x
, &address
)
2182 && address
.code
== UNKNOWN
2188 /* Return true if X matches the 'U' constraint. It must be a base address
2189 with a constant offset and no index. */
2192 m68k_matches_u_p (rtx x
)
2194 struct m68k_address address
;
2196 return (m68k_legitimate_mem_p (x
, &address
)
2197 && address
.code
== UNKNOWN
2203 /* Return GOT pointer. */
2208 if (pic_offset_table_rtx
== NULL_RTX
)
2209 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2211 crtl
->uses_pic_offset_table
= 1;
2213 return pic_offset_table_rtx
;
2216 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2218 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2219 RELOC_TLSIE
, RELOC_TLSLE
};
2221 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2223 /* Wrap symbol X into unspec representing relocation RELOC.
2224 BASE_REG - register that should be added to the result.
2225 TEMP_REG - if non-null, temporary register. */
2228 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2232 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2234 if (TARGET_COLDFIRE
&& use_x_p
)
2235 /* When compiling with -mx{got, tls} switch the code will look like this:
2237 move.l <X>@<RELOC>,<TEMP_REG>
2238 add.l <BASE_REG>,<TEMP_REG> */
2240 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2241 to put @RELOC after reference. */
2242 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2244 x
= gen_rtx_CONST (Pmode
, x
);
2246 if (temp_reg
== NULL
)
2248 gcc_assert (can_create_pseudo_p ());
2249 temp_reg
= gen_reg_rtx (Pmode
);
2252 emit_move_insn (temp_reg
, x
);
2253 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2258 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2260 x
= gen_rtx_CONST (Pmode
, x
);
2262 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2268 /* Helper for m68k_unwrap_symbol.
2269 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2270 sets *RELOC_PTR to relocation type for the symbol. */
2273 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2274 enum m68k_reloc
*reloc_ptr
)
2276 if (GET_CODE (orig
) == CONST
)
2279 enum m68k_reloc dummy
;
2283 if (reloc_ptr
== NULL
)
2286 /* Handle an addend. */
2287 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2288 && CONST_INT_P (XEXP (x
, 1)))
2291 if (GET_CODE (x
) == UNSPEC
)
2293 switch (XINT (x
, 1))
2295 case UNSPEC_RELOC16
:
2296 orig
= XVECEXP (x
, 0, 0);
2297 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2300 case UNSPEC_RELOC32
:
2301 if (unwrap_reloc32_p
)
2303 orig
= XVECEXP (x
, 0, 0);
2304 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2317 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2318 UNSPEC_RELOC32 wrappers. */
2321 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2323 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2326 /* Adjust decorated address operand before outputing assembler for it. */
2329 m68k_adjust_decorated_operand (rtx op
)
2331 /* Combine and, possibly, other optimizations may do good job
2333 (const (unspec [(symbol)]))
2335 (const (plus (unspec [(symbol)])
2337 The problem with this is emitting @TLS or @GOT decorations.
2338 The decoration is emitted when processing (unspec), so the
2339 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2341 It seems that the easiest solution to this is to convert such
2343 (const (unspec [(plus (symbol)
2345 Note, that the top level of operand remains intact, so we don't have
2346 to patch up anything outside of the operand. */
2348 subrtx_var_iterator::array_type array
;
2349 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2352 if (m68k_unwrap_symbol (x
, true) != x
)
2356 gcc_assert (GET_CODE (x
) == CONST
);
2359 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2364 unspec
= XEXP (plus
, 0);
2365 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2366 addend
= XEXP (plus
, 1);
2367 gcc_assert (CONST_INT_P (addend
));
2369 /* We now have all the pieces, rearrange them. */
2371 /* Move symbol to plus. */
2372 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2374 /* Move plus inside unspec. */
2375 XVECEXP (unspec
, 0, 0) = plus
;
2377 /* Move unspec to top level of const. */
2378 XEXP (x
, 0) = unspec
;
2380 iter
.skip_subrtxes ();
2385 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2386 If REG is non-null, use it; generate new pseudo otherwise. */
2389 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2393 if (reg
== NULL_RTX
)
2395 gcc_assert (can_create_pseudo_p ());
2396 reg
= gen_reg_rtx (Pmode
);
2399 insn
= emit_move_insn (reg
, x
);
2400 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2402 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2407 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2411 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2413 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2415 x
= gen_rtx_MEM (Pmode
, x
);
2416 MEM_READONLY_P (x
) = 1;
2421 /* Legitimize PIC addresses. If the address is already
2422 position-independent, we return ORIG. Newly generated
2423 position-independent addresses go to REG. If we need more
2424 than one register, we lose.
2426 An address is legitimized by making an indirect reference
2427 through the Global Offset Table with the name of the symbol
2430 The assembler and linker are responsible for placing the
2431 address of the symbol in the GOT. The function prologue
2432 is responsible for initializing a5 to the starting address
2435 The assembler is also responsible for translating a symbol name
2436 into a constant displacement from the start of the GOT.
2438 A quick example may make things a little clearer:
2440 When not generating PIC code to store the value 12345 into _foo
2441 we would generate the following code:
2445 When generating PIC two transformations are made. First, the compiler
2446 loads the address of foo into a register. So the first transformation makes:
2451 The code in movsi will intercept the lea instruction and call this
2452 routine which will transform the instructions into:
2454 movel a5@(_foo:w), a0
2458 That (in a nutshell) is how *all* symbol and label references are
2462 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2467 /* First handle a simple SYMBOL_REF or LABEL_REF */
2468 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2472 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2473 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2475 else if (GET_CODE (orig
) == CONST
)
2479 /* Make sure this has not already been legitimized. */
2480 if (m68k_unwrap_symbol (orig
, true) != orig
)
2485 /* legitimize both operands of the PLUS */
2486 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2488 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2489 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2490 base
== reg
? 0 : reg
);
2492 if (GET_CODE (orig
) == CONST_INT
)
2493 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2495 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2501 /* The __tls_get_addr symbol. */
2502 static GTY(()) rtx m68k_tls_get_addr
;
2504 /* Return SYMBOL_REF for __tls_get_addr. */
2507 m68k_get_tls_get_addr (void)
2509 if (m68k_tls_get_addr
== NULL_RTX
)
2510 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2512 return m68k_tls_get_addr
;
2515 /* Return libcall result in A0 instead of usual D0. */
2516 static bool m68k_libcall_value_in_a0_p
= false;
2518 /* Emit instruction sequence that calls __tls_get_addr. X is
2519 the TLS symbol we are referencing and RELOC is the symbol type to use
2520 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2521 emitted. A pseudo register with result of __tls_get_addr call is
2525 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2531 /* Emit the call sequence. */
2534 /* FIXME: Unfortunately, emit_library_call_value does not
2535 consider (plus (%a5) (const (unspec))) to be a good enough
2536 operand for push, so it forces it into a register. The bad
2537 thing about this is that combiner, due to copy propagation and other
2538 optimizations, sometimes cannot later fix this. As a consequence,
2539 additional register may be allocated resulting in a spill.
2540 For reference, see args processing loops in
2541 calls.c:emit_library_call_value_1.
2542 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2543 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2545 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2546 is the simpliest way of generating a call. The difference between
2547 __tls_get_addr() and libcall is that the result is returned in D0
2548 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2549 which temporarily switches returning the result to A0. */
2551 m68k_libcall_value_in_a0_p
= true;
2552 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2554 m68k_libcall_value_in_a0_p
= false;
2556 insns
= get_insns ();
2559 gcc_assert (can_create_pseudo_p ());
2560 dest
= gen_reg_rtx (Pmode
);
2561 emit_libcall_block (insns
, dest
, a0
, eqv
);
2566 /* The __tls_get_addr symbol. */
2567 static GTY(()) rtx m68k_read_tp
;
2569 /* Return SYMBOL_REF for __m68k_read_tp. */
2572 m68k_get_m68k_read_tp (void)
2574 if (m68k_read_tp
== NULL_RTX
)
2575 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2577 return m68k_read_tp
;
2580 /* Emit instruction sequence that calls __m68k_read_tp.
2581 A pseudo register with result of __m68k_read_tp call is returned. */
2584 m68k_call_m68k_read_tp (void)
2593 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2594 is the simpliest way of generating a call. The difference between
2595 __m68k_read_tp() and libcall is that the result is returned in D0
2596 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2597 which temporarily switches returning the result to A0. */
2599 /* Emit the call sequence. */
2600 m68k_libcall_value_in_a0_p
= true;
2601 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2603 m68k_libcall_value_in_a0_p
= false;
2604 insns
= get_insns ();
2607 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2608 share the m68k_read_tp result with other IE/LE model accesses. */
2609 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2611 gcc_assert (can_create_pseudo_p ());
2612 dest
= gen_reg_rtx (Pmode
);
2613 emit_libcall_block (insns
, dest
, a0
, eqv
);
2618 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2619 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2623 m68k_legitimize_tls_address (rtx orig
)
2625 switch (SYMBOL_REF_TLS_MODEL (orig
))
2627 case TLS_MODEL_GLOBAL_DYNAMIC
:
2628 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2631 case TLS_MODEL_LOCAL_DYNAMIC
:
2637 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2638 share the LDM result with other LD model accesses. */
2639 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2642 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2644 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2646 if (can_create_pseudo_p ())
2647 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2653 case TLS_MODEL_INITIAL_EXEC
:
2658 a0
= m68k_call_m68k_read_tp ();
2660 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2661 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2663 if (can_create_pseudo_p ())
2664 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2670 case TLS_MODEL_LOCAL_EXEC
:
2675 a0
= m68k_call_m68k_read_tp ();
2677 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2679 if (can_create_pseudo_p ())
2680 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2693 /* Return true if X is a TLS symbol. */
2696 m68k_tls_symbol_p (rtx x
)
2698 if (!TARGET_HAVE_TLS
)
2701 if (GET_CODE (x
) != SYMBOL_REF
)
2704 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2707 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2708 though illegitimate one.
2709 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2712 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2714 if (!TARGET_HAVE_TLS
)
2719 subrtx_var_iterator::array_type array
;
2720 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2724 /* Note: this is not the same as m68k_tls_symbol_p. */
2725 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2728 /* Don't recurse into legitimate TLS references. */
2729 if (m68k_tls_reference_p (x
, true))
2730 iter
.skip_subrtxes ();
2736 enum m68k_reloc reloc
= RELOC_GOT
;
2738 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2739 && TLS_RELOC_P (reloc
));
2745 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2747 /* Return the type of move that should be used for integer I. */
2750 m68k_const_method (HOST_WIDE_INT i
)
2757 /* The ColdFire doesn't have byte or word operations. */
2758 /* FIXME: This may not be useful for the m68060 either. */
2759 if (!TARGET_COLDFIRE
)
2761 /* if -256 < N < 256 but N is not in range for a moveq
2762 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2763 if (USE_MOVQ (i
^ 0xff))
2765 /* Likewise, try with not.w */
2766 if (USE_MOVQ (i
^ 0xffff))
2768 /* This is the only value where neg.w is useful */
2773 /* Try also with swap. */
2775 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2780 /* Try using MVZ/MVS with an immediate value to load constants. */
2781 if (i
>= 0 && i
<= 65535)
2783 if (i
>= -32768 && i
<= 32767)
2787 /* Otherwise, use move.l */
2791 /* Return the cost of moving constant I into a data register. */
2794 const_int_cost (HOST_WIDE_INT i
)
2796 switch (m68k_const_method (i
))
2799 /* Constants between -128 and 127 are cheap due to moveq. */
2807 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2817 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2818 int opno ATTRIBUTE_UNUSED
,
2819 int *total
, bool speed ATTRIBUTE_UNUSED
)
2821 int code
= GET_CODE (x
);
2826 /* Constant zero is super cheap due to clr instruction. */
2827 if (x
== const0_rtx
)
2830 *total
= const_int_cost (INTVAL (x
));
2840 /* Make 0.0 cheaper than other floating constants to
2841 encourage creating tstsf and tstdf insns. */
2842 if (outer_code
== COMPARE
2843 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2849 /* These are vaguely right for a 68020. */
2850 /* The costs for long multiply have been adjusted to work properly
2851 in synth_mult on the 68020, relative to an average of the time
2852 for add and the time for shift, taking away a little more because
2853 sometimes move insns are needed. */
2854 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2859 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2860 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2862 : TARGET_COLDFIRE ? 3 : 13)
2867 : TUNE_68000_10 ? 5 \
2868 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2869 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2871 : TARGET_COLDFIRE ? 2 : 8)
2874 (TARGET_CF_HWDIV ? 11 \
2875 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2878 /* An lea costs about three times as much as a simple add. */
2880 && GET_CODE (XEXP (x
, 1)) == REG
2881 && GET_CODE (XEXP (x
, 0)) == MULT
2882 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2883 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2884 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2885 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2886 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2888 /* lea an@(dx:l:i),am */
2889 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2899 *total
= COSTS_N_INSNS(1);
2904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2906 if (INTVAL (XEXP (x
, 1)) < 16)
2907 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2909 /* We're using clrw + swap for these cases. */
2910 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2913 *total
= COSTS_N_INSNS (10); /* Worst case. */
2916 /* A shift by a big integer takes an extra instruction. */
2917 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2918 && (INTVAL (XEXP (x
, 1)) == 16))
2920 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2923 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2924 && !(INTVAL (XEXP (x
, 1)) > 0
2925 && INTVAL (XEXP (x
, 1)) <= 8))
2927 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2933 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2934 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2936 *total
= COSTS_N_INSNS (MULW_COST
);
2937 else if (mode
== QImode
|| mode
== HImode
)
2938 *total
= COSTS_N_INSNS (MULW_COST
);
2940 *total
= COSTS_N_INSNS (MULL_COST
);
2947 if (mode
== QImode
|| mode
== HImode
)
2948 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2949 else if (TARGET_CF_HWDIV
)
2950 *total
= COSTS_N_INSNS (18);
2952 *total
= COSTS_N_INSNS (43); /* div.l */
2956 if (outer_code
== COMPARE
)
2965 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2969 output_move_const_into_data_reg (rtx
*operands
)
2973 i
= INTVAL (operands
[1]);
2974 switch (m68k_const_method (i
))
2977 return "mvzw %1,%0";
2979 return "mvsw %1,%0";
2981 return "moveq %1,%0";
2984 operands
[1] = GEN_INT (i
^ 0xff);
2985 return "moveq %1,%0\n\tnot%.b %0";
2988 operands
[1] = GEN_INT (i
^ 0xffff);
2989 return "moveq %1,%0\n\tnot%.w %0";
2992 return "moveq #-128,%0\n\tneg%.w %0";
2997 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2998 return "moveq %1,%0\n\tswap %0";
3001 return "move%.l %1,%0";
3007 /* Return true if I can be handled by ISA B's mov3q instruction. */
3010 valid_mov3q_const (HOST_WIDE_INT i
)
3012 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3015 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3016 I is the value of OPERANDS[1]. */
3019 output_move_simode_const (rtx
*operands
)
3025 src
= INTVAL (operands
[1]);
3027 && (DATA_REG_P (dest
) || MEM_P (dest
))
3028 /* clr insns on 68000 read before writing. */
3029 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3030 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3032 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3033 return "mov3q%.l %1,%0";
3034 else if (src
== 0 && ADDRESS_REG_P (dest
))
3035 return "sub%.l %0,%0";
3036 else if (DATA_REG_P (dest
))
3037 return output_move_const_into_data_reg (operands
);
3038 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3040 if (valid_mov3q_const (src
))
3041 return "mov3q%.l %1,%0";
3042 return "move%.w %1,%0";
3044 else if (MEM_P (dest
)
3045 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3046 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3047 && IN_RANGE (src
, -0x8000, 0x7fff))
3049 if (valid_mov3q_const (src
))
3050 return "mov3q%.l %1,%-";
3053 return "move%.l %1,%0";
3057 output_move_simode (rtx
*operands
)
3059 if (GET_CODE (operands
[1]) == CONST_INT
)
3060 return output_move_simode_const (operands
);
3061 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3062 || GET_CODE (operands
[1]) == CONST
)
3063 && push_operand (operands
[0], SImode
))
3065 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3066 || GET_CODE (operands
[1]) == CONST
)
3067 && ADDRESS_REG_P (operands
[0]))
3068 return "lea %a1,%0";
3069 return "move%.l %1,%0";
3073 output_move_himode (rtx
*operands
)
3075 if (GET_CODE (operands
[1]) == CONST_INT
)
3077 if (operands
[1] == const0_rtx
3078 && (DATA_REG_P (operands
[0])
3079 || GET_CODE (operands
[0]) == MEM
)
3080 /* clr insns on 68000 read before writing. */
3081 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3082 || !(GET_CODE (operands
[0]) == MEM
3083 && MEM_VOLATILE_P (operands
[0]))))
3085 else if (operands
[1] == const0_rtx
3086 && ADDRESS_REG_P (operands
[0]))
3087 return "sub%.l %0,%0";
3088 else if (DATA_REG_P (operands
[0])
3089 && INTVAL (operands
[1]) < 128
3090 && INTVAL (operands
[1]) >= -128)
3091 return "moveq %1,%0";
3092 else if (INTVAL (operands
[1]) < 0x8000
3093 && INTVAL (operands
[1]) >= -0x8000)
3094 return "move%.w %1,%0";
3096 else if (CONSTANT_P (operands
[1]))
3097 return "move%.l %1,%0";
3098 return "move%.w %1,%0";
3102 output_move_qimode (rtx
*operands
)
3104 /* 68k family always modifies the stack pointer by at least 2, even for
3105 byte pushes. The 5200 (ColdFire) does not do this. */
3107 /* This case is generated by pushqi1 pattern now. */
3108 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3109 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3110 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3111 && ! ADDRESS_REG_P (operands
[1])
3112 && ! TARGET_COLDFIRE
));
3114 /* clr and st insns on 68000 read before writing. */
3115 if (!ADDRESS_REG_P (operands
[0])
3116 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3117 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3119 if (operands
[1] == const0_rtx
)
3121 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3122 && GET_CODE (operands
[1]) == CONST_INT
3123 && (INTVAL (operands
[1]) & 255) == 255)
3129 if (GET_CODE (operands
[1]) == CONST_INT
3130 && DATA_REG_P (operands
[0])
3131 && INTVAL (operands
[1]) < 128
3132 && INTVAL (operands
[1]) >= -128)
3133 return "moveq %1,%0";
3134 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3135 return "sub%.l %0,%0";
3136 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3137 return "move%.l %1,%0";
3138 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3139 from address registers. */
3140 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3141 return "move%.w %1,%0";
3142 return "move%.b %1,%0";
3146 output_move_stricthi (rtx
*operands
)
3148 if (operands
[1] == const0_rtx
3149 /* clr insns on 68000 read before writing. */
3150 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3151 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3153 return "move%.w %1,%0";
3157 output_move_strictqi (rtx
*operands
)
3159 if (operands
[1] == const0_rtx
3160 /* clr insns on 68000 read before writing. */
3161 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3162 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3164 return "move%.b %1,%0";
3167 /* Return the best assembler insn template
3168 for moving operands[1] into operands[0] as a fullword. */
3171 singlemove_string (rtx
*operands
)
3173 if (GET_CODE (operands
[1]) == CONST_INT
)
3174 return output_move_simode_const (operands
);
3175 return "move%.l %1,%0";
3179 /* Output assembler or rtl code to perform a doubleword move insn
3180 with operands OPERANDS.
3181 Pointers to 3 helper functions should be specified:
3182 HANDLE_REG_ADJUST to adjust a register by a small value,
3183 HANDLE_COMPADR to compute an address and
3184 HANDLE_MOVSI to move 4 bytes. */
3187 handle_move_double (rtx operands
[2],
3188 void (*handle_reg_adjust
) (rtx
, int),
3189 void (*handle_compadr
) (rtx
[2]),
3190 void (*handle_movsi
) (rtx
[2]))
3194 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3199 rtx addreg0
= 0, addreg1
= 0;
3200 int dest_overlapped_low
= 0;
3201 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3206 /* First classify both operands. */
3208 if (REG_P (operands
[0]))
3210 else if (offsettable_memref_p (operands
[0]))
3212 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3214 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3216 else if (GET_CODE (operands
[0]) == MEM
)
3221 if (REG_P (operands
[1]))
3223 else if (CONSTANT_P (operands
[1]))
3225 else if (offsettable_memref_p (operands
[1]))
3227 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3229 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3231 else if (GET_CODE (operands
[1]) == MEM
)
3236 /* Check for the cases that the operand constraints are not supposed
3237 to allow to happen. Generating code for these cases is
3239 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3241 /* If one operand is decrementing and one is incrementing
3242 decrement the former register explicitly
3243 and change that operand into ordinary indexing. */
3245 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3247 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3249 handle_reg_adjust (operands
[0], -size
);
3251 if (GET_MODE (operands
[1]) == XFmode
)
3252 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3253 else if (GET_MODE (operands
[0]) == DFmode
)
3254 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3256 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3259 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3261 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3263 handle_reg_adjust (operands
[1], -size
);
3265 if (GET_MODE (operands
[1]) == XFmode
)
3266 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3267 else if (GET_MODE (operands
[1]) == DFmode
)
3268 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3270 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3274 /* If an operand is an unoffsettable memory ref, find a register
3275 we can increment temporarily to make it refer to the second word. */
3277 if (optype0
== MEMOP
)
3278 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3280 if (optype1
== MEMOP
)
3281 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3283 /* Ok, we can do one word at a time.
3284 Normally we do the low-numbered word first,
3285 but if either operand is autodecrementing then we
3286 do the high-numbered word first.
3288 In either case, set up in LATEHALF the operands to use
3289 for the high-numbered word and in some cases alter the
3290 operands in OPERANDS to be suitable for the low-numbered word. */
3294 if (optype0
== REGOP
)
3296 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3297 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3299 else if (optype0
== OFFSOP
)
3301 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3302 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3306 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3307 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3310 if (optype1
== REGOP
)
3312 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3313 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3315 else if (optype1
== OFFSOP
)
3317 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3318 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3320 else if (optype1
== CNSTOP
)
3322 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3326 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3327 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3328 operands
[1] = GEN_INT (l
[0]);
3329 middlehalf
[1] = GEN_INT (l
[1]);
3330 latehalf
[1] = GEN_INT (l
[2]);
3334 /* No non-CONST_DOUBLE constant should ever appear
3336 gcc_assert (!CONSTANT_P (operands
[1]));
3341 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3342 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3346 /* size is not 12: */
3348 if (optype0
== REGOP
)
3349 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3350 else if (optype0
== OFFSOP
)
3351 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3353 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3355 if (optype1
== REGOP
)
3356 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3357 else if (optype1
== OFFSOP
)
3358 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3359 else if (optype1
== CNSTOP
)
3360 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3362 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3365 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3366 word first. We should use the adjusted operand 1 (which is N+4(REG))
3367 for the low word as well, to compensate for the first decrement of
3369 if (optype0
== PUSHOP
3370 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3371 operands
[1] = middlehalf
[1] = latehalf
[1];
3373 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3374 if the upper part of reg N does not appear in the MEM, arrange to
3375 emit the move late-half first. Otherwise, compute the MEM address
3376 into the upper part of N and use that as a pointer to the memory
3378 if (optype0
== REGOP
3379 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3381 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3383 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3384 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3386 /* If both halves of dest are used in the src memory address,
3387 compute the address into latehalf of dest.
3388 Note that this can't happen if the dest is two data regs. */
3390 xops
[0] = latehalf
[0];
3391 xops
[1] = XEXP (operands
[1], 0);
3393 handle_compadr (xops
);
3394 if (GET_MODE (operands
[1]) == XFmode
)
3396 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3397 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3398 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3402 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3403 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3407 && reg_overlap_mentioned_p (middlehalf
[0],
3408 XEXP (operands
[1], 0)))
3410 /* Check for two regs used by both source and dest.
3411 Note that this can't happen if the dest is all data regs.
3412 It can happen if the dest is d6, d7, a0.
3413 But in that case, latehalf is an addr reg, so
3414 the code at compadr does ok. */
3416 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3417 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3420 /* JRV says this can't happen: */
3421 gcc_assert (!addreg0
&& !addreg1
);
3423 /* Only the middle reg conflicts; simply put it last. */
3424 handle_movsi (operands
);
3425 handle_movsi (latehalf
);
3426 handle_movsi (middlehalf
);
3430 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3431 /* If the low half of dest is mentioned in the source memory
3432 address, the arrange to emit the move late half first. */
3433 dest_overlapped_low
= 1;
3436 /* If one or both operands autodecrementing,
3437 do the two words, high-numbered first. */
3439 /* Likewise, the first move would clobber the source of the second one,
3440 do them in the other order. This happens only for registers;
3441 such overlap can't happen in memory unless the user explicitly
3442 sets it up, and that is an undefined circumstance. */
3444 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3445 || (optype0
== REGOP
&& optype1
== REGOP
3446 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3447 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3448 || dest_overlapped_low
)
3450 /* Make any unoffsettable addresses point at high-numbered word. */
3452 handle_reg_adjust (addreg0
, size
- 4);
3454 handle_reg_adjust (addreg1
, size
- 4);
3457 handle_movsi (latehalf
);
3459 /* Undo the adds we just did. */
3461 handle_reg_adjust (addreg0
, -4);
3463 handle_reg_adjust (addreg1
, -4);
3467 handle_movsi (middlehalf
);
3470 handle_reg_adjust (addreg0
, -4);
3472 handle_reg_adjust (addreg1
, -4);
3475 /* Do low-numbered word. */
3477 handle_movsi (operands
);
3481 /* Normal case: do the two words, low-numbered first. */
3483 handle_movsi (operands
);
3485 /* Do the middle one of the three words for long double */
3489 handle_reg_adjust (addreg0
, 4);
3491 handle_reg_adjust (addreg1
, 4);
3493 handle_movsi (middlehalf
);
3496 /* Make any unoffsettable addresses point at high-numbered word. */
3498 handle_reg_adjust (addreg0
, 4);
3500 handle_reg_adjust (addreg1
, 4);
3503 handle_movsi (latehalf
);
3505 /* Undo the adds we just did. */
3507 handle_reg_adjust (addreg0
, -(size
- 4));
3509 handle_reg_adjust (addreg1
, -(size
- 4));
3514 /* Output assembler code to adjust REG by N. */
3516 output_reg_adjust (rtx reg
, int n
)
3520 gcc_assert (GET_MODE (reg
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3525 s
= "add%.l #12,%0";
3529 s
= "addq%.l #8,%0";
3533 s
= "addq%.l #4,%0";
3537 s
= "sub%.l #12,%0";
3541 s
= "subq%.l #8,%0";
3545 s
= "subq%.l #4,%0";
3553 output_asm_insn (s
, ®
);
3556 /* Emit rtl code to adjust REG by N. */
3558 emit_reg_adjust (rtx reg1
, int n
)
3562 gcc_assert (GET_MODE (reg1
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3564 reg1
= copy_rtx (reg1
);
3565 reg2
= copy_rtx (reg1
);
3568 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3570 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3575 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3577 output_compadr (rtx operands
[2])
3579 output_asm_insn ("lea %a1,%0", operands
);
3582 /* Output the best assembler insn for moving operands[1] into operands[0]
3585 output_movsi (rtx operands
[2])
3587 output_asm_insn (singlemove_string (operands
), operands
);
3590 /* Copy OP and change its mode to MODE. */
3592 copy_operand (rtx op
, machine_mode mode
)
3594 /* ??? This looks really ugly. There must be a better way
3595 to change a mode on the operand. */
3596 if (GET_MODE (op
) != VOIDmode
)
3599 op
= gen_rtx_REG (mode
, REGNO (op
));
3603 PUT_MODE (op
, mode
);
3610 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3612 emit_movsi (rtx operands
[2])
3614 operands
[0] = copy_operand (operands
[0], SImode
);
3615 operands
[1] = copy_operand (operands
[1], SImode
);
3617 emit_insn (gen_movsi (operands
[0], operands
[1]));
3620 /* Output assembler code to perform a doubleword move insn
3621 with operands OPERANDS. */
3623 output_move_double (rtx
*operands
)
3625 handle_move_double (operands
,
3626 output_reg_adjust
, output_compadr
, output_movsi
);
3631 /* Output rtl code to perform a doubleword move insn
3632 with operands OPERANDS. */
3634 m68k_emit_move_double (rtx operands
[2])
3636 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3639 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3640 new rtx with the correct mode. */
3643 force_mode (machine_mode mode
, rtx orig
)
3645 if (mode
== GET_MODE (orig
))
3648 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3651 return gen_rtx_REG (mode
, REGNO (orig
));
3655 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3657 return reg_renumber
&& FP_REG_P (op
);
3660 /* Emit insns to move operands[1] into operands[0].
3662 Return 1 if we have written out everything that needs to be done to
3663 do the move. Otherwise, return 0 and the caller will emit the move
3666 Note SCRATCH_REG may not be in the proper mode depending on how it
3667 will be used. This routine is responsible for creating a new copy
3668 of SCRATCH_REG in the proper mode. */
3671 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3673 register rtx operand0
= operands
[0];
3674 register rtx operand1
= operands
[1];
3678 && reload_in_progress
&& GET_CODE (operand0
) == REG
3679 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3680 operand0
= reg_equiv_mem (REGNO (operand0
));
3681 else if (scratch_reg
3682 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3683 && GET_CODE (SUBREG_REG (operand0
)) == REG
3684 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3686 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3687 the code which tracks sets/uses for delete_output_reload. */
3688 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3689 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3690 SUBREG_BYTE (operand0
));
3691 operand0
= alter_subreg (&temp
, true);
3695 && reload_in_progress
&& GET_CODE (operand1
) == REG
3696 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3697 operand1
= reg_equiv_mem (REGNO (operand1
));
3698 else if (scratch_reg
3699 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3700 && GET_CODE (SUBREG_REG (operand1
)) == REG
3701 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3703 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3704 the code which tracks sets/uses for delete_output_reload. */
3705 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3706 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3707 SUBREG_BYTE (operand1
));
3708 operand1
= alter_subreg (&temp
, true);
3711 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3712 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3713 != XEXP (operand0
, 0)))
3714 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3715 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3716 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3717 != XEXP (operand1
, 0)))
3718 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3720 /* Handle secondary reloads for loads/stores of FP registers where
3721 the address is symbolic by using the scratch register */
3722 if (fp_reg_operand (operand0
, mode
)
3723 && ((GET_CODE (operand1
) == MEM
3724 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3725 || ((GET_CODE (operand1
) == SUBREG
3726 && GET_CODE (XEXP (operand1
, 0)) == MEM
3727 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3730 if (GET_CODE (operand1
) == SUBREG
)
3731 operand1
= XEXP (operand1
, 0);
3733 /* SCRATCH_REG will hold an address. We want
3734 it in SImode regardless of what mode it was originally given
3736 scratch_reg
= force_mode (SImode
, scratch_reg
);
3738 /* D might not fit in 14 bits either; for such cases load D into
3740 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3742 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3743 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3745 XEXP (XEXP (operand1
, 0), 0),
3749 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3750 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3753 else if (fp_reg_operand (operand1
, mode
)
3754 && ((GET_CODE (operand0
) == MEM
3755 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3756 || ((GET_CODE (operand0
) == SUBREG
)
3757 && GET_CODE (XEXP (operand0
, 0)) == MEM
3758 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3761 if (GET_CODE (operand0
) == SUBREG
)
3762 operand0
= XEXP (operand0
, 0);
3764 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3765 it in SIMODE regardless of what mode it was originally given
3767 scratch_reg
= force_mode (SImode
, scratch_reg
);
3769 /* D might not fit in 14 bits either; for such cases load D into
3771 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3773 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3774 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3777 XEXP (XEXP (operand0
, 0),
3782 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3783 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3786 /* Handle secondary reloads for loads of FP registers from constant
3787 expressions by forcing the constant into memory.
3789 use scratch_reg to hold the address of the memory location.
3791 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3792 NO_REGS when presented with a const_int and an register class
3793 containing only FP registers. Doing so unfortunately creates
3794 more problems than it solves. Fix this for 2.5. */
3795 else if (fp_reg_operand (operand0
, mode
)
3796 && CONSTANT_P (operand1
)
3801 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3802 it in SIMODE regardless of what mode it was originally given
3804 scratch_reg
= force_mode (SImode
, scratch_reg
);
3806 /* Force the constant into memory and put the address of the
3807 memory location into scratch_reg. */
3808 xoperands
[0] = scratch_reg
;
3809 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3810 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3812 /* Now load the destination register. */
3813 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3817 /* Now have insn-emit do whatever it normally does. */
3821 /* Split one or more DImode RTL references into pairs of SImode
3822 references. The RTL can be REG, offsettable MEM, integer constant, or
3823 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3824 split and "num" is its length. lo_half and hi_half are output arrays
3825 that parallel "operands". */
3828 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3832 rtx op
= operands
[num
];
3834 /* simplify_subreg refuses to split volatile memory addresses,
3835 but we still have to handle it. */
3836 if (GET_CODE (op
) == MEM
)
3838 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3839 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3843 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3844 GET_MODE (op
) == VOIDmode
3845 ? DImode
: GET_MODE (op
), 4);
3846 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3847 GET_MODE (op
) == VOIDmode
3848 ? DImode
: GET_MODE (op
), 0);
3853 /* Split X into a base and a constant offset, storing them in *BASE
3854 and *OFFSET respectively. */
3857 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3860 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3862 *offset
+= INTVAL (XEXP (x
, 1));
3868 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3869 instruction. STORE_P says whether the move is a load or store.
3871 If the instruction uses post-increment or pre-decrement addressing,
3872 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3873 adjustment. This adjustment will be made by the first element of
3874 PARALLEL, with the loads or stores starting at element 1. If the
3875 instruction does not use post-increment or pre-decrement addressing,
3876 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3877 start at element 0. */
3880 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3881 HOST_WIDE_INT automod_offset
, bool store_p
)
3883 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3884 HOST_WIDE_INT offset
, mem_offset
;
3886 enum reg_class rclass
;
3888 len
= XVECLEN (pattern
, 0);
3889 first
= (automod_base
!= NULL
);
3893 /* Stores must be pre-decrement and loads must be post-increment. */
3894 if (store_p
!= (automod_offset
< 0))
3897 /* Work out the base and offset for lowest memory location. */
3898 base
= automod_base
;
3899 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3903 /* Allow any valid base and offset in the first access. */
3910 for (i
= first
; i
< len
; i
++)
3912 /* We need a plain SET. */
3913 set
= XVECEXP (pattern
, 0, i
);
3914 if (GET_CODE (set
) != SET
)
3917 /* Check that we have a memory location... */
3918 mem
= XEXP (set
, !store_p
);
3919 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3922 /* ...with the right address. */
3925 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3926 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3927 There are no mode restrictions for 680x0 besides the
3928 automodification rules enforced above. */
3930 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3935 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3936 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3940 /* Check that we have a register of the required mode and class. */
3941 reg
= XEXP (set
, store_p
);
3943 || !HARD_REGISTER_P (reg
)
3944 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3949 /* The register must belong to RCLASS and have a higher number
3950 than the register in the previous SET. */
3951 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3952 || REGNO (last_reg
) >= REGNO (reg
))
3957 /* Work out which register class we need. */
3958 if (INT_REGNO_P (REGNO (reg
)))
3959 rclass
= GENERAL_REGS
;
3960 else if (FP_REGNO_P (REGNO (reg
)))
3967 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3970 /* If we have an automodification, check whether the final offset is OK. */
3971 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3974 /* Reject unprofitable cases. */
3975 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3981 /* Return the assembly code template for a movem or fmovem instruction
3982 whose pattern is given by PATTERN. Store the template's operands
3985 If the instruction uses post-increment or pre-decrement addressing,
3986 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3987 is true if this is a store instruction. */
3990 m68k_output_movem (rtx
*operands
, rtx pattern
,
3991 HOST_WIDE_INT automod_offset
, bool store_p
)
3996 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3998 first
= (automod_offset
!= 0);
3999 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4001 /* When using movem with pre-decrement addressing, register X + D0_REG
4002 is controlled by bit 15 - X. For all other addressing modes,
4003 register X + D0_REG is controlled by bit X. Confusingly, the
4004 register mask for fmovem is in the opposite order to that for
4008 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4009 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4010 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4011 if (automod_offset
< 0)
4013 if (FP_REGNO_P (regno
))
4014 mask
|= 1 << (regno
- FP0_REG
);
4016 mask
|= 1 << (15 - (regno
- D0_REG
));
4020 if (FP_REGNO_P (regno
))
4021 mask
|= 1 << (7 - (regno
- FP0_REG
));
4023 mask
|= 1 << (regno
- D0_REG
);
4028 if (automod_offset
== 0)
4029 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4030 else if (automod_offset
< 0)
4031 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4033 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4034 operands
[1] = GEN_INT (mask
);
4035 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4038 return "fmovem %1,%a0";
4040 return "fmovem %a0,%1";
4045 return "movem%.l %1,%a0";
4047 return "movem%.l %a0,%1";
4051 /* Return a REG that occurs in ADDR with coefficient 1.
4052 ADDR can be effectively incremented by incrementing REG. */
4055 find_addr_reg (rtx addr
)
4057 while (GET_CODE (addr
) == PLUS
)
4059 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4060 addr
= XEXP (addr
, 0);
4061 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4062 addr
= XEXP (addr
, 1);
4063 else if (CONSTANT_P (XEXP (addr
, 0)))
4064 addr
= XEXP (addr
, 1);
4065 else if (CONSTANT_P (XEXP (addr
, 1)))
4066 addr
= XEXP (addr
, 0);
4070 gcc_assert (GET_CODE (addr
) == REG
);
4074 /* Output assembler code to perform a 32-bit 3-operand add. */
4077 output_addsi3 (rtx
*operands
)
4079 if (! operands_match_p (operands
[0], operands
[1]))
4081 if (!ADDRESS_REG_P (operands
[1]))
4083 rtx tmp
= operands
[1];
4085 operands
[1] = operands
[2];
4089 /* These insns can result from reloads to access
4090 stack slots over 64k from the frame pointer. */
4091 if (GET_CODE (operands
[2]) == CONST_INT
4092 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4093 return "move%.l %2,%0\n\tadd%.l %1,%0";
4094 if (GET_CODE (operands
[2]) == REG
)
4095 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4096 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4098 if (GET_CODE (operands
[2]) == CONST_INT
)
4100 if (INTVAL (operands
[2]) > 0
4101 && INTVAL (operands
[2]) <= 8)
4102 return "addq%.l %2,%0";
4103 if (INTVAL (operands
[2]) < 0
4104 && INTVAL (operands
[2]) >= -8)
4106 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4107 return "subq%.l %2,%0";
4109 /* On the CPU32 it is faster to use two addql instructions to
4110 add a small integer (8 < N <= 16) to a register.
4111 Likewise for subql. */
4112 if (TUNE_CPU32
&& REG_P (operands
[0]))
4114 if (INTVAL (operands
[2]) > 8
4115 && INTVAL (operands
[2]) <= 16)
4117 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4118 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4120 if (INTVAL (operands
[2]) < -8
4121 && INTVAL (operands
[2]) >= -16)
4123 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4124 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4127 if (ADDRESS_REG_P (operands
[0])
4128 && INTVAL (operands
[2]) >= -0x8000
4129 && INTVAL (operands
[2]) < 0x8000)
4132 return "add%.w %2,%0";
4134 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4137 return "add%.l %2,%0";
4140 /* Store in cc_status the expressions that the condition codes will
4141 describe after execution of an instruction whose pattern is EXP.
4142 Do not alter them if the instruction would not alter the cc's. */
4144 /* On the 68000, all the insns to store in an address register fail to
4145 set the cc's. However, in some cases these instructions can make it
4146 possibly invalid to use the saved cc's. In those cases we clear out
4147 some or all of the saved cc's so they won't be used. */
4150 notice_update_cc (rtx exp
, rtx insn
)
4152 if (GET_CODE (exp
) == SET
)
4154 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4156 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4158 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4159 cc_status
.value1
= 0;
4160 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4161 cc_status
.value2
= 0;
4163 /* fmoves to memory or data registers do not set the condition
4164 codes. Normal moves _do_ set the condition codes, but not in
4165 a way that is appropriate for comparison with 0, because -0.0
4166 would be treated as a negative nonzero number. Note that it
4167 isn't appropriate to conditionalize this restriction on
4168 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4169 we care about the difference between -0.0 and +0.0. */
4170 else if (!FP_REG_P (SET_DEST (exp
))
4171 && SET_DEST (exp
) != cc0_rtx
4172 && (FP_REG_P (SET_SRC (exp
))
4173 || GET_CODE (SET_SRC (exp
)) == FIX
4174 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4176 /* A pair of move insns doesn't produce a useful overall cc. */
4177 else if (!FP_REG_P (SET_DEST (exp
))
4178 && !FP_REG_P (SET_SRC (exp
))
4179 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4180 && (GET_CODE (SET_SRC (exp
)) == REG
4181 || GET_CODE (SET_SRC (exp
)) == MEM
4182 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4184 else if (SET_DEST (exp
) != pc_rtx
)
4186 cc_status
.flags
= 0;
4187 cc_status
.value1
= SET_DEST (exp
);
4188 cc_status
.value2
= SET_SRC (exp
);
4191 else if (GET_CODE (exp
) == PARALLEL
4192 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4194 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4195 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4197 if (ADDRESS_REG_P (dest
))
4199 else if (dest
!= pc_rtx
)
4201 cc_status
.flags
= 0;
4202 cc_status
.value1
= dest
;
4203 cc_status
.value2
= src
;
4208 if (cc_status
.value2
!= 0
4209 && ADDRESS_REG_P (cc_status
.value2
)
4210 && GET_MODE (cc_status
.value2
) == QImode
)
4212 if (cc_status
.value2
!= 0)
4213 switch (GET_CODE (cc_status
.value2
))
4215 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4216 case ROTATE
: case ROTATERT
:
4217 /* These instructions always clear the overflow bit, and set
4218 the carry to the bit shifted out. */
4219 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4222 case PLUS
: case MINUS
: case MULT
:
4223 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4224 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4225 cc_status
.flags
|= CC_NO_OVERFLOW
;
4228 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4229 ends with a move insn moving r2 in r2's mode.
4230 Thus, the cc's are set for r2.
4231 This can set N bit spuriously. */
4232 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4237 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4239 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4240 cc_status
.value2
= 0;
4241 /* Check for PRE_DEC in dest modifying a register used in src. */
4242 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4243 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4245 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4247 cc_status
.value2
= 0;
4248 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4249 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4250 cc_status
.flags
= CC_IN_68881
;
4251 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4252 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4254 cc_status
.flags
= CC_IN_68881
;
4255 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4256 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4257 cc_status
.flags
|= CC_REVERSED
;
4262 output_move_const_double (rtx
*operands
)
4264 int code
= standard_68881_constant_p (operands
[1]);
4268 static char buf
[40];
4270 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4273 return "fmove%.d %1,%0";
4277 output_move_const_single (rtx
*operands
)
4279 int code
= standard_68881_constant_p (operands
[1]);
4283 static char buf
[40];
4285 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4288 return "fmove%.s %f1,%0";
4291 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4292 from the "fmovecr" instruction.
4293 The value, anded with 0xff, gives the code to use in fmovecr
4294 to get the desired constant. */
4296 /* This code has been fixed for cross-compilation. */
4298 static int inited_68881_table
= 0;
4300 static const char *const strings_68881
[7] = {
4310 static const int codes_68881
[7] = {
4320 REAL_VALUE_TYPE values_68881
[7];
4322 /* Set up values_68881 array by converting the decimal values
4323 strings_68881 to binary. */
4326 init_68881_table (void)
4333 for (i
= 0; i
< 7; i
++)
4337 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4338 values_68881
[i
] = r
;
4340 inited_68881_table
= 1;
4344 standard_68881_constant_p (rtx x
)
4346 const REAL_VALUE_TYPE
*r
;
4349 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4350 used at all on those chips. */
4354 if (! inited_68881_table
)
4355 init_68881_table ();
4357 r
= CONST_DOUBLE_REAL_VALUE (x
);
4359 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4360 for (i
= 0; i
< 6; i
++)
4362 if (real_identical (r
, &values_68881
[i
]))
4363 return (codes_68881
[i
]);
4366 if (GET_MODE (x
) == SFmode
)
4369 if (real_equal (r
, &values_68881
[6]))
4370 return (codes_68881
[6]);
4372 /* larger powers of ten in the constants ram are not used
4373 because they are not equal to a `double' C constant. */
4377 /* If X is a floating-point constant, return the logarithm of X base 2,
4378 or 0 if X is not a power of 2. */
4381 floating_exact_log2 (rtx x
)
4383 const REAL_VALUE_TYPE
*r
;
4387 r
= CONST_DOUBLE_REAL_VALUE (x
);
4389 if (real_less (r
, &dconst1
))
4392 exp
= real_exponent (r
);
4393 real_2expN (&r1
, exp
, DFmode
);
4394 if (real_equal (&r1
, r
))
4400 /* A C compound statement to output to stdio stream STREAM the
4401 assembler syntax for an instruction operand X. X is an RTL
4404 CODE is a value that can be used to specify one of several ways
4405 of printing the operand. It is used when identical operands
4406 must be printed differently depending on the context. CODE
4407 comes from the `%' specification that was used to request
4408 printing of the operand. If the specification was just `%DIGIT'
4409 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4410 is the ASCII code for LTR.
4412 If X is a register, this macro should print the register's name.
4413 The names can be found in an array `reg_names' whose type is
4414 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4416 When the machine description has a specification `%PUNCT' (a `%'
4417 followed by a punctuation character), this macro is called with
4418 a null pointer for X and the punctuation character for CODE.
4420 The m68k specific codes are:
4422 '.' for dot needed in Motorola-style opcode names.
4423 '-' for an operand pushing on the stack:
4424 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4425 '+' for an operand pushing on the stack:
4426 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4427 '@' for a reference to the top word on the stack:
4428 sp@, (sp) or (%sp) depending on the style of syntax.
4429 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4430 but & in SGS syntax).
4431 '!' for the cc register (used in an `and to cc' insn).
4432 '$' for the letter `s' in an op code, but only on the 68040.
4433 '&' for the letter `d' in an op code, but only on the 68040.
4434 '/' for register prefix needed by longlong.h.
4435 '?' for m68k_library_id_string
4437 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4438 'd' to force memory addressing to be absolute, not relative.
4439 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4440 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4441 or print pair of registers as rx:ry.
4442 'p' print an address with @PLTPC attached, but only if the operand
4443 is not locally-bound. */
4446 print_operand (FILE *file
, rtx op
, int letter
)
4449 m68k_adjust_decorated_operand (op
);
4454 fprintf (file
, ".");
4456 else if (letter
== '#')
4457 asm_fprintf (file
, "%I");
4458 else if (letter
== '-')
4459 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4460 else if (letter
== '+')
4461 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4462 else if (letter
== '@')
4463 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4464 else if (letter
== '!')
4465 asm_fprintf (file
, "%Rfpcr");
4466 else if (letter
== '$')
4469 fprintf (file
, "s");
4471 else if (letter
== '&')
4474 fprintf (file
, "d");
4476 else if (letter
== '/')
4477 asm_fprintf (file
, "%R");
4478 else if (letter
== '?')
4479 asm_fprintf (file
, m68k_library_id_string
);
4480 else if (letter
== 'p')
4482 output_addr_const (file
, op
);
4483 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4484 fprintf (file
, "@PLTPC");
4486 else if (GET_CODE (op
) == REG
)
4489 /* Print out the second register name of a register pair.
4490 I.e., R (6) => 7. */
4491 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4493 fputs (M68K_REGNAME(REGNO (op
)), file
);
4495 else if (GET_CODE (op
) == MEM
)
4497 output_address (GET_MODE (op
), XEXP (op
, 0));
4498 if (letter
== 'd' && ! TARGET_68020
4499 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4500 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4501 && INTVAL (XEXP (op
, 0)) < 0x8000
4502 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4503 fprintf (file
, MOTOROLA
? ".l" : ":l");
4505 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4508 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4509 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4511 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4514 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4515 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4516 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4518 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4521 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4522 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4526 /* Use `print_operand_address' instead of `output_addr_const'
4527 to ensure that we print relevant PIC stuff. */
4528 asm_fprintf (file
, "%I");
4530 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4531 print_operand_address (file
, op
);
4533 output_addr_const (file
, op
);
4537 /* Return string for TLS relocation RELOC. */
4540 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4542 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4543 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4550 if (flag_pic
== 1 && TARGET_68020
)
4592 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4595 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4597 if (GET_CODE (x
) == UNSPEC
)
4599 switch (XINT (x
, 1))
4601 case UNSPEC_RELOC16
:
4602 case UNSPEC_RELOC32
:
4603 output_addr_const (file
, XVECEXP (x
, 0, 0));
4604 fputs (m68k_get_reloc_decoration
4605 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4616 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4619 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4621 gcc_assert (size
== 4);
4622 fputs ("\t.long\t", file
);
4623 output_addr_const (file
, x
);
4624 fputs ("@TLSLDO+0x8000", file
);
4627 /* In the name of slightly smaller debug output, and to cater to
4628 general assembler lossage, recognize various UNSPEC sequences
4629 and turn them back into a direct symbol reference. */
4632 m68k_delegitimize_address (rtx orig_x
)
4635 struct m68k_address addr
;
4638 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4643 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4646 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4647 || addr
.offset
== NULL_RTX
4648 || GET_CODE (addr
.offset
) != CONST
)
4651 unspec
= XEXP (addr
.offset
, 0);
4652 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4653 unspec
= XEXP (unspec
, 0);
4654 if (GET_CODE (unspec
) != UNSPEC
4655 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4656 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4658 x
= XVECEXP (unspec
, 0, 0);
4659 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4660 if (unspec
!= XEXP (addr
.offset
, 0))
4661 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4664 rtx idx
= addr
.index
;
4665 if (addr
.scale
!= 1)
4666 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4667 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4670 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4672 x
= replace_equiv_address_nv (orig_x
, x
);
4677 /* A C compound statement to output to stdio stream STREAM the
4678 assembler syntax for an instruction operand that is a memory
4679 reference whose address is ADDR. ADDR is an RTL expression.
4681 Note that this contains a kludge that knows that the only reason
4682 we have an address (plus (label_ref...) (reg...)) when not generating
4683 PIC code is in the insn before a tablejump, and we know that m68k.md
4684 generates a label LInnn: on such an insn.
4686 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4687 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4689 This routine is responsible for distinguishing between -fpic and -fPIC
4690 style relocations in an address. When generating -fpic code the
4691 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4692 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4695 print_operand_address (FILE *file
, rtx addr
)
4697 struct m68k_address address
;
4699 m68k_adjust_decorated_operand (addr
);
4701 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4704 if (address
.code
== PRE_DEC
)
4705 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4706 M68K_REGNAME (REGNO (address
.base
)));
4707 else if (address
.code
== POST_INC
)
4708 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4709 M68K_REGNAME (REGNO (address
.base
)));
4710 else if (!address
.base
&& !address
.index
)
4712 /* A constant address. */
4713 gcc_assert (address
.offset
== addr
);
4714 if (GET_CODE (addr
) == CONST_INT
)
4716 /* (xxx).w or (xxx).l. */
4717 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4718 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4720 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4722 else if (TARGET_PCREL
)
4724 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4726 output_addr_const (file
, addr
);
4727 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4731 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4732 name ends in `.<letter>', as the last 2 characters can be
4733 mistaken as a size suffix. Put the name in parentheses. */
4734 if (GET_CODE (addr
) == SYMBOL_REF
4735 && strlen (XSTR (addr
, 0)) > 2
4736 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4739 output_addr_const (file
, addr
);
4743 output_addr_const (file
, addr
);
4750 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4751 label being accessed, otherwise it is -1. */
4752 labelno
= (address
.offset
4754 && GET_CODE (address
.offset
) == LABEL_REF
4755 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4759 /* Print the "offset(base" component. */
4761 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4765 output_addr_const (file
, address
.offset
);
4769 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4771 /* Print the ",index" component, if any. */
4776 fprintf (file
, "%s.%c",
4777 M68K_REGNAME (REGNO (address
.index
)),
4778 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4779 if (address
.scale
!= 1)
4780 fprintf (file
, "*%d", address
.scale
);
4784 else /* !MOTOROLA */
4786 if (!address
.offset
&& !address
.index
)
4787 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4790 /* Print the "base@(offset" component. */
4792 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4796 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4797 fprintf (file
, "@(");
4799 output_addr_const (file
, address
.offset
);
4801 /* Print the ",index" component, if any. */
4804 fprintf (file
, ",%s:%c",
4805 M68K_REGNAME (REGNO (address
.index
)),
4806 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4807 if (address
.scale
!= 1)
4808 fprintf (file
, ":%d", address
.scale
);
4816 /* Check for cases where a clr insns can be omitted from code using
4817 strict_low_part sets. For example, the second clrl here is not needed:
4818 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4820 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4821 insn we are checking for redundancy. TARGET is the register set by the
4825 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4828 rtx_insn
*p
= first_insn
;
4830 while ((p
= PREV_INSN (p
)))
4832 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4838 /* If it isn't an insn, then give up. */
4842 if (reg_set_p (target
, p
))
4844 rtx set
= single_set (p
);
4847 /* If it isn't an easy to recognize insn, then give up. */
4851 dest
= SET_DEST (set
);
4853 /* If this sets the entire target register to zero, then our
4854 first_insn is redundant. */
4855 if (rtx_equal_p (dest
, target
)
4856 && SET_SRC (set
) == const0_rtx
)
4858 else if (GET_CODE (dest
) == STRICT_LOW_PART
4859 && GET_CODE (XEXP (dest
, 0)) == REG
4860 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4861 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4862 <= GET_MODE_SIZE (mode
)))
4863 /* This is a strict low part set which modifies less than
4864 we are using, so it is safe. */
4874 /* Operand predicates for implementing asymmetric pc-relative addressing
4875 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4876 when used as a source operand, but not as a destination operand.
4878 We model this by restricting the meaning of the basic predicates
4879 (general_operand, memory_operand, etc) to forbid the use of this
4880 addressing mode, and then define the following predicates that permit
4881 this addressing mode. These predicates can then be used for the
4882 source operands of the appropriate instructions.
4884 n.b. While it is theoretically possible to change all machine patterns
4885 to use this addressing more where permitted by the architecture,
4886 it has only been implemented for "common" cases: SImode, HImode, and
4887 QImode operands, and only for the principle operations that would
4888 require this addressing mode: data movement and simple integer operations.
4890 In parallel with these new predicates, two new constraint letters
4891 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4892 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4893 In the pcrel case 's' is only valid in combination with 'a' registers.
4894 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4895 of how these constraints are used.
4897 The use of these predicates is strictly optional, though patterns that
4898 don't will cause an extra reload register to be allocated where one
4901 lea (abc:w,%pc),%a0 ; need to reload address
4902 moveq &1,%d1 ; since write to pc-relative space
4903 movel %d1,%a0@ ; is not allowed
4905 lea (abc:w,%pc),%a1 ; no need to reload address here
4906 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4908 For more info, consult tiemann@cygnus.com.
4911 All of the ugliness with predicates and constraints is due to the
4912 simple fact that the m68k does not allow a pc-relative addressing
4913 mode as a destination. gcc does not distinguish between source and
4914 destination addresses. Hence, if we claim that pc-relative address
4915 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4916 end up with invalid code. To get around this problem, we left
4917 pc-relative modes as invalid addresses, and then added special
4918 predicates and constraints to accept them.
4920 A cleaner way to handle this is to modify gcc to distinguish
4921 between source and destination addresses. We can then say that
4922 pc-relative is a valid source address but not a valid destination
4923 address, and hopefully avoid a lot of the predicate and constraint
4924 hackery. Unfortunately, this would be a pretty big change. It would
4925 be a useful change for a number of ports, but there aren't any current
4926 plans to undertake this.
4928 ***************************************************************************/
4932 output_andsi3 (rtx
*operands
)
4935 if (GET_CODE (operands
[2]) == CONST_INT
4936 && (INTVAL (operands
[2]) | 0xffff) == -1
4937 && (DATA_REG_P (operands
[0])
4938 || offsettable_memref_p (operands
[0]))
4939 && !TARGET_COLDFIRE
)
4941 if (GET_CODE (operands
[0]) != REG
)
4942 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4943 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4944 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4946 if (operands
[2] == const0_rtx
)
4948 return "and%.w %2,%0";
4950 if (GET_CODE (operands
[2]) == CONST_INT
4951 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4952 && (DATA_REG_P (operands
[0])
4953 || offsettable_memref_p (operands
[0])))
4955 if (DATA_REG_P (operands
[0]))
4956 operands
[1] = GEN_INT (logval
);
4959 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4960 operands
[1] = GEN_INT (logval
% 8);
4962 /* This does not set condition codes in a standard way. */
4964 return "bclr %1,%0";
4966 return "and%.l %2,%0";
4970 output_iorsi3 (rtx
*operands
)
4972 register int logval
;
4973 if (GET_CODE (operands
[2]) == CONST_INT
4974 && INTVAL (operands
[2]) >> 16 == 0
4975 && (DATA_REG_P (operands
[0])
4976 || offsettable_memref_p (operands
[0]))
4977 && !TARGET_COLDFIRE
)
4979 if (GET_CODE (operands
[0]) != REG
)
4980 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4981 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4983 if (INTVAL (operands
[2]) == 0xffff)
4984 return "mov%.w %2,%0";
4985 return "or%.w %2,%0";
4987 if (GET_CODE (operands
[2]) == CONST_INT
4988 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4989 && (DATA_REG_P (operands
[0])
4990 || offsettable_memref_p (operands
[0])))
4992 if (DATA_REG_P (operands
[0]))
4993 operands
[1] = GEN_INT (logval
);
4996 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4997 operands
[1] = GEN_INT (logval
% 8);
5000 return "bset %1,%0";
5002 return "or%.l %2,%0";
5006 output_xorsi3 (rtx
*operands
)
5008 register int logval
;
5009 if (GET_CODE (operands
[2]) == CONST_INT
5010 && INTVAL (operands
[2]) >> 16 == 0
5011 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5012 && !TARGET_COLDFIRE
)
5014 if (! DATA_REG_P (operands
[0]))
5015 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5016 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5018 if (INTVAL (operands
[2]) == 0xffff)
5020 return "eor%.w %2,%0";
5022 if (GET_CODE (operands
[2]) == CONST_INT
5023 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5024 && (DATA_REG_P (operands
[0])
5025 || offsettable_memref_p (operands
[0])))
5027 if (DATA_REG_P (operands
[0]))
5028 operands
[1] = GEN_INT (logval
);
5031 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5032 operands
[1] = GEN_INT (logval
% 8);
5035 return "bchg %1,%0";
5037 return "eor%.l %2,%0";
5040 /* Return the instruction that should be used for a call to address X,
5041 which is known to be in operand 0. */
5046 if (symbolic_operand (x
, VOIDmode
))
5047 return m68k_symbolic_call
;
5052 /* Likewise sibling calls. */
5055 output_sibcall (rtx x
)
5057 if (symbolic_operand (x
, VOIDmode
))
5058 return m68k_symbolic_jump
;
5064 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5065 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5068 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk
));
5069 rtx this_slot
, offset
, addr
, mem
, tmp
;
5072 /* Avoid clobbering the struct value reg by using the
5073 static chain reg as a temporary. */
5074 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5076 /* Pretend to be a post-reload pass while generating rtl. */
5077 reload_completed
= 1;
5079 /* The "this" pointer is stored at 4(%sp). */
5080 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5081 stack_pointer_rtx
, 4));
5083 /* Add DELTA to THIS. */
5086 /* Make the offset a legitimate operand for memory addition. */
5087 offset
= GEN_INT (delta
);
5088 if ((delta
< -8 || delta
> 8)
5089 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5091 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5092 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5094 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5095 copy_rtx (this_slot
), offset
));
5098 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5099 if (vcall_offset
!= 0)
5101 /* Set the static chain register to *THIS. */
5102 emit_move_insn (tmp
, this_slot
);
5103 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5105 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5106 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5107 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5109 emit_insn (gen_rtx_SET (tmp
, addr
));
5113 /* Load the offset into %d0 and add it to THIS. */
5114 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5115 gen_rtx_MEM (Pmode
, addr
));
5116 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5117 copy_rtx (this_slot
),
5118 gen_rtx_REG (Pmode
, D0_REG
)));
5121 /* Jump to the target function. Use a sibcall if direct jumps are
5122 allowed, otherwise load the address into a register first. */
5123 mem
= DECL_RTL (function
);
5124 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5126 gcc_assert (flag_pic
);
5128 if (!TARGET_SEP_DATA
)
5130 /* Use the static chain register as a temporary (call-clobbered)
5131 GOT pointer for this function. We can use the static chain
5132 register because it isn't live on entry to the thunk. */
5133 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5134 emit_insn (gen_load_got (pic_offset_table_rtx
));
5136 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5137 mem
= replace_equiv_address (mem
, tmp
);
5139 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5140 SIBLING_CALL_P (insn
) = 1;
5142 /* Run just enough of rest_of_compilation. */
5143 insn
= get_insns ();
5144 split_all_insns_noflow ();
5145 assemble_start_function (thunk
, fnname
);
5146 final_start_function (insn
, file
, 1);
5147 final (insn
, file
, 1);
5148 final_end_function ();
5149 assemble_end_function (thunk
, fnname
);
5151 /* Clean up the vars set above. */
5152 reload_completed
= 0;
5154 /* Restore the original PIC register. */
5156 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5159 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5162 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5163 int incoming ATTRIBUTE_UNUSED
)
5165 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5168 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5170 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5171 unsigned int new_reg
)
5174 /* Interrupt functions can only use registers that have already been
5175 saved by the prologue, even if they would normally be
5178 if ((m68k_get_function_kind (current_function_decl
)
5179 == m68k_fk_interrupt_handler
)
5180 && !df_regs_ever_live_p (new_reg
))
5186 /* Implement TARGET_HARD_REGNO_NREGS.
5188 On the m68k, ordinary registers hold 32 bits worth;
5189 for the 68881 registers, a single register is always enough for
5190 anything that can be stored in them at all. */
5193 m68k_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
5196 return GET_MODE_NUNITS (mode
);
5197 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
5200 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5201 registers can hold any mode, but restrict the 68881 registers to
5202 floating-point modes. */
5205 m68k_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5207 if (DATA_REGNO_P (regno
))
5209 /* Data Registers, can hold aggregate if fits in. */
5210 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5213 else if (ADDRESS_REGNO_P (regno
))
5215 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5218 else if (FP_REGNO_P (regno
))
5220 /* FPU registers, hold float or complex float of long double or
5222 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5223 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5224 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5230 /* Implement TARGET_MODES_TIEABLE_P. */
5233 m68k_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5235 return (!TARGET_HARD_FLOAT
5236 || ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
5237 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
5238 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
5239 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
)));
5242 /* Implement SECONDARY_RELOAD_CLASS. */
5245 m68k_secondary_reload_class (enum reg_class rclass
,
5246 machine_mode mode
, rtx x
)
5250 regno
= true_regnum (x
);
5252 /* If one operand of a movqi is an address register, the other
5253 operand must be a general register or constant. Other types
5254 of operand must be reloaded through a data register. */
5255 if (GET_MODE_SIZE (mode
) == 1
5256 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5257 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5260 /* PC-relative addresses must be loaded into an address register first. */
5262 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5263 && symbolic_operand (x
, VOIDmode
))
5269 /* Implement PREFERRED_RELOAD_CLASS. */
5272 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5274 enum reg_class secondary_class
;
5276 /* If RCLASS might need a secondary reload, try restricting it to
5277 a class that doesn't. */
5278 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5279 if (secondary_class
!= NO_REGS
5280 && reg_class_subset_p (secondary_class
, rclass
))
5281 return secondary_class
;
5283 /* Prefer to use moveq for in-range constants. */
5284 if (GET_CODE (x
) == CONST_INT
5285 && reg_class_subset_p (DATA_REGS
, rclass
)
5286 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5289 /* ??? Do we really need this now? */
5290 if (GET_CODE (x
) == CONST_DOUBLE
5291 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5293 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5302 /* Return floating point values in a 68881 register. This makes 68881 code
5303 a little bit faster. It also makes -msoft-float code incompatible with
5304 hard-float code, so people have to be careful not to mix the two.
5305 For ColdFire it was decided the ABI incompatibility is undesirable.
5306 If there is need for a hard-float ABI it is probably worth doing it
5307 properly and also passing function arguments in FP registers. */
5309 m68k_libcall_value (machine_mode mode
)
5316 return gen_rtx_REG (mode
, FP0_REG
);
5322 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5325 /* Location in which function value is returned.
5326 NOTE: Due to differences in ABIs, don't call this function directly,
5327 use FUNCTION_VALUE instead. */
5329 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5333 mode
= TYPE_MODE (valtype
);
5339 return gen_rtx_REG (mode
, FP0_REG
);
5345 /* If the function returns a pointer, push that into %a0. */
5346 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5347 /* For compatibility with the large body of existing code which
5348 does not always properly declare external functions returning
5349 pointer types, the m68k/SVR4 convention is to copy the value
5350 returned for pointer functions from a0 to d0 in the function
5351 epilogue, so that callers that have neglected to properly
5352 declare the callee can still find the correct return value in
5354 return gen_rtx_PARALLEL
5357 gen_rtx_EXPR_LIST (VOIDmode
,
5358 gen_rtx_REG (mode
, A0_REG
),
5360 gen_rtx_EXPR_LIST (VOIDmode
,
5361 gen_rtx_REG (mode
, D0_REG
),
5363 else if (POINTER_TYPE_P (valtype
))
5364 return gen_rtx_REG (mode
, A0_REG
);
5366 return gen_rtx_REG (mode
, D0_REG
);
5369 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5370 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5372 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5374 machine_mode mode
= TYPE_MODE (type
);
5376 if (mode
== BLKmode
)
5379 /* If TYPE's known alignment is less than the alignment of MODE that
5380 would contain the structure, then return in memory. We need to
5381 do so to maintain the compatibility between code compiled with
5382 -mstrict-align and that compiled with -mno-strict-align. */
5383 if (AGGREGATE_TYPE_P (type
)
5384 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5391 /* CPU to schedule the program for. */
5392 enum attr_cpu m68k_sched_cpu
;
5394 /* MAC to schedule the program for. */
5395 enum attr_mac m68k_sched_mac
;
5403 /* Integer register. */
5409 /* Implicit mem reference (e.g. stack). */
5412 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5415 /* Memory with offset but without indexing. EA mode 5. */
5418 /* Memory with indexing. EA mode 6. */
5421 /* Memory referenced by absolute address. EA mode 7. */
5424 /* Immediate operand that doesn't require extension word. */
5427 /* Immediate 16 bit operand. */
5430 /* Immediate 32 bit operand. */
5434 /* Return type of memory ADDR_RTX refers to. */
5435 static enum attr_op_type
5436 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5438 struct m68k_address address
;
5440 if (symbolic_operand (addr_rtx
, VOIDmode
))
5441 return OP_TYPE_MEM7
;
5443 if (!m68k_decompose_address (mode
, addr_rtx
,
5444 reload_completed
, &address
))
5446 gcc_assert (!reload_completed
);
5447 /* Reload will likely fix the address to be in the register. */
5448 return OP_TYPE_MEM234
;
5451 if (address
.scale
!= 0)
5452 return OP_TYPE_MEM6
;
5454 if (address
.base
!= NULL_RTX
)
5456 if (address
.offset
== NULL_RTX
)
5457 return OP_TYPE_MEM234
;
5459 return OP_TYPE_MEM5
;
5462 gcc_assert (address
.offset
!= NULL_RTX
);
5464 return OP_TYPE_MEM7
;
5467 /* Return X or Y (depending on OPX_P) operand of INSN. */
5469 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5473 if (recog_memoized (insn
) < 0)
5476 extract_constrain_insn_cached (insn
);
5479 i
= get_attr_opx (insn
);
5481 i
= get_attr_opy (insn
);
5483 if (i
>= recog_data
.n_operands
)
5486 return recog_data
.operand
[i
];
5489 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5490 If ADDRESS_P is true, return type of memory location operand refers to. */
5491 static enum attr_op_type
5492 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5496 op
= sched_get_operand (insn
, opx_p
);
5500 gcc_assert (!reload_completed
);
5505 return sched_address_type (QImode
, op
);
5507 if (memory_operand (op
, VOIDmode
))
5508 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5510 if (register_operand (op
, VOIDmode
))
5512 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5513 || (reload_completed
&& FP_REG_P (op
)))
5519 if (GET_CODE (op
) == CONST_INT
)
5525 /* Check for quick constants. */
5526 switch (get_attr_type (insn
))
5529 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5530 return OP_TYPE_IMM_Q
;
5532 gcc_assert (!reload_completed
);
5536 if (USE_MOVQ (ival
))
5537 return OP_TYPE_IMM_Q
;
5539 gcc_assert (!reload_completed
);
5543 if (valid_mov3q_const (ival
))
5544 return OP_TYPE_IMM_Q
;
5546 gcc_assert (!reload_completed
);
5553 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5554 return OP_TYPE_IMM_W
;
5556 return OP_TYPE_IMM_L
;
5559 if (GET_CODE (op
) == CONST_DOUBLE
)
5561 switch (GET_MODE (op
))
5564 return OP_TYPE_IMM_W
;
5568 return OP_TYPE_IMM_L
;
5575 if (GET_CODE (op
) == CONST
5576 || symbolic_operand (op
, VOIDmode
)
5579 switch (GET_MODE (op
))
5582 return OP_TYPE_IMM_Q
;
5585 return OP_TYPE_IMM_W
;
5588 return OP_TYPE_IMM_L
;
5591 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5593 return OP_TYPE_IMM_W
;
5595 return OP_TYPE_IMM_L
;
5599 gcc_assert (!reload_completed
);
5601 if (FLOAT_MODE_P (GET_MODE (op
)))
5607 /* Implement opx_type attribute.
5608 Return type of INSN's operand X.
5609 If ADDRESS_P is true, return type of memory location operand refers to. */
5611 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5613 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5619 return OPX_TYPE_FPN
;
5622 return OPX_TYPE_MEM1
;
5624 case OP_TYPE_MEM234
:
5625 return OPX_TYPE_MEM234
;
5628 return OPX_TYPE_MEM5
;
5631 return OPX_TYPE_MEM6
;
5634 return OPX_TYPE_MEM7
;
5637 return OPX_TYPE_IMM_Q
;
5640 return OPX_TYPE_IMM_W
;
5643 return OPX_TYPE_IMM_L
;
5650 /* Implement opy_type attribute.
5651 Return type of INSN's operand Y.
5652 If ADDRESS_P is true, return type of memory location operand refers to. */
5654 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5656 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5662 return OPY_TYPE_FPN
;
5665 return OPY_TYPE_MEM1
;
5667 case OP_TYPE_MEM234
:
5668 return OPY_TYPE_MEM234
;
5671 return OPY_TYPE_MEM5
;
5674 return OPY_TYPE_MEM6
;
5677 return OPY_TYPE_MEM7
;
5680 return OPY_TYPE_IMM_Q
;
5683 return OPY_TYPE_IMM_W
;
5686 return OPY_TYPE_IMM_L
;
5693 /* Return size of INSN as int. */
5695 sched_get_attr_size_int (rtx_insn
*insn
)
5699 switch (get_attr_type (insn
))
5702 /* There should be no references to m68k_sched_attr_size for 'ignore'
5716 switch (get_attr_opx_type (insn
))
5722 case OPX_TYPE_MEM234
:
5723 case OPY_TYPE_IMM_Q
:
5728 /* Here we assume that most absolute references are short. */
5730 case OPY_TYPE_IMM_W
:
5734 case OPY_TYPE_IMM_L
:
5742 switch (get_attr_opy_type (insn
))
5748 case OPY_TYPE_MEM234
:
5749 case OPY_TYPE_IMM_Q
:
5754 /* Here we assume that most absolute references are short. */
5756 case OPY_TYPE_IMM_W
:
5760 case OPY_TYPE_IMM_L
:
5770 gcc_assert (!reload_completed
);
5778 /* Return size of INSN as attribute enum value. */
5780 m68k_sched_attr_size (rtx_insn
*insn
)
5782 switch (sched_get_attr_size_int (insn
))
5798 /* Return operand X or Y (depending on OPX_P) of INSN,
5799 if it is a MEM, or NULL overwise. */
5800 static enum attr_op_type
5801 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5805 switch (get_attr_opx_type (insn
))
5810 case OPX_TYPE_IMM_Q
:
5811 case OPX_TYPE_IMM_W
:
5812 case OPX_TYPE_IMM_L
:
5816 case OPX_TYPE_MEM234
:
5819 return OP_TYPE_MEM1
;
5822 return OP_TYPE_MEM6
;
5830 switch (get_attr_opy_type (insn
))
5835 case OPY_TYPE_IMM_Q
:
5836 case OPY_TYPE_IMM_W
:
5837 case OPY_TYPE_IMM_L
:
5841 case OPY_TYPE_MEM234
:
5844 return OP_TYPE_MEM1
;
5847 return OP_TYPE_MEM6
;
5855 /* Implement op_mem attribute. */
5857 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5859 enum attr_op_type opx
;
5860 enum attr_op_type opy
;
5862 opx
= sched_get_opxy_mem_type (insn
, true);
5863 opy
= sched_get_opxy_mem_type (insn
, false);
5865 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5868 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5870 switch (get_attr_opx_access (insn
))
5886 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5888 switch (get_attr_opx_access (insn
))
5904 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5907 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5909 switch (get_attr_opx_access (insn
))
5915 gcc_assert (!reload_completed
);
5920 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5922 switch (get_attr_opx_access (insn
))
5928 gcc_assert (!reload_completed
);
5933 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5936 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5938 switch (get_attr_opx_access (insn
))
5944 gcc_assert (!reload_completed
);
5949 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5950 gcc_assert (!reload_completed
);
5954 /* Data for ColdFire V4 index bypass.
5955 Producer modifies register that is used as index in consumer with
5959 /* Producer instruction. */
5962 /* Consumer instruction. */
5965 /* Scale of indexed memory access within consumer.
5966 Or zero if bypass should not be effective at the moment. */
5968 } sched_cfv4_bypass_data
;
5970 /* An empty state that is used in m68k_sched_adjust_cost. */
5971 static state_t sched_adjust_cost_state
;
5973 /* Implement adjust_cost scheduler hook.
5974 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5976 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
5981 if (recog_memoized (def_insn
) < 0
5982 || recog_memoized (insn
) < 0)
5985 if (sched_cfv4_bypass_data
.scale
== 1)
5986 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5988 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5989 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5990 that the data in sched_cfv4_bypass_data is up to date. */
5991 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5992 && sched_cfv4_bypass_data
.con
== insn
);
5997 sched_cfv4_bypass_data
.pro
= NULL
;
5998 sched_cfv4_bypass_data
.con
= NULL
;
5999 sched_cfv4_bypass_data
.scale
= 0;
6002 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6003 && sched_cfv4_bypass_data
.con
== NULL
6004 && sched_cfv4_bypass_data
.scale
== 0);
6006 /* Don't try to issue INSN earlier than DFA permits.
6007 This is especially useful for instructions that write to memory,
6008 as their true dependence (default) latency is better to be set to 0
6009 to workaround alias analysis limitations.
6010 This is, in fact, a machine independent tweak, so, probably,
6011 it should be moved to haifa-sched.c: insn_cost (). */
6012 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
6019 /* Return maximal number of insns that can be scheduled on a single cycle. */
6021 m68k_sched_issue_rate (void)
6023 switch (m68k_sched_cpu
)
6039 /* Maximal length of instruction for current CPU.
6040 E.g. it is 3 for any ColdFire core. */
6041 static int max_insn_size
;
6043 /* Data to model instruction buffer of CPU. */
6046 /* True if instruction buffer model is modeled for current CPU. */
6049 /* Size of the instruction buffer in words. */
6052 /* Number of filled words in the instruction buffer. */
6055 /* Additional information about instruction buffer for CPUs that have
6056 a buffer of instruction records, rather then a plain buffer
6057 of instruction words. */
6058 struct _sched_ib_records
6060 /* Size of buffer in records. */
6063 /* Array to hold data on adjustments made to the size of the buffer. */
6066 /* Index of the above array. */
6070 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6074 static struct _sched_ib sched_ib
;
6076 /* ID of memory unit. */
6077 static int sched_mem_unit_code
;
6079 /* Implementation of the targetm.sched.variable_issue () hook.
6080 It is called after INSN was issued. It returns the number of insns
6081 that can possibly get scheduled on the current cycle.
6082 It is used here to determine the effect of INSN on the instruction
6085 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6086 int sched_verbose ATTRIBUTE_UNUSED
,
6087 rtx_insn
*insn
, int can_issue_more
)
6091 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6093 switch (m68k_sched_cpu
)
6097 insn_size
= sched_get_attr_size_int (insn
);
6101 insn_size
= sched_get_attr_size_int (insn
);
6103 /* ColdFire V3 and V4 cores have instruction buffers that can
6104 accumulate up to 8 instructions regardless of instructions'
6105 sizes. So we should take care not to "prefetch" 24 one-word
6106 or 12 two-words instructions.
6107 To model this behavior we temporarily decrease size of the
6108 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6112 adjust
= max_insn_size
- insn_size
;
6113 sched_ib
.size
-= adjust
;
6115 if (sched_ib
.filled
> sched_ib
.size
)
6116 sched_ib
.filled
= sched_ib
.size
;
6118 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6121 ++sched_ib
.records
.adjust_index
;
6122 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6123 sched_ib
.records
.adjust_index
= 0;
6125 /* Undo adjustment we did 7 instructions ago. */
6127 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6132 gcc_assert (!sched_ib
.enabled_p
);
6140 if (insn_size
> sched_ib
.filled
)
6141 /* Scheduling for register pressure does not always take DFA into
6142 account. Workaround instruction buffer not being filled enough. */
6144 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6145 insn_size
= sched_ib
.filled
;
6150 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6151 || asm_noperands (PATTERN (insn
)) >= 0)
6152 insn_size
= sched_ib
.filled
;
6156 sched_ib
.filled
-= insn_size
;
6158 return can_issue_more
;
6161 /* Return how many instructions should scheduler lookahead to choose the
6164 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6166 return m68k_sched_issue_rate () - 1;
6169 /* Implementation of targetm.sched.init_global () hook.
6170 It is invoked once per scheduling pass and is used here
6171 to initialize scheduler constants. */
6173 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6174 int sched_verbose ATTRIBUTE_UNUSED
,
6175 int n_insns ATTRIBUTE_UNUSED
)
6177 /* Check that all instructions have DFA reservations and
6178 that all instructions can be issued from a clean state. */
6184 state
= alloca (state_size ());
6186 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6188 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6190 gcc_assert (insn_has_dfa_reservation_p (insn
));
6192 state_reset (state
);
6193 if (state_transition (state
, insn
) >= 0)
6199 /* Setup target cpu. */
6201 /* ColdFire V4 has a set of features to keep its instruction buffer full
6202 (e.g., a separate memory bus for instructions) and, hence, we do not model
6203 buffer for this CPU. */
6204 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6206 switch (m68k_sched_cpu
)
6209 sched_ib
.filled
= 0;
6216 sched_ib
.records
.n_insns
= 0;
6217 sched_ib
.records
.adjust
= NULL
;
6222 sched_ib
.records
.n_insns
= 8;
6223 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6230 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6232 sched_adjust_cost_state
= xmalloc (state_size ());
6233 state_reset (sched_adjust_cost_state
);
6236 emit_insn (gen_ib ());
6237 sched_ib
.insn
= get_insns ();
6241 /* Scheduling pass is now finished. Free/reset static variables. */
6243 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6244 int verbose ATTRIBUTE_UNUSED
)
6246 sched_ib
.insn
= NULL
;
6248 free (sched_adjust_cost_state
);
6249 sched_adjust_cost_state
= NULL
;
6251 sched_mem_unit_code
= 0;
6253 free (sched_ib
.records
.adjust
);
6254 sched_ib
.records
.adjust
= NULL
;
6255 sched_ib
.records
.n_insns
= 0;
6259 /* Implementation of targetm.sched.init () hook.
6260 It is invoked each time scheduler starts on the new block (basic block or
6261 extended basic block). */
6263 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6264 int sched_verbose ATTRIBUTE_UNUSED
,
6265 int n_insns ATTRIBUTE_UNUSED
)
6267 switch (m68k_sched_cpu
)
6275 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6277 memset (sched_ib
.records
.adjust
, 0,
6278 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6279 sched_ib
.records
.adjust_index
= 0;
6283 gcc_assert (!sched_ib
.enabled_p
);
6291 if (sched_ib
.enabled_p
)
6292 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6293 the first cycle. Workaround that. */
6294 sched_ib
.filled
= -2;
6297 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6298 It is invoked just before current cycle finishes and is used here
6299 to track if instruction buffer got its two words this cycle. */
6301 m68k_sched_dfa_pre_advance_cycle (void)
6303 if (!sched_ib
.enabled_p
)
6306 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6308 sched_ib
.filled
+= 2;
6310 if (sched_ib
.filled
> sched_ib
.size
)
6311 sched_ib
.filled
= sched_ib
.size
;
6315 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6316 It is invoked just after new cycle begins and is used here
6317 to setup number of filled words in the instruction buffer so that
6318 instructions which won't have all their words prefetched would be
6319 stalled for a cycle. */
6321 m68k_sched_dfa_post_advance_cycle (void)
6325 if (!sched_ib
.enabled_p
)
6328 /* Setup number of prefetched instruction words in the instruction
6330 i
= max_insn_size
- sched_ib
.filled
;
6334 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6335 /* Pick up scheduler state. */
6340 /* Return X or Y (depending on OPX_P) operand of INSN,
6341 if it is an integer register, or NULL overwise. */
6343 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6349 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6351 op
= sched_get_operand (insn
, true);
6352 gcc_assert (op
!= NULL
);
6354 if (!reload_completed
&& !REG_P (op
))
6360 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6362 op
= sched_get_operand (insn
, false);
6363 gcc_assert (op
!= NULL
);
6365 if (!reload_completed
&& !REG_P (op
))
6373 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6376 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6378 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6389 /* Return X or Y (depending on OPX_P) operand of INSN,
6390 if it is a MEM, or NULL overwise. */
6392 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6412 if (opy_p
&& sched_mem_operand_p (insn
, false))
6413 return sched_get_operand (insn
, false);
6415 if (opx_p
&& sched_mem_operand_p (insn
, true))
6416 return sched_get_operand (insn
, true);
6422 /* Return non-zero if PRO modifies register used as part of
6425 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6430 pro_x
= sched_get_reg_operand (pro
, true);
6434 con_mem_read
= sched_get_mem_operand (con
, true, false);
6435 gcc_assert (con_mem_read
!= NULL
);
6437 if (reg_mentioned_p (pro_x
, con_mem_read
))
6443 /* Helper function for m68k_sched_indexed_address_bypass_p.
6444 if PRO modifies register used as index in CON,
6445 return scale of indexed memory access in CON. Return zero overwise. */
6447 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6451 struct m68k_address address
;
6453 reg
= sched_get_reg_operand (pro
, true);
6457 mem
= sched_get_mem_operand (con
, true, false);
6458 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6460 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6464 if (REGNO (reg
) == REGNO (address
.index
))
6466 gcc_assert (address
.scale
!= 0);
6467 return address
.scale
;
6473 /* Return non-zero if PRO modifies register used
6474 as index with scale 2 or 4 in CON. */
6476 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6478 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6479 && sched_cfv4_bypass_data
.con
== NULL
6480 && sched_cfv4_bypass_data
.scale
== 0);
6482 switch (sched_get_indexed_address_scale (pro
, con
))
6485 /* We can't have a variable latency bypass, so
6486 remember to adjust the insn cost in adjust_cost hook. */
6487 sched_cfv4_bypass_data
.pro
= pro
;
6488 sched_cfv4_bypass_data
.con
= con
;
6489 sched_cfv4_bypass_data
.scale
= 1;
6501 /* We generate a two-instructions program at M_TRAMP :
6502 movea.l &CHAIN_VALUE,%a0
6504 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6507 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6509 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6512 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6514 mem
= adjust_address (m_tramp
, HImode
, 0);
6515 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6516 mem
= adjust_address (m_tramp
, SImode
, 2);
6517 emit_move_insn (mem
, chain_value
);
6519 mem
= adjust_address (m_tramp
, HImode
, 6);
6520 emit_move_insn (mem
, GEN_INT(0x4EF9));
6521 mem
= adjust_address (m_tramp
, SImode
, 8);
6522 emit_move_insn (mem
, fnaddr
);
6524 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6527 /* On the 68000, the RTS insn cannot pop anything.
6528 On the 68010, the RTD insn may be used to pop them if the number
6529 of args is fixed, but if the number is variable then the caller
6530 must pop them all. RTD can't be used for library calls now
6531 because the library is compiled with the Unix compiler.
6532 Use of RTD is a selectable option, since it is incompatible with
6533 standard Unix calling sequences. If the option is not selected,
6534 the caller must always pop the args. */
6537 m68k_return_pops_args (tree fundecl
, tree funtype
, poly_int64 size
)
6541 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6542 && (!stdarg_p (funtype
)))
6543 ? (HOST_WIDE_INT
) size
: 0);
6546 /* Make sure everything's fine if we *don't* have a given processor.
6547 This assumes that putting a register in fixed_regs will keep the
6548 compiler's mitts completely off it. We don't bother to zero it out
6549 of register classes. */
6552 m68k_conditional_register_usage (void)
6556 if (!TARGET_HARD_FLOAT
)
6558 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6559 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6560 if (TEST_HARD_REG_BIT (x
, i
))
6561 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6564 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6568 m68k_init_sync_libfuncs (void)
6570 init_sync_libfuncs (UNITS_PER_WORD
);
6573 /* Implements EPILOGUE_USES. All registers are live on exit from an
6574 interrupt routine. */
6576 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6578 return (reload_completed
6579 && (m68k_get_function_kind (current_function_decl
)
6580 == m68k_fk_interrupt_handler
));
6584 /* Implement TARGET_C_EXCESS_PRECISION.
6586 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6587 instructions, we get proper intermediate rounding, otherwise we
6588 get extended precision results. */
6590 static enum flt_eval_method
6591 m68k_excess_precision (enum excess_precision_type type
)
6595 case EXCESS_PRECISION_TYPE_FAST
:
6596 /* The fastest type to promote to will always be the native type,
6597 whether that occurs with implicit excess precision or
6599 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6600 case EXCESS_PRECISION_TYPE_STANDARD
:
6601 case EXCESS_PRECISION_TYPE_IMPLICIT
:
6602 /* Otherwise, the excess precision we want when we are
6603 in a standards compliant mode, and the implicit precision we
6604 provide can be identical. */
6605 if (TARGET_68040
|| ! TARGET_68881
)
6606 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6608 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE
;
6612 return FLT_EVAL_METHOD_UNPREDICTABLE
;
6615 /* Implement PUSH_ROUNDING. On the 680x0, sp@- in a byte insn really pushes
6616 a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */
6619 m68k_push_rounding (poly_int64 bytes
)
6621 if (TARGET_COLDFIRE
)
6623 return (bytes
+ 1) & ~1;
6626 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
6629 m68k_promote_function_mode (const_tree type
, machine_mode mode
,
6630 int *punsignedp ATTRIBUTE_UNUSED
,
6631 const_tree fntype ATTRIBUTE_UNUSED
,
6634 /* Promote libcall arguments narrower than int to match the normal C
6635 ABI (for which promotions are handled via
6636 TARGET_PROMOTE_PROTOTYPES). */
6637 if (type
== NULL_TREE
&& !for_return
&& (mode
== QImode
|| mode
== HImode
))
6642 #include "gt-m68k.h"