1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
51 enum reg_class regno_reg_class
[] =
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
63 /* The minimum number of integer registers that we want to save with the
64 movem instruction. Using two movel instructions instead of a single
65 moveml is about 15% faster for the 68020 and 68030 at no expense in
67 #define MIN_MOVEM_REGS 3
69 /* The minimum number of floating point registers that we want to save
70 with the fmovem instruction. */
71 #define MIN_FMOVEM_REGS 1
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
91 unsigned int fpu_mask
;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset
;
95 HOST_WIDE_INT stack_pointer_offset
;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame
;
104 /* Structure describing an m68k address.
106 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
107 with null fields evaluating to 0. Here:
109 - BASE satisfies m68k_legitimate_base_reg_p
110 - INDEX satisfies m68k_legitimate_index_reg_p
111 - OFFSET satisfies m68k_legitimate_constant_address_p
113 INDEX is either HImode or SImode. The other fields are SImode.
115 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
116 the address is (BASE)+. */
117 struct m68k_address
{
125 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
126 static int m68k_sched_issue_rate (void);
127 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
128 static void m68k_sched_md_init_global (FILE *, int, int);
129 static void m68k_sched_md_finish_global (FILE *, int);
130 static void m68k_sched_md_init (FILE *, int, int);
131 static void m68k_sched_dfa_pre_advance_cycle (void);
132 static void m68k_sched_dfa_post_advance_cycle (void);
133 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
135 static bool m68k_can_eliminate (const int, const int);
136 static void m68k_conditional_register_usage (void);
137 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
138 static void m68k_option_override (void);
139 static void m68k_override_options_after_change (void);
140 static rtx
find_addr_reg (rtx
);
141 static const char *singlemove_string (rtx
*);
142 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
143 HOST_WIDE_INT
, tree
);
144 static rtx
m68k_struct_value_rtx (tree
, int);
145 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
146 tree args
, int flags
,
148 static void m68k_compute_frame_layout (void);
149 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
150 static bool m68k_ok_for_sibcall_p (tree
, tree
);
151 static bool m68k_tls_symbol_p (rtx
);
152 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
153 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
154 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
155 static bool m68k_return_in_memory (const_tree
, const_tree
);
157 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
158 static void m68k_trampoline_init (rtx
, tree
, rtx
);
159 static int m68k_return_pops_args (tree
, tree
, int);
160 static rtx
m68k_delegitimize_address (rtx
);
161 static void m68k_function_arg_advance (cumulative_args_t
, enum machine_mode
,
163 static rtx
m68k_function_arg (cumulative_args_t
, enum machine_mode
,
165 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
166 static bool m68k_output_addr_const_extra (FILE *, rtx
);
168 /* Initialize the GCC target structure. */
170 #if INT_OP_GROUP == INT_OP_DOT_WORD
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
175 #if INT_OP_GROUP == INT_OP_NO_DOT
176 #undef TARGET_ASM_BYTE_OP
177 #define TARGET_ASM_BYTE_OP "\tbyte\t"
178 #undef TARGET_ASM_ALIGNED_HI_OP
179 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
180 #undef TARGET_ASM_ALIGNED_SI_OP
181 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
184 #if INT_OP_GROUP == INT_OP_DC
185 #undef TARGET_ASM_BYTE_OP
186 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
187 #undef TARGET_ASM_ALIGNED_HI_OP
188 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
189 #undef TARGET_ASM_ALIGNED_SI_OP
190 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
193 #undef TARGET_ASM_UNALIGNED_HI_OP
194 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
195 #undef TARGET_ASM_UNALIGNED_SI_OP
196 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
198 #undef TARGET_ASM_OUTPUT_MI_THUNK
199 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
200 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
201 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
203 #undef TARGET_ASM_FILE_START_APP_OFF
204 #define TARGET_ASM_FILE_START_APP_OFF true
206 #undef TARGET_LEGITIMIZE_ADDRESS
207 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
209 #undef TARGET_SCHED_ADJUST_COST
210 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
212 #undef TARGET_SCHED_ISSUE_RATE
213 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
215 #undef TARGET_SCHED_VARIABLE_ISSUE
216 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
218 #undef TARGET_SCHED_INIT_GLOBAL
219 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
221 #undef TARGET_SCHED_FINISH_GLOBAL
222 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
224 #undef TARGET_SCHED_INIT
225 #define TARGET_SCHED_INIT m68k_sched_md_init
227 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
228 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
230 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
231 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
233 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
234 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
235 m68k_sched_first_cycle_multipass_dfa_lookahead
237 #undef TARGET_OPTION_OVERRIDE
238 #define TARGET_OPTION_OVERRIDE m68k_option_override
240 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
241 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
243 #undef TARGET_RTX_COSTS
244 #define TARGET_RTX_COSTS m68k_rtx_costs
246 #undef TARGET_ATTRIBUTE_TABLE
247 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
249 #undef TARGET_PROMOTE_PROTOTYPES
250 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
252 #undef TARGET_STRUCT_VALUE_RTX
253 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
255 #undef TARGET_CANNOT_FORCE_CONST_MEM
256 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
258 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
259 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
261 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
262 #undef TARGET_RETURN_IN_MEMORY
263 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
267 #undef TARGET_HAVE_TLS
268 #define TARGET_HAVE_TLS (true)
270 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
271 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
274 #undef TARGET_LEGITIMATE_ADDRESS_P
275 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
277 #undef TARGET_CAN_ELIMINATE
278 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
280 #undef TARGET_CONDITIONAL_REGISTER_USAGE
281 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
283 #undef TARGET_TRAMPOLINE_INIT
284 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
286 #undef TARGET_RETURN_POPS_ARGS
287 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
289 #undef TARGET_DELEGITIMIZE_ADDRESS
290 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
292 #undef TARGET_FUNCTION_ARG
293 #define TARGET_FUNCTION_ARG m68k_function_arg
295 #undef TARGET_FUNCTION_ARG_ADVANCE
296 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
298 #undef TARGET_LEGITIMATE_CONSTANT_P
299 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
301 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
302 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
304 static const struct attribute_spec m68k_attribute_table
[] =
306 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
307 affects_type_identity } */
308 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
310 { "interrupt_handler", 0, 0, true, false, false,
311 m68k_handle_fndecl_attribute
, false },
312 { "interrupt_thread", 0, 0, true, false, false,
313 m68k_handle_fndecl_attribute
, false },
314 { NULL
, 0, 0, false, false, false, NULL
, false }
317 struct gcc_target targetm
= TARGET_INITIALIZER
;
319 /* Base flags for 68k ISAs. */
320 #define FL_FOR_isa_00 FL_ISA_68000
321 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
322 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
323 generated 68881 code for 68020 and 68030 targets unless explicitly told
325 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
326 | FL_BITFIELD | FL_68881)
327 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
328 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
330 /* Base flags for ColdFire ISAs. */
331 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
332 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
333 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
334 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
335 /* ISA_C is not upwardly compatible with ISA_B. */
336 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
340 /* Traditional 68000 instruction sets. */
346 /* ColdFire instruction set variants. */
354 /* Information about one of the -march, -mcpu or -mtune arguments. */
355 struct m68k_target_selection
357 /* The argument being described. */
360 /* For -mcpu, this is the device selected by the option.
361 For -mtune and -march, it is a representative device
362 for the microarchitecture or ISA respectively. */
363 enum target_device device
;
365 /* The M68K_DEVICE fields associated with DEVICE. See the comment
366 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
368 enum uarch_type microarch
;
373 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
374 static const struct m68k_target_selection all_devices
[] =
376 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
377 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
378 #include "m68k-devices.def"
380 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
383 /* A list of all ISAs, mapping each one to a representative device.
384 Used for -march selection. */
385 static const struct m68k_target_selection all_isas
[] =
387 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
388 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
389 #include "m68k-isas.def"
391 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
394 /* A list of all microarchitectures, mapping each one to a representative
395 device. Used for -mtune selection. */
396 static const struct m68k_target_selection all_microarchs
[] =
398 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
399 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
400 #include "m68k-microarchs.def"
401 #undef M68K_MICROARCH
402 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
405 /* The entries associated with the -mcpu, -march and -mtune settings,
406 or null for options that have not been used. */
407 const struct m68k_target_selection
*m68k_cpu_entry
;
408 const struct m68k_target_selection
*m68k_arch_entry
;
409 const struct m68k_target_selection
*m68k_tune_entry
;
411 /* Which CPU we are generating code for. */
412 enum target_device m68k_cpu
;
414 /* Which microarchitecture to tune for. */
415 enum uarch_type m68k_tune
;
417 /* Which FPU to use. */
418 enum fpu_type m68k_fpu
;
420 /* The set of FL_* flags that apply to the target processor. */
421 unsigned int m68k_cpu_flags
;
423 /* The set of FL_* flags that apply to the processor to be tuned for. */
424 unsigned int m68k_tune_flags
;
426 /* Asm templates for calling or jumping to an arbitrary symbolic address,
427 or NULL if such calls or jumps are not supported. The address is held
429 const char *m68k_symbolic_call
;
430 const char *m68k_symbolic_jump
;
432 /* Enum variable that corresponds to m68k_symbolic_call values. */
433 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
436 /* Implement TARGET_OPTION_OVERRIDE. */
439 m68k_option_override (void)
441 const struct m68k_target_selection
*entry
;
442 unsigned long target_mask
;
444 if (global_options_set
.x_m68k_arch_option
)
445 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
447 if (global_options_set
.x_m68k_cpu_option
)
448 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
450 if (global_options_set
.x_m68k_tune_option
)
451 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
459 -march=ARCH should generate code that runs any processor
460 implementing architecture ARCH. -mcpu=CPU should override -march
461 and should generate code that runs on processor CPU, making free
462 use of any instructions that CPU understands. -mtune=UARCH applies
463 on top of -mcpu or -march and optimizes the code for UARCH. It does
464 not change the target architecture. */
467 /* Complain if the -march setting is for a different microarchitecture,
468 or includes flags that the -mcpu setting doesn't. */
470 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
471 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
472 warning (0, "-mcpu=%s conflicts with -march=%s",
473 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
475 entry
= m68k_cpu_entry
;
478 entry
= m68k_arch_entry
;
481 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
483 m68k_cpu_flags
= entry
->flags
;
485 /* Use the architecture setting to derive default values for
489 /* ColdFire is lenient about alignment. */
490 if (!TARGET_COLDFIRE
)
491 target_mask
|= MASK_STRICT_ALIGNMENT
;
493 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
494 target_mask
|= MASK_BITFIELD
;
495 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
496 target_mask
|= MASK_CF_HWDIV
;
497 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
498 target_mask
|= MASK_HARD_FLOAT
;
499 target_flags
|= target_mask
& ~target_flags_explicit
;
501 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
502 m68k_cpu
= entry
->device
;
505 m68k_tune
= m68k_tune_entry
->microarch
;
506 m68k_tune_flags
= m68k_tune_entry
->flags
;
508 #ifdef M68K_DEFAULT_TUNE
509 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
511 enum target_device dev
;
512 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
513 m68k_tune_flags
= all_devices
[dev
]->flags
;
518 m68k_tune
= entry
->microarch
;
519 m68k_tune_flags
= entry
->flags
;
522 /* Set the type of FPU. */
523 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
524 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
527 /* Sanity check to ensure that msep-data and mid-sahred-library are not
528 * both specified together. Doing so simply doesn't make sense.
530 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
531 error ("cannot specify both -msep-data and -mid-shared-library");
533 /* If we're generating code for a separate A5 relative data segment,
534 * we've got to enable -fPIC as well. This might be relaxable to
535 * -fpic but it hasn't been tested properly.
537 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
540 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
541 error if the target does not support them. */
542 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
543 error ("-mpcrel -fPIC is not currently supported on selected cpu");
545 /* ??? A historic way of turning on pic, or is this intended to
546 be an embedded thing that doesn't have the same name binding
547 significance that it does on hosted ELF systems? */
548 if (TARGET_PCREL
&& flag_pic
== 0)
553 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
555 m68k_symbolic_jump
= "jra %a0";
557 else if (TARGET_ID_SHARED_LIBRARY
)
558 /* All addresses must be loaded from the GOT. */
560 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
563 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
565 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
568 /* No unconditional long branch */;
569 else if (TARGET_PCREL
)
570 m68k_symbolic_jump
= "bra%.l %c0";
572 m68k_symbolic_jump
= "bra%.l %p0";
573 /* Turn off function cse if we are doing PIC. We always want
574 function call to be done as `bsr foo@PLTPC'. */
575 /* ??? It's traditional to do this for -mpcrel too, but it isn't
576 clear how intentional that is. */
577 flag_no_function_cse
= 1;
580 switch (m68k_symbolic_call_var
)
582 case M68K_SYMBOLIC_CALL_JSR
:
583 m68k_symbolic_call
= "jsr %a0";
586 case M68K_SYMBOLIC_CALL_BSR_C
:
587 m68k_symbolic_call
= "bsr%.l %c0";
590 case M68K_SYMBOLIC_CALL_BSR_P
:
591 m68k_symbolic_call
= "bsr%.l %p0";
594 case M68K_SYMBOLIC_CALL_NONE
:
595 gcc_assert (m68k_symbolic_call
== NULL
);
602 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
603 if (align_labels
> 2)
605 warning (0, "-falign-labels=%d is not supported", align_labels
);
610 warning (0, "-falign-loops=%d is not supported", align_loops
);
615 SUBTARGET_OVERRIDE_OPTIONS
;
617 /* Setup scheduling options. */
619 m68k_sched_cpu
= CPU_CFV1
;
621 m68k_sched_cpu
= CPU_CFV2
;
623 m68k_sched_cpu
= CPU_CFV3
;
625 m68k_sched_cpu
= CPU_CFV4
;
628 m68k_sched_cpu
= CPU_UNKNOWN
;
629 flag_schedule_insns
= 0;
630 flag_schedule_insns_after_reload
= 0;
631 flag_modulo_sched
= 0;
634 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
636 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
637 m68k_sched_mac
= MAC_CF_EMAC
;
638 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
639 m68k_sched_mac
= MAC_CF_MAC
;
641 m68k_sched_mac
= MAC_NO
;
645 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
648 m68k_override_options_after_change (void)
650 if (m68k_sched_cpu
== CPU_UNKNOWN
)
652 flag_schedule_insns
= 0;
653 flag_schedule_insns_after_reload
= 0;
654 flag_modulo_sched
= 0;
658 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
659 given argument and NAME is the argument passed to -mcpu. Return NULL
660 if -mcpu was not passed. */
663 m68k_cpp_cpu_ident (const char *prefix
)
667 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
670 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
671 given argument and NAME is the name of the representative device for
672 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
675 m68k_cpp_cpu_family (const char *prefix
)
679 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
682 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
683 "interrupt_handler" attribute and interrupt_thread if FUNC has an
684 "interrupt_thread" attribute. Otherwise, return
685 m68k_fk_normal_function. */
687 enum m68k_function_kind
688 m68k_get_function_kind (tree func
)
692 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
694 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
696 return m68k_fk_interrupt_handler
;
698 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
700 return m68k_fk_interrupt_handler
;
702 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
704 return m68k_fk_interrupt_thread
;
706 return m68k_fk_normal_function
;
709 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
710 struct attribute_spec.handler. */
712 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
713 tree args ATTRIBUTE_UNUSED
,
714 int flags ATTRIBUTE_UNUSED
,
717 if (TREE_CODE (*node
) != FUNCTION_DECL
)
719 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
721 *no_add_attrs
= true;
724 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
726 error ("multiple interrupt attributes not allowed");
727 *no_add_attrs
= true;
731 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
733 error ("interrupt_thread is available only on fido");
734 *no_add_attrs
= true;
741 m68k_compute_frame_layout (void)
745 enum m68k_function_kind func_kind
=
746 m68k_get_function_kind (current_function_decl
);
747 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
748 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
750 /* Only compute the frame once per function.
751 Don't cache information until reload has been completed. */
752 if (current_frame
.funcdef_no
== current_function_funcdef_no
756 current_frame
.size
= (get_frame_size () + 3) & -4;
760 /* Interrupt thread does not need to save any register. */
761 if (!interrupt_thread
)
762 for (regno
= 0; regno
< 16; regno
++)
763 if (m68k_save_reg (regno
, interrupt_handler
))
765 mask
|= 1 << (regno
- D0_REG
);
768 current_frame
.offset
= saved
* 4;
769 current_frame
.reg_no
= saved
;
770 current_frame
.reg_mask
= mask
;
772 current_frame
.foffset
= 0;
774 if (TARGET_HARD_FLOAT
)
776 /* Interrupt thread does not need to save any register. */
777 if (!interrupt_thread
)
778 for (regno
= 16; regno
< 24; regno
++)
779 if (m68k_save_reg (regno
, interrupt_handler
))
781 mask
|= 1 << (regno
- FP0_REG
);
784 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
785 current_frame
.offset
+= current_frame
.foffset
;
787 current_frame
.fpu_no
= saved
;
788 current_frame
.fpu_mask
= mask
;
790 /* Remember what function this frame refers to. */
791 current_frame
.funcdef_no
= current_function_funcdef_no
;
794 /* Worker function for TARGET_CAN_ELIMINATE. */
797 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
799 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
803 m68k_initial_elimination_offset (int from
, int to
)
806 /* The arg pointer points 8 bytes before the start of the arguments,
807 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
808 frame pointer in most frames. */
809 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
810 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
811 return argptr_offset
;
813 m68k_compute_frame_layout ();
815 gcc_assert (to
== STACK_POINTER_REGNUM
);
818 case ARG_POINTER_REGNUM
:
819 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
820 case FRAME_POINTER_REGNUM
:
821 return current_frame
.offset
+ current_frame
.size
;
827 /* Refer to the array `regs_ever_live' to determine which registers
828 to save; `regs_ever_live[I]' is nonzero if register number I
829 is ever used in the function. This function is responsible for
830 knowing which registers should not be saved even if used.
831 Return true if we need to save REGNO. */
834 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
836 if (flag_pic
&& regno
== PIC_REG
)
838 if (crtl
->saves_all_registers
)
840 if (crtl
->uses_pic_offset_table
)
842 /* Reload may introduce constant pool references into a function
843 that thitherto didn't need a PIC register. Note that the test
844 above will not catch that case because we will only set
845 crtl->uses_pic_offset_table when emitting
846 the address reloads. */
847 if (crtl
->uses_const_pool
)
851 if (crtl
->calls_eh_return
)
856 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
857 if (test
== INVALID_REGNUM
)
864 /* Fixed regs we never touch. */
865 if (fixed_regs
[regno
])
868 /* The frame pointer (if it is such) is handled specially. */
869 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
872 /* Interrupt handlers must also save call_used_regs
873 if they are live or when calling nested functions. */
874 if (interrupt_handler
)
876 if (df_regs_ever_live_p (regno
))
879 if (!current_function_is_leaf
&& call_used_regs
[regno
])
883 /* Never need to save registers that aren't touched. */
884 if (!df_regs_ever_live_p (regno
))
887 /* Otherwise save everything that isn't call-clobbered. */
888 return !call_used_regs
[regno
];
891 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
892 the lowest memory address. COUNT is the number of registers to be
893 moved, with register REGNO + I being moved if bit I of MASK is set.
894 STORE_P specifies the direction of the move and ADJUST_STACK_P says
895 whether or not this is pre-decrement (if STORE_P) or post-increment
896 (if !STORE_P) operation. */
899 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
900 unsigned int count
, unsigned int regno
,
901 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
904 rtx body
, addr
, src
, operands
[2];
905 enum machine_mode mode
;
907 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
908 mode
= reg_raw_mode
[regno
];
913 src
= plus_constant (base
, (count
914 * GET_MODE_SIZE (mode
)
915 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
916 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
919 for (; mask
!= 0; mask
>>= 1, regno
++)
922 addr
= plus_constant (base
, offset
);
923 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
924 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
925 XVECEXP (body
, 0, i
++)
926 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
927 offset
+= GET_MODE_SIZE (mode
);
929 gcc_assert (i
== XVECLEN (body
, 0));
931 return emit_insn (body
);
934 /* Make INSN a frame-related instruction. */
937 m68k_set_frame_related (rtx insn
)
942 RTX_FRAME_RELATED_P (insn
) = 1;
943 body
= PATTERN (insn
);
944 if (GET_CODE (body
) == PARALLEL
)
945 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
946 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
949 /* Emit RTL for the "prologue" define_expand. */
952 m68k_expand_prologue (void)
954 HOST_WIDE_INT fsize_with_regs
;
955 rtx limit
, src
, dest
;
957 m68k_compute_frame_layout ();
959 if (flag_stack_usage_info
)
960 current_function_static_stack_size
961 = current_frame
.size
+ current_frame
.offset
;
963 /* If the stack limit is a symbol, we can check it here,
964 before actually allocating the space. */
965 if (crtl
->limit_stack
966 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
968 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
969 if (!m68k_legitimate_constant_p (Pmode
, limit
))
971 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
972 limit
= gen_rtx_REG (Pmode
, D0_REG
);
974 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
975 stack_pointer_rtx
, limit
),
976 stack_pointer_rtx
, limit
,
980 fsize_with_regs
= current_frame
.size
;
983 /* ColdFire's move multiple instructions do not allow pre-decrement
984 addressing. Add the size of movem saves to the initial stack
985 allocation instead. */
986 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
987 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
988 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
989 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
992 if (frame_pointer_needed
)
994 if (fsize_with_regs
== 0 && TUNE_68040
)
996 /* On the 68040, two separate moves are faster than link.w 0. */
997 dest
= gen_frame_mem (Pmode
,
998 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
999 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1000 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1001 stack_pointer_rtx
));
1003 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1004 m68k_set_frame_related
1005 (emit_insn (gen_link (frame_pointer_rtx
,
1006 GEN_INT (-4 - fsize_with_regs
))));
1009 m68k_set_frame_related
1010 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1011 m68k_set_frame_related
1012 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1014 GEN_INT (-fsize_with_regs
))));
1017 /* If the frame pointer is needed, emit a special barrier that
1018 will prevent the scheduler from moving stores to the frame
1019 before the stack adjustment. */
1020 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1022 else if (fsize_with_regs
!= 0)
1023 m68k_set_frame_related
1024 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1026 GEN_INT (-fsize_with_regs
))));
1028 if (current_frame
.fpu_mask
)
1030 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1032 m68k_set_frame_related
1033 (m68k_emit_movem (stack_pointer_rtx
,
1034 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1035 current_frame
.fpu_no
, FP0_REG
,
1036 current_frame
.fpu_mask
, true, true));
1041 /* If we're using moveml to save the integer registers,
1042 the stack pointer will point to the bottom of the moveml
1043 save area. Find the stack offset of the first FP register. */
1044 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1047 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1048 m68k_set_frame_related
1049 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1050 current_frame
.fpu_no
, FP0_REG
,
1051 current_frame
.fpu_mask
, true, false));
1055 /* If the stack limit is not a symbol, check it here.
1056 This has the disadvantage that it may be too late... */
1057 if (crtl
->limit_stack
)
1059 if (REG_P (stack_limit_rtx
))
1060 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1062 stack_pointer_rtx
, stack_limit_rtx
,
1065 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1066 warning (0, "stack limit expression is not supported");
1069 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1071 /* Store each register separately in the same order moveml does. */
1074 for (i
= 16; i
-- > 0; )
1075 if (current_frame
.reg_mask
& (1 << i
))
1077 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1078 dest
= gen_frame_mem (SImode
,
1079 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1080 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1085 if (TARGET_COLDFIRE
)
1086 /* The required register save space has already been allocated.
1087 The first register should be stored at (%sp). */
1088 m68k_set_frame_related
1089 (m68k_emit_movem (stack_pointer_rtx
, 0,
1090 current_frame
.reg_no
, D0_REG
,
1091 current_frame
.reg_mask
, true, false));
1093 m68k_set_frame_related
1094 (m68k_emit_movem (stack_pointer_rtx
,
1095 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1096 current_frame
.reg_no
, D0_REG
,
1097 current_frame
.reg_mask
, true, true));
1100 if (!TARGET_SEP_DATA
1101 && crtl
->uses_pic_offset_table
)
1102 emit_insn (gen_load_got (pic_offset_table_rtx
));
1105 /* Return true if a simple (return) instruction is sufficient for this
1106 instruction (i.e. if no epilogue is needed). */
1109 m68k_use_return_insn (void)
1111 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1114 m68k_compute_frame_layout ();
1115 return current_frame
.offset
== 0;
1118 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1119 SIBCALL_P says which.
1121 The function epilogue should not depend on the current stack pointer!
1122 It should use the frame pointer only, if there is a frame pointer.
1123 This is mandatory because of alloca; we also take advantage of it to
1124 omit stack adjustments before returning. */
1127 m68k_expand_epilogue (bool sibcall_p
)
1129 HOST_WIDE_INT fsize
, fsize_with_regs
;
1130 bool big
, restore_from_sp
;
1132 m68k_compute_frame_layout ();
1134 fsize
= current_frame
.size
;
1136 restore_from_sp
= false;
1138 /* FIXME : current_function_is_leaf below is too strong.
1139 What we really need to know there is if there could be pending
1140 stack adjustment needed at that point. */
1141 restore_from_sp
= (!frame_pointer_needed
1142 || (!cfun
->calls_alloca
1143 && current_function_is_leaf
));
1145 /* fsize_with_regs is the size we need to adjust the sp when
1146 popping the frame. */
1147 fsize_with_regs
= fsize
;
1148 if (TARGET_COLDFIRE
&& restore_from_sp
)
1150 /* ColdFire's move multiple instructions do not allow post-increment
1151 addressing. Add the size of movem loads to the final deallocation
1153 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1154 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1155 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1156 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1159 if (current_frame
.offset
+ fsize
>= 0x8000
1161 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1164 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1165 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1167 /* ColdFire's move multiple instructions do not support the
1168 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1169 stack-based restore. */
1170 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1171 GEN_INT (-(current_frame
.offset
+ fsize
)));
1172 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1173 gen_rtx_REG (Pmode
, A1_REG
),
1174 frame_pointer_rtx
));
1175 restore_from_sp
= true;
1179 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1185 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1187 /* Restore each register separately in the same order moveml does. */
1189 HOST_WIDE_INT offset
;
1191 offset
= current_frame
.offset
+ fsize
;
1192 for (i
= 0; i
< 16; i
++)
1193 if (current_frame
.reg_mask
& (1 << i
))
1199 /* Generate the address -OFFSET(%fp,%a1.l). */
1200 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1201 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1202 addr
= plus_constant (addr
, -offset
);
1204 else if (restore_from_sp
)
1205 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1207 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1208 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1209 gen_frame_mem (SImode
, addr
));
1210 offset
-= GET_MODE_SIZE (SImode
);
1213 else if (current_frame
.reg_mask
)
1216 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1217 gen_rtx_REG (Pmode
, A1_REG
),
1219 -(current_frame
.offset
+ fsize
),
1220 current_frame
.reg_no
, D0_REG
,
1221 current_frame
.reg_mask
, false, false);
1222 else if (restore_from_sp
)
1223 m68k_emit_movem (stack_pointer_rtx
, 0,
1224 current_frame
.reg_no
, D0_REG
,
1225 current_frame
.reg_mask
, false,
1228 m68k_emit_movem (frame_pointer_rtx
,
1229 -(current_frame
.offset
+ fsize
),
1230 current_frame
.reg_no
, D0_REG
,
1231 current_frame
.reg_mask
, false, false);
1234 if (current_frame
.fpu_no
> 0)
1237 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1238 gen_rtx_REG (Pmode
, A1_REG
),
1240 -(current_frame
.foffset
+ fsize
),
1241 current_frame
.fpu_no
, FP0_REG
,
1242 current_frame
.fpu_mask
, false, false);
1243 else if (restore_from_sp
)
1245 if (TARGET_COLDFIRE
)
1249 /* If we used moveml to restore the integer registers, the
1250 stack pointer will still point to the bottom of the moveml
1251 save area. Find the stack offset of the first FP
1253 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1256 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1257 m68k_emit_movem (stack_pointer_rtx
, offset
,
1258 current_frame
.fpu_no
, FP0_REG
,
1259 current_frame
.fpu_mask
, false, false);
1262 m68k_emit_movem (stack_pointer_rtx
, 0,
1263 current_frame
.fpu_no
, FP0_REG
,
1264 current_frame
.fpu_mask
, false, true);
1267 m68k_emit_movem (frame_pointer_rtx
,
1268 -(current_frame
.foffset
+ fsize
),
1269 current_frame
.fpu_no
, FP0_REG
,
1270 current_frame
.fpu_mask
, false, false);
1273 if (frame_pointer_needed
)
1274 emit_insn (gen_unlink (frame_pointer_rtx
));
1275 else if (fsize_with_regs
)
1276 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1278 GEN_INT (fsize_with_regs
)));
1280 if (crtl
->calls_eh_return
)
1281 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1283 EH_RETURN_STACKADJ_RTX
));
1286 emit_jump_insn (ret_rtx
);
1289 /* Return true if X is a valid comparison operator for the dbcc
1292 Note it rejects floating point comparison operators.
1293 (In the future we could use Fdbcc).
1295 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1298 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1300 switch (GET_CODE (x
))
1302 case EQ
: case NE
: case GTU
: case LTU
:
1306 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1308 case GT
: case LT
: case GE
: case LE
:
1309 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1315 /* Return nonzero if flags are currently in the 68881 flag register. */
1317 flags_in_68881 (void)
1319 /* We could add support for these in the future */
1320 return cc_status
.flags
& CC_IN_68881
;
1323 /* Return true if PARALLEL contains register REGNO. */
1325 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1329 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1332 if (GET_CODE (parallel
) != PARALLEL
)
1335 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1339 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1340 if (REG_P (x
) && REGNO (x
) == regno
)
1347 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1350 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1352 enum m68k_function_kind kind
;
1354 /* We cannot use sibcalls for nested functions because we use the
1355 static chain register for indirect calls. */
1356 if (CALL_EXPR_STATIC_CHAIN (exp
))
1359 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1361 /* Check that the return value locations are the same. For
1362 example that we aren't returning a value from the sibling in
1363 a D0 register but then need to transfer it to a A0 register. */
1367 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1369 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1371 /* Check that the values are equal or that the result the callee
1372 function returns is superset of what the current function returns. */
1373 if (!(rtx_equal_p (cfun_value
, call_value
)
1374 || (REG_P (cfun_value
)
1375 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1379 kind
= m68k_get_function_kind (current_function_decl
);
1380 if (kind
== m68k_fk_normal_function
)
1381 /* We can always sibcall from a normal function, because it's
1382 undefined if it is calling an interrupt function. */
1385 /* Otherwise we can only sibcall if the function kind is known to be
1387 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1393 /* On the m68k all args are always pushed. */
1396 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1397 enum machine_mode mode ATTRIBUTE_UNUSED
,
1398 const_tree type ATTRIBUTE_UNUSED
,
1399 bool named ATTRIBUTE_UNUSED
)
1405 m68k_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1406 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1408 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1410 *cum
+= (mode
!= BLKmode
1411 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1412 : (int_size_in_bytes (type
) + 3) & ~3);
1415 /* Convert X to a legitimate function call memory reference and return the
1419 m68k_legitimize_call_address (rtx x
)
1421 gcc_assert (MEM_P (x
));
1422 if (call_operand (XEXP (x
, 0), VOIDmode
))
1424 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1427 /* Likewise for sibling calls. */
1430 m68k_legitimize_sibcall_address (rtx x
)
1432 gcc_assert (MEM_P (x
));
1433 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1436 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1437 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1440 /* Convert X to a legitimate address and return it if successful. Otherwise
1443 For the 68000, we handle X+REG by loading X into a register R and
1444 using R+REG. R will go in an address reg and indexing will be used.
1445 However, if REG is a broken-out memory address or multiplication,
1446 nothing needs to be done because REG can certainly go in an address reg. */
1449 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1451 if (m68k_tls_symbol_p (x
))
1452 return m68k_legitimize_tls_address (x
);
1454 if (GET_CODE (x
) == PLUS
)
1456 int ch
= (x
) != (oldx
);
1459 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1461 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1464 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1466 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1469 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1473 if (GET_CODE (XEXP (x
, 1)) == REG
1474 && GET_CODE (XEXP (x
, 0)) == REG
)
1476 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1479 x
= force_operand (x
, 0);
1483 if (memory_address_p (mode
, x
))
1486 if (GET_CODE (XEXP (x
, 0)) == REG
1487 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1488 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1489 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1491 rtx temp
= gen_reg_rtx (Pmode
);
1492 rtx val
= force_operand (XEXP (x
, 1), 0);
1493 emit_move_insn (temp
, val
);
1496 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1497 && GET_CODE (XEXP (x
, 0)) == REG
)
1498 x
= force_operand (x
, 0);
1500 else if (GET_CODE (XEXP (x
, 1)) == REG
1501 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1502 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1503 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1505 rtx temp
= gen_reg_rtx (Pmode
);
1506 rtx val
= force_operand (XEXP (x
, 0), 0);
1507 emit_move_insn (temp
, val
);
1510 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1511 && GET_CODE (XEXP (x
, 1)) == REG
)
1512 x
= force_operand (x
, 0);
1520 /* Output a dbCC; jCC sequence. Note we do not handle the
1521 floating point version of this sequence (Fdbcc). We also
1522 do not handle alternative conditions when CC_NO_OVERFLOW is
1523 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1524 kick those out before we get here. */
1527 output_dbcc_and_branch (rtx
*operands
)
1529 switch (GET_CODE (operands
[3]))
1532 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1536 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1540 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1544 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1548 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1552 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1556 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1560 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1564 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1568 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1575 /* If the decrement is to be done in SImode, then we have
1576 to compensate for the fact that dbcc decrements in HImode. */
1577 switch (GET_MODE (operands
[0]))
1580 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1592 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1595 enum rtx_code op_code
= GET_CODE (op
);
1597 /* This does not produce a useful cc. */
1600 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1601 below. Swap the operands and change the op if these requirements
1602 are not fulfilled. */
1603 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1607 operand1
= operand2
;
1609 op_code
= swap_condition (op_code
);
1611 loperands
[0] = operand1
;
1612 if (GET_CODE (operand1
) == REG
)
1613 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1615 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1616 if (operand2
!= const0_rtx
)
1618 loperands
[2] = operand2
;
1619 if (GET_CODE (operand2
) == REG
)
1620 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1622 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1624 loperands
[4] = gen_label_rtx ();
1625 if (operand2
!= const0_rtx
)
1626 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1629 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1630 output_asm_insn ("tst%.l %0", loperands
);
1632 output_asm_insn ("cmp%.w #0,%0", loperands
);
1634 output_asm_insn ("jne %l4", loperands
);
1636 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1637 output_asm_insn ("tst%.l %1", loperands
);
1639 output_asm_insn ("cmp%.w #0,%1", loperands
);
1642 loperands
[5] = dest
;
1647 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1648 CODE_LABEL_NUMBER (loperands
[4]));
1649 output_asm_insn ("seq %5", loperands
);
1653 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1654 CODE_LABEL_NUMBER (loperands
[4]));
1655 output_asm_insn ("sne %5", loperands
);
1659 loperands
[6] = gen_label_rtx ();
1660 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1661 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1662 CODE_LABEL_NUMBER (loperands
[4]));
1663 output_asm_insn ("sgt %5", loperands
);
1664 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1665 CODE_LABEL_NUMBER (loperands
[6]));
1669 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1670 CODE_LABEL_NUMBER (loperands
[4]));
1671 output_asm_insn ("shi %5", loperands
);
1675 loperands
[6] = gen_label_rtx ();
1676 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1677 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1678 CODE_LABEL_NUMBER (loperands
[4]));
1679 output_asm_insn ("slt %5", loperands
);
1680 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1681 CODE_LABEL_NUMBER (loperands
[6]));
1685 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1686 CODE_LABEL_NUMBER (loperands
[4]));
1687 output_asm_insn ("scs %5", loperands
);
1691 loperands
[6] = gen_label_rtx ();
1692 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1693 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1694 CODE_LABEL_NUMBER (loperands
[4]));
1695 output_asm_insn ("sge %5", loperands
);
1696 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1697 CODE_LABEL_NUMBER (loperands
[6]));
1701 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1702 CODE_LABEL_NUMBER (loperands
[4]));
1703 output_asm_insn ("scc %5", loperands
);
1707 loperands
[6] = gen_label_rtx ();
1708 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1709 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1710 CODE_LABEL_NUMBER (loperands
[4]));
1711 output_asm_insn ("sle %5", loperands
);
1712 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1713 CODE_LABEL_NUMBER (loperands
[6]));
1717 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1718 CODE_LABEL_NUMBER (loperands
[4]));
1719 output_asm_insn ("sls %5", loperands
);
1729 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1731 operands
[0] = countop
;
1732 operands
[1] = dataop
;
1734 if (GET_CODE (countop
) == CONST_INT
)
1736 register int count
= INTVAL (countop
);
1737 /* If COUNT is bigger than size of storage unit in use,
1738 advance to the containing unit of same size. */
1739 if (count
> signpos
)
1741 int offset
= (count
& ~signpos
) / 8;
1742 count
= count
& signpos
;
1743 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1745 if (count
== signpos
)
1746 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1748 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1750 /* These three statements used to use next_insns_test_no...
1751 but it appears that this should do the same job. */
1753 && next_insn_tests_no_inequality (insn
))
1756 && next_insn_tests_no_inequality (insn
))
1759 && next_insn_tests_no_inequality (insn
))
1761 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1762 On some m68k variants unfortunately that's slower than btst.
1763 On 68000 and higher, that should also work for all HImode operands. */
1764 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1766 if (count
== 3 && DATA_REG_P (operands
[1])
1767 && next_insn_tests_no_inequality (insn
))
1769 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1770 return "move%.w %1,%%ccr";
1772 if (count
== 2 && DATA_REG_P (operands
[1])
1773 && next_insn_tests_no_inequality (insn
))
1775 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1776 return "move%.w %1,%%ccr";
1778 /* count == 1 followed by bvc/bvs and
1779 count == 0 followed by bcc/bcs are also possible, but need
1780 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1783 cc_status
.flags
= CC_NOT_NEGATIVE
;
1785 return "btst %0,%1";
1788 /* Return true if X is a legitimate base register. STRICT_P says
1789 whether we need strict checking. */
1792 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1794 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1795 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1800 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1801 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1804 /* Return true if X is a legitimate index register. STRICT_P says
1805 whether we need strict checking. */
1808 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1810 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1815 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1816 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1819 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1820 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1821 ADDRESS if so. STRICT_P says whether we need strict checking. */
1824 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1828 /* Check for a scale factor. */
1830 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1831 && GET_CODE (x
) == MULT
1832 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1833 && (INTVAL (XEXP (x
, 1)) == 2
1834 || INTVAL (XEXP (x
, 1)) == 4
1835 || (INTVAL (XEXP (x
, 1)) == 8
1836 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1838 scale
= INTVAL (XEXP (x
, 1));
1842 /* Check for a word extension. */
1843 if (!TARGET_COLDFIRE
1844 && GET_CODE (x
) == SIGN_EXTEND
1845 && GET_MODE (XEXP (x
, 0)) == HImode
)
1848 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1850 address
->scale
= scale
;
1858 /* Return true if X is an illegitimate symbolic constant. */
1861 m68k_illegitimate_symbolic_constant_p (rtx x
)
1865 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1867 split_const (x
, &base
, &offset
);
1868 if (GET_CODE (base
) == SYMBOL_REF
1869 && !offset_within_block_p (base
, INTVAL (offset
)))
1872 return m68k_tls_reference_p (x
, false);
1875 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1878 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1880 return m68k_illegitimate_symbolic_constant_p (x
);
1883 /* Return true if X is a legitimate constant address that can reach
1884 bytes in the range [X, X + REACH). STRICT_P says whether we need
1888 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1892 if (!CONSTANT_ADDRESS_P (x
))
1896 && !(strict_p
&& TARGET_PCREL
)
1897 && symbolic_operand (x
, VOIDmode
))
1900 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1902 split_const (x
, &base
, &offset
);
1903 if (GET_CODE (base
) == SYMBOL_REF
1904 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1908 return !m68k_tls_reference_p (x
, false);
1911 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1912 labels will become jump tables. */
1915 m68k_jump_table_ref_p (rtx x
)
1917 if (GET_CODE (x
) != LABEL_REF
)
1921 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1924 x
= next_nonnote_insn (x
);
1925 return x
&& JUMP_TABLE_DATA_P (x
);
1928 /* Return true if X is a legitimate address for values of mode MODE.
1929 STRICT_P says whether strict checking is needed. If the address
1930 is valid, describe its components in *ADDRESS. */
1933 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1934 bool strict_p
, struct m68k_address
*address
)
1938 memset (address
, 0, sizeof (*address
));
1940 if (mode
== BLKmode
)
1943 reach
= GET_MODE_SIZE (mode
);
1945 /* Check for (An) (mode 2). */
1946 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1952 /* Check for -(An) and (An)+ (modes 3 and 4). */
1953 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1954 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1956 address
->code
= GET_CODE (x
);
1957 address
->base
= XEXP (x
, 0);
1961 /* Check for (d16,An) (mode 5). */
1962 if (GET_CODE (x
) == PLUS
1963 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1964 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1965 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1967 address
->base
= XEXP (x
, 0);
1968 address
->offset
= XEXP (x
, 1);
1972 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1973 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1975 if (GET_CODE (x
) == PLUS
1976 && XEXP (x
, 0) == pic_offset_table_rtx
)
1978 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1979 they are invalid in this context. */
1980 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1982 address
->base
= XEXP (x
, 0);
1983 address
->offset
= XEXP (x
, 1);
1988 /* The ColdFire FPU only accepts addressing modes 2-5. */
1989 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1992 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1993 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1994 All these modes are variations of mode 7. */
1995 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1997 address
->offset
= x
;
2001 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2004 ??? do_tablejump creates these addresses before placing the target
2005 label, so we have to assume that unplaced labels are jump table
2006 references. It seems unlikely that we would ever generate indexed
2007 accesses to unplaced labels in other cases. */
2008 if (GET_CODE (x
) == PLUS
2009 && m68k_jump_table_ref_p (XEXP (x
, 1))
2010 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2012 address
->offset
= XEXP (x
, 1);
2016 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2017 (bd,An,Xn.SIZE*SCALE) addresses. */
2021 /* Check for a nonzero base displacement. */
2022 if (GET_CODE (x
) == PLUS
2023 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2025 address
->offset
= XEXP (x
, 1);
2029 /* Check for a suppressed index register. */
2030 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2036 /* Check for a suppressed base register. Do not allow this case
2037 for non-symbolic offsets as it effectively gives gcc freedom
2038 to treat data registers as base registers, which can generate
2041 && symbolic_operand (address
->offset
, VOIDmode
)
2042 && m68k_decompose_index (x
, strict_p
, address
))
2047 /* Check for a nonzero base displacement. */
2048 if (GET_CODE (x
) == PLUS
2049 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2050 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2052 address
->offset
= XEXP (x
, 1);
2057 /* We now expect the sum of a base and an index. */
2058 if (GET_CODE (x
) == PLUS
)
2060 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2061 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2063 address
->base
= XEXP (x
, 0);
2067 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2068 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2070 address
->base
= XEXP (x
, 1);
2077 /* Return true if X is a legitimate address for values of mode MODE.
2078 STRICT_P says whether strict checking is needed. */
2081 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2083 struct m68k_address address
;
2085 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2088 /* Return true if X is a memory, describing its address in ADDRESS if so.
2089 Apply strict checking if called during or after reload. */
2092 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2095 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2096 reload_in_progress
|| reload_completed
,
2100 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2103 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2105 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2108 /* Return true if X matches the 'Q' constraint. It must be a memory
2109 with a base address and no constant offset or index. */
2112 m68k_matches_q_p (rtx x
)
2114 struct m68k_address address
;
2116 return (m68k_legitimate_mem_p (x
, &address
)
2117 && address
.code
== UNKNOWN
2123 /* Return true if X matches the 'U' constraint. It must be a base address
2124 with a constant offset and no index. */
2127 m68k_matches_u_p (rtx x
)
2129 struct m68k_address address
;
2131 return (m68k_legitimate_mem_p (x
, &address
)
2132 && address
.code
== UNKNOWN
2138 /* Return GOT pointer. */
2143 if (pic_offset_table_rtx
== NULL_RTX
)
2144 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2146 crtl
->uses_pic_offset_table
= 1;
2148 return pic_offset_table_rtx
;
2151 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2153 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2154 RELOC_TLSIE
, RELOC_TLSLE
};
2156 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2158 /* Wrap symbol X into unspec representing relocation RELOC.
2159 BASE_REG - register that should be added to the result.
2160 TEMP_REG - if non-null, temporary register. */
2163 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2167 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2169 if (TARGET_COLDFIRE
&& use_x_p
)
2170 /* When compiling with -mx{got, tls} switch the code will look like this:
2172 move.l <X>@<RELOC>,<TEMP_REG>
2173 add.l <BASE_REG>,<TEMP_REG> */
2175 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2176 to put @RELOC after reference. */
2177 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2179 x
= gen_rtx_CONST (Pmode
, x
);
2181 if (temp_reg
== NULL
)
2183 gcc_assert (can_create_pseudo_p ());
2184 temp_reg
= gen_reg_rtx (Pmode
);
2187 emit_move_insn (temp_reg
, x
);
2188 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2193 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2195 x
= gen_rtx_CONST (Pmode
, x
);
2197 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2203 /* Helper for m68k_unwrap_symbol.
2204 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2205 sets *RELOC_PTR to relocation type for the symbol. */
2208 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2209 enum m68k_reloc
*reloc_ptr
)
2211 if (GET_CODE (orig
) == CONST
)
2214 enum m68k_reloc dummy
;
2218 if (reloc_ptr
== NULL
)
2221 /* Handle an addend. */
2222 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2223 && CONST_INT_P (XEXP (x
, 1)))
2226 if (GET_CODE (x
) == UNSPEC
)
2228 switch (XINT (x
, 1))
2230 case UNSPEC_RELOC16
:
2231 orig
= XVECEXP (x
, 0, 0);
2232 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2235 case UNSPEC_RELOC32
:
2236 if (unwrap_reloc32_p
)
2238 orig
= XVECEXP (x
, 0, 0);
2239 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2252 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2253 UNSPEC_RELOC32 wrappers. */
2256 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2258 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2261 /* Helper for m68k_final_prescan_insn. */
2264 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2268 if (m68k_unwrap_symbol (x
, true) != x
)
2269 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2273 gcc_assert (GET_CODE (x
) == CONST
);
2276 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2281 unspec
= XEXP (plus
, 0);
2282 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2283 addend
= XEXP (plus
, 1);
2284 gcc_assert (CONST_INT_P (addend
));
2286 /* We now have all the pieces, rearrange them. */
2288 /* Move symbol to plus. */
2289 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2291 /* Move plus inside unspec. */
2292 XVECEXP (unspec
, 0, 0) = plus
;
2294 /* Move unspec to top level of const. */
2295 XEXP (x
, 0) = unspec
;
2304 /* Prescan insn before outputing assembler for it. */
2307 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2308 rtx
*operands
, int n_operands
)
2312 /* Combine and, possibly, other optimizations may do good job
2314 (const (unspec [(symbol)]))
2316 (const (plus (unspec [(symbol)])
2318 The problem with this is emitting @TLS or @GOT decorations.
2319 The decoration is emitted when processing (unspec), so the
2320 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2322 It seems that the easiest solution to this is to convert such
2324 (const (unspec [(plus (symbol)
2326 Note, that the top level of operand remains intact, so we don't have
2327 to patch up anything outside of the operand. */
2329 for (i
= 0; i
< n_operands
; ++i
)
2335 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2339 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2340 If REG is non-null, use it; generate new pseudo otherwise. */
2343 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2347 if (reg
== NULL_RTX
)
2349 gcc_assert (can_create_pseudo_p ());
2350 reg
= gen_reg_rtx (Pmode
);
2353 insn
= emit_move_insn (reg
, x
);
2354 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2356 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2361 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2365 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2367 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2369 x
= gen_rtx_MEM (Pmode
, x
);
2370 MEM_READONLY_P (x
) = 1;
2375 /* Legitimize PIC addresses. If the address is already
2376 position-independent, we return ORIG. Newly generated
2377 position-independent addresses go to REG. If we need more
2378 than one register, we lose.
2380 An address is legitimized by making an indirect reference
2381 through the Global Offset Table with the name of the symbol
2384 The assembler and linker are responsible for placing the
2385 address of the symbol in the GOT. The function prologue
2386 is responsible for initializing a5 to the starting address
2389 The assembler is also responsible for translating a symbol name
2390 into a constant displacement from the start of the GOT.
2392 A quick example may make things a little clearer:
2394 When not generating PIC code to store the value 12345 into _foo
2395 we would generate the following code:
2399 When generating PIC two transformations are made. First, the compiler
2400 loads the address of foo into a register. So the first transformation makes:
2405 The code in movsi will intercept the lea instruction and call this
2406 routine which will transform the instructions into:
2408 movel a5@(_foo:w), a0
2412 That (in a nutshell) is how *all* symbol and label references are
2416 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2421 /* First handle a simple SYMBOL_REF or LABEL_REF */
2422 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2426 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2427 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2429 else if (GET_CODE (orig
) == CONST
)
2433 /* Make sure this has not already been legitimized. */
2434 if (m68k_unwrap_symbol (orig
, true) != orig
)
2439 /* legitimize both operands of the PLUS */
2440 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2442 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2443 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2444 base
== reg
? 0 : reg
);
2446 if (GET_CODE (orig
) == CONST_INT
)
2447 pic_ref
= plus_constant (base
, INTVAL (orig
));
2449 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2455 /* The __tls_get_addr symbol. */
2456 static GTY(()) rtx m68k_tls_get_addr
;
2458 /* Return SYMBOL_REF for __tls_get_addr. */
2461 m68k_get_tls_get_addr (void)
2463 if (m68k_tls_get_addr
== NULL_RTX
)
2464 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2466 return m68k_tls_get_addr
;
2469 /* Return libcall result in A0 instead of usual D0. */
2470 static bool m68k_libcall_value_in_a0_p
= false;
2472 /* Emit instruction sequence that calls __tls_get_addr. X is
2473 the TLS symbol we are referencing and RELOC is the symbol type to use
2474 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2475 emitted. A pseudo register with result of __tls_get_addr call is
2479 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2485 /* Emit the call sequence. */
2488 /* FIXME: Unfortunately, emit_library_call_value does not
2489 consider (plus (%a5) (const (unspec))) to be a good enough
2490 operand for push, so it forces it into a register. The bad
2491 thing about this is that combiner, due to copy propagation and other
2492 optimizations, sometimes can not later fix this. As a consequence,
2493 additional register may be allocated resulting in a spill.
2494 For reference, see args processing loops in
2495 calls.c:emit_library_call_value_1.
2496 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2497 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2499 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2500 is the simpliest way of generating a call. The difference between
2501 __tls_get_addr() and libcall is that the result is returned in D0
2502 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2503 which temporarily switches returning the result to A0. */
2505 m68k_libcall_value_in_a0_p
= true;
2506 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2507 Pmode
, 1, x
, Pmode
);
2508 m68k_libcall_value_in_a0_p
= false;
2510 insns
= get_insns ();
2513 gcc_assert (can_create_pseudo_p ());
2514 dest
= gen_reg_rtx (Pmode
);
2515 emit_libcall_block (insns
, dest
, a0
, eqv
);
2520 /* The __tls_get_addr symbol. */
2521 static GTY(()) rtx m68k_read_tp
;
2523 /* Return SYMBOL_REF for __m68k_read_tp. */
2526 m68k_get_m68k_read_tp (void)
2528 if (m68k_read_tp
== NULL_RTX
)
2529 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2531 return m68k_read_tp
;
2534 /* Emit instruction sequence that calls __m68k_read_tp.
2535 A pseudo register with result of __m68k_read_tp call is returned. */
2538 m68k_call_m68k_read_tp (void)
2547 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2548 is the simpliest way of generating a call. The difference between
2549 __m68k_read_tp() and libcall is that the result is returned in D0
2550 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2551 which temporarily switches returning the result to A0. */
2553 /* Emit the call sequence. */
2554 m68k_libcall_value_in_a0_p
= true;
2555 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2557 m68k_libcall_value_in_a0_p
= false;
2558 insns
= get_insns ();
2561 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2562 share the m68k_read_tp result with other IE/LE model accesses. */
2563 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2565 gcc_assert (can_create_pseudo_p ());
2566 dest
= gen_reg_rtx (Pmode
);
2567 emit_libcall_block (insns
, dest
, a0
, eqv
);
2572 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2573 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2577 m68k_legitimize_tls_address (rtx orig
)
2579 switch (SYMBOL_REF_TLS_MODEL (orig
))
2581 case TLS_MODEL_GLOBAL_DYNAMIC
:
2582 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2585 case TLS_MODEL_LOCAL_DYNAMIC
:
2591 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2592 share the LDM result with other LD model accesses. */
2593 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2596 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2598 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2600 if (can_create_pseudo_p ())
2601 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2607 case TLS_MODEL_INITIAL_EXEC
:
2612 a0
= m68k_call_m68k_read_tp ();
2614 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2615 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2617 if (can_create_pseudo_p ())
2618 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2624 case TLS_MODEL_LOCAL_EXEC
:
2629 a0
= m68k_call_m68k_read_tp ();
2631 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2633 if (can_create_pseudo_p ())
2634 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2647 /* Return true if X is a TLS symbol. */
2650 m68k_tls_symbol_p (rtx x
)
2652 if (!TARGET_HAVE_TLS
)
2655 if (GET_CODE (x
) != SYMBOL_REF
)
2658 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2661 /* Helper for m68k_tls_referenced_p. */
2664 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2666 /* Note: this is not the same as m68k_tls_symbol_p. */
2667 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2668 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2670 /* Don't recurse into legitimate TLS references. */
2671 if (m68k_tls_reference_p (*x_ptr
, true))
2677 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2678 though illegitimate one.
2679 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2682 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2684 if (!TARGET_HAVE_TLS
)
2688 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2691 enum m68k_reloc reloc
= RELOC_GOT
;
2693 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2694 && TLS_RELOC_P (reloc
));
2700 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2702 /* Return the type of move that should be used for integer I. */
2705 m68k_const_method (HOST_WIDE_INT i
)
2712 /* The ColdFire doesn't have byte or word operations. */
2713 /* FIXME: This may not be useful for the m68060 either. */
2714 if (!TARGET_COLDFIRE
)
2716 /* if -256 < N < 256 but N is not in range for a moveq
2717 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2718 if (USE_MOVQ (i
^ 0xff))
2720 /* Likewise, try with not.w */
2721 if (USE_MOVQ (i
^ 0xffff))
2723 /* This is the only value where neg.w is useful */
2728 /* Try also with swap. */
2730 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2735 /* Try using MVZ/MVS with an immediate value to load constants. */
2736 if (i
>= 0 && i
<= 65535)
2738 if (i
>= -32768 && i
<= 32767)
2742 /* Otherwise, use move.l */
2746 /* Return the cost of moving constant I into a data register. */
2749 const_int_cost (HOST_WIDE_INT i
)
2751 switch (m68k_const_method (i
))
2754 /* Constants between -128 and 127 are cheap due to moveq. */
2762 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2772 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2773 int *total
, bool speed ATTRIBUTE_UNUSED
)
2778 /* Constant zero is super cheap due to clr instruction. */
2779 if (x
== const0_rtx
)
2782 *total
= const_int_cost (INTVAL (x
));
2792 /* Make 0.0 cheaper than other floating constants to
2793 encourage creating tstsf and tstdf insns. */
2794 if (outer_code
== COMPARE
2795 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2801 /* These are vaguely right for a 68020. */
2802 /* The costs for long multiply have been adjusted to work properly
2803 in synth_mult on the 68020, relative to an average of the time
2804 for add and the time for shift, taking away a little more because
2805 sometimes move insns are needed. */
2806 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2811 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2812 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2814 : TARGET_COLDFIRE ? 3 : 13)
2819 : TUNE_68000_10 ? 5 \
2820 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2821 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2823 : TARGET_COLDFIRE ? 2 : 8)
2826 (TARGET_CF_HWDIV ? 11 \
2827 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2830 /* An lea costs about three times as much as a simple add. */
2831 if (GET_MODE (x
) == SImode
2832 && GET_CODE (XEXP (x
, 1)) == REG
2833 && GET_CODE (XEXP (x
, 0)) == MULT
2834 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2835 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2836 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2837 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2838 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2840 /* lea an@(dx:l:i),am */
2841 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2851 *total
= COSTS_N_INSNS(1);
2856 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2858 if (INTVAL (XEXP (x
, 1)) < 16)
2859 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2861 /* We're using clrw + swap for these cases. */
2862 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2865 *total
= COSTS_N_INSNS (10); /* Worst case. */
2868 /* A shift by a big integer takes an extra instruction. */
2869 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2870 && (INTVAL (XEXP (x
, 1)) == 16))
2872 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2875 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2876 && !(INTVAL (XEXP (x
, 1)) > 0
2877 && INTVAL (XEXP (x
, 1)) <= 8))
2879 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2885 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2886 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2887 && GET_MODE (x
) == SImode
)
2888 *total
= COSTS_N_INSNS (MULW_COST
);
2889 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2890 *total
= COSTS_N_INSNS (MULW_COST
);
2892 *total
= COSTS_N_INSNS (MULL_COST
);
2899 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2900 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2901 else if (TARGET_CF_HWDIV
)
2902 *total
= COSTS_N_INSNS (18);
2904 *total
= COSTS_N_INSNS (43); /* div.l */
2908 if (outer_code
== COMPARE
)
2917 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2921 output_move_const_into_data_reg (rtx
*operands
)
2925 i
= INTVAL (operands
[1]);
2926 switch (m68k_const_method (i
))
2929 return "mvzw %1,%0";
2931 return "mvsw %1,%0";
2933 return "moveq %1,%0";
2936 operands
[1] = GEN_INT (i
^ 0xff);
2937 return "moveq %1,%0\n\tnot%.b %0";
2940 operands
[1] = GEN_INT (i
^ 0xffff);
2941 return "moveq %1,%0\n\tnot%.w %0";
2944 return "moveq #-128,%0\n\tneg%.w %0";
2949 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2950 return "moveq %1,%0\n\tswap %0";
2953 return "move%.l %1,%0";
2959 /* Return true if I can be handled by ISA B's mov3q instruction. */
2962 valid_mov3q_const (HOST_WIDE_INT i
)
2964 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2967 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2968 I is the value of OPERANDS[1]. */
2971 output_move_simode_const (rtx
*operands
)
2977 src
= INTVAL (operands
[1]);
2979 && (DATA_REG_P (dest
) || MEM_P (dest
))
2980 /* clr insns on 68000 read before writing. */
2981 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2982 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2984 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2985 return "mov3q%.l %1,%0";
2986 else if (src
== 0 && ADDRESS_REG_P (dest
))
2987 return "sub%.l %0,%0";
2988 else if (DATA_REG_P (dest
))
2989 return output_move_const_into_data_reg (operands
);
2990 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2992 if (valid_mov3q_const (src
))
2993 return "mov3q%.l %1,%0";
2994 return "move%.w %1,%0";
2996 else if (MEM_P (dest
)
2997 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2998 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2999 && IN_RANGE (src
, -0x8000, 0x7fff))
3001 if (valid_mov3q_const (src
))
3002 return "mov3q%.l %1,%-";
3005 return "move%.l %1,%0";
3009 output_move_simode (rtx
*operands
)
3011 if (GET_CODE (operands
[1]) == CONST_INT
)
3012 return output_move_simode_const (operands
);
3013 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3014 || GET_CODE (operands
[1]) == CONST
)
3015 && push_operand (operands
[0], SImode
))
3017 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3018 || GET_CODE (operands
[1]) == CONST
)
3019 && ADDRESS_REG_P (operands
[0]))
3020 return "lea %a1,%0";
3021 return "move%.l %1,%0";
3025 output_move_himode (rtx
*operands
)
3027 if (GET_CODE (operands
[1]) == CONST_INT
)
3029 if (operands
[1] == const0_rtx
3030 && (DATA_REG_P (operands
[0])
3031 || GET_CODE (operands
[0]) == MEM
)
3032 /* clr insns on 68000 read before writing. */
3033 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3034 || !(GET_CODE (operands
[0]) == MEM
3035 && MEM_VOLATILE_P (operands
[0]))))
3037 else if (operands
[1] == const0_rtx
3038 && ADDRESS_REG_P (operands
[0]))
3039 return "sub%.l %0,%0";
3040 else if (DATA_REG_P (operands
[0])
3041 && INTVAL (operands
[1]) < 128
3042 && INTVAL (operands
[1]) >= -128)
3043 return "moveq %1,%0";
3044 else if (INTVAL (operands
[1]) < 0x8000
3045 && INTVAL (operands
[1]) >= -0x8000)
3046 return "move%.w %1,%0";
3048 else if (CONSTANT_P (operands
[1]))
3049 return "move%.l %1,%0";
3050 return "move%.w %1,%0";
3054 output_move_qimode (rtx
*operands
)
3056 /* 68k family always modifies the stack pointer by at least 2, even for
3057 byte pushes. The 5200 (ColdFire) does not do this. */
3059 /* This case is generated by pushqi1 pattern now. */
3060 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3061 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3062 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3063 && ! ADDRESS_REG_P (operands
[1])
3064 && ! TARGET_COLDFIRE
));
3066 /* clr and st insns on 68000 read before writing. */
3067 if (!ADDRESS_REG_P (operands
[0])
3068 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3069 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3071 if (operands
[1] == const0_rtx
)
3073 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3074 && GET_CODE (operands
[1]) == CONST_INT
3075 && (INTVAL (operands
[1]) & 255) == 255)
3081 if (GET_CODE (operands
[1]) == CONST_INT
3082 && DATA_REG_P (operands
[0])
3083 && INTVAL (operands
[1]) < 128
3084 && INTVAL (operands
[1]) >= -128)
3085 return "moveq %1,%0";
3086 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3087 return "sub%.l %0,%0";
3088 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3089 return "move%.l %1,%0";
3090 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3091 from address registers. */
3092 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3093 return "move%.w %1,%0";
3094 return "move%.b %1,%0";
3098 output_move_stricthi (rtx
*operands
)
3100 if (operands
[1] == const0_rtx
3101 /* clr insns on 68000 read before writing. */
3102 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3103 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3105 return "move%.w %1,%0";
3109 output_move_strictqi (rtx
*operands
)
3111 if (operands
[1] == const0_rtx
3112 /* clr insns on 68000 read before writing. */
3113 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3114 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3116 return "move%.b %1,%0";
3119 /* Return the best assembler insn template
3120 for moving operands[1] into operands[0] as a fullword. */
3123 singlemove_string (rtx
*operands
)
3125 if (GET_CODE (operands
[1]) == CONST_INT
)
3126 return output_move_simode_const (operands
);
3127 return "move%.l %1,%0";
3131 /* Output assembler or rtl code to perform a doubleword move insn
3132 with operands OPERANDS.
3133 Pointers to 3 helper functions should be specified:
3134 HANDLE_REG_ADJUST to adjust a register by a small value,
3135 HANDLE_COMPADR to compute an address and
3136 HANDLE_MOVSI to move 4 bytes. */
3139 handle_move_double (rtx operands
[2],
3140 void (*handle_reg_adjust
) (rtx
, int),
3141 void (*handle_compadr
) (rtx
[2]),
3142 void (*handle_movsi
) (rtx
[2]))
3146 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3151 rtx addreg0
= 0, addreg1
= 0;
3152 int dest_overlapped_low
= 0;
3153 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3158 /* First classify both operands. */
3160 if (REG_P (operands
[0]))
3162 else if (offsettable_memref_p (operands
[0]))
3164 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3166 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3168 else if (GET_CODE (operands
[0]) == MEM
)
3173 if (REG_P (operands
[1]))
3175 else if (CONSTANT_P (operands
[1]))
3177 else if (offsettable_memref_p (operands
[1]))
3179 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3181 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3183 else if (GET_CODE (operands
[1]) == MEM
)
3188 /* Check for the cases that the operand constraints are not supposed
3189 to allow to happen. Generating code for these cases is
3191 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3193 /* If one operand is decrementing and one is incrementing
3194 decrement the former register explicitly
3195 and change that operand into ordinary indexing. */
3197 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3199 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3201 handle_reg_adjust (operands
[0], -size
);
3203 if (GET_MODE (operands
[1]) == XFmode
)
3204 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3205 else if (GET_MODE (operands
[0]) == DFmode
)
3206 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3208 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3211 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3213 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3215 handle_reg_adjust (operands
[1], -size
);
3217 if (GET_MODE (operands
[1]) == XFmode
)
3218 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3219 else if (GET_MODE (operands
[1]) == DFmode
)
3220 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3222 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3226 /* If an operand is an unoffsettable memory ref, find a register
3227 we can increment temporarily to make it refer to the second word. */
3229 if (optype0
== MEMOP
)
3230 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3232 if (optype1
== MEMOP
)
3233 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3235 /* Ok, we can do one word at a time.
3236 Normally we do the low-numbered word first,
3237 but if either operand is autodecrementing then we
3238 do the high-numbered word first.
3240 In either case, set up in LATEHALF the operands to use
3241 for the high-numbered word and in some cases alter the
3242 operands in OPERANDS to be suitable for the low-numbered word. */
3246 if (optype0
== REGOP
)
3248 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3249 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3251 else if (optype0
== OFFSOP
)
3253 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3254 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3258 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3259 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3262 if (optype1
== REGOP
)
3264 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3265 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3267 else if (optype1
== OFFSOP
)
3269 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3270 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3272 else if (optype1
== CNSTOP
)
3274 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3279 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3280 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3281 operands
[1] = GEN_INT (l
[0]);
3282 middlehalf
[1] = GEN_INT (l
[1]);
3283 latehalf
[1] = GEN_INT (l
[2]);
3287 /* No non-CONST_DOUBLE constant should ever appear
3289 gcc_assert (!CONSTANT_P (operands
[1]));
3294 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3295 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3299 /* size is not 12: */
3301 if (optype0
== REGOP
)
3302 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3303 else if (optype0
== OFFSOP
)
3304 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3306 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3308 if (optype1
== REGOP
)
3309 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3310 else if (optype1
== OFFSOP
)
3311 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3312 else if (optype1
== CNSTOP
)
3313 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3315 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3318 /* If insn is effectively movd N(sp),-(sp) then we will do the
3319 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3320 for the low word as well, to compensate for the first decrement of sp. */
3321 if (optype0
== PUSHOP
3322 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3323 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3324 operands
[1] = middlehalf
[1] = latehalf
[1];
3326 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3327 if the upper part of reg N does not appear in the MEM, arrange to
3328 emit the move late-half first. Otherwise, compute the MEM address
3329 into the upper part of N and use that as a pointer to the memory
3331 if (optype0
== REGOP
3332 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3334 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3336 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3337 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3339 /* If both halves of dest are used in the src memory address,
3340 compute the address into latehalf of dest.
3341 Note that this can't happen if the dest is two data regs. */
3343 xops
[0] = latehalf
[0];
3344 xops
[1] = XEXP (operands
[1], 0);
3346 handle_compadr (xops
);
3347 if (GET_MODE (operands
[1]) == XFmode
)
3349 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3350 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3351 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3355 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3356 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3360 && reg_overlap_mentioned_p (middlehalf
[0],
3361 XEXP (operands
[1], 0)))
3363 /* Check for two regs used by both source and dest.
3364 Note that this can't happen if the dest is all data regs.
3365 It can happen if the dest is d6, d7, a0.
3366 But in that case, latehalf is an addr reg, so
3367 the code at compadr does ok. */
3369 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3370 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3373 /* JRV says this can't happen: */
3374 gcc_assert (!addreg0
&& !addreg1
);
3376 /* Only the middle reg conflicts; simply put it last. */
3377 handle_movsi (operands
);
3378 handle_movsi (latehalf
);
3379 handle_movsi (middlehalf
);
3383 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3384 /* If the low half of dest is mentioned in the source memory
3385 address, the arrange to emit the move late half first. */
3386 dest_overlapped_low
= 1;
3389 /* If one or both operands autodecrementing,
3390 do the two words, high-numbered first. */
3392 /* Likewise, the first move would clobber the source of the second one,
3393 do them in the other order. This happens only for registers;
3394 such overlap can't happen in memory unless the user explicitly
3395 sets it up, and that is an undefined circumstance. */
3397 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3398 || (optype0
== REGOP
&& optype1
== REGOP
3399 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3400 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3401 || dest_overlapped_low
)
3403 /* Make any unoffsettable addresses point at high-numbered word. */
3405 handle_reg_adjust (addreg0
, size
- 4);
3407 handle_reg_adjust (addreg1
, size
- 4);
3410 handle_movsi (latehalf
);
3412 /* Undo the adds we just did. */
3414 handle_reg_adjust (addreg0
, -4);
3416 handle_reg_adjust (addreg1
, -4);
3420 handle_movsi (middlehalf
);
3423 handle_reg_adjust (addreg0
, -4);
3425 handle_reg_adjust (addreg1
, -4);
3428 /* Do low-numbered word. */
3430 handle_movsi (operands
);
3434 /* Normal case: do the two words, low-numbered first. */
3436 m68k_final_prescan_insn (NULL
, operands
, 2);
3437 handle_movsi (operands
);
3439 /* Do the middle one of the three words for long double */
3443 handle_reg_adjust (addreg0
, 4);
3445 handle_reg_adjust (addreg1
, 4);
3447 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3448 handle_movsi (middlehalf
);
3451 /* Make any unoffsettable addresses point at high-numbered word. */
3453 handle_reg_adjust (addreg0
, 4);
3455 handle_reg_adjust (addreg1
, 4);
3458 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3459 handle_movsi (latehalf
);
3461 /* Undo the adds we just did. */
3463 handle_reg_adjust (addreg0
, -(size
- 4));
3465 handle_reg_adjust (addreg1
, -(size
- 4));
3470 /* Output assembler code to adjust REG by N. */
3472 output_reg_adjust (rtx reg
, int n
)
3476 gcc_assert (GET_MODE (reg
) == SImode
3477 && -12 <= n
&& n
!= 0 && n
<= 12);
3482 s
= "add%.l #12,%0";
3486 s
= "addq%.l #8,%0";
3490 s
= "addq%.l #4,%0";
3494 s
= "sub%.l #12,%0";
3498 s
= "subq%.l #8,%0";
3502 s
= "subq%.l #4,%0";
3510 output_asm_insn (s
, ®
);
3513 /* Emit rtl code to adjust REG by N. */
3515 emit_reg_adjust (rtx reg1
, int n
)
3519 gcc_assert (GET_MODE (reg1
) == SImode
3520 && -12 <= n
&& n
!= 0 && n
<= 12);
3522 reg1
= copy_rtx (reg1
);
3523 reg2
= copy_rtx (reg1
);
3526 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3528 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3533 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3535 output_compadr (rtx operands
[2])
3537 output_asm_insn ("lea %a1,%0", operands
);
3540 /* Output the best assembler insn for moving operands[1] into operands[0]
3543 output_movsi (rtx operands
[2])
3545 output_asm_insn (singlemove_string (operands
), operands
);
3548 /* Copy OP and change its mode to MODE. */
3550 copy_operand (rtx op
, enum machine_mode mode
)
3552 /* ??? This looks really ugly. There must be a better way
3553 to change a mode on the operand. */
3554 if (GET_MODE (op
) != VOIDmode
)
3557 op
= gen_rtx_REG (mode
, REGNO (op
));
3561 PUT_MODE (op
, mode
);
3568 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3570 emit_movsi (rtx operands
[2])
3572 operands
[0] = copy_operand (operands
[0], SImode
);
3573 operands
[1] = copy_operand (operands
[1], SImode
);
3575 emit_insn (gen_movsi (operands
[0], operands
[1]));
3578 /* Output assembler code to perform a doubleword move insn
3579 with operands OPERANDS. */
3581 output_move_double (rtx
*operands
)
3583 handle_move_double (operands
,
3584 output_reg_adjust
, output_compadr
, output_movsi
);
3589 /* Output rtl code to perform a doubleword move insn
3590 with operands OPERANDS. */
3592 m68k_emit_move_double (rtx operands
[2])
3594 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3597 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3598 new rtx with the correct mode. */
3601 force_mode (enum machine_mode mode
, rtx orig
)
3603 if (mode
== GET_MODE (orig
))
3606 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3609 return gen_rtx_REG (mode
, REGNO (orig
));
3613 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3615 return reg_renumber
&& FP_REG_P (op
);
3618 /* Emit insns to move operands[1] into operands[0].
3620 Return 1 if we have written out everything that needs to be done to
3621 do the move. Otherwise, return 0 and the caller will emit the move
3624 Note SCRATCH_REG may not be in the proper mode depending on how it
3625 will be used. This routine is responsible for creating a new copy
3626 of SCRATCH_REG in the proper mode. */
3629 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3631 register rtx operand0
= operands
[0];
3632 register rtx operand1
= operands
[1];
3636 && reload_in_progress
&& GET_CODE (operand0
) == REG
3637 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3638 operand0
= reg_equiv_mem (REGNO (operand0
));
3639 else if (scratch_reg
3640 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3641 && GET_CODE (SUBREG_REG (operand0
)) == REG
3642 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3644 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3645 the code which tracks sets/uses for delete_output_reload. */
3646 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3647 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3648 SUBREG_BYTE (operand0
));
3649 operand0
= alter_subreg (&temp
);
3653 && reload_in_progress
&& GET_CODE (operand1
) == REG
3654 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3655 operand1
= reg_equiv_mem (REGNO (operand1
));
3656 else if (scratch_reg
3657 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3658 && GET_CODE (SUBREG_REG (operand1
)) == REG
3659 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3661 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3662 the code which tracks sets/uses for delete_output_reload. */
3663 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3664 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3665 SUBREG_BYTE (operand1
));
3666 operand1
= alter_subreg (&temp
);
3669 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3670 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3671 != XEXP (operand0
, 0)))
3672 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3673 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3674 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3675 != XEXP (operand1
, 0)))
3676 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3678 /* Handle secondary reloads for loads/stores of FP registers where
3679 the address is symbolic by using the scratch register */
3680 if (fp_reg_operand (operand0
, mode
)
3681 && ((GET_CODE (operand1
) == MEM
3682 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3683 || ((GET_CODE (operand1
) == SUBREG
3684 && GET_CODE (XEXP (operand1
, 0)) == MEM
3685 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3688 if (GET_CODE (operand1
) == SUBREG
)
3689 operand1
= XEXP (operand1
, 0);
3691 /* SCRATCH_REG will hold an address. We want
3692 it in SImode regardless of what mode it was originally given
3694 scratch_reg
= force_mode (SImode
, scratch_reg
);
3696 /* D might not fit in 14 bits either; for such cases load D into
3698 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3700 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3701 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3703 XEXP (XEXP (operand1
, 0), 0),
3707 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3708 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3709 gen_rtx_MEM (mode
, scratch_reg
)));
3712 else if (fp_reg_operand (operand1
, mode
)
3713 && ((GET_CODE (operand0
) == MEM
3714 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3715 || ((GET_CODE (operand0
) == SUBREG
)
3716 && GET_CODE (XEXP (operand0
, 0)) == MEM
3717 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3720 if (GET_CODE (operand0
) == SUBREG
)
3721 operand0
= XEXP (operand0
, 0);
3723 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3724 it in SIMODE regardless of what mode it was originally given
3726 scratch_reg
= force_mode (SImode
, scratch_reg
);
3728 /* D might not fit in 14 bits either; for such cases load D into
3730 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3732 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3733 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3736 XEXP (XEXP (operand0
, 0),
3741 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3742 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3746 /* Handle secondary reloads for loads of FP registers from constant
3747 expressions by forcing the constant into memory.
3749 use scratch_reg to hold the address of the memory location.
3751 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3752 NO_REGS when presented with a const_int and an register class
3753 containing only FP registers. Doing so unfortunately creates
3754 more problems than it solves. Fix this for 2.5. */
3755 else if (fp_reg_operand (operand0
, mode
)
3756 && CONSTANT_P (operand1
)
3761 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3762 it in SIMODE regardless of what mode it was originally given
3764 scratch_reg
= force_mode (SImode
, scratch_reg
);
3766 /* Force the constant into memory and put the address of the
3767 memory location into scratch_reg. */
3768 xoperands
[0] = scratch_reg
;
3769 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3770 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3772 /* Now load the destination register. */
3773 emit_insn (gen_rtx_SET (mode
, operand0
,
3774 gen_rtx_MEM (mode
, scratch_reg
)));
3778 /* Now have insn-emit do whatever it normally does. */
3782 /* Split one or more DImode RTL references into pairs of SImode
3783 references. The RTL can be REG, offsettable MEM, integer constant, or
3784 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3785 split and "num" is its length. lo_half and hi_half are output arrays
3786 that parallel "operands". */
3789 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3793 rtx op
= operands
[num
];
3795 /* simplify_subreg refuses to split volatile memory addresses,
3796 but we still have to handle it. */
3797 if (GET_CODE (op
) == MEM
)
3799 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3800 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3804 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3805 GET_MODE (op
) == VOIDmode
3806 ? DImode
: GET_MODE (op
), 4);
3807 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3808 GET_MODE (op
) == VOIDmode
3809 ? DImode
: GET_MODE (op
), 0);
3814 /* Split X into a base and a constant offset, storing them in *BASE
3815 and *OFFSET respectively. */
3818 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3821 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3823 *offset
+= INTVAL (XEXP (x
, 1));
3829 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3830 instruction. STORE_P says whether the move is a load or store.
3832 If the instruction uses post-increment or pre-decrement addressing,
3833 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3834 adjustment. This adjustment will be made by the first element of
3835 PARALLEL, with the loads or stores starting at element 1. If the
3836 instruction does not use post-increment or pre-decrement addressing,
3837 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3838 start at element 0. */
3841 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3842 HOST_WIDE_INT automod_offset
, bool store_p
)
3844 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3845 HOST_WIDE_INT offset
, mem_offset
;
3847 enum reg_class rclass
;
3849 len
= XVECLEN (pattern
, 0);
3850 first
= (automod_base
!= NULL
);
3854 /* Stores must be pre-decrement and loads must be post-increment. */
3855 if (store_p
!= (automod_offset
< 0))
3858 /* Work out the base and offset for lowest memory location. */
3859 base
= automod_base
;
3860 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3864 /* Allow any valid base and offset in the first access. */
3871 for (i
= first
; i
< len
; i
++)
3873 /* We need a plain SET. */
3874 set
= XVECEXP (pattern
, 0, i
);
3875 if (GET_CODE (set
) != SET
)
3878 /* Check that we have a memory location... */
3879 mem
= XEXP (set
, !store_p
);
3880 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3883 /* ...with the right address. */
3886 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3887 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3888 There are no mode restrictions for 680x0 besides the
3889 automodification rules enforced above. */
3891 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3896 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3897 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3901 /* Check that we have a register of the required mode and class. */
3902 reg
= XEXP (set
, store_p
);
3904 || !HARD_REGISTER_P (reg
)
3905 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3910 /* The register must belong to RCLASS and have a higher number
3911 than the register in the previous SET. */
3912 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3913 || REGNO (last_reg
) >= REGNO (reg
))
3918 /* Work out which register class we need. */
3919 if (INT_REGNO_P (REGNO (reg
)))
3920 rclass
= GENERAL_REGS
;
3921 else if (FP_REGNO_P (REGNO (reg
)))
3928 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3931 /* If we have an automodification, check whether the final offset is OK. */
3932 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3935 /* Reject unprofitable cases. */
3936 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3942 /* Return the assembly code template for a movem or fmovem instruction
3943 whose pattern is given by PATTERN. Store the template's operands
3946 If the instruction uses post-increment or pre-decrement addressing,
3947 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3948 is true if this is a store instruction. */
3951 m68k_output_movem (rtx
*operands
, rtx pattern
,
3952 HOST_WIDE_INT automod_offset
, bool store_p
)
3957 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3959 first
= (automod_offset
!= 0);
3960 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3962 /* When using movem with pre-decrement addressing, register X + D0_REG
3963 is controlled by bit 15 - X. For all other addressing modes,
3964 register X + D0_REG is controlled by bit X. Confusingly, the
3965 register mask for fmovem is in the opposite order to that for
3969 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3970 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3971 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3972 if (automod_offset
< 0)
3974 if (FP_REGNO_P (regno
))
3975 mask
|= 1 << (regno
- FP0_REG
);
3977 mask
|= 1 << (15 - (regno
- D0_REG
));
3981 if (FP_REGNO_P (regno
))
3982 mask
|= 1 << (7 - (regno
- FP0_REG
));
3984 mask
|= 1 << (regno
- D0_REG
);
3989 if (automod_offset
== 0)
3990 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3991 else if (automod_offset
< 0)
3992 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3994 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3995 operands
[1] = GEN_INT (mask
);
3996 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3999 return "fmovem %1,%a0";
4001 return "fmovem %a0,%1";
4006 return "movem%.l %1,%a0";
4008 return "movem%.l %a0,%1";
4012 /* Return a REG that occurs in ADDR with coefficient 1.
4013 ADDR can be effectively incremented by incrementing REG. */
4016 find_addr_reg (rtx addr
)
4018 while (GET_CODE (addr
) == PLUS
)
4020 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4021 addr
= XEXP (addr
, 0);
4022 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4023 addr
= XEXP (addr
, 1);
4024 else if (CONSTANT_P (XEXP (addr
, 0)))
4025 addr
= XEXP (addr
, 1);
4026 else if (CONSTANT_P (XEXP (addr
, 1)))
4027 addr
= XEXP (addr
, 0);
4031 gcc_assert (GET_CODE (addr
) == REG
);
4035 /* Output assembler code to perform a 32-bit 3-operand add. */
4038 output_addsi3 (rtx
*operands
)
4040 if (! operands_match_p (operands
[0], operands
[1]))
4042 if (!ADDRESS_REG_P (operands
[1]))
4044 rtx tmp
= operands
[1];
4046 operands
[1] = operands
[2];
4050 /* These insns can result from reloads to access
4051 stack slots over 64k from the frame pointer. */
4052 if (GET_CODE (operands
[2]) == CONST_INT
4053 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4054 return "move%.l %2,%0\n\tadd%.l %1,%0";
4055 if (GET_CODE (operands
[2]) == REG
)
4056 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4057 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4059 if (GET_CODE (operands
[2]) == CONST_INT
)
4061 if (INTVAL (operands
[2]) > 0
4062 && INTVAL (operands
[2]) <= 8)
4063 return "addq%.l %2,%0";
4064 if (INTVAL (operands
[2]) < 0
4065 && INTVAL (operands
[2]) >= -8)
4067 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4068 return "subq%.l %2,%0";
4070 /* On the CPU32 it is faster to use two addql instructions to
4071 add a small integer (8 < N <= 16) to a register.
4072 Likewise for subql. */
4073 if (TUNE_CPU32
&& REG_P (operands
[0]))
4075 if (INTVAL (operands
[2]) > 8
4076 && INTVAL (operands
[2]) <= 16)
4078 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4079 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4081 if (INTVAL (operands
[2]) < -8
4082 && INTVAL (operands
[2]) >= -16)
4084 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4085 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4088 if (ADDRESS_REG_P (operands
[0])
4089 && INTVAL (operands
[2]) >= -0x8000
4090 && INTVAL (operands
[2]) < 0x8000)
4093 return "add%.w %2,%0";
4095 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4098 return "add%.l %2,%0";
4101 /* Store in cc_status the expressions that the condition codes will
4102 describe after execution of an instruction whose pattern is EXP.
4103 Do not alter them if the instruction would not alter the cc's. */
4105 /* On the 68000, all the insns to store in an address register fail to
4106 set the cc's. However, in some cases these instructions can make it
4107 possibly invalid to use the saved cc's. In those cases we clear out
4108 some or all of the saved cc's so they won't be used. */
4111 notice_update_cc (rtx exp
, rtx insn
)
4113 if (GET_CODE (exp
) == SET
)
4115 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4117 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4119 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4120 cc_status
.value1
= 0;
4121 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4122 cc_status
.value2
= 0;
4124 /* fmoves to memory or data registers do not set the condition
4125 codes. Normal moves _do_ set the condition codes, but not in
4126 a way that is appropriate for comparison with 0, because -0.0
4127 would be treated as a negative nonzero number. Note that it
4128 isn't appropriate to conditionalize this restriction on
4129 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4130 we care about the difference between -0.0 and +0.0. */
4131 else if (!FP_REG_P (SET_DEST (exp
))
4132 && SET_DEST (exp
) != cc0_rtx
4133 && (FP_REG_P (SET_SRC (exp
))
4134 || GET_CODE (SET_SRC (exp
)) == FIX
4135 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4137 /* A pair of move insns doesn't produce a useful overall cc. */
4138 else if (!FP_REG_P (SET_DEST (exp
))
4139 && !FP_REG_P (SET_SRC (exp
))
4140 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4141 && (GET_CODE (SET_SRC (exp
)) == REG
4142 || GET_CODE (SET_SRC (exp
)) == MEM
4143 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4145 else if (SET_DEST (exp
) != pc_rtx
)
4147 cc_status
.flags
= 0;
4148 cc_status
.value1
= SET_DEST (exp
);
4149 cc_status
.value2
= SET_SRC (exp
);
4152 else if (GET_CODE (exp
) == PARALLEL
4153 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4155 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4156 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4158 if (ADDRESS_REG_P (dest
))
4160 else if (dest
!= pc_rtx
)
4162 cc_status
.flags
= 0;
4163 cc_status
.value1
= dest
;
4164 cc_status
.value2
= src
;
4169 if (cc_status
.value2
!= 0
4170 && ADDRESS_REG_P (cc_status
.value2
)
4171 && GET_MODE (cc_status
.value2
) == QImode
)
4173 if (cc_status
.value2
!= 0)
4174 switch (GET_CODE (cc_status
.value2
))
4176 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4177 case ROTATE
: case ROTATERT
:
4178 /* These instructions always clear the overflow bit, and set
4179 the carry to the bit shifted out. */
4180 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4183 case PLUS
: case MINUS
: case MULT
:
4184 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4185 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4186 cc_status
.flags
|= CC_NO_OVERFLOW
;
4189 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4190 ends with a move insn moving r2 in r2's mode.
4191 Thus, the cc's are set for r2.
4192 This can set N bit spuriously. */
4193 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4198 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4200 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4201 cc_status
.value2
= 0;
4202 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4203 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4204 cc_status
.flags
= CC_IN_68881
;
4205 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4206 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4208 cc_status
.flags
= CC_IN_68881
;
4209 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4210 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4211 cc_status
.flags
|= CC_REVERSED
;
4216 output_move_const_double (rtx
*operands
)
4218 int code
= standard_68881_constant_p (operands
[1]);
4222 static char buf
[40];
4224 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4227 return "fmove%.d %1,%0";
4231 output_move_const_single (rtx
*operands
)
4233 int code
= standard_68881_constant_p (operands
[1]);
4237 static char buf
[40];
4239 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4242 return "fmove%.s %f1,%0";
4245 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4246 from the "fmovecr" instruction.
4247 The value, anded with 0xff, gives the code to use in fmovecr
4248 to get the desired constant. */
4250 /* This code has been fixed for cross-compilation. */
4252 static int inited_68881_table
= 0;
4254 static const char *const strings_68881
[7] = {
4264 static const int codes_68881
[7] = {
4274 REAL_VALUE_TYPE values_68881
[7];
4276 /* Set up values_68881 array by converting the decimal values
4277 strings_68881 to binary. */
4280 init_68881_table (void)
4284 enum machine_mode mode
;
4287 for (i
= 0; i
< 7; i
++)
4291 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4292 values_68881
[i
] = r
;
4294 inited_68881_table
= 1;
4298 standard_68881_constant_p (rtx x
)
4303 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4304 used at all on those chips. */
4308 if (! inited_68881_table
)
4309 init_68881_table ();
4311 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4313 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4315 for (i
= 0; i
< 6; i
++)
4317 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4318 return (codes_68881
[i
]);
4321 if (GET_MODE (x
) == SFmode
)
4324 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4325 return (codes_68881
[6]);
4327 /* larger powers of ten in the constants ram are not used
4328 because they are not equal to a `double' C constant. */
4332 /* If X is a floating-point constant, return the logarithm of X base 2,
4333 or 0 if X is not a power of 2. */
4336 floating_exact_log2 (rtx x
)
4338 REAL_VALUE_TYPE r
, r1
;
4341 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4343 if (REAL_VALUES_LESS (r
, dconst1
))
4346 exp
= real_exponent (&r
);
4347 real_2expN (&r1
, exp
, DFmode
);
4348 if (REAL_VALUES_EQUAL (r1
, r
))
4354 /* A C compound statement to output to stdio stream STREAM the
4355 assembler syntax for an instruction operand X. X is an RTL
4358 CODE is a value that can be used to specify one of several ways
4359 of printing the operand. It is used when identical operands
4360 must be printed differently depending on the context. CODE
4361 comes from the `%' specification that was used to request
4362 printing of the operand. If the specification was just `%DIGIT'
4363 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4364 is the ASCII code for LTR.
4366 If X is a register, this macro should print the register's name.
4367 The names can be found in an array `reg_names' whose type is
4368 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4370 When the machine description has a specification `%PUNCT' (a `%'
4371 followed by a punctuation character), this macro is called with
4372 a null pointer for X and the punctuation character for CODE.
4374 The m68k specific codes are:
4376 '.' for dot needed in Motorola-style opcode names.
4377 '-' for an operand pushing on the stack:
4378 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4379 '+' for an operand pushing on the stack:
4380 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4381 '@' for a reference to the top word on the stack:
4382 sp@, (sp) or (%sp) depending on the style of syntax.
4383 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4384 but & in SGS syntax).
4385 '!' for the cc register (used in an `and to cc' insn).
4386 '$' for the letter `s' in an op code, but only on the 68040.
4387 '&' for the letter `d' in an op code, but only on the 68040.
4388 '/' for register prefix needed by longlong.h.
4389 '?' for m68k_library_id_string
4391 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4392 'd' to force memory addressing to be absolute, not relative.
4393 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4394 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4395 or print pair of registers as rx:ry.
4396 'p' print an address with @PLTPC attached, but only if the operand
4397 is not locally-bound. */
4400 print_operand (FILE *file
, rtx op
, int letter
)
4405 fprintf (file
, ".");
4407 else if (letter
== '#')
4408 asm_fprintf (file
, "%I");
4409 else if (letter
== '-')
4410 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4411 else if (letter
== '+')
4412 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4413 else if (letter
== '@')
4414 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4415 else if (letter
== '!')
4416 asm_fprintf (file
, "%Rfpcr");
4417 else if (letter
== '$')
4420 fprintf (file
, "s");
4422 else if (letter
== '&')
4425 fprintf (file
, "d");
4427 else if (letter
== '/')
4428 asm_fprintf (file
, "%R");
4429 else if (letter
== '?')
4430 asm_fprintf (file
, m68k_library_id_string
);
4431 else if (letter
== 'p')
4433 output_addr_const (file
, op
);
4434 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4435 fprintf (file
, "@PLTPC");
4437 else if (GET_CODE (op
) == REG
)
4440 /* Print out the second register name of a register pair.
4441 I.e., R (6) => 7. */
4442 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4444 fputs (M68K_REGNAME(REGNO (op
)), file
);
4446 else if (GET_CODE (op
) == MEM
)
4448 output_address (XEXP (op
, 0));
4449 if (letter
== 'd' && ! TARGET_68020
4450 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4451 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4452 && INTVAL (XEXP (op
, 0)) < 0x8000
4453 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4454 fprintf (file
, MOTOROLA
? ".l" : ":l");
4456 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4460 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4461 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4462 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4464 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4468 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4469 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4470 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4471 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4473 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4477 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4478 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4479 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4483 /* Use `print_operand_address' instead of `output_addr_const'
4484 to ensure that we print relevant PIC stuff. */
4485 asm_fprintf (file
, "%I");
4487 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4488 print_operand_address (file
, op
);
4490 output_addr_const (file
, op
);
4494 /* Return string for TLS relocation RELOC. */
4497 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4499 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4500 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4507 if (flag_pic
== 1 && TARGET_68020
)
4548 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4551 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4553 if (GET_CODE (x
) == UNSPEC
)
4555 switch (XINT (x
, 1))
4557 case UNSPEC_RELOC16
:
4558 case UNSPEC_RELOC32
:
4559 output_addr_const (file
, XVECEXP (x
, 0, 0));
4560 fputs (m68k_get_reloc_decoration
4561 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4572 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4575 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4577 gcc_assert (size
== 4);
4578 fputs ("\t.long\t", file
);
4579 output_addr_const (file
, x
);
4580 fputs ("@TLSLDO+0x8000", file
);
4583 /* In the name of slightly smaller debug output, and to cater to
4584 general assembler lossage, recognize various UNSPEC sequences
4585 and turn them back into a direct symbol reference. */
4588 m68k_delegitimize_address (rtx orig_x
)
4591 struct m68k_address addr
;
4594 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4599 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4602 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4603 || addr
.offset
== NULL_RTX
4604 || GET_CODE (addr
.offset
) != CONST
)
4607 unspec
= XEXP (addr
.offset
, 0);
4608 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4609 unspec
= XEXP (unspec
, 0);
4610 if (GET_CODE (unspec
) != UNSPEC
4611 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4612 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4614 x
= XVECEXP (unspec
, 0, 0);
4615 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4616 if (unspec
!= XEXP (addr
.offset
, 0))
4617 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4620 rtx idx
= addr
.index
;
4621 if (addr
.scale
!= 1)
4622 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4623 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4626 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4628 x
= replace_equiv_address_nv (orig_x
, x
);
4633 /* A C compound statement to output to stdio stream STREAM the
4634 assembler syntax for an instruction operand that is a memory
4635 reference whose address is ADDR. ADDR is an RTL expression.
4637 Note that this contains a kludge that knows that the only reason
4638 we have an address (plus (label_ref...) (reg...)) when not generating
4639 PIC code is in the insn before a tablejump, and we know that m68k.md
4640 generates a label LInnn: on such an insn.
4642 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4643 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4645 This routine is responsible for distinguishing between -fpic and -fPIC
4646 style relocations in an address. When generating -fpic code the
4647 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4648 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4651 print_operand_address (FILE *file
, rtx addr
)
4653 struct m68k_address address
;
4655 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4658 if (address
.code
== PRE_DEC
)
4659 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4660 M68K_REGNAME (REGNO (address
.base
)));
4661 else if (address
.code
== POST_INC
)
4662 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4663 M68K_REGNAME (REGNO (address
.base
)));
4664 else if (!address
.base
&& !address
.index
)
4666 /* A constant address. */
4667 gcc_assert (address
.offset
== addr
);
4668 if (GET_CODE (addr
) == CONST_INT
)
4670 /* (xxx).w or (xxx).l. */
4671 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4672 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4674 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4676 else if (TARGET_PCREL
)
4678 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4680 output_addr_const (file
, addr
);
4681 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4685 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4686 name ends in `.<letter>', as the last 2 characters can be
4687 mistaken as a size suffix. Put the name in parentheses. */
4688 if (GET_CODE (addr
) == SYMBOL_REF
4689 && strlen (XSTR (addr
, 0)) > 2
4690 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4693 output_addr_const (file
, addr
);
4697 output_addr_const (file
, addr
);
4704 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4705 label being accessed, otherwise it is -1. */
4706 labelno
= (address
.offset
4708 && GET_CODE (address
.offset
) == LABEL_REF
4709 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4713 /* Print the "offset(base" component. */
4715 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4719 output_addr_const (file
, address
.offset
);
4723 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4725 /* Print the ",index" component, if any. */
4730 fprintf (file
, "%s.%c",
4731 M68K_REGNAME (REGNO (address
.index
)),
4732 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4733 if (address
.scale
!= 1)
4734 fprintf (file
, "*%d", address
.scale
);
4738 else /* !MOTOROLA */
4740 if (!address
.offset
&& !address
.index
)
4741 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4744 /* Print the "base@(offset" component. */
4746 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4750 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4751 fprintf (file
, "@(");
4753 output_addr_const (file
, address
.offset
);
4755 /* Print the ",index" component, if any. */
4758 fprintf (file
, ",%s:%c",
4759 M68K_REGNAME (REGNO (address
.index
)),
4760 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4761 if (address
.scale
!= 1)
4762 fprintf (file
, ":%d", address
.scale
);
4770 /* Check for cases where a clr insns can be omitted from code using
4771 strict_low_part sets. For example, the second clrl here is not needed:
4772 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4774 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4775 insn we are checking for redundancy. TARGET is the register set by the
4779 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4784 while ((p
= PREV_INSN (p
)))
4786 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4792 /* If it isn't an insn, then give up. */
4796 if (reg_set_p (target
, p
))
4798 rtx set
= single_set (p
);
4801 /* If it isn't an easy to recognize insn, then give up. */
4805 dest
= SET_DEST (set
);
4807 /* If this sets the entire target register to zero, then our
4808 first_insn is redundant. */
4809 if (rtx_equal_p (dest
, target
)
4810 && SET_SRC (set
) == const0_rtx
)
4812 else if (GET_CODE (dest
) == STRICT_LOW_PART
4813 && GET_CODE (XEXP (dest
, 0)) == REG
4814 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4815 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4816 <= GET_MODE_SIZE (mode
)))
4817 /* This is a strict low part set which modifies less than
4818 we are using, so it is safe. */
4828 /* Operand predicates for implementing asymmetric pc-relative addressing
4829 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4830 when used as a source operand, but not as a destination operand.
4832 We model this by restricting the meaning of the basic predicates
4833 (general_operand, memory_operand, etc) to forbid the use of this
4834 addressing mode, and then define the following predicates that permit
4835 this addressing mode. These predicates can then be used for the
4836 source operands of the appropriate instructions.
4838 n.b. While it is theoretically possible to change all machine patterns
4839 to use this addressing more where permitted by the architecture,
4840 it has only been implemented for "common" cases: SImode, HImode, and
4841 QImode operands, and only for the principle operations that would
4842 require this addressing mode: data movement and simple integer operations.
4844 In parallel with these new predicates, two new constraint letters
4845 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4846 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4847 In the pcrel case 's' is only valid in combination with 'a' registers.
4848 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4849 of how these constraints are used.
4851 The use of these predicates is strictly optional, though patterns that
4852 don't will cause an extra reload register to be allocated where one
4855 lea (abc:w,%pc),%a0 ; need to reload address
4856 moveq &1,%d1 ; since write to pc-relative space
4857 movel %d1,%a0@ ; is not allowed
4859 lea (abc:w,%pc),%a1 ; no need to reload address here
4860 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4862 For more info, consult tiemann@cygnus.com.
4865 All of the ugliness with predicates and constraints is due to the
4866 simple fact that the m68k does not allow a pc-relative addressing
4867 mode as a destination. gcc does not distinguish between source and
4868 destination addresses. Hence, if we claim that pc-relative address
4869 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4870 end up with invalid code. To get around this problem, we left
4871 pc-relative modes as invalid addresses, and then added special
4872 predicates and constraints to accept them.
4874 A cleaner way to handle this is to modify gcc to distinguish
4875 between source and destination addresses. We can then say that
4876 pc-relative is a valid source address but not a valid destination
4877 address, and hopefully avoid a lot of the predicate and constraint
4878 hackery. Unfortunately, this would be a pretty big change. It would
4879 be a useful change for a number of ports, but there aren't any current
4880 plans to undertake this.
4882 ***************************************************************************/
4886 output_andsi3 (rtx
*operands
)
4889 if (GET_CODE (operands
[2]) == CONST_INT
4890 && (INTVAL (operands
[2]) | 0xffff) == -1
4891 && (DATA_REG_P (operands
[0])
4892 || offsettable_memref_p (operands
[0]))
4893 && !TARGET_COLDFIRE
)
4895 if (GET_CODE (operands
[0]) != REG
)
4896 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4897 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4898 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4900 if (operands
[2] == const0_rtx
)
4902 return "and%.w %2,%0";
4904 if (GET_CODE (operands
[2]) == CONST_INT
4905 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4906 && (DATA_REG_P (operands
[0])
4907 || offsettable_memref_p (operands
[0])))
4909 if (DATA_REG_P (operands
[0]))
4910 operands
[1] = GEN_INT (logval
);
4913 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4914 operands
[1] = GEN_INT (logval
% 8);
4916 /* This does not set condition codes in a standard way. */
4918 return "bclr %1,%0";
4920 return "and%.l %2,%0";
4924 output_iorsi3 (rtx
*operands
)
4926 register int logval
;
4927 if (GET_CODE (operands
[2]) == CONST_INT
4928 && INTVAL (operands
[2]) >> 16 == 0
4929 && (DATA_REG_P (operands
[0])
4930 || offsettable_memref_p (operands
[0]))
4931 && !TARGET_COLDFIRE
)
4933 if (GET_CODE (operands
[0]) != REG
)
4934 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4935 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4937 if (INTVAL (operands
[2]) == 0xffff)
4938 return "mov%.w %2,%0";
4939 return "or%.w %2,%0";
4941 if (GET_CODE (operands
[2]) == CONST_INT
4942 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4943 && (DATA_REG_P (operands
[0])
4944 || offsettable_memref_p (operands
[0])))
4946 if (DATA_REG_P (operands
[0]))
4947 operands
[1] = GEN_INT (logval
);
4950 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4951 operands
[1] = GEN_INT (logval
% 8);
4954 return "bset %1,%0";
4956 return "or%.l %2,%0";
4960 output_xorsi3 (rtx
*operands
)
4962 register int logval
;
4963 if (GET_CODE (operands
[2]) == CONST_INT
4964 && INTVAL (operands
[2]) >> 16 == 0
4965 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4966 && !TARGET_COLDFIRE
)
4968 if (! DATA_REG_P (operands
[0]))
4969 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4970 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4972 if (INTVAL (operands
[2]) == 0xffff)
4974 return "eor%.w %2,%0";
4976 if (GET_CODE (operands
[2]) == CONST_INT
4977 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4978 && (DATA_REG_P (operands
[0])
4979 || offsettable_memref_p (operands
[0])))
4981 if (DATA_REG_P (operands
[0]))
4982 operands
[1] = GEN_INT (logval
);
4985 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4986 operands
[1] = GEN_INT (logval
% 8);
4989 return "bchg %1,%0";
4991 return "eor%.l %2,%0";
4994 /* Return the instruction that should be used for a call to address X,
4995 which is known to be in operand 0. */
5000 if (symbolic_operand (x
, VOIDmode
))
5001 return m68k_symbolic_call
;
5006 /* Likewise sibling calls. */
5009 output_sibcall (rtx x
)
5011 if (symbolic_operand (x
, VOIDmode
))
5012 return m68k_symbolic_jump
;
5018 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5019 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5022 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5024 /* Avoid clobbering the struct value reg by using the
5025 static chain reg as a temporary. */
5026 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5028 /* Pretend to be a post-reload pass while generating rtl. */
5029 reload_completed
= 1;
5031 /* The "this" pointer is stored at 4(%sp). */
5032 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
5034 /* Add DELTA to THIS. */
5037 /* Make the offset a legitimate operand for memory addition. */
5038 offset
= GEN_INT (delta
);
5039 if ((delta
< -8 || delta
> 8)
5040 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5042 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5043 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5045 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5046 copy_rtx (this_slot
), offset
));
5049 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5050 if (vcall_offset
!= 0)
5052 /* Set the static chain register to *THIS. */
5053 emit_move_insn (tmp
, this_slot
);
5054 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5056 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5057 addr
= plus_constant (tmp
, vcall_offset
);
5058 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5060 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5064 /* Load the offset into %d0 and add it to THIS. */
5065 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5066 gen_rtx_MEM (Pmode
, addr
));
5067 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5068 copy_rtx (this_slot
),
5069 gen_rtx_REG (Pmode
, D0_REG
)));
5072 /* Jump to the target function. Use a sibcall if direct jumps are
5073 allowed, otherwise load the address into a register first. */
5074 mem
= DECL_RTL (function
);
5075 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5077 gcc_assert (flag_pic
);
5079 if (!TARGET_SEP_DATA
)
5081 /* Use the static chain register as a temporary (call-clobbered)
5082 GOT pointer for this function. We can use the static chain
5083 register because it isn't live on entry to the thunk. */
5084 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5085 emit_insn (gen_load_got (pic_offset_table_rtx
));
5087 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5088 mem
= replace_equiv_address (mem
, tmp
);
5090 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5091 SIBLING_CALL_P (insn
) = 1;
5093 /* Run just enough of rest_of_compilation. */
5094 insn
= get_insns ();
5095 split_all_insns_noflow ();
5096 final_start_function (insn
, file
, 1);
5097 final (insn
, file
, 1);
5098 final_end_function ();
5100 /* Clean up the vars set above. */
5101 reload_completed
= 0;
5103 /* Restore the original PIC register. */
5105 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5108 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5111 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5112 int incoming ATTRIBUTE_UNUSED
)
5114 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5117 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5119 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5120 unsigned int new_reg
)
5123 /* Interrupt functions can only use registers that have already been
5124 saved by the prologue, even if they would normally be
5127 if ((m68k_get_function_kind (current_function_decl
)
5128 == m68k_fk_interrupt_handler
)
5129 && !df_regs_ever_live_p (new_reg
))
5135 /* Value is true if hard register REGNO can hold a value of machine-mode
5136 MODE. On the 68000, we let the cpu registers can hold any mode, but
5137 restrict the 68881 registers to floating-point modes. */
5140 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5142 if (DATA_REGNO_P (regno
))
5144 /* Data Registers, can hold aggregate if fits in. */
5145 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5148 else if (ADDRESS_REGNO_P (regno
))
5150 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5153 else if (FP_REGNO_P (regno
))
5155 /* FPU registers, hold float or complex float of long double or
5157 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5158 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5159 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5165 /* Implement SECONDARY_RELOAD_CLASS. */
5168 m68k_secondary_reload_class (enum reg_class rclass
,
5169 enum machine_mode mode
, rtx x
)
5173 regno
= true_regnum (x
);
5175 /* If one operand of a movqi is an address register, the other
5176 operand must be a general register or constant. Other types
5177 of operand must be reloaded through a data register. */
5178 if (GET_MODE_SIZE (mode
) == 1
5179 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5180 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5183 /* PC-relative addresses must be loaded into an address register first. */
5185 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5186 && symbolic_operand (x
, VOIDmode
))
5192 /* Implement PREFERRED_RELOAD_CLASS. */
5195 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5197 enum reg_class secondary_class
;
5199 /* If RCLASS might need a secondary reload, try restricting it to
5200 a class that doesn't. */
5201 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5202 if (secondary_class
!= NO_REGS
5203 && reg_class_subset_p (secondary_class
, rclass
))
5204 return secondary_class
;
5206 /* Prefer to use moveq for in-range constants. */
5207 if (GET_CODE (x
) == CONST_INT
5208 && reg_class_subset_p (DATA_REGS
, rclass
)
5209 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5212 /* ??? Do we really need this now? */
5213 if (GET_CODE (x
) == CONST_DOUBLE
5214 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5216 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5225 /* Return floating point values in a 68881 register. This makes 68881 code
5226 a little bit faster. It also makes -msoft-float code incompatible with
5227 hard-float code, so people have to be careful not to mix the two.
5228 For ColdFire it was decided the ABI incompatibility is undesirable.
5229 If there is need for a hard-float ABI it is probably worth doing it
5230 properly and also passing function arguments in FP registers. */
5232 m68k_libcall_value (enum machine_mode mode
)
5239 return gen_rtx_REG (mode
, FP0_REG
);
5245 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5248 /* Location in which function value is returned.
5249 NOTE: Due to differences in ABIs, don't call this function directly,
5250 use FUNCTION_VALUE instead. */
5252 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5254 enum machine_mode mode
;
5256 mode
= TYPE_MODE (valtype
);
5262 return gen_rtx_REG (mode
, FP0_REG
);
5268 /* If the function returns a pointer, push that into %a0. */
5269 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5270 /* For compatibility with the large body of existing code which
5271 does not always properly declare external functions returning
5272 pointer types, the m68k/SVR4 convention is to copy the value
5273 returned for pointer functions from a0 to d0 in the function
5274 epilogue, so that callers that have neglected to properly
5275 declare the callee can still find the correct return value in
5277 return gen_rtx_PARALLEL
5280 gen_rtx_EXPR_LIST (VOIDmode
,
5281 gen_rtx_REG (mode
, A0_REG
),
5283 gen_rtx_EXPR_LIST (VOIDmode
,
5284 gen_rtx_REG (mode
, D0_REG
),
5286 else if (POINTER_TYPE_P (valtype
))
5287 return gen_rtx_REG (mode
, A0_REG
);
5289 return gen_rtx_REG (mode
, D0_REG
);
5292 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5293 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5295 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5297 enum machine_mode mode
= TYPE_MODE (type
);
5299 if (mode
== BLKmode
)
5302 /* If TYPE's known alignment is less than the alignment of MODE that
5303 would contain the structure, then return in memory. We need to
5304 do so to maintain the compatibility between code compiled with
5305 -mstrict-align and that compiled with -mno-strict-align. */
5306 if (AGGREGATE_TYPE_P (type
)
5307 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5314 /* CPU to schedule the program for. */
5315 enum attr_cpu m68k_sched_cpu
;
5317 /* MAC to schedule the program for. */
5318 enum attr_mac m68k_sched_mac
;
5326 /* Integer register. */
5332 /* Implicit mem reference (e.g. stack). */
5335 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5338 /* Memory with offset but without indexing. EA mode 5. */
5341 /* Memory with indexing. EA mode 6. */
5344 /* Memory referenced by absolute address. EA mode 7. */
5347 /* Immediate operand that doesn't require extension word. */
5350 /* Immediate 16 bit operand. */
5353 /* Immediate 32 bit operand. */
5357 /* Return type of memory ADDR_RTX refers to. */
5358 static enum attr_op_type
5359 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5361 struct m68k_address address
;
5363 if (symbolic_operand (addr_rtx
, VOIDmode
))
5364 return OP_TYPE_MEM7
;
5366 if (!m68k_decompose_address (mode
, addr_rtx
,
5367 reload_completed
, &address
))
5369 gcc_assert (!reload_completed
);
5370 /* Reload will likely fix the address to be in the register. */
5371 return OP_TYPE_MEM234
;
5374 if (address
.scale
!= 0)
5375 return OP_TYPE_MEM6
;
5377 if (address
.base
!= NULL_RTX
)
5379 if (address
.offset
== NULL_RTX
)
5380 return OP_TYPE_MEM234
;
5382 return OP_TYPE_MEM5
;
5385 gcc_assert (address
.offset
!= NULL_RTX
);
5387 return OP_TYPE_MEM7
;
5390 /* Return X or Y (depending on OPX_P) operand of INSN. */
5392 sched_get_operand (rtx insn
, bool opx_p
)
5396 if (recog_memoized (insn
) < 0)
5399 extract_constrain_insn_cached (insn
);
5402 i
= get_attr_opx (insn
);
5404 i
= get_attr_opy (insn
);
5406 if (i
>= recog_data
.n_operands
)
5409 return recog_data
.operand
[i
];
5412 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5413 If ADDRESS_P is true, return type of memory location operand refers to. */
5414 static enum attr_op_type
5415 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5419 op
= sched_get_operand (insn
, opx_p
);
5423 gcc_assert (!reload_completed
);
5428 return sched_address_type (QImode
, op
);
5430 if (memory_operand (op
, VOIDmode
))
5431 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5433 if (register_operand (op
, VOIDmode
))
5435 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5436 || (reload_completed
&& FP_REG_P (op
)))
5442 if (GET_CODE (op
) == CONST_INT
)
5448 /* Check for quick constants. */
5449 switch (get_attr_type (insn
))
5452 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5453 return OP_TYPE_IMM_Q
;
5455 gcc_assert (!reload_completed
);
5459 if (USE_MOVQ (ival
))
5460 return OP_TYPE_IMM_Q
;
5462 gcc_assert (!reload_completed
);
5466 if (valid_mov3q_const (ival
))
5467 return OP_TYPE_IMM_Q
;
5469 gcc_assert (!reload_completed
);
5476 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5477 return OP_TYPE_IMM_W
;
5479 return OP_TYPE_IMM_L
;
5482 if (GET_CODE (op
) == CONST_DOUBLE
)
5484 switch (GET_MODE (op
))
5487 return OP_TYPE_IMM_W
;
5491 return OP_TYPE_IMM_L
;
5498 if (GET_CODE (op
) == CONST
5499 || symbolic_operand (op
, VOIDmode
)
5502 switch (GET_MODE (op
))
5505 return OP_TYPE_IMM_Q
;
5508 return OP_TYPE_IMM_W
;
5511 return OP_TYPE_IMM_L
;
5514 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5516 return OP_TYPE_IMM_W
;
5518 return OP_TYPE_IMM_L
;
5522 gcc_assert (!reload_completed
);
5524 if (FLOAT_MODE_P (GET_MODE (op
)))
5530 /* Implement opx_type attribute.
5531 Return type of INSN's operand X.
5532 If ADDRESS_P is true, return type of memory location operand refers to. */
5534 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5536 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5542 return OPX_TYPE_FPN
;
5545 return OPX_TYPE_MEM1
;
5547 case OP_TYPE_MEM234
:
5548 return OPX_TYPE_MEM234
;
5551 return OPX_TYPE_MEM5
;
5554 return OPX_TYPE_MEM6
;
5557 return OPX_TYPE_MEM7
;
5560 return OPX_TYPE_IMM_Q
;
5563 return OPX_TYPE_IMM_W
;
5566 return OPX_TYPE_IMM_L
;
5573 /* Implement opy_type attribute.
5574 Return type of INSN's operand Y.
5575 If ADDRESS_P is true, return type of memory location operand refers to. */
5577 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5579 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5585 return OPY_TYPE_FPN
;
5588 return OPY_TYPE_MEM1
;
5590 case OP_TYPE_MEM234
:
5591 return OPY_TYPE_MEM234
;
5594 return OPY_TYPE_MEM5
;
5597 return OPY_TYPE_MEM6
;
5600 return OPY_TYPE_MEM7
;
5603 return OPY_TYPE_IMM_Q
;
5606 return OPY_TYPE_IMM_W
;
5609 return OPY_TYPE_IMM_L
;
5616 /* Return size of INSN as int. */
5618 sched_get_attr_size_int (rtx insn
)
5622 switch (get_attr_type (insn
))
5625 /* There should be no references to m68k_sched_attr_size for 'ignore'
5639 switch (get_attr_opx_type (insn
))
5645 case OPX_TYPE_MEM234
:
5646 case OPY_TYPE_IMM_Q
:
5651 /* Here we assume that most absolute references are short. */
5653 case OPY_TYPE_IMM_W
:
5657 case OPY_TYPE_IMM_L
:
5665 switch (get_attr_opy_type (insn
))
5671 case OPY_TYPE_MEM234
:
5672 case OPY_TYPE_IMM_Q
:
5677 /* Here we assume that most absolute references are short. */
5679 case OPY_TYPE_IMM_W
:
5683 case OPY_TYPE_IMM_L
:
5693 gcc_assert (!reload_completed
);
5701 /* Return size of INSN as attribute enum value. */
5703 m68k_sched_attr_size (rtx insn
)
5705 switch (sched_get_attr_size_int (insn
))
5721 /* Return operand X or Y (depending on OPX_P) of INSN,
5722 if it is a MEM, or NULL overwise. */
5723 static enum attr_op_type
5724 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5728 switch (get_attr_opx_type (insn
))
5733 case OPX_TYPE_IMM_Q
:
5734 case OPX_TYPE_IMM_W
:
5735 case OPX_TYPE_IMM_L
:
5739 case OPX_TYPE_MEM234
:
5742 return OP_TYPE_MEM1
;
5745 return OP_TYPE_MEM6
;
5753 switch (get_attr_opy_type (insn
))
5758 case OPY_TYPE_IMM_Q
:
5759 case OPY_TYPE_IMM_W
:
5760 case OPY_TYPE_IMM_L
:
5764 case OPY_TYPE_MEM234
:
5767 return OP_TYPE_MEM1
;
5770 return OP_TYPE_MEM6
;
5778 /* Implement op_mem attribute. */
5780 m68k_sched_attr_op_mem (rtx insn
)
5782 enum attr_op_type opx
;
5783 enum attr_op_type opy
;
5785 opx
= sched_get_opxy_mem_type (insn
, true);
5786 opy
= sched_get_opxy_mem_type (insn
, false);
5788 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5791 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5793 switch (get_attr_opx_access (insn
))
5809 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5811 switch (get_attr_opx_access (insn
))
5827 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5830 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5832 switch (get_attr_opx_access (insn
))
5838 gcc_assert (!reload_completed
);
5843 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5845 switch (get_attr_opx_access (insn
))
5851 gcc_assert (!reload_completed
);
5856 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5859 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5861 switch (get_attr_opx_access (insn
))
5867 gcc_assert (!reload_completed
);
5872 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5873 gcc_assert (!reload_completed
);
5877 /* Jump instructions types. Indexed by INSN_UID.
5878 The same rtl insn can be expanded into different asm instructions
5879 depending on the cc0_status. To properly determine type of jump
5880 instructions we scan instruction stream and map jumps types to this
5882 static enum attr_type
*sched_branch_type
;
5884 /* Return the type of the jump insn. */
5886 m68k_sched_branch_type (rtx insn
)
5888 enum attr_type type
;
5890 type
= sched_branch_type
[INSN_UID (insn
)];
5892 gcc_assert (type
!= 0);
5897 /* Data for ColdFire V4 index bypass.
5898 Producer modifies register that is used as index in consumer with
5902 /* Producer instruction. */
5905 /* Consumer instruction. */
5908 /* Scale of indexed memory access within consumer.
5909 Or zero if bypass should not be effective at the moment. */
5911 } sched_cfv4_bypass_data
;
5913 /* An empty state that is used in m68k_sched_adjust_cost. */
5914 static state_t sched_adjust_cost_state
;
5916 /* Implement adjust_cost scheduler hook.
5917 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5919 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5924 if (recog_memoized (def_insn
) < 0
5925 || recog_memoized (insn
) < 0)
5928 if (sched_cfv4_bypass_data
.scale
== 1)
5929 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5931 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5932 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5933 that the data in sched_cfv4_bypass_data is up to date. */
5934 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5935 && sched_cfv4_bypass_data
.con
== insn
);
5940 sched_cfv4_bypass_data
.pro
= NULL
;
5941 sched_cfv4_bypass_data
.con
= NULL
;
5942 sched_cfv4_bypass_data
.scale
= 0;
5945 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5946 && sched_cfv4_bypass_data
.con
== NULL
5947 && sched_cfv4_bypass_data
.scale
== 0);
5949 /* Don't try to issue INSN earlier than DFA permits.
5950 This is especially useful for instructions that write to memory,
5951 as their true dependence (default) latency is better to be set to 0
5952 to workaround alias analysis limitations.
5953 This is, in fact, a machine independent tweak, so, probably,
5954 it should be moved to haifa-sched.c: insn_cost (). */
5955 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5962 /* Return maximal number of insns that can be scheduled on a single cycle. */
5964 m68k_sched_issue_rate (void)
5966 switch (m68k_sched_cpu
)
5982 /* Maximal length of instruction for current CPU.
5983 E.g. it is 3 for any ColdFire core. */
5984 static int max_insn_size
;
5986 /* Data to model instruction buffer of CPU. */
5989 /* True if instruction buffer model is modeled for current CPU. */
5992 /* Size of the instruction buffer in words. */
5995 /* Number of filled words in the instruction buffer. */
5998 /* Additional information about instruction buffer for CPUs that have
5999 a buffer of instruction records, rather then a plain buffer
6000 of instruction words. */
6001 struct _sched_ib_records
6003 /* Size of buffer in records. */
6006 /* Array to hold data on adjustements made to the size of the buffer. */
6009 /* Index of the above array. */
6013 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6017 static struct _sched_ib sched_ib
;
6019 /* ID of memory unit. */
6020 static int sched_mem_unit_code
;
6022 /* Implementation of the targetm.sched.variable_issue () hook.
6023 It is called after INSN was issued. It returns the number of insns
6024 that can possibly get scheduled on the current cycle.
6025 It is used here to determine the effect of INSN on the instruction
6028 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6029 int sched_verbose ATTRIBUTE_UNUSED
,
6030 rtx insn
, int can_issue_more
)
6034 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6036 switch (m68k_sched_cpu
)
6040 insn_size
= sched_get_attr_size_int (insn
);
6044 insn_size
= sched_get_attr_size_int (insn
);
6046 /* ColdFire V3 and V4 cores have instruction buffers that can
6047 accumulate up to 8 instructions regardless of instructions'
6048 sizes. So we should take care not to "prefetch" 24 one-word
6049 or 12 two-words instructions.
6050 To model this behavior we temporarily decrease size of the
6051 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6055 adjust
= max_insn_size
- insn_size
;
6056 sched_ib
.size
-= adjust
;
6058 if (sched_ib
.filled
> sched_ib
.size
)
6059 sched_ib
.filled
= sched_ib
.size
;
6061 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6064 ++sched_ib
.records
.adjust_index
;
6065 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6066 sched_ib
.records
.adjust_index
= 0;
6068 /* Undo adjustement we did 7 instructions ago. */
6070 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6075 gcc_assert (!sched_ib
.enabled_p
);
6083 if (insn_size
> sched_ib
.filled
)
6084 /* Scheduling for register pressure does not always take DFA into
6085 account. Workaround instruction buffer not being filled enough. */
6087 gcc_assert (sched_pressure_p
);
6088 insn_size
= sched_ib
.filled
;
6093 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6094 || asm_noperands (PATTERN (insn
)) >= 0)
6095 insn_size
= sched_ib
.filled
;
6099 sched_ib
.filled
-= insn_size
;
6101 return can_issue_more
;
6104 /* Return how many instructions should scheduler lookahead to choose the
6107 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6109 return m68k_sched_issue_rate () - 1;
6112 /* Implementation of targetm.sched.init_global () hook.
6113 It is invoked once per scheduling pass and is used here
6114 to initialize scheduler constants. */
6116 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6117 int sched_verbose ATTRIBUTE_UNUSED
,
6118 int n_insns ATTRIBUTE_UNUSED
)
6120 /* Init branch types. */
6124 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
6126 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6129 /* !!! FIXME: Implement real scan here. */
6130 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
6134 #ifdef ENABLE_CHECKING
6135 /* Check that all instructions have DFA reservations and
6136 that all instructions can be issued from a clean state. */
6141 state
= alloca (state_size ());
6143 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6145 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6147 gcc_assert (insn_has_dfa_reservation_p (insn
));
6149 state_reset (state
);
6150 if (state_transition (state
, insn
) >= 0)
6157 /* Setup target cpu. */
6159 /* ColdFire V4 has a set of features to keep its instruction buffer full
6160 (e.g., a separate memory bus for instructions) and, hence, we do not model
6161 buffer for this CPU. */
6162 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6164 switch (m68k_sched_cpu
)
6167 sched_ib
.filled
= 0;
6174 sched_ib
.records
.n_insns
= 0;
6175 sched_ib
.records
.adjust
= NULL
;
6180 sched_ib
.records
.n_insns
= 8;
6181 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6188 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6190 sched_adjust_cost_state
= xmalloc (state_size ());
6191 state_reset (sched_adjust_cost_state
);
6194 emit_insn (gen_ib ());
6195 sched_ib
.insn
= get_insns ();
6199 /* Scheduling pass is now finished. Free/reset static variables. */
6201 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6202 int verbose ATTRIBUTE_UNUSED
)
6204 sched_ib
.insn
= NULL
;
6206 free (sched_adjust_cost_state
);
6207 sched_adjust_cost_state
= NULL
;
6209 sched_mem_unit_code
= 0;
6211 free (sched_ib
.records
.adjust
);
6212 sched_ib
.records
.adjust
= NULL
;
6213 sched_ib
.records
.n_insns
= 0;
6216 free (sched_branch_type
);
6217 sched_branch_type
= NULL
;
6220 /* Implementation of targetm.sched.init () hook.
6221 It is invoked each time scheduler starts on the new block (basic block or
6222 extended basic block). */
6224 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6225 int sched_verbose ATTRIBUTE_UNUSED
,
6226 int n_insns ATTRIBUTE_UNUSED
)
6228 switch (m68k_sched_cpu
)
6236 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6238 memset (sched_ib
.records
.adjust
, 0,
6239 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6240 sched_ib
.records
.adjust_index
= 0;
6244 gcc_assert (!sched_ib
.enabled_p
);
6252 if (sched_ib
.enabled_p
)
6253 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6254 the first cycle. Workaround that. */
6255 sched_ib
.filled
= -2;
6258 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6259 It is invoked just before current cycle finishes and is used here
6260 to track if instruction buffer got its two words this cycle. */
6262 m68k_sched_dfa_pre_advance_cycle (void)
6264 if (!sched_ib
.enabled_p
)
6267 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6269 sched_ib
.filled
+= 2;
6271 if (sched_ib
.filled
> sched_ib
.size
)
6272 sched_ib
.filled
= sched_ib
.size
;
6276 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6277 It is invoked just after new cycle begins and is used here
6278 to setup number of filled words in the instruction buffer so that
6279 instructions which won't have all their words prefetched would be
6280 stalled for a cycle. */
6282 m68k_sched_dfa_post_advance_cycle (void)
6286 if (!sched_ib
.enabled_p
)
6289 /* Setup number of prefetched instruction words in the instruction
6291 i
= max_insn_size
- sched_ib
.filled
;
6295 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6300 /* Return X or Y (depending on OPX_P) operand of INSN,
6301 if it is an integer register, or NULL overwise. */
6303 sched_get_reg_operand (rtx insn
, bool opx_p
)
6309 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6311 op
= sched_get_operand (insn
, true);
6312 gcc_assert (op
!= NULL
);
6314 if (!reload_completed
&& !REG_P (op
))
6320 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6322 op
= sched_get_operand (insn
, false);
6323 gcc_assert (op
!= NULL
);
6325 if (!reload_completed
&& !REG_P (op
))
6333 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6336 sched_mem_operand_p (rtx insn
, bool opx_p
)
6338 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6349 /* Return X or Y (depending on OPX_P) operand of INSN,
6350 if it is a MEM, or NULL overwise. */
6352 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6372 if (opy_p
&& sched_mem_operand_p (insn
, false))
6373 return sched_get_operand (insn
, false);
6375 if (opx_p
&& sched_mem_operand_p (insn
, true))
6376 return sched_get_operand (insn
, true);
6382 /* Return non-zero if PRO modifies register used as part of
6385 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6390 pro_x
= sched_get_reg_operand (pro
, true);
6394 con_mem_read
= sched_get_mem_operand (con
, true, false);
6395 gcc_assert (con_mem_read
!= NULL
);
6397 if (reg_mentioned_p (pro_x
, con_mem_read
))
6403 /* Helper function for m68k_sched_indexed_address_bypass_p.
6404 if PRO modifies register used as index in CON,
6405 return scale of indexed memory access in CON. Return zero overwise. */
6407 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6411 struct m68k_address address
;
6413 reg
= sched_get_reg_operand (pro
, true);
6417 mem
= sched_get_mem_operand (con
, true, false);
6418 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6420 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6424 if (REGNO (reg
) == REGNO (address
.index
))
6426 gcc_assert (address
.scale
!= 0);
6427 return address
.scale
;
6433 /* Return non-zero if PRO modifies register used
6434 as index with scale 2 or 4 in CON. */
6436 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6438 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6439 && sched_cfv4_bypass_data
.con
== NULL
6440 && sched_cfv4_bypass_data
.scale
== 0);
6442 switch (sched_get_indexed_address_scale (pro
, con
))
6445 /* We can't have a variable latency bypass, so
6446 remember to adjust the insn cost in adjust_cost hook. */
6447 sched_cfv4_bypass_data
.pro
= pro
;
6448 sched_cfv4_bypass_data
.con
= con
;
6449 sched_cfv4_bypass_data
.scale
= 1;
6461 /* We generate a two-instructions program at M_TRAMP :
6462 movea.l &CHAIN_VALUE,%a0
6464 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6467 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6469 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6472 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6474 mem
= adjust_address (m_tramp
, HImode
, 0);
6475 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6476 mem
= adjust_address (m_tramp
, SImode
, 2);
6477 emit_move_insn (mem
, chain_value
);
6479 mem
= adjust_address (m_tramp
, HImode
, 6);
6480 emit_move_insn (mem
, GEN_INT(0x4EF9));
6481 mem
= adjust_address (m_tramp
, SImode
, 8);
6482 emit_move_insn (mem
, fnaddr
);
6484 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6487 /* On the 68000, the RTS insn cannot pop anything.
6488 On the 68010, the RTD insn may be used to pop them if the number
6489 of args is fixed, but if the number is variable then the caller
6490 must pop them all. RTD can't be used for library calls now
6491 because the library is compiled with the Unix compiler.
6492 Use of RTD is a selectable option, since it is incompatible with
6493 standard Unix calling sequences. If the option is not selected,
6494 the caller must always pop the args. */
6497 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6501 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6502 && (!stdarg_p (funtype
)))
6506 /* Make sure everything's fine if we *don't* have a given processor.
6507 This assumes that putting a register in fixed_regs will keep the
6508 compiler's mitts completely off it. We don't bother to zero it out
6509 of register classes. */
6512 m68k_conditional_register_usage (void)
6516 if (!TARGET_HARD_FLOAT
)
6518 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6519 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6520 if (TEST_HARD_REG_BIT (x
, i
))
6521 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6524 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6527 #include "gt-m68k.h"