1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #define IN_TARGET_CODE 1
23 #define INCLUDE_STRING
25 #include "coretypes.h"
29 #include "stringpool.h"
34 #include "fold-const.h"
36 #include "stor-layout.h"
39 #include "insn-config.h"
40 #include "conditions.h"
42 #include "insn-attr.h"
44 #include "diagnostic-core.h"
61 #include "cfgcleanup.h"
62 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
63 #include "sched-int.h"
64 #include "insn-codes.h"
71 /* This file should be included last. */
72 #include "target-def.h"
74 enum reg_class regno_reg_class
[] =
76 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
77 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
78 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
79 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
80 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
81 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
86 /* The minimum number of integer registers that we want to save with the
87 movem instruction. Using two movel instructions instead of a single
88 moveml is about 15% faster for the 68020 and 68030 at no expense in
90 #define MIN_MOVEM_REGS 3
92 /* The minimum number of floating point registers that we want to save
93 with the fmovem instruction. */
94 #define MIN_FMOVEM_REGS 1
96 /* Structure describing stack frame layout. */
99 /* Stack pointer to frame pointer offset. */
100 HOST_WIDE_INT offset
;
102 /* Offset of FPU registers. */
103 HOST_WIDE_INT foffset
;
105 /* Frame size in bytes (rounded up). */
108 /* Data and address register. */
110 unsigned int reg_mask
;
114 unsigned int fpu_mask
;
116 /* Offsets relative to ARG_POINTER. */
117 HOST_WIDE_INT frame_pointer_offset
;
118 HOST_WIDE_INT stack_pointer_offset
;
120 /* Function which the above information refers to. */
124 /* Current frame information calculated by m68k_compute_frame_layout(). */
125 static struct m68k_frame current_frame
;
127 /* Structure describing an m68k address.
129 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
130 with null fields evaluating to 0. Here:
132 - BASE satisfies m68k_legitimate_base_reg_p
133 - INDEX satisfies m68k_legitimate_index_reg_p
134 - OFFSET satisfies m68k_legitimate_constant_address_p
136 INDEX is either HImode or SImode. The other fields are SImode.
138 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
139 the address is (BASE)+. */
140 struct m68k_address
{
148 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
150 static int m68k_sched_issue_rate (void);
151 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
152 static void m68k_sched_md_init_global (FILE *, int, int);
153 static void m68k_sched_md_finish_global (FILE *, int);
154 static void m68k_sched_md_init (FILE *, int, int);
155 static void m68k_sched_dfa_pre_advance_cycle (void);
156 static void m68k_sched_dfa_post_advance_cycle (void);
157 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
159 static bool m68k_can_eliminate (const int, const int);
160 static void m68k_conditional_register_usage (void);
161 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
162 static void m68k_option_override (void);
163 static void m68k_override_options_after_change (void);
164 static rtx
find_addr_reg (rtx
);
165 static const char *singlemove_string (rtx
*);
166 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
167 HOST_WIDE_INT
, tree
);
168 static rtx
m68k_struct_value_rtx (tree
, int);
169 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
170 tree args
, int flags
,
172 static void m68k_compute_frame_layout (void);
173 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
174 static bool m68k_ok_for_sibcall_p (tree
, tree
);
175 static bool m68k_tls_symbol_p (rtx
);
176 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
177 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
178 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
179 static bool m68k_return_in_memory (const_tree
, const_tree
);
181 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
182 static void m68k_trampoline_init (rtx
, tree
, rtx
);
183 static poly_int64
m68k_return_pops_args (tree
, tree
, poly_int64
);
184 static rtx
m68k_delegitimize_address (rtx
);
185 static void m68k_function_arg_advance (cumulative_args_t
,
186 const function_arg_info
&);
187 static rtx
m68k_function_arg (cumulative_args_t
, const function_arg_info
&);
188 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
189 static bool m68k_output_addr_const_extra (FILE *, rtx
);
190 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
191 static enum flt_eval_method
192 m68k_excess_precision (enum excess_precision_type
);
193 static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode
);
194 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode
);
195 static bool m68k_modes_tieable_p (machine_mode
, machine_mode
);
196 static machine_mode
m68k_promote_function_mode (const_tree
, machine_mode
,
197 int *, const_tree
, int);
198 static void m68k_asm_final_postscan_insn (FILE *, rtx_insn
*insn
, rtx
[], int);
200 /* Initialize the GCC target structure. */
202 #if INT_OP_GROUP == INT_OP_DOT_WORD
203 #undef TARGET_ASM_ALIGNED_HI_OP
204 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
207 #if INT_OP_GROUP == INT_OP_NO_DOT
208 #undef TARGET_ASM_BYTE_OP
209 #define TARGET_ASM_BYTE_OP "\tbyte\t"
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
216 #if INT_OP_GROUP == INT_OP_DC
217 #undef TARGET_ASM_BYTE_OP
218 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
219 #undef TARGET_ASM_ALIGNED_HI_OP
220 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
225 #undef TARGET_ASM_UNALIGNED_HI_OP
226 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
227 #undef TARGET_ASM_UNALIGNED_SI_OP
228 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
230 #undef TARGET_ASM_OUTPUT_MI_THUNK
231 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
232 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
233 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
235 #undef TARGET_ASM_FILE_START_APP_OFF
236 #define TARGET_ASM_FILE_START_APP_OFF true
238 #undef TARGET_LEGITIMIZE_ADDRESS
239 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
244 #undef TARGET_SCHED_ISSUE_RATE
245 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
247 #undef TARGET_SCHED_VARIABLE_ISSUE
248 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
250 #undef TARGET_SCHED_INIT_GLOBAL
251 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
253 #undef TARGET_SCHED_FINISH_GLOBAL
254 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
256 #undef TARGET_SCHED_INIT
257 #define TARGET_SCHED_INIT m68k_sched_md_init
259 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
260 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
262 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
263 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
265 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
266 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
267 m68k_sched_first_cycle_multipass_dfa_lookahead
269 #undef TARGET_OPTION_OVERRIDE
270 #define TARGET_OPTION_OVERRIDE m68k_option_override
272 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
273 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
275 #undef TARGET_RTX_COSTS
276 #define TARGET_RTX_COSTS m68k_rtx_costs
278 #undef TARGET_ATTRIBUTE_TABLE
279 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
281 #undef TARGET_PROMOTE_PROTOTYPES
282 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
284 #undef TARGET_STRUCT_VALUE_RTX
285 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
287 #undef TARGET_CANNOT_FORCE_CONST_MEM
288 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
290 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
291 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
293 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
294 #undef TARGET_RETURN_IN_MEMORY
295 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
299 #undef TARGET_HAVE_TLS
300 #define TARGET_HAVE_TLS (true)
302 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
303 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
307 #define TARGET_LRA_P hook_bool_void_false
309 #undef TARGET_LEGITIMATE_ADDRESS_P
310 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
312 #undef TARGET_CAN_ELIMINATE
313 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
315 #undef TARGET_CONDITIONAL_REGISTER_USAGE
316 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
318 #undef TARGET_TRAMPOLINE_INIT
319 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
321 #undef TARGET_RETURN_POPS_ARGS
322 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
324 #undef TARGET_DELEGITIMIZE_ADDRESS
325 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
327 #undef TARGET_FUNCTION_ARG
328 #define TARGET_FUNCTION_ARG m68k_function_arg
330 #undef TARGET_FUNCTION_ARG_ADVANCE
331 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
333 #undef TARGET_LEGITIMATE_CONSTANT_P
334 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
336 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
337 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
339 #undef TARGET_C_EXCESS_PRECISION
340 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
342 /* The value stored by TAS. */
343 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
344 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
346 #undef TARGET_HARD_REGNO_NREGS
347 #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
348 #undef TARGET_HARD_REGNO_MODE_OK
349 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
351 #undef TARGET_MODES_TIEABLE_P
352 #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
354 #undef TARGET_PROMOTE_FUNCTION_MODE
355 #define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode
357 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
358 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
360 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
361 #define TARGET_ASM_FINAL_POSTSCAN_INSN m68k_asm_final_postscan_insn
363 static const struct attribute_spec m68k_attribute_table
[] =
365 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
366 affects_type_identity, handler, exclude } */
367 { "interrupt", 0, 0, true, false, false, false,
368 m68k_handle_fndecl_attribute
, NULL
},
369 { "interrupt_handler", 0, 0, true, false, false, false,
370 m68k_handle_fndecl_attribute
, NULL
},
371 { "interrupt_thread", 0, 0, true, false, false, false,
372 m68k_handle_fndecl_attribute
, NULL
},
373 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
376 struct gcc_target targetm
= TARGET_INITIALIZER
;
378 /* Base flags for 68k ISAs. */
379 #define FL_FOR_isa_00 FL_ISA_68000
380 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
381 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
382 generated 68881 code for 68020 and 68030 targets unless explicitly told
384 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
385 | FL_BITFIELD | FL_68881 | FL_CAS)
386 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
387 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
389 /* Base flags for ColdFire ISAs. */
390 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
391 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
392 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
393 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
394 /* ISA_C is not upwardly compatible with ISA_B. */
395 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
399 /* Traditional 68000 instruction sets. */
405 /* ColdFire instruction set variants. */
413 /* Information about one of the -march, -mcpu or -mtune arguments. */
414 struct m68k_target_selection
416 /* The argument being described. */
419 /* For -mcpu, this is the device selected by the option.
420 For -mtune and -march, it is a representative device
421 for the microarchitecture or ISA respectively. */
422 enum target_device device
;
424 /* The M68K_DEVICE fields associated with DEVICE. See the comment
425 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
427 enum uarch_type microarch
;
432 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
433 static const struct m68k_target_selection all_devices
[] =
435 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
436 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
437 #include "m68k-devices.def"
439 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
442 /* A list of all ISAs, mapping each one to a representative device.
443 Used for -march selection. */
444 static const struct m68k_target_selection all_isas
[] =
446 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
447 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
448 #include "m68k-isas.def"
450 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
453 /* A list of all microarchitectures, mapping each one to a representative
454 device. Used for -mtune selection. */
455 static const struct m68k_target_selection all_microarchs
[] =
457 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
458 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
459 #include "m68k-microarchs.def"
460 #undef M68K_MICROARCH
461 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
464 /* The entries associated with the -mcpu, -march and -mtune settings,
465 or null for options that have not been used. */
466 const struct m68k_target_selection
*m68k_cpu_entry
;
467 const struct m68k_target_selection
*m68k_arch_entry
;
468 const struct m68k_target_selection
*m68k_tune_entry
;
470 /* Which CPU we are generating code for. */
471 enum target_device m68k_cpu
;
473 /* Which microarchitecture to tune for. */
474 enum uarch_type m68k_tune
;
476 /* Which FPU to use. */
477 enum fpu_type m68k_fpu
;
479 /* The set of FL_* flags that apply to the target processor. */
480 unsigned int m68k_cpu_flags
;
482 /* The set of FL_* flags that apply to the processor to be tuned for. */
483 unsigned int m68k_tune_flags
;
485 /* Asm templates for calling or jumping to an arbitrary symbolic address,
486 or NULL if such calls or jumps are not supported. The address is held
488 const char *m68k_symbolic_call
;
489 const char *m68k_symbolic_jump
;
491 /* Enum variable that corresponds to m68k_symbolic_call values. */
492 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
495 /* Implement TARGET_OPTION_OVERRIDE. */
498 m68k_option_override (void)
500 const struct m68k_target_selection
*entry
;
501 unsigned long target_mask
;
503 if (global_options_set
.x_m68k_arch_option
)
504 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
506 if (global_options_set
.x_m68k_cpu_option
)
507 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
509 if (global_options_set
.x_m68k_tune_option
)
510 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
518 -march=ARCH should generate code that runs any processor
519 implementing architecture ARCH. -mcpu=CPU should override -march
520 and should generate code that runs on processor CPU, making free
521 use of any instructions that CPU understands. -mtune=UARCH applies
522 on top of -mcpu or -march and optimizes the code for UARCH. It does
523 not change the target architecture. */
526 /* Complain if the -march setting is for a different microarchitecture,
527 or includes flags that the -mcpu setting doesn't. */
529 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
530 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
531 warning (0, "%<-mcpu=%s%> conflicts with %<-march=%s%>",
532 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
534 entry
= m68k_cpu_entry
;
537 entry
= m68k_arch_entry
;
540 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
542 m68k_cpu_flags
= entry
->flags
;
544 /* Use the architecture setting to derive default values for
548 /* ColdFire is lenient about alignment. */
549 if (!TARGET_COLDFIRE
)
550 target_mask
|= MASK_STRICT_ALIGNMENT
;
552 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
553 target_mask
|= MASK_BITFIELD
;
554 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
555 target_mask
|= MASK_CF_HWDIV
;
556 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
557 target_mask
|= MASK_HARD_FLOAT
;
558 target_flags
|= target_mask
& ~target_flags_explicit
;
560 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
561 m68k_cpu
= entry
->device
;
564 m68k_tune
= m68k_tune_entry
->microarch
;
565 m68k_tune_flags
= m68k_tune_entry
->flags
;
567 #ifdef M68K_DEFAULT_TUNE
568 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
570 enum target_device dev
;
571 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
572 m68k_tune_flags
= all_devices
[dev
].flags
;
577 m68k_tune
= entry
->microarch
;
578 m68k_tune_flags
= entry
->flags
;
581 /* Set the type of FPU. */
582 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
583 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
586 /* Sanity check to ensure that msep-data and mid-sahred-library are not
587 * both specified together. Doing so simply doesn't make sense.
589 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
590 error ("cannot specify both %<-msep-data%> and %<-mid-shared-library%>");
592 /* If we're generating code for a separate A5 relative data segment,
593 * we've got to enable -fPIC as well. This might be relaxable to
594 * -fpic but it hasn't been tested properly.
596 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
599 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
600 error if the target does not support them. */
601 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
602 error ("%<-mpcrel%> %<-fPIC%> is not currently supported on selected cpu");
604 /* ??? A historic way of turning on pic, or is this intended to
605 be an embedded thing that doesn't have the same name binding
606 significance that it does on hosted ELF systems? */
607 if (TARGET_PCREL
&& flag_pic
== 0)
612 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
614 m68k_symbolic_jump
= "jra %a0";
616 else if (TARGET_ID_SHARED_LIBRARY
)
617 /* All addresses must be loaded from the GOT. */
619 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
622 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
624 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
627 /* No unconditional long branch */;
628 else if (TARGET_PCREL
)
629 m68k_symbolic_jump
= "bra%.l %c0";
631 m68k_symbolic_jump
= "bra%.l %p0";
632 /* Turn off function cse if we are doing PIC. We always want
633 function call to be done as `bsr foo@PLTPC'. */
634 /* ??? It's traditional to do this for -mpcrel too, but it isn't
635 clear how intentional that is. */
636 flag_no_function_cse
= 1;
639 switch (m68k_symbolic_call_var
)
641 case M68K_SYMBOLIC_CALL_JSR
:
642 m68k_symbolic_call
= "jsr %a0";
645 case M68K_SYMBOLIC_CALL_BSR_C
:
646 m68k_symbolic_call
= "bsr%.l %c0";
649 case M68K_SYMBOLIC_CALL_BSR_P
:
650 m68k_symbolic_call
= "bsr%.l %p0";
653 case M68K_SYMBOLIC_CALL_NONE
:
654 gcc_assert (m68k_symbolic_call
== NULL
);
661 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
662 parse_alignment_opts ();
663 int label_alignment
= align_labels
.levels
[0].get_value ();
664 if (label_alignment
> 2)
666 warning (0, "%<-falign-labels=%d%> is not supported", label_alignment
);
667 str_align_labels
= "1";
670 int loop_alignment
= align_loops
.levels
[0].get_value ();
671 if (loop_alignment
> 2)
673 warning (0, "%<-falign-loops=%d%> is not supported", loop_alignment
);
674 str_align_loops
= "1";
678 if ((opt_fstack_limit_symbol_arg
!= NULL
|| opt_fstack_limit_register_no
>= 0)
681 warning (0, "%<-fstack-limit-%> options are not supported on this cpu");
682 opt_fstack_limit_symbol_arg
= NULL
;
683 opt_fstack_limit_register_no
= -1;
686 SUBTARGET_OVERRIDE_OPTIONS
;
688 /* Setup scheduling options. */
690 m68k_sched_cpu
= CPU_CFV1
;
692 m68k_sched_cpu
= CPU_CFV2
;
694 m68k_sched_cpu
= CPU_CFV3
;
696 m68k_sched_cpu
= CPU_CFV4
;
699 m68k_sched_cpu
= CPU_UNKNOWN
;
700 flag_schedule_insns
= 0;
701 flag_schedule_insns_after_reload
= 0;
702 flag_modulo_sched
= 0;
703 flag_live_range_shrinkage
= 0;
706 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
708 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
709 m68k_sched_mac
= MAC_CF_EMAC
;
710 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
711 m68k_sched_mac
= MAC_CF_MAC
;
713 m68k_sched_mac
= MAC_NO
;
717 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
720 m68k_override_options_after_change (void)
722 if (m68k_sched_cpu
== CPU_UNKNOWN
)
724 flag_schedule_insns
= 0;
725 flag_schedule_insns_after_reload
= 0;
726 flag_modulo_sched
= 0;
727 flag_live_range_shrinkage
= 0;
731 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
732 given argument and NAME is the argument passed to -mcpu. Return NULL
733 if -mcpu was not passed. */
736 m68k_cpp_cpu_ident (const char *prefix
)
740 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
743 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
744 given argument and NAME is the name of the representative device for
745 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
748 m68k_cpp_cpu_family (const char *prefix
)
752 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
755 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
756 "interrupt_handler" attribute and interrupt_thread if FUNC has an
757 "interrupt_thread" attribute. Otherwise, return
758 m68k_fk_normal_function. */
760 enum m68k_function_kind
761 m68k_get_function_kind (tree func
)
765 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
767 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
769 return m68k_fk_interrupt_handler
;
771 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
773 return m68k_fk_interrupt_handler
;
775 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
777 return m68k_fk_interrupt_thread
;
779 return m68k_fk_normal_function
;
782 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
783 struct attribute_spec.handler. */
785 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
786 tree args ATTRIBUTE_UNUSED
,
787 int flags ATTRIBUTE_UNUSED
,
790 if (TREE_CODE (*node
) != FUNCTION_DECL
)
792 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
794 *no_add_attrs
= true;
797 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
799 error ("multiple interrupt attributes not allowed");
800 *no_add_attrs
= true;
804 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
806 error ("interrupt_thread is available only on fido");
807 *no_add_attrs
= true;
814 m68k_compute_frame_layout (void)
818 enum m68k_function_kind func_kind
=
819 m68k_get_function_kind (current_function_decl
);
820 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
821 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
823 /* Only compute the frame once per function.
824 Don't cache information until reload has been completed. */
825 if (current_frame
.funcdef_no
== current_function_funcdef_no
829 current_frame
.size
= (get_frame_size () + 3) & -4;
833 /* Interrupt thread does not need to save any register. */
834 if (!interrupt_thread
)
835 for (regno
= 0; regno
< 16; regno
++)
836 if (m68k_save_reg (regno
, interrupt_handler
))
838 mask
|= 1 << (regno
- D0_REG
);
841 current_frame
.offset
= saved
* 4;
842 current_frame
.reg_no
= saved
;
843 current_frame
.reg_mask
= mask
;
845 current_frame
.foffset
= 0;
847 if (TARGET_HARD_FLOAT
)
849 /* Interrupt thread does not need to save any register. */
850 if (!interrupt_thread
)
851 for (regno
= 16; regno
< 24; regno
++)
852 if (m68k_save_reg (regno
, interrupt_handler
))
854 mask
|= 1 << (regno
- FP0_REG
);
857 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
858 current_frame
.offset
+= current_frame
.foffset
;
860 current_frame
.fpu_no
= saved
;
861 current_frame
.fpu_mask
= mask
;
863 /* Remember what function this frame refers to. */
864 current_frame
.funcdef_no
= current_function_funcdef_no
;
867 /* Worker function for TARGET_CAN_ELIMINATE. */
870 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
872 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
876 m68k_initial_elimination_offset (int from
, int to
)
879 /* The arg pointer points 8 bytes before the start of the arguments,
880 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
881 frame pointer in most frames. */
882 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
883 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
884 return argptr_offset
;
886 m68k_compute_frame_layout ();
888 gcc_assert (to
== STACK_POINTER_REGNUM
);
891 case ARG_POINTER_REGNUM
:
892 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
893 case FRAME_POINTER_REGNUM
:
894 return current_frame
.offset
+ current_frame
.size
;
900 /* Refer to the array `regs_ever_live' to determine which registers
901 to save; `regs_ever_live[I]' is nonzero if register number I
902 is ever used in the function. This function is responsible for
903 knowing which registers should not be saved even if used.
904 Return true if we need to save REGNO. */
907 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
909 if (flag_pic
&& regno
== PIC_REG
)
911 if (crtl
->saves_all_registers
)
913 if (crtl
->uses_pic_offset_table
)
915 /* Reload may introduce constant pool references into a function
916 that thitherto didn't need a PIC register. Note that the test
917 above will not catch that case because we will only set
918 crtl->uses_pic_offset_table when emitting
919 the address reloads. */
920 if (crtl
->uses_const_pool
)
924 if (crtl
->calls_eh_return
)
929 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
930 if (test
== INVALID_REGNUM
)
937 /* Fixed regs we never touch. */
938 if (fixed_regs
[regno
])
941 /* The frame pointer (if it is such) is handled specially. */
942 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
945 /* Interrupt handlers must also save call_used_regs
946 if they are live or when calling nested functions. */
947 if (interrupt_handler
)
949 if (df_regs_ever_live_p (regno
))
952 if (!crtl
->is_leaf
&& call_used_or_fixed_reg_p (regno
))
956 /* Never need to save registers that aren't touched. */
957 if (!df_regs_ever_live_p (regno
))
960 /* Otherwise save everything that isn't call-clobbered. */
961 return !call_used_or_fixed_reg_p (regno
);
964 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
965 the lowest memory address. COUNT is the number of registers to be
966 moved, with register REGNO + I being moved if bit I of MASK is set.
967 STORE_P specifies the direction of the move and ADJUST_STACK_P says
968 whether or not this is pre-decrement (if STORE_P) or post-increment
969 (if !STORE_P) operation. */
972 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
973 unsigned int count
, unsigned int regno
,
974 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
977 rtx body
, addr
, src
, operands
[2];
980 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
981 mode
= reg_raw_mode
[regno
];
986 src
= plus_constant (Pmode
, base
,
988 * GET_MODE_SIZE (mode
)
989 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
990 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
993 for (; mask
!= 0; mask
>>= 1, regno
++)
996 addr
= plus_constant (Pmode
, base
, offset
);
997 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
998 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
999 XVECEXP (body
, 0, i
++)
1000 = gen_rtx_SET (operands
[0], operands
[1]);
1001 offset
+= GET_MODE_SIZE (mode
);
1003 gcc_assert (i
== XVECLEN (body
, 0));
1005 return emit_insn (body
);
1008 /* Make INSN a frame-related instruction. */
1011 m68k_set_frame_related (rtx_insn
*insn
)
1016 RTX_FRAME_RELATED_P (insn
) = 1;
1017 body
= PATTERN (insn
);
1018 if (GET_CODE (body
) == PARALLEL
)
1019 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1020 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1023 /* Emit RTL for the "prologue" define_expand. */
1026 m68k_expand_prologue (void)
1028 HOST_WIDE_INT fsize_with_regs
;
1029 rtx limit
, src
, dest
;
1031 m68k_compute_frame_layout ();
1033 if (flag_stack_usage_info
)
1034 current_function_static_stack_size
1035 = current_frame
.size
+ current_frame
.offset
;
1037 /* If the stack limit is a symbol, we can check it here,
1038 before actually allocating the space. */
1039 if (crtl
->limit_stack
1040 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1042 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1043 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1045 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1046 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1048 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1049 stack_pointer_rtx
, limit
),
1050 stack_pointer_rtx
, limit
,
1054 fsize_with_regs
= current_frame
.size
;
1055 if (TARGET_COLDFIRE
)
1057 /* ColdFire's move multiple instructions do not allow pre-decrement
1058 addressing. Add the size of movem saves to the initial stack
1059 allocation instead. */
1060 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1061 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1062 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1063 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1066 if (frame_pointer_needed
)
1068 if (fsize_with_regs
== 0 && TUNE_68040
)
1070 /* On the 68040, two separate moves are faster than link.w 0. */
1071 dest
= gen_frame_mem (Pmode
,
1072 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1073 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1074 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1075 stack_pointer_rtx
));
1077 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1078 m68k_set_frame_related
1079 (emit_insn (gen_link (frame_pointer_rtx
,
1080 GEN_INT (-4 - fsize_with_regs
))));
1083 m68k_set_frame_related
1084 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1085 m68k_set_frame_related
1086 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1088 GEN_INT (-fsize_with_regs
))));
1091 /* If the frame pointer is needed, emit a special barrier that
1092 will prevent the scheduler from moving stores to the frame
1093 before the stack adjustment. */
1094 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1096 else if (fsize_with_regs
!= 0)
1097 m68k_set_frame_related
1098 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1100 GEN_INT (-fsize_with_regs
))));
1102 if (current_frame
.fpu_mask
)
1104 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1106 m68k_set_frame_related
1107 (m68k_emit_movem (stack_pointer_rtx
,
1108 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1109 current_frame
.fpu_no
, FP0_REG
,
1110 current_frame
.fpu_mask
, true, true));
1115 /* If we're using moveml to save the integer registers,
1116 the stack pointer will point to the bottom of the moveml
1117 save area. Find the stack offset of the first FP register. */
1118 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1121 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1122 m68k_set_frame_related
1123 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1124 current_frame
.fpu_no
, FP0_REG
,
1125 current_frame
.fpu_mask
, true, false));
1129 /* If the stack limit is not a symbol, check it here.
1130 This has the disadvantage that it may be too late... */
1131 if (crtl
->limit_stack
)
1133 if (REG_P (stack_limit_rtx
))
1134 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1136 stack_pointer_rtx
, stack_limit_rtx
,
1139 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1140 warning (0, "stack limit expression is not supported");
1143 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1145 /* Store each register separately in the same order moveml does. */
1148 for (i
= 16; i
-- > 0; )
1149 if (current_frame
.reg_mask
& (1 << i
))
1151 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1152 dest
= gen_frame_mem (SImode
,
1153 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1154 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1159 if (TARGET_COLDFIRE
)
1160 /* The required register save space has already been allocated.
1161 The first register should be stored at (%sp). */
1162 m68k_set_frame_related
1163 (m68k_emit_movem (stack_pointer_rtx
, 0,
1164 current_frame
.reg_no
, D0_REG
,
1165 current_frame
.reg_mask
, true, false));
1167 m68k_set_frame_related
1168 (m68k_emit_movem (stack_pointer_rtx
,
1169 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1170 current_frame
.reg_no
, D0_REG
,
1171 current_frame
.reg_mask
, true, true));
1174 if (!TARGET_SEP_DATA
1175 && crtl
->uses_pic_offset_table
)
1176 emit_insn (gen_load_got (pic_offset_table_rtx
));
1179 /* Return true if a simple (return) instruction is sufficient for this
1180 instruction (i.e. if no epilogue is needed). */
1183 m68k_use_return_insn (void)
1185 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1188 m68k_compute_frame_layout ();
1189 return current_frame
.offset
== 0;
1192 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1193 SIBCALL_P says which.
1195 The function epilogue should not depend on the current stack pointer!
1196 It should use the frame pointer only, if there is a frame pointer.
1197 This is mandatory because of alloca; we also take advantage of it to
1198 omit stack adjustments before returning. */
1201 m68k_expand_epilogue (bool sibcall_p
)
1203 HOST_WIDE_INT fsize
, fsize_with_regs
;
1204 bool big
, restore_from_sp
;
1206 m68k_compute_frame_layout ();
1208 fsize
= current_frame
.size
;
1210 restore_from_sp
= false;
1212 /* FIXME : crtl->is_leaf below is too strong.
1213 What we really need to know there is if there could be pending
1214 stack adjustment needed at that point. */
1215 restore_from_sp
= (!frame_pointer_needed
1216 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1218 /* fsize_with_regs is the size we need to adjust the sp when
1219 popping the frame. */
1220 fsize_with_regs
= fsize
;
1221 if (TARGET_COLDFIRE
&& restore_from_sp
)
1223 /* ColdFire's move multiple instructions do not allow post-increment
1224 addressing. Add the size of movem loads to the final deallocation
1226 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1227 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1228 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1229 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1232 if (current_frame
.offset
+ fsize
>= 0x8000
1234 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1237 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1238 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1240 /* ColdFire's move multiple instructions do not support the
1241 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1242 stack-based restore. */
1243 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1244 GEN_INT (-(current_frame
.offset
+ fsize
)));
1245 emit_insn (gen_blockage ());
1246 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1247 gen_rtx_REG (Pmode
, A1_REG
),
1248 frame_pointer_rtx
));
1249 restore_from_sp
= true;
1253 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1259 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1261 /* Restore each register separately in the same order moveml does. */
1263 HOST_WIDE_INT offset
;
1265 offset
= current_frame
.offset
+ fsize
;
1266 for (i
= 0; i
< 16; i
++)
1267 if (current_frame
.reg_mask
& (1 << i
))
1273 /* Generate the address -OFFSET(%fp,%a1.l). */
1274 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1275 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1276 addr
= plus_constant (Pmode
, addr
, -offset
);
1278 else if (restore_from_sp
)
1279 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1281 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1282 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1283 gen_frame_mem (SImode
, addr
));
1284 offset
-= GET_MODE_SIZE (SImode
);
1287 else if (current_frame
.reg_mask
)
1290 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1291 gen_rtx_REG (Pmode
, A1_REG
),
1293 -(current_frame
.offset
+ fsize
),
1294 current_frame
.reg_no
, D0_REG
,
1295 current_frame
.reg_mask
, false, false);
1296 else if (restore_from_sp
)
1297 m68k_emit_movem (stack_pointer_rtx
, 0,
1298 current_frame
.reg_no
, D0_REG
,
1299 current_frame
.reg_mask
, false,
1302 m68k_emit_movem (frame_pointer_rtx
,
1303 -(current_frame
.offset
+ fsize
),
1304 current_frame
.reg_no
, D0_REG
,
1305 current_frame
.reg_mask
, false, false);
1308 if (current_frame
.fpu_no
> 0)
1311 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1312 gen_rtx_REG (Pmode
, A1_REG
),
1314 -(current_frame
.foffset
+ fsize
),
1315 current_frame
.fpu_no
, FP0_REG
,
1316 current_frame
.fpu_mask
, false, false);
1317 else if (restore_from_sp
)
1319 if (TARGET_COLDFIRE
)
1323 /* If we used moveml to restore the integer registers, the
1324 stack pointer will still point to the bottom of the moveml
1325 save area. Find the stack offset of the first FP
1327 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1330 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1331 m68k_emit_movem (stack_pointer_rtx
, offset
,
1332 current_frame
.fpu_no
, FP0_REG
,
1333 current_frame
.fpu_mask
, false, false);
1336 m68k_emit_movem (stack_pointer_rtx
, 0,
1337 current_frame
.fpu_no
, FP0_REG
,
1338 current_frame
.fpu_mask
, false, true);
1341 m68k_emit_movem (frame_pointer_rtx
,
1342 -(current_frame
.foffset
+ fsize
),
1343 current_frame
.fpu_no
, FP0_REG
,
1344 current_frame
.fpu_mask
, false, false);
1347 emit_insn (gen_blockage ());
1348 if (frame_pointer_needed
)
1349 emit_insn (gen_unlink (frame_pointer_rtx
));
1350 else if (fsize_with_regs
)
1351 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1353 GEN_INT (fsize_with_regs
)));
1355 if (crtl
->calls_eh_return
)
1356 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1358 EH_RETURN_STACKADJ_RTX
));
1361 emit_jump_insn (ret_rtx
);
1364 /* Return true if PARALLEL contains register REGNO. */
1366 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1370 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1373 if (GET_CODE (parallel
) != PARALLEL
)
1376 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1380 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1381 if (REG_P (x
) && REGNO (x
) == regno
)
1388 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1391 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1393 enum m68k_function_kind kind
;
1395 /* We cannot use sibcalls for nested functions because we use the
1396 static chain register for indirect calls. */
1397 if (CALL_EXPR_STATIC_CHAIN (exp
))
1400 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1402 /* Check that the return value locations are the same. For
1403 example that we aren't returning a value from the sibling in
1404 a D0 register but then need to transfer it to a A0 register. */
1408 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1410 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1412 /* Check that the values are equal or that the result the callee
1413 function returns is superset of what the current function returns. */
1414 if (!(rtx_equal_p (cfun_value
, call_value
)
1415 || (REG_P (cfun_value
)
1416 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1420 kind
= m68k_get_function_kind (current_function_decl
);
1421 if (kind
== m68k_fk_normal_function
)
1422 /* We can always sibcall from a normal function, because it's
1423 undefined if it is calling an interrupt function. */
1426 /* Otherwise we can only sibcall if the function kind is known to be
1428 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1434 /* On the m68k all args are always pushed. */
1437 m68k_function_arg (cumulative_args_t
, const function_arg_info
&)
1443 m68k_function_arg_advance (cumulative_args_t cum_v
,
1444 const function_arg_info
&arg
)
1446 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1448 *cum
+= (arg
.promoted_size_in_bytes () + 3) & ~3;
1451 /* Convert X to a legitimate function call memory reference and return the
1455 m68k_legitimize_call_address (rtx x
)
1457 gcc_assert (MEM_P (x
));
1458 if (call_operand (XEXP (x
, 0), VOIDmode
))
1460 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1463 /* Likewise for sibling calls. */
1466 m68k_legitimize_sibcall_address (rtx x
)
1468 gcc_assert (MEM_P (x
));
1469 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1472 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1473 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1476 /* Convert X to a legitimate address and return it if successful. Otherwise
1479 For the 68000, we handle X+REG by loading X into a register R and
1480 using R+REG. R will go in an address reg and indexing will be used.
1481 However, if REG is a broken-out memory address or multiplication,
1482 nothing needs to be done because REG can certainly go in an address reg. */
1485 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1487 if (m68k_tls_symbol_p (x
))
1488 return m68k_legitimize_tls_address (x
);
1490 if (GET_CODE (x
) == PLUS
)
1492 int ch
= (x
) != (oldx
);
1495 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1497 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1500 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1502 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1505 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1509 if (GET_CODE (XEXP (x
, 1)) == REG
1510 && GET_CODE (XEXP (x
, 0)) == REG
)
1512 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1515 x
= force_operand (x
, 0);
1519 if (memory_address_p (mode
, x
))
1522 if (GET_CODE (XEXP (x
, 0)) == REG
1523 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1524 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1525 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1527 rtx temp
= gen_reg_rtx (Pmode
);
1528 rtx val
= force_operand (XEXP (x
, 1), 0);
1529 emit_move_insn (temp
, val
);
1532 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1533 && GET_CODE (XEXP (x
, 0)) == REG
)
1534 x
= force_operand (x
, 0);
1536 else if (GET_CODE (XEXP (x
, 1)) == REG
1537 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1538 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1539 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1541 rtx temp
= gen_reg_rtx (Pmode
);
1542 rtx val
= force_operand (XEXP (x
, 0), 0);
1543 emit_move_insn (temp
, val
);
1546 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1547 && GET_CODE (XEXP (x
, 1)) == REG
)
1548 x
= force_operand (x
, 0);
1555 /* For eliding comparisons, we remember how the flags were set.
1556 FLAGS_COMPARE_OP0 and FLAGS_COMPARE_OP1 are remembered for a direct
1557 comparison, they take priority. FLAGS_OPERAND1 and FLAGS_OPERAND2
1558 are used in more cases, they are a fallback for comparisons against
1559 zero after a move or arithmetic insn.
1560 FLAGS_VALID is set to FLAGS_VALID_NO if we should not use any of
1563 static rtx flags_compare_op0
, flags_compare_op1
;
1564 static rtx flags_operand1
, flags_operand2
;
1565 static attr_flags_valid flags_valid
= FLAGS_VALID_NO
;
1567 /* Return a code other than UNKNOWN if we can elide a CODE comparison of
1571 m68k_find_flags_value (rtx op0
, rtx op1
, rtx_code code
)
1573 if (flags_compare_op0
!= NULL_RTX
)
1575 if (rtx_equal_p (op0
, flags_compare_op0
)
1576 && rtx_equal_p (op1
, flags_compare_op1
))
1578 if (rtx_equal_p (op0
, flags_compare_op1
)
1579 && rtx_equal_p (op1
, flags_compare_op0
))
1580 return swap_condition (code
);
1584 machine_mode mode
= GET_MODE (op0
);
1585 if (op1
!= CONST0_RTX (mode
))
1587 /* Comparisons against 0 with these two should have been optimized out. */
1588 gcc_assert (code
!= LTU
&& code
!= GEU
);
1589 if (flags_valid
== FLAGS_VALID_NOOV
&& (code
== GT
|| code
== LE
))
1591 if (rtx_equal_p (flags_operand1
, op0
) || rtx_equal_p (flags_operand2
, op0
))
1592 return (FLOAT_MODE_P (mode
) ? code
1593 : code
== GE
? PLUS
: code
== LT
? MINUS
: code
);
1594 /* See if we are testing whether the high part of a DImode value is
1595 positive or negative and we have the full value as a remembered
1597 if (code
!= GE
&& code
!= LT
)
1600 && flags_operand1
!= NULL_RTX
&& GET_MODE (flags_operand1
) == DImode
1601 && REG_P (flags_operand1
) && REG_P (op0
)
1602 && hard_regno_nregs (REGNO (flags_operand1
), DImode
) == 2
1603 && REGNO (flags_operand1
) == REGNO (op0
))
1604 return code
== GE
? PLUS
: MINUS
;
1606 && flags_operand2
!= NULL_RTX
&& GET_MODE (flags_operand2
) == DImode
1607 && REG_P (flags_operand2
) && REG_P (op0
)
1608 && hard_regno_nregs (REGNO (flags_operand2
), DImode
) == 2
1609 && REGNO (flags_operand2
) == REGNO (op0
))
1610 return code
== GE
? PLUS
: MINUS
;
1614 /* Called through CC_STATUS_INIT, which is invoked by final whenever a
1615 label is encountered. */
1620 flags_compare_op0
= flags_compare_op1
= NULL_RTX
;
1621 flags_operand1
= flags_operand2
= NULL_RTX
;
1622 flags_valid
= FLAGS_VALID_NO
;
1625 /* Update flags for a move operation with OPERANDS. Called for move
1626 operations where attr_flags_valid returns "set". */
1629 handle_flags_for_move (rtx
*operands
)
1631 flags_compare_op0
= flags_compare_op1
= NULL_RTX
;
1632 if (!ADDRESS_REG_P (operands
[0]))
1634 flags_valid
= FLAGS_VALID_MOVE
;
1635 flags_operand1
= side_effects_p (operands
[0]) ? NULL_RTX
: operands
[0];
1636 if (side_effects_p (operands
[1])
1637 /* ??? For mem->mem moves, this can discard the source as a
1638 valid compare operand. If you assume aligned moves, this
1639 is unnecessary, but in theory, we could have an unaligned
1640 move overwriting parts of its source. */
1641 || modified_in_p (operands
[1], current_output_insn
))
1642 flags_operand2
= NULL_RTX
;
1644 flags_operand2
= operands
[1];
1647 if (flags_operand1
!= NULL_RTX
1648 && modified_in_p (flags_operand1
, current_output_insn
))
1649 flags_operand1
= NULL_RTX
;
1650 if (flags_operand2
!= NULL_RTX
1651 && modified_in_p (flags_operand2
, current_output_insn
))
1652 flags_operand2
= NULL_RTX
;
1655 /* Process INSN to remember flag operands if possible. */
1658 m68k_asm_final_postscan_insn (FILE *, rtx_insn
*insn
, rtx
[], int)
1660 enum attr_flags_valid v
= get_attr_flags_valid (insn
);
1661 if (v
== FLAGS_VALID_SET
)
1663 /* Comparisons use FLAGS_VALID_SET, so we can be sure we need to clear these
1665 flags_compare_op0
= flags_compare_op1
= NULL_RTX
;
1667 if (v
== FLAGS_VALID_NO
)
1669 flags_operand1
= flags_operand2
= NULL_RTX
;
1672 else if (v
== FLAGS_VALID_UNCHANGED
)
1674 if (flags_operand1
!= NULL_RTX
&& modified_in_p (flags_operand1
, insn
))
1675 flags_operand1
= NULL_RTX
;
1676 if (flags_operand2
!= NULL_RTX
&& modified_in_p (flags_operand2
, insn
))
1677 flags_operand2
= NULL_RTX
;
1682 rtx set
= single_set (insn
);
1683 rtx dest
= SET_DEST (set
);
1684 rtx src
= SET_SRC (set
);
1685 if (side_effects_p (dest
))
1690 case FLAGS_VALID_YES
:
1691 case FLAGS_VALID_NOOV
:
1692 flags_operand1
= dest
;
1693 flags_operand2
= NULL_RTX
;
1695 case FLAGS_VALID_MOVE
:
1696 /* fmoves to memory or data registers do not set the condition
1697 codes. Normal moves _do_ set the condition codes, but not in
1698 a way that is appropriate for comparison with 0, because -0.0
1699 would be treated as a negative nonzero number. Note that it
1700 isn't appropriate to conditionalize this restriction on
1701 HONOR_SIGNED_ZEROS because that macro merely indicates whether
1702 we care about the difference between -0.0 and +0.0. */
1703 if (dest
!= NULL_RTX
1706 || GET_CODE (src
) == FIX
1707 || FLOAT_MODE_P (GET_MODE (dest
))))
1708 flags_operand1
= flags_operand2
= NULL_RTX
;
1711 flags_operand1
= dest
;
1712 if (GET_MODE (src
) != VOIDmode
&& !side_effects_p (src
)
1713 && !modified_in_p (src
, insn
))
1714 flags_operand2
= src
;
1716 flags_operand2
= NULL_RTX
;
1725 /* Output a dbCC; jCC sequence. Note we do not handle the
1726 floating point version of this sequence (Fdbcc).
1727 OPERANDS are as in the two peepholes. CODE is the code
1728 returned by m68k_output_branch_<mode>. */
1731 output_dbcc_and_branch (rtx
*operands
, rtx_code code
)
1736 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1740 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1744 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1748 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1752 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1756 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1760 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1764 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1768 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1772 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1776 output_asm_insn ("dbpl %0,%l1\n\tjle %l2", operands
);
1780 output_asm_insn ("dbmi %0,%l1\n\tjle %l2", operands
);
1787 /* If the decrement is to be done in SImode, then we have
1788 to compensate for the fact that dbcc decrements in HImode. */
1789 switch (GET_MODE (operands
[0]))
1792 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1804 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1807 enum rtx_code op_code
= GET_CODE (op
);
1809 /* This does not produce a useful cc. */
1812 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1813 below. Swap the operands and change the op if these requirements
1814 are not fulfilled. */
1815 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1819 operand1
= operand2
;
1821 op_code
= swap_condition (op_code
);
1823 loperands
[0] = operand1
;
1824 if (GET_CODE (operand1
) == REG
)
1825 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1827 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1828 if (operand2
!= const0_rtx
)
1830 loperands
[2] = operand2
;
1831 if (GET_CODE (operand2
) == REG
)
1832 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1834 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1836 loperands
[4] = gen_label_rtx ();
1837 if (operand2
!= const0_rtx
)
1838 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1841 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1842 output_asm_insn ("tst%.l %0", loperands
);
1844 output_asm_insn ("cmp%.w #0,%0", loperands
);
1846 output_asm_insn ("jne %l4", loperands
);
1848 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1849 output_asm_insn ("tst%.l %1", loperands
);
1851 output_asm_insn ("cmp%.w #0,%1", loperands
);
1854 loperands
[5] = dest
;
1859 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1860 CODE_LABEL_NUMBER (loperands
[4]));
1861 output_asm_insn ("seq %5", loperands
);
1865 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1866 CODE_LABEL_NUMBER (loperands
[4]));
1867 output_asm_insn ("sne %5", loperands
);
1871 loperands
[6] = gen_label_rtx ();
1872 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1873 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1874 CODE_LABEL_NUMBER (loperands
[4]));
1875 output_asm_insn ("sgt %5", loperands
);
1876 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1877 CODE_LABEL_NUMBER (loperands
[6]));
1881 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1882 CODE_LABEL_NUMBER (loperands
[4]));
1883 output_asm_insn ("shi %5", loperands
);
1887 loperands
[6] = gen_label_rtx ();
1888 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1889 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1890 CODE_LABEL_NUMBER (loperands
[4]));
1891 output_asm_insn ("slt %5", loperands
);
1892 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1893 CODE_LABEL_NUMBER (loperands
[6]));
1897 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1898 CODE_LABEL_NUMBER (loperands
[4]));
1899 output_asm_insn ("scs %5", loperands
);
1903 loperands
[6] = gen_label_rtx ();
1904 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1905 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1906 CODE_LABEL_NUMBER (loperands
[4]));
1907 output_asm_insn ("sge %5", loperands
);
1908 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1909 CODE_LABEL_NUMBER (loperands
[6]));
1913 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1914 CODE_LABEL_NUMBER (loperands
[4]));
1915 output_asm_insn ("scc %5", loperands
);
1919 loperands
[6] = gen_label_rtx ();
1920 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1921 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1922 CODE_LABEL_NUMBER (loperands
[4]));
1923 output_asm_insn ("sle %5", loperands
);
1924 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1925 CODE_LABEL_NUMBER (loperands
[6]));
1929 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1930 CODE_LABEL_NUMBER (loperands
[4]));
1931 output_asm_insn ("sls %5", loperands
);
1941 m68k_output_btst (rtx countop
, rtx dataop
, rtx_code code
, int signpos
)
1947 if (GET_CODE (countop
) == CONST_INT
)
1949 register int count
= INTVAL (countop
);
1950 /* If COUNT is bigger than size of storage unit in use,
1951 advance to the containing unit of same size. */
1952 if (count
> signpos
)
1954 int offset
= (count
& ~signpos
) / 8;
1955 count
= count
& signpos
;
1956 ops
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1959 if (code
== EQ
|| code
== NE
)
1963 output_asm_insn ("tst%.l %1", ops
);
1964 return code
== EQ
? PLUS
: MINUS
;
1968 output_asm_insn ("tst%.w %1", ops
);
1969 return code
== EQ
? PLUS
: MINUS
;
1973 output_asm_insn ("tst%.b %1", ops
);
1974 return code
== EQ
? PLUS
: MINUS
;
1977 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1978 On some m68k variants unfortunately that's slower than btst.
1979 On 68000 and higher, that should also work for all HImode operands. */
1980 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1982 if (count
== 3 && DATA_REG_P (ops
[1]) && (code
== EQ
|| code
== NE
))
1984 output_asm_insn ("move%.w %1,%%ccr", ops
);
1985 return code
== EQ
? PLUS
: MINUS
;
1987 if (count
== 2 && DATA_REG_P (ops
[1]) && (code
== EQ
|| code
== NE
))
1989 output_asm_insn ("move%.w %1,%%ccr", ops
);
1990 return code
== EQ
? NE
: EQ
;
1992 /* count == 1 followed by bvc/bvs and
1993 count == 0 followed by bcc/bcs are also possible, but need
1994 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1997 cc_status
.flags
= CC_NOT_NEGATIVE
;
1999 output_asm_insn ("btst %0,%1", ops
);
2003 /* Output a bftst instruction for a zero_extract with ZXOP0, ZXOP1 and ZXOP2
2004 operands. CODE is the code of the comparison, and we return the code to
2005 be actually used in the jump. */
2008 m68k_output_bftst (rtx zxop0
, rtx zxop1
, rtx zxop2
, rtx_code code
)
2010 if (zxop1
== const1_rtx
&& GET_CODE (zxop2
) == CONST_INT
)
2012 int width
= GET_CODE (zxop0
) == REG
? 31 : 7;
2013 /* Pass 1000 as SIGNPOS argument so that btst will
2014 not think we are testing the sign bit for an `and'
2015 and assume that nonzero implies a negative result. */
2016 return m68k_output_btst (GEN_INT (width
- INTVAL (zxop2
)), zxop0
, code
, 1000);
2018 rtx ops
[3] = { zxop0
, zxop1
, zxop2
};
2019 output_asm_insn ("bftst %0{%b2:%b1}", ops
);
2023 /* Return true if X is a legitimate base register. STRICT_P says
2024 whether we need strict checking. */
2027 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
2029 /* Allow SUBREG everywhere we allow REG. This results in better code. */
2030 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2035 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
2036 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
2039 /* Return true if X is a legitimate index register. STRICT_P says
2040 whether we need strict checking. */
2043 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
2045 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2050 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
2051 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
2054 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
2055 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
2056 ADDRESS if so. STRICT_P says whether we need strict checking. */
2059 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
2063 /* Check for a scale factor. */
2065 if ((TARGET_68020
|| TARGET_COLDFIRE
)
2066 && GET_CODE (x
) == MULT
2067 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2068 && (INTVAL (XEXP (x
, 1)) == 2
2069 || INTVAL (XEXP (x
, 1)) == 4
2070 || (INTVAL (XEXP (x
, 1)) == 8
2071 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
2073 scale
= INTVAL (XEXP (x
, 1));
2077 /* Check for a word extension. */
2078 if (!TARGET_COLDFIRE
2079 && GET_CODE (x
) == SIGN_EXTEND
2080 && GET_MODE (XEXP (x
, 0)) == HImode
)
2083 if (m68k_legitimate_index_reg_p (x
, strict_p
))
2085 address
->scale
= scale
;
2093 /* Return true if X is an illegitimate symbolic constant. */
2096 m68k_illegitimate_symbolic_constant_p (rtx x
)
2100 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
2102 split_const (x
, &base
, &offset
);
2103 if (GET_CODE (base
) == SYMBOL_REF
2104 && !offset_within_block_p (base
, INTVAL (offset
)))
2107 return m68k_tls_reference_p (x
, false);
2110 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2113 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2115 return m68k_illegitimate_symbolic_constant_p (x
);
2118 /* Return true if X is a legitimate constant address that can reach
2119 bytes in the range [X, X + REACH). STRICT_P says whether we need
2123 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
2127 if (!CONSTANT_ADDRESS_P (x
))
2131 && !(strict_p
&& TARGET_PCREL
)
2132 && symbolic_operand (x
, VOIDmode
))
2135 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
2137 split_const (x
, &base
, &offset
);
2138 if (GET_CODE (base
) == SYMBOL_REF
2139 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
2143 return !m68k_tls_reference_p (x
, false);
2146 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
2147 labels will become jump tables. */
2150 m68k_jump_table_ref_p (rtx x
)
2152 if (GET_CODE (x
) != LABEL_REF
)
2155 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
2156 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
2159 insn
= next_nonnote_insn (insn
);
2160 return insn
&& JUMP_TABLE_DATA_P (insn
);
2163 /* Return true if X is a legitimate address for values of mode MODE.
2164 STRICT_P says whether strict checking is needed. If the address
2165 is valid, describe its components in *ADDRESS. */
2168 m68k_decompose_address (machine_mode mode
, rtx x
,
2169 bool strict_p
, struct m68k_address
*address
)
2173 memset (address
, 0, sizeof (*address
));
2175 if (mode
== BLKmode
)
2178 reach
= GET_MODE_SIZE (mode
);
2180 /* Check for (An) (mode 2). */
2181 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2187 /* Check for -(An) and (An)+ (modes 3 and 4). */
2188 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2189 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2191 address
->code
= GET_CODE (x
);
2192 address
->base
= XEXP (x
, 0);
2196 /* Check for (d16,An) (mode 5). */
2197 if (GET_CODE (x
) == PLUS
2198 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2199 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2200 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2202 address
->base
= XEXP (x
, 0);
2203 address
->offset
= XEXP (x
, 1);
2207 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2208 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2210 if (GET_CODE (x
) == PLUS
2211 && XEXP (x
, 0) == pic_offset_table_rtx
)
2213 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2214 they are invalid in this context. */
2215 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2217 address
->base
= XEXP (x
, 0);
2218 address
->offset
= XEXP (x
, 1);
2223 /* The ColdFire FPU only accepts addressing modes 2-5. */
2224 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2227 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2228 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2229 All these modes are variations of mode 7. */
2230 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2232 address
->offset
= x
;
2236 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2239 ??? do_tablejump creates these addresses before placing the target
2240 label, so we have to assume that unplaced labels are jump table
2241 references. It seems unlikely that we would ever generate indexed
2242 accesses to unplaced labels in other cases. */
2243 if (GET_CODE (x
) == PLUS
2244 && m68k_jump_table_ref_p (XEXP (x
, 1))
2245 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2247 address
->offset
= XEXP (x
, 1);
2251 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2252 (bd,An,Xn.SIZE*SCALE) addresses. */
2256 /* Check for a nonzero base displacement. */
2257 if (GET_CODE (x
) == PLUS
2258 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2260 address
->offset
= XEXP (x
, 1);
2264 /* Check for a suppressed index register. */
2265 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2271 /* Check for a suppressed base register. Do not allow this case
2272 for non-symbolic offsets as it effectively gives gcc freedom
2273 to treat data registers as base registers, which can generate
2276 && symbolic_operand (address
->offset
, VOIDmode
)
2277 && m68k_decompose_index (x
, strict_p
, address
))
2282 /* Check for a nonzero base displacement. */
2283 if (GET_CODE (x
) == PLUS
2284 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2285 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2287 address
->offset
= XEXP (x
, 1);
2292 /* We now expect the sum of a base and an index. */
2293 if (GET_CODE (x
) == PLUS
)
2295 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2296 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2298 address
->base
= XEXP (x
, 0);
2302 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2303 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2305 address
->base
= XEXP (x
, 1);
2312 /* Return true if X is a legitimate address for values of mode MODE.
2313 STRICT_P says whether strict checking is needed. */
2316 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2318 struct m68k_address address
;
2320 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2323 /* Return true if X is a memory, describing its address in ADDRESS if so.
2324 Apply strict checking if called during or after reload. */
2327 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2330 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2331 reload_in_progress
|| reload_completed
,
2335 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2338 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2340 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2343 /* Return true if X matches the 'Q' constraint. It must be a memory
2344 with a base address and no constant offset or index. */
2347 m68k_matches_q_p (rtx x
)
2349 struct m68k_address address
;
2351 return (m68k_legitimate_mem_p (x
, &address
)
2352 && address
.code
== UNKNOWN
2358 /* Return true if X matches the 'U' constraint. It must be a base address
2359 with a constant offset and no index. */
2362 m68k_matches_u_p (rtx x
)
2364 struct m68k_address address
;
2366 return (m68k_legitimate_mem_p (x
, &address
)
2367 && address
.code
== UNKNOWN
2373 /* Return GOT pointer. */
2378 if (pic_offset_table_rtx
== NULL_RTX
)
2379 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2381 crtl
->uses_pic_offset_table
= 1;
2383 return pic_offset_table_rtx
;
2386 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2388 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2389 RELOC_TLSIE
, RELOC_TLSLE
};
2391 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2393 /* Wrap symbol X into unspec representing relocation RELOC.
2394 BASE_REG - register that should be added to the result.
2395 TEMP_REG - if non-null, temporary register. */
2398 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2402 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2404 if (TARGET_COLDFIRE
&& use_x_p
)
2405 /* When compiling with -mx{got, tls} switch the code will look like this:
2407 move.l <X>@<RELOC>,<TEMP_REG>
2408 add.l <BASE_REG>,<TEMP_REG> */
2410 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2411 to put @RELOC after reference. */
2412 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2414 x
= gen_rtx_CONST (Pmode
, x
);
2416 if (temp_reg
== NULL
)
2418 gcc_assert (can_create_pseudo_p ());
2419 temp_reg
= gen_reg_rtx (Pmode
);
2422 emit_move_insn (temp_reg
, x
);
2423 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2428 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2430 x
= gen_rtx_CONST (Pmode
, x
);
2432 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2438 /* Helper for m68k_unwrap_symbol.
2439 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2440 sets *RELOC_PTR to relocation type for the symbol. */
2443 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2444 enum m68k_reloc
*reloc_ptr
)
2446 if (GET_CODE (orig
) == CONST
)
2449 enum m68k_reloc dummy
;
2453 if (reloc_ptr
== NULL
)
2456 /* Handle an addend. */
2457 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2458 && CONST_INT_P (XEXP (x
, 1)))
2461 if (GET_CODE (x
) == UNSPEC
)
2463 switch (XINT (x
, 1))
2465 case UNSPEC_RELOC16
:
2466 orig
= XVECEXP (x
, 0, 0);
2467 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2470 case UNSPEC_RELOC32
:
2471 if (unwrap_reloc32_p
)
2473 orig
= XVECEXP (x
, 0, 0);
2474 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2487 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2488 UNSPEC_RELOC32 wrappers. */
2491 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2493 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2496 /* Adjust decorated address operand before outputing assembler for it. */
2499 m68k_adjust_decorated_operand (rtx op
)
2501 /* Combine and, possibly, other optimizations may do good job
2503 (const (unspec [(symbol)]))
2505 (const (plus (unspec [(symbol)])
2507 The problem with this is emitting @TLS or @GOT decorations.
2508 The decoration is emitted when processing (unspec), so the
2509 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2511 It seems that the easiest solution to this is to convert such
2513 (const (unspec [(plus (symbol)
2515 Note, that the top level of operand remains intact, so we don't have
2516 to patch up anything outside of the operand. */
2518 subrtx_var_iterator::array_type array
;
2519 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2522 if (m68k_unwrap_symbol (x
, true) != x
)
2526 gcc_assert (GET_CODE (x
) == CONST
);
2529 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2534 unspec
= XEXP (plus
, 0);
2535 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2536 addend
= XEXP (plus
, 1);
2537 gcc_assert (CONST_INT_P (addend
));
2539 /* We now have all the pieces, rearrange them. */
2541 /* Move symbol to plus. */
2542 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2544 /* Move plus inside unspec. */
2545 XVECEXP (unspec
, 0, 0) = plus
;
2547 /* Move unspec to top level of const. */
2548 XEXP (x
, 0) = unspec
;
2550 iter
.skip_subrtxes ();
2555 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2556 If REG is non-null, use it; generate new pseudo otherwise. */
2559 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2563 if (reg
== NULL_RTX
)
2565 gcc_assert (can_create_pseudo_p ());
2566 reg
= gen_reg_rtx (Pmode
);
2569 insn
= emit_move_insn (reg
, x
);
2570 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2572 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2577 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2581 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2583 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2585 x
= gen_rtx_MEM (Pmode
, x
);
2586 MEM_READONLY_P (x
) = 1;
2591 /* Legitimize PIC addresses. If the address is already
2592 position-independent, we return ORIG. Newly generated
2593 position-independent addresses go to REG. If we need more
2594 than one register, we lose.
2596 An address is legitimized by making an indirect reference
2597 through the Global Offset Table with the name of the symbol
2600 The assembler and linker are responsible for placing the
2601 address of the symbol in the GOT. The function prologue
2602 is responsible for initializing a5 to the starting address
2605 The assembler is also responsible for translating a symbol name
2606 into a constant displacement from the start of the GOT.
2608 A quick example may make things a little clearer:
2610 When not generating PIC code to store the value 12345 into _foo
2611 we would generate the following code:
2615 When generating PIC two transformations are made. First, the compiler
2616 loads the address of foo into a register. So the first transformation makes:
2621 The code in movsi will intercept the lea instruction and call this
2622 routine which will transform the instructions into:
2624 movel a5@(_foo:w), a0
2628 That (in a nutshell) is how *all* symbol and label references are
2632 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2637 /* First handle a simple SYMBOL_REF or LABEL_REF */
2638 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2642 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2643 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2645 else if (GET_CODE (orig
) == CONST
)
2649 /* Make sure this has not already been legitimized. */
2650 if (m68k_unwrap_symbol (orig
, true) != orig
)
2655 /* legitimize both operands of the PLUS */
2656 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2658 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2659 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2660 base
== reg
? 0 : reg
);
2662 if (GET_CODE (orig
) == CONST_INT
)
2663 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2665 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2671 /* The __tls_get_addr symbol. */
2672 static GTY(()) rtx m68k_tls_get_addr
;
2674 /* Return SYMBOL_REF for __tls_get_addr. */
2677 m68k_get_tls_get_addr (void)
2679 if (m68k_tls_get_addr
== NULL_RTX
)
2680 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2682 return m68k_tls_get_addr
;
2685 /* Return libcall result in A0 instead of usual D0. */
2686 static bool m68k_libcall_value_in_a0_p
= false;
2688 /* Emit instruction sequence that calls __tls_get_addr. X is
2689 the TLS symbol we are referencing and RELOC is the symbol type to use
2690 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2691 emitted. A pseudo register with result of __tls_get_addr call is
2695 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2701 /* Emit the call sequence. */
2704 /* FIXME: Unfortunately, emit_library_call_value does not
2705 consider (plus (%a5) (const (unspec))) to be a good enough
2706 operand for push, so it forces it into a register. The bad
2707 thing about this is that combiner, due to copy propagation and other
2708 optimizations, sometimes cannot later fix this. As a consequence,
2709 additional register may be allocated resulting in a spill.
2710 For reference, see args processing loops in
2711 calls.c:emit_library_call_value_1.
2712 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2713 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2715 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2716 is the simpliest way of generating a call. The difference between
2717 __tls_get_addr() and libcall is that the result is returned in D0
2718 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2719 which temporarily switches returning the result to A0. */
2721 m68k_libcall_value_in_a0_p
= true;
2722 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2724 m68k_libcall_value_in_a0_p
= false;
2726 insns
= get_insns ();
2729 gcc_assert (can_create_pseudo_p ());
2730 dest
= gen_reg_rtx (Pmode
);
2731 emit_libcall_block (insns
, dest
, a0
, eqv
);
2736 /* The __tls_get_addr symbol. */
2737 static GTY(()) rtx m68k_read_tp
;
2739 /* Return SYMBOL_REF for __m68k_read_tp. */
2742 m68k_get_m68k_read_tp (void)
2744 if (m68k_read_tp
== NULL_RTX
)
2745 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2747 return m68k_read_tp
;
2750 /* Emit instruction sequence that calls __m68k_read_tp.
2751 A pseudo register with result of __m68k_read_tp call is returned. */
2754 m68k_call_m68k_read_tp (void)
2763 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2764 is the simpliest way of generating a call. The difference between
2765 __m68k_read_tp() and libcall is that the result is returned in D0
2766 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2767 which temporarily switches returning the result to A0. */
2769 /* Emit the call sequence. */
2770 m68k_libcall_value_in_a0_p
= true;
2771 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2773 m68k_libcall_value_in_a0_p
= false;
2774 insns
= get_insns ();
2777 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2778 share the m68k_read_tp result with other IE/LE model accesses. */
2779 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2781 gcc_assert (can_create_pseudo_p ());
2782 dest
= gen_reg_rtx (Pmode
);
2783 emit_libcall_block (insns
, dest
, a0
, eqv
);
2788 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2789 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2793 m68k_legitimize_tls_address (rtx orig
)
2795 switch (SYMBOL_REF_TLS_MODEL (orig
))
2797 case TLS_MODEL_GLOBAL_DYNAMIC
:
2798 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2801 case TLS_MODEL_LOCAL_DYNAMIC
:
2807 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2808 share the LDM result with other LD model accesses. */
2809 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2812 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2814 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2816 if (can_create_pseudo_p ())
2817 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2823 case TLS_MODEL_INITIAL_EXEC
:
2828 a0
= m68k_call_m68k_read_tp ();
2830 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2831 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2833 if (can_create_pseudo_p ())
2834 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2840 case TLS_MODEL_LOCAL_EXEC
:
2845 a0
= m68k_call_m68k_read_tp ();
2847 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2849 if (can_create_pseudo_p ())
2850 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2863 /* Return true if X is a TLS symbol. */
2866 m68k_tls_symbol_p (rtx x
)
2868 if (!TARGET_HAVE_TLS
)
2871 if (GET_CODE (x
) != SYMBOL_REF
)
2874 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2877 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2878 though illegitimate one.
2879 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2882 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2884 if (!TARGET_HAVE_TLS
)
2889 subrtx_var_iterator::array_type array
;
2890 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2894 /* Note: this is not the same as m68k_tls_symbol_p. */
2895 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2898 /* Don't recurse into legitimate TLS references. */
2899 if (m68k_tls_reference_p (x
, true))
2900 iter
.skip_subrtxes ();
2906 enum m68k_reloc reloc
= RELOC_GOT
;
2908 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2909 && TLS_RELOC_P (reloc
));
2915 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2917 /* Return the type of move that should be used for integer I. */
2920 m68k_const_method (HOST_WIDE_INT i
)
2927 /* The ColdFire doesn't have byte or word operations. */
2928 /* FIXME: This may not be useful for the m68060 either. */
2929 if (!TARGET_COLDFIRE
)
2931 /* if -256 < N < 256 but N is not in range for a moveq
2932 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2933 if (USE_MOVQ (i
^ 0xff))
2935 /* Likewise, try with not.w */
2936 if (USE_MOVQ (i
^ 0xffff))
2938 /* This is the only value where neg.w is useful */
2943 /* Try also with swap. */
2945 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2950 /* Try using MVZ/MVS with an immediate value to load constants. */
2951 if (i
>= 0 && i
<= 65535)
2953 if (i
>= -32768 && i
<= 32767)
2957 /* Otherwise, use move.l */
2961 /* Return the cost of moving constant I into a data register. */
2964 const_int_cost (HOST_WIDE_INT i
)
2966 switch (m68k_const_method (i
))
2969 /* Constants between -128 and 127 are cheap due to moveq. */
2977 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2987 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2988 int opno ATTRIBUTE_UNUSED
,
2989 int *total
, bool speed ATTRIBUTE_UNUSED
)
2991 int code
= GET_CODE (x
);
2996 /* Constant zero is super cheap due to clr instruction. */
2997 if (x
== const0_rtx
)
3000 *total
= const_int_cost (INTVAL (x
));
3010 /* Make 0.0 cheaper than other floating constants to
3011 encourage creating tstsf and tstdf insns. */
3012 if ((GET_RTX_CLASS (outer_code
) == RTX_COMPARE
3013 || GET_RTX_CLASS (outer_code
) == RTX_COMM_COMPARE
)
3014 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
3020 /* These are vaguely right for a 68020. */
3021 /* The costs for long multiply have been adjusted to work properly
3022 in synth_mult on the 68020, relative to an average of the time
3023 for add and the time for shift, taking away a little more because
3024 sometimes move insns are needed. */
3025 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
3030 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
3031 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
3033 : TARGET_COLDFIRE ? 3 : 13)
3038 : TUNE_68000_10 ? 5 \
3039 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
3040 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
3042 : TARGET_COLDFIRE ? 2 : 8)
3045 (TARGET_CF_HWDIV ? 11 \
3046 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
3049 /* An lea costs about three times as much as a simple add. */
3051 && GET_CODE (XEXP (x
, 1)) == REG
3052 && GET_CODE (XEXP (x
, 0)) == MULT
3053 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3054 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3055 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
3056 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
3057 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
3059 /* lea an@(dx:l:i),am */
3060 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
3070 *total
= COSTS_N_INSNS(1);
3075 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3077 if (INTVAL (XEXP (x
, 1)) < 16)
3078 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
3080 /* We're using clrw + swap for these cases. */
3081 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
3084 *total
= COSTS_N_INSNS (10); /* Worst case. */
3087 /* A shift by a big integer takes an extra instruction. */
3088 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
3089 && (INTVAL (XEXP (x
, 1)) == 16))
3091 *total
= COSTS_N_INSNS (2); /* clrw;swap */
3094 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
3095 && !(INTVAL (XEXP (x
, 1)) > 0
3096 && INTVAL (XEXP (x
, 1)) <= 8))
3098 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
3104 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3105 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
3107 *total
= COSTS_N_INSNS (MULW_COST
);
3108 else if (mode
== QImode
|| mode
== HImode
)
3109 *total
= COSTS_N_INSNS (MULW_COST
);
3111 *total
= COSTS_N_INSNS (MULL_COST
);
3118 if (mode
== QImode
|| mode
== HImode
)
3119 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
3120 else if (TARGET_CF_HWDIV
)
3121 *total
= COSTS_N_INSNS (18);
3123 *total
= COSTS_N_INSNS (43); /* div.l */
3127 if (GET_RTX_CLASS (outer_code
) == RTX_COMPARE
3128 || GET_RTX_CLASS (outer_code
) == RTX_COMM_COMPARE
)
3137 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
3141 output_move_const_into_data_reg (rtx
*operands
)
3145 i
= INTVAL (operands
[1]);
3146 switch (m68k_const_method (i
))
3149 return "mvzw %1,%0";
3151 return "mvsw %1,%0";
3153 return "moveq %1,%0";
3156 operands
[1] = GEN_INT (i
^ 0xff);
3157 return "moveq %1,%0\n\tnot%.b %0";
3160 operands
[1] = GEN_INT (i
^ 0xffff);
3161 return "moveq %1,%0\n\tnot%.w %0";
3164 return "moveq #-128,%0\n\tneg%.w %0";
3169 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
3170 return "moveq %1,%0\n\tswap %0";
3173 return "move%.l %1,%0";
3179 /* Return true if I can be handled by ISA B's mov3q instruction. */
3182 valid_mov3q_const (HOST_WIDE_INT i
)
3184 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3187 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3188 I is the value of OPERANDS[1]. */
3191 output_move_simode_const (rtx
*operands
)
3197 src
= INTVAL (operands
[1]);
3199 && (DATA_REG_P (dest
) || MEM_P (dest
))
3200 /* clr insns on 68000 read before writing. */
3201 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3202 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3204 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3205 return "mov3q%.l %1,%0";
3206 else if (src
== 0 && ADDRESS_REG_P (dest
))
3207 return "sub%.l %0,%0";
3208 else if (DATA_REG_P (dest
))
3209 return output_move_const_into_data_reg (operands
);
3210 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3212 if (valid_mov3q_const (src
))
3213 return "mov3q%.l %1,%0";
3214 return "move%.w %1,%0";
3216 else if (MEM_P (dest
)
3217 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3218 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3219 && IN_RANGE (src
, -0x8000, 0x7fff))
3221 if (valid_mov3q_const (src
))
3222 return "mov3q%.l %1,%-";
3225 return "move%.l %1,%0";
3229 output_move_simode (rtx
*operands
)
3231 handle_flags_for_move (operands
);
3233 if (GET_CODE (operands
[1]) == CONST_INT
)
3234 return output_move_simode_const (operands
);
3235 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3236 || GET_CODE (operands
[1]) == CONST
)
3237 && push_operand (operands
[0], SImode
))
3239 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3240 || GET_CODE (operands
[1]) == CONST
)
3241 && ADDRESS_REG_P (operands
[0]))
3242 return "lea %a1,%0";
3243 return "move%.l %1,%0";
3247 output_move_himode (rtx
*operands
)
3249 if (GET_CODE (operands
[1]) == CONST_INT
)
3251 if (operands
[1] == const0_rtx
3252 && (DATA_REG_P (operands
[0])
3253 || GET_CODE (operands
[0]) == MEM
)
3254 /* clr insns on 68000 read before writing. */
3255 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3256 || !(GET_CODE (operands
[0]) == MEM
3257 && MEM_VOLATILE_P (operands
[0]))))
3259 else if (operands
[1] == const0_rtx
3260 && ADDRESS_REG_P (operands
[0]))
3261 return "sub%.l %0,%0";
3262 else if (DATA_REG_P (operands
[0])
3263 && INTVAL (operands
[1]) < 128
3264 && INTVAL (operands
[1]) >= -128)
3265 return "moveq %1,%0";
3266 else if (INTVAL (operands
[1]) < 0x8000
3267 && INTVAL (operands
[1]) >= -0x8000)
3268 return "move%.w %1,%0";
3270 else if (CONSTANT_P (operands
[1]))
3272 return "move%.w %1,%0";
3276 output_move_qimode (rtx
*operands
)
3278 handle_flags_for_move (operands
);
3280 /* 68k family always modifies the stack pointer by at least 2, even for
3281 byte pushes. The 5200 (ColdFire) does not do this. */
3283 /* This case is generated by pushqi1 pattern now. */
3284 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3285 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3286 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3287 && ! ADDRESS_REG_P (operands
[1])
3288 && ! TARGET_COLDFIRE
));
3290 /* clr and st insns on 68000 read before writing. */
3291 if (!ADDRESS_REG_P (operands
[0])
3292 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3293 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3295 if (operands
[1] == const0_rtx
)
3297 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3298 && GET_CODE (operands
[1]) == CONST_INT
3299 && (INTVAL (operands
[1]) & 255) == 255)
3305 if (GET_CODE (operands
[1]) == CONST_INT
3306 && DATA_REG_P (operands
[0])
3307 && INTVAL (operands
[1]) < 128
3308 && INTVAL (operands
[1]) >= -128)
3309 return "moveq %1,%0";
3310 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3311 return "sub%.l %0,%0";
3312 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3314 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3315 from address registers. */
3316 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3318 if (ADDRESS_REG_P (operands
[1]))
3320 return "move%.w %1,%0";
3322 return "move%.b %1,%0";
3326 output_move_stricthi (rtx
*operands
)
3328 if (operands
[1] == const0_rtx
3329 /* clr insns on 68000 read before writing. */
3330 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3331 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3333 return "move%.w %1,%0";
3337 output_move_strictqi (rtx
*operands
)
3339 if (operands
[1] == const0_rtx
3340 /* clr insns on 68000 read before writing. */
3341 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3342 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3344 return "move%.b %1,%0";
3347 /* Return the best assembler insn template
3348 for moving operands[1] into operands[0] as a fullword. */
3351 singlemove_string (rtx
*operands
)
3353 if (GET_CODE (operands
[1]) == CONST_INT
)
3354 return output_move_simode_const (operands
);
3355 return "move%.l %1,%0";
3359 /* Output assembler or rtl code to perform a doubleword move insn
3360 with operands OPERANDS.
3361 Pointers to 3 helper functions should be specified:
3362 HANDLE_REG_ADJUST to adjust a register by a small value,
3363 HANDLE_COMPADR to compute an address and
3364 HANDLE_MOVSI to move 4 bytes. */
3367 handle_move_double (rtx operands
[2],
3368 void (*handle_reg_adjust
) (rtx
, int),
3369 void (*handle_compadr
) (rtx
[2]),
3370 void (*handle_movsi
) (rtx
[2]))
3374 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3379 rtx addreg0
= 0, addreg1
= 0;
3380 int dest_overlapped_low
= 0;
3381 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3386 /* First classify both operands. */
3388 if (REG_P (operands
[0]))
3390 else if (offsettable_memref_p (operands
[0]))
3392 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3394 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3396 else if (GET_CODE (operands
[0]) == MEM
)
3401 if (REG_P (operands
[1]))
3403 else if (CONSTANT_P (operands
[1]))
3405 else if (offsettable_memref_p (operands
[1]))
3407 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3409 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3411 else if (GET_CODE (operands
[1]) == MEM
)
3416 /* Check for the cases that the operand constraints are not supposed
3417 to allow to happen. Generating code for these cases is
3419 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3421 /* If one operand is decrementing and one is incrementing
3422 decrement the former register explicitly
3423 and change that operand into ordinary indexing. */
3425 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3427 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3429 handle_reg_adjust (operands
[0], -size
);
3431 if (GET_MODE (operands
[1]) == XFmode
)
3432 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3433 else if (GET_MODE (operands
[0]) == DFmode
)
3434 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3436 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3439 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3441 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3443 handle_reg_adjust (operands
[1], -size
);
3445 if (GET_MODE (operands
[1]) == XFmode
)
3446 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3447 else if (GET_MODE (operands
[1]) == DFmode
)
3448 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3450 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3454 /* If an operand is an unoffsettable memory ref, find a register
3455 we can increment temporarily to make it refer to the second word. */
3457 if (optype0
== MEMOP
)
3458 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3460 if (optype1
== MEMOP
)
3461 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3463 /* Ok, we can do one word at a time.
3464 Normally we do the low-numbered word first,
3465 but if either operand is autodecrementing then we
3466 do the high-numbered word first.
3468 In either case, set up in LATEHALF the operands to use
3469 for the high-numbered word and in some cases alter the
3470 operands in OPERANDS to be suitable for the low-numbered word. */
3474 if (optype0
== REGOP
)
3476 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3477 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3479 else if (optype0
== OFFSOP
)
3481 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3482 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3486 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3487 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3490 if (optype1
== REGOP
)
3492 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3493 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3495 else if (optype1
== OFFSOP
)
3497 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3498 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3500 else if (optype1
== CNSTOP
)
3502 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3506 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3507 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3508 operands
[1] = GEN_INT (l
[0]);
3509 middlehalf
[1] = GEN_INT (l
[1]);
3510 latehalf
[1] = GEN_INT (l
[2]);
3514 /* No non-CONST_DOUBLE constant should ever appear
3516 gcc_assert (!CONSTANT_P (operands
[1]));
3521 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3522 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3526 /* size is not 12: */
3528 if (optype0
== REGOP
)
3529 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3530 else if (optype0
== OFFSOP
)
3531 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3533 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3535 if (optype1
== REGOP
)
3536 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3537 else if (optype1
== OFFSOP
)
3538 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3539 else if (optype1
== CNSTOP
)
3540 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3542 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3545 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3546 word first. We should use the adjusted operand 1 (which is N+4(REG))
3547 for the low word as well, to compensate for the first decrement of
3549 if (optype0
== PUSHOP
3550 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3551 operands
[1] = middlehalf
[1] = latehalf
[1];
3553 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3554 if the upper part of reg N does not appear in the MEM, arrange to
3555 emit the move late-half first. Otherwise, compute the MEM address
3556 into the upper part of N and use that as a pointer to the memory
3558 if (optype0
== REGOP
3559 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3561 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3563 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3564 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3566 /* If both halves of dest are used in the src memory address,
3567 compute the address into latehalf of dest.
3568 Note that this can't happen if the dest is two data regs. */
3570 xops
[0] = latehalf
[0];
3571 xops
[1] = XEXP (operands
[1], 0);
3573 handle_compadr (xops
);
3574 if (GET_MODE (operands
[1]) == XFmode
)
3576 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3577 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3578 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3582 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3583 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3587 && reg_overlap_mentioned_p (middlehalf
[0],
3588 XEXP (operands
[1], 0)))
3590 /* Check for two regs used by both source and dest.
3591 Note that this can't happen if the dest is all data regs.
3592 It can happen if the dest is d6, d7, a0.
3593 But in that case, latehalf is an addr reg, so
3594 the code at compadr does ok. */
3596 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3597 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3600 /* JRV says this can't happen: */
3601 gcc_assert (!addreg0
&& !addreg1
);
3603 /* Only the middle reg conflicts; simply put it last. */
3604 handle_movsi (operands
);
3605 handle_movsi (latehalf
);
3606 handle_movsi (middlehalf
);
3610 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3611 /* If the low half of dest is mentioned in the source memory
3612 address, the arrange to emit the move late half first. */
3613 dest_overlapped_low
= 1;
3616 /* If one or both operands autodecrementing,
3617 do the two words, high-numbered first. */
3619 /* Likewise, the first move would clobber the source of the second one,
3620 do them in the other order. This happens only for registers;
3621 such overlap can't happen in memory unless the user explicitly
3622 sets it up, and that is an undefined circumstance. */
3624 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3625 || (optype0
== REGOP
&& optype1
== REGOP
3626 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3627 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3628 || dest_overlapped_low
)
3630 /* Make any unoffsettable addresses point at high-numbered word. */
3632 handle_reg_adjust (addreg0
, size
- 4);
3634 handle_reg_adjust (addreg1
, size
- 4);
3637 handle_movsi (latehalf
);
3639 /* Undo the adds we just did. */
3641 handle_reg_adjust (addreg0
, -4);
3643 handle_reg_adjust (addreg1
, -4);
3647 handle_movsi (middlehalf
);
3650 handle_reg_adjust (addreg0
, -4);
3652 handle_reg_adjust (addreg1
, -4);
3655 /* Do low-numbered word. */
3657 handle_movsi (operands
);
3661 /* Normal case: do the two words, low-numbered first. */
3663 handle_movsi (operands
);
3665 /* Do the middle one of the three words for long double */
3669 handle_reg_adjust (addreg0
, 4);
3671 handle_reg_adjust (addreg1
, 4);
3673 handle_movsi (middlehalf
);
3676 /* Make any unoffsettable addresses point at high-numbered word. */
3678 handle_reg_adjust (addreg0
, 4);
3680 handle_reg_adjust (addreg1
, 4);
3683 handle_movsi (latehalf
);
3685 /* Undo the adds we just did. */
3687 handle_reg_adjust (addreg0
, -(size
- 4));
3689 handle_reg_adjust (addreg1
, -(size
- 4));
3694 /* Output assembler code to adjust REG by N. */
3696 output_reg_adjust (rtx reg
, int n
)
3700 gcc_assert (GET_MODE (reg
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3705 s
= "add%.l #12,%0";
3709 s
= "addq%.l #8,%0";
3713 s
= "addq%.l #4,%0";
3717 s
= "sub%.l #12,%0";
3721 s
= "subq%.l #8,%0";
3725 s
= "subq%.l #4,%0";
3733 output_asm_insn (s
, ®
);
3736 /* Emit rtl code to adjust REG by N. */
3738 emit_reg_adjust (rtx reg1
, int n
)
3742 gcc_assert (GET_MODE (reg1
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3744 reg1
= copy_rtx (reg1
);
3745 reg2
= copy_rtx (reg1
);
3748 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3750 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3755 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3757 output_compadr (rtx operands
[2])
3759 output_asm_insn ("lea %a1,%0", operands
);
3762 /* Output the best assembler insn for moving operands[1] into operands[0]
3765 output_movsi (rtx operands
[2])
3767 output_asm_insn (singlemove_string (operands
), operands
);
3770 /* Copy OP and change its mode to MODE. */
3772 copy_operand (rtx op
, machine_mode mode
)
3774 /* ??? This looks really ugly. There must be a better way
3775 to change a mode on the operand. */
3776 if (GET_MODE (op
) != VOIDmode
)
3779 op
= gen_rtx_REG (mode
, REGNO (op
));
3783 PUT_MODE (op
, mode
);
3790 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3792 emit_movsi (rtx operands
[2])
3794 operands
[0] = copy_operand (operands
[0], SImode
);
3795 operands
[1] = copy_operand (operands
[1], SImode
);
3797 emit_insn (gen_movsi (operands
[0], operands
[1]));
3800 /* Output assembler code to perform a doubleword move insn
3801 with operands OPERANDS. */
3803 output_move_double (rtx
*operands
)
3805 handle_move_double (operands
,
3806 output_reg_adjust
, output_compadr
, output_movsi
);
3811 /* Output rtl code to perform a doubleword move insn
3812 with operands OPERANDS. */
3814 m68k_emit_move_double (rtx operands
[2])
3816 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3819 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3820 new rtx with the correct mode. */
3823 force_mode (machine_mode mode
, rtx orig
)
3825 if (mode
== GET_MODE (orig
))
3828 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3831 return gen_rtx_REG (mode
, REGNO (orig
));
3835 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3837 return reg_renumber
&& FP_REG_P (op
);
3840 /* Emit insns to move operands[1] into operands[0].
3842 Return 1 if we have written out everything that needs to be done to
3843 do the move. Otherwise, return 0 and the caller will emit the move
3846 Note SCRATCH_REG may not be in the proper mode depending on how it
3847 will be used. This routine is responsible for creating a new copy
3848 of SCRATCH_REG in the proper mode. */
3851 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3853 register rtx operand0
= operands
[0];
3854 register rtx operand1
= operands
[1];
3858 && reload_in_progress
&& GET_CODE (operand0
) == REG
3859 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3860 operand0
= reg_equiv_mem (REGNO (operand0
));
3861 else if (scratch_reg
3862 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3863 && GET_CODE (SUBREG_REG (operand0
)) == REG
3864 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3866 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3867 the code which tracks sets/uses for delete_output_reload. */
3868 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3869 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3870 SUBREG_BYTE (operand0
));
3871 operand0
= alter_subreg (&temp
, true);
3875 && reload_in_progress
&& GET_CODE (operand1
) == REG
3876 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3877 operand1
= reg_equiv_mem (REGNO (operand1
));
3878 else if (scratch_reg
3879 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3880 && GET_CODE (SUBREG_REG (operand1
)) == REG
3881 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3883 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3884 the code which tracks sets/uses for delete_output_reload. */
3885 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3886 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3887 SUBREG_BYTE (operand1
));
3888 operand1
= alter_subreg (&temp
, true);
3891 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3892 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3893 != XEXP (operand0
, 0)))
3894 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3895 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3896 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3897 != XEXP (operand1
, 0)))
3898 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3900 /* Handle secondary reloads for loads/stores of FP registers where
3901 the address is symbolic by using the scratch register */
3902 if (fp_reg_operand (operand0
, mode
)
3903 && ((GET_CODE (operand1
) == MEM
3904 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3905 || ((GET_CODE (operand1
) == SUBREG
3906 && GET_CODE (XEXP (operand1
, 0)) == MEM
3907 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3910 if (GET_CODE (operand1
) == SUBREG
)
3911 operand1
= XEXP (operand1
, 0);
3913 /* SCRATCH_REG will hold an address. We want
3914 it in SImode regardless of what mode it was originally given
3916 scratch_reg
= force_mode (SImode
, scratch_reg
);
3918 /* D might not fit in 14 bits either; for such cases load D into
3920 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3922 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3923 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3925 XEXP (XEXP (operand1
, 0), 0),
3929 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3930 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3933 else if (fp_reg_operand (operand1
, mode
)
3934 && ((GET_CODE (operand0
) == MEM
3935 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3936 || ((GET_CODE (operand0
) == SUBREG
)
3937 && GET_CODE (XEXP (operand0
, 0)) == MEM
3938 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3941 if (GET_CODE (operand0
) == SUBREG
)
3942 operand0
= XEXP (operand0
, 0);
3944 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3945 it in SIMODE regardless of what mode it was originally given
3947 scratch_reg
= force_mode (SImode
, scratch_reg
);
3949 /* D might not fit in 14 bits either; for such cases load D into
3951 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3953 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3954 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3957 XEXP (XEXP (operand0
, 0),
3962 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3963 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3966 /* Handle secondary reloads for loads of FP registers from constant
3967 expressions by forcing the constant into memory.
3969 use scratch_reg to hold the address of the memory location.
3971 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3972 NO_REGS when presented with a const_int and an register class
3973 containing only FP registers. Doing so unfortunately creates
3974 more problems than it solves. Fix this for 2.5. */
3975 else if (fp_reg_operand (operand0
, mode
)
3976 && CONSTANT_P (operand1
)
3981 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3982 it in SIMODE regardless of what mode it was originally given
3984 scratch_reg
= force_mode (SImode
, scratch_reg
);
3986 /* Force the constant into memory and put the address of the
3987 memory location into scratch_reg. */
3988 xoperands
[0] = scratch_reg
;
3989 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3990 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3992 /* Now load the destination register. */
3993 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3997 /* Now have insn-emit do whatever it normally does. */
4001 /* Split one or more DImode RTL references into pairs of SImode
4002 references. The RTL can be REG, offsettable MEM, integer constant, or
4003 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
4004 split and "num" is its length. lo_half and hi_half are output arrays
4005 that parallel "operands". */
4008 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
4012 rtx op
= operands
[num
];
4014 /* simplify_subreg refuses to split volatile memory addresses,
4015 but we still have to handle it. */
4016 if (GET_CODE (op
) == MEM
)
4018 lo_half
[num
] = adjust_address (op
, SImode
, 4);
4019 hi_half
[num
] = adjust_address (op
, SImode
, 0);
4023 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
4024 GET_MODE (op
) == VOIDmode
4025 ? DImode
: GET_MODE (op
), 4);
4026 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
4027 GET_MODE (op
) == VOIDmode
4028 ? DImode
: GET_MODE (op
), 0);
4033 /* Split X into a base and a constant offset, storing them in *BASE
4034 and *OFFSET respectively. */
4037 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
4040 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4042 *offset
+= INTVAL (XEXP (x
, 1));
4048 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
4049 instruction. STORE_P says whether the move is a load or store.
4051 If the instruction uses post-increment or pre-decrement addressing,
4052 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
4053 adjustment. This adjustment will be made by the first element of
4054 PARALLEL, with the loads or stores starting at element 1. If the
4055 instruction does not use post-increment or pre-decrement addressing,
4056 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
4057 start at element 0. */
4060 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
4061 HOST_WIDE_INT automod_offset
, bool store_p
)
4063 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
4064 HOST_WIDE_INT offset
, mem_offset
;
4066 enum reg_class rclass
;
4068 len
= XVECLEN (pattern
, 0);
4069 first
= (automod_base
!= NULL
);
4073 /* Stores must be pre-decrement and loads must be post-increment. */
4074 if (store_p
!= (automod_offset
< 0))
4077 /* Work out the base and offset for lowest memory location. */
4078 base
= automod_base
;
4079 offset
= (automod_offset
< 0 ? automod_offset
: 0);
4083 /* Allow any valid base and offset in the first access. */
4090 for (i
= first
; i
< len
; i
++)
4092 /* We need a plain SET. */
4093 set
= XVECEXP (pattern
, 0, i
);
4094 if (GET_CODE (set
) != SET
)
4097 /* Check that we have a memory location... */
4098 mem
= XEXP (set
, !store_p
);
4099 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
4102 /* ...with the right address. */
4105 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
4106 /* The ColdFire instruction only allows (An) and (d16,An) modes.
4107 There are no mode restrictions for 680x0 besides the
4108 automodification rules enforced above. */
4110 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
4115 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
4116 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
4120 /* Check that we have a register of the required mode and class. */
4121 reg
= XEXP (set
, store_p
);
4123 || !HARD_REGISTER_P (reg
)
4124 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
4129 /* The register must belong to RCLASS and have a higher number
4130 than the register in the previous SET. */
4131 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
4132 || REGNO (last_reg
) >= REGNO (reg
))
4137 /* Work out which register class we need. */
4138 if (INT_REGNO_P (REGNO (reg
)))
4139 rclass
= GENERAL_REGS
;
4140 else if (FP_REGNO_P (REGNO (reg
)))
4147 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
4150 /* If we have an automodification, check whether the final offset is OK. */
4151 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
4154 /* Reject unprofitable cases. */
4155 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
4161 /* Return the assembly code template for a movem or fmovem instruction
4162 whose pattern is given by PATTERN. Store the template's operands
4165 If the instruction uses post-increment or pre-decrement addressing,
4166 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
4167 is true if this is a store instruction. */
4170 m68k_output_movem (rtx
*operands
, rtx pattern
,
4171 HOST_WIDE_INT automod_offset
, bool store_p
)
4176 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
4178 first
= (automod_offset
!= 0);
4179 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4181 /* When using movem with pre-decrement addressing, register X + D0_REG
4182 is controlled by bit 15 - X. For all other addressing modes,
4183 register X + D0_REG is controlled by bit X. Confusingly, the
4184 register mask for fmovem is in the opposite order to that for
4188 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4189 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4190 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4191 if (automod_offset
< 0)
4193 if (FP_REGNO_P (regno
))
4194 mask
|= 1 << (regno
- FP0_REG
);
4196 mask
|= 1 << (15 - (regno
- D0_REG
));
4200 if (FP_REGNO_P (regno
))
4201 mask
|= 1 << (7 - (regno
- FP0_REG
));
4203 mask
|= 1 << (regno
- D0_REG
);
4208 if (automod_offset
== 0)
4209 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4210 else if (automod_offset
< 0)
4211 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4213 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4214 operands
[1] = GEN_INT (mask
);
4215 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4218 return "fmovem %1,%a0";
4220 return "fmovem %a0,%1";
4225 return "movem%.l %1,%a0";
4227 return "movem%.l %a0,%1";
4231 /* Return a REG that occurs in ADDR with coefficient 1.
4232 ADDR can be effectively incremented by incrementing REG. */
4235 find_addr_reg (rtx addr
)
4237 while (GET_CODE (addr
) == PLUS
)
4239 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4240 addr
= XEXP (addr
, 0);
4241 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4242 addr
= XEXP (addr
, 1);
4243 else if (CONSTANT_P (XEXP (addr
, 0)))
4244 addr
= XEXP (addr
, 1);
4245 else if (CONSTANT_P (XEXP (addr
, 1)))
4246 addr
= XEXP (addr
, 0);
4250 gcc_assert (GET_CODE (addr
) == REG
);
4254 /* Output assembler code to perform a 32-bit 3-operand add. */
4257 output_addsi3 (rtx
*operands
)
4259 if (! operands_match_p (operands
[0], operands
[1]))
4261 if (!ADDRESS_REG_P (operands
[1]))
4263 rtx tmp
= operands
[1];
4265 operands
[1] = operands
[2];
4269 /* These insns can result from reloads to access
4270 stack slots over 64k from the frame pointer. */
4271 if (GET_CODE (operands
[2]) == CONST_INT
4272 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4273 return "move%.l %2,%0\n\tadd%.l %1,%0";
4274 if (GET_CODE (operands
[2]) == REG
)
4275 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4276 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4278 if (GET_CODE (operands
[2]) == CONST_INT
)
4280 if (INTVAL (operands
[2]) > 0
4281 && INTVAL (operands
[2]) <= 8)
4282 return "addq%.l %2,%0";
4283 if (INTVAL (operands
[2]) < 0
4284 && INTVAL (operands
[2]) >= -8)
4286 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4287 return "subq%.l %2,%0";
4289 /* On the CPU32 it is faster to use two addql instructions to
4290 add a small integer (8 < N <= 16) to a register.
4291 Likewise for subql. */
4292 if (TUNE_CPU32
&& REG_P (operands
[0]))
4294 if (INTVAL (operands
[2]) > 8
4295 && INTVAL (operands
[2]) <= 16)
4297 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4298 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4300 if (INTVAL (operands
[2]) < -8
4301 && INTVAL (operands
[2]) >= -16)
4303 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4304 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4307 if (ADDRESS_REG_P (operands
[0])
4308 && INTVAL (operands
[2]) >= -0x8000
4309 && INTVAL (operands
[2]) < 0x8000)
4312 return "add%.w %2,%0";
4314 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4317 return "add%.l %2,%0";
4320 /* Emit a comparison between OP0 and OP1. Return true iff the comparison
4321 was reversed. SC1 is an SImode scratch reg, and SC2 a DImode scratch reg,
4322 as needed. CODE is the code of the comparison, we return it unchanged or
4323 swapped, as necessary. */
4325 m68k_output_compare_di (rtx op0
, rtx op1
, rtx sc1
, rtx sc2
, rtx_insn
*insn
,
4333 if (op1
== const0_rtx
)
4335 if (!REG_P (op0
) || ADDRESS_REG_P (op0
))
4341 output_move_double (xoperands
);
4342 output_asm_insn ("neg%.l %R0\n\tnegx%.l %0", xoperands
);
4343 return swap_condition (code
);
4345 if (find_reg_note (insn
, REG_DEAD
, op0
))
4347 output_asm_insn ("neg%.l %R0\n\tnegx%.l %0", ops
);
4348 return swap_condition (code
);
4352 /* 'sub' clears %1, and also clears the X cc bit.
4353 'tst' sets the Z cc bit according to the low part of the DImode
4355 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high
4357 output_asm_insn ("sub%.l %2,%2\n\ttst%.l %R0\n\tsubx%.l %2,%0", ops
);
4362 if (rtx_equal_p (sc2
, op0
))
4364 output_asm_insn ("sub%.l %R1,%R3\n\tsubx%.l %1,%3", ops
);
4369 output_asm_insn ("sub%.l %R0,%R3\n\tsubx%.l %0,%3", ops
);
4370 return swap_condition (code
);
4375 remember_compare_flags (rtx op0
, rtx op1
)
4377 if (side_effects_p (op0
) || side_effects_p (op1
))
4381 flags_compare_op0
= op0
;
4382 flags_compare_op1
= op1
;
4383 flags_operand1
= flags_operand2
= NULL_RTX
;
4384 flags_valid
= FLAGS_VALID_SET
;
4388 /* Emit a comparison between OP0 and OP1. CODE is the code of the
4389 comparison. It is returned, potentially modified if necessary. */
4391 m68k_output_compare_si (rtx op0
, rtx op1
, rtx_code code
)
4393 rtx_code tmp
= m68k_find_flags_value (op0
, op1
, code
);
4397 remember_compare_flags (op0
, op1
);
4402 if (op1
== const0_rtx
&& (TARGET_68020
|| TARGET_COLDFIRE
|| !ADDRESS_REG_P (op0
)))
4403 output_asm_insn ("tst%.l %0", ops
);
4404 else if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
4405 output_asm_insn ("cmpm%.l %1,%0", ops
);
4406 else if (REG_P (op1
)
4407 || (!REG_P (op0
) && GET_CODE (op0
) != MEM
))
4409 output_asm_insn ("cmp%.l %d0,%d1", ops
);
4410 std::swap (flags_compare_op0
, flags_compare_op1
);
4411 return swap_condition (code
);
4413 else if (!TARGET_COLDFIRE
4414 && ADDRESS_REG_P (op0
)
4415 && GET_CODE (op1
) == CONST_INT
4416 && INTVAL (op1
) < 0x8000
4417 && INTVAL (op1
) >= -0x8000)
4418 output_asm_insn ("cmp%.w %1,%0", ops
);
4420 output_asm_insn ("cmp%.l %d1,%d0", ops
);
4424 /* Emit a comparison between OP0 and OP1. CODE is the code of the
4425 comparison. It is returned, potentially modified if necessary. */
4427 m68k_output_compare_hi (rtx op0
, rtx op1
, rtx_code code
)
4429 rtx_code tmp
= m68k_find_flags_value (op0
, op1
, code
);
4433 remember_compare_flags (op0
, op1
);
4438 if (op1
== const0_rtx
)
4439 output_asm_insn ("tst%.w %d0", ops
);
4440 else if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
4441 output_asm_insn ("cmpm%.w %1,%0", ops
);
4442 else if ((REG_P (op1
) && !ADDRESS_REG_P (op1
))
4443 || (!REG_P (op0
) && GET_CODE (op0
) != MEM
))
4445 output_asm_insn ("cmp%.w %d0,%d1", ops
);
4446 std::swap (flags_compare_op0
, flags_compare_op1
);
4447 return swap_condition (code
);
4450 output_asm_insn ("cmp%.w %d1,%d0", ops
);
4454 /* Emit a comparison between OP0 and OP1. CODE is the code of the
4455 comparison. It is returned, potentially modified if necessary. */
4457 m68k_output_compare_qi (rtx op0
, rtx op1
, rtx_code code
)
4459 rtx_code tmp
= m68k_find_flags_value (op0
, op1
, code
);
4463 remember_compare_flags (op0
, op1
);
4468 if (op1
== const0_rtx
)
4469 output_asm_insn ("tst%.b %d0", ops
);
4470 else if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
4471 output_asm_insn ("cmpm%.b %1,%0", ops
);
4472 else if (REG_P (op1
) || (!REG_P (op0
) && GET_CODE (op0
) != MEM
))
4474 output_asm_insn ("cmp%.b %d0,%d1", ops
);
4475 std::swap (flags_compare_op0
, flags_compare_op1
);
4476 return swap_condition (code
);
4479 output_asm_insn ("cmp%.b %d1,%d0", ops
);
4483 /* Emit a comparison between OP0 and OP1. CODE is the code of the
4484 comparison. It is returned, potentially modified if necessary. */
4486 m68k_output_compare_fp (rtx op0
, rtx op1
, rtx_code code
)
4488 rtx_code tmp
= m68k_find_flags_value (op0
, op1
, code
);
4496 remember_compare_flags (op0
, op1
);
4498 machine_mode mode
= GET_MODE (op0
);
4499 std::string prec
= mode
== SFmode
? "s" : mode
== DFmode
? "d" : "x";
4501 if (op1
== CONST0_RTX (GET_MODE (op0
)))
4504 output_asm_insn ("ftst%.x %0", ops
);
4506 output_asm_insn (("ftst%." + prec
+ " %0").c_str (), ops
);
4510 switch (which_alternative
)
4513 output_asm_insn ("fcmp%.x %1,%0", ops
);
4516 output_asm_insn (("fcmp%." + prec
+ " %f1,%0").c_str (), ops
);
4519 output_asm_insn (("fcmp%." + prec
+ " %0,%f1").c_str (), ops
);
4520 std::swap (flags_compare_op0
, flags_compare_op1
);
4521 return swap_condition (code
);
4523 /* This is the ftst case, handled earlier. */
4529 /* Return an output template for a branch with CODE. */
4531 m68k_output_branch_integer (rtx_code code
)
4564 /* Return an output template for a reversed branch with CODE. */
4566 m68k_output_branch_integer_rev (rtx_code code
)
4599 /* Return an output template for a scc instruction with CODE. */
4601 m68k_output_scc (rtx_code code
)
4634 /* Return an output template for a floating point branch
4635 instruction with CODE. */
4637 m68k_output_branch_float (rtx_code code
)
4674 /* Return an output template for a reversed floating point branch
4675 instruction with CODE. */
4677 m68k_output_branch_float_rev (rtx_code code
)
4714 /* Return an output template for a floating point scc
4715 instruction with CODE. */
4717 m68k_output_scc_float (rtx_code code
)
4757 output_move_const_double (rtx
*operands
)
4759 int code
= standard_68881_constant_p (operands
[1]);
4763 static char buf
[40];
4765 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4768 return "fmove%.d %1,%0";
4772 output_move_const_single (rtx
*operands
)
4774 int code
= standard_68881_constant_p (operands
[1]);
4778 static char buf
[40];
4780 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4783 return "fmove%.s %f1,%0";
4786 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4787 from the "fmovecr" instruction.
4788 The value, anded with 0xff, gives the code to use in fmovecr
4789 to get the desired constant. */
4791 /* This code has been fixed for cross-compilation. */
4793 static int inited_68881_table
= 0;
4795 static const char *const strings_68881
[7] = {
4805 static const int codes_68881
[7] = {
4815 REAL_VALUE_TYPE values_68881
[7];
4817 /* Set up values_68881 array by converting the decimal values
4818 strings_68881 to binary. */
4821 init_68881_table (void)
4828 for (i
= 0; i
< 7; i
++)
4832 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4833 values_68881
[i
] = r
;
4835 inited_68881_table
= 1;
4839 standard_68881_constant_p (rtx x
)
4841 const REAL_VALUE_TYPE
*r
;
4844 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4845 used at all on those chips. */
4849 if (! inited_68881_table
)
4850 init_68881_table ();
4852 r
= CONST_DOUBLE_REAL_VALUE (x
);
4854 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4855 for (i
= 0; i
< 6; i
++)
4857 if (real_identical (r
, &values_68881
[i
]))
4858 return (codes_68881
[i
]);
4861 if (GET_MODE (x
) == SFmode
)
4864 if (real_equal (r
, &values_68881
[6]))
4865 return (codes_68881
[6]);
4867 /* larger powers of ten in the constants ram are not used
4868 because they are not equal to a `double' C constant. */
4872 /* If X is a floating-point constant, return the logarithm of X base 2,
4873 or 0 if X is not a power of 2. */
4876 floating_exact_log2 (rtx x
)
4878 const REAL_VALUE_TYPE
*r
;
4882 r
= CONST_DOUBLE_REAL_VALUE (x
);
4884 if (real_less (r
, &dconst1
))
4887 exp
= real_exponent (r
);
4888 real_2expN (&r1
, exp
, DFmode
);
4889 if (real_equal (&r1
, r
))
4895 /* A C compound statement to output to stdio stream STREAM the
4896 assembler syntax for an instruction operand X. X is an RTL
4899 CODE is a value that can be used to specify one of several ways
4900 of printing the operand. It is used when identical operands
4901 must be printed differently depending on the context. CODE
4902 comes from the `%' specification that was used to request
4903 printing of the operand. If the specification was just `%DIGIT'
4904 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4905 is the ASCII code for LTR.
4907 If X is a register, this macro should print the register's name.
4908 The names can be found in an array `reg_names' whose type is
4909 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4911 When the machine description has a specification `%PUNCT' (a `%'
4912 followed by a punctuation character), this macro is called with
4913 a null pointer for X and the punctuation character for CODE.
4915 The m68k specific codes are:
4917 '.' for dot needed in Motorola-style opcode names.
4918 '-' for an operand pushing on the stack:
4919 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4920 '+' for an operand pushing on the stack:
4921 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4922 '@' for a reference to the top word on the stack:
4923 sp@, (sp) or (%sp) depending on the style of syntax.
4924 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4925 but & in SGS syntax).
4926 '!' for the cc register (used in an `and to cc' insn).
4927 '$' for the letter `s' in an op code, but only on the 68040.
4928 '&' for the letter `d' in an op code, but only on the 68040.
4929 '/' for register prefix needed by longlong.h.
4930 '?' for m68k_library_id_string
4932 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4933 'd' to force memory addressing to be absolute, not relative.
4934 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4935 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4936 or print pair of registers as rx:ry.
4937 'p' print an address with @PLTPC attached, but only if the operand
4938 is not locally-bound. */
4941 print_operand (FILE *file
, rtx op
, int letter
)
4944 m68k_adjust_decorated_operand (op
);
4949 fprintf (file
, ".");
4951 else if (letter
== '#')
4952 asm_fprintf (file
, "%I");
4953 else if (letter
== '-')
4954 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4955 else if (letter
== '+')
4956 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4957 else if (letter
== '@')
4958 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4959 else if (letter
== '!')
4960 asm_fprintf (file
, "%Rfpcr");
4961 else if (letter
== '$')
4964 fprintf (file
, "s");
4966 else if (letter
== '&')
4969 fprintf (file
, "d");
4971 else if (letter
== '/')
4972 asm_fprintf (file
, "%R");
4973 else if (letter
== '?')
4974 asm_fprintf (file
, m68k_library_id_string
);
4975 else if (letter
== 'p')
4977 output_addr_const (file
, op
);
4978 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4979 fprintf (file
, "@PLTPC");
4981 else if (GET_CODE (op
) == REG
)
4984 /* Print out the second register name of a register pair.
4985 I.e., R (6) => 7. */
4986 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4988 fputs (M68K_REGNAME(REGNO (op
)), file
);
4990 else if (GET_CODE (op
) == MEM
)
4992 output_address (GET_MODE (op
), XEXP (op
, 0));
4993 if (letter
== 'd' && ! TARGET_68020
4994 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4995 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4996 && INTVAL (XEXP (op
, 0)) < 0x8000
4997 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4998 fprintf (file
, MOTOROLA
? ".l" : ":l");
5000 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
5003 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5004 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
5006 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
5009 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5010 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
5011 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
5013 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
5016 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5017 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
5021 /* Use `print_operand_address' instead of `output_addr_const'
5022 to ensure that we print relevant PIC stuff. */
5023 asm_fprintf (file
, "%I");
5025 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
5026 print_operand_address (file
, op
);
5028 output_addr_const (file
, op
);
5032 /* Return string for TLS relocation RELOC. */
5035 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
5037 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
5038 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
5045 if (flag_pic
== 1 && TARGET_68020
)
5087 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
5090 m68k_output_addr_const_extra (FILE *file
, rtx x
)
5092 if (GET_CODE (x
) == UNSPEC
)
5094 switch (XINT (x
, 1))
5096 case UNSPEC_RELOC16
:
5097 case UNSPEC_RELOC32
:
5098 output_addr_const (file
, XVECEXP (x
, 0, 0));
5099 fputs (m68k_get_reloc_decoration
5100 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
5111 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
5114 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5116 gcc_assert (size
== 4);
5117 fputs ("\t.long\t", file
);
5118 output_addr_const (file
, x
);
5119 fputs ("@TLSLDO+0x8000", file
);
5122 /* In the name of slightly smaller debug output, and to cater to
5123 general assembler lossage, recognize various UNSPEC sequences
5124 and turn them back into a direct symbol reference. */
5127 m68k_delegitimize_address (rtx orig_x
)
5130 struct m68k_address addr
;
5133 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5138 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
5141 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
5142 || addr
.offset
== NULL_RTX
5143 || GET_CODE (addr
.offset
) != CONST
)
5146 unspec
= XEXP (addr
.offset
, 0);
5147 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
5148 unspec
= XEXP (unspec
, 0);
5149 if (GET_CODE (unspec
) != UNSPEC
5150 || (XINT (unspec
, 1) != UNSPEC_RELOC16
5151 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
5153 x
= XVECEXP (unspec
, 0, 0);
5154 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
5155 if (unspec
!= XEXP (addr
.offset
, 0))
5156 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
5159 rtx idx
= addr
.index
;
5160 if (addr
.scale
!= 1)
5161 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
5162 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
5165 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
5167 x
= replace_equiv_address_nv (orig_x
, x
);
5172 /* A C compound statement to output to stdio stream STREAM the
5173 assembler syntax for an instruction operand that is a memory
5174 reference whose address is ADDR. ADDR is an RTL expression.
5176 Note that this contains a kludge that knows that the only reason
5177 we have an address (plus (label_ref...) (reg...)) when not generating
5178 PIC code is in the insn before a tablejump, and we know that m68k.md
5179 generates a label LInnn: on such an insn.
5181 It is possible for PIC to generate a (plus (label_ref...) (reg...))
5182 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
5184 This routine is responsible for distinguishing between -fpic and -fPIC
5185 style relocations in an address. When generating -fpic code the
5186 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
5187 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
5190 print_operand_address (FILE *file
, rtx addr
)
5192 struct m68k_address address
;
5194 m68k_adjust_decorated_operand (addr
);
5196 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
5199 if (address
.code
== PRE_DEC
)
5200 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
5201 M68K_REGNAME (REGNO (address
.base
)));
5202 else if (address
.code
== POST_INC
)
5203 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
5204 M68K_REGNAME (REGNO (address
.base
)));
5205 else if (!address
.base
&& !address
.index
)
5207 /* A constant address. */
5208 gcc_assert (address
.offset
== addr
);
5209 if (GET_CODE (addr
) == CONST_INT
)
5211 /* (xxx).w or (xxx).l. */
5212 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
5213 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
5215 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
5217 else if (TARGET_PCREL
)
5219 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
5221 output_addr_const (file
, addr
);
5222 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
5226 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
5227 name ends in `.<letter>', as the last 2 characters can be
5228 mistaken as a size suffix. Put the name in parentheses. */
5229 if (GET_CODE (addr
) == SYMBOL_REF
5230 && strlen (XSTR (addr
, 0)) > 2
5231 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
5234 output_addr_const (file
, addr
);
5238 output_addr_const (file
, addr
);
5245 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
5246 label being accessed, otherwise it is -1. */
5247 labelno
= (address
.offset
5249 && GET_CODE (address
.offset
) == LABEL_REF
5250 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
5254 /* Print the "offset(base" component. */
5256 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
5260 output_addr_const (file
, address
.offset
);
5264 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
5266 /* Print the ",index" component, if any. */
5271 fprintf (file
, "%s.%c",
5272 M68K_REGNAME (REGNO (address
.index
)),
5273 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
5274 if (address
.scale
!= 1)
5275 fprintf (file
, "*%d", address
.scale
);
5279 else /* !MOTOROLA */
5281 if (!address
.offset
&& !address
.index
)
5282 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
5285 /* Print the "base@(offset" component. */
5287 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
5291 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
5292 fprintf (file
, "@(");
5294 output_addr_const (file
, address
.offset
);
5296 /* Print the ",index" component, if any. */
5299 fprintf (file
, ",%s:%c",
5300 M68K_REGNAME (REGNO (address
.index
)),
5301 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
5302 if (address
.scale
!= 1)
5303 fprintf (file
, ":%d", address
.scale
);
5311 /* Check for cases where a clr insns can be omitted from code using
5312 strict_low_part sets. For example, the second clrl here is not needed:
5313 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
5315 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
5316 insn we are checking for redundancy. TARGET is the register set by the
5320 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
5323 rtx_insn
*p
= first_insn
;
5325 while ((p
= PREV_INSN (p
)))
5327 if (NOTE_INSN_BASIC_BLOCK_P (p
))
5333 /* If it isn't an insn, then give up. */
5337 if (reg_set_p (target
, p
))
5339 rtx set
= single_set (p
);
5342 /* If it isn't an easy to recognize insn, then give up. */
5346 dest
= SET_DEST (set
);
5348 /* If this sets the entire target register to zero, then our
5349 first_insn is redundant. */
5350 if (rtx_equal_p (dest
, target
)
5351 && SET_SRC (set
) == const0_rtx
)
5353 else if (GET_CODE (dest
) == STRICT_LOW_PART
5354 && GET_CODE (XEXP (dest
, 0)) == REG
5355 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
5356 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
5357 <= GET_MODE_SIZE (mode
)))
5358 /* This is a strict low part set which modifies less than
5359 we are using, so it is safe. */
5369 /* Operand predicates for implementing asymmetric pc-relative addressing
5370 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
5371 when used as a source operand, but not as a destination operand.
5373 We model this by restricting the meaning of the basic predicates
5374 (general_operand, memory_operand, etc) to forbid the use of this
5375 addressing mode, and then define the following predicates that permit
5376 this addressing mode. These predicates can then be used for the
5377 source operands of the appropriate instructions.
5379 n.b. While it is theoretically possible to change all machine patterns
5380 to use this addressing more where permitted by the architecture,
5381 it has only been implemented for "common" cases: SImode, HImode, and
5382 QImode operands, and only for the principle operations that would
5383 require this addressing mode: data movement and simple integer operations.
5385 In parallel with these new predicates, two new constraint letters
5386 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
5387 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
5388 In the pcrel case 's' is only valid in combination with 'a' registers.
5389 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
5390 of how these constraints are used.
5392 The use of these predicates is strictly optional, though patterns that
5393 don't will cause an extra reload register to be allocated where one
5396 lea (abc:w,%pc),%a0 ; need to reload address
5397 moveq &1,%d1 ; since write to pc-relative space
5398 movel %d1,%a0@ ; is not allowed
5400 lea (abc:w,%pc),%a1 ; no need to reload address here
5401 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
5403 For more info, consult tiemann@cygnus.com.
5406 All of the ugliness with predicates and constraints is due to the
5407 simple fact that the m68k does not allow a pc-relative addressing
5408 mode as a destination. gcc does not distinguish between source and
5409 destination addresses. Hence, if we claim that pc-relative address
5410 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
5411 end up with invalid code. To get around this problem, we left
5412 pc-relative modes as invalid addresses, and then added special
5413 predicates and constraints to accept them.
5415 A cleaner way to handle this is to modify gcc to distinguish
5416 between source and destination addresses. We can then say that
5417 pc-relative is a valid source address but not a valid destination
5418 address, and hopefully avoid a lot of the predicate and constraint
5419 hackery. Unfortunately, this would be a pretty big change. It would
5420 be a useful change for a number of ports, but there aren't any current
5421 plans to undertake this.
5423 ***************************************************************************/
5427 output_andsi3 (rtx
*operands
)
5431 if (GET_CODE (operands
[2]) == CONST_INT
5432 && (INTVAL (operands
[2]) | 0xffff) == -1
5433 && (DATA_REG_P (operands
[0])
5434 || offsettable_memref_p (operands
[0]))
5435 && !TARGET_COLDFIRE
)
5437 if (GET_CODE (operands
[0]) != REG
)
5438 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5439 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
5440 if (operands
[2] == const0_rtx
)
5442 return "and%.w %2,%0";
5444 if (GET_CODE (operands
[2]) == CONST_INT
5445 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
5446 && (DATA_REG_P (operands
[0])
5447 || offsettable_memref_p (operands
[0])))
5449 if (DATA_REG_P (operands
[0]))
5450 operands
[1] = GEN_INT (logval
);
5453 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5454 operands
[1] = GEN_INT (logval
% 8);
5456 return "bclr %1,%0";
5458 /* Only a standard logical operation on the whole word sets the
5459 condition codes in a way we can use. */
5460 if (!side_effects_p (operands
[0]))
5461 flags_operand1
= operands
[0];
5462 flags_valid
= FLAGS_VALID_YES
;
5463 return "and%.l %2,%0";
5467 output_iorsi3 (rtx
*operands
)
5469 register int logval
;
5471 if (GET_CODE (operands
[2]) == CONST_INT
5472 && INTVAL (operands
[2]) >> 16 == 0
5473 && (DATA_REG_P (operands
[0])
5474 || offsettable_memref_p (operands
[0]))
5475 && !TARGET_COLDFIRE
)
5477 if (GET_CODE (operands
[0]) != REG
)
5478 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5479 if (INTVAL (operands
[2]) == 0xffff)
5480 return "mov%.w %2,%0";
5481 return "or%.w %2,%0";
5483 if (GET_CODE (operands
[2]) == CONST_INT
5484 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5485 && (DATA_REG_P (operands
[0])
5486 || offsettable_memref_p (operands
[0])))
5488 if (DATA_REG_P (operands
[0]))
5489 operands
[1] = GEN_INT (logval
);
5492 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5493 operands
[1] = GEN_INT (logval
% 8);
5495 return "bset %1,%0";
5497 /* Only a standard logical operation on the whole word sets the
5498 condition codes in a way we can use. */
5499 if (!side_effects_p (operands
[0]))
5500 flags_operand1
= operands
[0];
5501 flags_valid
= FLAGS_VALID_YES
;
5502 return "or%.l %2,%0";
5506 output_xorsi3 (rtx
*operands
)
5508 register int logval
;
5510 if (GET_CODE (operands
[2]) == CONST_INT
5511 && INTVAL (operands
[2]) >> 16 == 0
5512 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5513 && !TARGET_COLDFIRE
)
5515 if (! DATA_REG_P (operands
[0]))
5516 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5517 if (INTVAL (operands
[2]) == 0xffff)
5519 return "eor%.w %2,%0";
5521 if (GET_CODE (operands
[2]) == CONST_INT
5522 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5523 && (DATA_REG_P (operands
[0])
5524 || offsettable_memref_p (operands
[0])))
5526 if (DATA_REG_P (operands
[0]))
5527 operands
[1] = GEN_INT (logval
);
5530 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5531 operands
[1] = GEN_INT (logval
% 8);
5533 return "bchg %1,%0";
5535 /* Only a standard logical operation on the whole word sets the
5536 condition codes in a way we can use. */
5537 if (!side_effects_p (operands
[0]))
5538 flags_operand1
= operands
[0];
5539 flags_valid
= FLAGS_VALID_YES
;
5540 return "eor%.l %2,%0";
5543 /* Return the instruction that should be used for a call to address X,
5544 which is known to be in operand 0. */
5549 if (symbolic_operand (x
, VOIDmode
))
5550 return m68k_symbolic_call
;
5555 /* Likewise sibling calls. */
5558 output_sibcall (rtx x
)
5560 if (symbolic_operand (x
, VOIDmode
))
5561 return m68k_symbolic_jump
;
5567 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5568 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5571 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk
));
5572 rtx this_slot
, offset
, addr
, mem
, tmp
;
5575 /* Avoid clobbering the struct value reg by using the
5576 static chain reg as a temporary. */
5577 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5579 /* Pretend to be a post-reload pass while generating rtl. */
5580 reload_completed
= 1;
5582 /* The "this" pointer is stored at 4(%sp). */
5583 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5584 stack_pointer_rtx
, 4));
5586 /* Add DELTA to THIS. */
5589 /* Make the offset a legitimate operand for memory addition. */
5590 offset
= GEN_INT (delta
);
5591 if ((delta
< -8 || delta
> 8)
5592 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5594 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5595 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5597 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5598 copy_rtx (this_slot
), offset
));
5601 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5602 if (vcall_offset
!= 0)
5604 /* Set the static chain register to *THIS. */
5605 emit_move_insn (tmp
, this_slot
);
5606 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5608 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5609 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5610 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5612 emit_insn (gen_rtx_SET (tmp
, addr
));
5616 /* Load the offset into %d0 and add it to THIS. */
5617 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5618 gen_rtx_MEM (Pmode
, addr
));
5619 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5620 copy_rtx (this_slot
),
5621 gen_rtx_REG (Pmode
, D0_REG
)));
5624 /* Jump to the target function. Use a sibcall if direct jumps are
5625 allowed, otherwise load the address into a register first. */
5626 mem
= DECL_RTL (function
);
5627 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5629 gcc_assert (flag_pic
);
5631 if (!TARGET_SEP_DATA
)
5633 /* Use the static chain register as a temporary (call-clobbered)
5634 GOT pointer for this function. We can use the static chain
5635 register because it isn't live on entry to the thunk. */
5636 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5637 emit_insn (gen_load_got (pic_offset_table_rtx
));
5639 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5640 mem
= replace_equiv_address (mem
, tmp
);
5642 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5643 SIBLING_CALL_P (insn
) = 1;
5645 /* Run just enough of rest_of_compilation. */
5646 insn
= get_insns ();
5647 split_all_insns_noflow ();
5648 assemble_start_function (thunk
, fnname
);
5649 final_start_function (insn
, file
, 1);
5650 final (insn
, file
, 1);
5651 final_end_function ();
5652 assemble_end_function (thunk
, fnname
);
5654 /* Clean up the vars set above. */
5655 reload_completed
= 0;
5657 /* Restore the original PIC register. */
5659 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5662 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5665 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5666 int incoming ATTRIBUTE_UNUSED
)
5668 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5671 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5673 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5674 unsigned int new_reg
)
5677 /* Interrupt functions can only use registers that have already been
5678 saved by the prologue, even if they would normally be
5681 if ((m68k_get_function_kind (current_function_decl
)
5682 == m68k_fk_interrupt_handler
)
5683 && !df_regs_ever_live_p (new_reg
))
5689 /* Implement TARGET_HARD_REGNO_NREGS.
5691 On the m68k, ordinary registers hold 32 bits worth;
5692 for the 68881 registers, a single register is always enough for
5693 anything that can be stored in them at all. */
5696 m68k_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
5699 return GET_MODE_NUNITS (mode
);
5700 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
5703 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5704 registers can hold any mode, but restrict the 68881 registers to
5705 floating-point modes. */
5708 m68k_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5710 if (DATA_REGNO_P (regno
))
5712 /* Data Registers, can hold aggregate if fits in. */
5713 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5716 else if (ADDRESS_REGNO_P (regno
))
5718 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5721 else if (FP_REGNO_P (regno
))
5723 /* FPU registers, hold float or complex float of long double or
5725 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5726 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5727 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5733 /* Implement TARGET_MODES_TIEABLE_P. */
5736 m68k_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5738 return (!TARGET_HARD_FLOAT
5739 || ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
5740 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
5741 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
5742 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
)));
5745 /* Implement SECONDARY_RELOAD_CLASS. */
5748 m68k_secondary_reload_class (enum reg_class rclass
,
5749 machine_mode mode
, rtx x
)
5753 regno
= true_regnum (x
);
5755 /* If one operand of a movqi is an address register, the other
5756 operand must be a general register or constant. Other types
5757 of operand must be reloaded through a data register. */
5758 if (GET_MODE_SIZE (mode
) == 1
5759 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5760 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5763 /* PC-relative addresses must be loaded into an address register first. */
5765 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5766 && symbolic_operand (x
, VOIDmode
))
5772 /* Implement PREFERRED_RELOAD_CLASS. */
5775 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5777 enum reg_class secondary_class
;
5779 /* If RCLASS might need a secondary reload, try restricting it to
5780 a class that doesn't. */
5781 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5782 if (secondary_class
!= NO_REGS
5783 && reg_class_subset_p (secondary_class
, rclass
))
5784 return secondary_class
;
5786 /* Prefer to use moveq for in-range constants. */
5787 if (GET_CODE (x
) == CONST_INT
5788 && reg_class_subset_p (DATA_REGS
, rclass
)
5789 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5792 /* ??? Do we really need this now? */
5793 if (GET_CODE (x
) == CONST_DOUBLE
5794 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5796 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5805 /* Return floating point values in a 68881 register. This makes 68881 code
5806 a little bit faster. It also makes -msoft-float code incompatible with
5807 hard-float code, so people have to be careful not to mix the two.
5808 For ColdFire it was decided the ABI incompatibility is undesirable.
5809 If there is need for a hard-float ABI it is probably worth doing it
5810 properly and also passing function arguments in FP registers. */
5812 m68k_libcall_value (machine_mode mode
)
5819 return gen_rtx_REG (mode
, FP0_REG
);
5825 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5828 /* Location in which function value is returned.
5829 NOTE: Due to differences in ABIs, don't call this function directly,
5830 use FUNCTION_VALUE instead. */
5832 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5836 mode
= TYPE_MODE (valtype
);
5842 return gen_rtx_REG (mode
, FP0_REG
);
5848 /* If the function returns a pointer, push that into %a0. */
5849 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5850 /* For compatibility with the large body of existing code which
5851 does not always properly declare external functions returning
5852 pointer types, the m68k/SVR4 convention is to copy the value
5853 returned for pointer functions from a0 to d0 in the function
5854 epilogue, so that callers that have neglected to properly
5855 declare the callee can still find the correct return value in
5857 return gen_rtx_PARALLEL
5860 gen_rtx_EXPR_LIST (VOIDmode
,
5861 gen_rtx_REG (mode
, A0_REG
),
5863 gen_rtx_EXPR_LIST (VOIDmode
,
5864 gen_rtx_REG (mode
, D0_REG
),
5866 else if (POINTER_TYPE_P (valtype
))
5867 return gen_rtx_REG (mode
, A0_REG
);
5869 return gen_rtx_REG (mode
, D0_REG
);
5872 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5873 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5875 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5877 machine_mode mode
= TYPE_MODE (type
);
5879 if (mode
== BLKmode
)
5882 /* If TYPE's known alignment is less than the alignment of MODE that
5883 would contain the structure, then return in memory. We need to
5884 do so to maintain the compatibility between code compiled with
5885 -mstrict-align and that compiled with -mno-strict-align. */
5886 if (AGGREGATE_TYPE_P (type
)
5887 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5894 /* CPU to schedule the program for. */
5895 enum attr_cpu m68k_sched_cpu
;
5897 /* MAC to schedule the program for. */
5898 enum attr_mac m68k_sched_mac
;
5906 /* Integer register. */
5912 /* Implicit mem reference (e.g. stack). */
5915 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5918 /* Memory with offset but without indexing. EA mode 5. */
5921 /* Memory with indexing. EA mode 6. */
5924 /* Memory referenced by absolute address. EA mode 7. */
5927 /* Immediate operand that doesn't require extension word. */
5930 /* Immediate 16 bit operand. */
5933 /* Immediate 32 bit operand. */
5937 /* Return type of memory ADDR_RTX refers to. */
5938 static enum attr_op_type
5939 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5941 struct m68k_address address
;
5943 if (symbolic_operand (addr_rtx
, VOIDmode
))
5944 return OP_TYPE_MEM7
;
5946 if (!m68k_decompose_address (mode
, addr_rtx
,
5947 reload_completed
, &address
))
5949 gcc_assert (!reload_completed
);
5950 /* Reload will likely fix the address to be in the register. */
5951 return OP_TYPE_MEM234
;
5954 if (address
.scale
!= 0)
5955 return OP_TYPE_MEM6
;
5957 if (address
.base
!= NULL_RTX
)
5959 if (address
.offset
== NULL_RTX
)
5960 return OP_TYPE_MEM234
;
5962 return OP_TYPE_MEM5
;
5965 gcc_assert (address
.offset
!= NULL_RTX
);
5967 return OP_TYPE_MEM7
;
5970 /* Return X or Y (depending on OPX_P) operand of INSN. */
5972 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5976 if (recog_memoized (insn
) < 0)
5979 extract_constrain_insn_cached (insn
);
5982 i
= get_attr_opx (insn
);
5984 i
= get_attr_opy (insn
);
5986 if (i
>= recog_data
.n_operands
)
5989 return recog_data
.operand
[i
];
5992 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5993 If ADDRESS_P is true, return type of memory location operand refers to. */
5994 static enum attr_op_type
5995 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5999 op
= sched_get_operand (insn
, opx_p
);
6003 gcc_assert (!reload_completed
);
6008 return sched_address_type (QImode
, op
);
6010 if (memory_operand (op
, VOIDmode
))
6011 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
6013 if (register_operand (op
, VOIDmode
))
6015 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
6016 || (reload_completed
&& FP_REG_P (op
)))
6022 if (GET_CODE (op
) == CONST_INT
)
6028 /* Check for quick constants. */
6029 switch (get_attr_type (insn
))
6032 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
6033 return OP_TYPE_IMM_Q
;
6035 gcc_assert (!reload_completed
);
6039 if (USE_MOVQ (ival
))
6040 return OP_TYPE_IMM_Q
;
6042 gcc_assert (!reload_completed
);
6046 if (valid_mov3q_const (ival
))
6047 return OP_TYPE_IMM_Q
;
6049 gcc_assert (!reload_completed
);
6056 if (IN_RANGE (ival
, -0x8000, 0x7fff))
6057 return OP_TYPE_IMM_W
;
6059 return OP_TYPE_IMM_L
;
6062 if (GET_CODE (op
) == CONST_DOUBLE
)
6064 switch (GET_MODE (op
))
6067 return OP_TYPE_IMM_W
;
6071 return OP_TYPE_IMM_L
;
6078 if (GET_CODE (op
) == CONST
6079 || symbolic_operand (op
, VOIDmode
)
6082 switch (GET_MODE (op
))
6085 return OP_TYPE_IMM_Q
;
6088 return OP_TYPE_IMM_W
;
6091 return OP_TYPE_IMM_L
;
6094 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
6096 return OP_TYPE_IMM_W
;
6098 return OP_TYPE_IMM_L
;
6102 gcc_assert (!reload_completed
);
6104 if (FLOAT_MODE_P (GET_MODE (op
)))
6110 /* Implement opx_type attribute.
6111 Return type of INSN's operand X.
6112 If ADDRESS_P is true, return type of memory location operand refers to. */
6114 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
6116 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
6122 return OPX_TYPE_FPN
;
6125 return OPX_TYPE_MEM1
;
6127 case OP_TYPE_MEM234
:
6128 return OPX_TYPE_MEM234
;
6131 return OPX_TYPE_MEM5
;
6134 return OPX_TYPE_MEM6
;
6137 return OPX_TYPE_MEM7
;
6140 return OPX_TYPE_IMM_Q
;
6143 return OPX_TYPE_IMM_W
;
6146 return OPX_TYPE_IMM_L
;
6153 /* Implement opy_type attribute.
6154 Return type of INSN's operand Y.
6155 If ADDRESS_P is true, return type of memory location operand refers to. */
6157 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
6159 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
6165 return OPY_TYPE_FPN
;
6168 return OPY_TYPE_MEM1
;
6170 case OP_TYPE_MEM234
:
6171 return OPY_TYPE_MEM234
;
6174 return OPY_TYPE_MEM5
;
6177 return OPY_TYPE_MEM6
;
6180 return OPY_TYPE_MEM7
;
6183 return OPY_TYPE_IMM_Q
;
6186 return OPY_TYPE_IMM_W
;
6189 return OPY_TYPE_IMM_L
;
6196 /* Return size of INSN as int. */
6198 sched_get_attr_size_int (rtx_insn
*insn
)
6202 switch (get_attr_type (insn
))
6205 /* There should be no references to m68k_sched_attr_size for 'ignore'
6219 switch (get_attr_opx_type (insn
))
6225 case OPX_TYPE_MEM234
:
6226 case OPY_TYPE_IMM_Q
:
6231 /* Here we assume that most absolute references are short. */
6233 case OPY_TYPE_IMM_W
:
6237 case OPY_TYPE_IMM_L
:
6245 switch (get_attr_opy_type (insn
))
6251 case OPY_TYPE_MEM234
:
6252 case OPY_TYPE_IMM_Q
:
6257 /* Here we assume that most absolute references are short. */
6259 case OPY_TYPE_IMM_W
:
6263 case OPY_TYPE_IMM_L
:
6273 gcc_assert (!reload_completed
);
6281 /* Return size of INSN as attribute enum value. */
6283 m68k_sched_attr_size (rtx_insn
*insn
)
6285 switch (sched_get_attr_size_int (insn
))
6301 /* Return operand X or Y (depending on OPX_P) of INSN,
6302 if it is a MEM, or NULL overwise. */
6303 static enum attr_op_type
6304 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
6308 switch (get_attr_opx_type (insn
))
6313 case OPX_TYPE_IMM_Q
:
6314 case OPX_TYPE_IMM_W
:
6315 case OPX_TYPE_IMM_L
:
6319 case OPX_TYPE_MEM234
:
6322 return OP_TYPE_MEM1
;
6325 return OP_TYPE_MEM6
;
6333 switch (get_attr_opy_type (insn
))
6338 case OPY_TYPE_IMM_Q
:
6339 case OPY_TYPE_IMM_W
:
6340 case OPY_TYPE_IMM_L
:
6344 case OPY_TYPE_MEM234
:
6347 return OP_TYPE_MEM1
;
6350 return OP_TYPE_MEM6
;
6358 /* Implement op_mem attribute. */
6360 m68k_sched_attr_op_mem (rtx_insn
*insn
)
6362 enum attr_op_type opx
;
6363 enum attr_op_type opy
;
6365 opx
= sched_get_opxy_mem_type (insn
, true);
6366 opy
= sched_get_opxy_mem_type (insn
, false);
6368 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
6371 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
6373 switch (get_attr_opx_access (insn
))
6389 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
6391 switch (get_attr_opx_access (insn
))
6407 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
6410 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
6412 switch (get_attr_opx_access (insn
))
6418 gcc_assert (!reload_completed
);
6423 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
6425 switch (get_attr_opx_access (insn
))
6431 gcc_assert (!reload_completed
);
6436 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
6439 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
6441 switch (get_attr_opx_access (insn
))
6447 gcc_assert (!reload_completed
);
6452 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
6453 gcc_assert (!reload_completed
);
6457 /* Data for ColdFire V4 index bypass.
6458 Producer modifies register that is used as index in consumer with
6462 /* Producer instruction. */
6465 /* Consumer instruction. */
6468 /* Scale of indexed memory access within consumer.
6469 Or zero if bypass should not be effective at the moment. */
6471 } sched_cfv4_bypass_data
;
6473 /* An empty state that is used in m68k_sched_adjust_cost. */
6474 static state_t sched_adjust_cost_state
;
6476 /* Implement adjust_cost scheduler hook.
6477 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
6479 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
6484 if (recog_memoized (def_insn
) < 0
6485 || recog_memoized (insn
) < 0)
6488 if (sched_cfv4_bypass_data
.scale
== 1)
6489 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
6491 /* haifa-sched.c: insn_cost () calls bypass_p () just before
6492 targetm.sched.adjust_cost (). Hence, we can be relatively sure
6493 that the data in sched_cfv4_bypass_data is up to date. */
6494 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
6495 && sched_cfv4_bypass_data
.con
== insn
);
6500 sched_cfv4_bypass_data
.pro
= NULL
;
6501 sched_cfv4_bypass_data
.con
= NULL
;
6502 sched_cfv4_bypass_data
.scale
= 0;
6505 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6506 && sched_cfv4_bypass_data
.con
== NULL
6507 && sched_cfv4_bypass_data
.scale
== 0);
6509 /* Don't try to issue INSN earlier than DFA permits.
6510 This is especially useful for instructions that write to memory,
6511 as their true dependence (default) latency is better to be set to 0
6512 to workaround alias analysis limitations.
6513 This is, in fact, a machine independent tweak, so, probably,
6514 it should be moved to haifa-sched.c: insn_cost (). */
6515 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
6522 /* Return maximal number of insns that can be scheduled on a single cycle. */
6524 m68k_sched_issue_rate (void)
6526 switch (m68k_sched_cpu
)
6542 /* Maximal length of instruction for current CPU.
6543 E.g. it is 3 for any ColdFire core. */
6544 static int max_insn_size
;
6546 /* Data to model instruction buffer of CPU. */
6549 /* True if instruction buffer model is modeled for current CPU. */
6552 /* Size of the instruction buffer in words. */
6555 /* Number of filled words in the instruction buffer. */
6558 /* Additional information about instruction buffer for CPUs that have
6559 a buffer of instruction records, rather then a plain buffer
6560 of instruction words. */
6561 struct _sched_ib_records
6563 /* Size of buffer in records. */
6566 /* Array to hold data on adjustments made to the size of the buffer. */
6569 /* Index of the above array. */
6573 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6577 static struct _sched_ib sched_ib
;
6579 /* ID of memory unit. */
6580 static int sched_mem_unit_code
;
6582 /* Implementation of the targetm.sched.variable_issue () hook.
6583 It is called after INSN was issued. It returns the number of insns
6584 that can possibly get scheduled on the current cycle.
6585 It is used here to determine the effect of INSN on the instruction
6588 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6589 int sched_verbose ATTRIBUTE_UNUSED
,
6590 rtx_insn
*insn
, int can_issue_more
)
6594 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6596 switch (m68k_sched_cpu
)
6600 insn_size
= sched_get_attr_size_int (insn
);
6604 insn_size
= sched_get_attr_size_int (insn
);
6606 /* ColdFire V3 and V4 cores have instruction buffers that can
6607 accumulate up to 8 instructions regardless of instructions'
6608 sizes. So we should take care not to "prefetch" 24 one-word
6609 or 12 two-words instructions.
6610 To model this behavior we temporarily decrease size of the
6611 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6615 adjust
= max_insn_size
- insn_size
;
6616 sched_ib
.size
-= adjust
;
6618 if (sched_ib
.filled
> sched_ib
.size
)
6619 sched_ib
.filled
= sched_ib
.size
;
6621 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6624 ++sched_ib
.records
.adjust_index
;
6625 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6626 sched_ib
.records
.adjust_index
= 0;
6628 /* Undo adjustment we did 7 instructions ago. */
6630 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6635 gcc_assert (!sched_ib
.enabled_p
);
6643 if (insn_size
> sched_ib
.filled
)
6644 /* Scheduling for register pressure does not always take DFA into
6645 account. Workaround instruction buffer not being filled enough. */
6647 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6648 insn_size
= sched_ib
.filled
;
6653 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6654 || asm_noperands (PATTERN (insn
)) >= 0)
6655 insn_size
= sched_ib
.filled
;
6659 sched_ib
.filled
-= insn_size
;
6661 return can_issue_more
;
6664 /* Return how many instructions should scheduler lookahead to choose the
6667 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6669 return m68k_sched_issue_rate () - 1;
6672 /* Implementation of targetm.sched.init_global () hook.
6673 It is invoked once per scheduling pass and is used here
6674 to initialize scheduler constants. */
6676 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6677 int sched_verbose ATTRIBUTE_UNUSED
,
6678 int n_insns ATTRIBUTE_UNUSED
)
6680 /* Check that all instructions have DFA reservations and
6681 that all instructions can be issued from a clean state. */
6687 state
= alloca (state_size ());
6689 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6691 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6693 gcc_assert (insn_has_dfa_reservation_p (insn
));
6695 state_reset (state
);
6696 if (state_transition (state
, insn
) >= 0)
6702 /* Setup target cpu. */
6704 /* ColdFire V4 has a set of features to keep its instruction buffer full
6705 (e.g., a separate memory bus for instructions) and, hence, we do not model
6706 buffer for this CPU. */
6707 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6709 switch (m68k_sched_cpu
)
6712 sched_ib
.filled
= 0;
6719 sched_ib
.records
.n_insns
= 0;
6720 sched_ib
.records
.adjust
= NULL
;
6725 sched_ib
.records
.n_insns
= 8;
6726 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6733 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6735 sched_adjust_cost_state
= xmalloc (state_size ());
6736 state_reset (sched_adjust_cost_state
);
6739 emit_insn (gen_ib ());
6740 sched_ib
.insn
= get_insns ();
6744 /* Scheduling pass is now finished. Free/reset static variables. */
6746 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6747 int verbose ATTRIBUTE_UNUSED
)
6749 sched_ib
.insn
= NULL
;
6751 free (sched_adjust_cost_state
);
6752 sched_adjust_cost_state
= NULL
;
6754 sched_mem_unit_code
= 0;
6756 free (sched_ib
.records
.adjust
);
6757 sched_ib
.records
.adjust
= NULL
;
6758 sched_ib
.records
.n_insns
= 0;
6762 /* Implementation of targetm.sched.init () hook.
6763 It is invoked each time scheduler starts on the new block (basic block or
6764 extended basic block). */
6766 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6767 int sched_verbose ATTRIBUTE_UNUSED
,
6768 int n_insns ATTRIBUTE_UNUSED
)
6770 switch (m68k_sched_cpu
)
6778 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6780 memset (sched_ib
.records
.adjust
, 0,
6781 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6782 sched_ib
.records
.adjust_index
= 0;
6786 gcc_assert (!sched_ib
.enabled_p
);
6794 if (sched_ib
.enabled_p
)
6795 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6796 the first cycle. Workaround that. */
6797 sched_ib
.filled
= -2;
6800 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6801 It is invoked just before current cycle finishes and is used here
6802 to track if instruction buffer got its two words this cycle. */
6804 m68k_sched_dfa_pre_advance_cycle (void)
6806 if (!sched_ib
.enabled_p
)
6809 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6811 sched_ib
.filled
+= 2;
6813 if (sched_ib
.filled
> sched_ib
.size
)
6814 sched_ib
.filled
= sched_ib
.size
;
6818 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6819 It is invoked just after new cycle begins and is used here
6820 to setup number of filled words in the instruction buffer so that
6821 instructions which won't have all their words prefetched would be
6822 stalled for a cycle. */
6824 m68k_sched_dfa_post_advance_cycle (void)
6828 if (!sched_ib
.enabled_p
)
6831 /* Setup number of prefetched instruction words in the instruction
6833 i
= max_insn_size
- sched_ib
.filled
;
6837 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6838 /* Pick up scheduler state. */
6843 /* Return X or Y (depending on OPX_P) operand of INSN,
6844 if it is an integer register, or NULL overwise. */
6846 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6852 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6854 op
= sched_get_operand (insn
, true);
6855 gcc_assert (op
!= NULL
);
6857 if (!reload_completed
&& !REG_P (op
))
6863 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6865 op
= sched_get_operand (insn
, false);
6866 gcc_assert (op
!= NULL
);
6868 if (!reload_completed
&& !REG_P (op
))
6876 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6879 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6881 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6892 /* Return X or Y (depending on OPX_P) operand of INSN,
6893 if it is a MEM, or NULL overwise. */
6895 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6915 if (opy_p
&& sched_mem_operand_p (insn
, false))
6916 return sched_get_operand (insn
, false);
6918 if (opx_p
&& sched_mem_operand_p (insn
, true))
6919 return sched_get_operand (insn
, true);
6925 /* Return non-zero if PRO modifies register used as part of
6928 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6933 pro_x
= sched_get_reg_operand (pro
, true);
6937 con_mem_read
= sched_get_mem_operand (con
, true, false);
6938 gcc_assert (con_mem_read
!= NULL
);
6940 if (reg_mentioned_p (pro_x
, con_mem_read
))
6946 /* Helper function for m68k_sched_indexed_address_bypass_p.
6947 if PRO modifies register used as index in CON,
6948 return scale of indexed memory access in CON. Return zero overwise. */
6950 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6954 struct m68k_address address
;
6956 reg
= sched_get_reg_operand (pro
, true);
6960 mem
= sched_get_mem_operand (con
, true, false);
6961 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6963 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6967 if (REGNO (reg
) == REGNO (address
.index
))
6969 gcc_assert (address
.scale
!= 0);
6970 return address
.scale
;
6976 /* Return non-zero if PRO modifies register used
6977 as index with scale 2 or 4 in CON. */
6979 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6981 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6982 && sched_cfv4_bypass_data
.con
== NULL
6983 && sched_cfv4_bypass_data
.scale
== 0);
6985 switch (sched_get_indexed_address_scale (pro
, con
))
6988 /* We can't have a variable latency bypass, so
6989 remember to adjust the insn cost in adjust_cost hook. */
6990 sched_cfv4_bypass_data
.pro
= pro
;
6991 sched_cfv4_bypass_data
.con
= con
;
6992 sched_cfv4_bypass_data
.scale
= 1;
7004 /* We generate a two-instructions program at M_TRAMP :
7005 movea.l &CHAIN_VALUE,%a0
7007 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
7010 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
7012 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
7015 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
7017 mem
= adjust_address (m_tramp
, HImode
, 0);
7018 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
7019 mem
= adjust_address (m_tramp
, SImode
, 2);
7020 emit_move_insn (mem
, chain_value
);
7022 mem
= adjust_address (m_tramp
, HImode
, 6);
7023 emit_move_insn (mem
, GEN_INT(0x4EF9));
7024 mem
= adjust_address (m_tramp
, SImode
, 8);
7025 emit_move_insn (mem
, fnaddr
);
7027 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
7030 /* On the 68000, the RTS insn cannot pop anything.
7031 On the 68010, the RTD insn may be used to pop them if the number
7032 of args is fixed, but if the number is variable then the caller
7033 must pop them all. RTD can't be used for library calls now
7034 because the library is compiled with the Unix compiler.
7035 Use of RTD is a selectable option, since it is incompatible with
7036 standard Unix calling sequences. If the option is not selected,
7037 the caller must always pop the args. */
7040 m68k_return_pops_args (tree fundecl
, tree funtype
, poly_int64 size
)
7044 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
7045 && (!stdarg_p (funtype
)))
7046 ? (HOST_WIDE_INT
) size
: 0);
7049 /* Make sure everything's fine if we *don't* have a given processor.
7050 This assumes that putting a register in fixed_regs will keep the
7051 compiler's mitts completely off it. We don't bother to zero it out
7052 of register classes. */
7055 m68k_conditional_register_usage (void)
7059 if (!TARGET_HARD_FLOAT
)
7061 x
= reg_class_contents
[FP_REGS
];
7062 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7063 if (TEST_HARD_REG_BIT (x
, i
))
7064 fixed_regs
[i
] = call_used_regs
[i
] = 1;
7067 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
7071 m68k_init_sync_libfuncs (void)
7073 init_sync_libfuncs (UNITS_PER_WORD
);
7076 /* Implements EPILOGUE_USES. All registers are live on exit from an
7077 interrupt routine. */
7079 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
7081 return (reload_completed
7082 && (m68k_get_function_kind (current_function_decl
)
7083 == m68k_fk_interrupt_handler
));
7087 /* Implement TARGET_C_EXCESS_PRECISION.
7089 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
7090 instructions, we get proper intermediate rounding, otherwise we
7091 get extended precision results. */
7093 static enum flt_eval_method
7094 m68k_excess_precision (enum excess_precision_type type
)
7098 case EXCESS_PRECISION_TYPE_FAST
:
7099 /* The fastest type to promote to will always be the native type,
7100 whether that occurs with implicit excess precision or
7102 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
7103 case EXCESS_PRECISION_TYPE_STANDARD
:
7104 case EXCESS_PRECISION_TYPE_IMPLICIT
:
7105 /* Otherwise, the excess precision we want when we are
7106 in a standards compliant mode, and the implicit precision we
7107 provide can be identical. */
7108 if (TARGET_68040
|| ! TARGET_68881
)
7109 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
7111 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE
;
7115 return FLT_EVAL_METHOD_UNPREDICTABLE
;
7118 /* Implement PUSH_ROUNDING. On the 680x0, sp@- in a byte insn really pushes
7119 a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */
7122 m68k_push_rounding (poly_int64 bytes
)
7124 if (TARGET_COLDFIRE
)
7126 return (bytes
+ 1) & ~1;
7129 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
7132 m68k_promote_function_mode (const_tree type
, machine_mode mode
,
7133 int *punsignedp ATTRIBUTE_UNUSED
,
7134 const_tree fntype ATTRIBUTE_UNUSED
,
7137 /* Promote libcall arguments narrower than int to match the normal C
7138 ABI (for which promotions are handled via
7139 TARGET_PROMOTE_PROTOTYPES). */
7140 if (type
== NULL_TREE
&& !for_return
&& (mode
== QImode
|| mode
== HImode
))
7145 #include "gt-m68k.h"