1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
24 #define IN_TARGET_CODE 1
28 #include "coretypes.h"
38 #include "stringpool.h"
45 #include "diagnostic.h"
46 #include "insn-attr.h"
49 #include "fold-const.h"
51 #include "stor-layout.h"
57 #include "common/common-target.h"
58 #include "langhooks.h"
61 #include "sched-int.h"
63 #include "target-globals.h"
64 #include "tree-pass.h"
69 /* This file should be included last. */
70 #include "target-def.h"
72 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
73 #define UNSPEC_ADDRESS_P(X) \
74 (GET_CODE (X) == UNSPEC \
75 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
76 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
78 /* Extract the symbol or label from UNSPEC wrapper X. */
79 #define UNSPEC_ADDRESS(X) \
82 /* Extract the symbol type from UNSPEC wrapper X. */
83 #define UNSPEC_ADDRESS_TYPE(X) \
84 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
86 /* The maximum distance between the top of the stack frame and the
87 value $sp has when we save and restore registers.
89 The value for normal-mode code must be a SMALL_OPERAND and must
90 preserve the maximum stack alignment. We therefore use a value
91 of 0x7ff0 in this case.
93 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
94 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
96 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
97 up to 0x7f8 bytes and can usually save or restore all the registers
98 that we need to save or restore. (Note that we can only use these
99 instructions for o32, for which the stack alignment is 8 bytes.)
101 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
102 RESTORE are not available. We can then use unextended instructions
103 to save and restore registers, and to allocate and deallocate the top
104 part of the frame. */
105 #define MIPS_MAX_FIRST_STACK_STEP \
106 (!TARGET_COMPRESSION ? 0x7ff0 \
107 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
108 : TARGET_64BIT ? 0x100 : 0x400)
110 /* True if INSN is a mips.md pattern or asm statement. */
111 /* ??? This test exists through the compiler, perhaps it should be
113 #define USEFUL_INSN_P(INSN) \
114 (NONDEBUG_INSN_P (INSN) \
115 && GET_CODE (PATTERN (INSN)) != USE \
116 && GET_CODE (PATTERN (INSN)) != CLOBBER)
118 /* If INSN is a delayed branch sequence, return the first instruction
119 in the sequence, otherwise return INSN itself. */
120 #define SEQ_BEGIN(INSN) \
121 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
122 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
125 /* Likewise for the last instruction in a delayed branch sequence. */
126 #define SEQ_END(INSN) \
127 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
128 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
130 XVECLEN (PATTERN (INSN), 0) - 1)) \
133 /* Execute the following loop body with SUBINSN set to each instruction
134 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
135 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
136 for ((SUBINSN) = SEQ_BEGIN (INSN); \
137 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
138 (SUBINSN) = NEXT_INSN (SUBINSN))
140 /* True if bit BIT is set in VALUE. */
141 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
143 /* Return the opcode for a ptr_mode load of the form:
145 l[wd] DEST, OFFSET(BASE). */
146 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
147 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
152 /* Return the opcode to move register SRC into register DEST. */
153 #define MIPS_MOVE(DEST, SRC) \
154 ((TARGET_64BIT ? 0x2d : 0x21) \
158 /* Return the opcode for:
161 #define MIPS_LUI(DEST, VALUE) \
162 ((0xf << 26) | ((DEST) << 16) | (VALUE))
164 /* Return the opcode to jump to register DEST. When the JR opcode is not
165 available use JALR $0, DEST. */
166 #define MIPS_JR(DEST) \
167 (TARGET_CB_ALWAYS ? ((0x1b << 27) | ((DEST) << 16)) \
168 : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9)))
170 /* Return the opcode for:
172 bal . + (1 + OFFSET) * 4. */
173 #define MIPS_BAL(OFFSET) \
174 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
176 /* Return the usual opcode for a nop. */
179 /* Classifies an address.
182 A natural register + offset address. The register satisfies
183 mips_valid_base_register_p and the offset is a const_arith_operand.
186 A LO_SUM rtx. The first operand is a valid base register and
187 the second operand is a symbolic address.
190 A signed 16-bit constant address.
193 A constant symbolic address. */
194 enum mips_address_type
{
201 /* Classifies an unconditional branch of interest for the P6600. */
203 enum mips_ucbranch_type
205 /* May not even be a branch. */
211 /* Macros to create an enumeration identifier for a function prototype. */
212 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
213 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
214 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
215 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
217 /* Classifies the prototype of a built-in function. */
218 enum mips_function_type
{
219 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
220 #include "config/mips/mips-ftypes.def"
221 #undef DEF_MIPS_FTYPE
225 /* Specifies how a built-in function should be converted into rtl. */
226 enum mips_builtin_type
{
227 /* The function corresponds directly to an .md pattern. The return
228 value is mapped to operand 0 and the arguments are mapped to
229 operands 1 and above. */
232 /* The function corresponds directly to an .md pattern. There is no return
233 value and the arguments are mapped to operands 0 and above. */
234 MIPS_BUILTIN_DIRECT_NO_TARGET
,
236 /* The function corresponds to a comparison instruction followed by
237 a mips_cond_move_tf_ps pattern. The first two arguments are the
238 values to compare and the second two arguments are the vector
239 operands for the movt.ps or movf.ps instruction (in assembly order). */
243 /* The function corresponds to a V2SF comparison instruction. Operand 0
244 of this instruction is the result of the comparison, which has mode
245 CCV2 or CCV4. The function arguments are mapped to operands 1 and
246 above. The function's return value is an SImode boolean that is
247 true under the following conditions:
249 MIPS_BUILTIN_CMP_ANY: one of the registers is true
250 MIPS_BUILTIN_CMP_ALL: all of the registers are true
251 MIPS_BUILTIN_CMP_LOWER: the first register is true
252 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
253 MIPS_BUILTIN_CMP_ANY
,
254 MIPS_BUILTIN_CMP_ALL
,
255 MIPS_BUILTIN_CMP_UPPER
,
256 MIPS_BUILTIN_CMP_LOWER
,
258 /* As above, but the instruction only sets a single $fcc register. */
259 MIPS_BUILTIN_CMP_SINGLE
,
261 /* The function corresponds to an MSA conditional branch instruction
262 combined with a compare instruction. */
263 MIPS_BUILTIN_MSA_TEST_BRANCH
,
265 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
266 MIPS_BUILTIN_BPOSGE32
269 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
270 #define MIPS_FP_CONDITIONS(MACRO) \
288 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
289 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
290 enum mips_fp_condition
{
291 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
293 #undef DECLARE_MIPS_COND
295 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
296 #define STRINGIFY(X) #X
297 static const char *const mips_fp_conditions
[] = {
298 MIPS_FP_CONDITIONS (STRINGIFY
)
302 /* A class used to control a comdat-style stub that we output in each
303 translation unit that needs it. */
304 class mips_one_only_stub
{
306 virtual ~mips_one_only_stub () {}
308 /* Return the name of the stub. */
309 virtual const char *get_name () = 0;
311 /* Output the body of the function to asm_out_file. */
312 virtual void output_body () = 0;
315 /* Tuning information that is automatically derived from other sources
316 (such as the scheduler). */
318 /* The architecture and tuning settings that this structure describes. */
322 /* True if this structure describes MIPS16 settings. */
325 /* True if the structure has been initialized. */
328 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
329 when optimizing for speed. */
330 bool fast_mult_zero_zero_p
;
333 /* Information about a single argument. */
334 struct mips_arg_info
{
335 /* True if the argument is passed in a floating-point register, or
336 would have been if we hadn't run out of registers. */
339 /* The number of words passed in registers, rounded up. */
340 unsigned int reg_words
;
342 /* For EABI, the offset of the first register from GP_ARG_FIRST or
343 FP_ARG_FIRST. For other ABIs, the offset of the first register from
344 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
345 comment for details).
347 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
349 unsigned int reg_offset
;
351 /* The number of words that must be passed on the stack, rounded up. */
352 unsigned int stack_words
;
354 /* The offset from the start of the stack overflow area of the argument's
355 first stack word. Only meaningful when STACK_WORDS is nonzero. */
356 unsigned int stack_offset
;
359 /* Information about an address described by mips_address_type.
365 REG is the base register and OFFSET is the constant offset.
368 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
369 is the type of symbol it references.
372 SYMBOL_TYPE is the type of symbol that the address references. */
373 struct mips_address_info
{
374 enum mips_address_type type
;
377 enum mips_symbol_type symbol_type
;
380 /* One stage in a constant building sequence. These sequences have
384 A = A CODE[1] VALUE[1]
385 A = A CODE[2] VALUE[2]
388 where A is an accumulator, each CODE[i] is a binary rtl operation
389 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
390 struct mips_integer_op
{
392 unsigned HOST_WIDE_INT value
;
395 /* The largest number of operations needed to load an integer constant.
396 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
397 When the lowest bit is clear, we can try, but reject a sequence with
398 an extra SLL at the end. */
399 #define MIPS_MAX_INTEGER_OPS 7
401 /* Information about a MIPS16e SAVE or RESTORE instruction. */
402 struct mips16e_save_restore_info
{
403 /* The number of argument registers saved by a SAVE instruction.
404 0 for RESTORE instructions. */
407 /* Bit X is set if the instruction saves or restores GPR X. */
410 /* The total number of bytes to allocate. */
414 /* Costs of various operations on the different architectures. */
416 struct mips_rtx_cost_data
418 unsigned short fp_add
;
419 unsigned short fp_mult_sf
;
420 unsigned short fp_mult_df
;
421 unsigned short fp_div_sf
;
422 unsigned short fp_div_df
;
423 unsigned short int_mult_si
;
424 unsigned short int_mult_di
;
425 unsigned short int_div_si
;
426 unsigned short int_div_di
;
427 unsigned short branch_cost
;
428 unsigned short memory_latency
;
431 /* Global variables for machine-dependent things. */
433 /* The -G setting, or the configuration's default small-data limit if
434 no -G option is given. */
435 static unsigned int mips_small_data_threshold
;
437 /* The number of file directives written by mips_output_filename. */
438 int num_source_filenames
;
440 /* The name that appeared in the last .file directive written by
441 mips_output_filename, or "" if mips_output_filename hasn't
442 written anything yet. */
443 const char *current_function_file
= "";
445 /* Arrays that map GCC register numbers to debugger register numbers. */
446 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
447 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
449 /* Information about the current function's epilogue, used only while
452 /* A list of queued REG_CFA_RESTORE notes. */
455 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
457 HOST_WIDE_INT cfa_offset
;
459 /* The offset of the CFA from the stack pointer while restoring
461 HOST_WIDE_INT cfa_restore_sp_offset
;
464 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
465 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
466 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
467 struct mips_asm_switch mips_noat
= { "at", 0 };
469 /* True if we're writing out a branch-likely instruction rather than a
471 static bool mips_branch_likely
;
473 /* The current instruction-set architecture. */
474 enum processor mips_arch
;
475 const struct mips_cpu_info
*mips_arch_info
;
477 /* The processor that we should tune the code for. */
478 enum processor mips_tune
;
479 const struct mips_cpu_info
*mips_tune_info
;
481 /* The ISA level associated with mips_arch. */
484 /* The ISA revision level. This is 0 for MIPS I to V and N for
488 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
489 static const struct mips_cpu_info
*mips_isa_option_info
;
491 /* Which cost information to use. */
492 static const struct mips_rtx_cost_data
*mips_cost
;
494 /* The ambient target flags, excluding MASK_MIPS16. */
495 static int mips_base_target_flags
;
497 /* The default compression mode. */
498 unsigned int mips_base_compression_flags
;
500 /* The ambient values of other global variables. */
501 static int mips_base_schedule_insns
; /* flag_schedule_insns */
502 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
503 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
504 static const char *mips_base_align_loops
; /* align_loops */
505 static const char *mips_base_align_jumps
; /* align_jumps */
506 static const char *mips_base_align_functions
; /* align_functions */
508 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
509 static bool mips_hard_regno_mode_ok_p
[MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
511 /* Index C is true if character C is a valid PRINT_OPERAND punctation
513 static bool mips_print_operand_punct
[256];
515 static GTY (()) int mips_output_filename_first_time
= 1;
517 /* mips_split_p[X] is true if symbols of type X can be split by
518 mips_split_symbol. */
519 bool mips_split_p
[NUM_SYMBOL_TYPES
];
521 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
522 can be split by mips_split_symbol. */
523 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
525 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
526 forced into a PC-relative constant pool. */
527 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
529 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
530 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
531 if they are matched by a special .md file pattern. */
532 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
534 /* Likewise for HIGHs. */
535 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
537 /* Target state for MIPS16. */
538 struct target_globals
*mips16_globals
;
540 /* Target state for MICROMIPS. */
541 struct target_globals
*micromips_globals
;
543 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
544 and returned from mips_sched_reorder2. */
545 static int cached_can_issue_more
;
547 /* The stubs for various MIPS16 support functions, if used. */
548 static mips_one_only_stub
*mips16_rdhwr_stub
;
549 static mips_one_only_stub
*mips16_get_fcsr_stub
;
550 static mips_one_only_stub
*mips16_set_fcsr_stub
;
552 /* Index R is the smallest register class that contains register R. */
553 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
554 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
555 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
556 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
557 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
558 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
559 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
560 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
561 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
563 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
564 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
565 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
566 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
567 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
568 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
569 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
570 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
571 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
572 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
573 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
574 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
575 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
576 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
577 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
578 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
579 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
580 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
581 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
582 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
583 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
584 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
585 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
586 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
587 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
588 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
589 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
590 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
591 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
592 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
593 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
594 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
595 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
596 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
597 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
598 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
599 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
600 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
601 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
604 static tree
mips_handle_interrupt_attr (tree
*, tree
, tree
, int, bool *);
605 static tree
mips_handle_use_shadow_register_set_attr (tree
*, tree
, tree
, int,
608 /* The value of TARGET_ATTRIBUTE_TABLE. */
609 static const struct attribute_spec mips_attribute_table
[] = {
610 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
611 affects_type_identity, handler, exclude } */
612 { "long_call", 0, 0, false, true, true, false, NULL
, NULL
},
613 { "short_call", 0, 0, false, true, true, false, NULL
, NULL
},
614 { "far", 0, 0, false, true, true, false, NULL
, NULL
},
615 { "near", 0, 0, false, true, true, false, NULL
, NULL
},
616 /* We would really like to treat "mips16" and "nomips16" as type
617 attributes, but GCC doesn't provide the hooks we need to support
618 the right conversion rules. As declaration attributes, they affect
619 code generation but don't carry other semantics. */
620 { "mips16", 0, 0, true, false, false, false, NULL
, NULL
},
621 { "nomips16", 0, 0, true, false, false, false, NULL
, NULL
},
622 { "micromips", 0, 0, true, false, false, false, NULL
, NULL
},
623 { "nomicromips", 0, 0, true, false, false, false, NULL
, NULL
},
624 { "nocompression", 0, 0, true, false, false, false, NULL
, NULL
},
625 /* Allow functions to be specified as interrupt handlers */
626 { "interrupt", 0, 1, false, true, true, false, mips_handle_interrupt_attr
,
628 { "use_shadow_register_set", 0, 1, false, true, true, false,
629 mips_handle_use_shadow_register_set_attr
, NULL
},
630 { "keep_interrupts_masked", 0, 0, false, true, true, false, NULL
, NULL
},
631 { "use_debug_exception_return", 0, 0, false, true, true, false, NULL
, NULL
},
632 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
635 /* A table describing all the processors GCC knows about; see
636 mips-cpus.def for details. */
637 static const struct mips_cpu_info mips_cpu_info_table
[] = {
638 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
639 { NAME, CPU, ISA, FLAGS },
640 #include "mips-cpus.def"
644 /* Default costs. If these are used for a processor we should look
645 up the actual costs. */
646 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
647 COSTS_N_INSNS (7), /* fp_mult_sf */ \
648 COSTS_N_INSNS (8), /* fp_mult_df */ \
649 COSTS_N_INSNS (23), /* fp_div_sf */ \
650 COSTS_N_INSNS (36), /* fp_div_df */ \
651 COSTS_N_INSNS (10), /* int_mult_si */ \
652 COSTS_N_INSNS (10), /* int_mult_di */ \
653 COSTS_N_INSNS (69), /* int_div_si */ \
654 COSTS_N_INSNS (69), /* int_div_di */ \
655 2, /* branch_cost */ \
656 4 /* memory_latency */
658 /* Floating-point costs for processors without an FPU. Just assume that
659 all floating-point libcalls are very expensive. */
660 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
661 COSTS_N_INSNS (256), /* fp_mult_sf */ \
662 COSTS_N_INSNS (256), /* fp_mult_df */ \
663 COSTS_N_INSNS (256), /* fp_div_sf */ \
664 COSTS_N_INSNS (256) /* fp_div_df */
666 /* Costs to use when optimizing for size. */
667 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
668 COSTS_N_INSNS (1), /* fp_add */
669 COSTS_N_INSNS (1), /* fp_mult_sf */
670 COSTS_N_INSNS (1), /* fp_mult_df */
671 COSTS_N_INSNS (1), /* fp_div_sf */
672 COSTS_N_INSNS (1), /* fp_div_df */
673 COSTS_N_INSNS (1), /* int_mult_si */
674 COSTS_N_INSNS (1), /* int_mult_di */
675 COSTS_N_INSNS (1), /* int_div_si */
676 COSTS_N_INSNS (1), /* int_div_di */
678 4 /* memory_latency */
681 /* Costs to use when optimizing for speed, indexed by processor. */
682 static const struct mips_rtx_cost_data
683 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
685 COSTS_N_INSNS (2), /* fp_add */
686 COSTS_N_INSNS (4), /* fp_mult_sf */
687 COSTS_N_INSNS (5), /* fp_mult_df */
688 COSTS_N_INSNS (12), /* fp_div_sf */
689 COSTS_N_INSNS (19), /* fp_div_df */
690 COSTS_N_INSNS (12), /* int_mult_si */
691 COSTS_N_INSNS (12), /* int_mult_di */
692 COSTS_N_INSNS (35), /* int_div_si */
693 COSTS_N_INSNS (35), /* int_div_di */
695 4 /* memory_latency */
699 COSTS_N_INSNS (6), /* int_mult_si */
700 COSTS_N_INSNS (6), /* int_mult_di */
701 COSTS_N_INSNS (36), /* int_div_si */
702 COSTS_N_INSNS (36), /* int_div_di */
704 4 /* memory_latency */
708 COSTS_N_INSNS (36), /* int_mult_si */
709 COSTS_N_INSNS (36), /* int_mult_di */
710 COSTS_N_INSNS (37), /* int_div_si */
711 COSTS_N_INSNS (37), /* int_div_di */
713 4 /* memory_latency */
717 COSTS_N_INSNS (4), /* int_mult_si */
718 COSTS_N_INSNS (11), /* int_mult_di */
719 COSTS_N_INSNS (36), /* int_div_si */
720 COSTS_N_INSNS (68), /* int_div_di */
722 4 /* memory_latency */
725 COSTS_N_INSNS (4), /* fp_add */
726 COSTS_N_INSNS (4), /* fp_mult_sf */
727 COSTS_N_INSNS (5), /* fp_mult_df */
728 COSTS_N_INSNS (17), /* fp_div_sf */
729 COSTS_N_INSNS (32), /* fp_div_df */
730 COSTS_N_INSNS (4), /* int_mult_si */
731 COSTS_N_INSNS (11), /* int_mult_di */
732 COSTS_N_INSNS (36), /* int_div_si */
733 COSTS_N_INSNS (68), /* int_div_di */
735 4 /* memory_latency */
738 COSTS_N_INSNS (4), /* fp_add */
739 COSTS_N_INSNS (4), /* fp_mult_sf */
740 COSTS_N_INSNS (5), /* fp_mult_df */
741 COSTS_N_INSNS (17), /* fp_div_sf */
742 COSTS_N_INSNS (32), /* fp_div_df */
743 COSTS_N_INSNS (4), /* int_mult_si */
744 COSTS_N_INSNS (7), /* int_mult_di */
745 COSTS_N_INSNS (42), /* int_div_si */
746 COSTS_N_INSNS (72), /* int_div_di */
748 4 /* memory_latency */
752 COSTS_N_INSNS (5), /* int_mult_si */
753 COSTS_N_INSNS (5), /* int_mult_di */
754 COSTS_N_INSNS (41), /* int_div_si */
755 COSTS_N_INSNS (41), /* int_div_di */
757 4 /* memory_latency */
760 COSTS_N_INSNS (8), /* fp_add */
761 COSTS_N_INSNS (8), /* fp_mult_sf */
762 COSTS_N_INSNS (10), /* fp_mult_df */
763 COSTS_N_INSNS (34), /* fp_div_sf */
764 COSTS_N_INSNS (64), /* fp_div_df */
765 COSTS_N_INSNS (5), /* int_mult_si */
766 COSTS_N_INSNS (5), /* int_mult_di */
767 COSTS_N_INSNS (41), /* int_div_si */
768 COSTS_N_INSNS (41), /* int_div_di */
770 4 /* memory_latency */
773 COSTS_N_INSNS (4), /* fp_add */
774 COSTS_N_INSNS (4), /* fp_mult_sf */
775 COSTS_N_INSNS (5), /* fp_mult_df */
776 COSTS_N_INSNS (17), /* fp_div_sf */
777 COSTS_N_INSNS (32), /* fp_div_df */
778 COSTS_N_INSNS (5), /* int_mult_si */
779 COSTS_N_INSNS (5), /* int_mult_di */
780 COSTS_N_INSNS (41), /* int_div_si */
781 COSTS_N_INSNS (41), /* int_div_di */
783 4 /* memory_latency */
787 COSTS_N_INSNS (5), /* int_mult_si */
788 COSTS_N_INSNS (5), /* int_mult_di */
789 COSTS_N_INSNS (41), /* int_div_si */
790 COSTS_N_INSNS (41), /* int_div_di */
792 4 /* memory_latency */
795 COSTS_N_INSNS (8), /* fp_add */
796 COSTS_N_INSNS (8), /* fp_mult_sf */
797 COSTS_N_INSNS (10), /* fp_mult_df */
798 COSTS_N_INSNS (34), /* fp_div_sf */
799 COSTS_N_INSNS (64), /* fp_div_df */
800 COSTS_N_INSNS (5), /* int_mult_si */
801 COSTS_N_INSNS (5), /* int_mult_di */
802 COSTS_N_INSNS (41), /* int_div_si */
803 COSTS_N_INSNS (41), /* int_div_di */
805 4 /* memory_latency */
808 COSTS_N_INSNS (4), /* fp_add */
809 COSTS_N_INSNS (4), /* fp_mult_sf */
810 COSTS_N_INSNS (5), /* fp_mult_df */
811 COSTS_N_INSNS (17), /* fp_div_sf */
812 COSTS_N_INSNS (32), /* fp_div_df */
813 COSTS_N_INSNS (5), /* int_mult_si */
814 COSTS_N_INSNS (5), /* int_mult_di */
815 COSTS_N_INSNS (41), /* int_div_si */
816 COSTS_N_INSNS (41), /* int_div_di */
818 4 /* memory_latency */
821 COSTS_N_INSNS (6), /* fp_add */
822 COSTS_N_INSNS (6), /* fp_mult_sf */
823 COSTS_N_INSNS (7), /* fp_mult_df */
824 COSTS_N_INSNS (25), /* fp_div_sf */
825 COSTS_N_INSNS (48), /* fp_div_df */
826 COSTS_N_INSNS (5), /* int_mult_si */
827 COSTS_N_INSNS (5), /* int_mult_di */
828 COSTS_N_INSNS (41), /* int_div_si */
829 COSTS_N_INSNS (41), /* int_div_di */
831 4 /* memory_latency */
839 { /* Loongson gs464. */
842 { /* Loongson gs464e. */
845 { /* Loongson gs264e. */
854 COSTS_N_INSNS (5), /* int_mult_si */
855 COSTS_N_INSNS (5), /* int_mult_di */
856 COSTS_N_INSNS (72), /* int_div_si */
857 COSTS_N_INSNS (72), /* int_div_di */
859 4 /* memory_latency */
864 COSTS_N_INSNS (6), /* int_mult_si */
865 COSTS_N_INSNS (6), /* int_mult_di */
866 COSTS_N_INSNS (18), /* int_div_si */
867 COSTS_N_INSNS (35), /* int_div_di */
869 4 /* memory_latency */
873 COSTS_N_INSNS (6), /* fp_add */
874 COSTS_N_INSNS (6), /* fp_mult_sf */
875 COSTS_N_INSNS (7), /* fp_mult_df */
876 COSTS_N_INSNS (25), /* fp_div_sf */
877 COSTS_N_INSNS (48), /* fp_div_df */
878 COSTS_N_INSNS (6), /* int_mult_si */
879 COSTS_N_INSNS (6), /* int_mult_di */
880 COSTS_N_INSNS (18), /* int_div_si */
881 COSTS_N_INSNS (35), /* int_div_di */
883 4 /* memory_latency */
886 COSTS_N_INSNS (2), /* fp_add */
887 COSTS_N_INSNS (4), /* fp_mult_sf */
888 COSTS_N_INSNS (5), /* fp_mult_df */
889 COSTS_N_INSNS (12), /* fp_div_sf */
890 COSTS_N_INSNS (19), /* fp_div_df */
891 COSTS_N_INSNS (2), /* int_mult_si */
892 COSTS_N_INSNS (2), /* int_mult_di */
893 COSTS_N_INSNS (35), /* int_div_si */
894 COSTS_N_INSNS (35), /* int_div_di */
896 4 /* memory_latency */
899 COSTS_N_INSNS (3), /* fp_add */
900 COSTS_N_INSNS (5), /* fp_mult_sf */
901 COSTS_N_INSNS (6), /* fp_mult_df */
902 COSTS_N_INSNS (15), /* fp_div_sf */
903 COSTS_N_INSNS (16), /* fp_div_df */
904 COSTS_N_INSNS (17), /* int_mult_si */
905 COSTS_N_INSNS (17), /* int_mult_di */
906 COSTS_N_INSNS (38), /* int_div_si */
907 COSTS_N_INSNS (38), /* int_div_di */
909 6 /* memory_latency */
912 COSTS_N_INSNS (6), /* fp_add */
913 COSTS_N_INSNS (7), /* fp_mult_sf */
914 COSTS_N_INSNS (8), /* fp_mult_df */
915 COSTS_N_INSNS (23), /* fp_div_sf */
916 COSTS_N_INSNS (36), /* fp_div_df */
917 COSTS_N_INSNS (10), /* int_mult_si */
918 COSTS_N_INSNS (10), /* int_mult_di */
919 COSTS_N_INSNS (69), /* int_div_si */
920 COSTS_N_INSNS (69), /* int_div_di */
922 6 /* memory_latency */
934 /* The only costs that appear to be updated here are
935 integer multiplication. */
937 COSTS_N_INSNS (4), /* int_mult_si */
938 COSTS_N_INSNS (6), /* int_mult_di */
939 COSTS_N_INSNS (69), /* int_div_si */
940 COSTS_N_INSNS (69), /* int_div_di */
942 4 /* memory_latency */
957 COSTS_N_INSNS (6), /* fp_add */
958 COSTS_N_INSNS (4), /* fp_mult_sf */
959 COSTS_N_INSNS (5), /* fp_mult_df */
960 COSTS_N_INSNS (23), /* fp_div_sf */
961 COSTS_N_INSNS (36), /* fp_div_df */
962 COSTS_N_INSNS (5), /* int_mult_si */
963 COSTS_N_INSNS (5), /* int_mult_di */
964 COSTS_N_INSNS (36), /* int_div_si */
965 COSTS_N_INSNS (36), /* int_div_di */
967 4 /* memory_latency */
970 COSTS_N_INSNS (6), /* fp_add */
971 COSTS_N_INSNS (5), /* fp_mult_sf */
972 COSTS_N_INSNS (6), /* fp_mult_df */
973 COSTS_N_INSNS (30), /* fp_div_sf */
974 COSTS_N_INSNS (59), /* fp_div_df */
975 COSTS_N_INSNS (3), /* int_mult_si */
976 COSTS_N_INSNS (4), /* int_mult_di */
977 COSTS_N_INSNS (42), /* int_div_si */
978 COSTS_N_INSNS (74), /* int_div_di */
980 4 /* memory_latency */
983 COSTS_N_INSNS (6), /* fp_add */
984 COSTS_N_INSNS (5), /* fp_mult_sf */
985 COSTS_N_INSNS (6), /* fp_mult_df */
986 COSTS_N_INSNS (30), /* fp_div_sf */
987 COSTS_N_INSNS (59), /* fp_div_df */
988 COSTS_N_INSNS (5), /* int_mult_si */
989 COSTS_N_INSNS (9), /* int_mult_di */
990 COSTS_N_INSNS (42), /* int_div_si */
991 COSTS_N_INSNS (74), /* int_div_di */
993 4 /* memory_latency */
996 COSTS_N_INSNS (4), /* fp_add */
997 COSTS_N_INSNS (4), /* fp_mult_sf */
998 COSTS_N_INSNS (256), /* fp_mult_df */
999 COSTS_N_INSNS (8), /* fp_div_sf */
1000 COSTS_N_INSNS (256), /* fp_div_df */
1001 COSTS_N_INSNS (4), /* int_mult_si */
1002 COSTS_N_INSNS (256), /* int_mult_di */
1003 COSTS_N_INSNS (37), /* int_div_si */
1004 COSTS_N_INSNS (256), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 /* The only costs that are changed here are
1010 integer multiplication. */
1011 COSTS_N_INSNS (6), /* fp_add */
1012 COSTS_N_INSNS (7), /* fp_mult_sf */
1013 COSTS_N_INSNS (8), /* fp_mult_df */
1014 COSTS_N_INSNS (23), /* fp_div_sf */
1015 COSTS_N_INSNS (36), /* fp_div_df */
1016 COSTS_N_INSNS (5), /* int_mult_si */
1017 COSTS_N_INSNS (9), /* int_mult_di */
1018 COSTS_N_INSNS (69), /* int_div_si */
1019 COSTS_N_INSNS (69), /* int_div_di */
1020 1, /* branch_cost */
1021 4 /* memory_latency */
1027 /* The only costs that are changed here are
1028 integer multiplication. */
1029 COSTS_N_INSNS (6), /* fp_add */
1030 COSTS_N_INSNS (7), /* fp_mult_sf */
1031 COSTS_N_INSNS (8), /* fp_mult_df */
1032 COSTS_N_INSNS (23), /* fp_div_sf */
1033 COSTS_N_INSNS (36), /* fp_div_df */
1034 COSTS_N_INSNS (3), /* int_mult_si */
1035 COSTS_N_INSNS (8), /* int_mult_di */
1036 COSTS_N_INSNS (69), /* int_div_si */
1037 COSTS_N_INSNS (69), /* int_div_di */
1038 1, /* branch_cost */
1039 4 /* memory_latency */
1042 COSTS_N_INSNS (2), /* fp_add */
1043 COSTS_N_INSNS (2), /* fp_mult_sf */
1044 COSTS_N_INSNS (2), /* fp_mult_df */
1045 COSTS_N_INSNS (12), /* fp_div_sf */
1046 COSTS_N_INSNS (19), /* fp_div_df */
1047 COSTS_N_INSNS (5), /* int_mult_si */
1048 COSTS_N_INSNS (9), /* int_mult_di */
1049 COSTS_N_INSNS (34), /* int_div_si */
1050 COSTS_N_INSNS (66), /* int_div_di */
1051 1, /* branch_cost */
1052 4 /* memory_latency */
1055 /* These costs are the same as the SB-1A below. */
1056 COSTS_N_INSNS (4), /* fp_add */
1057 COSTS_N_INSNS (4), /* fp_mult_sf */
1058 COSTS_N_INSNS (4), /* fp_mult_df */
1059 COSTS_N_INSNS (24), /* fp_div_sf */
1060 COSTS_N_INSNS (32), /* fp_div_df */
1061 COSTS_N_INSNS (3), /* int_mult_si */
1062 COSTS_N_INSNS (4), /* int_mult_di */
1063 COSTS_N_INSNS (36), /* int_div_si */
1064 COSTS_N_INSNS (68), /* int_div_di */
1065 1, /* branch_cost */
1066 4 /* memory_latency */
1069 /* These costs are the same as the SB-1 above. */
1070 COSTS_N_INSNS (4), /* fp_add */
1071 COSTS_N_INSNS (4), /* fp_mult_sf */
1072 COSTS_N_INSNS (4), /* fp_mult_df */
1073 COSTS_N_INSNS (24), /* fp_div_sf */
1074 COSTS_N_INSNS (32), /* fp_div_df */
1075 COSTS_N_INSNS (3), /* int_mult_si */
1076 COSTS_N_INSNS (4), /* int_mult_di */
1077 COSTS_N_INSNS (36), /* int_div_si */
1078 COSTS_N_INSNS (68), /* int_div_di */
1079 1, /* branch_cost */
1080 4 /* memory_latency */
1087 COSTS_N_INSNS (8), /* int_mult_si */
1088 COSTS_N_INSNS (8), /* int_mult_di */
1089 COSTS_N_INSNS (72), /* int_div_si */
1090 COSTS_N_INSNS (72), /* int_div_di */
1091 1, /* branch_cost */
1092 4 /* memory_latency */
1095 /* These costs are the same as 5KF above. */
1096 COSTS_N_INSNS (4), /* fp_add */
1097 COSTS_N_INSNS (4), /* fp_mult_sf */
1098 COSTS_N_INSNS (5), /* fp_mult_df */
1099 COSTS_N_INSNS (17), /* fp_div_sf */
1100 COSTS_N_INSNS (32), /* fp_div_df */
1101 COSTS_N_INSNS (4), /* int_mult_si */
1102 COSTS_N_INSNS (11), /* int_mult_di */
1103 COSTS_N_INSNS (36), /* int_div_si */
1104 COSTS_N_INSNS (68), /* int_div_di */
1105 1, /* branch_cost */
1106 4 /* memory_latency */
1109 COSTS_N_INSNS (4), /* fp_add */
1110 COSTS_N_INSNS (5), /* fp_mult_sf */
1111 COSTS_N_INSNS (5), /* fp_mult_df */
1112 COSTS_N_INSNS (17), /* fp_div_sf */
1113 COSTS_N_INSNS (17), /* fp_div_df */
1114 COSTS_N_INSNS (5), /* int_mult_si */
1115 COSTS_N_INSNS (5), /* int_mult_di */
1116 COSTS_N_INSNS (8), /* int_div_si */
1117 COSTS_N_INSNS (8), /* int_div_di */
1118 2, /* branch_cost */
1119 4 /* memory_latency */
1122 COSTS_N_INSNS (4), /* fp_add */
1123 COSTS_N_INSNS (4), /* fp_mult_sf */
1124 COSTS_N_INSNS (5), /* fp_mult_df */
1125 COSTS_N_INSNS (17), /* fp_div_sf */
1126 COSTS_N_INSNS (32), /* fp_div_df */
1127 COSTS_N_INSNS (5), /* int_mult_si */
1128 COSTS_N_INSNS (5), /* int_mult_di */
1129 COSTS_N_INSNS (34), /* int_div_si */
1130 COSTS_N_INSNS (68), /* int_div_di */
1131 1, /* branch_cost */
1132 4 /* memory_latency */
1135 COSTS_N_INSNS (4), /* fp_add */
1136 COSTS_N_INSNS (5), /* fp_mult_sf */
1137 COSTS_N_INSNS (5), /* fp_mult_df */
1138 COSTS_N_INSNS (32), /* fp_div_sf */
1139 COSTS_N_INSNS (32), /* fp_div_df */
1140 COSTS_N_INSNS (5), /* int_mult_si */
1141 COSTS_N_INSNS (5), /* int_mult_di */
1142 COSTS_N_INSNS (36), /* int_div_si */
1143 COSTS_N_INSNS (36), /* int_div_di */
1144 2, /* branch_cost */
1145 4 /* memory_latency */
1148 COSTS_N_INSNS (4), /* fp_add */
1149 COSTS_N_INSNS (5), /* fp_mult_sf */
1150 COSTS_N_INSNS (5), /* fp_mult_df */
1151 COSTS_N_INSNS (17), /* fp_div_sf */
1152 COSTS_N_INSNS (17), /* fp_div_df */
1153 COSTS_N_INSNS (5), /* int_mult_si */
1154 COSTS_N_INSNS (5), /* int_mult_di */
1155 COSTS_N_INSNS (8), /* int_div_si */
1156 COSTS_N_INSNS (8), /* int_div_di */
1157 2, /* branch_cost */
1158 4 /* memory_latency */
1162 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1163 static int mips_register_move_cost (machine_mode
, reg_class_t
,
1165 static unsigned int mips_function_arg_boundary (machine_mode
, const_tree
);
1166 static rtx
mips_gen_const_int_vector_shuffle (machine_mode
, int);
1168 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1169 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1170 static GTY (()) hash_map
<nofree_string_hash
, bool> *mflip_mips16_htab
;
1172 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1173 mode, false if it should next add an attribute for the opposite mode. */
1174 static GTY(()) bool mips16_flipper
;
1176 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1177 for -mflip-mips16. Return true if it should use "mips16" and false if
1178 it should use "nomips16". */
1181 mflip_mips16_use_mips16_p (tree decl
)
1184 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1186 /* Use the opposite of the command-line setting for anonymous decls. */
1187 if (!DECL_NAME (decl
))
1188 return !base_is_mips16
;
1190 if (!mflip_mips16_htab
)
1191 mflip_mips16_htab
= hash_map
<nofree_string_hash
, bool>::create_ggc (37);
1193 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1196 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1199 mips16_flipper
= !mips16_flipper
;
1200 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1205 /* Predicates to test for presence of "near"/"short_call" and "far"/"long_call"
1206 attributes on the given TYPE. */
1209 mips_near_type_p (const_tree type
)
1211 return (lookup_attribute ("short_call", TYPE_ATTRIBUTES (type
)) != NULL
1212 || lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
);
1216 mips_far_type_p (const_tree type
)
1218 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1219 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1223 /* Check if the interrupt attribute is set for a function. */
1226 mips_interrupt_type_p (tree type
)
1228 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1231 /* Return the mask for the "interrupt" attribute. */
1233 static enum mips_int_mask
1234 mips_interrupt_mask (tree type
)
1236 tree attr
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
));
1240 /* For missing attributes or no arguments then return 'eic' as a safe
1243 return INT_MASK_EIC
;
1245 args
= TREE_VALUE (attr
);
1248 return INT_MASK_EIC
;
1250 cst
= TREE_VALUE (args
);
1252 if (strcmp (TREE_STRING_POINTER (cst
), "eic") == 0)
1253 return INT_MASK_EIC
;
1255 /* The validation code in mips_handle_interrupt_attr guarantees that the
1256 argument is now in the form:
1257 vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5). */
1258 str
= TREE_STRING_POINTER (cst
);
1260 gcc_assert (strlen (str
) == strlen ("vector=sw0"));
1263 return (enum mips_int_mask
) (INT_MASK_SW0
+ (str
[9] - '0'));
1265 return (enum mips_int_mask
) (INT_MASK_HW0
+ (str
[9] - '0'));
1268 /* Return the mips_shadow_set if the "use_shadow_register_set" attribute is
1269 set for a function. */
1271 static enum mips_shadow_set
1272 mips_use_shadow_register_set (tree type
)
1274 tree attr
= lookup_attribute ("use_shadow_register_set",
1275 TYPE_ATTRIBUTES (type
));
1278 /* The validation code in mips_handle_use_shadow_register_set_attr guarantees
1279 that if an argument is present then it means: Assume the shadow register
1280 set has a valid stack pointer in it. */
1282 return SHADOW_SET_NO
;
1284 args
= TREE_VALUE (attr
);
1287 return SHADOW_SET_YES
;
1289 return SHADOW_SET_INTSTACK
;
1292 /* Check if the attribute to keep interrupts masked is set for a function. */
1295 mips_keep_interrupts_masked_p (tree type
)
1297 return lookup_attribute ("keep_interrupts_masked",
1298 TYPE_ATTRIBUTES (type
)) != NULL
;
1301 /* Check if the attribute to use debug exception return is set for
1305 mips_use_debug_exception_return_p (tree type
)
1307 return lookup_attribute ("use_debug_exception_return",
1308 TYPE_ATTRIBUTES (type
)) != NULL
;
1311 /* Return the set of compression modes that are explicitly required
1312 by the attributes in ATTRIBUTES. */
1315 mips_get_compress_on_flags (tree attributes
)
1317 unsigned int flags
= 0;
1319 if (lookup_attribute ("mips16", attributes
) != NULL
)
1320 flags
|= MASK_MIPS16
;
1322 if (lookup_attribute ("micromips", attributes
) != NULL
)
1323 flags
|= MASK_MICROMIPS
;
1328 /* Return the set of compression modes that are explicitly forbidden
1329 by the attributes in ATTRIBUTES. */
1332 mips_get_compress_off_flags (tree attributes
)
1334 unsigned int flags
= 0;
1336 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1337 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1339 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1340 flags
|= MASK_MIPS16
;
1342 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1343 flags
|= MASK_MICROMIPS
;
1348 /* Return the compression mode that should be used for function DECL.
1349 Return the ambient setting if DECL is null. */
1352 mips_get_compress_mode (tree decl
)
1354 unsigned int flags
, force_on
;
1356 flags
= mips_base_compression_flags
;
1359 /* Nested functions must use the same frame pointer as their
1360 parent and must therefore use the same ISA mode. */
1361 tree parent
= decl_function_context (decl
);
1364 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1367 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1372 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1376 mips_get_compress_on_name (unsigned int flags
)
1378 if (flags
== MASK_MIPS16
)
1383 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1387 mips_get_compress_off_name (unsigned int flags
)
1389 if (flags
== MASK_MIPS16
)
1391 if (flags
== MASK_MICROMIPS
)
1392 return "nomicromips";
1393 return "nocompression";
1396 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1399 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1401 /* Disallow mixed near/far attributes. */
1402 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1404 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1409 /* Implement TARGET_INSERT_ATTRIBUTES. */
1412 mips_insert_attributes (tree decl
, tree
*attributes
)
1415 unsigned int compression_flags
, nocompression_flags
;
1417 /* Check for "mips16" and "nomips16" attributes. */
1418 compression_flags
= mips_get_compress_on_flags (*attributes
);
1419 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1421 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1423 if (nocompression_flags
)
1424 error ("%qs attribute only applies to functions",
1425 mips_get_compress_off_name (nocompression_flags
));
1427 if (compression_flags
)
1428 error ("%qs attribute only applies to functions",
1429 mips_get_compress_on_name (nocompression_flags
));
1433 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1434 nocompression_flags
|=
1435 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1437 if (compression_flags
&& nocompression_flags
)
1438 error ("%qE cannot have both %qs and %qs attributes",
1439 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1440 mips_get_compress_off_name (nocompression_flags
));
1442 if (compression_flags
& MASK_MIPS16
1443 && compression_flags
& MASK_MICROMIPS
)
1444 error ("%qE cannot have both %qs and %qs attributes",
1445 DECL_NAME (decl
), "mips16", "micromips");
1447 if (TARGET_FLIP_MIPS16
1448 && !DECL_ARTIFICIAL (decl
)
1449 && compression_flags
== 0
1450 && nocompression_flags
== 0)
1452 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1453 "mips16" attribute, arbitrarily pick one. We must pick the same
1454 setting for duplicate declarations of a function. */
1455 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1456 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1457 name
= "nomicromips";
1458 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1463 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1466 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1470 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1471 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1473 error ("%qE redeclared with conflicting %qs attributes",
1474 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1476 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1477 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1479 error ("%qE redeclared with conflicting %qs attributes",
1480 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1482 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1483 DECL_ATTRIBUTES (newdecl
));
1486 /* Implement TARGET_CAN_INLINE_P. */
1489 mips_can_inline_p (tree caller
, tree callee
)
1491 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1493 return default_target_can_inline_p (caller
, callee
);
1496 /* Handle an "interrupt" attribute with an optional argument. */
1499 mips_handle_interrupt_attr (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
1500 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1502 /* Check for an argument. */
1503 if (is_attribute_p ("interrupt", name
) && args
!= NULL
)
1507 cst
= TREE_VALUE (args
);
1508 if (TREE_CODE (cst
) != STRING_CST
)
1510 warning (OPT_Wattributes
,
1511 "%qE attribute requires a string argument",
1513 *no_add_attrs
= true;
1515 else if (strcmp (TREE_STRING_POINTER (cst
), "eic") != 0
1516 && strncmp (TREE_STRING_POINTER (cst
), "vector=", 7) != 0)
1518 warning (OPT_Wattributes
,
1519 "argument to %qE attribute is neither eic, nor "
1520 "vector=<line>", name
);
1521 *no_add_attrs
= true;
1523 else if (strncmp (TREE_STRING_POINTER (cst
), "vector=", 7) == 0)
1525 const char *arg
= TREE_STRING_POINTER (cst
) + 7;
1527 /* Acceptable names are: sw0,sw1,hw0,hw1,hw2,hw3,hw4,hw5. */
1528 if (strlen (arg
) != 3
1529 || (arg
[0] != 's' && arg
[0] != 'h')
1531 || (arg
[0] == 's' && arg
[2] != '0' && arg
[2] != '1')
1532 || (arg
[0] == 'h' && (arg
[2] < '0' || arg
[2] > '5')))
1534 warning (OPT_Wattributes
,
1535 "interrupt vector to %qE attribute is not "
1536 "vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)",
1538 *no_add_attrs
= true;
1548 /* Handle a "use_shadow_register_set" attribute with an optional argument. */
1551 mips_handle_use_shadow_register_set_attr (tree
*node ATTRIBUTE_UNUSED
,
1552 tree name
, tree args
,
1553 int flags ATTRIBUTE_UNUSED
,
1556 /* Check for an argument. */
1557 if (is_attribute_p ("use_shadow_register_set", name
) && args
!= NULL
)
1561 cst
= TREE_VALUE (args
);
1562 if (TREE_CODE (cst
) != STRING_CST
)
1564 warning (OPT_Wattributes
,
1565 "%qE attribute requires a string argument",
1567 *no_add_attrs
= true;
1569 else if (strcmp (TREE_STRING_POINTER (cst
), "intstack") != 0)
1571 warning (OPT_Wattributes
,
1572 "argument to %qE attribute is not intstack", name
);
1573 *no_add_attrs
= true;
1582 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1583 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1586 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1588 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1590 *base_ptr
= XEXP (x
, 0);
1591 *offset_ptr
= INTVAL (XEXP (x
, 1));
1600 static unsigned int mips_build_integer (struct mips_integer_op
*,
1601 unsigned HOST_WIDE_INT
);
1603 /* A subroutine of mips_build_integer, with the same interface.
1604 Assume that the final action in the sequence should be a left shift. */
1607 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1609 unsigned int i
, shift
;
1611 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1612 since signed numbers are easier to load than unsigned ones. */
1614 while ((value
& 1) == 0)
1615 value
/= 2, shift
++;
1617 i
= mips_build_integer (codes
, value
);
1618 codes
[i
].code
= ASHIFT
;
1619 codes
[i
].value
= shift
;
1623 /* As for mips_build_shift, but assume that the final action will be
1624 an IOR or PLUS operation. */
1627 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1629 unsigned HOST_WIDE_INT high
;
1632 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1633 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1635 /* The constant is too complex to load with a simple LUI/ORI pair,
1636 so we want to give the recursive call as many trailing zeros as
1637 possible. In this case, we know bit 16 is set and that the
1638 low 16 bits form a negative number. If we subtract that number
1639 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1640 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1641 codes
[i
].code
= PLUS
;
1642 codes
[i
].value
= CONST_LOW_PART (value
);
1646 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1647 bits gives a value with at least 17 trailing zeros. */
1648 i
= mips_build_integer (codes
, high
);
1649 codes
[i
].code
= IOR
;
1650 codes
[i
].value
= value
& 0xffff;
1655 /* Fill CODES with a sequence of rtl operations to load VALUE.
1656 Return the number of operations needed. */
1659 mips_build_integer (struct mips_integer_op
*codes
,
1660 unsigned HOST_WIDE_INT value
)
1662 if (SMALL_OPERAND (value
)
1663 || SMALL_OPERAND_UNSIGNED (value
)
1664 || LUI_OPERAND (value
))
1666 /* The value can be loaded with a single instruction. */
1667 codes
[0].code
= UNKNOWN
;
1668 codes
[0].value
= value
;
1671 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1673 /* Either the constant is a simple LUI/ORI combination or its
1674 lowest bit is set. We don't want to shift in this case. */
1675 return mips_build_lower (codes
, value
);
1677 else if ((value
& 0xffff) == 0)
1679 /* The constant will need at least three actions. The lowest
1680 16 bits are clear, so the final action will be a shift. */
1681 return mips_build_shift (codes
, value
);
1685 /* The final action could be a shift, add or inclusive OR.
1686 Rather than use a complex condition to select the best
1687 approach, try both mips_build_shift and mips_build_lower
1688 and pick the one that gives the shortest sequence.
1689 Note that this case is only used once per constant. */
1690 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1691 unsigned int cost
, alt_cost
;
1693 cost
= mips_build_shift (codes
, value
);
1694 alt_cost
= mips_build_lower (alt_codes
, value
);
1695 if (alt_cost
< cost
)
1697 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1704 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1707 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1709 return mips_const_insns (x
) > 0;
1712 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1715 mips16_stub_function (const char *name
)
1719 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1720 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1724 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1725 support function. */
1728 mips16_stub_call_address (mips_one_only_stub
*stub
)
1730 rtx fn
= mips16_stub_function (stub
->get_name ());
1731 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1732 if (!call_insn_operand (fn
, VOIDmode
))
1733 fn
= force_reg (Pmode
, fn
);
1737 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1739 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1741 virtual const char *get_name ();
1742 virtual void output_body ();
1746 mips16_rdhwr_one_only_stub::get_name ()
1748 return "__mips16_rdhwr";
1752 mips16_rdhwr_one_only_stub::output_body ()
1754 fprintf (asm_out_file
,
1756 "\t.set\tmips32r2\n"
1757 "\t.set\tnoreorder\n"
1763 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1764 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1766 virtual const char *get_name ();
1767 virtual void output_body ();
1771 mips16_get_fcsr_one_only_stub::get_name ()
1773 return "__mips16_get_fcsr";
1777 mips16_get_fcsr_one_only_stub::output_body ()
1779 fprintf (asm_out_file
,
1781 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1784 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1785 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1787 virtual const char *get_name ();
1788 virtual void output_body ();
1792 mips16_set_fcsr_one_only_stub::get_name ()
1794 return "__mips16_set_fcsr";
1798 mips16_set_fcsr_one_only_stub::output_body ()
1800 fprintf (asm_out_file
,
1802 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1805 /* Return true if symbols of type TYPE require a GOT access. */
1808 mips_got_symbol_type_p (enum mips_symbol_type type
)
1812 case SYMBOL_GOT_PAGE_OFST
:
1813 case SYMBOL_GOT_DISP
:
1821 /* Return true if X is a thread-local symbol. */
1824 mips_tls_symbol_p (rtx x
)
1826 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1829 /* Return true if SYMBOL_REF X is associated with a global symbol
1830 (in the STB_GLOBAL sense). */
1833 mips_global_symbol_p (const_rtx x
)
1835 const_tree decl
= SYMBOL_REF_DECL (x
);
1838 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1840 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1841 or weak symbols. Relocations in the object file will be against
1842 the target symbol, so it's that symbol's binding that matters here. */
1843 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1846 /* Return true if function X is a libgcc MIPS16 stub function. */
1849 mips16_stub_function_p (const_rtx x
)
1851 return (GET_CODE (x
) == SYMBOL_REF
1852 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1855 /* Return true if function X is a locally-defined and locally-binding
1859 mips16_local_function_p (const_rtx x
)
1861 return (GET_CODE (x
) == SYMBOL_REF
1862 && SYMBOL_REF_LOCAL_P (x
)
1863 && !SYMBOL_REF_EXTERNAL_P (x
)
1864 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1867 /* Return true if SYMBOL_REF X binds locally. */
1870 mips_symbol_binds_local_p (const_rtx x
)
1872 return (SYMBOL_REF_DECL (x
)
1873 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1874 : SYMBOL_REF_LOCAL_P (x
));
1877 /* Return true if OP is a constant vector with the number of units in MODE,
1878 and each unit has the same bit set. */
1881 mips_const_vector_bitimm_set_p (rtx op
, machine_mode mode
)
1883 if (GET_CODE (op
) == CONST_VECTOR
&& op
!= CONST0_RTX (mode
))
1885 unsigned HOST_WIDE_INT val
= UINTVAL (CONST_VECTOR_ELT (op
, 0));
1886 int vlog2
= exact_log2 (val
& GET_MODE_MASK (GET_MODE_INNER (mode
)));
1890 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
1891 gcc_assert (vlog2
>= 0 && vlog2
<= GET_MODE_UNIT_BITSIZE (mode
) - 1);
1892 return mips_const_vector_same_val_p (op
, mode
);
1899 /* Return true if OP is a constant vector with the number of units in MODE,
1900 and each unit has the same bit clear. */
1903 mips_const_vector_bitimm_clr_p (rtx op
, machine_mode mode
)
1905 if (GET_CODE (op
) == CONST_VECTOR
&& op
!= CONSTM1_RTX (mode
))
1907 unsigned HOST_WIDE_INT val
= ~UINTVAL (CONST_VECTOR_ELT (op
, 0));
1908 int vlog2
= exact_log2 (val
& GET_MODE_MASK (GET_MODE_INNER (mode
)));
1912 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
1913 gcc_assert (vlog2
>= 0 && vlog2
<= GET_MODE_UNIT_BITSIZE (mode
) - 1);
1914 return mips_const_vector_same_val_p (op
, mode
);
1921 /* Return true if OP is a constant vector with the number of units in MODE,
1922 and each unit has the same value. */
1925 mips_const_vector_same_val_p (rtx op
, machine_mode mode
)
1927 int i
, nunits
= GET_MODE_NUNITS (mode
);
1930 if (GET_CODE (op
) != CONST_VECTOR
|| GET_MODE (op
) != mode
)
1933 first
= CONST_VECTOR_ELT (op
, 0);
1934 for (i
= 1; i
< nunits
; i
++)
1935 if (!rtx_equal_p (first
, CONST_VECTOR_ELT (op
, i
)))
1941 /* Return true if OP is a constant vector with the number of units in MODE,
1942 and each unit has the same value as well as replicated bytes in the value.
1946 mips_const_vector_same_bytes_p (rtx op
, machine_mode mode
)
1949 HOST_WIDE_INT val
, first_byte
;
1952 if (!mips_const_vector_same_val_p (op
, mode
))
1955 first
= CONST_VECTOR_ELT (op
, 0);
1956 bytes
= GET_MODE_UNIT_SIZE (mode
);
1957 val
= INTVAL (first
);
1958 first_byte
= val
& 0xff;
1959 for (i
= 1; i
< bytes
; i
++)
1962 if ((val
& 0xff) != first_byte
)
1969 /* Return true if OP is a constant vector with the number of units in MODE,
1970 and each unit has the same integer value in the range [LOW, HIGH]. */
1973 mips_const_vector_same_int_p (rtx op
, machine_mode mode
, HOST_WIDE_INT low
,
1976 HOST_WIDE_INT value
;
1979 if (!mips_const_vector_same_val_p (op
, mode
))
1982 elem0
= CONST_VECTOR_ELT (op
, 0);
1983 if (!CONST_INT_P (elem0
))
1986 value
= INTVAL (elem0
);
1987 return (value
>= low
&& value
<= high
);
1990 /* Return true if OP is a constant vector with repeated 4-element sets
1994 mips_const_vector_shuffle_set_p (rtx op
, machine_mode mode
)
1996 int nunits
= GET_MODE_NUNITS (mode
);
1997 int nsets
= nunits
/ 4;
2001 /* Check if we have the same 4-element sets. */
2002 for (j
= 0; j
< nsets
; j
++, set
= 4 * j
)
2003 for (i
= 0; i
< 4; i
++)
2004 if ((INTVAL (XVECEXP (op
, 0, i
))
2005 != (INTVAL (XVECEXP (op
, 0, set
+ i
)) - set
))
2006 || !IN_RANGE (INTVAL (XVECEXP (op
, 0, set
+ i
)), 0, set
+ 3))
2011 /* Return true if rtx constants of mode MODE should be put into a small
2015 mips_rtx_constant_in_small_data_p (machine_mode mode
)
2017 return (!TARGET_EMBEDDED_DATA
2018 && TARGET_LOCAL_SDATA
2019 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
2022 /* Return true if X should not be moved directly into register $25.
2023 We need this because many versions of GAS will treat "la $25,foo" as
2024 part of a call sequence and so allow a global "foo" to be lazily bound. */
2027 mips_dangerous_for_la25_p (rtx x
)
2029 return (!TARGET_EXPLICIT_RELOCS
2031 && GET_CODE (x
) == SYMBOL_REF
2032 && mips_global_symbol_p (x
));
2035 /* Return true if calls to X might need $25 to be valid on entry. */
2038 mips_use_pic_fn_addr_reg_p (const_rtx x
)
2040 if (!TARGET_USE_PIC_FN_ADDR_REG
)
2043 /* MIPS16 stub functions are guaranteed not to use $25. */
2044 if (mips16_stub_function_p (x
))
2047 if (GET_CODE (x
) == SYMBOL_REF
)
2049 /* If PLTs and copy relocations are available, the static linker
2050 will make sure that $25 is valid on entry to the target function. */
2051 if (TARGET_ABICALLS_PIC0
)
2054 /* Locally-defined functions use absolute accesses to set up
2055 the global pointer. */
2056 if (TARGET_ABSOLUTE_ABICALLS
2057 && mips_symbol_binds_local_p (x
)
2058 && !SYMBOL_REF_EXTERNAL_P (x
))
2065 /* Return the method that should be used to access SYMBOL_REF or
2066 LABEL_REF X in context CONTEXT. */
2068 static enum mips_symbol_type
2069 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
2072 return SYMBOL_GOT_DISP
;
2074 if (GET_CODE (x
) == LABEL_REF
)
2076 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
2077 code and if we know that the label is in the current function's
2078 text section. LABEL_REFs are used for jump tables as well as
2079 text labels, so we must check whether jump tables live in the
2081 if (TARGET_MIPS16_SHORT_JUMP_TABLES
2082 && !LABEL_REF_NONLOCAL_P (x
))
2083 return SYMBOL_PC_RELATIVE
;
2085 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
2086 return SYMBOL_GOT_PAGE_OFST
;
2088 return SYMBOL_ABSOLUTE
;
2091 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
2093 if (SYMBOL_REF_TLS_MODEL (x
))
2096 if (CONSTANT_POOL_ADDRESS_P (x
))
2098 if (TARGET_MIPS16_TEXT_LOADS
)
2099 return SYMBOL_PC_RELATIVE
;
2101 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
2102 return SYMBOL_PC_RELATIVE
;
2104 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
2105 return SYMBOL_GP_RELATIVE
;
2108 /* Do not use small-data accesses for weak symbols; they may end up
2110 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
2111 return SYMBOL_GP_RELATIVE
;
2113 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
2115 if (TARGET_ABICALLS_PIC2
2116 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
2118 /* There are three cases to consider:
2120 - o32 PIC (either with or without explicit relocs)
2121 - n32/n64 PIC without explicit relocs
2122 - n32/n64 PIC with explicit relocs
2124 In the first case, both local and global accesses will use an
2125 R_MIPS_GOT16 relocation. We must correctly predict which of
2126 the two semantics (local or global) the assembler and linker
2127 will apply. The choice depends on the symbol's binding rather
2128 than its visibility.
2130 In the second case, the assembler will not use R_MIPS_GOT16
2131 relocations, but it chooses between local and global accesses
2132 in the same way as for o32 PIC.
2134 In the third case we have more freedom since both forms of
2135 access will work for any kind of symbol. However, there seems
2136 little point in doing things differently. */
2137 if (mips_global_symbol_p (x
))
2138 return SYMBOL_GOT_DISP
;
2140 return SYMBOL_GOT_PAGE_OFST
;
2143 return SYMBOL_ABSOLUTE
;
2146 /* Classify the base of symbolic expression X, given that X appears in
2149 static enum mips_symbol_type
2150 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
2154 split_const (x
, &x
, &offset
);
2155 if (UNSPEC_ADDRESS_P (x
))
2156 return UNSPEC_ADDRESS_TYPE (x
);
2158 return mips_classify_symbol (x
, context
);
2161 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
2162 is the alignment in bytes of SYMBOL_REF X. */
2165 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
2167 HOST_WIDE_INT align
;
2169 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
2170 return IN_RANGE (offset
, 0, align
- 1);
2173 /* Return true if X is a symbolic constant that can be used in context
2174 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
2177 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
2178 enum mips_symbol_type
*symbol_type
)
2182 split_const (x
, &x
, &offset
);
2183 if (UNSPEC_ADDRESS_P (x
))
2185 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
2186 x
= UNSPEC_ADDRESS (x
);
2188 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
2190 *symbol_type
= mips_classify_symbol (x
, context
);
2191 if (*symbol_type
== SYMBOL_TLS
)
2197 if (offset
== const0_rtx
)
2200 /* Check whether a nonzero offset is valid for the underlying
2202 switch (*symbol_type
)
2204 case SYMBOL_ABSOLUTE
:
2205 case SYMBOL_64_HIGH
:
2208 /* If the target has 64-bit pointers and the object file only
2209 supports 32-bit symbols, the values of those symbols will be
2210 sign-extended. In this case we can't allow an arbitrary offset
2211 in case the 32-bit value X + OFFSET has a different sign from X. */
2212 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2213 return offset_within_block_p (x
, INTVAL (offset
));
2215 /* In other cases the relocations can handle any offset. */
2218 case SYMBOL_PC_RELATIVE
:
2219 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2220 In this case, we no longer have access to the underlying constant,
2221 but the original symbol-based access was known to be valid. */
2222 if (GET_CODE (x
) == LABEL_REF
)
2227 case SYMBOL_GP_RELATIVE
:
2228 /* Make sure that the offset refers to something within the
2229 same object block. This should guarantee that the final
2230 PC- or GP-relative offset is within the 16-bit limit. */
2231 return offset_within_block_p (x
, INTVAL (offset
));
2233 case SYMBOL_GOT_PAGE_OFST
:
2234 case SYMBOL_GOTOFF_PAGE
:
2235 /* If the symbol is global, the GOT entry will contain the symbol's
2236 address, and we will apply a 16-bit offset after loading it.
2237 If the symbol is local, the linker should provide enough local
2238 GOT entries for a 16-bit offset, but larger offsets may lead
2240 return SMALL_INT (offset
);
2244 /* There is no carry between the HI and LO REL relocations, so the
2245 offset is only valid if we know it won't lead to such a carry. */
2246 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2248 case SYMBOL_GOT_DISP
:
2249 case SYMBOL_GOTOFF_DISP
:
2250 case SYMBOL_GOTOFF_CALL
:
2251 case SYMBOL_GOTOFF_LOADGP
:
2254 case SYMBOL_GOTTPREL
:
2262 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2263 single instruction. We rely on the fact that, in the worst case,
2264 all instructions involved in a MIPS16 address calculation are usually
2268 mips_symbol_insns_1 (enum mips_symbol_type type
, machine_mode mode
)
2270 if (mips_use_pcrel_pool_p
[(int) type
])
2272 if (mode
== MAX_MACHINE_MODE
)
2273 /* LEAs will be converted into constant-pool references by
2275 type
= SYMBOL_PC_RELATIVE
;
2277 /* The constant must be loaded and then dereferenced. */
2283 case SYMBOL_ABSOLUTE
:
2284 /* When using 64-bit symbols, we need 5 preparatory instructions,
2287 lui $at,%highest(symbol)
2288 daddiu $at,$at,%higher(symbol)
2290 daddiu $at,$at,%hi(symbol)
2293 The final address is then $at + %lo(symbol). With 32-bit
2294 symbols we just need a preparatory LUI for normal mode and
2295 a preparatory LI and SLL for MIPS16. */
2296 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2298 case SYMBOL_GP_RELATIVE
:
2299 /* Treat GP-relative accesses as taking a single instruction on
2300 MIPS16 too; the copy of $gp can often be shared. */
2303 case SYMBOL_PC_RELATIVE
:
2304 /* PC-relative constants can be only be used with ADDIUPC,
2305 DADDIUPC, LWPC and LDPC. */
2306 if (mode
== MAX_MACHINE_MODE
2307 || GET_MODE_SIZE (mode
) == 4
2308 || GET_MODE_SIZE (mode
) == 8)
2311 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2314 case SYMBOL_GOT_DISP
:
2315 /* The constant will have to be loaded from the GOT before it
2316 is used in an address. */
2317 if (mode
!= MAX_MACHINE_MODE
)
2322 case SYMBOL_GOT_PAGE_OFST
:
2323 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2324 local/global classification is accurate. The worst cases are:
2326 (1) For local symbols when generating o32 or o64 code. The assembler
2332 ...and the final address will be $at + %lo(symbol).
2334 (2) For global symbols when -mxgot. The assembler will use:
2336 lui $at,%got_hi(symbol)
2339 ...and the final address will be $at + %got_lo(symbol). */
2342 case SYMBOL_GOTOFF_PAGE
:
2343 case SYMBOL_GOTOFF_DISP
:
2344 case SYMBOL_GOTOFF_CALL
:
2345 case SYMBOL_GOTOFF_LOADGP
:
2346 case SYMBOL_64_HIGH
:
2352 case SYMBOL_GOTTPREL
:
2355 /* A 16-bit constant formed by a single relocation, or a 32-bit
2356 constant formed from a high 16-bit relocation and a low 16-bit
2357 relocation. Use mips_split_p to determine which. 32-bit
2358 constants need an "lui; addiu" sequence for normal mode and
2359 an "li; sll; addiu" sequence for MIPS16 mode. */
2360 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2363 /* We don't treat a bare TLS symbol as a constant. */
2369 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2370 to load symbols of type TYPE into a register. Return 0 if the given
2371 type of symbol cannot be used as an immediate operand.
2373 Otherwise, return the number of instructions needed to load or store
2374 values of mode MODE to or from addresses of type TYPE. Return 0 if
2375 the given type of symbol is not valid in addresses.
2377 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2380 mips_symbol_insns (enum mips_symbol_type type
, machine_mode mode
)
2382 /* MSA LD.* and ST.* cannot support loading symbols via an immediate
2384 if (MSA_SUPPORTED_MODE_P (mode
))
2387 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2390 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2393 mips_cannot_force_const_mem (machine_mode mode
, rtx x
)
2395 enum mips_symbol_type type
;
2398 /* There is no assembler syntax for expressing an address-sized
2400 if (GET_CODE (x
) == HIGH
)
2403 /* As an optimization, reject constants that mips_legitimize_move
2406 Suppose we have a multi-instruction sequence that loads constant C
2407 into register R. If R does not get allocated a hard register, and
2408 R is used in an operand that allows both registers and memory
2409 references, reload will consider forcing C into memory and using
2410 one of the instruction's memory alternatives. Returning false
2411 here will force it to use an input reload instead. */
2412 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2415 split_const (x
, &base
, &offset
);
2416 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2418 /* See whether we explicitly want these symbols in the pool. */
2419 if (mips_use_pcrel_pool_p
[(int) type
])
2422 /* The same optimization as for CONST_INT. */
2423 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2426 /* If MIPS16 constant pools live in the text section, they should
2427 not refer to anything that might need run-time relocation. */
2428 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2432 /* TLS symbols must be computed by mips_legitimize_move. */
2433 if (tls_referenced_p (x
))
2439 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2440 constants when we're using a per-function constant pool. */
2443 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2444 const_rtx x ATTRIBUTE_UNUSED
)
2446 return !TARGET_MIPS16_PCREL_LOADS
;
2449 /* Return true if register REGNO is a valid base register for mode MODE.
2450 STRICT_P is true if REG_OK_STRICT is in effect. */
2453 mips_regno_mode_ok_for_base_p (int regno
, machine_mode mode
,
2456 if (!HARD_REGISTER_NUM_P (regno
))
2460 regno
= reg_renumber
[regno
];
2463 /* These fake registers will be eliminated to either the stack or
2464 hard frame pointer, both of which are usually valid base registers.
2465 Reload deals with the cases where the eliminated form isn't valid. */
2466 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2469 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2470 values, nothing smaller. */
2471 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2472 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2474 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2477 /* Return true if X is a valid base register for mode MODE.
2478 STRICT_P is true if REG_OK_STRICT is in effect. */
2481 mips_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
2483 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2487 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2490 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2491 can address a value of mode MODE. */
2494 mips_valid_offset_p (rtx x
, machine_mode mode
)
2496 /* Check that X is a signed 16-bit number. */
2497 if (!const_arith_operand (x
, Pmode
))
2500 /* We may need to split multiword moves, so make sure that every word
2502 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2503 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2506 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2507 if (MSA_SUPPORTED_MODE_P (mode
)
2508 && !mips_signed_immediate_p (INTVAL (x
), 10,
2509 mips_ldst_scaled_shift (mode
)))
2515 /* Return true if a LO_SUM can address a value of mode MODE when the
2516 LO_SUM symbol has type SYMBOL_TYPE. */
2519 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, machine_mode mode
)
2521 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2523 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2526 /* Check that there is a known low-part relocation. */
2527 if (mips_lo_relocs
[symbol_type
] == NULL
)
2530 /* We may need to split multiword moves, so make sure that each word
2531 can be accessed without inducing a carry. This is mainly needed
2532 for o64, which has historically only guaranteed 64-bit alignment
2533 for 128-bit types. */
2534 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2535 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2538 /* MSA LD.* and ST.* cannot support loading symbols via %lo($base). */
2539 if (MSA_SUPPORTED_MODE_P (mode
))
2545 /* Return true if X is a valid address for machine mode MODE. If it is,
2546 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2550 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2551 machine_mode mode
, bool strict_p
)
2553 switch (GET_CODE (x
))
2557 info
->type
= ADDRESS_REG
;
2559 info
->offset
= const0_rtx
;
2560 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2563 info
->type
= ADDRESS_REG
;
2564 info
->reg
= XEXP (x
, 0);
2565 info
->offset
= XEXP (x
, 1);
2566 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2567 && mips_valid_offset_p (info
->offset
, mode
));
2570 info
->type
= ADDRESS_LO_SUM
;
2571 info
->reg
= XEXP (x
, 0);
2572 info
->offset
= XEXP (x
, 1);
2573 /* We have to trust the creator of the LO_SUM to do something vaguely
2574 sane. Target-independent code that creates a LO_SUM should also
2575 create and verify the matching HIGH. Target-independent code that
2576 adds an offset to a LO_SUM must prove that the offset will not
2577 induce a carry. Failure to do either of these things would be
2578 a bug, and we are not required to check for it here. The MIPS
2579 backend itself should only create LO_SUMs for valid symbolic
2580 constants, with the high part being either a HIGH or a copy
2583 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2584 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2585 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2588 /* Small-integer addresses don't occur very often, but they
2589 are legitimate if $0 is a valid base register. */
2590 info
->type
= ADDRESS_CONST_INT
;
2591 return !TARGET_MIPS16
&& SMALL_INT (x
);
2596 info
->type
= ADDRESS_SYMBOLIC
;
2597 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2599 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2600 && !mips_split_p
[info
->symbol_type
]);
2607 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2610 mips_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2612 struct mips_address_info addr
;
2614 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2617 /* Return true if X is a legitimate $sp-based address for mode MODE. */
2620 mips_stack_address_p (rtx x
, machine_mode mode
)
2622 struct mips_address_info addr
;
2624 return (mips_classify_address (&addr
, x
, mode
, false)
2625 && addr
.type
== ADDRESS_REG
2626 && addr
.reg
== stack_pointer_rtx
);
2629 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2630 address instruction. Note that such addresses are not considered
2631 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2632 is so restricted. */
2635 mips_lwxs_address_p (rtx addr
)
2638 && GET_CODE (addr
) == PLUS
2639 && REG_P (XEXP (addr
, 1)))
2641 rtx offset
= XEXP (addr
, 0);
2642 if (GET_CODE (offset
) == MULT
2643 && REG_P (XEXP (offset
, 0))
2644 && CONST_INT_P (XEXP (offset
, 1))
2645 && INTVAL (XEXP (offset
, 1)) == 4)
2651 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2652 indexed address instruction. Note that such addresses are
2653 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2654 sense, because their use is so restricted. */
2657 mips_lx_address_p (rtx addr
, machine_mode mode
)
2659 if (GET_CODE (addr
) != PLUS
2660 || !REG_P (XEXP (addr
, 0))
2661 || !REG_P (XEXP (addr
, 1)))
2663 if (ISA_HAS_LBX
&& mode
== QImode
)
2665 if (ISA_HAS_LHX
&& mode
== HImode
)
2667 if (ISA_HAS_LWX
&& mode
== SImode
)
2669 if (ISA_HAS_LDX
&& mode
== DImode
)
2671 if (MSA_SUPPORTED_MODE_P (mode
))
2676 /* Return true if a value at OFFSET bytes from base register BASE can be
2677 accessed using an unextended MIPS16 instruction. MODE is the mode of
2680 Usually the offset in an unextended instruction is a 5-bit field.
2681 The offset is unsigned and shifted left once for LH and SH, twice
2682 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2683 an 8-bit immediate field that's shifted left twice. */
2686 mips16_unextended_reference_p (machine_mode mode
, rtx base
,
2687 unsigned HOST_WIDE_INT offset
)
2689 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2691 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2692 return offset
< 256U * GET_MODE_SIZE (mode
);
2693 return offset
< 32U * GET_MODE_SIZE (mode
);
2698 /* Return the number of instructions needed to load or store a value
2699 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2700 length of one instruction. Return 0 if X isn't valid for MODE.
2701 Assume that multiword moves may need to be split into word moves
2702 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2706 mips_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
2708 struct mips_address_info addr
;
2710 bool msa_p
= (!might_split_p
&& MSA_SUPPORTED_MODE_P (mode
));
2712 /* BLKmode is used for single unaligned loads and stores and should
2713 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2714 meaningless, so we have to single it out as a special case one way
2716 if (mode
!= BLKmode
&& might_split_p
)
2717 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2721 if (mips_classify_address (&addr
, x
, mode
, false))
2727 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2728 if (mips_signed_immediate_p (INTVAL (addr
.offset
), 10,
2729 mips_ldst_scaled_shift (mode
)))
2735 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2736 UINTVAL (addr
.offset
)))
2740 case ADDRESS_LO_SUM
:
2741 return msa_p
? 0 : TARGET_MIPS16
? factor
* 2 : factor
;
2743 case ADDRESS_CONST_INT
:
2744 return msa_p
? 0 : factor
;
2746 case ADDRESS_SYMBOLIC
:
2747 return msa_p
? 0 : factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2752 /* Return true if X fits within an unsigned field of BITS bits that is
2753 shifted left SHIFT bits before being used. */
2756 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2758 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2761 /* Return true if X fits within a signed field of BITS bits that is
2762 shifted left SHIFT bits before being used. */
2765 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2767 x
+= 1 << (bits
+ shift
- 1);
2768 return mips_unsigned_immediate_p (x
, bits
, shift
);
2771 /* Return the scale shift that applied to MSA LD/ST address offset. */
2774 mips_ldst_scaled_shift (machine_mode mode
)
2776 int shift
= exact_log2 (GET_MODE_UNIT_SIZE (mode
));
2778 if (shift
< 0 || shift
> 8)
2784 /* Return true if X is legitimate for accessing values of mode MODE,
2785 if it is based on a MIPS16 register, and if the offset satisfies
2786 OFFSET_PREDICATE. */
2789 m16_based_address_p (rtx x
, machine_mode mode
,
2790 insn_operand_predicate_fn offset_predicate
)
2792 struct mips_address_info addr
;
2794 return (mips_classify_address (&addr
, x
, mode
, false)
2795 && addr
.type
== ADDRESS_REG
2796 && M16_REG_P (REGNO (addr
.reg
))
2797 && offset_predicate (addr
.offset
, mode
));
2800 /* Return true if X is a legitimate address that conforms to the requirements
2801 for a microMIPS LWSP or SWSP insn. */
2804 lwsp_swsp_address_p (rtx x
, machine_mode mode
)
2806 struct mips_address_info addr
;
2808 return (mips_classify_address (&addr
, x
, mode
, false)
2809 && addr
.type
== ADDRESS_REG
2810 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2811 && uw5_operand (addr
.offset
, mode
));
2814 /* Return true if X is a legitimate address with a 12-bit offset.
2815 MODE is the mode of the value being accessed. */
2818 umips_12bit_offset_address_p (rtx x
, machine_mode mode
)
2820 struct mips_address_info addr
;
2822 return (mips_classify_address (&addr
, x
, mode
, false)
2823 && addr
.type
== ADDRESS_REG
2824 && CONST_INT_P (addr
.offset
)
2825 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2828 /* Return true if X is a legitimate address with a 9-bit offset.
2829 MODE is the mode of the value being accessed. */
2832 mips_9bit_offset_address_p (rtx x
, machine_mode mode
)
2834 struct mips_address_info addr
;
2836 return (mips_classify_address (&addr
, x
, mode
, false)
2837 && addr
.type
== ADDRESS_REG
2838 && CONST_INT_P (addr
.offset
)
2839 && MIPS_9BIT_OFFSET_P (INTVAL (addr
.offset
)));
2842 /* Return the number of instructions needed to load constant X,
2843 assuming that BASE_INSN_LENGTH is the length of one instruction.
2844 Return 0 if X isn't a valid constant. */
2847 mips_const_insns (rtx x
)
2849 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2850 enum mips_symbol_type symbol_type
;
2853 switch (GET_CODE (x
))
2856 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2858 || !mips_split_p
[symbol_type
])
2861 /* This is simply an LUI for normal mode. It is an extended
2862 LI followed by an extended SLL for MIPS16. */
2863 return TARGET_MIPS16
? 4 : 1;
2867 /* Unsigned 8-bit constants can be loaded using an unextended
2868 LI instruction. Unsigned 16-bit constants can be loaded
2869 using an extended LI. Negative constants must be loaded
2870 using LI and then negated. */
2871 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2872 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2873 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2874 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2877 return mips_build_integer (codes
, INTVAL (x
));
2881 && mips_const_vector_same_int_p (x
, GET_MODE (x
), -512, 511))
2885 /* Allow zeros for normal mode, where we can use $0. */
2886 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2892 /* See if we can refer to X directly. */
2893 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2894 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2896 /* Otherwise try splitting the constant into a base and offset.
2897 If the offset is a 16-bit value, we can load the base address
2898 into a register and then use (D)ADDIU to add in the offset.
2899 If the offset is larger, we can load the base and offset
2900 into separate registers and add them together with (D)ADDU.
2901 However, the latter is only possible before reload; during
2902 and after reload, we must have the option of forcing the
2903 constant into the pool instead. */
2904 split_const (x
, &x
, &offset
);
2907 int n
= mips_const_insns (x
);
2910 if (SMALL_INT (offset
))
2912 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2913 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2920 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2928 /* X is a doubleword constant that can be handled by splitting it into
2929 two words and loading each word separately. Return the number of
2930 instructions required to do this, assuming that BASE_INSN_LENGTH
2931 is the length of one instruction. */
2934 mips_split_const_insns (rtx x
)
2936 unsigned int low
, high
;
2938 low
= mips_const_insns (mips_subword (x
, false));
2939 high
= mips_const_insns (mips_subword (x
, true));
2940 gcc_assert (low
> 0 && high
> 0);
2944 /* Return one word of 128-bit value OP, taking into account the fixed
2945 endianness of certain registers. BYTE selects from the byte address. */
2948 mips_subword_at_byte (rtx op
, unsigned int byte
)
2952 mode
= GET_MODE (op
);
2953 if (mode
== VOIDmode
)
2956 gcc_assert (!FP_REG_RTX_P (op
));
2959 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
2961 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2964 /* Return the number of instructions needed to implement INSN,
2965 given that it loads from or stores to MEM. Assume that
2966 BASE_INSN_LENGTH is the length of one instruction. */
2969 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2975 gcc_assert (MEM_P (mem
));
2976 mode
= GET_MODE (mem
);
2978 /* Try to prove that INSN does not need to be split. */
2979 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2982 set
= single_set (insn
);
2983 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2984 might_split_p
= false;
2987 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2990 /* Return the number of instructions needed for an integer division,
2991 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2994 mips_idiv_insns (machine_mode mode
)
2999 if (TARGET_CHECK_ZERO_DIV
)
3001 if (GENERATE_DIVIDE_TRAPS
&& !MSA_SUPPORTED_MODE_P (mode
))
3007 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
3013 /* Emit a move from SRC to DEST. Assume that the move expanders can
3014 handle all moves if !can_create_pseudo_p (). The distinction is
3015 important because, unlike emit_move_insn, the move expanders know
3016 how to force Pmode objects into the constant pool even when the
3017 constant pool address is not itself legitimate. */
3020 mips_emit_move (rtx dest
, rtx src
)
3022 return (can_create_pseudo_p ()
3023 ? emit_move_insn (dest
, src
)
3024 : emit_move_insn_1 (dest
, src
));
3027 /* Emit a move from SRC to DEST, splitting compound moves into individual
3028 instructions. SPLIT_TYPE is the type of split to perform. */
3031 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
3033 if (mips_split_move_p (dest
, src
, split_type
))
3034 mips_split_move (dest
, src
, split_type
);
3036 mips_emit_move (dest
, src
);
3039 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
3042 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
3044 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
3047 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
3048 Return that new register. */
3051 mips_force_unary (machine_mode mode
, enum rtx_code code
, rtx op0
)
3055 reg
= gen_reg_rtx (mode
);
3056 mips_emit_unary (code
, reg
, op0
);
3060 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3063 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
3065 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (code
, GET_MODE (target
),
3069 /* Compute (CODE OP0 OP1) and store the result in a new register
3070 of mode MODE. Return that new register. */
3073 mips_force_binary (machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
3077 reg
= gen_reg_rtx (mode
);
3078 mips_emit_binary (code
, reg
, op0
, op1
);
3082 /* Copy VALUE to a register and return that register. If new pseudos
3083 are allowed, copy it into a new register, otherwise use DEST. */
3086 mips_force_temporary (rtx dest
, rtx value
)
3088 if (can_create_pseudo_p ())
3089 return force_reg (Pmode
, value
);
3092 mips_emit_move (dest
, value
);
3097 /* Emit a call sequence with call pattern PATTERN and return the call
3098 instruction itself (which is not necessarily the last instruction
3099 emitted). ORIG_ADDR is the original, unlegitimized address,
3100 ADDR is the legitimized form, and LAZY_P is true if the call
3101 address is lazily-bound. */
3104 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
3109 insn
= emit_call_insn (pattern
);
3111 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
3113 /* MIPS16 JALRs only take MIPS16 registers. If the target
3114 function requires $25 to be valid on entry, we must copy it
3115 there separately. The move instruction can be put in the
3116 call's delay slot. */
3117 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
3118 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
3119 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
3123 /* Lazy-binding stubs require $gp to be valid on entry. */
3124 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3128 /* See the comment above load_call<mode> for details. */
3129 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
3130 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
3131 emit_insn (gen_update_got_version ());
3135 && TARGET_EXPLICIT_RELOCS
3136 && TARGET_CALL_CLOBBERED_GP
)
3138 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
3139 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
3145 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
3146 then add CONST_INT OFFSET to the result. */
3149 mips_unspec_address_offset (rtx base
, rtx offset
,
3150 enum mips_symbol_type symbol_type
)
3152 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
3153 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
3154 if (offset
!= const0_rtx
)
3155 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
3156 return gen_rtx_CONST (Pmode
, base
);
3159 /* Return an UNSPEC address with underlying address ADDRESS and symbol
3160 type SYMBOL_TYPE. */
3163 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
3167 split_const (address
, &base
, &offset
);
3168 return mips_unspec_address_offset (base
, offset
, symbol_type
);
3171 /* If OP is an UNSPEC address, return the address to which it refers,
3172 otherwise return OP itself. */
3175 mips_strip_unspec_address (rtx op
)
3179 split_const (op
, &base
, &offset
);
3180 if (UNSPEC_ADDRESS_P (base
))
3181 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
3185 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
3186 high part to BASE and return the result. Just return BASE otherwise.
3187 TEMP is as for mips_force_temporary.
3189 The returned expression can be used as the first operand to a LO_SUM. */
3192 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
3193 enum mips_symbol_type symbol_type
)
3195 if (mips_split_p
[symbol_type
])
3197 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
3198 addr
= mips_force_temporary (temp
, addr
);
3199 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
3204 /* Return an instruction that copies $gp into register REG. We want
3205 GCC to treat the register's value as constant, so that its value
3206 can be rematerialized on demand. */
3209 gen_load_const_gp (rtx reg
)
3211 return PMODE_INSN (gen_load_const_gp
, (reg
));
3214 /* Return a pseudo register that contains the value of $gp throughout
3215 the current function. Such registers are needed by MIPS16 functions,
3216 for which $gp itself is not a valid base register or addition operand. */
3219 mips16_gp_pseudo_reg (void)
3221 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
3225 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
3227 push_topmost_sequence ();
3229 scan
= get_insns ();
3230 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
3231 scan
= NEXT_INSN (scan
);
3233 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
3234 rtx_insn
*insn
= emit_insn_after (set
, scan
);
3235 INSN_LOCATION (insn
) = 0;
3237 pop_topmost_sequence ();
3240 return cfun
->machine
->mips16_gp_pseudo_rtx
;
3243 /* Return a base register that holds pic_offset_table_rtx.
3244 TEMP, if nonnull, is a scratch Pmode base register. */
3247 mips_pic_base_register (rtx temp
)
3250 return pic_offset_table_rtx
;
3252 if (currently_expanding_to_rtl
)
3253 return mips16_gp_pseudo_reg ();
3255 if (can_create_pseudo_p ())
3256 temp
= gen_reg_rtx (Pmode
);
3259 /* The first post-reload split exposes all references to $gp
3260 (both uses and definitions). All references must remain
3261 explicit after that point.
3263 It is safe to introduce uses of $gp at any time, so for
3264 simplicity, we do that before the split too. */
3265 mips_emit_move (temp
, pic_offset_table_rtx
);
3267 emit_insn (gen_load_const_gp (temp
));
3271 /* Return the RHS of a load_call<mode> insn. */
3274 mips_unspec_call (rtx reg
, rtx symbol
)
3278 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3279 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3282 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3283 reference. Return NULL_RTX otherwise. */
3286 mips_strip_unspec_call (rtx src
)
3288 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3289 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3293 /* Create and return a GOT reference of type TYPE for address ADDR.
3294 TEMP, if nonnull, is a scratch Pmode base register. */
3297 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3299 rtx base
, high
, lo_sum_symbol
;
3301 base
= mips_pic_base_register (temp
);
3303 /* If we used the temporary register to load $gp, we can't use
3304 it for the high part as well. */
3305 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3308 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3309 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3311 if (type
== SYMBOL_GOTOFF_CALL
)
3312 return mips_unspec_call (high
, lo_sum_symbol
);
3314 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3317 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3318 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3319 constant in that context and can be split into high and low parts.
3320 If so, and if LOW_OUT is nonnull, emit the high part and store the
3321 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3323 TEMP is as for mips_force_temporary and is used to load the high
3324 part into a register.
3326 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3327 a legitimize SET_SRC for an .md pattern, otherwise the low part
3328 is guaranteed to be a legitimate address for mode MODE. */
3331 mips_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
3333 enum mips_symbol_context context
;
3334 enum mips_symbol_type symbol_type
;
3337 context
= (mode
== MAX_MACHINE_MODE
3338 ? SYMBOL_CONTEXT_LEA
3339 : SYMBOL_CONTEXT_MEM
);
3340 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3342 addr
= XEXP (addr
, 0);
3343 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3344 && mips_symbol_insns (symbol_type
, mode
) > 0
3345 && mips_split_hi_p
[symbol_type
])
3348 switch (symbol_type
)
3350 case SYMBOL_GOT_PAGE_OFST
:
3351 /* The high part of a page/ofst pair is loaded from the GOT. */
3352 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3363 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3364 && mips_symbol_insns (symbol_type
, mode
) > 0
3365 && mips_split_p
[symbol_type
])
3368 switch (symbol_type
)
3370 case SYMBOL_GOT_DISP
:
3371 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3372 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3375 case SYMBOL_GP_RELATIVE
:
3376 high
= mips_pic_base_register (temp
);
3377 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3381 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3382 high
= mips_force_temporary (temp
, high
);
3383 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3392 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3393 mips_force_temporary; it is only needed when OFFSET is not a
3397 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3399 if (!SMALL_OPERAND (offset
))
3405 /* Load the full offset into a register so that we can use
3406 an unextended instruction for the address itself. */
3407 high
= GEN_INT (offset
);
3412 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3413 The addition inside the macro CONST_HIGH_PART may cause an
3414 overflow, so we need to force a sign-extension check. */
3415 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3416 offset
= CONST_LOW_PART (offset
);
3418 high
= mips_force_temporary (temp
, high
);
3419 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3421 return plus_constant (Pmode
, reg
, offset
);
3424 /* The __tls_get_attr symbol. */
3425 static GTY(()) rtx mips_tls_symbol
;
3427 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3428 the TLS symbol we are referencing and TYPE is the symbol type to use
3429 (either global dynamic or local dynamic). V0 is an RTX for the
3430 return value location. */
3433 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3438 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3440 if (!mips_tls_symbol
)
3441 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3443 loc
= mips_unspec_address (sym
, type
);
3447 emit_insn (gen_rtx_SET (a0
, gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
,
3449 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3450 const0_rtx
, NULL_RTX
, false);
3451 RTL_CONST_CALL_P (insn
) = 1;
3452 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3453 insn
= get_insns ();
3460 /* Return a pseudo register that contains the current thread pointer. */
3463 mips_expand_thread_pointer (rtx tp
)
3469 if (!mips16_rdhwr_stub
)
3470 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3471 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3472 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3475 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3482 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3485 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3486 its address. The return value will be both a valid address and a valid
3487 SET_SRC (either a REG or a LO_SUM). */
3490 mips_legitimize_tls_address (rtx loc
)
3492 rtx dest
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3493 enum tls_model model
;
3495 model
= SYMBOL_REF_TLS_MODEL (loc
);
3496 /* Only TARGET_ABICALLS code can have more than one module; other
3497 code must be static and should not use a GOT. All TLS models
3498 reduce to local exec in this situation. */
3499 if (!TARGET_ABICALLS
)
3500 model
= TLS_MODEL_LOCAL_EXEC
;
3504 case TLS_MODEL_GLOBAL_DYNAMIC
:
3506 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3507 rtx_insn
*insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3508 dest
= gen_reg_rtx (Pmode
);
3509 emit_libcall_block (insn
, dest
, v0
, loc
);
3513 case TLS_MODEL_LOCAL_DYNAMIC
:
3515 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3516 rtx_insn
*insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3517 tmp1
= gen_reg_rtx (Pmode
);
3519 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3520 share the LDM result with other LD model accesses. */
3521 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3523 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3525 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3526 if (mips_split_p
[SYMBOL_DTPREL
])
3528 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3529 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3532 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3533 0, 0, OPTAB_DIRECT
);
3537 case TLS_MODEL_INITIAL_EXEC
:
3538 tp
= mips_get_tp ();
3539 tmp1
= gen_reg_rtx (Pmode
);
3540 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3541 if (Pmode
== DImode
)
3542 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3544 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3545 dest
= gen_reg_rtx (Pmode
);
3546 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3549 case TLS_MODEL_LOCAL_EXEC
:
3550 tmp1
= mips_get_tp ();
3551 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3552 if (mips_split_p
[SYMBOL_TPREL
])
3554 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3555 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3558 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3559 0, 0, OPTAB_DIRECT
);
3568 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3572 mips16_expand_get_fcsr (rtx target
)
3574 if (!mips16_get_fcsr_stub
)
3575 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3576 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3577 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3578 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3581 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3584 mips16_expand_set_fcsr (rtx newval
)
3586 if (!mips16_set_fcsr_stub
)
3587 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3588 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3589 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3590 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3593 /* If X is not a valid address for mode MODE, force it into a register. */
3596 mips_force_address (rtx x
, machine_mode mode
)
3598 if (!mips_legitimate_address_p (mode
, x
, false))
3599 x
= force_reg (Pmode
, x
);
3603 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3604 be legitimized in a way that the generic machinery might not expect,
3605 return a new address, otherwise return NULL. MODE is the mode of
3606 the memory being accessed. */
3609 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3613 HOST_WIDE_INT offset
;
3615 if (mips_tls_symbol_p (x
))
3616 return mips_legitimize_tls_address (x
);
3618 /* See if the address can split into a high part and a LO_SUM. */
3619 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3620 return mips_force_address (addr
, mode
);
3622 /* Handle BASE + OFFSET using mips_add_offset. */
3623 mips_split_plus (x
, &base
, &offset
);
3626 if (!mips_valid_base_register_p (base
, mode
, false))
3627 base
= copy_to_mode_reg (Pmode
, base
);
3628 addr
= mips_add_offset (NULL
, base
, offset
);
3629 return mips_force_address (addr
, mode
);
3635 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3638 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3640 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3642 unsigned int i
, num_ops
;
3645 mode
= GET_MODE (dest
);
3646 num_ops
= mips_build_integer (codes
, value
);
3648 /* Apply each binary operation to X. Invariant: X is a legitimate
3649 source operand for a SET pattern. */
3650 x
= GEN_INT (codes
[0].value
);
3651 for (i
= 1; i
< num_ops
; i
++)
3653 if (!can_create_pseudo_p ())
3655 emit_insn (gen_rtx_SET (temp
, x
));
3659 x
= force_reg (mode
, x
);
3660 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3663 emit_insn (gen_rtx_SET (dest
, x
));
3666 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3667 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3671 mips_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
3675 /* Split moves of big integers into smaller pieces. */
3676 if (splittable_const_int_operand (src
, mode
))
3678 mips_move_integer (dest
, dest
, INTVAL (src
));
3682 /* Split moves of symbolic constants into high/low pairs. */
3683 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3685 emit_insn (gen_rtx_SET (dest
, src
));
3689 /* Generate the appropriate access sequences for TLS symbols. */
3690 if (mips_tls_symbol_p (src
))
3692 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3696 /* If we have (const (plus symbol offset)), and that expression cannot
3697 be forced into memory, load the symbol first and add in the offset.
3698 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3699 forced into memory, as it usually produces better code. */
3700 split_const (src
, &base
, &offset
);
3701 if (offset
!= const0_rtx
3702 && (targetm
.cannot_force_const_mem (mode
, src
)
3703 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3705 base
= mips_force_temporary (dest
, base
);
3706 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3710 src
= force_const_mem (mode
, src
);
3712 /* When using explicit relocs, constant pool references are sometimes
3713 not legitimate addresses. */
3714 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3715 mips_emit_move (dest
, src
);
3718 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3719 sequence that is valid. */
3722 mips_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
3724 /* Both src and dest are non-registers; one special case is supported where
3725 the source is (const_int 0) and the store can source the zero register.
3726 MIPS16 and MSA are never able to source the zero register directly in
3727 memory operations. */
3728 if (!register_operand (dest
, mode
)
3729 && !register_operand (src
, mode
)
3730 && (TARGET_MIPS16
|| !const_0_operand (src
, mode
)
3731 || MSA_SUPPORTED_MODE_P (mode
)))
3733 mips_emit_move (dest
, force_reg (mode
, src
));
3737 /* We need to deal with constants that would be legitimate
3738 immediate_operands but aren't legitimate move_operands. */
3739 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3741 mips_legitimize_const_move (mode
, dest
, src
);
3742 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3748 /* Return true if value X in context CONTEXT is a small-data address
3749 that can be rewritten as a LO_SUM. */
3752 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3754 enum mips_symbol_type symbol_type
;
3756 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3757 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3758 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3759 && symbol_type
== SYMBOL_GP_RELATIVE
);
3762 /* Return true if OP refers to small data symbols directly, not through
3763 a LO_SUM. CONTEXT is the context in which X appears. */
3766 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3768 subrtx_var_iterator::array_type array
;
3769 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3773 /* Ignore things like "g" constraints in asms. We make no particular
3774 guarantee about which symbolic constants are acceptable as asm operands
3775 versus which must be forced into a GPR. */
3776 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3777 iter
.skip_subrtxes ();
3780 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3782 iter
.skip_subrtxes ();
3784 else if (mips_rewrite_small_data_p (x
, context
))
3790 /* Return true if OP refers to small data symbols directly, not through
3794 mips_small_data_pattern_p (rtx op
)
3796 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3799 /* Rewrite *LOC so that it refers to small data using explicit
3800 relocations. CONTEXT is the context in which *LOC appears. */
3803 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3805 subrtx_ptr_iterator::array_type array
;
3806 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3811 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3812 iter
.skip_subrtxes ();
3814 else if (mips_rewrite_small_data_p (*loc
, context
))
3816 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3817 iter
.skip_subrtxes ();
3819 else if (GET_CODE (*loc
) == LO_SUM
)
3820 iter
.skip_subrtxes ();
3824 /* Rewrite instruction pattern PATTERN so that it refers to small data
3825 using explicit relocations. */
3828 mips_rewrite_small_data (rtx pattern
)
3830 pattern
= copy_insn (pattern
);
3831 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3835 /* The cost of loading values from the constant pool. It should be
3836 larger than the cost of any constant we want to synthesize inline. */
3837 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3839 /* Return the cost of X when used as an operand to the MIPS16 instruction
3840 that implements CODE. Return -1 if there is no such instruction, or if
3841 X is not a valid immediate operand for it. */
3844 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3851 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3852 other shifts are extended. The shift patterns truncate the shift
3853 count to the right size, so there are no out-of-range values. */
3854 if (IN_RANGE (x
, 1, 8))
3856 return COSTS_N_INSNS (1);
3859 if (IN_RANGE (x
, -128, 127))
3861 if (SMALL_OPERAND (x
))
3862 return COSTS_N_INSNS (1);
3866 /* Like LE, but reject the always-true case. */
3871 /* We add 1 to the immediate and use SLT. */
3875 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3878 if (IN_RANGE (x
, 0, 255))
3880 if (SMALL_OPERAND_UNSIGNED (x
))
3881 return COSTS_N_INSNS (1);
3886 /* Equality comparisons with 0 are cheap. */
3896 /* Return true if there is a non-MIPS16 instruction that implements CODE
3897 and if that instruction accepts X as an immediate operand. */
3900 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3907 /* All shift counts are truncated to a valid constant. */
3912 /* Likewise rotates, if the target supports rotates at all. */
3918 /* These instructions take 16-bit unsigned immediates. */
3919 return SMALL_OPERAND_UNSIGNED (x
);
3924 /* These instructions take 16-bit signed immediates. */
3925 return SMALL_OPERAND (x
);
3931 /* The "immediate" forms of these instructions are really
3932 implemented as comparisons with register 0. */
3937 /* Likewise, meaning that the only valid immediate operand is 1. */
3941 /* We add 1 to the immediate and use SLT. */
3942 return SMALL_OPERAND (x
+ 1);
3945 /* Likewise SLTU, but reject the always-true case. */
3946 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3950 /* The bit position and size are immediate operands. */
3951 return ISA_HAS_EXT_INS
;
3954 /* By default assume that $0 can be used for 0. */
3959 /* Return the cost of binary operation X, given that the instruction
3960 sequence for a word-sized or smaller operation has cost SINGLE_COST
3961 and that the sequence of a double-word operation has cost DOUBLE_COST.
3962 If SPEED is true, optimize for speed otherwise optimize for size. */
3965 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3969 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3974 + set_src_cost (XEXP (x
, 0), GET_MODE (x
), speed
)
3975 + rtx_cost (XEXP (x
, 1), GET_MODE (x
), GET_CODE (x
), 1, speed
));
3978 /* Return the cost of floating-point multiplications of mode MODE. */
3981 mips_fp_mult_cost (machine_mode mode
)
3983 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3986 /* Return the cost of floating-point divisions of mode MODE. */
3989 mips_fp_div_cost (machine_mode mode
)
3991 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3994 /* Return the cost of sign-extending OP to mode MODE, not including the
3995 cost of OP itself. */
3998 mips_sign_extend_cost (machine_mode mode
, rtx op
)
4001 /* Extended loads are as cheap as unextended ones. */
4004 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
4005 /* A sign extension from SImode to DImode in 64-bit mode is free. */
4008 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
4009 /* We can use SEB or SEH. */
4010 return COSTS_N_INSNS (1);
4012 /* We need to use a shift left and a shift right. */
4013 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
4016 /* Return the cost of zero-extending OP to mode MODE, not including the
4017 cost of OP itself. */
4020 mips_zero_extend_cost (machine_mode mode
, rtx op
)
4023 /* Extended loads are as cheap as unextended ones. */
4026 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
4027 /* We need a shift left by 32 bits and a shift right by 32 bits. */
4028 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
4030 if (GENERATE_MIPS16E
)
4031 /* We can use ZEB or ZEH. */
4032 return COSTS_N_INSNS (1);
4035 /* We need to load 0xff or 0xffff into a register and use AND. */
4036 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
4038 /* We can use ANDI. */
4039 return COSTS_N_INSNS (1);
4042 /* Return the cost of moving between two registers of mode MODE,
4043 assuming that the move will be in pieces of at most UNITS bytes. */
4046 mips_set_reg_reg_piece_cost (machine_mode mode
, unsigned int units
)
4048 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
4051 /* Return the cost of moving between two registers of mode MODE. */
4054 mips_set_reg_reg_cost (machine_mode mode
)
4056 switch (GET_MODE_CLASS (mode
))
4059 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
4062 case MODE_COMPLEX_FLOAT
:
4063 case MODE_VECTOR_FLOAT
:
4064 if (TARGET_HARD_FLOAT
)
4065 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
4069 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
4073 /* Implement TARGET_RTX_COSTS. */
4076 mips_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
4077 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
4079 int code
= GET_CODE (x
);
4080 bool float_mode_p
= FLOAT_MODE_P (mode
);
4084 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
4085 appear in the instruction stream, and the cost of a comparison is
4086 really the cost of the branch or scc condition. At the time of
4087 writing, GCC only uses an explicit outer COMPARE code when optabs
4088 is testing whether a constant is expensive enough to force into a
4089 register. We want optabs to pass such constants through the MIPS
4090 expanders instead, so make all constants very cheap here. */
4091 if (outer_code
== COMPARE
)
4093 gcc_assert (CONSTANT_P (x
));
4101 /* Treat *clear_upper32-style ANDs as having zero cost in the
4102 second operand. The cost is entirely in the first operand.
4104 ??? This is needed because we would otherwise try to CSE
4105 the constant operand. Although that's the right thing for
4106 instructions that continue to be a register operation throughout
4107 compilation, it is disastrous for instructions that could
4108 later be converted into a memory operation. */
4110 && outer_code
== AND
4111 && UINTVAL (x
) == 0xffffffff)
4119 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
4128 /* When not optimizing for size, we care more about the cost
4129 of hot code, and hot code is often in a loop. If a constant
4130 operand needs to be forced into a register, we will often be
4131 able to hoist the constant load out of the loop, so the load
4132 should not contribute to the cost. */
4133 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
4145 if (force_to_mem_operand (x
, VOIDmode
))
4147 *total
= COSTS_N_INSNS (1);
4150 cost
= mips_const_insns (x
);
4153 /* If the constant is likely to be stored in a GPR, SETs of
4154 single-insn constants are as cheap as register sets; we
4155 never want to CSE them.
4157 Don't reduce the cost of storing a floating-point zero in
4158 FPRs. If we have a zero in an FPR for other reasons, we
4159 can get better cfg-cleanup and delayed-branch results by
4160 using it consistently, rather than using $0 sometimes and
4161 an FPR at other times. Also, moves between floating-point
4162 registers are sometimes cheaper than (D)MTC1 $0. */
4164 && outer_code
== SET
4165 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
4167 /* When non-MIPS16 code loads a constant N>1 times, we rarely
4168 want to CSE the constant itself. It is usually better to
4169 have N copies of the last operation in the sequence and one
4170 shared copy of the other operations. (Note that this is
4171 not true for MIPS16 code, where the final operation in the
4172 sequence is often an extended instruction.)
4174 Also, if we have a CONST_INT, we don't know whether it is
4175 for a word or doubleword operation, so we cannot rely on
4176 the result of mips_build_integer. */
4177 else if (!TARGET_MIPS16
4178 && (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
))
4180 *total
= COSTS_N_INSNS (cost
);
4183 /* The value will need to be fetched from the constant pool. */
4184 *total
= CONSTANT_POOL_COST
;
4188 /* If the address is legitimate, return the number of
4189 instructions it needs. */
4191 cost
= mips_address_insns (addr
, mode
, true);
4194 *total
= COSTS_N_INSNS (cost
+ 1);
4197 /* Check for a scaled indexed address. */
4198 if (mips_lwxs_address_p (addr
)
4199 || mips_lx_address_p (addr
, mode
))
4201 *total
= COSTS_N_INSNS (2);
4204 /* Otherwise use the default handling. */
4208 *total
= COSTS_N_INSNS (6);
4212 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
4216 /* Check for a *clear_upper32 pattern and treat it like a zero
4217 extension. See the pattern's comment for details. */
4220 && CONST_INT_P (XEXP (x
, 1))
4221 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
4223 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
4224 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4227 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
4229 rtx op
= XEXP (x
, 0);
4230 if (GET_CODE (op
) == ASHIFT
4231 && CONST_INT_P (XEXP (op
, 1))
4232 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
4234 *total
= COSTS_N_INSNS (1);
4235 *total
+= set_src_cost (XEXP (op
, 0), mode
, speed
);
4239 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
4240 a single instruction. */
4242 && GET_CODE (XEXP (x
, 0)) == NOT
4243 && GET_CODE (XEXP (x
, 1)) == NOT
)
4245 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
4246 *total
= (COSTS_N_INSNS (cost
)
4247 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4248 + set_src_cost (XEXP (XEXP (x
, 1), 0), mode
, speed
));
4256 /* Double-word operations use two single-word operations. */
4257 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4266 if (CONSTANT_P (XEXP (x
, 1)))
4267 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4270 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4276 *total
= mips_cost
->fp_add
;
4278 *total
= COSTS_N_INSNS (4);
4282 /* Low-part immediates need an extended MIPS16 instruction. */
4283 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
4284 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4303 /* Branch comparisons have VOIDmode, so use the first operand's
4305 mode
= GET_MODE (XEXP (x
, 0));
4306 if (FLOAT_MODE_P (mode
))
4308 *total
= mips_cost
->fp_add
;
4311 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4316 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
&& !HONOR_SIGNED_ZEROS (mode
))
4318 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4319 or *nmsub4<mode>_fastmath patterns. These patterns check for
4320 HONOR_SIGNED_ZEROS so we check here too. */
4321 rtx op0
= XEXP (x
, 0);
4322 rtx op1
= XEXP (x
, 1);
4323 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4325 *total
= (mips_fp_mult_cost (mode
)
4326 + set_src_cost (XEXP (XEXP (op0
, 0), 0), mode
, speed
)
4327 + set_src_cost (XEXP (op0
, 1), mode
, speed
)
4328 + set_src_cost (op1
, mode
, speed
));
4331 if (GET_CODE (op1
) == MULT
)
4333 *total
= (mips_fp_mult_cost (mode
)
4334 + set_src_cost (op0
, mode
, speed
)
4335 + set_src_cost (XEXP (op1
, 0), mode
, speed
)
4336 + set_src_cost (XEXP (op1
, 1), mode
, speed
));
4345 /* If this is part of a MADD or MSUB, treat the PLUS as
4347 if (ISA_HAS_UNFUSED_MADD4
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4350 *total
= mips_cost
->fp_add
;
4354 /* If it's an add + mult (which is equivalent to shift left) and
4355 it's immediate operand satisfies const_immlsa_operand predicate. */
4356 if (((ISA_HAS_LSA
&& mode
== SImode
)
4357 || (ISA_HAS_DLSA
&& mode
== DImode
))
4358 && GET_CODE (XEXP (x
, 0)) == MULT
)
4360 rtx op2
= XEXP (XEXP (x
, 0), 1);
4361 if (const_immlsa_operand (op2
, mode
))
4363 *total
= (COSTS_N_INSNS (1)
4364 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4365 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4370 /* Double-word operations require three single-word operations and
4371 an SLTU. The MIPS16 version then needs to move the result of
4372 the SLTU from $24 to a MIPS16 register. */
4373 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4374 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4379 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
)
4381 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4382 *nmsub4<mode> patterns. */
4383 rtx op
= XEXP (x
, 0);
4384 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4385 && GET_CODE (XEXP (op
, 0)) == MULT
)
4387 *total
= (mips_fp_mult_cost (mode
)
4388 + set_src_cost (XEXP (XEXP (op
, 0), 0), mode
, speed
)
4389 + set_src_cost (XEXP (XEXP (op
, 0), 1), mode
, speed
)
4390 + set_src_cost (XEXP (op
, 1), mode
, speed
));
4396 *total
= mips_cost
->fp_add
;
4398 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4402 *total
= mips_fp_mult_cost (mode
);
4407 *total
= mips_fp_mult_cost (mode
);
4408 else if (mode
== DImode
&& !TARGET_64BIT
)
4409 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4410 where the mulsidi3 always includes an MFHI and an MFLO. */
4412 ? mips_cost
->int_mult_si
* 3 + 6
4413 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4415 *total
= COSTS_N_INSNS ((ISA_HAS_MUL3
|| ISA_HAS_R6MUL
) ? 1 : 2) + 1;
4416 else if (mode
== DImode
)
4417 *total
= mips_cost
->int_mult_di
;
4419 *total
= mips_cost
->int_mult_si
;
4423 /* Check for a reciprocal. */
4425 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4426 && flag_unsafe_math_optimizations
4427 && XEXP (x
, 0) == CONST1_RTX (mode
))
4429 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4430 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4431 division as being free. */
4432 *total
= set_src_cost (XEXP (x
, 1), mode
, speed
);
4434 *total
= (mips_fp_div_cost (mode
)
4435 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4444 *total
= mips_fp_div_cost (mode
);
4453 /* It is our responsibility to make division by a power of 2
4454 as cheap as 2 register additions if we want the division
4455 expanders to be used for such operations; see the setting
4456 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4457 should always produce shorter code than using
4458 expand_sdiv2_pow2. */
4460 && CONST_INT_P (XEXP (x
, 1))
4461 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4463 *total
= COSTS_N_INSNS (2);
4464 *total
+= set_src_cost (XEXP (x
, 0), mode
, speed
);
4467 *total
= COSTS_N_INSNS (mips_idiv_insns (mode
));
4469 else if (mode
== DImode
)
4470 *total
= mips_cost
->int_div_di
;
4472 *total
= mips_cost
->int_div_si
;
4476 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4480 if (outer_code
== SET
4482 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4483 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4484 && GET_MODE (XEXP (x
, 0)) == QImode
4485 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4487 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, speed
);
4490 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4493 /* Costings for highpart multiplies. Matching patterns of the form:
4495 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4496 (sign_extend:DI (...))
4500 && (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4501 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
4502 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4503 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
4504 && GET_MODE (XEXP (x
, 0)) == DImode
)
4506 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 64
4507 && GET_MODE (XEXP (x
, 0)) == TImode
))
4508 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4509 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
4510 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
4511 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4512 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4516 *total
= COSTS_N_INSNS (1) + 1;
4517 else if (mode
== DImode
)
4518 *total
= mips_cost
->int_mult_di
;
4520 *total
= mips_cost
->int_mult_si
;
4522 /* Sign extension is free, zero extension costs for DImode when
4523 on a 64bit core / when DMUL is present. */
4524 for (int i
= 0; i
< 2; ++i
)
4526 rtx op
= XEXP (XEXP (XEXP (x
, 0), 0), i
);
4528 && GET_CODE (op
) == ZERO_EXTEND
4529 && GET_MODE (op
) == DImode
)
4530 *total
+= rtx_cost (op
, DImode
, MULT
, i
, speed
);
4532 *total
+= rtx_cost (XEXP (op
, 0), VOIDmode
, GET_CODE (op
),
4541 case UNSIGNED_FLOAT
:
4544 case FLOAT_TRUNCATE
:
4545 *total
= mips_cost
->fp_add
;
4549 if (register_operand (SET_DEST (x
), VOIDmode
)
4550 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4552 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4562 /* Implement TARGET_ADDRESS_COST. */
4565 mips_address_cost (rtx addr
, machine_mode mode
,
4566 addr_space_t as ATTRIBUTE_UNUSED
,
4567 bool speed ATTRIBUTE_UNUSED
)
4569 return mips_address_insns (addr
, mode
, false);
4572 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
4575 mips_no_speculation_in_delay_slots_p ()
4577 return TARGET_CB_MAYBE
;
4580 /* Information about a single instruction in a multi-instruction
4582 struct mips_multi_member
{
4583 /* True if this is a label, false if it is code. */
4586 /* The output_asm_insn format of the instruction. */
4589 /* The operands to the instruction. */
4590 rtx operands
[MAX_RECOG_OPERANDS
];
4592 typedef struct mips_multi_member mips_multi_member
;
4594 /* The instructions that make up the current multi-insn sequence. */
4595 static vec
<mips_multi_member
> mips_multi_members
;
4597 /* How many instructions (as opposed to labels) are in the current
4598 multi-insn sequence. */
4599 static unsigned int mips_multi_num_insns
;
4601 /* Start a new multi-insn sequence. */
4604 mips_multi_start (void)
4606 mips_multi_members
.truncate (0);
4607 mips_multi_num_insns
= 0;
4610 /* Add a new, zero initialized member to the current multi-insn sequence. */
4612 static struct mips_multi_member
*
4613 mips_multi_add (void)
4615 mips_multi_member empty
;
4616 memset (&empty
, 0, sizeof (empty
));
4617 return mips_multi_members
.safe_push (empty
);
4620 /* Add a normal insn with the given asm format to the current multi-insn
4621 sequence. The other arguments are a null-terminated list of operands. */
4624 mips_multi_add_insn (const char *format
, ...)
4626 struct mips_multi_member
*member
;
4631 member
= mips_multi_add ();
4632 member
->is_label_p
= false;
4633 member
->format
= format
;
4634 va_start (ap
, format
);
4636 while ((op
= va_arg (ap
, rtx
)))
4637 member
->operands
[i
++] = op
;
4639 mips_multi_num_insns
++;
4642 /* Add the given label definition to the current multi-insn sequence.
4643 The definition should include the colon. */
4646 mips_multi_add_label (const char *label
)
4648 struct mips_multi_member
*member
;
4650 member
= mips_multi_add ();
4651 member
->is_label_p
= true;
4652 member
->format
= label
;
4655 /* Return the index of the last member of the current multi-insn sequence. */
4658 mips_multi_last_index (void)
4660 return mips_multi_members
.length () - 1;
4663 /* Add a copy of an existing instruction to the current multi-insn
4664 sequence. I is the index of the instruction that should be copied. */
4667 mips_multi_copy_insn (unsigned int i
)
4669 struct mips_multi_member
*member
;
4671 member
= mips_multi_add ();
4672 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4673 gcc_assert (!member
->is_label_p
);
4676 /* Change the operand of an existing instruction in the current
4677 multi-insn sequence. I is the index of the instruction,
4678 OP is the index of the operand, and X is the new value. */
4681 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4683 mips_multi_members
[i
].operands
[op
] = x
;
4686 /* Write out the asm code for the current multi-insn sequence. */
4689 mips_multi_write (void)
4691 struct mips_multi_member
*member
;
4694 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4695 if (member
->is_label_p
)
4696 fprintf (asm_out_file
, "%s\n", member
->format
);
4698 output_asm_insn (member
->format
, member
->operands
);
4701 /* Return one word of double-word value OP, taking into account the fixed
4702 endianness of certain registers. HIGH_P is true to select the high part,
4703 false to select the low part. */
4706 mips_subword (rtx op
, bool high_p
)
4708 unsigned int byte
, offset
;
4711 mode
= GET_MODE (op
);
4712 if (mode
== VOIDmode
)
4713 mode
= TARGET_64BIT
? TImode
: DImode
;
4715 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4716 byte
= UNITS_PER_WORD
;
4720 if (FP_REG_RTX_P (op
))
4722 /* Paired FPRs are always ordered little-endian. */
4723 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4724 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4728 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4730 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4733 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4734 SPLIT_TYPE is the condition under which moves should be split. */
4737 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4739 return ((split_type
!= SPLIT_FOR_SPEED
4740 || mips_tuning_info
.fast_mult_zero_zero_p
)
4741 && src
== const0_rtx
4743 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4744 && (ISA_HAS_DSP_MULT
4745 ? ACC_REG_P (REGNO (dest
))
4746 : MD_REG_P (REGNO (dest
))));
4749 /* Return true if a move from SRC to DEST should be split into two.
4750 SPLIT_TYPE describes the split condition. */
4753 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4755 /* Check whether the move can be done using some variant of MULT $0,$0. */
4756 if (mips_mult_move_p (dest
, src
, split_type
))
4759 /* FPR-to-FPR moves can be done in a single instruction, if they're
4761 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4762 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4765 /* Check for floating-point loads and stores. */
4766 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4768 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4770 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4774 /* Check if MSA moves need splitting. */
4775 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest
)))
4776 return mips_split_128bit_move_p (dest
, src
);
4778 /* Otherwise split all multiword moves. */
4779 return size
> UNITS_PER_WORD
;
4782 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4783 SPLIT_TYPE describes the split condition. */
4786 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4790 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4791 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest
)))
4792 mips_split_128bit_move (dest
, src
);
4793 else if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4795 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4796 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4797 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4798 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4799 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4800 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4801 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4802 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4803 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4804 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4805 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4806 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4807 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4808 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4812 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4814 low_dest
= mips_subword (dest
, false);
4815 mips_emit_move (low_dest
, mips_subword (src
, false));
4817 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4819 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4821 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4823 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4825 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4827 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4831 /* The operation can be split into two normal moves. Decide in
4832 which order to do them. */
4833 low_dest
= mips_subword (dest
, false);
4834 if (REG_P (low_dest
)
4835 && reg_overlap_mentioned_p (low_dest
, src
))
4837 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4838 mips_emit_move (low_dest
, mips_subword (src
, false));
4842 mips_emit_move (low_dest
, mips_subword (src
, false));
4843 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4848 /* Return the split type for instruction INSN. */
4850 static enum mips_split_type
4851 mips_insn_split_type (rtx insn
)
4853 basic_block bb
= BLOCK_FOR_INSN (insn
);
4856 if (optimize_bb_for_speed_p (bb
))
4857 return SPLIT_FOR_SPEED
;
4859 return SPLIT_FOR_SIZE
;
4861 /* Once CFG information has been removed, we should trust the optimization
4862 decisions made by previous passes and only split where necessary. */
4863 return SPLIT_IF_NECESSARY
;
4866 /* Return true if a 128-bit move from SRC to DEST should be split. */
4869 mips_split_128bit_move_p (rtx dest
, rtx src
)
4871 /* MSA-to-MSA moves can be done in a single instruction. */
4872 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4875 /* Check for MSA loads and stores. */
4876 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4878 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4881 /* Check for MSA set to an immediate const vector with valid replicated
4883 if (FP_REG_RTX_P (dest
)
4884 && mips_const_vector_same_int_p (src
, GET_MODE (src
), -512, 511))
4887 /* Check for MSA load zero immediate. */
4888 if (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))
4894 /* Split a 128-bit move from SRC to DEST. */
4897 mips_split_128bit_move (rtx dest
, rtx src
)
4900 rtx low_dest
, low_src
, d
, s
;
4902 if (FP_REG_RTX_P (dest
))
4904 gcc_assert (!MEM_P (src
));
4906 rtx new_dest
= dest
;
4909 if (GET_MODE (dest
) != V4SImode
)
4910 new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
4914 if (GET_MODE (dest
) != V2DImode
)
4915 new_dest
= simplify_gen_subreg (V2DImode
, dest
, GET_MODE (dest
), 0);
4918 for (byte
= 0, index
= 0; byte
< GET_MODE_SIZE (TImode
);
4919 byte
+= UNITS_PER_WORD
, index
++)
4921 s
= mips_subword_at_byte (src
, byte
);
4923 emit_insn (gen_msa_insert_w (new_dest
, s
, new_dest
,
4924 GEN_INT (1 << index
)));
4926 emit_insn (gen_msa_insert_d (new_dest
, s
, new_dest
,
4927 GEN_INT (1 << index
)));
4930 else if (FP_REG_RTX_P (src
))
4932 gcc_assert (!MEM_P (dest
));
4937 if (GET_MODE (src
) != V4SImode
)
4938 new_src
= simplify_gen_subreg (V4SImode
, src
, GET_MODE (src
), 0);
4942 if (GET_MODE (src
) != V2DImode
)
4943 new_src
= simplify_gen_subreg (V2DImode
, src
, GET_MODE (src
), 0);
4946 for (byte
= 0, index
= 0; byte
< GET_MODE_SIZE (TImode
);
4947 byte
+= UNITS_PER_WORD
, index
++)
4949 d
= mips_subword_at_byte (dest
, byte
);
4951 emit_insn (gen_msa_copy_s_w (d
, new_src
, GEN_INT (index
)));
4953 emit_insn (gen_msa_copy_s_d (d
, new_src
, GEN_INT (index
)));
4958 low_dest
= mips_subword_at_byte (dest
, 0);
4959 low_src
= mips_subword_at_byte (src
, 0);
4960 gcc_assert (REG_P (low_dest
) && REG_P (low_src
));
4961 /* Make sure the source register is not written before reading. */
4962 if (REGNO (low_dest
) <= REGNO (low_src
))
4964 for (byte
= 0; byte
< GET_MODE_SIZE (TImode
);
4965 byte
+= UNITS_PER_WORD
)
4967 d
= mips_subword_at_byte (dest
, byte
);
4968 s
= mips_subword_at_byte (src
, byte
);
4969 mips_emit_move (d
, s
);
4974 for (byte
= GET_MODE_SIZE (TImode
) - UNITS_PER_WORD
; byte
>= 0;
4975 byte
-= UNITS_PER_WORD
)
4977 d
= mips_subword_at_byte (dest
, byte
);
4978 s
= mips_subword_at_byte (src
, byte
);
4979 mips_emit_move (d
, s
);
4985 /* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function
4986 used to generate subregs. */
4989 mips_split_msa_copy_d (rtx dest
, rtx src
, rtx index
,
4990 rtx (*gen_fn
)(rtx
, rtx
, rtx
))
4992 gcc_assert ((GET_MODE (src
) == V2DImode
&& GET_MODE (dest
) == DImode
)
4993 || (GET_MODE (src
) == V2DFmode
&& GET_MODE (dest
) == DFmode
));
4995 /* Note that low is always from the lower index, and high is always
4996 from the higher index. */
4997 rtx low
= mips_subword (dest
, false);
4998 rtx high
= mips_subword (dest
, true);
4999 rtx new_src
= simplify_gen_subreg (V4SImode
, src
, GET_MODE (src
), 0);
5001 emit_insn (gen_fn (low
, new_src
, GEN_INT (INTVAL (index
) * 2)));
5002 emit_insn (gen_fn (high
, new_src
, GEN_INT (INTVAL (index
) * 2 + 1)));
5005 /* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */
5008 mips_split_msa_insert_d (rtx dest
, rtx src1
, rtx index
, rtx src2
)
5011 gcc_assert (GET_MODE (dest
) == GET_MODE (src1
));
5012 gcc_assert ((GET_MODE (dest
) == V2DImode
5013 && (GET_MODE (src2
) == DImode
|| src2
== const0_rtx
))
5014 || (GET_MODE (dest
) == V2DFmode
&& GET_MODE (src2
) == DFmode
));
5016 /* Note that low is always from the lower index, and high is always
5017 from the higher index. */
5018 rtx low
= mips_subword (src2
, false);
5019 rtx high
= mips_subword (src2
, true);
5020 rtx new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
5021 rtx new_src1
= simplify_gen_subreg (V4SImode
, src1
, GET_MODE (src1
), 0);
5022 i
= exact_log2 (INTVAL (index
));
5023 gcc_assert (i
!= -1);
5025 emit_insn (gen_msa_insert_w (new_dest
, low
, new_src1
,
5026 GEN_INT (1 << (i
* 2))));
5027 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
,
5028 GEN_INT (1 << (i
* 2 + 1))));
5034 mips_split_msa_fill_d (rtx dest
, rtx src
)
5036 gcc_assert ((GET_MODE (dest
) == V2DImode
5037 && (GET_MODE (src
) == DImode
|| src
== const0_rtx
))
5038 || (GET_MODE (dest
) == V2DFmode
&& GET_MODE (src
) == DFmode
));
5040 /* Note that low is always from the lower index, and high is always
5041 from the higher index. */
5043 if (src
== const0_rtx
)
5050 low
= mips_subword (src
, false);
5051 high
= mips_subword (src
, true);
5053 rtx new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
5054 emit_insn (gen_msa_fill_w (new_dest
, low
));
5055 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
, GEN_INT (1 << 1)));
5056 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
, GEN_INT (1 << 3)));
5059 /* Return true if a move from SRC to DEST in INSN should be split. */
5062 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
5064 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
5067 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
5071 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
5073 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
5076 /* Return the appropriate instructions to move SRC into DEST. Assume
5077 that SRC is operand 1 and DEST is operand 0. */
5080 mips_output_move (rtx dest
, rtx src
)
5082 enum rtx_code dest_code
= GET_CODE (dest
);
5083 enum rtx_code src_code
= GET_CODE (src
);
5084 machine_mode mode
= GET_MODE (dest
);
5085 bool dbl_p
= (GET_MODE_SIZE (mode
) == 8);
5086 bool msa_p
= MSA_SUPPORTED_MODE_P (mode
);
5087 enum mips_symbol_type symbol_type
;
5089 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
5093 && dest_code
== REG
&& FP_REG_P (REGNO (dest
))
5094 && src_code
== CONST_VECTOR
5095 && CONST_INT_P (CONST_VECTOR_ELT (src
, 0)))
5097 gcc_assert (mips_const_vector_same_int_p (src
, mode
, -512, 511));
5098 return "ldi.%v0\t%w0,%E1";
5101 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
5102 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
5104 if (dest_code
== REG
)
5106 if (GP_REG_P (REGNO (dest
)))
5107 return "move\t%0,%z1";
5109 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
5111 if (ISA_HAS_DSP_MULT
)
5112 return "mult\t%q0,%.,%.";
5114 return "mult\t%.,%.";
5117 /* Moves to HI are handled by special .md insns. */
5118 if (REGNO (dest
) == LO_REGNUM
)
5121 if (DSP_ACC_REG_P (REGNO (dest
)))
5123 static char retval
[] = "mt__\t%z1,%q0";
5125 retval
[2] = reg_names
[REGNO (dest
)][4];
5126 retval
[3] = reg_names
[REGNO (dest
)][5];
5130 if (FP_REG_P (REGNO (dest
)))
5134 gcc_assert (src
== CONST0_RTX (GET_MODE (src
)));
5135 return "ldi.%v0\t%w0,0";
5138 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
5141 if (ALL_COP_REG_P (REGNO (dest
)))
5143 static char retval
[] = "dmtc_\t%z1,%0";
5145 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
5146 return dbl_p
? retval
: retval
+ 1;
5149 if (dest_code
== MEM
)
5150 switch (GET_MODE_SIZE (mode
))
5152 case 1: return "sb\t%z1,%0";
5153 case 2: return "sh\t%z1,%0";
5154 case 4: return "sw\t%z1,%0";
5155 case 8: return "sd\t%z1,%0";
5156 default: gcc_unreachable ();
5159 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
5161 if (src_code
== REG
)
5163 /* Moves from HI are handled by special .md insns. */
5164 if (REGNO (src
) == LO_REGNUM
)
5166 /* When generating VR4120 or VR4130 code, we use MACC and
5167 DMACC instead of MFLO. This avoids both the normal
5168 MIPS III HI/LO hazards and the errata related to
5171 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
5175 if (DSP_ACC_REG_P (REGNO (src
)))
5177 static char retval
[] = "mf__\t%0,%q1";
5179 retval
[2] = reg_names
[REGNO (src
)][4];
5180 retval
[3] = reg_names
[REGNO (src
)][5];
5184 if (FP_REG_P (REGNO (src
)))
5186 gcc_assert (!msa_p
);
5187 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
5190 if (ALL_COP_REG_P (REGNO (src
)))
5192 static char retval
[] = "dmfc_\t%0,%1";
5194 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
5195 return dbl_p
? retval
: retval
+ 1;
5199 if (src_code
== MEM
)
5200 switch (GET_MODE_SIZE (mode
))
5202 case 1: return "lbu\t%0,%1";
5203 case 2: return "lhu\t%0,%1";
5204 case 4: return "lw\t%0,%1";
5205 case 8: return "ld\t%0,%1";
5206 default: gcc_unreachable ();
5209 if (src_code
== CONST_INT
)
5211 /* Don't use the X format for the operand itself, because that
5212 will give out-of-range numbers for 64-bit hosts and 32-bit
5215 return "li\t%0,%1\t\t\t# %X1";
5217 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
5220 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
5224 if (src_code
== HIGH
)
5225 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
5227 if (CONST_GP_P (src
))
5228 return "move\t%0,%1";
5230 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
5231 && mips_lo_relocs
[symbol_type
] != 0)
5233 /* A signed 16-bit constant formed by applying a relocation
5234 operator to a symbolic address. */
5235 gcc_assert (!mips_split_p
[symbol_type
]);
5236 return "li\t%0,%R1";
5239 if (symbolic_operand (src
, VOIDmode
))
5241 gcc_assert (TARGET_MIPS16
5242 ? TARGET_MIPS16_TEXT_LOADS
5243 : !TARGET_EXPLICIT_RELOCS
);
5244 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
5247 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
5249 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
5251 if (GET_MODE (dest
) == V2SFmode
)
5252 return "mov.ps\t%0,%1";
5254 return "move.v\t%w0,%w1";
5256 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
5259 if (dest_code
== MEM
)
5262 return "st.%v1\t%w1,%0";
5264 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
5267 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
5269 if (src_code
== MEM
)
5272 return "ld.%v0\t%w0,%1";
5274 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
5277 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
5279 static char retval
[] = "l_c_\t%0,%1";
5281 retval
[1] = (dbl_p
? 'd' : 'w');
5282 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
5285 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
5287 static char retval
[] = "s_c_\t%1,%0";
5289 retval
[1] = (dbl_p
? 'd' : 'w');
5290 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
5296 /* Return true if CMP1 is a suitable second operand for integer ordering
5297 test CODE. See also the *sCC patterns in mips.md. */
5300 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
5306 return reg_or_0_operand (cmp1
, VOIDmode
);
5310 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
5314 return arith_operand (cmp1
, VOIDmode
);
5317 return sle_operand (cmp1
, VOIDmode
);
5320 return sleu_operand (cmp1
, VOIDmode
);
5327 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
5328 integer ordering test *CODE, or if an equivalent combination can
5329 be formed by adjusting *CODE and *CMP1. When returning true, update
5330 *CODE and *CMP1 with the chosen code and operand, otherwise leave
5334 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
5337 HOST_WIDE_INT plus_one
;
5339 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
5342 if (CONST_INT_P (*cmp1
))
5346 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
5347 if (INTVAL (*cmp1
) < plus_one
)
5350 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
5356 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
5360 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
5371 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
5372 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
5373 is nonnull, it's OK to set TARGET to the inverse of the result and
5374 flip *INVERT_PTR instead. */
5377 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
5378 rtx target
, rtx cmp0
, rtx cmp1
)
5382 /* First see if there is a MIPS instruction that can do this operation.
5383 If not, try doing the same for the inverse operation. If that also
5384 fails, force CMP1 into a register and try again. */
5385 mode
= GET_MODE (cmp0
);
5386 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
5387 mips_emit_binary (code
, target
, cmp0
, cmp1
);
5390 enum rtx_code inv_code
= reverse_condition (code
);
5391 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
5393 cmp1
= force_reg (mode
, cmp1
);
5394 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
5396 else if (invert_ptr
== 0)
5400 inv_target
= mips_force_binary (GET_MODE (target
),
5401 inv_code
, cmp0
, cmp1
);
5402 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
5406 *invert_ptr
= !*invert_ptr
;
5407 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
5412 /* Return a register that is zero iff CMP0 and CMP1 are equal.
5413 The register will have the same mode as CMP0. */
5416 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
5418 if (cmp1
== const0_rtx
)
5421 if (uns_arith_operand (cmp1
, VOIDmode
))
5422 return expand_binop (GET_MODE (cmp0
), xor_optab
,
5423 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
5425 return expand_binop (GET_MODE (cmp0
), sub_optab
,
5426 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
5429 /* Convert *CODE into a code that can be used in a floating-point
5430 scc instruction (C.cond.fmt). Return true if the values of
5431 the condition code registers will be inverted, with 0 indicating
5432 that the condition holds. */
5435 mips_reversed_fp_cond (enum rtx_code
*code
)
5442 *code
= reverse_condition_maybe_unordered (*code
);
5450 /* Allocate a floating-point condition-code register of mode MODE.
5452 These condition code registers are used for certain kinds
5453 of compound operation, such as compare and branches, vconds,
5454 and built-in functions. At expand time, their use is entirely
5455 controlled by MIPS-specific code and is entirely internal
5456 to these compound operations.
5458 We could (and did in the past) expose condition-code values
5459 as pseudo registers and leave the register allocator to pick
5460 appropriate registers. The problem is that it is not practically
5461 possible for the rtl optimizers to guarantee that no spills will
5462 be needed, even when AVOID_CCMODE_COPIES is defined. We would
5463 therefore need spill and reload sequences to handle the worst case.
5465 Although such sequences do exist, they are very expensive and are
5466 not something we'd want to use. This is especially true of CCV2 and
5467 CCV4, where all the shuffling would greatly outweigh whatever benefit
5468 the vectorization itself provides.
5470 The main benefit of having more than one condition-code register
5471 is to allow the pipelining of operations, especially those involving
5472 comparisons and conditional moves. We don't really expect the
5473 registers to be live for long periods, and certainly never want
5474 them to be live across calls.
5476 Also, there should be no penalty attached to using all the available
5477 registers. They are simply bits in the same underlying FPU control
5480 We therefore expose the hardware registers from the outset and use
5481 a simple round-robin allocation scheme. */
5484 mips_allocate_fcc (machine_mode mode
)
5486 unsigned int regno
, count
;
5488 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
5492 else if (mode
== CCV2mode
)
5494 else if (mode
== CCV4mode
)
5499 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
5500 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
5501 cfun
->machine
->next_fcc
= 0;
5502 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
5503 cfun
->machine
->next_fcc
+= count
;
5504 return gen_rtx_REG (mode
, regno
);
5507 /* Convert a comparison into something that can be used in a branch or
5508 conditional move. On entry, *OP0 and *OP1 are the values being
5509 compared and *CODE is the code used to compare them.
5511 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5512 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5513 otherwise any standard branch condition can be used. The standard branch
5516 - EQ or NE between two registers.
5517 - any comparison between a register and zero.
5518 - if compact branches are available then any condition is valid. */
5521 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
5526 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
5528 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
5530 else if (*code
== EQ
|| *code
== NE
)
5534 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
5538 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5540 else if (!need_eq_ne_p
&& TARGET_CB_MAYBE
)
5570 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5580 /* The comparison needs a separate scc instruction. Store the
5581 result of the scc in *OP0 and compare it against zero. */
5582 bool invert
= false;
5583 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
5584 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
5585 *code
= (invert
? EQ
: NE
);
5589 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
5591 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
5592 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
5598 enum rtx_code cmp_code
;
5600 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5601 comparison to set a register. The branch or conditional move will
5602 then compare that register against zero.
5604 Set CMP_CODE to the code of the comparison instruction and
5605 *CODE to the code that the branch or move should use. */
5609 /* All FP conditions can be implemented directly with CMP.cond.fmt
5610 or by reversing the operands. */
5612 *op0
= gen_reg_rtx (CCFmode
);
5616 /* Three FP conditions cannot be implemented by reversing the
5617 operands for C.cond.fmt, instead a reversed condition code is
5618 required and a test for false. */
5619 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
5621 *op0
= mips_allocate_fcc (CCmode
);
5623 *op0
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
5627 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
5631 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5632 and OPERAND[3]. Store the result in OPERANDS[0].
5634 On 64-bit targets, the mode of the comparison and target will always be
5635 SImode, thus possibly narrower than that of the comparison's operands. */
5638 mips_expand_scc (rtx operands
[])
5640 rtx target
= operands
[0];
5641 enum rtx_code code
= GET_CODE (operands
[1]);
5642 rtx op0
= operands
[2];
5643 rtx op1
= operands
[3];
5645 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5647 if (code
== EQ
|| code
== NE
)
5650 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5651 mips_emit_binary (code
, target
, op0
, op1
);
5654 rtx zie
= mips_zero_if_equal (op0
, op1
);
5655 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5659 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5662 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5663 CODE and jump to OPERANDS[3] if the condition holds. */
5666 mips_expand_conditional_branch (rtx
*operands
)
5668 enum rtx_code code
= GET_CODE (operands
[0]);
5669 rtx op0
= operands
[1];
5670 rtx op1
= operands
[2];
5673 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5674 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5675 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5680 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5681 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5684 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5685 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5690 reversed_p
= mips_reversed_fp_cond (&cond
);
5691 cmp_result
= mips_allocate_fcc (CCV2mode
);
5692 emit_insn (gen_scc_ps (cmp_result
,
5693 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5695 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5698 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5702 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5703 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5706 mips_expand_conditional_move (rtx
*operands
)
5709 enum rtx_code code
= GET_CODE (operands
[1]);
5710 rtx op0
= XEXP (operands
[1], 0);
5711 rtx op1
= XEXP (operands
[1], 1);
5713 mips_emit_compare (&code
, &op0
, &op1
, true);
5714 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5716 /* There is no direct support for general conditional GP move involving
5717 two registers using SEL. */
5719 && INTEGRAL_MODE_P (GET_MODE (operands
[2]))
5720 && register_operand (operands
[2], VOIDmode
)
5721 && register_operand (operands
[3], VOIDmode
))
5723 machine_mode mode
= GET_MODE (operands
[0]);
5724 rtx temp
= gen_reg_rtx (mode
);
5725 rtx temp2
= gen_reg_rtx (mode
);
5727 emit_insn (gen_rtx_SET (temp
,
5728 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5729 operands
[2], const0_rtx
)));
5731 /* Flip the test for the second operand. */
5732 cond
= gen_rtx_fmt_ee ((code
== EQ
) ? NE
: EQ
, GET_MODE (op0
), op0
, op1
);
5734 emit_insn (gen_rtx_SET (temp2
,
5735 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5736 operands
[3], const0_rtx
)));
5738 /* Merge the two results, at least one is guaranteed to be zero. */
5739 emit_insn (gen_rtx_SET (operands
[0], gen_rtx_IOR (mode
, temp
, temp2
)));
5743 if (FLOAT_MODE_P (GET_MODE (operands
[2])) && !ISA_HAS_SEL
)
5745 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5746 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5749 emit_insn (gen_rtx_SET (operands
[0],
5750 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5751 operands
[2], operands
[3])));
5755 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5758 mips_expand_conditional_trap (rtx comparison
)
5764 /* MIPS conditional trap instructions don't have GT or LE flavors,
5765 so we must swap the operands and convert to LT and GE respectively. */
5766 code
= GET_CODE (comparison
);
5773 code
= swap_condition (code
);
5774 op0
= XEXP (comparison
, 1);
5775 op1
= XEXP (comparison
, 0);
5779 op0
= XEXP (comparison
, 0);
5780 op1
= XEXP (comparison
, 1);
5784 mode
= GET_MODE (XEXP (comparison
, 0));
5785 op0
= force_reg (mode
, op0
);
5786 if (!(ISA_HAS_COND_TRAPI
5787 ? arith_operand (op1
, mode
)
5788 : reg_or_0_operand (op1
, mode
)))
5789 op1
= force_reg (mode
, op1
);
5791 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5792 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5796 /* Initialize *CUM for a call to a function of type FNTYPE. */
5799 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5801 memset (cum
, 0, sizeof (*cum
));
5802 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5803 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5806 /* Fill INFO with information about a single argument. CUM is the
5807 cumulative state for earlier arguments. MODE is the mode of this
5808 argument and TYPE is its type (if known). NAMED is true if this
5809 is a named (fixed) argument rather than a variable one. */
5812 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5813 machine_mode mode
, const_tree type
, bool named
)
5815 bool doubleword_aligned_p
;
5816 unsigned int num_bytes
, num_words
, max_regs
;
5818 /* Work out the size of the argument. */
5819 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5820 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5822 /* Decide whether it should go in a floating-point register, assuming
5823 one is free. Later code checks for availability.
5825 The checks against UNITS_PER_FPVALUE handle the soft-float and
5826 single-float cases. */
5830 /* The EABI conventions have traditionally been defined in terms
5831 of TYPE_MODE, regardless of the actual type. */
5832 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5833 || mode
== V2SFmode
)
5834 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5839 /* Only leading floating-point scalars are passed in
5840 floating-point registers. We also handle vector floats the same
5841 say, which is OK because they are not covered by the standard ABI. */
5842 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5843 info
->fpr_p
= (!cum
->gp_reg_found
5844 && cum
->arg_number
< 2
5846 || SCALAR_FLOAT_TYPE_P (type
)
5847 || VECTOR_FLOAT_TYPE_P (type
))
5848 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5849 || mode
== V2SFmode
)
5850 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5855 /* Scalar, complex and vector floating-point types are passed in
5856 floating-point registers, as long as this is a named rather
5857 than a variable argument. */
5858 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5859 info
->fpr_p
= (named
5860 && (type
== 0 || FLOAT_TYPE_P (type
))
5861 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5862 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5863 || mode
== V2SFmode
)
5864 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5866 /* ??? According to the ABI documentation, the real and imaginary
5867 parts of complex floats should be passed in individual registers.
5868 The real and imaginary parts of stack arguments are supposed
5869 to be contiguous and there should be an extra word of padding
5872 This has two problems. First, it makes it impossible to use a
5873 single "void *" va_list type, since register and stack arguments
5874 are passed differently. (At the time of writing, MIPSpro cannot
5875 handle complex float varargs correctly.) Second, it's unclear
5876 what should happen when there is only one register free.
5878 For now, we assume that named complex floats should go into FPRs
5879 if there are two FPRs free, otherwise they should be passed in the
5880 same way as a struct containing two floats. */
5882 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5883 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5885 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5886 info
->fpr_p
= false;
5896 /* See whether the argument has doubleword alignment. */
5897 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5900 /* Set REG_OFFSET to the register count we're interested in.
5901 The EABI allocates the floating-point registers separately,
5902 but the other ABIs allocate them like integer registers. */
5903 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5907 /* Advance to an even register if the argument is doubleword-aligned. */
5908 if (doubleword_aligned_p
)
5909 info
->reg_offset
+= info
->reg_offset
& 1;
5911 /* Work out the offset of a stack argument. */
5912 info
->stack_offset
= cum
->stack_words
;
5913 if (doubleword_aligned_p
)
5914 info
->stack_offset
+= info
->stack_offset
& 1;
5916 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5918 /* Partition the argument between registers and stack. */
5919 info
->reg_words
= MIN (num_words
, max_regs
);
5920 info
->stack_words
= num_words
- info
->reg_words
;
5923 /* INFO describes a register argument that has the normal format for the
5924 argument's mode. Return the register it uses, assuming that FPRs are
5925 available if HARD_FLOAT_P. */
5928 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5930 if (!info
->fpr_p
|| !hard_float_p
)
5931 return GP_ARG_FIRST
+ info
->reg_offset
;
5932 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5933 /* In o32, the second argument is always passed in $f14
5934 for TARGET_DOUBLE_FLOAT, regardless of whether the
5935 first argument was a word or doubleword. */
5936 return FP_ARG_FIRST
+ 2;
5938 return FP_ARG_FIRST
+ info
->reg_offset
;
5941 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5944 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5946 return !TARGET_OLDABI
;
5949 /* Implement TARGET_FUNCTION_ARG. */
5952 mips_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
5953 const_tree type
, bool named
)
5955 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5956 struct mips_arg_info info
;
5958 /* We will be called with a mode of VOIDmode after the last argument
5959 has been seen. Whatever we return will be passed to the call expander.
5960 If we need a MIPS16 fp_code, return a REG with the code stored as
5962 if (mode
== VOIDmode
)
5964 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5965 return gen_rtx_REG ((machine_mode
) cum
->fp_code
, 0);
5970 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5972 /* Return straight away if the whole argument is passed on the stack. */
5973 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5976 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5977 contains a double in its entirety, then that 64-bit chunk is passed
5978 in a floating-point register. */
5980 && TARGET_HARD_FLOAT
5983 && TREE_CODE (type
) == RECORD_TYPE
5984 && TYPE_SIZE_UNIT (type
)
5985 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5989 /* First check to see if there is any such field. */
5990 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5991 if (TREE_CODE (field
) == FIELD_DECL
5992 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5993 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5994 && tree_fits_shwi_p (bit_position (field
))
5995 && int_bit_position (field
) % BITS_PER_WORD
== 0)
6000 /* Now handle the special case by returning a PARALLEL
6001 indicating where each 64-bit chunk goes. INFO.REG_WORDS
6002 chunks are passed in registers. */
6004 HOST_WIDE_INT bitpos
;
6007 /* assign_parms checks the mode of ENTRY_PARM, so we must
6008 use the actual mode here. */
6009 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
6012 field
= TYPE_FIELDS (type
);
6013 for (i
= 0; i
< info
.reg_words
; i
++)
6017 for (; field
; field
= DECL_CHAIN (field
))
6018 if (TREE_CODE (field
) == FIELD_DECL
6019 && int_bit_position (field
) >= bitpos
)
6023 && int_bit_position (field
) == bitpos
6024 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
6025 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
6026 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
6028 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
6031 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
6032 GEN_INT (bitpos
/ BITS_PER_UNIT
));
6034 bitpos
+= BITS_PER_WORD
;
6040 /* Handle the n32/n64 conventions for passing complex floating-point
6041 arguments in FPR pairs. The real part goes in the lower register
6042 and the imaginary part goes in the upper register. */
6045 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6051 inner
= GET_MODE_INNER (mode
);
6052 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
6053 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
6055 /* Real part in registers, imaginary part on stack. */
6056 gcc_assert (info
.stack_words
== info
.reg_words
);
6057 return gen_rtx_REG (inner
, regno
);
6061 gcc_assert (info
.stack_words
== 0);
6062 real
= gen_rtx_EXPR_LIST (VOIDmode
,
6063 gen_rtx_REG (inner
, regno
),
6065 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
6067 regno
+ info
.reg_words
/ 2),
6068 GEN_INT (GET_MODE_SIZE (inner
)));
6069 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
6073 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
6076 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
6079 mips_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
6080 const_tree type
, bool named
)
6082 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6083 struct mips_arg_info info
;
6085 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
6088 cum
->gp_reg_found
= true;
6090 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
6091 an explanation of what this code does. It assumes that we're using
6092 either the o32 or the o64 ABI, both of which pass at most 2 arguments
6094 if (cum
->arg_number
< 2 && info
.fpr_p
)
6095 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
6097 /* Advance the register count. This has the effect of setting
6098 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
6099 argument required us to skip the final GPR and pass the whole
6100 argument on the stack. */
6101 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
6102 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
6103 else if (info
.reg_words
> 0)
6104 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
6106 /* Advance the stack word count. */
6107 if (info
.stack_words
> 0)
6108 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
6113 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6116 mips_arg_partial_bytes (cumulative_args_t cum
,
6117 machine_mode mode
, tree type
, bool named
)
6119 struct mips_arg_info info
;
6121 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
6122 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
6125 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
6126 least PARM_BOUNDARY bits of alignment, but will be given anything up
6127 to STACK_BOUNDARY bits if the type requires it. */
6130 mips_function_arg_boundary (machine_mode mode
, const_tree type
)
6132 unsigned int alignment
;
6134 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
6135 if (alignment
< PARM_BOUNDARY
)
6136 alignment
= PARM_BOUNDARY
;
6137 if (alignment
> STACK_BOUNDARY
)
6138 alignment
= STACK_BOUNDARY
;
6142 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
6144 static fixed_size_mode
6145 mips_get_reg_raw_mode (int regno
)
6147 if (TARGET_FLOATXX
&& FP_REG_P (regno
))
6149 return default_get_reg_raw_mode (regno
);
6152 /* Implement TARGET_FUNCTION_ARG_PADDING; return PAD_UPWARD if the first
6153 byte of the stack slot has useful data, PAD_DOWNWARD if the last byte
6156 static pad_direction
6157 mips_function_arg_padding (machine_mode mode
, const_tree type
)
6159 /* On little-endian targets, the first byte of every stack argument
6160 is passed in the first byte of the stack slot. */
6161 if (!BYTES_BIG_ENDIAN
)
6164 /* Otherwise, integral types are padded downward: the last byte of a
6165 stack argument is passed in the last byte of the stack slot. */
6167 ? (INTEGRAL_TYPE_P (type
)
6168 || POINTER_TYPE_P (type
)
6169 || FIXED_POINT_TYPE_P (type
))
6170 : (SCALAR_INT_MODE_P (mode
)
6171 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
6172 return PAD_DOWNWARD
;
6174 /* Big-endian o64 pads floating-point arguments downward. */
6175 if (mips_abi
== ABI_O64
)
6176 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6177 return PAD_DOWNWARD
;
6179 /* Other types are padded upward for o32, o64, n32 and n64. */
6180 if (mips_abi
!= ABI_EABI
)
6183 /* Arguments smaller than a stack slot are padded downward. */
6185 ? GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
6186 : int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
))
6189 return PAD_DOWNWARD
;
6192 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
6193 if the least significant byte of the register has useful data. Return
6194 the opposite if the most significant byte does. */
6197 mips_pad_reg_upward (machine_mode mode
, tree type
)
6199 /* No shifting is required for floating-point arguments. */
6200 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6201 return !BYTES_BIG_ENDIAN
;
6203 /* Otherwise, apply the same padding to register arguments as we do
6204 to stack arguments. */
6205 return mips_function_arg_padding (mode
, type
) == PAD_UPWARD
;
6208 /* Return nonzero when an argument must be passed by reference. */
6211 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6212 machine_mode mode
, const_tree type
,
6213 bool named ATTRIBUTE_UNUSED
)
6215 if (mips_abi
== ABI_EABI
)
6219 /* ??? How should SCmode be handled? */
6220 if (mode
== DImode
|| mode
== DFmode
6221 || mode
== DQmode
|| mode
== UDQmode
6222 || mode
== DAmode
|| mode
== UDAmode
)
6225 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
6226 return size
== -1 || size
> UNITS_PER_WORD
;
6230 /* If we have a variable-sized parameter, we have no choice. */
6231 return targetm
.calls
.must_pass_in_stack (mode
, type
);
6235 /* Implement TARGET_CALLEE_COPIES. */
6238 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6239 machine_mode mode ATTRIBUTE_UNUSED
,
6240 const_tree type ATTRIBUTE_UNUSED
, bool named
)
6242 return mips_abi
== ABI_EABI
&& named
;
6245 /* See whether VALTYPE is a record whose fields should be returned in
6246 floating-point registers. If so, return the number of fields and
6247 list them in FIELDS (which should have two elements). Return 0
6250 For n32 & n64, a structure with one or two fields is returned in
6251 floating-point registers as long as every field has a floating-point
6255 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
6263 if (TREE_CODE (valtype
) != RECORD_TYPE
)
6267 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
6269 if (TREE_CODE (field
) != FIELD_DECL
)
6272 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
6278 fields
[i
++] = field
;
6283 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6284 a value in the most significant part of $2/$3 if:
6286 - the target is big-endian;
6288 - the value has a structure or union type (we generalize this to
6289 cover aggregates from other languages too); and
6291 - the structure is not returned in floating-point registers. */
6294 mips_return_in_msb (const_tree valtype
)
6298 return (TARGET_NEWABI
6299 && TARGET_BIG_ENDIAN
6300 && AGGREGATE_TYPE_P (valtype
)
6301 && mips_fpr_return_fields (valtype
, fields
) == 0);
6304 /* Return true if the function return value MODE will get returned in a
6305 floating-point register. */
6308 mips_return_mode_in_fpr_p (machine_mode mode
)
6310 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
6311 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
6313 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6314 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
6317 /* Return the representation of an FPR return register when the
6318 value being returned in FP_RETURN has mode VALUE_MODE and the
6319 return type itself has mode TYPE_MODE. On NewABI targets,
6320 the two modes may be different for structures like:
6322 struct __attribute__((packed)) foo { float f; }
6324 where we return the SFmode value of "f" in FP_RETURN, but where
6325 the structure itself has mode BLKmode. */
6328 mips_return_fpr_single (machine_mode type_mode
,
6329 machine_mode value_mode
)
6333 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
6334 if (type_mode
!= value_mode
)
6336 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
6337 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
6342 /* Return a composite value in a pair of floating-point registers.
6343 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6344 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6347 For n32 & n64, $f0 always holds the first value and $f2 the second.
6348 Otherwise the values are packed together as closely as possible. */
6351 mips_return_fpr_pair (machine_mode mode
,
6352 machine_mode mode1
, HOST_WIDE_INT offset1
,
6353 machine_mode mode2
, HOST_WIDE_INT offset2
)
6357 inc
= (TARGET_NEWABI
|| mips_abi
== ABI_32
? 2 : MAX_FPRS_PER_FMT
);
6358 return gen_rtx_PARALLEL
6361 gen_rtx_EXPR_LIST (VOIDmode
,
6362 gen_rtx_REG (mode1
, FP_RETURN
),
6364 gen_rtx_EXPR_LIST (VOIDmode
,
6365 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
6366 GEN_INT (offset2
))));
6370 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
6371 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
6372 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
6375 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
6384 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
6385 func
= fn_decl_or_type
;
6389 mode
= TYPE_MODE (valtype
);
6390 unsigned_p
= TYPE_UNSIGNED (valtype
);
6392 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
6393 return values, promote the mode here too. */
6394 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
6396 /* Handle structures whose fields are returned in $f0/$f2. */
6397 switch (mips_fpr_return_fields (valtype
, fields
))
6400 return mips_return_fpr_single (mode
,
6401 TYPE_MODE (TREE_TYPE (fields
[0])));
6404 return mips_return_fpr_pair (mode
,
6405 TYPE_MODE (TREE_TYPE (fields
[0])),
6406 int_byte_position (fields
[0]),
6407 TYPE_MODE (TREE_TYPE (fields
[1])),
6408 int_byte_position (fields
[1]));
6411 /* If a value is passed in the most significant part of a register, see
6412 whether we have to round the mode up to a whole number of words. */
6413 if (mips_return_in_msb (valtype
))
6415 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
6416 if (size
% UNITS_PER_WORD
!= 0)
6418 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
6419 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).require ();
6423 /* For EABI, the class of return register depends entirely on MODE.
6424 For example, "struct { some_type x; }" and "union { some_type x; }"
6425 are returned in the same way as a bare "some_type" would be.
6426 Other ABIs only use FPRs for scalar, complex or vector types. */
6427 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
6428 return gen_rtx_REG (mode
, GP_RETURN
);
6433 /* Handle long doubles for n32 & n64. */
6435 return mips_return_fpr_pair (mode
,
6437 DImode
, GET_MODE_SIZE (mode
) / 2);
6439 if (mips_return_mode_in_fpr_p (mode
))
6441 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6442 return mips_return_fpr_pair (mode
,
6443 GET_MODE_INNER (mode
), 0,
6444 GET_MODE_INNER (mode
),
6445 GET_MODE_SIZE (mode
) / 2);
6447 return gen_rtx_REG (mode
, FP_RETURN
);
6451 return gen_rtx_REG (mode
, GP_RETURN
);
6454 /* Implement TARGET_FUNCTION_VALUE. */
6457 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
6458 bool outgoing ATTRIBUTE_UNUSED
)
6460 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
6463 /* Implement TARGET_LIBCALL_VALUE. */
6466 mips_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
6468 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
6471 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
6473 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
6476 mips_function_value_regno_p (const unsigned int regno
)
6478 /* Most types only require one GPR or one FPR for return values but for
6479 hard-float two FPRs can be used for _Complex types (for all ABIs)
6480 and long doubles (for n64). */
6481 if (regno
== GP_RETURN
6482 || regno
== FP_RETURN
6483 || (FP_RETURN
!= GP_RETURN
6484 && regno
== FP_RETURN
+ 2))
6487 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
6488 This does not apply to o32 FPXX as floating-point function argument and
6489 return registers are described as 64-bit even though floating-point
6490 registers are primarily described as 32-bit internally.
6491 See: mips_get_reg_raw_mode. */
6492 if ((mips_abi
== ABI_32
&& TARGET_FLOAT32
)
6493 && FP_RETURN
!= GP_RETURN
6494 && (regno
== FP_RETURN
+ 1
6495 || regno
== FP_RETURN
+ 3))
6501 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
6502 all BLKmode objects are returned in memory. Under the n32, n64
6503 and embedded ABIs, small structures are returned in a register.
6504 Objects with varying size must still be returned in memory, of
6508 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
6511 /* Ensure that any floating point vector types are returned via memory
6512 even if they are supported through a vector mode with some ASEs. */
6513 return (VECTOR_FLOAT_TYPE_P (type
)
6514 || TYPE_MODE (type
) == BLKmode
);
6516 return (!IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
6519 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6522 mips_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
6523 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6526 CUMULATIVE_ARGS local_cum
;
6527 int gp_saved
, fp_saved
;
6529 /* The caller has advanced CUM up to, but not beyond, the last named
6530 argument. Advance a local copy of CUM past the last "real" named
6531 argument, to find out how many registers are left over. */
6532 local_cum
= *get_cumulative_args (cum
);
6533 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
6536 /* Found out how many registers we need to save. */
6537 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
6538 fp_saved
= (EABI_FLOAT_VARARGS_P
6539 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
6548 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
6549 REG_PARM_STACK_SPACE (cfun
->decl
)
6550 - gp_saved
* UNITS_PER_WORD
);
6551 mem
= gen_frame_mem (BLKmode
, ptr
);
6552 set_mem_alias_set (mem
, get_varargs_alias_set ());
6554 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
6559 /* We can't use move_block_from_reg, because it will use
6564 /* Set OFF to the offset from virtual_incoming_args_rtx of
6565 the first float register. The FP save area lies below
6566 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6567 off
= ROUND_DOWN (-gp_saved
* UNITS_PER_WORD
, UNITS_PER_FPVALUE
);
6568 off
-= fp_saved
* UNITS_PER_FPREG
;
6570 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6572 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
6573 i
+= MAX_FPRS_PER_FMT
)
6577 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
6578 mem
= gen_frame_mem (mode
, ptr
);
6579 set_mem_alias_set (mem
, get_varargs_alias_set ());
6580 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
6581 off
+= UNITS_PER_HWFPVALUE
;
6585 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
6586 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
6587 + fp_saved
* UNITS_PER_FPREG
);
6590 /* Implement TARGET_BUILTIN_VA_LIST. */
6593 mips_build_builtin_va_list (void)
6595 if (EABI_FLOAT_VARARGS_P
)
6597 /* We keep 3 pointers, and two offsets.
6599 Two pointers are to the overflow area, which starts at the CFA.
6600 One of these is constant, for addressing into the GPR save area
6601 below it. The other is advanced up the stack through the
6604 The third pointer is to the bottom of the GPR save area.
6605 Since the FPR save area is just below it, we can address
6606 FPR slots off this pointer.
6608 We also keep two one-byte offsets, which are to be subtracted
6609 from the constant pointers to yield addresses in the GPR and
6610 FPR save areas. These are downcounted as float or non-float
6611 arguments are used, and when they get to zero, the argument
6612 must be obtained from the overflow region. */
6613 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
6616 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
6618 f_ovfl
= build_decl (BUILTINS_LOCATION
,
6619 FIELD_DECL
, get_identifier ("__overflow_argptr"),
6621 f_gtop
= build_decl (BUILTINS_LOCATION
,
6622 FIELD_DECL
, get_identifier ("__gpr_top"),
6624 f_ftop
= build_decl (BUILTINS_LOCATION
,
6625 FIELD_DECL
, get_identifier ("__fpr_top"),
6627 f_goff
= build_decl (BUILTINS_LOCATION
,
6628 FIELD_DECL
, get_identifier ("__gpr_offset"),
6629 unsigned_char_type_node
);
6630 f_foff
= build_decl (BUILTINS_LOCATION
,
6631 FIELD_DECL
, get_identifier ("__fpr_offset"),
6632 unsigned_char_type_node
);
6633 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6634 warn on every user file. */
6635 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
6636 array
= build_array_type (unsigned_char_type_node
,
6637 build_index_type (index
));
6638 f_res
= build_decl (BUILTINS_LOCATION
,
6639 FIELD_DECL
, get_identifier ("__reserved"), array
);
6641 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
6642 DECL_FIELD_CONTEXT (f_gtop
) = record
;
6643 DECL_FIELD_CONTEXT (f_ftop
) = record
;
6644 DECL_FIELD_CONTEXT (f_goff
) = record
;
6645 DECL_FIELD_CONTEXT (f_foff
) = record
;
6646 DECL_FIELD_CONTEXT (f_res
) = record
;
6648 TYPE_FIELDS (record
) = f_ovfl
;
6649 DECL_CHAIN (f_ovfl
) = f_gtop
;
6650 DECL_CHAIN (f_gtop
) = f_ftop
;
6651 DECL_CHAIN (f_ftop
) = f_goff
;
6652 DECL_CHAIN (f_goff
) = f_foff
;
6653 DECL_CHAIN (f_foff
) = f_res
;
6655 layout_type (record
);
6659 /* Otherwise, we use 'void *'. */
6660 return ptr_type_node
;
6663 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6666 mips_va_start (tree valist
, rtx nextarg
)
6668 if (EABI_FLOAT_VARARGS_P
)
6670 const CUMULATIVE_ARGS
*cum
;
6671 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6672 tree ovfl
, gtop
, ftop
, goff
, foff
;
6674 int gpr_save_area_size
;
6675 int fpr_save_area_size
;
6678 cum
= &crtl
->args
.info
;
6680 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
6682 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
6684 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6685 f_gtop
= DECL_CHAIN (f_ovfl
);
6686 f_ftop
= DECL_CHAIN (f_gtop
);
6687 f_goff
= DECL_CHAIN (f_ftop
);
6688 f_foff
= DECL_CHAIN (f_goff
);
6690 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6692 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
6694 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
6696 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
6698 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
6701 /* Emit code to initialize OVFL, which points to the next varargs
6702 stack argument. CUM->STACK_WORDS gives the number of stack
6703 words used by named arguments. */
6704 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
6705 if (cum
->stack_words
> 0)
6706 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
6707 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
6708 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6710 /* Emit code to initialize GTOP, the top of the GPR save area. */
6711 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6712 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6713 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6715 /* Emit code to initialize FTOP, the top of the FPR save area.
6716 This address is gpr_save_area_bytes below GTOP, rounded
6717 down to the next fp-aligned boundary. */
6718 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6719 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6720 fpr_offset
&= -UNITS_PER_FPVALUE
;
6722 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6723 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6724 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6726 /* Emit code to initialize GOFF, the offset from GTOP of the
6727 next GPR argument. */
6728 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6729 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6730 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6732 /* Likewise emit code to initialize FOFF, the offset from FTOP
6733 of the next FPR argument. */
6734 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6735 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6736 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6740 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6741 std_expand_builtin_va_start (valist
, nextarg
);
6745 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6749 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6752 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6753 unsigned HOST_WIDE_INT align
, boundary
;
6756 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6758 type
= build_pointer_type (type
);
6760 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6761 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6763 /* When we align parameter on stack for caller, if the parameter
6764 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6765 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6766 here with caller. */
6767 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6768 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6770 boundary
/= BITS_PER_UNIT
;
6772 /* Hoist the valist value into a temporary for the moment. */
6773 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6775 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6776 requires greater alignment, we must perform dynamic alignment. */
6777 if (boundary
> align
)
6779 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6780 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6781 gimplify_and_add (t
, pre_p
);
6783 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6784 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6786 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6787 gimplify_and_add (t
, pre_p
);
6792 /* If the actual alignment is less than the alignment of the type,
6793 adjust the type accordingly so that we don't assume strict alignment
6794 when dereferencing the pointer. */
6795 boundary
*= BITS_PER_UNIT
;
6796 if (boundary
< TYPE_ALIGN (type
))
6798 type
= build_variant_type_copy (type
);
6799 SET_TYPE_ALIGN (type
, boundary
);
6802 /* Compute the rounded size of the type. */
6803 type_size
= size_in_bytes (type
);
6804 rounded_size
= round_up (type_size
, align
);
6806 /* Reduce rounded_size so it's sharable with the postqueue. */
6807 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6811 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6813 /* Small args are padded downward. */
6814 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6815 rounded_size
, size_int (align
));
6816 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6817 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6818 addr
= fold_build_pointer_plus (addr
, t
);
6821 /* Compute new value for AP. */
6822 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6823 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6824 gimplify_and_add (t
, pre_p
);
6826 addr
= fold_convert (build_pointer_type (type
), addr
);
6829 addr
= build_va_arg_indirect_ref (addr
);
6831 return build_va_arg_indirect_ref (addr
);
6834 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6837 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6843 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6845 type
= build_pointer_type (type
);
6847 if (!EABI_FLOAT_VARARGS_P
)
6848 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6851 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6852 tree ovfl
, top
, off
, align
;
6853 HOST_WIDE_INT size
, rsize
, osize
;
6856 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6857 f_gtop
= DECL_CHAIN (f_ovfl
);
6858 f_ftop
= DECL_CHAIN (f_gtop
);
6859 f_goff
= DECL_CHAIN (f_ftop
);
6860 f_foff
= DECL_CHAIN (f_goff
);
6864 TOP be the top of the GPR or FPR save area;
6865 OFF be the offset from TOP of the next register;
6866 ADDR_RTX be the address of the argument;
6867 SIZE be the number of bytes in the argument type;
6868 RSIZE be the number of bytes used to store the argument
6869 when it's in the register save area; and
6870 OSIZE be the number of bytes used to store it when it's
6871 in the stack overflow area.
6873 The code we want is:
6875 1: off &= -rsize; // round down
6878 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6883 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6884 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6888 [1] and [9] can sometimes be optimized away. */
6890 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6892 size
= int_size_in_bytes (type
);
6894 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6895 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6897 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6898 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6899 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6900 unshare_expr (valist
), f_foff
, NULL_TREE
);
6902 /* When va_start saves FPR arguments to the stack, each slot
6903 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6904 argument's precision. */
6905 rsize
= UNITS_PER_HWFPVALUE
;
6907 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6908 (= PARM_BOUNDARY bits). This can be different from RSIZE
6911 (1) On 32-bit targets when TYPE is a structure such as:
6913 struct s { float f; };
6915 Such structures are passed in paired FPRs, so RSIZE
6916 will be 8 bytes. However, the structure only takes
6917 up 4 bytes of memory, so OSIZE will only be 4.
6919 (2) In combinations such as -mgp64 -msingle-float
6920 -fshort-double. Doubles passed in registers will then take
6921 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6922 stack take up UNITS_PER_WORD bytes. */
6923 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6927 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6928 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6929 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6930 unshare_expr (valist
), f_goff
, NULL_TREE
);
6931 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
6932 if (rsize
> UNITS_PER_WORD
)
6934 /* [1] Emit code for: off &= -rsize. */
6935 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6936 build_int_cst (TREE_TYPE (off
), -rsize
));
6937 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6942 /* [2] Emit code to branch if off == 0. */
6943 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6944 build_int_cst (TREE_TYPE (off
), 0));
6945 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6947 /* [5] Emit code for: off -= rsize. We do this as a form of
6948 post-decrement not available to C. */
6949 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6950 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6952 /* [4] Emit code for:
6953 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6954 t
= fold_convert (sizetype
, t
);
6955 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6956 t
= fold_build_pointer_plus (top
, t
);
6957 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6958 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6959 COND_EXPR_THEN (addr
) = t
;
6961 if (osize
> UNITS_PER_WORD
)
6963 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6964 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6965 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6966 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6967 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6968 unshare_expr (ovfl
), t
);
6973 /* [10, 11] Emit code for:
6974 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6976 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6977 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6978 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6979 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6981 /* String [9] and [10, 11] together. */
6983 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6984 COND_EXPR_ELSE (addr
) = t
;
6986 addr
= fold_convert (build_pointer_type (type
), addr
);
6987 addr
= build_va_arg_indirect_ref (addr
);
6991 addr
= build_va_arg_indirect_ref (addr
);
6996 /* Declare a unique, locally-binding function called NAME, then start
7000 mips_start_unique_function (const char *name
)
7004 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
7005 get_identifier (name
),
7006 build_function_type_list (void_type_node
, NULL_TREE
));
7007 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
7008 NULL_TREE
, void_type_node
);
7009 TREE_PUBLIC (decl
) = 1;
7010 TREE_STATIC (decl
) = 1;
7012 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
7014 targetm
.asm_out
.unique_section (decl
, 0);
7015 switch_to_section (get_named_section (decl
, NULL
, 0));
7017 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
7018 fputs ("\t.hidden\t", asm_out_file
);
7019 assemble_name (asm_out_file
, name
);
7020 putc ('\n', asm_out_file
);
7023 /* Start a definition of function NAME. MIPS16_P indicates whether the
7024 function contains MIPS16 code. */
7027 mips_start_function_definition (const char *name
, bool mips16_p
)
7030 fprintf (asm_out_file
, "\t.set\tmips16\n");
7032 fprintf (asm_out_file
, "\t.set\tnomips16\n");
7034 if (TARGET_MICROMIPS
)
7035 fprintf (asm_out_file
, "\t.set\tmicromips\n");
7036 #ifdef HAVE_GAS_MICROMIPS
7038 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
7041 if (!flag_inhibit_size_directive
)
7043 fputs ("\t.ent\t", asm_out_file
);
7044 assemble_name (asm_out_file
, name
);
7045 fputs ("\n", asm_out_file
);
7048 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
7050 /* Start the definition proper. */
7051 assemble_name (asm_out_file
, name
);
7052 fputs (":\n", asm_out_file
);
7055 /* End a function definition started by mips_start_function_definition. */
7058 mips_end_function_definition (const char *name
)
7060 if (!flag_inhibit_size_directive
)
7062 fputs ("\t.end\t", asm_out_file
);
7063 assemble_name (asm_out_file
, name
);
7064 fputs ("\n", asm_out_file
);
7068 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
7069 then free *STUB_PTR. */
7072 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
7074 mips_one_only_stub
*stub
= *stub_ptr
;
7078 const char *name
= stub
->get_name ();
7079 mips_start_unique_function (name
);
7080 mips_start_function_definition (name
, false);
7081 stub
->output_body ();
7082 mips_end_function_definition (name
);
7087 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
7090 mips_ok_for_lazy_binding_p (rtx x
)
7092 return (TARGET_USE_GOT
7093 && GET_CODE (x
) == SYMBOL_REF
7094 && !SYMBOL_REF_BIND_NOW_P (x
)
7095 && !mips_symbol_binds_local_p (x
));
7098 /* Load function address ADDR into register DEST. TYPE is as for
7099 mips_expand_call. Return true if we used an explicit lazy-binding
7103 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
7105 /* If we're generating PIC, and this call is to a global function,
7106 try to allow its address to be resolved lazily. This isn't
7107 possible for sibcalls when $gp is call-saved because the value
7108 of $gp on entry to the stub would be our caller's gp, not ours. */
7109 if (TARGET_EXPLICIT_RELOCS
7110 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
7111 && mips_ok_for_lazy_binding_p (addr
))
7113 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
7114 emit_insn (gen_rtx_SET (dest
, addr
));
7119 mips_emit_move (dest
, addr
);
7124 /* Each locally-defined hard-float MIPS16 function has a local symbol
7125 associated with it. This hash table maps the function symbol (FUNC)
7126 to the local symbol (LOCAL). */
7127 static GTY (()) hash_map
<nofree_string_hash
, rtx
> *mips16_local_aliases
;
7129 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
7130 Return a local alias for it, creating a new one if necessary. */
7133 mips16_local_alias (rtx func
)
7135 /* Create the hash table if this is the first call. */
7136 if (mips16_local_aliases
== NULL
)
7137 mips16_local_aliases
= hash_map
<nofree_string_hash
, rtx
>::create_ggc (37);
7139 /* Look up the function symbol, creating a new entry if need be. */
7141 const char *func_name
= XSTR (func
, 0);
7142 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func_name
, &existed
);
7143 gcc_assert (slot
!= NULL
);
7149 /* Create a new SYMBOL_REF for the local symbol. The choice of
7150 __fn_local_* is based on the __fn_stub_* names that we've
7151 traditionally used for the non-MIPS16 stub. */
7152 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
7153 const char *local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
7154 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
7155 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
7157 /* Create a new structure to represent the mapping. */
7163 /* A chained list of functions for which mips16_build_call_stub has already
7164 generated a stub. NAME is the name of the function and FP_RET_P is true
7165 if the function returns a value in floating-point registers. */
7166 struct mips16_stub
{
7167 struct mips16_stub
*next
;
7171 static struct mips16_stub
*mips16_stubs
;
7173 /* Return the two-character string that identifies floating-point
7174 return mode MODE in the name of a MIPS16 function stub. */
7177 mips16_call_stub_mode_suffix (machine_mode mode
)
7181 else if (mode
== DFmode
)
7183 else if (mode
== SCmode
)
7185 else if (mode
== DCmode
)
7187 else if (mode
== V2SFmode
)
7189 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
);
7196 /* Write instructions to move a 32-bit value between general register
7197 GPREG and floating-point register FPREG. DIRECTION is 't' to move
7198 from GPREG to FPREG and 'f' to move in the opposite direction. */
7201 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
7203 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7204 reg_names
[gpreg
], reg_names
[fpreg
]);
7207 /* Likewise for 64-bit values. */
7210 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
7213 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
7214 reg_names
[gpreg
], reg_names
[fpreg
]);
7215 else if (ISA_HAS_MXHC1
)
7217 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7218 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
7219 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
7220 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
7222 else if (TARGET_FLOATXX
&& direction
== 't')
7224 /* Use the argument save area to move via memory. */
7225 fprintf (asm_out_file
, "\tsw\t%s,0($sp)\n", reg_names
[gpreg
]);
7226 fprintf (asm_out_file
, "\tsw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
7227 fprintf (asm_out_file
, "\tldc1\t%s,0($sp)\n", reg_names
[fpreg
]);
7229 else if (TARGET_FLOATXX
&& direction
== 'f')
7231 /* Use the argument save area to move via memory. */
7232 fprintf (asm_out_file
, "\tsdc1\t%s,0($sp)\n", reg_names
[fpreg
]);
7233 fprintf (asm_out_file
, "\tlw\t%s,0($sp)\n", reg_names
[gpreg
]);
7234 fprintf (asm_out_file
, "\tlw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
7238 /* Move the least-significant word. */
7239 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7240 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
7241 /* ...then the most significant word. */
7242 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7243 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
7247 /* Write out code to move floating-point arguments into or out of
7248 general registers. FP_CODE is the code describing which arguments
7249 are present (see the comment above the definition of CUMULATIVE_ARGS
7250 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
7253 mips_output_args_xfer (int fp_code
, char direction
)
7255 unsigned int gparg
, fparg
, f
;
7256 CUMULATIVE_ARGS cum
;
7258 /* This code only works for o32 and o64. */
7259 gcc_assert (TARGET_OLDABI
);
7261 mips_init_cumulative_args (&cum
, NULL
);
7263 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7266 struct mips_arg_info info
;
7270 else if ((f
& 3) == 2)
7275 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
7276 gparg
= mips_arg_regno (&info
, false);
7277 fparg
= mips_arg_regno (&info
, true);
7280 mips_output_32bit_xfer (direction
, gparg
, fparg
);
7282 mips_output_64bit_xfer (direction
, gparg
, fparg
);
7284 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
7288 /* Write a MIPS16 stub for the current function. This stub is used
7289 for functions which take arguments in the floating-point registers.
7290 It is normal-mode code that moves the floating-point arguments
7291 into the general registers and then jumps to the MIPS16 code. */
7294 mips16_build_function_stub (void)
7296 const char *fnname
, *alias_name
, *separator
;
7297 char *secname
, *stubname
;
7302 /* Create the name of the stub, and its unique section. */
7303 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
7304 alias
= mips16_local_alias (symbol
);
7306 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
7307 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
7308 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
7309 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
7311 /* Build a decl for the stub. */
7312 stubdecl
= build_decl (BUILTINS_LOCATION
,
7313 FUNCTION_DECL
, get_identifier (stubname
),
7314 build_function_type_list (void_type_node
, NULL_TREE
));
7315 set_decl_section_name (stubdecl
, secname
);
7316 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7317 RESULT_DECL
, NULL_TREE
, void_type_node
);
7319 /* Output a comment. */
7320 fprintf (asm_out_file
, "\t# Stub function for %s (",
7321 current_function_name ());
7323 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
7325 fprintf (asm_out_file
, "%s%s", separator
,
7326 (f
& 3) == 1 ? "float" : "double");
7329 fprintf (asm_out_file
, ")\n");
7331 /* Start the function definition. */
7332 assemble_start_function (stubdecl
, stubname
);
7333 mips_start_function_definition (stubname
, false);
7335 /* If generating pic2 code, either set up the global pointer or
7337 if (TARGET_ABICALLS_PIC2
)
7339 if (TARGET_ABSOLUTE_ABICALLS
)
7340 fprintf (asm_out_file
, "\t.option\tpic0\n");
7343 output_asm_insn ("%(.cpload\t%^%)", NULL
);
7344 /* Emit an R_MIPS_NONE relocation to tell the linker what the
7345 target function is. Use a local GOT access when loading the
7346 symbol, to cut down on the number of unnecessary GOT entries
7347 for stubs that aren't needed. */
7348 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
7353 /* Load the address of the MIPS16 function into $25. Do this first so
7354 that targets with coprocessor interlocks can use an MFC1 to fill the
7356 output_asm_insn ("la\t%^,%0", &symbol
);
7358 /* Move the arguments from floating-point registers to general registers. */
7359 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
7361 /* Jump to the MIPS16 function. */
7362 output_asm_insn ("jr\t%^", NULL
);
7364 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
7365 fprintf (asm_out_file
, "\t.option\tpic2\n");
7367 mips_end_function_definition (stubname
);
7369 /* If the linker needs to create a dynamic symbol for the target
7370 function, it will associate the symbol with the stub (which,
7371 unlike the target function, follows the proper calling conventions).
7372 It is therefore useful to have a local alias for the target function,
7373 so that it can still be identified as MIPS16 code. As an optimization,
7374 this symbol can also be used for indirect MIPS16 references from
7375 within this file. */
7376 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
7378 switch_to_section (function_section (current_function_decl
));
7381 /* The current function is a MIPS16 function that returns a value in an FPR.
7382 Copy the return value from its soft-float to its hard-float location.
7383 libgcc2 has special non-MIPS16 helper functions for each case. */
7386 mips16_copy_fpr_return_value (void)
7388 rtx fn
, insn
, retval
;
7390 machine_mode return_mode
;
7393 return_type
= DECL_RESULT (current_function_decl
);
7394 return_mode
= DECL_MODE (return_type
);
7396 name
= ACONCAT (("__mips16_ret_",
7397 mips16_call_stub_mode_suffix (return_mode
),
7399 fn
= mips16_stub_function (name
);
7401 /* The function takes arguments in $2 (and possibly $3), so calls
7402 to it cannot be lazily bound. */
7403 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
7405 /* Model the call as something that takes the GPR return value as
7406 argument and returns an "updated" value. */
7407 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
7408 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
7409 const0_rtx
, NULL_RTX
, false);
7410 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
7413 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
7414 RETVAL is the location of the return value, or null if this is
7415 a "call" rather than a "call_value". ARGS_SIZE is the size of the
7416 arguments and FP_CODE is the code built by mips_function_arg;
7417 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
7419 There are three alternatives:
7421 - If a stub was needed, emit the call and return the call insn itself.
7423 - If we can avoid using a stub by redirecting the call, set *FN_PTR
7424 to the new target and return null.
7426 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
7429 A stub is needed for calls to functions that, in normal mode,
7430 receive arguments in FPRs or return values in FPRs. The stub
7431 copies the arguments from their soft-float positions to their
7432 hard-float positions, calls the real function, then copies the
7433 return value from its hard-float position to its soft-float
7436 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
7437 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
7438 automatically redirects the JAL to the stub, otherwise the JAL
7439 continues to call FN directly. */
7442 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
7446 struct mips16_stub
*l
;
7450 /* We don't need to do anything if we aren't in MIPS16 mode, or if
7451 we were invoked with the -msoft-float option. */
7452 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
7455 /* Figure out whether the value might come back in a floating-point
7457 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
7459 /* We don't need to do anything if there were no floating-point
7460 arguments and the value will not be returned in a floating-point
7462 if (fp_code
== 0 && !fp_ret_p
)
7465 /* We don't need to do anything if this is a call to a special
7466 MIPS16 support function. */
7468 if (mips16_stub_function_p (fn
))
7471 /* If we're calling a locally-defined MIPS16 function, we know that
7472 it will return values in both the "soft-float" and "hard-float"
7473 registers. There is no need to use a stub to move the latter
7475 if (fp_code
== 0 && mips16_local_function_p (fn
))
7478 /* This code will only work for o32 and o64 abis. The other ABI's
7479 require more sophisticated support. */
7480 gcc_assert (TARGET_OLDABI
);
7482 /* If we're calling via a function pointer, use one of the magic
7483 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
7484 Each stub expects the function address to arrive in register $2. */
7485 if (GET_CODE (fn
) != SYMBOL_REF
7486 || !call_insn_operand (fn
, VOIDmode
))
7493 /* If this is a locally-defined and locally-binding function,
7494 avoid the stub by calling the local alias directly. */
7495 if (mips16_local_function_p (fn
))
7497 *fn_ptr
= mips16_local_alias (fn
);
7501 /* Create a SYMBOL_REF for the libgcc.a function. */
7503 sprintf (buf
, "__mips16_call_stub_%s_%d",
7504 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
7507 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
7508 stub_fn
= mips16_stub_function (buf
);
7510 /* The function uses $2 as an argument, so calls to it
7511 cannot be lazily bound. */
7512 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
7514 /* Load the target function into $2. */
7515 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
7516 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
7518 /* Emit the call. */
7519 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
7520 args_size
, NULL_RTX
, lazy_p
);
7522 /* Tell GCC that this call does indeed use the value of $2. */
7523 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
7525 /* If we are handling a floating-point return value, we need to
7526 save $18 in the function prologue. Putting a note on the
7527 call will mean that df_regs_ever_live_p ($18) will be true if the
7528 call is not eliminated, and we can check that in the prologue
7531 CALL_INSN_FUNCTION_USAGE (insn
) =
7532 gen_rtx_EXPR_LIST (VOIDmode
,
7533 gen_rtx_CLOBBER (VOIDmode
,
7534 gen_rtx_REG (word_mode
, 18)),
7535 CALL_INSN_FUNCTION_USAGE (insn
));
7540 /* We know the function we are going to call. If we have already
7541 built a stub, we don't need to do anything further. */
7542 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
7543 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
7544 if (strcmp (l
->name
, fnname
) == 0)
7549 const char *separator
;
7550 char *secname
, *stubname
;
7551 tree stubid
, stubdecl
;
7554 /* If the function does not return in FPRs, the special stub
7558 If the function does return in FPRs, the stub section is named
7559 .mips16.call.fp.FNNAME
7561 Build a decl for the stub. */
7562 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
7564 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
7566 stubid
= get_identifier (stubname
);
7567 stubdecl
= build_decl (BUILTINS_LOCATION
,
7568 FUNCTION_DECL
, stubid
,
7569 build_function_type_list (void_type_node
,
7571 set_decl_section_name (stubdecl
, secname
);
7572 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7573 RESULT_DECL
, NULL_TREE
,
7576 /* Output a comment. */
7577 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7579 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7583 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7585 fprintf (asm_out_file
, "%s%s", separator
,
7586 (f
& 3) == 1 ? "float" : "double");
7589 fprintf (asm_out_file
, ")\n");
7591 /* Start the function definition. */
7592 assemble_start_function (stubdecl
, stubname
);
7593 mips_start_function_definition (stubname
, false);
7597 fprintf (asm_out_file
, "\t.cfi_startproc\n");
7599 /* Create a fake CFA 4 bytes below the stack pointer.
7600 This works around unwinders (like libgcc's) that expect
7601 the CFA for non-signal frames to be unique. */
7602 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
7604 /* "Save" $sp in itself so we don't use the fake CFA.
7605 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7606 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
7608 /* Save the return address in $18. The stub's caller knows
7609 that $18 might be clobbered, even though $18 is usually
7610 a call-saved register.
7612 Do it early on in case the last move to a floating-point
7613 register can be scheduled into the delay slot of the
7614 call we are about to make. */
7615 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7616 reg_names
[GP_REG_FIRST
+ 18],
7617 reg_names
[RETURN_ADDR_REGNUM
]);
7621 /* Load the address of the MIPS16 function into $25. Do this
7622 first so that targets with coprocessor interlocks can use
7623 an MFC1 to fill the delay slot. */
7624 if (TARGET_EXPLICIT_RELOCS
)
7626 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
7627 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
7630 output_asm_insn ("la\t%^,%0", &fn
);
7633 /* Move the arguments from general registers to floating-point
7635 mips_output_args_xfer (fp_code
, 't');
7639 /* Now call the non-MIPS16 function. */
7640 output_asm_insn (mips_output_jump (&fn
, 0, -1, true), &fn
);
7641 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
7643 /* Move the result from floating-point registers to
7644 general registers. */
7645 switch (GET_MODE (retval
))
7648 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
7652 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
7653 TARGET_LITTLE_ENDIAN
7656 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
7658 /* On 64-bit targets, complex floats are returned in
7659 a single GPR, such that "sd" on a suitably-aligned
7660 target would store the value correctly. */
7661 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7662 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7663 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7664 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7665 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
7666 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
7667 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
7668 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7669 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7670 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
7671 reg_names
[GP_RETURN
],
7672 reg_names
[GP_RETURN
],
7673 reg_names
[GP_RETURN
+ 1]);
7678 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7682 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
7687 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7688 || GET_MODE (retval
) != V2SFmode
);
7689 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7695 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7696 fprintf (asm_out_file
, "\t.cfi_endproc\n");
7700 /* Jump to the previously-loaded address. */
7701 output_asm_insn ("jr\t%^", NULL
);
7704 #ifdef ASM_DECLARE_FUNCTION_SIZE
7705 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7708 mips_end_function_definition (stubname
);
7710 /* Record this stub. */
7711 l
= XNEW (struct mips16_stub
);
7712 l
->name
= xstrdup (fnname
);
7713 l
->fp_ret_p
= fp_ret_p
;
7714 l
->next
= mips16_stubs
;
7718 /* If we expect a floating-point return value, but we've built a
7719 stub which does not expect one, then we're in trouble. We can't
7720 use the existing stub, because it won't handle the floating-point
7721 value. We can't build a new stub, because the linker won't know
7722 which stub to use for the various calls in this object file.
7723 Fortunately, this case is illegal, since it means that a function
7724 was declared in two different ways in a single compilation. */
7725 if (fp_ret_p
&& !l
->fp_ret_p
)
7726 error ("cannot handle inconsistent calls to %qs", fnname
);
7728 if (retval
== NULL_RTX
)
7729 pattern
= gen_call_internal_direct (fn
, args_size
);
7731 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7732 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7734 /* If we are calling a stub which handles a floating-point return
7735 value, we need to arrange to save $18 in the prologue. We do this
7736 by marking the function call as using the register. The prologue
7737 will later see that it is used, and emit code to save it. */
7739 CALL_INSN_FUNCTION_USAGE (insn
) =
7740 gen_rtx_EXPR_LIST (VOIDmode
,
7741 gen_rtx_CLOBBER (VOIDmode
,
7742 gen_rtx_REG (word_mode
, 18)),
7743 CALL_INSN_FUNCTION_USAGE (insn
));
7748 /* Expand a call of type TYPE. RESULT is where the result will go (null
7749 for "call"s and "sibcall"s), ADDR is the address of the function,
7750 ARGS_SIZE is the size of the arguments and AUX is the value passed
7751 to us by mips_function_arg. LAZY_P is true if this call already
7752 involves a lazily-bound function address (such as when calling
7753 functions through a MIPS16 hard-float stub).
7755 Return the call itself. */
7758 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7759 rtx args_size
, rtx aux
, bool lazy_p
)
7761 rtx orig_addr
, pattern
;
7765 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7766 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7769 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7774 if (!call_insn_operand (addr
, VOIDmode
))
7776 if (type
== MIPS_CALL_EPILOGUE
)
7777 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7779 addr
= gen_reg_rtx (Pmode
);
7780 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7785 rtx (*fn
) (rtx
, rtx
);
7787 if (type
== MIPS_CALL_SIBCALL
)
7788 fn
= gen_sibcall_internal
;
7790 fn
= gen_call_internal
;
7792 pattern
= fn (addr
, args_size
);
7794 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7796 /* Handle return values created by mips_return_fpr_pair. */
7797 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7800 if (type
== MIPS_CALL_SIBCALL
)
7801 fn
= gen_sibcall_value_multiple_internal
;
7803 fn
= gen_call_value_multiple_internal
;
7805 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7806 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7807 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7811 rtx (*fn
) (rtx
, rtx
, rtx
);
7813 if (type
== MIPS_CALL_SIBCALL
)
7814 fn
= gen_sibcall_value_internal
;
7816 fn
= gen_call_value_internal
;
7818 /* Handle return values created by mips_return_fpr_single. */
7819 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7820 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7821 pattern
= fn (result
, addr
, args_size
);
7824 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7827 /* Split call instruction INSN into a $gp-clobbering call and
7828 (where necessary) an instruction to restore $gp from its save slot.
7829 CALL_PATTERN is the pattern of the new call. */
7832 mips_split_call (rtx insn
, rtx call_pattern
)
7834 emit_call_insn (call_pattern
);
7835 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7836 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7837 POST_CALL_TMP_REG
));
7840 /* Return true if a call to DECL may need to use JALX. */
7843 mips_call_may_need_jalx_p (tree decl
)
7845 /* If the current translation unit would use a different mode for DECL,
7846 assume that the call needs JALX. */
7847 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7850 /* mips_get_compress_mode is always accurate for locally-binding
7851 functions in the current translation unit. */
7852 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7855 /* When -minterlink-compressed is in effect, assume that functions
7856 could use a different encoding mode unless an attribute explicitly
7857 tells us otherwise. */
7858 if (TARGET_INTERLINK_COMPRESSED
)
7860 if (!TARGET_COMPRESSION
7861 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7863 if (TARGET_COMPRESSION
7864 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7871 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7874 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7876 if (!TARGET_SIBCALLS
)
7879 /* Interrupt handlers need special epilogue code and therefore can't
7881 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7884 /* Direct Js are only possible to functions that use the same ISA encoding.
7885 There is no JX counterpoart of JALX. */
7887 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7888 && mips_call_may_need_jalx_p (decl
))
7891 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7892 require $gp to be valid on entry, so sibcalls can only use stubs
7893 if $gp is call-clobbered. */
7895 && TARGET_CALL_SAVED_GP
7896 && !TARGET_ABICALLS_PIC0
7897 && !targetm
.binds_local_p (decl
))
7904 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7907 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
7909 enum by_pieces_operation op
,
7912 if (op
== STORE_BY_PIECES
)
7913 return mips_store_by_pieces_p (size
, align
);
7914 if (op
== MOVE_BY_PIECES
&& HAVE_movmemsi
)
7916 /* movmemsi is meant to generate code that is at least as good as
7917 move_by_pieces. However, movmemsi effectively uses a by-pieces
7918 implementation both for moves smaller than a word and for
7919 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7920 bytes. We should allow the tree-level optimisers to do such
7921 moves by pieces, as it often exposes other optimization
7922 opportunities. We might as well continue to use movmemsi at
7923 the rtl level though, as it produces better code when
7924 scheduling is disabled (such as at -O). */
7925 if (currently_expanding_to_rtl
)
7927 if (align
< BITS_PER_WORD
)
7928 return size
< UNITS_PER_WORD
;
7929 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7932 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
7935 /* Implement a handler for STORE_BY_PIECES operations
7936 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7939 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7941 /* Storing by pieces involves moving constants into registers
7942 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7943 We need to decide whether it is cheaper to load the address of
7944 constant data into a register and use a block move instead. */
7946 /* If the data is only byte aligned, then:
7948 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7949 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7952 (a2) A block move of 4 bytes from aligned source data can use an
7953 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7954 4 SBs that we would generate when storing by pieces. */
7955 if (align
<= BITS_PER_UNIT
)
7958 /* If the data is 2-byte aligned, then:
7960 (b1) A block move of less than 4 bytes would use a combination of LBs,
7961 LHs, SBs and SHs. We get better code by using single-instruction
7962 LIs, SBs and SHs instead.
7964 (b2) A block move of 4 bytes from aligned source data would again use
7965 an LW/SWL/SWR sequence. In most cases, loading the address of
7966 the source data would require at least one extra instruction.
7967 It is often more efficient to use 2 single-instruction LIs and
7970 (b3) A block move of up to 3 additional bytes would be like (b1).
7972 (b4) A block move of 8 bytes from aligned source data can use two
7973 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7974 sequences are better than the 4 LIs and 4 SHs that we'd generate
7975 when storing by pieces.
7977 The reasoning for higher alignments is similar:
7979 (c1) A block move of less than 4 bytes would be the same as (b1).
7981 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7982 loading the address of the source data would typically require
7983 at least one extra instruction. It is generally better to use
7986 (c3) A block move of up to 3 additional bytes would be like (b1).
7988 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7989 LD/SD sequence, and in these cases we've traditionally preferred
7990 the memory copy over the more bulky constant moves. */
7994 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7995 Assume that the areas do not overlap. */
7998 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
8000 HOST_WIDE_INT offset
, delta
;
8001 unsigned HOST_WIDE_INT bits
;
8006 /* Work out how many bits to move at a time. If both operands have
8007 half-word alignment, it is usually better to move in half words.
8008 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
8009 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
8010 Otherwise move word-sized chunks.
8012 For ISA_HAS_LWL_LWR we rely on the lwl/lwr & swl/swr load. Otherwise
8013 picking the minimum of alignment or BITS_PER_WORD gets us the
8014 desired size for bits. */
8016 if (!ISA_HAS_LWL_LWR
)
8017 bits
= MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)));
8020 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
8021 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
8022 bits
= BITS_PER_WORD
/ 2;
8024 bits
= BITS_PER_WORD
;
8027 mode
= int_mode_for_size (bits
, 0).require ();
8028 delta
= bits
/ BITS_PER_UNIT
;
8030 /* Allocate a buffer for the temporary registers. */
8031 regs
= XALLOCAVEC (rtx
, length
/ delta
);
8033 /* Load as many BITS-sized chunks as possible. Use a normal load if
8034 the source has enough alignment, otherwise use left/right pairs. */
8035 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
8037 regs
[i
] = gen_reg_rtx (mode
);
8038 if (MEM_ALIGN (src
) >= bits
)
8039 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
8042 rtx part
= adjust_address (src
, BLKmode
, offset
);
8043 set_mem_size (part
, delta
);
8044 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
8049 /* Copy the chunks to the destination. */
8050 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
8051 if (MEM_ALIGN (dest
) >= bits
)
8052 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
8055 rtx part
= adjust_address (dest
, BLKmode
, offset
);
8056 set_mem_size (part
, delta
);
8057 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
8061 /* Mop up any left-over bytes. */
8062 if (offset
< length
)
8064 src
= adjust_address (src
, BLKmode
, offset
);
8065 dest
= adjust_address (dest
, BLKmode
, offset
);
8066 move_by_pieces (dest
, src
, length
- offset
,
8067 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), RETURN_BEGIN
);
8071 /* Helper function for doing a loop-based block operation on memory
8072 reference MEM. Each iteration of the loop will operate on LENGTH
8075 Create a new base register for use within the loop and point it to
8076 the start of MEM. Create a new memory reference that uses this
8077 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
8080 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
8081 rtx
*loop_reg
, rtx
*loop_mem
)
8083 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
8085 /* Although the new mem does not refer to a known location,
8086 it does keep up to LENGTH bytes of alignment. */
8087 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
8088 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
8091 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
8092 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
8093 the memory regions do not overlap. */
8096 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
8097 HOST_WIDE_INT bytes_per_iter
)
8099 rtx_code_label
*label
;
8100 rtx src_reg
, dest_reg
, final_src
, test
;
8101 HOST_WIDE_INT leftover
;
8103 leftover
= length
% bytes_per_iter
;
8106 /* Create registers and memory references for use within the loop. */
8107 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
8108 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
8110 /* Calculate the value that SRC_REG should have after the last iteration
8112 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
8115 /* Emit the start of the loop. */
8116 label
= gen_label_rtx ();
8119 /* Emit the loop body. */
8120 mips_block_move_straight (dest
, src
, bytes_per_iter
);
8122 /* Move on to the next block. */
8123 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
8124 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
8126 /* Emit the loop condition. */
8127 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
8128 if (Pmode
== DImode
)
8129 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
8131 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
8133 /* Mop up any left-over bytes. */
8135 mips_block_move_straight (dest
, src
, leftover
);
8137 /* Temporary fix for PR79150. */
8138 emit_insn (gen_nop ());
8141 /* Expand a movmemsi instruction, which copies LENGTH bytes from
8142 memory reference SRC to memory reference DEST. */
8145 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
8147 if (!ISA_HAS_LWL_LWR
8148 && (MEM_ALIGN (src
) < MIPS_MIN_MOVE_MEM_ALIGN
8149 || MEM_ALIGN (dest
) < MIPS_MIN_MOVE_MEM_ALIGN
))
8152 if (CONST_INT_P (length
))
8154 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
8156 mips_block_move_straight (dest
, src
, INTVAL (length
));
8161 mips_block_move_loop (dest
, src
, INTVAL (length
),
8162 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
8169 /* Expand a loop of synci insns for the address range [BEGIN, END). */
8172 mips_expand_synci_loop (rtx begin
, rtx end
)
8174 rtx inc
, cmp_result
, mask
, length
;
8175 rtx_code_label
*label
, *end_label
;
8177 /* Create end_label. */
8178 end_label
= gen_label_rtx ();
8180 /* Check if begin equals end. */
8181 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
8182 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
8184 /* Load INC with the cache line size (rdhwr INC,$1). */
8185 inc
= gen_reg_rtx (Pmode
);
8186 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
8188 /* Check if inc is 0. */
8189 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
8190 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
8192 /* Calculate mask. */
8193 mask
= mips_force_unary (Pmode
, NEG
, inc
);
8195 /* Mask out begin by mask. */
8196 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
8198 /* Calculate length. */
8199 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
8201 /* Loop back to here. */
8202 label
= gen_label_rtx ();
8205 emit_insn (gen_synci (begin
));
8207 /* Update length. */
8208 mips_emit_binary (MINUS
, length
, length
, inc
);
8211 mips_emit_binary (PLUS
, begin
, begin
, inc
);
8213 /* Check if length is greater than 0. */
8214 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
8215 emit_jump_insn (gen_condjump (cmp_result
, label
));
8217 emit_label (end_label
);
8220 /* Expand a QI or HI mode atomic memory operation.
8222 GENERATOR contains a pointer to the gen_* function that generates
8223 the SI mode underlying atomic operation using masks that we
8226 RESULT is the return register for the operation. Its value is NULL
8229 MEM is the location of the atomic access.
8231 OLDVAL is the first operand for the operation.
8233 NEWVAL is the optional second operand for the operation. Its value
8234 is NULL if unused. */
8237 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
8238 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
8240 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
8241 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
8245 mode
= GET_MODE (mem
);
8247 /* Compute the address of the containing SImode value. */
8248 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
8249 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
8250 force_reg (Pmode
, GEN_INT (-4)));
8252 /* Create a memory reference for it. */
8253 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
8254 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
8255 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
8257 /* Work out the byte offset of the QImode or HImode value,
8258 counting from the least significant byte. */
8259 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
8260 if (TARGET_BIG_ENDIAN
)
8261 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
8263 /* Multiply by eight to convert the shift value from bytes to bits. */
8264 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
8266 /* Make the final shift an SImode value, so that it can be used in
8267 SImode operations. */
8268 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
8270 /* Set MASK to an inclusive mask of the QImode or HImode value. */
8271 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
8272 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
8273 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
8275 /* Compute the equivalent exclusive mask. */
8276 inverted_mask
= gen_reg_rtx (SImode
);
8277 emit_insn (gen_rtx_SET (inverted_mask
, gen_rtx_NOT (SImode
, mask
)));
8279 /* Shift the old value into place. */
8280 if (oldval
!= const0_rtx
)
8282 oldval
= convert_modes (SImode
, mode
, oldval
, true);
8283 oldval
= force_reg (SImode
, oldval
);
8284 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
8287 /* Do the same for the new value. */
8288 if (newval
&& newval
!= const0_rtx
)
8290 newval
= convert_modes (SImode
, mode
, newval
, true);
8291 newval
= force_reg (SImode
, newval
);
8292 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
8295 /* Do the SImode atomic access. */
8297 res
= gen_reg_rtx (SImode
);
8299 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
8301 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
8303 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
8309 /* Shift and convert the result. */
8310 mips_emit_binary (AND
, res
, res
, mask
);
8311 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
8312 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
8316 /* Return true if it is possible to use left/right accesses for a
8317 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
8318 When returning true, update *LEFT and *RIGHT as follows:
8320 *LEFT is a QImode reference to the first byte if big endian or
8321 the last byte if little endian. This address can be used in the
8322 left-side instructions (LWL, SWL, LDL, SDL).
8324 *RIGHT is a QImode reference to the opposite end of the field and
8325 can be used in the patterning right-side instruction. */
8328 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
8329 rtx
*left
, rtx
*right
)
8333 /* Check that the size is valid. */
8334 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
8337 /* We can only access byte-aligned values. Since we are always passed
8338 a reference to the first byte of the field, it is not necessary to
8339 do anything with BITPOS after this check. */
8340 if (bitpos
% BITS_PER_UNIT
!= 0)
8343 /* Reject aligned bitfields: we want to use a normal load or store
8344 instead of a left/right pair. */
8345 if (MEM_ALIGN (op
) >= width
)
8348 /* Get references to both ends of the field. */
8349 first
= adjust_address (op
, QImode
, 0);
8350 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
8352 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
8353 correspond to the MSB and RIGHT to the LSB. */
8354 if (TARGET_BIG_ENDIAN
)
8355 *left
= first
, *right
= last
;
8357 *left
= last
, *right
= first
;
8362 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
8363 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
8364 the operation is the equivalent of:
8366 (set DEST (*_extract SRC WIDTH BITPOS))
8368 Return true on success. */
8371 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
8372 HOST_WIDE_INT bitpos
, bool unsigned_p
)
8374 rtx left
, right
, temp
;
8375 rtx dest1
= NULL_RTX
;
8377 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
8378 be a DImode, create a new temp and emit a zero extend at the end. */
8379 if (GET_MODE (dest
) == DImode
8381 && GET_MODE_BITSIZE (SImode
) == width
)
8384 dest
= gen_reg_rtx (SImode
);
8387 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
8390 temp
= gen_reg_rtx (GET_MODE (dest
));
8391 if (GET_MODE (dest
) == DImode
)
8393 emit_insn (gen_mov_ldl (temp
, src
, left
));
8394 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
8398 emit_insn (gen_mov_lwl (temp
, src
, left
));
8399 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
8402 /* If we were loading 32bits and the original register was DI then
8403 sign/zero extend into the orignal dest. */
8407 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
8409 emit_insn (gen_extendsidi2 (dest1
, dest
));
8414 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
8415 BITPOS and SRC are the operands passed to the expander; the operation
8416 is the equivalent of:
8418 (set (zero_extract DEST WIDTH BITPOS) SRC)
8420 Return true on success. */
8423 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
8424 HOST_WIDE_INT bitpos
)
8429 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
8432 mode
= int_mode_for_size (width
, 0).require ();
8433 src
= gen_lowpart (mode
, src
);
8436 emit_insn (gen_mov_sdl (dest
, src
, left
));
8437 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
8441 emit_insn (gen_mov_swl (dest
, src
, left
));
8442 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
8447 /* Return true if X is a MEM with the same size as MODE. */
8450 mips_mem_fits_mode_p (machine_mode mode
, rtx x
)
8453 && MEM_SIZE_KNOWN_P (x
)
8454 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
8457 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
8458 source of an "ext" instruction or the destination of an "ins"
8459 instruction. OP must be a register operand and the following
8460 conditions must hold:
8462 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
8463 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8464 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8466 Also reject lengths equal to a word as they are better handled
8467 by the move patterns. */
8470 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
8472 if (!ISA_HAS_EXT_INS
8473 || !register_operand (op
, VOIDmode
)
8474 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
8477 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
8480 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
8486 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
8487 operation if MAXLEN is the maxium length of consecutive bits that
8488 can make up MASK. MODE is the mode of the operation. See
8489 mask_low_and_shift_len for the actual definition. */
8492 mask_low_and_shift_p (machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
8494 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
8497 /* Return true iff OP1 and OP2 are valid operands together for the
8498 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
8499 see the table in the comment before the pattern. */
8502 and_operands_ok (machine_mode mode
, rtx op1
, rtx op2
)
8505 if (memory_operand (op1
, mode
))
8507 if (TARGET_MIPS16
) {
8508 struct mips_address_info addr
;
8509 if (!mips_classify_address (&addr
, op1
, mode
, false))
8512 return and_load_operand (op2
, mode
);
8515 return and_reg_operand (op2
, mode
);
8518 /* The canonical form of a mask-low-and-shift-left operation is
8519 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
8520 cleared. Thus we need to shift MASK to the right before checking if it
8521 is a valid mask value. MODE is the mode of the operation. If true
8522 return the length of the mask, otherwise return -1. */
8525 mask_low_and_shift_len (machine_mode mode
, rtx mask
, rtx shift
)
8527 HOST_WIDE_INT shval
;
8529 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
8530 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
8533 /* Return true if -msplit-addresses is selected and should be honored.
8535 -msplit-addresses is a half-way house between explicit relocations
8536 and the traditional assembler macros. It can split absolute 32-bit
8537 symbolic constants into a high/lo_sum pair but uses macros for other
8540 Like explicit relocation support for REL targets, it relies
8541 on GNU extensions in the assembler and the linker.
8543 Although this code should work for -O0, it has traditionally
8544 been treated as an optimization. */
8547 mips_split_addresses_p (void)
8549 return (TARGET_SPLIT_ADDRESSES
8553 && !ABI_HAS_64BIT_SYMBOLS
);
8556 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
8559 mips_init_relocs (void)
8561 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
8562 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
8563 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
8564 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
8565 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
8567 if (TARGET_MIPS16_PCREL_LOADS
)
8568 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
8571 if (ABI_HAS_64BIT_SYMBOLS
)
8573 if (TARGET_EXPLICIT_RELOCS
)
8575 mips_split_p
[SYMBOL_64_HIGH
] = true;
8576 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
8577 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
8579 mips_split_p
[SYMBOL_64_MID
] = true;
8580 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
8581 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
8583 mips_split_p
[SYMBOL_64_LOW
] = true;
8584 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
8585 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
8587 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8588 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8593 if (TARGET_EXPLICIT_RELOCS
8594 || mips_split_addresses_p ()
8597 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8598 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
8599 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8606 /* The high part is provided by a pseudo copy of $gp. */
8607 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
8608 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
8610 else if (TARGET_EXPLICIT_RELOCS
)
8611 /* Small data constants are kept whole until after reload,
8612 then lowered by mips_rewrite_small_data. */
8613 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
8615 if (TARGET_EXPLICIT_RELOCS
)
8617 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8620 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
8621 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
8625 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
8626 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
8629 /* Expose the use of $28 as soon as possible. */
8630 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8634 /* The HIGH and LO_SUM are matched by special .md patterns. */
8635 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8637 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
8638 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
8639 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
8641 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
8642 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
8643 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
8648 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
8650 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
8651 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
8653 /* Expose the use of $28 as soon as possible. */
8654 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8660 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
8661 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
8662 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
8665 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
8666 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
8668 if (TARGET_MIPS16_PCREL_LOADS
)
8670 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
8671 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
8675 mips_split_p
[SYMBOL_DTPREL
] = true;
8676 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
8677 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
8679 mips_split_p
[SYMBOL_TPREL
] = true;
8680 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
8681 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
8684 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
8685 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
8688 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8689 in context CONTEXT. RELOCS is the array of relocations to use. */
8692 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
8693 const char **relocs
)
8695 enum mips_symbol_type symbol_type
;
8698 symbol_type
= mips_classify_symbolic_expression (op
, context
);
8699 gcc_assert (relocs
[symbol_type
]);
8701 fputs (relocs
[symbol_type
], file
);
8702 output_addr_const (file
, mips_strip_unspec_address (op
));
8703 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
8708 /* Start a new block with the given asm switch enabled. If we need
8709 to print a directive, emit PREFIX before it and SUFFIX after it. */
8712 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8713 const char *prefix
, const char *suffix
)
8715 if (asm_switch
->nesting_level
== 0)
8716 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8717 asm_switch
->nesting_level
++;
8720 /* Likewise, but end a block. */
8723 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8724 const char *prefix
, const char *suffix
)
8726 gcc_assert (asm_switch
->nesting_level
);
8727 asm_switch
->nesting_level
--;
8728 if (asm_switch
->nesting_level
== 0)
8729 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8732 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8733 that either print a complete line or print nothing. */
8736 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8738 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8742 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8744 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8747 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8748 The punctuation characters are:
8750 '(' Start a nested ".set noreorder" block.
8751 ')' End a nested ".set noreorder" block.
8752 '[' Start a nested ".set noat" block.
8753 ']' End a nested ".set noat" block.
8754 '<' Start a nested ".set nomacro" block.
8755 '>' End a nested ".set nomacro" block.
8756 '*' Behave like %(%< if generating a delayed-branch sequence.
8757 '#' Print a nop if in a ".set noreorder" block.
8758 '/' Like '#', but do nothing within a delayed-branch sequence.
8759 '?' Print "l" if mips_branch_likely is true
8760 '~' Print a nop if mips_branch_likely is true
8761 '.' Print the name of the register with a hard-wired zero (zero or $0).
8762 '@' Print the name of the assembler temporary register (at or $1).
8763 '^' Print the name of the pic call-through register (t9 or $25).
8764 '+' Print the name of the gp register (usually gp or $28).
8765 '$' Print the name of the stack pointer register (sp or $29).
8766 ':' Print "c" to use the compact version if the delay slot is a nop.
8767 '!' Print "s" to use the short version if the delay slot contains a
8770 See also mips_init_print_operand_punct. */
8773 mips_print_operand_punctuation (FILE *file
, int ch
)
8778 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8782 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8786 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8790 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8794 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8798 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8802 if (final_sequence
!= 0)
8804 mips_print_operand_punctuation (file
, '(');
8805 mips_print_operand_punctuation (file
, '<');
8810 if (mips_noreorder
.nesting_level
> 0)
8811 fputs ("\n\tnop", file
);
8815 /* Print an extra newline so that the delayed insn is separated
8816 from the following ones. This looks neater and is consistent
8817 with non-nop delayed sequences. */
8818 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8819 fputs ("\n\tnop\n", file
);
8823 if (mips_branch_likely
)
8828 if (mips_branch_likely
)
8829 fputs ("\n\tnop", file
);
8833 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8837 fputs (reg_names
[AT_REGNUM
], file
);
8841 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8845 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8849 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8853 /* When final_sequence is 0, the delay slot will be a nop. We can
8854 use the compact version where available. The %: formatter will
8855 only be present if a compact form of the branch is available. */
8856 if (final_sequence
== 0)
8861 /* If the delay slot instruction is short, then use the
8863 if (TARGET_MICROMIPS
&& !TARGET_INTERLINK_COMPRESSED
&& mips_isa_rev
<= 5
8864 && (final_sequence
== 0
8865 || get_attr_length (final_sequence
->insn (1)) == 2))
8875 /* Initialize mips_print_operand_punct. */
8878 mips_init_print_operand_punct (void)
8882 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8883 mips_print_operand_punct
[(unsigned char) *p
] = true;
8886 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8887 associated with condition CODE. Print the condition part of the
8891 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8905 /* Conveniently, the MIPS names for these conditions are the same
8906 as their RTL equivalents. */
8907 fputs (GET_RTX_NAME (code
), file
);
8911 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8916 /* Likewise floating-point branches. */
8919 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8925 fputs ("c1eqz", file
);
8927 fputs ("c1f", file
);
8932 fputs ("c1nez", file
);
8934 fputs ("c1t", file
);
8938 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8943 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8946 mips_print_operand_punct_valid_p (unsigned char code
)
8948 return mips_print_operand_punct
[code
];
8951 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8953 'E' Print CONST_INT OP element 0 of a replicated CONST_VECTOR in decimal.
8954 'X' Print CONST_INT OP in hexadecimal format.
8955 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8956 'd' Print CONST_INT OP in decimal.
8957 'B' Print CONST_INT OP element 0 of a replicated CONST_VECTOR
8958 as an unsigned byte [0..255].
8959 'm' Print one less than CONST_INT OP in decimal.
8960 'y' Print exact log2 of CONST_INT OP in decimal.
8961 'h' Print the high-part relocation associated with OP, after stripping
8963 'R' Print the low-part relocation associated with OP.
8964 'C' Print the integer branch condition for comparison OP.
8965 'N' Print the inverse of the integer branch condition for comparison OP.
8966 'F' Print the FPU branch condition for comparison OP.
8967 'W' Print the inverse of the FPU branch condition for comparison OP.
8968 'w' Print a MSA register.
8969 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8970 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8971 't' Like 'T', but with the EQ/NE cases reversed
8972 'Y' Print mips_fp_conditions[INTVAL (OP)]
8973 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8974 'q' Print a DSP accumulator register.
8975 'D' Print the second part of a double-word register or memory operand.
8976 'L' Print the low-order register in a double-word register operand.
8977 'M' Print high-order register in a double-word register operand.
8978 'z' Print $0 if OP is zero, otherwise print OP normally.
8979 'b' Print the address of a memory operand, without offset.
8980 'v' Print the insn size suffix b, h, w or d for vector modes V16QI, V8HI,
8981 V4SI, V2SI, and w, d for vector modes V4SF, V2DF respectively.
8982 'V' Print exact log2 of CONST_INT OP element 0 of a replicated
8983 CONST_VECTOR in decimal. */
8986 mips_print_operand (FILE *file
, rtx op
, int letter
)
8990 if (mips_print_operand_punct_valid_p (letter
))
8992 mips_print_operand_punctuation (file
, letter
);
8997 code
= GET_CODE (op
);
9002 if (GET_CODE (op
) == CONST_VECTOR
)
9004 gcc_assert (mips_const_vector_same_val_p (op
, GET_MODE (op
)));
9005 op
= CONST_VECTOR_ELT (op
, 0);
9006 gcc_assert (CONST_INT_P (op
));
9007 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
9010 output_operand_lossage ("invalid use of '%%%c'", letter
);
9014 if (CONST_INT_P (op
))
9015 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
9017 output_operand_lossage ("invalid use of '%%%c'", letter
);
9021 if (CONST_INT_P (op
))
9022 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
9024 output_operand_lossage ("invalid use of '%%%c'", letter
);
9028 if (CONST_INT_P (op
))
9029 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
9031 output_operand_lossage ("invalid use of '%%%c'", letter
);
9035 if (GET_CODE (op
) == CONST_VECTOR
)
9037 gcc_assert (mips_const_vector_same_val_p (op
, GET_MODE (op
)));
9038 op
= CONST_VECTOR_ELT (op
, 0);
9039 gcc_assert (CONST_INT_P (op
));
9040 unsigned HOST_WIDE_INT val8
= UINTVAL (op
) & GET_MODE_MASK (QImode
);
9041 fprintf (file
, HOST_WIDE_INT_PRINT_UNSIGNED
, val8
);
9044 output_operand_lossage ("invalid use of '%%%c'", letter
);
9048 if (CONST_INT_P (op
))
9049 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
9051 output_operand_lossage ("invalid use of '%%%c'", letter
);
9055 if (CONST_INT_P (op
))
9057 int val
= exact_log2 (INTVAL (op
));
9059 fprintf (file
, "%d", val
);
9061 output_operand_lossage ("invalid use of '%%%c'", letter
);
9064 output_operand_lossage ("invalid use of '%%%c'", letter
);
9068 if (GET_CODE (op
) == CONST_VECTOR
)
9070 machine_mode mode
= GET_MODE_INNER (GET_MODE (op
));
9071 unsigned HOST_WIDE_INT val
= UINTVAL (CONST_VECTOR_ELT (op
, 0));
9072 int vlog2
= exact_log2 (val
& GET_MODE_MASK (mode
));
9074 fprintf (file
, "%d", vlog2
);
9076 output_operand_lossage ("invalid use of '%%%c'", letter
);
9079 output_operand_lossage ("invalid use of '%%%c'", letter
);
9085 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
9089 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
9093 mips_print_int_branch_condition (file
, code
, letter
);
9097 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
9101 mips_print_float_branch_condition (file
, code
, letter
);
9105 mips_print_float_branch_condition (file
, reverse_condition (code
),
9112 int truth
= (code
== NE
) == (letter
== 'T');
9113 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
9118 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
9119 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
9121 output_operand_lossage ("'%%%c' is not a valid operand prefix",
9126 if (ISA_HAS_8CC
|| ISA_HAS_CCF
)
9128 mips_print_operand (file
, op
, 0);
9134 if (code
== REG
&& MD_REG_P (REGNO (op
)))
9135 fprintf (file
, "$ac0");
9136 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
9137 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
9139 output_operand_lossage ("invalid use of '%%%c'", letter
);
9143 if (code
== REG
&& MSA_REG_P (REGNO (op
)))
9144 fprintf (file
, "$w%s", ®_names
[REGNO (op
)][2]);
9146 output_operand_lossage ("invalid use of '%%%c'", letter
);
9150 switch (GET_MODE (op
))
9153 fprintf (file
, "b");
9156 fprintf (file
, "h");
9160 fprintf (file
, "w");
9164 fprintf (file
, "d");
9167 output_operand_lossage ("invalid use of '%%%c'", letter
);
9176 unsigned int regno
= REGNO (op
);
9177 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
9178 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
9181 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
9182 output_operand_lossage ("invalid use of '%%%c'", letter
);
9183 /* We need to print $0 .. $31 for COP0 registers. */
9184 if (COP0_REG_P (regno
))
9185 fprintf (file
, "$%s", ®_names
[regno
][4]);
9187 fprintf (file
, "%s", reg_names
[regno
]);
9193 output_address (GET_MODE (op
), plus_constant (Pmode
,
9195 else if (letter
== 'b')
9197 gcc_assert (REG_P (XEXP (op
, 0)));
9198 mips_print_operand (file
, XEXP (op
, 0), 0);
9200 else if (letter
&& letter
!= 'z')
9201 output_operand_lossage ("invalid use of '%%%c'", letter
);
9203 output_address (GET_MODE (op
), XEXP (op
, 0));
9207 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
9208 fputs (reg_names
[GP_REG_FIRST
], file
);
9209 else if (letter
&& letter
!= 'z')
9210 output_operand_lossage ("invalid use of '%%%c'", letter
);
9211 else if (CONST_GP_P (op
))
9212 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
9214 output_addr_const (file
, mips_strip_unspec_address (op
));
9220 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9223 mips_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9225 struct mips_address_info addr
;
9227 if (mips_classify_address (&addr
, x
, word_mode
, true))
9231 mips_print_operand (file
, addr
.offset
, 0);
9232 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
9235 case ADDRESS_LO_SUM
:
9236 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
9238 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
9241 case ADDRESS_CONST_INT
:
9242 output_addr_const (file
, x
);
9243 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
9246 case ADDRESS_SYMBOLIC
:
9247 output_addr_const (file
, mips_strip_unspec_address (x
));
9253 /* Implement TARGET_ENCODE_SECTION_INFO. */
9256 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
9258 default_encode_section_info (decl
, rtl
, first
);
9260 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9262 rtx symbol
= XEXP (rtl
, 0);
9263 tree type
= TREE_TYPE (decl
);
9265 /* Encode whether the symbol is short or long. */
9266 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
9267 || mips_far_type_p (type
))
9268 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
9272 /* Implement TARGET_SELECT_RTX_SECTION. */
9275 mips_select_rtx_section (machine_mode mode
, rtx x
,
9276 unsigned HOST_WIDE_INT align
)
9278 /* ??? Consider using mergeable small data sections. */
9279 if (mips_rtx_constant_in_small_data_p (mode
))
9280 return get_named_section (NULL
, ".sdata", 0);
9282 return default_elf_select_rtx_section (mode
, x
, align
);
9285 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
9287 The complication here is that, with the combination TARGET_ABICALLS
9288 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
9289 absolute addresses, and should therefore not be included in the
9290 read-only part of a DSO. Handle such cases by selecting a normal
9291 data section instead of a read-only one. The logic apes that in
9292 default_function_rodata_section. */
9295 mips_function_rodata_section (tree decl
)
9297 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
9298 return default_function_rodata_section (decl
);
9300 if (decl
&& DECL_SECTION_NAME (decl
))
9302 const char *name
= DECL_SECTION_NAME (decl
);
9303 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
9305 char *rname
= ASTRDUP (name
);
9307 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
9309 else if (flag_function_sections
9310 && flag_data_sections
9311 && strncmp (name
, ".text.", 6) == 0)
9313 char *rname
= ASTRDUP (name
);
9314 memcpy (rname
+ 1, "data", 4);
9315 return get_section (rname
, SECTION_WRITE
, decl
);
9318 return data_section
;
9321 /* Implement TARGET_IN_SMALL_DATA_P. */
9324 mips_in_small_data_p (const_tree decl
)
9326 unsigned HOST_WIDE_INT size
;
9328 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
9331 /* We don't yet generate small-data references for -mabicalls
9332 or VxWorks RTP code. See the related -G handling in
9333 mips_option_override. */
9334 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
9337 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
9341 /* Reject anything that isn't in a known small-data section. */
9342 name
= DECL_SECTION_NAME (decl
);
9343 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
9346 /* If a symbol is defined externally, the assembler will use the
9347 usual -G rules when deciding how to implement macros. */
9348 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
9351 else if (TARGET_EMBEDDED_DATA
)
9353 /* Don't put constants into the small data section: we want them
9354 to be in ROM rather than RAM. */
9355 if (TREE_CODE (decl
) != VAR_DECL
)
9358 if (TREE_READONLY (decl
)
9359 && !TREE_SIDE_EFFECTS (decl
)
9360 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
9364 /* Enforce -mlocal-sdata. */
9365 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
9368 /* Enforce -mextern-sdata. */
9369 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
9371 if (DECL_EXTERNAL (decl
))
9373 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
9377 /* We have traditionally not treated zero-sized objects as small data,
9378 so this is now effectively part of the ABI. */
9379 size
= int_size_in_bytes (TREE_TYPE (decl
));
9380 return size
> 0 && size
<= mips_small_data_threshold
;
9383 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
9384 anchors for small data: the GP register acts as an anchor in that
9385 case. We also don't want to use them for PC-relative accesses,
9386 where the PC acts as an anchor. */
9389 mips_use_anchors_for_symbol_p (const_rtx symbol
)
9391 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
9393 case SYMBOL_PC_RELATIVE
:
9394 case SYMBOL_GP_RELATIVE
:
9398 return default_use_anchors_for_symbol_p (symbol
);
9402 /* The MIPS debug format wants all automatic variables and arguments
9403 to be in terms of the virtual frame pointer (stack pointer before
9404 any adjustment in the function), while the MIPS 3.0 linker wants
9405 the frame pointer to be the stack pointer after the initial
9406 adjustment. So, we do the adjustment here. The arg pointer (which
9407 is eliminated) points to the virtual frame pointer, while the frame
9408 pointer (which may be eliminated) points to the stack pointer after
9409 the initial adjustments. */
9412 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
9414 rtx offset2
= const0_rtx
;
9415 rtx reg
= eliminate_constant_term (addr
, &offset2
);
9418 offset
= INTVAL (offset2
);
9420 if (reg
== stack_pointer_rtx
9421 || reg
== frame_pointer_rtx
9422 || reg
== hard_frame_pointer_rtx
)
9424 offset
-= cfun
->machine
->frame
.total_size
;
9425 if (reg
== hard_frame_pointer_rtx
)
9426 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9432 /* Implement ASM_OUTPUT_EXTERNAL. */
9435 mips_output_external (FILE *file
, tree decl
, const char *name
)
9437 default_elf_asm_output_external (file
, decl
, name
);
9439 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9440 set in order to avoid putting out names that are never really
9442 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
9444 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
9446 /* When using assembler macros, emit .extern directives for
9447 all small-data externs so that the assembler knows how
9450 In most cases it would be safe (though pointless) to emit
9451 .externs for other symbols too. One exception is when an
9452 object is within the -G limit but declared by the user to
9453 be in a section other than .sbss or .sdata. */
9454 fputs ("\t.extern\t", file
);
9455 assemble_name (file
, name
);
9456 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
9457 int_size_in_bytes (TREE_TYPE (decl
)));
9462 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
9465 mips_output_filename (FILE *stream
, const char *name
)
9467 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
9469 if (write_symbols
== DWARF2_DEBUG
)
9471 else if (mips_output_filename_first_time
)
9473 mips_output_filename_first_time
= 0;
9474 num_source_filenames
+= 1;
9475 current_function_file
= name
;
9476 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
9477 output_quoted_string (stream
, name
);
9478 putc ('\n', stream
);
9480 /* If we are emitting stabs, let dbxout.c handle this (except for
9481 the mips_output_filename_first_time case). */
9482 else if (write_symbols
== DBX_DEBUG
)
9484 else if (name
!= current_function_file
9485 && strcmp (name
, current_function_file
) != 0)
9487 num_source_filenames
+= 1;
9488 current_function_file
= name
;
9489 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
9490 output_quoted_string (stream
, name
);
9491 putc ('\n', stream
);
9495 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
9497 static void ATTRIBUTE_UNUSED
9498 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9503 fputs ("\t.dtprelword\t", file
);
9507 fputs ("\t.dtpreldword\t", file
);
9513 output_addr_const (file
, x
);
9514 fputs ("+0x8000", file
);
9517 /* Implement TARGET_DWARF_REGISTER_SPAN. */
9520 mips_dwarf_register_span (rtx reg
)
9525 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
9526 ensures that double-precision registers are treated as if they were
9527 64-bit physical registers. The code will run correctly with 32-bit or
9528 64-bit registers which means that dwarf information cannot be precise
9529 for all scenarios. We choose to state that the 64-bit values are stored
9530 in a single 64-bit 'piece'. This slightly unusual construct can then be
9531 interpreted as either a pair of registers if the registers are 32-bit or
9532 a single 64-bit register depending on hardware. */
9533 mode
= GET_MODE (reg
);
9534 if (FP_REG_P (REGNO (reg
))
9536 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
9538 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, reg
));
9540 /* By default, GCC maps increasing register numbers to increasing
9541 memory locations, but paired FPRs are always little-endian,
9542 regardless of the prevailing endianness. */
9543 else if (FP_REG_P (REGNO (reg
))
9544 && TARGET_BIG_ENDIAN
9545 && MAX_FPRS_PER_FMT
> 1
9546 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
9548 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
9549 high
= mips_subword (reg
, true);
9550 low
= mips_subword (reg
, false);
9551 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
9557 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
9560 mips_dwarf_frame_reg_mode (int regno
)
9562 machine_mode mode
= default_dwarf_frame_reg_mode (regno
);
9564 if (FP_REG_P (regno
) && mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9570 /* DSP ALU can bypass data with no delays for the following pairs. */
9571 enum insn_code dspalu_bypass_table
[][2] =
9573 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
9574 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
9575 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
9576 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
9577 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
9578 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
9579 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
9580 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
9584 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
9587 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
9588 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
9589 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
9591 for (i
= 0; i
< num_bypass
; i
++)
9593 if (out_icode
== dspalu_bypass_table
[i
][0]
9594 && in_icode
== dspalu_bypass_table
[i
][1])
9600 /* Implement ASM_OUTPUT_ASCII. */
9603 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
9609 fprintf (stream
, "\t.ascii\t\"");
9610 for (i
= 0; i
< len
; i
++)
9614 c
= (unsigned char) string
[i
];
9617 if (c
== '\\' || c
== '\"')
9619 putc ('\\', stream
);
9627 fprintf (stream
, "\\%03o", c
);
9631 if (cur_pos
> 72 && i
+1 < len
)
9634 fprintf (stream
, "\"\n\t.ascii\t\"");
9637 fprintf (stream
, "\"\n");
9640 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
9641 Update *ADDR with the operand that should be printed. */
9644 mips_output_tls_reloc_directive (rtx
*addr
)
9646 enum mips_symbol_type type
;
9648 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
9649 *addr
= mips_strip_unspec_address (*addr
);
9653 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
9656 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
9663 /* Emit either a label, .comm, or .lcomm directive. When using assembler
9664 macros, mark the symbol as written so that mips_asm_output_external
9665 won't emit an .extern for it. STREAM is the output file, NAME is the
9666 name of the symbol, INIT_STRING is the string that should be written
9667 before the symbol and FINAL_STRING is the string that should be
9668 written after it. FINAL_STRING is a printf format that consumes the
9669 remaining arguments. */
9672 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
9673 const char *final_string
, ...)
9677 fputs (init_string
, stream
);
9678 assemble_name (stream
, name
);
9679 va_start (ap
, final_string
);
9680 vfprintf (stream
, final_string
, ap
);
9683 if (!TARGET_EXPLICIT_RELOCS
)
9685 tree name_tree
= get_identifier (name
);
9686 TREE_ASM_WRITTEN (name_tree
) = 1;
9690 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9691 NAME is the name of the object and ALIGN is the required alignment
9692 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9693 alignment argument. */
9696 mips_declare_common_object (FILE *stream
, const char *name
,
9697 const char *init_string
,
9698 unsigned HOST_WIDE_INT size
,
9699 unsigned int align
, bool takes_alignment_p
)
9701 if (!takes_alignment_p
)
9703 size
+= (align
/ BITS_PER_UNIT
) - 1;
9704 size
-= size
% (align
/ BITS_PER_UNIT
);
9705 mips_declare_object (stream
, name
, init_string
,
9706 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
9709 mips_declare_object (stream
, name
, init_string
,
9710 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
9711 size
, align
/ BITS_PER_UNIT
);
9714 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9715 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9718 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
9719 unsigned HOST_WIDE_INT size
,
9722 /* If the target wants uninitialized const declarations in
9723 .rdata then don't put them in .comm. */
9724 if (TARGET_EMBEDDED_DATA
9725 && TARGET_UNINIT_CONST_IN_RODATA
9726 && TREE_CODE (decl
) == VAR_DECL
9727 && TREE_READONLY (decl
)
9728 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
9730 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
9731 targetm
.asm_out
.globalize_label (stream
, name
);
9733 switch_to_section (readonly_data_section
);
9734 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
9735 mips_declare_object (stream
, name
, "",
9736 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
9740 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
9744 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9745 extern int size_directive_output
;
9747 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9748 definitions except that it uses mips_declare_object to emit the label. */
9751 mips_declare_object_name (FILE *stream
, const char *name
,
9752 tree decl ATTRIBUTE_UNUSED
)
9754 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9755 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
9758 size_directive_output
= 0;
9759 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
9763 size_directive_output
= 1;
9764 size
= int_size_in_bytes (TREE_TYPE (decl
));
9765 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9768 mips_declare_object (stream
, name
, "", ":\n");
9771 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9774 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
9778 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
9779 if (!flag_inhibit_size_directive
9780 && DECL_SIZE (decl
) != 0
9783 && DECL_INITIAL (decl
) == error_mark_node
9784 && !size_directive_output
)
9788 size_directive_output
= 1;
9789 size
= int_size_in_bytes (TREE_TYPE (decl
));
9790 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9795 /* Mark text contents as code or data, mainly for the purpose of correct
9796 disassembly. Emit a local symbol and set its type appropriately for
9797 that purpose. Also emit `.insn' if marking contents as code so that
9798 the ISA mode is recorded and any padding that follows is disassembled
9799 as correct instructions. */
9802 mips_set_text_contents_type (FILE *file ATTRIBUTE_UNUSED
,
9803 const char *prefix ATTRIBUTE_UNUSED
,
9804 unsigned long num ATTRIBUTE_UNUSED
,
9805 bool function_p ATTRIBUTE_UNUSED
)
9807 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9808 char buf
[(sizeof (num
) * 10) / 4 + 2];
9813 sprintf (buf
, "%lu", num
);
9814 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
9815 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
9816 sname
= ACONCAT ((prefix
, fnname
, "_", buf
, NULL
));
9818 ASM_OUTPUT_TYPE_DIRECTIVE (file
, sname
, function_p
? "function" : "object");
9819 assemble_name (file
, sname
);
9820 fputs (":\n", file
);
9822 fputs ("\t.insn\n", file
);
9826 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9827 with the current ABI. */
9830 mips_mdebug_abi_name (void)
9843 return TARGET_64BIT
? "eabi64" : "eabi32";
9849 /* Implement TARGET_ASM_FILE_START. */
9852 mips_file_start (void)
9854 default_file_start ();
9856 /* Generate a special section to describe the ABI switches used to
9857 produce the resultant binary. */
9859 /* Record the ABI itself. Modern versions of binutils encode
9860 this information in the ELF header flags, but GDB needs the
9861 information in order to correctly debug binaries produced by
9862 older binutils. See the function mips_gdbarch_init in
9864 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
9865 mips_mdebug_abi_name ());
9867 /* There is no ELF header flag to distinguish long32 forms of the
9868 EABI from long64 forms. Emit a special section to help tools
9869 such as GDB. Do the same for o64, which is sometimes used with
9871 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9872 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9873 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9875 /* Record the NaN encoding. */
9876 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9877 fprintf (asm_out_file
, "\t.nan\t%s\n",
9878 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9880 #ifdef HAVE_AS_DOT_MODULE
9881 /* Record the FP ABI. See below for comments. */
9882 if (TARGET_NO_FLOAT
)
9883 #ifdef HAVE_AS_GNU_ATTRIBUTE
9884 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file
);
9888 else if (!TARGET_HARD_FLOAT_ABI
)
9889 fputs ("\t.module\tsoftfloat\n", asm_out_file
);
9890 else if (!TARGET_DOUBLE_FLOAT
)
9891 fputs ("\t.module\tsinglefloat\n", asm_out_file
);
9892 else if (TARGET_FLOATXX
)
9893 fputs ("\t.module\tfp=xx\n", asm_out_file
);
9894 else if (TARGET_FLOAT64
)
9895 fputs ("\t.module\tfp=64\n", asm_out_file
);
9897 fputs ("\t.module\tfp=32\n", asm_out_file
);
9899 if (TARGET_ODD_SPREG
)
9900 fputs ("\t.module\toddspreg\n", asm_out_file
);
9902 fputs ("\t.module\tnooddspreg\n", asm_out_file
);
9905 #ifdef HAVE_AS_GNU_ATTRIBUTE
9909 /* No floating-point operations, -mno-float. */
9910 if (TARGET_NO_FLOAT
)
9912 /* Soft-float code, -msoft-float. */
9913 else if (!TARGET_HARD_FLOAT_ABI
)
9915 /* Single-float code, -msingle-float. */
9916 else if (!TARGET_DOUBLE_FLOAT
)
9918 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9920 This case used 12 callee-saved double-precision registers
9921 and is deprecated. */
9922 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9923 else if (TARGET_FLOATXX
)
9925 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9926 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
&& TARGET_ODD_SPREG
)
9928 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9929 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9931 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9935 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9939 fprintf (asm_out_file
, "\t.gnu_attribute 8, 1\n");
9944 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9945 if (TARGET_ABICALLS
)
9947 fprintf (asm_out_file
, "\t.abicalls\n");
9948 if (TARGET_ABICALLS_PIC0
)
9949 fprintf (asm_out_file
, "\t.option\tpic0\n");
9952 if (flag_verbose_asm
)
9953 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9955 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9958 /* Implement TARGET_ASM_CODE_END. */
9961 mips_code_end (void)
9963 mips_finish_stub (&mips16_rdhwr_stub
);
9964 mips_finish_stub (&mips16_get_fcsr_stub
);
9965 mips_finish_stub (&mips16_set_fcsr_stub
);
9968 /* Make the last instruction frame-related and note that it performs
9969 the operation described by FRAME_PATTERN. */
9972 mips_set_frame_expr (rtx frame_pattern
)
9976 insn
= get_last_insn ();
9977 RTX_FRAME_RELATED_P (insn
) = 1;
9978 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9983 /* Return a frame-related rtx that stores REG at MEM.
9984 REG must be a single register. */
9987 mips_frame_set (rtx mem
, rtx reg
)
9991 set
= gen_rtx_SET (mem
, reg
);
9992 RTX_FRAME_RELATED_P (set
) = 1;
9997 /* Record that the epilogue has restored call-saved register REG. */
10000 mips_add_cfa_restore (rtx reg
)
10002 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
10003 mips_epilogue
.cfa_restores
);
10006 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
10007 mips16e_s2_s8_regs[X], it must also save the registers in indexes
10008 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
10009 static const unsigned char mips16e_s2_s8_regs
[] = {
10010 30, 23, 22, 21, 20, 19, 18
10012 static const unsigned char mips16e_a0_a3_regs
[] = {
10016 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
10017 ordered from the uppermost in memory to the lowest in memory. */
10018 static const unsigned char mips16e_save_restore_regs
[] = {
10019 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
10022 /* Return the index of the lowest X in the range [0, SIZE) for which
10023 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
10025 static unsigned int
10026 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
10031 for (i
= 0; i
< size
; i
++)
10032 if (BITSET_P (mask
, regs
[i
]))
10038 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
10039 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
10040 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
10041 is true for all indexes (X, SIZE). */
10044 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
10045 unsigned int size
, unsigned int *num_regs_ptr
)
10049 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
10050 for (i
++; i
< size
; i
++)
10051 if (!BITSET_P (*mask_ptr
, regs
[i
]))
10053 *num_regs_ptr
+= 1;
10054 *mask_ptr
|= 1 << regs
[i
];
10058 /* Return a simplified form of X using the register values in REG_VALUES.
10059 REG_VALUES[R] is the last value assigned to hard register R, or null
10060 if R has not been modified.
10062 This function is rather limited, but is good enough for our purposes. */
10065 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
10067 x
= avoid_constant_pool_reference (x
);
10071 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
10072 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
10073 x0
, GET_MODE (XEXP (x
, 0)));
10076 if (ARITHMETIC_P (x
))
10078 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
10079 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
10080 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
10084 && reg_values
[REGNO (x
)]
10085 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
10086 return reg_values
[REGNO (x
)];
10091 /* Return true if (set DEST SRC) stores an argument register into its
10092 caller-allocated save slot, storing the number of that argument
10093 register in *REGNO_PTR if so. REG_VALUES is as for
10094 mips16e_collect_propagate_value. */
10097 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
10098 unsigned int *regno_ptr
)
10100 unsigned int argno
, regno
;
10101 HOST_WIDE_INT offset
, required_offset
;
10104 /* Check that this is a word-mode store. */
10105 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
10108 /* Check that the register being saved is an unmodified argument
10110 regno
= REGNO (src
);
10111 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
10113 argno
= regno
- GP_ARG_FIRST
;
10115 /* Check whether the address is an appropriate stack-pointer or
10116 frame-pointer access. */
10117 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
10118 mips_split_plus (addr
, &base
, &offset
);
10119 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
10120 if (base
== hard_frame_pointer_rtx
)
10121 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10122 else if (base
!= stack_pointer_rtx
)
10124 if (offset
!= required_offset
)
10127 *regno_ptr
= regno
;
10131 /* A subroutine of mips_expand_prologue, called only when generating
10132 MIPS16e SAVE instructions. Search the start of the function for any
10133 instructions that save argument registers into their caller-allocated
10134 save slots. Delete such instructions and return a value N such that
10135 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
10136 instructions redundant. */
10138 static unsigned int
10139 mips16e_collect_argument_saves (void)
10141 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
10142 rtx_insn
*insn
, *next
;
10143 rtx set
, dest
, src
;
10144 unsigned int nargs
, regno
;
10146 push_topmost_sequence ();
10148 memset (reg_values
, 0, sizeof (reg_values
));
10149 for (insn
= get_insns (); insn
; insn
= next
)
10151 next
= NEXT_INSN (insn
);
10152 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
10155 if (!INSN_P (insn
))
10158 set
= PATTERN (insn
);
10159 if (GET_CODE (set
) != SET
)
10162 dest
= SET_DEST (set
);
10163 src
= SET_SRC (set
);
10164 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
10166 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
10168 delete_insn (insn
);
10169 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
10172 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
10173 reg_values
[REGNO (dest
)]
10174 = mips16e_collect_propagate_value (src
, reg_values
);
10178 pop_topmost_sequence ();
10183 /* Return a move between register REGNO and memory location SP + OFFSET.
10184 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
10185 Make the move a load if RESTORE_P, otherwise make it a store. */
10188 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
10189 HOST_WIDE_INT offset
, unsigned int regno
)
10193 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
10195 reg
= gen_rtx_REG (SImode
, regno
);
10198 mips_add_cfa_restore (reg
);
10199 return gen_rtx_SET (reg
, mem
);
10202 return gen_rtx_SET (mem
, reg
);
10203 return mips_frame_set (mem
, reg
);
10206 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
10207 The instruction must:
10209 - Allocate or deallocate SIZE bytes in total; SIZE is known
10212 - Save or restore as many registers in *MASK_PTR as possible.
10213 The instruction saves the first registers at the top of the
10214 allocated area, with the other registers below it.
10216 - Save NARGS argument registers above the allocated area.
10218 (NARGS is always zero if RESTORE_P.)
10220 The SAVE and RESTORE instructions cannot save and restore all general
10221 registers, so there may be some registers left over for the caller to
10222 handle. Destructively modify *MASK_PTR so that it contains the registers
10223 that still need to be saved or restored. The caller can save these
10224 registers in the memory immediately below *OFFSET_PTR, which is a
10225 byte offset from the bottom of the allocated stack area. */
10228 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
10229 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
10230 HOST_WIDE_INT size
)
10233 HOST_WIDE_INT offset
, top_offset
;
10234 unsigned int i
, regno
;
10237 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
10239 /* Calculate the number of elements in the PARALLEL. We need one element
10240 for the stack adjustment, one for each argument register save, and one
10241 for each additional register move. */
10243 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
10244 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
10247 /* Create the final PARALLEL. */
10248 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
10251 /* Add the stack pointer adjustment. */
10252 set
= gen_rtx_SET (stack_pointer_rtx
,
10253 plus_constant (Pmode
, stack_pointer_rtx
,
10254 restore_p
? size
: -size
));
10255 RTX_FRAME_RELATED_P (set
) = 1;
10256 XVECEXP (pattern
, 0, n
++) = set
;
10258 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10259 top_offset
= restore_p
? size
: 0;
10261 /* Save the arguments. */
10262 for (i
= 0; i
< nargs
; i
++)
10264 offset
= top_offset
+ i
* UNITS_PER_WORD
;
10265 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
10267 XVECEXP (pattern
, 0, n
++) = set
;
10270 /* Then fill in the other register moves. */
10271 offset
= top_offset
;
10272 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
10274 regno
= mips16e_save_restore_regs
[i
];
10275 if (BITSET_P (*mask_ptr
, regno
))
10277 offset
-= UNITS_PER_WORD
;
10278 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
10279 XVECEXP (pattern
, 0, n
++) = set
;
10280 *mask_ptr
&= ~(1 << regno
);
10284 /* Tell the caller what offset it should use for the remaining registers. */
10285 *offset_ptr
= size
+ (offset
- top_offset
);
10287 gcc_assert (n
== XVECLEN (pattern
, 0));
10292 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
10293 pointer. Return true if PATTERN matches the kind of instruction
10294 generated by mips16e_build_save_restore. If INFO is nonnull,
10295 initialize it when returning true. */
10298 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
10299 struct mips16e_save_restore_info
*info
)
10301 unsigned int i
, nargs
, mask
, extra
;
10302 HOST_WIDE_INT top_offset
, save_offset
, offset
;
10303 rtx set
, reg
, mem
, base
;
10306 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
10309 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10310 top_offset
= adjust
> 0 ? adjust
: 0;
10312 /* Interpret all other members of the PARALLEL. */
10313 save_offset
= top_offset
- UNITS_PER_WORD
;
10317 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
10319 /* Check that we have a SET. */
10320 set
= XVECEXP (pattern
, 0, n
);
10321 if (GET_CODE (set
) != SET
)
10324 /* Check that the SET is a load (if restoring) or a store
10326 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
10330 /* Check that the address is the sum of the stack pointer and a
10331 possibly-zero constant offset. */
10332 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
10333 if (base
!= stack_pointer_rtx
)
10336 /* Check that SET's other operand is a register. */
10337 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
10341 /* Check for argument saves. */
10342 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
10343 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
10345 else if (offset
== save_offset
)
10347 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
10348 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
10351 mask
|= 1 << REGNO (reg
);
10352 save_offset
-= UNITS_PER_WORD
;
10358 /* Check that the restrictions on register ranges are met. */
10360 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
10361 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
10362 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
10363 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
10367 /* Make sure that the topmost argument register is not saved twice.
10368 The checks above ensure that the same is then true for the other
10369 argument registers. */
10370 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
10373 /* Pass back information, if requested. */
10376 info
->nargs
= nargs
;
10378 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
10384 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
10385 for the register range [MIN_REG, MAX_REG]. Return a pointer to
10386 the null terminator. */
10389 mips16e_add_register_range (char *s
, unsigned int min_reg
,
10390 unsigned int max_reg
)
10392 if (min_reg
!= max_reg
)
10393 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
10395 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
10399 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
10400 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
10403 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
10405 static char buffer
[300];
10407 struct mips16e_save_restore_info info
;
10408 unsigned int i
, end
;
10411 /* Parse the pattern. */
10412 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
10413 gcc_unreachable ();
10415 /* Add the mnemonic. */
10416 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
10419 /* Save the arguments. */
10420 if (info
.nargs
> 1)
10421 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
10422 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
10423 else if (info
.nargs
== 1)
10424 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
10426 /* Emit the amount of stack space to allocate or deallocate. */
10427 s
+= sprintf (s
, "%d", (int) info
.size
);
10429 /* Save or restore $16. */
10430 if (BITSET_P (info
.mask
, 16))
10431 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
10433 /* Save or restore $17. */
10434 if (BITSET_P (info
.mask
, 17))
10435 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
10437 /* Save or restore registers in the range $s2...$s8, which
10438 mips16e_s2_s8_regs lists in decreasing order. Note that this
10439 is a software register range; the hardware registers are not
10440 numbered consecutively. */
10441 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
10442 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
10444 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
10445 mips16e_s2_s8_regs
[i
]);
10447 /* Save or restore registers in the range $a0...$a3. */
10448 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
10449 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
10451 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
10452 mips16e_a0_a3_regs
[end
- 1]);
10454 /* Save or restore $31. */
10455 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
10456 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
10461 /* Return true if the current function returns its value in a floating-point
10462 register in MIPS16 mode. */
10465 mips16_cfun_returns_in_fpr_p (void)
10467 tree return_type
= DECL_RESULT (current_function_decl
);
10468 return (TARGET_MIPS16
10469 && TARGET_HARD_FLOAT_ABI
10470 && !aggregate_value_p (return_type
, current_function_decl
)
10471 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
10474 /* Return true if predicate PRED is true for at least one instruction.
10475 Cache the result in *CACHE, and assume that the result is true
10476 if *CACHE is already true. */
10479 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
10481 rtx_insn
*insn
, *subinsn
;
10485 push_topmost_sequence ();
10486 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10487 FOR_EACH_SUBINSN (subinsn
, insn
)
10488 if (USEFUL_INSN_P (subinsn
) && pred (subinsn
))
10493 pop_topmost_sequence ();
10498 /* Return true if INSN refers to the global pointer in an "inflexible" way.
10499 See mips_cfun_has_inflexible_gp_ref_p for details. */
10502 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
10504 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
10505 indicate that the target could be a traditional MIPS
10506 lazily-binding stub. */
10507 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
10510 /* Return true if the current function refers to the global pointer
10511 in a way that forces $28 to be valid. This means that we can't
10512 change the choice of global pointer, even for NewABI code.
10514 One example of this (and one which needs several checks) is that
10515 $28 must be valid when calling traditional MIPS lazy-binding stubs.
10516 (This restriction does not apply to PLTs.) */
10519 mips_cfun_has_inflexible_gp_ref_p (void)
10521 /* If the function has a nonlocal goto, $28 must hold the correct
10522 global pointer for the target function. That is, the target
10523 of the goto implicitly uses $28. */
10524 if (crtl
->has_nonlocal_goto
)
10527 if (TARGET_ABICALLS_PIC2
)
10529 /* Symbolic accesses implicitly use the global pointer unless
10530 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
10531 might go to traditional MIPS lazy-binding stubs. */
10532 if (!TARGET_EXPLICIT_RELOCS
)
10535 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
10536 can be lazily-bound. */
10540 /* MIPS16 functions that return in FPRs need to call an
10541 external libgcc routine. This call is only made explict
10542 during mips_expand_epilogue, and it too might be lazily bound. */
10543 if (mips16_cfun_returns_in_fpr_p ())
10547 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
10548 mips_insn_has_inflexible_gp_ref_p
);
10551 /* Return true if INSN refers to the global pointer in a "flexible" way.
10552 See mips_cfun_has_flexible_gp_ref_p for details. */
10555 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
10557 return (get_attr_got (insn
) != GOT_UNSET
10558 || mips_small_data_pattern_p (PATTERN (insn
))
10559 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
10562 /* Return true if the current function references the global pointer,
10563 but if those references do not inherently require the global pointer
10564 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
10567 mips_cfun_has_flexible_gp_ref_p (void)
10569 /* Reload can sometimes introduce constant pool references
10570 into a function that otherwise didn't need them. For example,
10571 suppose we have an instruction like:
10573 (set (reg:DF R1) (float:DF (reg:SI R2)))
10575 If R2 turns out to be a constant such as 1, the instruction may
10576 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
10577 the option of using this constant if R2 doesn't get allocated
10580 In cases like these, reload will have added the constant to the
10581 pool but no instruction will yet refer to it. */
10582 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
10585 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
10586 mips_insn_has_flexible_gp_ref_p
);
10589 /* Return the register that should be used as the global pointer
10590 within this function. Return INVALID_REGNUM if the function
10591 doesn't need a global pointer. */
10593 static unsigned int
10594 mips_global_pointer (void)
10596 unsigned int regno
;
10598 /* $gp is always available unless we're using a GOT. */
10599 if (!TARGET_USE_GOT
)
10600 return GLOBAL_POINTER_REGNUM
;
10602 /* If there are inflexible references to $gp, we must use the
10603 standard register. */
10604 if (mips_cfun_has_inflexible_gp_ref_p ())
10605 return GLOBAL_POINTER_REGNUM
;
10607 /* If there are no current references to $gp, then the only uses
10608 we can introduce later are those involved in long branches. */
10609 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
10610 return INVALID_REGNUM
;
10612 /* If the global pointer is call-saved, try to use a call-clobbered
10614 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
10615 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10616 if (!df_regs_ever_live_p (regno
)
10617 && call_really_used_regs
[regno
]
10618 && !fixed_regs
[regno
]
10619 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
10622 return GLOBAL_POINTER_REGNUM
;
10625 /* Return true if the current function's prologue must load the global
10626 pointer value into pic_offset_table_rtx and store the same value in
10627 the function's cprestore slot (if any).
10629 One problem we have to deal with is that, when emitting GOT-based
10630 position independent code, long-branch sequences will need to load
10631 the address of the branch target from the GOT. We don't know until
10632 the very end of compilation whether (and where) the function needs
10633 long branches, so we must ensure that _any_ branch can access the
10634 global pointer in some form. However, we do not want to pessimize
10635 the usual case in which all branches are short.
10637 We handle this as follows:
10639 (1) During reload, we set cfun->machine->global_pointer to
10640 INVALID_REGNUM if we _know_ that the current function
10641 doesn't need a global pointer. This is only valid if
10642 long branches don't need the GOT.
10644 Otherwise, we assume that we might need a global pointer
10645 and pick an appropriate register.
10647 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
10648 we ensure that the global pointer is available at every
10649 block boundary bar entry and exit. We do this in one of two ways:
10651 - If the function has a cprestore slot, we ensure that this
10652 slot is valid at every branch. However, as explained in
10653 point (6) below, there is no guarantee that pic_offset_table_rtx
10654 itself is valid if new uses of the global pointer are introduced
10655 after the first post-epilogue split.
10657 We guarantee that the cprestore slot is valid by loading it
10658 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
10659 this register live at every block boundary bar function entry
10660 and exit. It is then invalid to move the load (and thus the
10661 preceding store) across a block boundary.
10663 - If the function has no cprestore slot, we guarantee that
10664 pic_offset_table_rtx itself is valid at every branch.
10666 See mips_eh_uses for the handling of the register liveness.
10668 (3) During prologue and epilogue generation, we emit "ghost"
10669 placeholder instructions to manipulate the global pointer.
10671 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
10672 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
10673 that the function needs a global pointer. (There is no need to set
10674 them earlier than this, and doing it as late as possible leads to
10675 fewer false positives.)
10677 (5) If cfun->machine->must_initialize_gp_p is true during a
10678 split_insns pass, we split the ghost instructions into real
10679 instructions. These split instructions can then be optimized in
10680 the usual way. Otherwise, we keep the ghost instructions intact,
10681 and optimize for the case where they aren't needed. We still
10682 have the option of splitting them later, if we need to introduce
10683 new uses of the global pointer.
10685 For example, the scheduler ignores a ghost instruction that
10686 stores $28 to the stack, but it handles the split form of
10687 the ghost instruction as an ordinary store.
10689 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
10690 is true during the first post-epilogue split_insns pass, we split
10691 calls and restore_gp patterns into instructions that explicitly
10692 load pic_offset_table_rtx from the cprestore slot. Otherwise,
10693 we split these patterns into instructions that _don't_ load from
10694 the cprestore slot.
10696 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
10697 time of the split, then any instructions that exist at that time
10698 can make free use of pic_offset_table_rtx. However, if we want
10699 to introduce new uses of the global pointer after the split,
10700 we must explicitly load the value from the cprestore slot, since
10701 pic_offset_table_rtx itself might not be valid at a given point
10704 The idea is that we want to be able to delete redundant
10705 loads from the cprestore slot in the usual case where no
10706 long branches are needed.
10708 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10709 of md_reorg, we decide whether the global pointer is needed for
10710 long branches. If so, we set cfun->machine->must_initialize_gp_p
10711 to true and split the ghost instructions into real instructions
10714 Note that the ghost instructions must have a zero length for three reasons:
10716 - Giving the length of the underlying $gp sequence might cause
10717 us to use long branches in cases where they aren't really needed.
10719 - They would perturb things like alignment calculations.
10721 - More importantly, the hazard detection in md_reorg relies on
10722 empty instructions having a zero length.
10724 If we find a long branch and split the ghost instructions at the
10725 end of md_reorg, the split could introduce more long branches.
10726 That isn't a problem though, because we still do the split before
10727 the final shorten_branches pass.
10729 This is extremely ugly, but it seems like the best compromise between
10730 correctness and efficiency. */
10733 mips_must_initialize_gp_p (void)
10735 return cfun
->machine
->must_initialize_gp_p
;
10738 /* Return true if REGNO is a register that is ordinarily call-clobbered
10739 but must nevertheless be preserved by an interrupt handler. */
10742 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
10744 if ((ISA_HAS_HILO
|| TARGET_DSP
)
10745 && MD_REG_P (regno
))
10748 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
10751 if (GP_REG_P (regno
)
10752 && cfun
->machine
->use_shadow_register_set
== SHADOW_SET_NO
)
10754 /* $0 is hard-wired. */
10755 if (regno
== GP_REG_FIRST
)
10758 /* The interrupt handler can treat kernel registers as
10759 scratch registers. */
10760 if (KERNEL_REG_P (regno
))
10763 /* The function will return the stack pointer to its original value
10765 if (regno
== STACK_POINTER_REGNUM
)
10768 /* Otherwise, return true for registers that aren't ordinarily
10770 return call_really_used_regs
[regno
];
10776 /* Return true if the current function should treat register REGNO
10780 mips_cfun_call_saved_reg_p (unsigned int regno
)
10782 /* If the user makes an ordinarily-call-saved register global,
10783 that register is no longer call-saved. */
10784 if (global_regs
[regno
])
10787 /* Interrupt handlers need to save extra registers. */
10788 if (cfun
->machine
->interrupt_handler_p
10789 && mips_interrupt_extra_call_saved_reg_p (regno
))
10792 /* call_insns preserve $28 unless they explicitly say otherwise,
10793 so call_really_used_regs[] treats $28 as call-saved. However,
10794 we want the ABI property rather than the default call_insn
10796 return (regno
== GLOBAL_POINTER_REGNUM
10797 ? TARGET_CALL_SAVED_GP
10798 : !call_really_used_regs
[regno
]);
10801 /* Return true if the function body might clobber register REGNO.
10802 We know that REGNO is call-saved. */
10805 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
10807 /* Some functions should be treated as clobbering all call-saved
10809 if (crtl
->saves_all_registers
)
10812 /* DF handles cases where a register is explicitly referenced in
10813 the rtl. Incoming values are passed in call-clobbered registers,
10814 so we can assume that any live call-saved register is set within
10816 if (df_regs_ever_live_p (regno
))
10819 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10820 These clobbers are not explicit in the rtl. */
10821 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
10824 /* If we're using a call-saved global pointer, the function's
10825 prologue will need to set it up. */
10826 if (cfun
->machine
->global_pointer
== regno
)
10829 /* The function's prologue will need to set the frame pointer if
10830 frame_pointer_needed. */
10831 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
10834 /* If a MIPS16 function returns a value in FPRs, its epilogue
10835 will need to call an external libgcc routine. This yet-to-be
10836 generated call_insn will clobber $31. */
10837 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
10840 /* If REGNO is ordinarily call-clobbered, we must assume that any
10841 called function could modify it. */
10842 if (cfun
->machine
->interrupt_handler_p
10844 && mips_interrupt_extra_call_saved_reg_p (regno
))
10850 /* Return true if the current function must save register REGNO. */
10853 mips_save_reg_p (unsigned int regno
)
10855 if (mips_cfun_call_saved_reg_p (regno
))
10857 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
10860 /* Save both registers in an FPR pair if either one is used. This is
10861 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10862 register to be used without the even register. */
10863 if (FP_REG_P (regno
)
10864 && MAX_FPRS_PER_FMT
== 2
10865 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
10869 /* We need to save the incoming return address if __builtin_eh_return
10870 is being used to set a different return address. */
10871 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
10877 /* Populate the current function's mips_frame_info structure.
10879 MIPS stack frames look like:
10881 +-------------------------------+
10883 | incoming stack arguments |
10885 +-------------------------------+
10887 | caller-allocated save area |
10888 A | for register arguments |
10890 +-------------------------------+ <-- incoming stack pointer
10892 | callee-allocated save area |
10893 B | for arguments that are |
10894 | split between registers and |
10897 +-------------------------------+ <-- arg_pointer_rtx
10899 C | callee-allocated save area |
10900 | for register varargs |
10902 +-------------------------------+ <-- frame_pointer_rtx
10903 | | + cop0_sp_offset
10904 | COP0 reg save area | + UNITS_PER_WORD
10906 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10907 | | + UNITS_PER_WORD
10908 | accumulator save area |
10910 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10911 | | + UNITS_PER_HWFPVALUE
10914 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10915 | | + UNITS_PER_WORD
10918 +-------------------------------+ <-- frame_pointer_rtx with
10919 | | \ -fstack-protector
10920 | local variables | | var_size
10922 +-------------------------------+
10924 | $gp save area | | cprestore_size
10926 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10928 | outgoing stack arguments | |
10930 +-------------------------------+ | args_size
10932 | caller-allocated save area | |
10933 | for register arguments | |
10935 +-------------------------------+ <-- stack_pointer_rtx
10936 frame_pointer_rtx without
10938 hard_frame_pointer_rtx for
10941 At least two of A, B and C will be empty.
10943 Dynamic stack allocations such as alloca insert data at point P.
10944 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10945 hard_frame_pointer_rtx unchanged. */
10948 mips_compute_frame_info (void)
10950 struct mips_frame_info
*frame
;
10951 HOST_WIDE_INT offset
, size
;
10952 unsigned int regno
, i
;
10954 /* Skip re-computing the frame info after reload completed. */
10955 if (reload_completed
)
10958 /* Set this function's interrupt properties. */
10959 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10961 if (mips_isa_rev
< 2)
10962 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10963 else if (TARGET_MIPS16
)
10964 error ("interrupt handlers cannot be MIPS16 functions");
10967 cfun
->machine
->interrupt_handler_p
= true;
10968 cfun
->machine
->int_mask
=
10969 mips_interrupt_mask (TREE_TYPE (current_function_decl
));
10970 cfun
->machine
->use_shadow_register_set
=
10971 mips_use_shadow_register_set (TREE_TYPE (current_function_decl
));
10972 cfun
->machine
->keep_interrupts_masked_p
=
10973 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10974 cfun
->machine
->use_debug_exception_return_p
=
10975 mips_use_debug_exception_return_p (TREE_TYPE
10976 (current_function_decl
));
10980 frame
= &cfun
->machine
->frame
;
10981 memset (frame
, 0, sizeof (*frame
));
10982 size
= get_frame_size ();
10984 /* The first two blocks contain the outgoing argument area and the $gp save
10985 slot. This area isn't needed in leaf functions. We can also skip it
10986 if we know that none of the called functions will use this space.
10988 But if the target-independent frame size is nonzero, we have already
10989 committed to allocating these in TARGET_STARTING_FRAME_OFFSET for
10990 !FRAME_GROWS_DOWNWARD. */
10992 if ((size
== 0 || FRAME_GROWS_DOWNWARD
)
10993 && (crtl
->is_leaf
|| (cfun
->machine
->optimize_call_stack
&& !flag_pic
)))
10995 /* The MIPS 3.0 linker does not like functions that dynamically
10996 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10997 looks like we are trying to create a second frame pointer to the
10998 function, so allocate some stack space to make it happy. */
10999 if (cfun
->calls_alloca
)
11000 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
11002 frame
->args_size
= 0;
11003 frame
->cprestore_size
= 0;
11007 frame
->args_size
= crtl
->outgoing_args_size
;
11008 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
11011 /* MIPS16 code offsets the frame pointer by the size of the outgoing
11012 arguments. This tends to increase the chances of using unextended
11013 instructions for local variables and incoming arguments. */
11015 frame
->hard_frame_pointer_offset
= frame
->args_size
;
11017 /* PR 69129 / 69012: Beware of a possible race condition. mips_global_pointer
11018 might call mips_cfun_has_inflexible_gp_ref_p which in turn can call
11019 mips_find_gp_ref which will iterate over the current insn sequence.
11020 If any of these insns use the cprestore_save_slot_operand or
11021 cprestore_load_slot_operand predicates in order to be recognised then
11022 they will call mips_cprestore_address_p which calls
11023 mips_get_cprestore_base_and_offset which expects the frame information
11024 to be filled in... In fact mips_get_cprestore_base_and_offset only
11025 needs the args_size and hard_frame_pointer_offset fields to be filled
11026 in, which is why the global_pointer field is initialised here and not
11028 cfun
->machine
->global_pointer
= mips_global_pointer ();
11030 offset
= frame
->args_size
+ frame
->cprestore_size
;
11032 /* Move above the local variables. */
11033 frame
->var_size
= MIPS_STACK_ALIGN (size
);
11034 offset
+= frame
->var_size
;
11036 /* Find out which GPRs we need to save. */
11037 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
11038 if (mips_save_reg_p (regno
))
11041 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
11044 /* If this function calls eh_return, we must also save and restore the
11045 EH data registers. */
11046 if (crtl
->calls_eh_return
)
11047 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
11050 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
11053 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
11054 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
11055 save all later registers too. */
11056 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11058 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
11059 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
11060 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
11061 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
11064 /* Move above the GPR save area. */
11065 if (frame
->num_gp
> 0)
11067 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
11068 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
11071 /* Find out which FPRs we need to save. This loop must iterate over
11072 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
11073 if (TARGET_HARD_FLOAT
)
11074 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
11075 if (mips_save_reg_p (regno
))
11077 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
11078 frame
->fmask
|= ~(~0U << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
11081 /* Move above the FPR save area. */
11082 if (frame
->num_fp
> 0)
11084 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
11085 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
11088 /* Add in space for the interrupt context information. */
11089 if (cfun
->machine
->interrupt_handler_p
)
11092 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
11095 frame
->acc_mask
|= (1 << 0);
11098 /* Check accumulators 1, 2, 3. */
11099 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
11100 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
11103 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
11106 /* All interrupt context functions need space to preserve STATUS. */
11107 frame
->num_cop0_regs
++;
11109 /* We need to save EPC regardless of whether interrupts remain masked
11110 as exceptions will corrupt EPC. */
11111 frame
->num_cop0_regs
++;
11114 /* Move above the accumulator save area. */
11115 if (frame
->num_acc
> 0)
11117 /* Each accumulator needs 2 words. */
11118 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
11119 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
11122 /* Move above the COP0 register save area. */
11123 if (frame
->num_cop0_regs
> 0)
11125 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
11126 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
11129 /* Determine if we can save the callee-saved registers in the frame
11130 header. Restrict this to functions where there is no other reason
11131 to allocate stack space so that we can eliminate the instructions
11132 that modify the stack pointer. */
11136 && flag_frame_header_optimization
11137 && !MAIN_NAME_P (DECL_NAME (current_function_decl
))
11138 && cfun
->machine
->varargs_size
== 0
11139 && crtl
->args
.pretend_args_size
== 0
11140 && frame
->var_size
== 0
11141 && frame
->num_acc
== 0
11142 && frame
->num_cop0_regs
== 0
11143 && frame
->num_fp
== 0
11144 && frame
->num_gp
> 0
11145 && frame
->num_gp
<= MAX_ARGS_IN_REGISTERS
11146 && !GENERATE_MIPS16E_SAVE_RESTORE
11147 && !cfun
->machine
->interrupt_handler_p
11148 && cfun
->machine
->does_not_use_frame_header
11149 && cfun
->machine
->optimize_call_stack
11150 && !cfun
->machine
->callers_may_not_allocate_frame
11151 && !mips_cfun_has_cprestore_slot_p ())
11154 frame
->gp_sp_offset
= REG_PARM_STACK_SPACE(cfun
) - UNITS_PER_WORD
;
11155 cfun
->machine
->use_frame_header_for_callee_saved_regs
= true;
11158 /* Move above the callee-allocated varargs save area. */
11159 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
11160 frame
->arg_pointer_offset
= offset
;
11162 /* Move above the callee-allocated area for pretend stack arguments. */
11163 offset
+= crtl
->args
.pretend_args_size
;
11164 frame
->total_size
= offset
;
11166 /* Work out the offsets of the save areas from the top of the frame. */
11167 if (frame
->gp_sp_offset
> 0)
11168 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
11169 if (frame
->fp_sp_offset
> 0)
11170 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
11171 if (frame
->acc_sp_offset
> 0)
11172 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
11173 if (frame
->num_cop0_regs
> 0)
11174 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
11177 /* Return the style of GP load sequence that is being used for the
11178 current function. */
11180 enum mips_loadgp_style
11181 mips_current_loadgp_style (void)
11183 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
11184 return LOADGP_NONE
;
11186 if (TARGET_RTP_PIC
)
11189 if (TARGET_ABSOLUTE_ABICALLS
)
11190 return LOADGP_ABSOLUTE
;
11192 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
11195 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11198 mips_frame_pointer_required (void)
11200 /* If the function contains dynamic stack allocations, we need to
11201 use the frame pointer to access the static parts of the frame. */
11202 if (cfun
->calls_alloca
)
11205 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
11206 reload may be unable to compute the address of a local variable,
11207 since there is no way to add a large constant to the stack pointer
11208 without using a second temporary register. */
11211 mips_compute_frame_info ();
11212 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
11219 /* Make sure that we're not trying to eliminate to the wrong hard frame
11223 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11225 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
11228 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
11229 or argument pointer. TO is either the stack pointer or hard frame
11233 mips_initial_elimination_offset (int from
, int to
)
11235 HOST_WIDE_INT offset
;
11237 mips_compute_frame_info ();
11239 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
11242 case FRAME_POINTER_REGNUM
:
11243 if (FRAME_GROWS_DOWNWARD
)
11244 offset
= (cfun
->machine
->frame
.args_size
11245 + cfun
->machine
->frame
.cprestore_size
11246 + cfun
->machine
->frame
.var_size
);
11251 case ARG_POINTER_REGNUM
:
11252 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
11256 gcc_unreachable ();
11259 if (to
== HARD_FRAME_POINTER_REGNUM
)
11260 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
11265 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
11268 mips_extra_live_on_entry (bitmap regs
)
11270 if (TARGET_USE_GOT
)
11272 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
11273 the global pointer. */
11274 if (!TARGET_ABSOLUTE_ABICALLS
)
11275 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
11277 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
11278 the global pointer. */
11280 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
11282 /* See the comment above load_call<mode> for details. */
11283 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
11287 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
11291 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
11296 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
11299 /* Emit code to change the current function's return address to
11300 ADDRESS. SCRATCH is available as a scratch register, if needed.
11301 ADDRESS and SCRATCH are both word-mode GPRs. */
11304 mips_set_return_address (rtx address
, rtx scratch
)
11308 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
11309 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
11310 cfun
->machine
->frame
.gp_sp_offset
);
11311 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
11314 /* Return true if the current function has a cprestore slot. */
11317 mips_cfun_has_cprestore_slot_p (void)
11319 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
11320 && cfun
->machine
->frame
.cprestore_size
> 0);
11323 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
11324 cprestore slot. LOAD_P is true if the caller wants to load from
11325 the cprestore slot; it is false if the caller wants to store to
11329 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
11332 const struct mips_frame_info
*frame
;
11334 frame
= &cfun
->machine
->frame
;
11335 /* .cprestore always uses the stack pointer instead of the frame pointer.
11336 We have a free choice for direct stores for non-MIPS16 functions,
11337 and for MIPS16 functions whose cprestore slot is in range of the
11338 stack pointer. Using the stack pointer would sometimes give more
11339 (early) scheduling freedom, but using the frame pointer would
11340 sometimes give more (late) scheduling freedom. It's hard to
11341 predict which applies to a given function, so let's keep things
11344 Loads must always use the frame pointer in functions that call
11345 alloca, and there's little benefit to using the stack pointer
11347 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
11349 *base
= hard_frame_pointer_rtx
;
11350 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
11354 *base
= stack_pointer_rtx
;
11355 *offset
= frame
->args_size
;
11359 /* Return true if X is the load or store address of the cprestore slot;
11360 LOAD_P says which. */
11363 mips_cprestore_address_p (rtx x
, bool load_p
)
11365 rtx given_base
, required_base
;
11366 HOST_WIDE_INT given_offset
, required_offset
;
11368 mips_split_plus (x
, &given_base
, &given_offset
);
11369 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
11370 return given_base
== required_base
&& given_offset
== required_offset
;
11373 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
11374 going to load from it, false if we are going to store to it.
11375 Use TEMP as a temporary register if need be. */
11378 mips_cprestore_slot (rtx temp
, bool load_p
)
11381 HOST_WIDE_INT offset
;
11383 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
11384 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
11387 /* Emit instructions to save global pointer value GP into cprestore
11388 slot MEM. OFFSET is the offset that MEM applies to the base register.
11390 MEM may not be a legitimate address. If it isn't, TEMP is a
11391 temporary register that can be used, otherwise it is a SCRATCH. */
11394 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
11396 if (TARGET_CPRESTORE_DIRECTIVE
)
11398 gcc_assert (gp
== pic_offset_table_rtx
);
11399 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
11402 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
11405 /* Restore $gp from its save slot, using TEMP as a temporary base register
11406 if need be. This function is for o32 and o64 abicalls only.
11408 See mips_must_initialize_gp_p for details about how we manage the
11412 mips_restore_gp_from_cprestore_slot (rtx temp
)
11414 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
11416 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
11418 emit_note (NOTE_INSN_DELETED
);
11424 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
11425 mips_emit_move (pic_offset_table_rtx
, temp
);
11428 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
11429 if (!TARGET_EXPLICIT_RELOCS
)
11430 emit_insn (gen_blockage ());
11433 /* A function to save or store a register. The first argument is the
11434 register and the second is the stack slot. */
11435 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
11437 /* Use FN to save or restore register REGNO. MODE is the register's
11438 mode and OFFSET is the offset of its save slot from the current
11442 mips_save_restore_reg (machine_mode mode
, int regno
,
11443 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
11447 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11449 fn (gen_rtx_REG (mode
, regno
), mem
);
11452 /* Call FN for each accumulator that is saved by the current function.
11453 SP_OFFSET is the offset of the current stack pointer from the start
11457 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
11459 HOST_WIDE_INT offset
;
11462 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
11463 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
11465 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
11466 offset
-= UNITS_PER_WORD
;
11467 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
11468 offset
-= UNITS_PER_WORD
;
11471 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
11472 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
11473 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
11475 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
11476 offset
-= UNITS_PER_WORD
;
11480 /* Save register REG to MEM. Make the instruction frame-related. */
11483 mips_save_reg (rtx reg
, rtx mem
)
11485 if (GET_MODE (reg
) == DFmode
11486 && (!TARGET_FLOAT64
11487 || mips_abi
== ABI_32
))
11491 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
11493 x1
= mips_frame_set (mips_subword (mem
, false),
11494 mips_subword (reg
, false));
11495 x2
= mips_frame_set (mips_subword (mem
, true),
11496 mips_subword (reg
, true));
11497 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
11500 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
11503 /* Capture the register combinations that are allowed in a SWM or LWM
11504 instruction. The entries are ordered by number of registers set in
11505 the mask. We also ignore the single register encodings because a
11506 normal SW/LW is preferred. */
11508 static const unsigned int umips_swm_mask
[17] = {
11509 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
11510 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
11511 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
11512 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
11516 static const unsigned int umips_swm_encoding
[17] = {
11517 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
11520 /* Try to use a microMIPS LWM or SWM instruction to save or restore
11521 as many GPRs in *MASK as possible. *OFFSET is the offset from the
11522 stack pointer of the topmost save slot.
11524 Remove from *MASK all registers that were handled using LWM and SWM.
11525 Update *OFFSET so that it points to the first unused save slot. */
11528 umips_build_save_restore (mips_save_restore_fn fn
,
11529 unsigned *mask
, HOST_WIDE_INT
*offset
)
11533 rtx pattern
, set
, reg
, mem
;
11534 HOST_WIDE_INT this_offset
;
11537 /* Try matching $16 to $31 (s0 to ra). */
11538 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
11539 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
11542 if (i
== ARRAY_SIZE (umips_swm_mask
))
11545 /* Get the offset of the lowest save slot. */
11546 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
11547 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
11549 /* LWM/SWM can only support offsets from -2048 to 2047. */
11550 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
11553 /* Create the final PARALLEL. */
11554 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
11555 this_base
= stack_pointer_rtx
;
11557 /* For registers $16-$23 and $30. */
11558 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
11560 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
11561 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
11562 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
11563 *mask
&= ~(1 << regno
);
11564 reg
= gen_rtx_REG (SImode
, regno
);
11565 if (fn
== mips_save_reg
)
11566 set
= mips_frame_set (mem
, reg
);
11569 set
= gen_rtx_SET (reg
, mem
);
11570 mips_add_cfa_restore (reg
);
11572 XVECEXP (pattern
, 0, j
) = set
;
11575 /* For register $31. */
11576 if (umips_swm_encoding
[i
] >> 4)
11578 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
11579 *mask
&= ~(1 << 31);
11580 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
11581 reg
= gen_rtx_REG (SImode
, 31);
11582 if (fn
== mips_save_reg
)
11583 set
= mips_frame_set (mem
, reg
);
11586 set
= gen_rtx_SET (reg
, mem
);
11587 mips_add_cfa_restore (reg
);
11589 XVECEXP (pattern
, 0, j
) = set
;
11592 pattern
= emit_insn (pattern
);
11593 if (fn
== mips_save_reg
)
11594 RTX_FRAME_RELATED_P (pattern
) = 1;
11596 /* Adjust the last offset. */
11597 *offset
-= UNITS_PER_WORD
* nregs
;
11602 /* Call FN for each register that is saved by the current function.
11603 SP_OFFSET is the offset of the current stack pointer from the start
11607 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
11608 mips_save_restore_fn fn
)
11610 machine_mode fpr_mode
;
11612 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
11613 HOST_WIDE_INT offset
;
11616 /* Save registers starting from high to low. The debuggers prefer at least
11617 the return register be stored at func+4, and also it allows us not to
11618 need a nop in the epilogue if at least one register is reloaded in
11619 addition to return address. */
11620 offset
= frame
->gp_sp_offset
- sp_offset
;
11621 mask
= frame
->mask
;
11623 if (TARGET_MICROMIPS
)
11624 umips_build_save_restore (fn
, &mask
, &offset
);
11626 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
11627 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11629 /* Record the ra offset for use by mips_function_profiler. */
11630 if (regno
== RETURN_ADDR_REGNUM
)
11631 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
11632 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
11633 offset
-= UNITS_PER_WORD
;
11636 /* This loop must iterate over the same space as its companion in
11637 mips_compute_frame_info. */
11638 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
11639 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
11640 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
11641 regno
>= FP_REG_FIRST
;
11642 regno
-= MAX_FPRS_PER_FMT
)
11643 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
11645 if (!TARGET_FLOAT64
&& TARGET_DOUBLE_FLOAT
11646 && (fixed_regs
[regno
] || fixed_regs
[regno
+ 1]))
11648 if (fixed_regs
[regno
])
11649 mips_save_restore_reg (SFmode
, regno
+ 1, offset
, fn
);
11651 mips_save_restore_reg (SFmode
, regno
, offset
, fn
);
11654 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
11655 offset
-= GET_MODE_SIZE (fpr_mode
);
11659 /* Return true if a move between register REGNO and its save slot (MEM)
11660 can be done in a single move. LOAD_P is true if we are loading
11661 from the slot, false if we are storing to it. */
11664 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
11666 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
11667 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
11670 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
11671 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
11674 /* Emit a move from SRC to DEST, given that one of them is a register
11675 save slot and that the other is a register. TEMP is a temporary
11676 GPR of the same mode that is available if need be. */
11679 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
11681 unsigned int regno
;
11686 regno
= REGNO (src
);
11691 regno
= REGNO (dest
);
11695 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
11697 /* We don't yet know whether we'll need this instruction or not.
11698 Postpone the decision by emitting a ghost move. This move
11699 is specifically not frame-related; only the split version is. */
11701 emit_insn (gen_move_gpdi (dest
, src
));
11703 emit_insn (gen_move_gpsi (dest
, src
));
11707 if (regno
== HI_REGNUM
)
11711 mips_emit_move (temp
, src
);
11713 emit_insn (gen_mthidi_ti (gen_rtx_REG (TImode
, MD_REG_FIRST
),
11714 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
11716 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
11717 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
11722 emit_insn (gen_mfhidi_ti (temp
,
11723 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
11725 emit_insn (gen_mfhisi_di (temp
,
11726 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
11727 mips_emit_move (dest
, temp
);
11730 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
11731 mips_emit_move (dest
, src
);
11734 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
11735 mips_emit_move (temp
, src
);
11736 mips_emit_move (dest
, temp
);
11739 mips_set_frame_expr (mips_frame_set (dest
, src
));
11742 /* If we're generating n32 or n64 abicalls, and the current function
11743 does not use $28 as its global pointer, emit a cplocal directive.
11744 Use pic_offset_table_rtx as the argument to the directive. */
11747 mips_output_cplocal (void)
11749 if (!TARGET_EXPLICIT_RELOCS
11750 && mips_must_initialize_gp_p ()
11751 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
11752 output_asm_insn (".cplocal %+", 0);
11755 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11758 mips_output_function_prologue (FILE *file
)
11760 const char *fnname
;
11762 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11763 floating-point arguments. */
11765 && TARGET_HARD_FLOAT_ABI
11766 && crtl
->args
.info
.fp_code
!= 0)
11767 mips16_build_function_stub ();
11769 /* Get the function name the same way that toplev.c does before calling
11770 assemble_start_function. This is needed so that the name used here
11771 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11772 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11773 mips_start_function_definition (fnname
, TARGET_MIPS16
);
11775 /* Output MIPS-specific frame information. */
11776 if (!flag_inhibit_size_directive
)
11778 const struct mips_frame_info
*frame
;
11780 frame
= &cfun
->machine
->frame
;
11782 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11784 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
11785 "# vars= " HOST_WIDE_INT_PRINT_DEC
11787 ", args= " HOST_WIDE_INT_PRINT_DEC
11788 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
11789 reg_names
[frame_pointer_needed
11790 ? HARD_FRAME_POINTER_REGNUM
11791 : STACK_POINTER_REGNUM
],
11792 (frame_pointer_needed
11793 ? frame
->total_size
- frame
->hard_frame_pointer_offset
11794 : frame
->total_size
),
11795 reg_names
[RETURN_ADDR_REGNUM
],
11797 frame
->num_gp
, frame
->num_fp
,
11799 frame
->cprestore_size
);
11801 /* .mask MASK, OFFSET. */
11802 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11803 frame
->mask
, frame
->gp_save_offset
);
11805 /* .fmask MASK, OFFSET. */
11806 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11807 frame
->fmask
, frame
->fp_save_offset
);
11810 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11811 Also emit the ".set noreorder; .set nomacro" sequence for functions
11813 if (mips_must_initialize_gp_p ()
11814 && mips_current_loadgp_style () == LOADGP_OLDABI
)
11818 /* This is a fixed-form sequence. The position of the
11819 first two instructions is important because of the
11820 way _gp_disp is defined. */
11821 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11822 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11823 output_asm_insn ("sll\t$2,16", 0);
11824 output_asm_insn ("addu\t$2,$3", 0);
11828 /* .cpload must be in a .set noreorder but not a
11829 .set nomacro block. */
11830 mips_push_asm_switch (&mips_noreorder
);
11831 output_asm_insn (".cpload\t%^", 0);
11832 if (!cfun
->machine
->all_noreorder_p
)
11833 mips_pop_asm_switch (&mips_noreorder
);
11835 mips_push_asm_switch (&mips_nomacro
);
11838 else if (cfun
->machine
->all_noreorder_p
)
11840 mips_push_asm_switch (&mips_noreorder
);
11841 mips_push_asm_switch (&mips_nomacro
);
11844 /* Tell the assembler which register we're using as the global
11845 pointer. This is needed for thunks, since they can use either
11846 explicit relocs or assembler macros. */
11847 mips_output_cplocal ();
11850 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11853 mips_output_function_epilogue (FILE *)
11855 const char *fnname
;
11857 /* Reinstate the normal $gp. */
11858 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
11859 mips_output_cplocal ();
11861 if (cfun
->machine
->all_noreorder_p
)
11863 mips_pop_asm_switch (&mips_nomacro
);
11864 mips_pop_asm_switch (&mips_noreorder
);
11867 /* Get the function name the same way that toplev.c does before calling
11868 assemble_start_function. This is needed so that the name used here
11869 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11870 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11871 mips_end_function_definition (fnname
);
11874 /* Emit an optimisation barrier for accesses to the current frame. */
11877 mips_frame_barrier (void)
11879 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
11883 /* The __gnu_local_gp symbol. */
11885 static GTY(()) rtx mips_gnu_local_gp
;
11887 /* If we're generating n32 or n64 abicalls, emit instructions
11888 to set up the global pointer. */
11891 mips_emit_loadgp (void)
11893 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
11895 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11896 switch (mips_current_loadgp_style ())
11898 case LOADGP_ABSOLUTE
:
11899 if (mips_gnu_local_gp
== NULL
)
11901 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
11902 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
11904 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
11905 (pic_reg
, mips_gnu_local_gp
)));
11908 case LOADGP_OLDABI
:
11909 /* Added by mips_output_function_prologue. */
11912 case LOADGP_NEWABI
:
11913 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
11914 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
11915 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11916 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
11917 (pic_reg
, offset
, incoming_address
)));
11921 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
11922 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
11923 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
11931 emit_insn (PMODE_INSN (gen_copygp_mips16
,
11932 (pic_offset_table_rtx
, pic_reg
)));
11934 /* Emit a blockage if there are implicit uses of the GP register.
11935 This includes profiled functions, because FUNCTION_PROFILE uses
11937 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
11938 emit_insn (gen_loadgp_blockage ());
11941 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11943 #if PROBE_INTERVAL > 32768
11944 #error Cannot use indexed addressing mode for stack probing
11947 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11948 inclusive. These are offsets from the current stack pointer. */
11951 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
11954 sorry ("-fstack-check=specific not implemented for MIPS16");
11956 /* See if we have a constant small number of probes to generate. If so,
11957 that's the easy case. */
11958 if (first
+ size
<= 32768)
11962 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11963 it exceeds SIZE. If only one probe is needed, this will not
11964 generate any code. Then probe at FIRST + SIZE. */
11965 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
11966 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11969 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11973 /* Otherwise, do the same as above, but in a loop. Note that we must be
11974 extra careful with variables wrapping around because we might be at
11975 the very top (or the very bottom) of the address space and we have
11976 to be able to handle this case properly; in particular, we use an
11977 equality test for the loop condition. */
11980 HOST_WIDE_INT rounded_size
;
11981 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11982 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11984 /* Sanity check for the addressing mode we're going to use. */
11985 gcc_assert (first
<= 32768);
11988 /* Step 1: round SIZE to the previous multiple of the interval. */
11990 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
11993 /* Step 2: compute initial and final value of the loop counter. */
11995 /* TEST_ADDR = SP + FIRST. */
11996 emit_insn (gen_rtx_SET (r3
, plus_constant (Pmode
, stack_pointer_rtx
,
11999 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
12000 if (rounded_size
> 32768)
12002 emit_move_insn (r12
, GEN_INT (rounded_size
));
12003 emit_insn (gen_rtx_SET (r12
, gen_rtx_MINUS (Pmode
, r3
, r12
)));
12006 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, r3
,
12010 /* Step 3: the loop
12014 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
12017 while (TEST_ADDR != LAST_ADDR)
12019 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
12020 until it is equal to ROUNDED_SIZE. */
12022 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
12025 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
12026 that SIZE is equal to ROUNDED_SIZE. */
12028 if (size
!= rounded_size
)
12029 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
12032 /* Make sure nothing is scheduled before we are done. */
12033 emit_insn (gen_blockage ());
12036 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
12037 absolute addresses. */
12040 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
12042 static int labelno
= 0;
12043 char loop_lab
[32], tmp
[64];
12046 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
12049 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
12051 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
12053 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
12054 if (TARGET_64BIT
&& TARGET_LONG64
)
12055 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
12057 output_asm_insn ("addiu\t%0,%0,%1", xops
);
12059 /* Probe at TEST_ADDR, test if TEST_ADDR == LAST_ADDR and branch. */
12061 strcpy (tmp
, "%(%<bne\t%0,%1,");
12062 output_asm_insn (strcat (tmp
, &loop_lab
[1]), xops
);
12064 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
12066 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
12071 /* Return true if X contains a kernel register. */
12074 mips_refers_to_kernel_reg_p (const_rtx x
)
12076 subrtx_iterator::array_type array
;
12077 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
12078 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
12083 /* Expand the "prologue" pattern. */
12086 mips_expand_prologue (void)
12088 const struct mips_frame_info
*frame
;
12089 HOST_WIDE_INT size
;
12090 unsigned int nargs
;
12092 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
12094 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
12095 or implicitly. If so, we can commit to using a global pointer
12096 straight away, otherwise we need to defer the decision. */
12097 if (mips_cfun_has_inflexible_gp_ref_p ()
12098 || mips_cfun_has_flexible_gp_ref_p ())
12100 cfun
->machine
->must_initialize_gp_p
= true;
12101 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
12104 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
12107 frame
= &cfun
->machine
->frame
;
12108 size
= frame
->total_size
;
12110 if (flag_stack_usage_info
)
12111 current_function_static_stack_size
= size
;
12113 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
12114 || flag_stack_clash_protection
)
12116 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
12118 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
12119 mips_emit_probe_stack_range (get_stack_check_protect (),
12120 size
- get_stack_check_protect ());
12123 mips_emit_probe_stack_range (get_stack_check_protect (), size
);
12126 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
12127 bytes beforehand; this is enough to cover the register save area
12128 without going out of range. */
12129 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
12130 || frame
->num_cop0_regs
> 0)
12132 HOST_WIDE_INT step1
;
12134 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
12135 if (GENERATE_MIPS16E_SAVE_RESTORE
)
12137 HOST_WIDE_INT offset
;
12138 unsigned int mask
, regno
;
12140 /* Try to merge argument stores into the save instruction. */
12141 nargs
= mips16e_collect_argument_saves ();
12143 /* Build the save instruction. */
12144 mask
= frame
->mask
;
12145 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
12147 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12148 mips_frame_barrier ();
12151 /* Check if we need to save other registers. */
12152 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
12153 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
12155 offset
-= UNITS_PER_WORD
;
12156 mips_save_restore_reg (word_mode
, regno
,
12157 offset
, mips_save_reg
);
12162 if (cfun
->machine
->interrupt_handler_p
)
12164 HOST_WIDE_INT offset
;
12167 /* If this interrupt is using a shadow register set, we need to
12168 get the stack pointer from the previous register set. */
12169 if (cfun
->machine
->use_shadow_register_set
== SHADOW_SET_YES
)
12170 emit_insn (PMODE_INSN (gen_mips_rdpgpr
, (stack_pointer_rtx
,
12171 stack_pointer_rtx
)));
12173 if (!cfun
->machine
->keep_interrupts_masked_p
)
12175 if (cfun
->machine
->int_mask
== INT_MASK_EIC
)
12176 /* Move from COP0 Cause to K0. */
12177 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
12178 gen_rtx_REG (SImode
, COP0_CAUSE_REG_NUM
)));
12180 /* Move from COP0 EPC to K1. */
12181 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
12182 gen_rtx_REG (SImode
,
12183 COP0_EPC_REG_NUM
)));
12185 /* Allocate the first part of the frame. */
12186 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
12188 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12189 mips_frame_barrier ();
12192 /* Start at the uppermost location for saving. */
12193 offset
= frame
->cop0_sp_offset
- size
;
12195 /* Push EPC into its stack slot. */
12196 mem
= gen_frame_mem (word_mode
,
12197 plus_constant (Pmode
, stack_pointer_rtx
,
12199 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
12200 offset
-= UNITS_PER_WORD
;
12202 /* Move from COP0 Status to K1. */
12203 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
12204 gen_rtx_REG (SImode
,
12205 COP0_STATUS_REG_NUM
)));
12207 /* Right justify the RIPL in k0. */
12208 if (!cfun
->machine
->keep_interrupts_masked_p
12209 && cfun
->machine
->int_mask
== INT_MASK_EIC
)
12210 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
12211 gen_rtx_REG (SImode
, K0_REG_NUM
),
12212 GEN_INT (CAUSE_IPL
)));
12214 /* Push Status into its stack slot. */
12215 mem
= gen_frame_mem (word_mode
,
12216 plus_constant (Pmode
, stack_pointer_rtx
,
12218 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
12219 offset
-= UNITS_PER_WORD
;
12221 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
12222 if (!cfun
->machine
->keep_interrupts_masked_p
12223 && cfun
->machine
->int_mask
== INT_MASK_EIC
)
12224 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12227 gen_rtx_REG (SImode
, K0_REG_NUM
)));
12229 /* Clear all interrupt mask bits up to and including the
12230 handler's interrupt line. */
12231 if (!cfun
->machine
->keep_interrupts_masked_p
12232 && cfun
->machine
->int_mask
!= INT_MASK_EIC
)
12233 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12234 GEN_INT (cfun
->machine
->int_mask
+ 1),
12236 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12238 if (!cfun
->machine
->keep_interrupts_masked_p
)
12239 /* Enable interrupts by clearing the KSU ERL and EXL bits.
12240 IE is already the correct value, so we don't have to do
12241 anything explicit. */
12242 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12245 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12247 /* Disable interrupts by clearing the KSU, ERL, EXL,
12249 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12252 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12254 if (TARGET_HARD_FLOAT
)
12255 /* Disable COP1 for hard-float. This will lead to an exception
12256 if floating-point code is executed in an ISR. */
12257 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12260 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12266 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
12269 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12270 mips_frame_barrier ();
12274 mips_for_each_saved_acc (size
, mips_save_reg
);
12275 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
12279 /* Allocate the rest of the frame. */
12282 if (SMALL_OPERAND (-size
))
12283 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
12285 GEN_INT (-size
)))) = 1;
12288 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
12291 /* There are no instructions to add or subtract registers
12292 from the stack pointer, so use the frame pointer as a
12293 temporary. We should always be using a frame pointer
12294 in this case anyway. */
12295 gcc_assert (frame_pointer_needed
);
12296 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12297 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
12298 hard_frame_pointer_rtx
,
12299 MIPS_PROLOGUE_TEMP (Pmode
)));
12300 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
12303 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
12305 MIPS_PROLOGUE_TEMP (Pmode
)));
12307 /* Describe the combined effect of the previous instructions. */
12308 mips_set_frame_expr
12309 (gen_rtx_SET (stack_pointer_rtx
,
12310 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
12312 mips_frame_barrier ();
12315 /* Set up the frame pointer, if we're using one. */
12316 if (frame_pointer_needed
)
12318 HOST_WIDE_INT offset
;
12320 offset
= frame
->hard_frame_pointer_offset
;
12323 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12324 RTX_FRAME_RELATED_P (insn
) = 1;
12326 else if (SMALL_OPERAND (offset
))
12328 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
12329 stack_pointer_rtx
, GEN_INT (offset
));
12330 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12334 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
12335 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12336 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
12337 hard_frame_pointer_rtx
,
12338 MIPS_PROLOGUE_TEMP (Pmode
)));
12339 mips_set_frame_expr
12340 (gen_rtx_SET (hard_frame_pointer_rtx
,
12341 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
12345 mips_emit_loadgp ();
12347 /* Initialize the $gp save slot. */
12348 if (mips_cfun_has_cprestore_slot_p ())
12350 rtx base
, mem
, gp
, temp
;
12351 HOST_WIDE_INT offset
;
12353 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
12354 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
12355 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
12356 temp
= (SMALL_OPERAND (offset
)
12357 ? gen_rtx_SCRATCH (Pmode
)
12358 : MIPS_PROLOGUE_TEMP (Pmode
));
12359 emit_insn (PMODE_INSN (gen_potential_cprestore
,
12360 (mem
, GEN_INT (offset
), gp
, temp
)));
12362 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12363 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
12364 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
12367 /* We need to search back to the last use of K0 or K1. */
12368 if (cfun
->machine
->interrupt_handler_p
)
12371 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
12373 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12375 /* Emit a move from K1 to COP0 Status after insn. */
12376 gcc_assert (insn
!= NULL_RTX
);
12377 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
12378 gen_rtx_REG (SImode
, K1_REG_NUM
)),
12382 /* If we are profiling, make sure no instructions are scheduled before
12383 the call to mcount. */
12385 emit_insn (gen_blockage ());
12388 /* Attach all pending register saves to the previous instruction.
12389 Return that instruction. */
12392 mips_epilogue_emit_cfa_restores (void)
12396 insn
= get_last_insn ();
12397 if (mips_epilogue
.cfa_restores
)
12399 gcc_assert (insn
&& !REG_NOTES (insn
));
12400 RTX_FRAME_RELATED_P (insn
) = 1;
12401 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
12402 mips_epilogue
.cfa_restores
= 0;
12407 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
12408 now at REG + OFFSET. */
12411 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
12415 insn
= mips_epilogue_emit_cfa_restores ();
12416 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
12418 RTX_FRAME_RELATED_P (insn
) = 1;
12419 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
12420 plus_constant (Pmode
, reg
, offset
),
12422 mips_epilogue
.cfa_reg
= reg
;
12423 mips_epilogue
.cfa_offset
= offset
;
12427 /* Emit instructions to restore register REG from slot MEM. Also update
12428 the cfa_restores list. */
12431 mips_restore_reg (rtx reg
, rtx mem
)
12433 /* There's no MIPS16 instruction to load $31 directly. Load into
12434 $7 instead and adjust the return insn appropriately. */
12435 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
12436 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
12437 else if (GET_MODE (reg
) == DFmode
12438 && (!TARGET_FLOAT64
12439 || mips_abi
== ABI_32
))
12441 mips_add_cfa_restore (mips_subword (reg
, true));
12442 mips_add_cfa_restore (mips_subword (reg
, false));
12445 mips_add_cfa_restore (reg
);
12447 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
12448 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
12449 /* The CFA is currently defined in terms of the register whose
12450 value we have just restored. Redefine the CFA in terms of
12451 the stack pointer. */
12452 mips_epilogue_set_cfa (stack_pointer_rtx
,
12453 mips_epilogue
.cfa_restore_sp_offset
);
12456 /* Emit code to set the stack pointer to BASE + OFFSET, given that
12457 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
12458 BASE, if not the stack pointer, is available as a temporary. */
12461 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
12463 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
12466 mips_frame_barrier ();
12467 if (offset
== const0_rtx
)
12469 emit_move_insn (stack_pointer_rtx
, base
);
12470 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
12472 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
12474 emit_insn (gen_add3_insn (base
, base
, offset
));
12475 mips_epilogue_set_cfa (base
, new_frame_size
);
12476 emit_move_insn (stack_pointer_rtx
, base
);
12480 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
12481 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
12485 /* Emit any instructions needed before a return. */
12488 mips_expand_before_return (void)
12490 /* When using a call-clobbered gp, we start out with unified call
12491 insns that include instructions to restore the gp. We then split
12492 these unified calls after reload. These split calls explicitly
12493 clobber gp, so there is no need to define
12494 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
12496 For consistency, we should also insert an explicit clobber of $28
12497 before return insns, so that the post-reload optimizers know that
12498 the register is not live on exit. */
12499 if (TARGET_CALL_CLOBBERED_GP
)
12500 emit_clobber (pic_offset_table_rtx
);
12503 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
12507 mips_expand_epilogue (bool sibcall_p
)
12509 const struct mips_frame_info
*frame
;
12510 HOST_WIDE_INT step1
, step2
;
12513 bool use_jraddiusp_p
= false;
12515 if (!sibcall_p
&& mips_can_use_return_insn ())
12517 emit_jump_insn (gen_return ());
12521 /* In MIPS16 mode, if the return value should go into a floating-point
12522 register, we need to call a helper routine to copy it over. */
12523 if (mips16_cfun_returns_in_fpr_p ())
12524 mips16_copy_fpr_return_value ();
12526 /* Split the frame into two. STEP1 is the amount of stack we should
12527 deallocate before restoring the registers. STEP2 is the amount we
12528 should deallocate afterwards.
12530 Start off by assuming that no registers need to be restored. */
12531 frame
= &cfun
->machine
->frame
;
12532 step1
= frame
->total_size
;
12535 /* Work out which register holds the frame address. */
12536 if (!frame_pointer_needed
)
12537 base
= stack_pointer_rtx
;
12540 base
= hard_frame_pointer_rtx
;
12541 step1
-= frame
->hard_frame_pointer_offset
;
12543 mips_epilogue
.cfa_reg
= base
;
12544 mips_epilogue
.cfa_offset
= step1
;
12545 mips_epilogue
.cfa_restores
= NULL_RTX
;
12547 /* If we need to restore registers, deallocate as much stack as
12548 possible in the second step without going out of range. */
12549 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
12550 || frame
->num_cop0_regs
> 0)
12552 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
12556 /* Get an rtx for STEP1 that we can add to BASE. */
12557 adjust
= GEN_INT (step1
);
12558 if (!SMALL_OPERAND (step1
))
12560 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
12561 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
12563 mips_deallocate_stack (base
, adjust
, step2
);
12565 /* If we're using addressing macros, $gp is implicitly used by all
12566 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
12568 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
12569 emit_insn (gen_blockage ());
12571 mips_epilogue
.cfa_restore_sp_offset
= step2
;
12572 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
12574 unsigned int regno
, mask
;
12575 HOST_WIDE_INT offset
;
12578 /* Generate the restore instruction. */
12579 mask
= frame
->mask
;
12580 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
12582 /* Restore any other registers manually. */
12583 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
12584 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
12586 offset
-= UNITS_PER_WORD
;
12587 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
12590 /* Restore the remaining registers and deallocate the final bit
12592 mips_frame_barrier ();
12593 emit_insn (restore
);
12594 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
12598 /* Restore the registers. */
12599 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
12600 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
12603 if (cfun
->machine
->interrupt_handler_p
)
12605 HOST_WIDE_INT offset
;
12608 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
12610 /* Restore the original EPC. */
12611 mem
= gen_frame_mem (word_mode
,
12612 plus_constant (Pmode
, stack_pointer_rtx
,
12614 mips_emit_move (gen_rtx_REG (word_mode
, K1_REG_NUM
), mem
);
12615 offset
-= UNITS_PER_WORD
;
12617 /* Move to COP0 EPC. */
12618 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
12619 gen_rtx_REG (SImode
, K1_REG_NUM
)));
12621 /* Restore the original Status. */
12622 mem
= gen_frame_mem (word_mode
,
12623 plus_constant (Pmode
, stack_pointer_rtx
,
12625 mips_emit_move (gen_rtx_REG (word_mode
, K1_REG_NUM
), mem
);
12626 offset
-= UNITS_PER_WORD
;
12628 /* If we don't use shadow register set, we need to update SP. */
12629 if (cfun
->machine
->use_shadow_register_set
== SHADOW_SET_NO
)
12630 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
12632 /* The choice of position is somewhat arbitrary in this case. */
12633 mips_epilogue_emit_cfa_restores ();
12635 /* Move to COP0 Status. */
12636 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
12637 gen_rtx_REG (SImode
, K1_REG_NUM
)));
12639 else if (TARGET_MICROMIPS
12640 && !crtl
->calls_eh_return
12643 && mips_unsigned_immediate_p (step2
, 5, 2))
12644 use_jraddiusp_p
= true;
12646 /* Deallocate the final bit of the frame. */
12647 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
12650 if (cfun
->machine
->use_frame_header_for_callee_saved_regs
)
12651 mips_epilogue_emit_cfa_restores ();
12652 else if (!use_jraddiusp_p
)
12653 gcc_assert (!mips_epilogue
.cfa_restores
);
12655 /* Add in the __builtin_eh_return stack adjustment. We need to
12656 use a temporary in MIPS16 code. */
12657 if (crtl
->calls_eh_return
)
12661 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
12662 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
12663 MIPS_EPILOGUE_TEMP (Pmode
),
12664 EH_RETURN_STACKADJ_RTX
));
12665 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
12668 emit_insn (gen_add3_insn (stack_pointer_rtx
,
12670 EH_RETURN_STACKADJ_RTX
));
12675 mips_expand_before_return ();
12676 if (cfun
->machine
->interrupt_handler_p
)
12678 /* Interrupt handlers generate eret or deret. */
12679 if (cfun
->machine
->use_debug_exception_return_p
)
12680 emit_jump_insn (gen_mips_deret ());
12682 emit_jump_insn (gen_mips_eret ());
12688 /* When generating MIPS16 code, the normal
12689 mips_for_each_saved_gpr_and_fpr path will restore the return
12690 address into $7 rather than $31. */
12692 && !GENERATE_MIPS16E_SAVE_RESTORE
12693 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
12695 /* simple_returns cannot rely on values that are only available
12696 on paths through the epilogue (because return paths that do
12697 not pass through the epilogue may nevertheless reuse a
12698 simple_return that occurs at the end of the epilogue).
12699 Use a normal return here instead. */
12700 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
12701 pat
= gen_return_internal (reg
);
12703 else if (use_jraddiusp_p
)
12704 pat
= gen_jraddiusp (GEN_INT (step2
));
12707 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
12708 pat
= gen_simple_return_internal (reg
);
12710 emit_jump_insn (pat
);
12711 if (use_jraddiusp_p
)
12712 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
12716 /* Search from the beginning to the first use of K0 or K1. */
12717 if (cfun
->machine
->interrupt_handler_p
12718 && !cfun
->machine
->keep_interrupts_masked_p
)
12720 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12722 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12724 gcc_assert (insn
!= NULL_RTX
);
12725 /* Insert disable interrupts before the first use of K0 or K1. */
12726 emit_insn_before (gen_mips_di (), insn
);
12727 emit_insn_before (gen_mips_ehb (), insn
);
12731 /* Return nonzero if this function is known to have a null epilogue.
12732 This allows the optimizer to omit jumps to jumps if no stack
12736 mips_can_use_return_insn (void)
12738 /* Interrupt handlers need to go through the epilogue. */
12739 if (cfun
->machine
->interrupt_handler_p
)
12742 if (!reload_completed
)
12748 /* In MIPS16 mode, a function that returns a floating-point value
12749 needs to arrange to copy the return value into the floating-point
12751 if (mips16_cfun_returns_in_fpr_p ())
12754 return (cfun
->machine
->frame
.total_size
== 0
12755 && !cfun
->machine
->use_frame_header_for_callee_saved_regs
);
12758 /* Return true if register REGNO can store a value of mode MODE.
12759 The result of this function is cached in mips_hard_regno_mode_ok. */
12762 mips_hard_regno_mode_ok_uncached (unsigned int regno
, machine_mode mode
)
12765 enum mode_class mclass
;
12767 if (mode
== CCV2mode
)
12768 return (ISA_HAS_8CC
12769 && ST_REG_P (regno
)
12770 && (regno
- ST_REG_FIRST
) % 2 == 0);
12772 if (mode
== CCV4mode
)
12773 return (ISA_HAS_8CC
12774 && ST_REG_P (regno
)
12775 && (regno
- ST_REG_FIRST
) % 4 == 0);
12777 if (mode
== CCmode
)
12778 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
12780 size
= GET_MODE_SIZE (mode
);
12781 mclass
= GET_MODE_CLASS (mode
);
12783 if (GP_REG_P (regno
) && mode
!= CCFmode
&& !MSA_SUPPORTED_MODE_P (mode
))
12784 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
12786 /* For MSA, allow TImode and 128-bit vector modes in all FPR. */
12787 if (FP_REG_P (regno
) && MSA_SUPPORTED_MODE_P (mode
))
12790 if (FP_REG_P (regno
)
12791 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
12792 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
12794 /* Deny use of odd-numbered registers for 32-bit data for
12795 the o32 FP64A ABI. */
12796 if (TARGET_O32_FP64A_ABI
&& size
<= 4 && (regno
& 1) != 0)
12799 /* The FPXX ABI requires double-precision values to be placed in
12800 even-numbered registers. Disallow odd-numbered registers with
12801 CCFmode because CCFmode double-precision compares will write a
12802 64-bit value to a register. */
12803 if (mode
== CCFmode
)
12804 return !(TARGET_FLOATXX
&& (regno
& 1) != 0);
12806 /* Allow 64-bit vector modes for Loongson MultiMedia extensions
12807 Instructions (MMI). */
12808 if (TARGET_LOONGSON_MMI
12809 && (mode
== V2SImode
12810 || mode
== V4HImode
12811 || mode
== V8QImode
12812 || mode
== DImode
))
12815 if (mclass
== MODE_FLOAT
12816 || mclass
== MODE_COMPLEX_FLOAT
12817 || mclass
== MODE_VECTOR_FLOAT
)
12818 return size
<= UNITS_PER_FPVALUE
;
12820 /* Allow integer modes that fit into a single register. We need
12821 to put integers into FPRs when using instructions like CVT
12822 and TRUNC. There's no point allowing sizes smaller than a word,
12823 because the FPU has no appropriate load/store instructions. */
12824 if (mclass
== MODE_INT
)
12825 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
12828 /* Don't allow vector modes in accumulators. */
12829 if (ACC_REG_P (regno
)
12830 && !VECTOR_MODE_P (mode
)
12831 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
12833 if (MD_REG_P (regno
))
12835 /* After a multiplication or division, clobbering HI makes
12836 the value of LO unpredictable, and vice versa. This means
12837 that, for all interesting cases, HI and LO are effectively
12840 We model this by requiring that any value that uses HI
12842 if (size
<= UNITS_PER_WORD
* 2)
12843 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
12847 /* DSP accumulators do not have the same restrictions as
12848 HI and LO, so we can treat them as normal doubleword
12850 if (size
<= UNITS_PER_WORD
)
12853 if (size
<= UNITS_PER_WORD
* 2
12854 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
12859 if (ALL_COP_REG_P (regno
))
12860 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
12862 if (regno
== GOT_VERSION_REGNUM
)
12863 return mode
== SImode
;
12868 /* Implement TARGET_HARD_REGNO_MODE_OK. */
12871 mips_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
12873 return mips_hard_regno_mode_ok_p
[mode
][regno
];
12876 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
12879 mips_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
12880 unsigned int new_reg
)
12882 /* Interrupt functions can only use registers that have already been
12883 saved by the prologue, even if they would normally be call-clobbered. */
12884 if (cfun
->machine
->interrupt_handler_p
&& !df_regs_ever_live_p (new_reg
))
12890 /* Return nonzero if register REGNO can be used as a scratch register
12894 mips_hard_regno_scratch_ok (unsigned int regno
)
12896 /* See mips_hard_regno_rename_ok. */
12897 if (cfun
->machine
->interrupt_handler_p
&& !df_regs_ever_live_p (regno
))
12903 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. Odd-numbered
12904 single-precision registers are not considered callee-saved for o32
12905 FPXX as they will be clobbered when run on an FR=1 FPU. MSA vector
12906 registers with MODE > 64 bits are part clobbered too. */
12909 mips_hard_regno_call_part_clobbered (unsigned int regno
, machine_mode mode
)
12912 && hard_regno_nregs (regno
, mode
) == 1
12913 && FP_REG_P (regno
)
12914 && (regno
& 1) != 0)
12917 if (ISA_HAS_MSA
&& FP_REG_P (regno
) && GET_MODE_SIZE (mode
) > 8)
12923 /* Implement TARGET_HARD_REGNO_NREGS. */
12925 static unsigned int
12926 mips_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
12928 if (ST_REG_P (regno
))
12929 /* The size of FP status registers is always 4, because they only hold
12930 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12931 return (GET_MODE_SIZE (mode
) + 3) / 4;
12933 if (FP_REG_P (regno
))
12935 if (MSA_SUPPORTED_MODE_P (mode
))
12938 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
12941 /* All other registers are word-sized. */
12942 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
12945 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12946 in mips_hard_regno_nregs. */
12949 mips_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
12955 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
12956 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
12958 if (mips_hard_regno_mode_ok (ST_REG_FIRST
, mode
))
12959 size
= MIN (size
, 4);
12961 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
12963 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
12965 if (mips_hard_regno_mode_ok (FP_REG_FIRST
, mode
))
12967 if (MSA_SUPPORTED_MODE_P (mode
))
12968 size
= MIN (size
, UNITS_PER_MSA_REG
);
12970 size
= MIN (size
, UNITS_PER_FPREG
);
12973 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
12975 if (!hard_reg_set_empty_p (left
))
12976 size
= MIN (size
, UNITS_PER_WORD
);
12977 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
12980 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
12983 mips_can_change_mode_class (machine_mode from
,
12984 machine_mode to
, reg_class_t rclass
)
12986 /* Allow conversions between different Loongson integer vectors,
12987 and between those vectors and DImode. */
12988 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
12989 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
12992 /* Allow conversions between different MSA vector modes. */
12993 if (MSA_SUPPORTED_MODE_P (from
) && MSA_SUPPORTED_MODE_P (to
))
12996 /* Otherwise, there are several problems with changing the modes of
12997 values in floating-point registers:
12999 - When a multi-word value is stored in paired floating-point
13000 registers, the first register always holds the low word. We
13001 therefore can't allow FPRs to change between single-word and
13002 multi-word modes on big-endian targets.
13004 - GCC assumes that each word of a multiword register can be
13005 accessed individually using SUBREGs. This is not true for
13006 floating-point registers if they are bigger than a word.
13008 - Loading a 32-bit value into a 64-bit floating-point register
13009 will not sign-extend the value, despite what LOAD_EXTEND_OP
13010 says. We can't allow FPRs to change from SImode to a wider
13011 mode on 64-bit targets.
13013 - If the FPU has already interpreted a value in one format, we
13014 must not ask it to treat the value as having a different
13017 We therefore disallow all mode changes involving FPRs. */
13019 return !reg_classes_intersect_p (FP_REGS
, rclass
);
13022 /* Implement target hook small_register_classes_for_mode_p. */
13025 mips_small_register_classes_for_mode_p (machine_mode mode
13028 return TARGET_MIPS16
;
13031 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction,
13032 or use the MSA's move.v instruction. */
13035 mips_mode_ok_for_mov_fmt_p (machine_mode mode
)
13041 return TARGET_HARD_FLOAT
;
13044 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
13047 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
13050 return MSA_SUPPORTED_MODE_P (mode
);
13054 /* Implement TARGET_MODES_TIEABLE_P. */
13057 mips_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13059 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
13060 prefer to put one of them in FPRs. */
13061 return (mode1
== mode2
13062 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
13063 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
13066 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
13069 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
13071 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
13074 if (reg_class_subset_p (FP_REGS
, rclass
)
13075 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
13078 if (reg_class_subset_p (GR_REGS
, rclass
))
13081 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
13087 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
13088 Return a "canonical" class to represent it in later calculations. */
13091 mips_canonicalize_move_class (reg_class_t rclass
)
13093 /* All moves involving accumulator registers have the same cost. */
13094 if (reg_class_subset_p (rclass
, ACC_REGS
))
13097 /* Likewise promote subclasses of general registers to the most
13098 interesting containing class. */
13099 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
13101 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
13102 rclass
= GENERAL_REGS
;
13107 /* Return the cost of moving a value from a register of class FROM to a GPR.
13108 Return 0 for classes that are unions of other classes handled by this
13112 mips_move_to_gpr_cost (reg_class_t from
)
13118 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13122 /* MFLO and MFHI. */
13132 /* This choice of value is historical. */
13140 /* Return the cost of moving a value from a GPR to a register of class TO.
13141 Return 0 for classes that are unions of other classes handled by this
13145 mips_move_from_gpr_cost (reg_class_t to
)
13151 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13155 /* MTLO and MTHI. */
13165 /* This choice of value is historical. */
13173 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
13174 maximum of the move costs for subclasses; regclass will work out
13175 the maximum for us. */
13178 mips_register_move_cost (machine_mode mode
,
13179 reg_class_t from
, reg_class_t to
)
13184 from
= mips_canonicalize_move_class (from
);
13185 to
= mips_canonicalize_move_class (to
);
13187 /* Handle moves that can be done without using general-purpose registers. */
13188 if (from
== FP_REGS
)
13190 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
13195 /* Handle cases in which only one class deviates from the ideal. */
13196 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
13198 return mips_move_from_gpr_cost (to
);
13200 return mips_move_to_gpr_cost (from
);
13202 /* Handles cases that require a GPR temporary. */
13203 cost1
= mips_move_to_gpr_cost (from
);
13206 cost2
= mips_move_from_gpr_cost (to
);
13208 return cost1
+ cost2
;
13214 /* Implement TARGET_REGISTER_PRIORITY. */
13217 mips_register_priority (int hard_regno
)
13219 /* Treat MIPS16 registers with higher priority than other regs. */
13221 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
13226 /* Implement TARGET_MEMORY_MOVE_COST. */
13229 mips_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
13231 return (mips_cost
->memory_latency
13232 + memory_move_secondary_cost (mode
, rclass
, in
));
13235 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13237 When targeting the o32 FPXX ABI, all moves with a length of doubleword
13238 or greater must be performed by FR-mode-aware instructions.
13239 This can be achieved using MFHC1/MTHC1 when these instructions are
13240 available but otherwise moves must go via memory.
13241 For the o32 FP64A ABI, all odd-numbered moves with a length of
13242 doubleword or greater are required to use memory. Using MTC1/MFC1
13243 to access the lower-half of these registers would require a forbidden
13244 single-precision access. We require all double-word moves to use
13245 memory because adding even and odd floating-point registers classes
13246 would have a significant impact on the backend. */
13249 mips_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13250 reg_class_t class2
)
13252 /* Ignore spilled pseudos. */
13253 if (lra_in_progress
&& (class1
== NO_REGS
|| class2
== NO_REGS
))
13256 if (((class1
== FP_REGS
) != (class2
== FP_REGS
))
13257 && ((TARGET_FLOATXX
&& !ISA_HAS_MXHC1
)
13258 || TARGET_O32_FP64A_ABI
)
13259 && GET_MODE_SIZE (mode
) >= 8)
13265 /* Return the register class required for a secondary register when
13266 copying between one of the registers in RCLASS and value X, which
13267 has mode MODE. X is the source of the move if IN_P, otherwise it
13268 is the destination. Return NO_REGS if no secondary register is
13272 mips_secondary_reload_class (enum reg_class rclass
,
13273 machine_mode mode
, rtx x
, bool)
13277 /* If X is a constant that cannot be loaded into $25, it must be loaded
13278 into some other GPR. No other register class allows a direct move. */
13279 if (mips_dangerous_for_la25_p (x
))
13280 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
13282 regno
= true_regnum (x
);
13285 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
13286 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
13292 /* Copying from accumulator registers to anywhere other than a general
13293 register requires a temporary general register. */
13294 if (reg_class_subset_p (rclass
, ACC_REGS
))
13295 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
13296 if (ACC_REG_P (regno
))
13297 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
13299 if (reg_class_subset_p (rclass
, FP_REGS
))
13303 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
13304 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
13305 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
13308 if (MEM_P (x
) && MSA_SUPPORTED_MODE_P (mode
))
13309 /* In this case we can use MSA LD.* and ST.*. */
13312 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
13313 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
13316 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
13317 /* We can force the constant to memory and use lwc1
13318 and ldc1. As above, we will use pairs of lwc1s if
13319 ldc1 is not supported. */
13322 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
13323 /* In this case we can use mov.fmt. */
13326 /* Otherwise, we need to reload through an integer register. */
13329 if (FP_REG_P (regno
))
13330 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
13335 /* Implement TARGET_MODE_REP_EXTENDED. */
13338 mips_mode_rep_extended (scalar_int_mode mode
, scalar_int_mode mode_rep
)
13340 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
13341 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
13342 return SIGN_EXTEND
;
13347 /* Implement TARGET_VALID_POINTER_MODE. */
13350 mips_valid_pointer_mode (scalar_int_mode mode
)
13352 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
13355 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
13358 mips_vector_mode_supported_p (machine_mode mode
)
13363 return TARGET_PAIRED_SINGLE_FLOAT
;
13378 return TARGET_LOONGSON_MMI
;
13381 return MSA_SUPPORTED_MODE_P (mode
);
13385 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
13388 mips_scalar_mode_supported_p (scalar_mode mode
)
13390 if (ALL_FIXED_POINT_MODE_P (mode
)
13391 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
13394 return default_scalar_mode_supported_p (mode
);
13397 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
13399 static machine_mode
13400 mips_preferred_simd_mode (scalar_mode mode
)
13402 if (TARGET_PAIRED_SINGLE_FLOAT
13432 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */
13435 mips_autovectorize_vector_sizes (vector_sizes
*sizes
)
13438 sizes
->safe_push (16);
13441 /* Implement TARGET_INIT_LIBFUNCS. */
13444 mips_init_libfuncs (void)
13446 if (TARGET_FIX_VR4120
)
13448 /* Register the special divsi3 and modsi3 functions needed to work
13449 around VR4120 division errata. */
13450 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
13451 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
13454 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
13456 /* Register the MIPS16 -mhard-float stubs. */
13457 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
13458 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
13459 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
13460 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
13462 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
13463 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
13464 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
13465 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
13466 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
13467 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
13468 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
13470 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
13471 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
13472 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
13474 if (TARGET_DOUBLE_FLOAT
)
13476 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
13477 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
13478 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
13479 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
13481 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
13482 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
13483 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
13484 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
13485 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
13486 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
13487 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
13489 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
13490 "__mips16_extendsfdf2");
13491 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
13492 "__mips16_truncdfsf2");
13493 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
13494 "__mips16_fix_truncdfsi");
13495 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
13496 "__mips16_floatsidf");
13497 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
13498 "__mips16_floatunsidf");
13502 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
13503 on an external non-MIPS16 routine to implement __sync_synchronize.
13504 Similarly for the rest of the ll/sc libfuncs. */
13507 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
13508 init_sync_libfuncs (UNITS_PER_WORD
);
13512 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
13515 mips_process_load_label (rtx target
)
13517 rtx base
, gp
, intop
;
13518 HOST_WIDE_INT offset
;
13520 mips_multi_start ();
13524 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
13525 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
13529 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
13530 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
13534 gp
= pic_offset_table_rtx
;
13535 if (mips_cfun_has_cprestore_slot_p ())
13537 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
13538 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
13539 if (!SMALL_OPERAND (offset
))
13541 intop
= GEN_INT (CONST_HIGH_PART (offset
));
13542 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
13543 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
13546 offset
= CONST_LOW_PART (offset
);
13548 intop
= GEN_INT (offset
);
13549 if (ISA_HAS_LOAD_DELAY
)
13550 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
13552 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
13554 if (ISA_HAS_LOAD_DELAY
)
13555 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
13557 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
13558 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
13563 /* Return the number of instructions needed to load a label into $AT. */
13565 static unsigned int
13566 mips_load_label_num_insns (void)
13568 if (cfun
->machine
->load_label_num_insns
== 0)
13570 mips_process_load_label (pc_rtx
);
13571 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
13573 return cfun
->machine
->load_label_num_insns
;
13576 /* Emit an asm sequence to start a noat block and load the address
13577 of a label into $1. */
13580 mips_output_load_label (rtx target
)
13582 mips_push_asm_switch (&mips_noat
);
13583 if (TARGET_EXPLICIT_RELOCS
)
13585 mips_process_load_label (target
);
13586 mips_multi_write ();
13590 if (Pmode
== DImode
)
13591 output_asm_insn ("dla\t%@,%0", &target
);
13593 output_asm_insn ("la\t%@,%0", &target
);
13597 /* Return the length of INSN. LENGTH is the initial length computed by
13598 attributes in the machine-description file. */
13601 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
13603 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
13604 of a PIC long-branch sequence. Substitute the correct value. */
13605 if (length
== MAX_PIC_BRANCH_LENGTH
13607 && INSN_CODE (insn
) >= 0
13608 && get_attr_type (insn
) == TYPE_BRANCH
)
13610 /* Add the branch-over instruction and its delay slot, if this
13611 is a conditional branch. */
13612 length
= simplejump_p (insn
) ? 0 : 8;
13614 /* Add the size of a load into $AT. */
13615 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
13617 /* Add the length of an indirect jump, ignoring the delay slot. */
13618 length
+= TARGET_COMPRESSION
? 2 : 4;
13621 /* A unconditional jump has an unfilled delay slot if it is not part
13622 of a sequence. A conditional jump normally has a delay slot, but
13623 does not on MIPS16. */
13624 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
13625 length
+= TARGET_MIPS16
? 2 : 4;
13627 /* See how many nops might be needed to avoid hardware hazards. */
13628 if (!cfun
->machine
->ignore_hazard_length_p
13630 && INSN_CODE (insn
) >= 0)
13631 switch (get_attr_hazard (insn
))
13637 case HAZARD_FORBIDDEN_SLOT
:
13638 length
+= NOP_INSN_LENGTH
;
13642 length
+= NOP_INSN_LENGTH
* 2;
13649 /* Return the asm template for a call. OPERANDS are the operands, TARGET_OPNO
13650 is the operand number of the target. SIZE_OPNO is the operand number of
13651 the argument size operand that can optionally hold the call attributes. If
13652 SIZE_OPNO is not -1 and the call is indirect, use the function symbol from
13653 the call attributes to attach a R_MIPS_JALR relocation to the call. LINK_P
13654 indicates whether the jump is a call and needs to set the link register.
13656 When generating GOT code without explicit relocation operators, all calls
13657 should use assembly macros. Otherwise, all indirect calls should use "jr"
13658 or "jalr"; we will arrange to restore $gp afterwards if necessary. Finally,
13659 we can only generate direct calls for -mabicalls by temporarily switching
13662 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
13663 instruction is in the delay slot of jal(r).
13665 Where compact branches are available, we try to use them if the delay slot
13666 has a NOP (or equivalently delay slots were not enabled for the instruction
13670 mips_output_jump (rtx
*operands
, int target_opno
, int size_opno
, bool link_p
)
13672 static char buffer
[300];
13674 bool reg_p
= REG_P (operands
[target_opno
]);
13676 const char *and_link
= link_p
? "al" : "";
13677 const char *reg
= reg_p
? "r" : "";
13678 const char *compact
= "";
13679 const char *nop
= "%/";
13680 const char *short_delay
= link_p
? "%!" : "";
13681 const char *insn_name
= TARGET_CB_NEVER
|| reg_p
? "j" : "b";
13683 /* Compact branches can only be described when the ISA has support for them
13684 as both the compact formatter '%:' and the delay slot NOP formatter '%/'
13685 work as a mutually exclusive pair. I.e. a NOP is never required if a
13686 compact form is available. */
13687 if (!final_sequence
13688 && (TARGET_CB_MAYBE
13689 || (ISA_HAS_JRC
&& !link_p
&& reg_p
)))
13695 if (TARGET_USE_GOT
&& !TARGET_EXPLICIT_RELOCS
)
13696 sprintf (s
, "%%*%s%s\t%%%d%%/", insn_name
, and_link
, target_opno
);
13699 if (!reg_p
&& TARGET_ABICALLS_PIC2
)
13700 s
+= sprintf (s
, ".option\tpic0\n\t");
13702 if (reg_p
&& mips_get_pic_call_symbol (operands
, size_opno
))
13703 s
+= sprintf (s
, "%%*.reloc\t1f,%s,%%%d\n1:\t",
13704 TARGET_MICROMIPS
? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
13707 s
+= sprintf (s
, "%%*");
13709 s
+= sprintf (s
, "%s%s%s%s%s\t%%%d%s",
13710 insn_name
, and_link
, reg
, compact
, short_delay
,
13713 if (!reg_p
&& TARGET_ABICALLS_PIC2
)
13714 s
+= sprintf (s
, "\n\t.option\tpic2");
13719 /* Return the assembly code for INSN, which has the operands given by
13720 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
13721 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
13722 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
13723 version of BRANCH_IF_TRUE. */
13726 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
13727 const char *branch_if_true
,
13728 const char *branch_if_false
)
13730 unsigned int length
;
13733 gcc_assert (LABEL_P (operands
[0]));
13735 length
= get_attr_length (insn
);
13738 /* Just a simple conditional branch. */
13739 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
13740 return branch_if_true
;
13743 /* Generate a reversed branch around a direct jump. This fallback does
13744 not use branch-likely instructions. */
13745 mips_branch_likely
= false;
13746 rtx_code_label
*not_taken
= gen_label_rtx ();
13747 taken
= operands
[0];
13749 /* Generate the reversed branch to NOT_TAKEN. */
13750 operands
[0] = not_taken
;
13751 output_asm_insn (branch_if_false
, operands
);
13753 /* If INSN has a delay slot, we must provide delay slots for both the
13754 branch to NOT_TAKEN and the conditional jump. We must also ensure
13755 that INSN's delay slot is executed in the appropriate cases. */
13756 if (final_sequence
)
13758 /* This first delay slot will always be executed, so use INSN's
13759 delay slot if is not annulled. */
13760 if (!INSN_ANNULLED_BRANCH_P (insn
))
13762 final_scan_insn (final_sequence
->insn (1),
13763 asm_out_file
, optimize
, 1, NULL
);
13764 final_sequence
->insn (1)->set_deleted ();
13767 output_asm_insn ("nop", 0);
13768 fprintf (asm_out_file
, "\n");
13771 /* Output the unconditional branch to TAKEN. */
13772 if (TARGET_ABSOLUTE_JUMPS
&& TARGET_CB_MAYBE
)
13774 /* Add a hazard nop. */
13775 if (!final_sequence
)
13777 output_asm_insn ("nop\t\t# hazard nop", 0);
13778 fprintf (asm_out_file
, "\n");
13780 output_asm_insn (MIPS_ABSOLUTE_JUMP ("bc\t%0"), &taken
);
13782 else if (TARGET_ABSOLUTE_JUMPS
)
13783 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
13786 mips_output_load_label (taken
);
13787 if (TARGET_CB_MAYBE
)
13788 output_asm_insn ("jrc\t%@%]", 0);
13790 output_asm_insn ("jr\t%@%]%/", 0);
13793 /* Now deal with its delay slot; see above. */
13794 if (final_sequence
)
13796 /* This delay slot will only be executed if the branch is taken.
13797 Use INSN's delay slot if is annulled. */
13798 if (INSN_ANNULLED_BRANCH_P (insn
))
13800 final_scan_insn (final_sequence
->insn (1),
13801 asm_out_file
, optimize
, 1, NULL
);
13802 final_sequence
->insn (1)->set_deleted ();
13804 else if (TARGET_CB_NEVER
)
13805 output_asm_insn ("nop", 0);
13806 fprintf (asm_out_file
, "\n");
13809 /* Output NOT_TAKEN. */
13810 targetm
.asm_out
.internal_label (asm_out_file
, "L",
13811 CODE_LABEL_NUMBER (not_taken
));
13815 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13816 if some equality condition is true. The condition is given by
13817 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13818 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13819 OPERANDS[3] is the second operand and may be zero or a register. */
13822 mips_output_equal_conditional_branch (rtx_insn
* insn
, rtx
*operands
,
13825 const char *branch
[2];
13826 /* For a simple BNEZ or BEQZ microMIPSr3 branch. */
13827 if (TARGET_MICROMIPS
13828 && mips_isa_rev
<= 5
13829 && operands
[3] == const0_rtx
13830 && get_attr_length (insn
) <= 8)
13832 if (mips_cb
== MIPS_CB_OPTIMAL
)
13834 branch
[!inverted_p
] = "%*b%C1z%:\t%2,%0";
13835 branch
[inverted_p
] = "%*b%N1z%:\t%2,%0";
13839 branch
[!inverted_p
] = "%*b%C1z\t%2,%0%/";
13840 branch
[inverted_p
] = "%*b%N1z\t%2,%0%/";
13843 else if (TARGET_CB_MAYBE
)
13845 if (operands
[3] == const0_rtx
)
13847 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13848 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13850 else if (REGNO (operands
[2]) != REGNO (operands
[3]))
13852 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13853 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13857 /* This case is degenerate. It should not happen, but does. */
13858 if (GET_CODE (operands
[1]) == NE
)
13859 inverted_p
= !inverted_p
;
13861 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13862 branch
[inverted_p
] = "%*\t\t# branch never";
13867 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1", "%2,%z3,%0");
13868 branch
[inverted_p
] = MIPS_BRANCH ("b%N1", "%2,%z3,%0");
13871 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
13874 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13875 if some ordering condition is true. The condition is given by
13876 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13877 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13878 OPERANDS[3] is the second operand and may be zero or a register. */
13881 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
13884 const char *branch
[2];
13886 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
13887 Make BRANCH[0] branch on the inverse condition. */
13888 if (operands
[3] != const0_rtx
)
13890 /* Handle degenerate cases that should not, but do, occur. */
13891 if (REGNO (operands
[2]) == REGNO (operands
[3]))
13893 switch (GET_CODE (operands
[1]))
13897 inverted_p
= !inverted_p
;
13898 /* Fall through. */
13901 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13902 branch
[inverted_p
] = "%*\t\t# branch never";
13905 gcc_unreachable ();
13910 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13911 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13916 switch (GET_CODE (operands
[1]))
13918 /* These cases are equivalent to comparisons against zero. */
13920 inverted_p
= !inverted_p
;
13921 /* Fall through. */
13923 if (TARGET_CB_MAYBE
)
13925 branch
[!inverted_p
] = MIPS_BRANCH_C ("bnez", "%2,%0");
13926 branch
[inverted_p
] = MIPS_BRANCH_C ("beqz", "%2,%0");
13930 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
13931 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
13935 /* These cases are always true or always false. */
13937 inverted_p
= !inverted_p
;
13938 /* Fall through. */
13940 if (TARGET_CB_MAYBE
)
13942 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13943 branch
[inverted_p
] = "%*\t\t# branch never";
13947 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
13948 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
13953 if (TARGET_CB_MAYBE
)
13955 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13956 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13960 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
13961 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
13966 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
13969 /* Start a block of code that needs access to the LL, SC and SYNC
13973 mips_start_ll_sc_sync_block (void)
13975 if (!ISA_HAS_LL_SC
)
13977 output_asm_insn (".set\tpush", 0);
13979 output_asm_insn (".set\tmips3", 0);
13981 output_asm_insn (".set\tmips2", 0);
13985 /* End a block started by mips_start_ll_sc_sync_block. */
13988 mips_end_ll_sc_sync_block (void)
13990 if (!ISA_HAS_LL_SC
)
13991 output_asm_insn (".set\tpop", 0);
13994 /* Output and/or return the asm template for a sync instruction. */
13997 mips_output_sync (void)
13999 mips_start_ll_sc_sync_block ();
14000 output_asm_insn ("sync", 0);
14001 mips_end_ll_sc_sync_block ();
14005 /* Return the asm template associated with sync_insn1 value TYPE.
14006 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
14008 static const char *
14009 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
14013 case SYNC_INSN1_MOVE
:
14014 return "move\t%0,%z2";
14015 case SYNC_INSN1_LI
:
14016 return "li\t%0,%2";
14017 case SYNC_INSN1_ADDU
:
14018 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
14019 case SYNC_INSN1_ADDIU
:
14020 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
14021 case SYNC_INSN1_SUBU
:
14022 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
14023 case SYNC_INSN1_AND
:
14024 return "and\t%0,%1,%z2";
14025 case SYNC_INSN1_ANDI
:
14026 return "andi\t%0,%1,%2";
14027 case SYNC_INSN1_OR
:
14028 return "or\t%0,%1,%z2";
14029 case SYNC_INSN1_ORI
:
14030 return "ori\t%0,%1,%2";
14031 case SYNC_INSN1_XOR
:
14032 return "xor\t%0,%1,%z2";
14033 case SYNC_INSN1_XORI
:
14034 return "xori\t%0,%1,%2";
14036 gcc_unreachable ();
14039 /* Return the asm template associated with sync_insn2 value TYPE. */
14041 static const char *
14042 mips_sync_insn2_template (enum attr_sync_insn2 type
)
14046 case SYNC_INSN2_NOP
:
14047 gcc_unreachable ();
14048 case SYNC_INSN2_AND
:
14049 return "and\t%0,%1,%z2";
14050 case SYNC_INSN2_XOR
:
14051 return "xor\t%0,%1,%z2";
14052 case SYNC_INSN2_NOT
:
14053 return "nor\t%0,%1,%.";
14055 gcc_unreachable ();
14058 /* OPERANDS are the operands to a sync loop instruction and INDEX is
14059 the value of the one of the sync_* attributes. Return the operand
14060 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
14061 have the associated attribute. */
14064 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
14067 default_value
= operands
[index
- 1];
14068 return default_value
;
14071 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
14072 sequence for it. */
14075 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
14077 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
14078 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
14079 unsigned int tmp3_insn
;
14080 enum attr_sync_insn1 insn1
;
14081 enum attr_sync_insn2 insn2
;
14084 enum memmodel model
;
14086 /* Read an operand from the sync_WHAT attribute and store it in
14087 variable WHAT. DEFAULT is the default value if no attribute
14089 #define READ_OPERAND(WHAT, DEFAULT) \
14090 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
14093 /* Read the memory. */
14094 READ_OPERAND (mem
, 0);
14096 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
14098 /* Read the other attributes. */
14099 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
14100 READ_OPERAND (oldval
, at
);
14101 READ_OPERAND (cmp
, 0);
14102 READ_OPERAND (newval
, at
);
14103 READ_OPERAND (inclusive_mask
, 0);
14104 READ_OPERAND (exclusive_mask
, 0);
14105 READ_OPERAND (required_oldval
, 0);
14106 READ_OPERAND (insn1_op2
, 0);
14107 insn1
= get_attr_sync_insn1 (insn
);
14108 insn2
= get_attr_sync_insn2 (insn
);
14110 /* Don't bother setting CMP result that is never used. */
14111 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
14114 memmodel_attr
= get_attr_sync_memmodel (insn
);
14115 switch (memmodel_attr
)
14118 model
= MEMMODEL_ACQ_REL
;
14121 model
= MEMMODEL_ACQUIRE
;
14124 model
= memmodel_from_int (INTVAL (operands
[memmodel_attr
]));
14127 mips_multi_start ();
14129 /* Output the release side of the memory barrier. */
14130 if (need_atomic_barrier_p (model
, true))
14132 if (required_oldval
== 0 && TARGET_OCTEON
)
14134 /* Octeon doesn't reorder reads, so a full barrier can be
14135 created by using SYNCW to order writes combined with the
14136 write from the following SC. When the SC successfully
14137 completes, we know that all preceding writes are also
14138 committed to the coherent memory system. It is possible
14139 for a single SYNCW to fail, but a pair of them will never
14140 fail, so we use two. */
14141 mips_multi_add_insn ("syncw", NULL
);
14142 mips_multi_add_insn ("syncw", NULL
);
14145 mips_multi_add_insn ("sync", NULL
);
14148 /* Output the branch-back label. */
14149 mips_multi_add_label ("1:");
14151 /* OLDVAL = *MEM. */
14152 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
14153 oldval
, mem
, NULL
);
14155 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
14156 if (required_oldval
)
14158 if (inclusive_mask
== 0)
14162 gcc_assert (oldval
!= at
);
14163 mips_multi_add_insn ("and\t%0,%1,%2",
14164 at
, oldval
, inclusive_mask
, NULL
);
14167 if (TARGET_CB_NEVER
)
14168 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
14170 /* CMP = 0 [delay slot]. */
14172 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
14174 if (TARGET_CB_MAYBE
&& required_oldval
== const0_rtx
)
14175 mips_multi_add_insn ("bnezc\t%0,2f", tmp1
, NULL
);
14176 else if (TARGET_CB_MAYBE
)
14177 mips_multi_add_insn ("bnec\t%0,%1,2f", tmp1
, required_oldval
, NULL
);
14181 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
14182 if (exclusive_mask
== 0)
14186 gcc_assert (oldval
!= at
);
14187 mips_multi_add_insn ("and\t%0,%1,%z2",
14188 at
, oldval
, exclusive_mask
, NULL
);
14192 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
14194 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
14195 at least one instruction in that case. */
14196 if (insn1
== SYNC_INSN1_MOVE
14197 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
14201 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
14202 newval
, oldval
, insn1_op2
, NULL
);
14206 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
14207 if (insn2
== SYNC_INSN2_NOP
)
14211 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
14212 newval
, tmp2
, inclusive_mask
, NULL
);
14215 tmp3_insn
= mips_multi_last_index ();
14217 /* $AT = $TMP1 | $TMP3. */
14218 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
14220 mips_multi_set_operand (tmp3_insn
, 0, at
);
14225 gcc_assert (tmp1
!= tmp3
);
14226 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
14229 /* if (!commit (*MEM = $AT)) goto 1.
14231 This will sometimes be a delayed branch; see the write code below
14233 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
14235 /* When using branch likely (-mfix-r10000), the delay slot instruction
14236 will be annulled on false. The normal delay slot instructions
14237 calculate the overall result of the atomic operation and must not
14238 be annulled. To ensure this behavior unconditionally use a NOP
14239 in the delay slot for the branch likely case. */
14241 if (TARGET_CB_MAYBE
)
14242 mips_multi_add_insn ("beqzc\t%0,1b", at
, NULL
);
14244 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at
, NULL
);
14246 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
14247 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
14249 mips_multi_copy_insn (tmp3_insn
);
14250 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
14252 else if (!(required_oldval
&& cmp
) && !mips_branch_likely
)
14253 mips_multi_add_insn ("nop", NULL
);
14255 /* CMP = 1 -- either standalone or in a delay slot. */
14256 if (required_oldval
&& cmp
)
14257 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
14259 /* Output the acquire side of the memory barrier. */
14260 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
14261 mips_multi_add_insn ("sync", NULL
);
14263 /* Output the exit label, if needed. */
14264 if (required_oldval
)
14265 mips_multi_add_label ("2:");
14267 #undef READ_OPERAND
14270 /* Output and/or return the asm template for sync loop INSN, which has
14271 the operands given by OPERANDS. */
14274 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
14276 /* Use branch-likely instructions to work around the LL/SC R10000
14278 mips_branch_likely
= TARGET_FIX_R10000
;
14280 mips_process_sync_loop (insn
, operands
);
14282 mips_push_asm_switch (&mips_noreorder
);
14283 mips_push_asm_switch (&mips_nomacro
);
14284 mips_push_asm_switch (&mips_noat
);
14285 mips_start_ll_sc_sync_block ();
14287 mips_multi_write ();
14289 mips_end_ll_sc_sync_block ();
14290 mips_pop_asm_switch (&mips_noat
);
14291 mips_pop_asm_switch (&mips_nomacro
);
14292 mips_pop_asm_switch (&mips_noreorder
);
14297 /* Return the number of individual instructions in sync loop INSN,
14298 which has the operands given by OPERANDS. */
14301 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
14303 /* Use branch-likely instructions to work around the LL/SC R10000
14305 mips_branch_likely
= TARGET_FIX_R10000
;
14306 mips_process_sync_loop (insn
, operands
);
14307 return mips_multi_num_insns
;
14310 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
14311 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
14313 When working around R4000 and R4400 errata, we need to make sure that
14314 the division is not immediately followed by a shift[1][2]. We also
14315 need to stop the division from being put into a branch delay slot[3].
14316 The easiest way to avoid both problems is to add a nop after the
14317 division. When a divide-by-zero check is needed, this nop can be
14318 used to fill the branch delay slot.
14320 [1] If a double-word or a variable shift executes immediately
14321 after starting an integer division, the shift may give an
14322 incorrect result. See quotations of errata #16 and #28 from
14323 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14324 in mips.md for details.
14326 [2] A similar bug to [1] exists for all revisions of the
14327 R4000 and the R4400 when run in an MC configuration.
14328 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
14330 "19. In this following sequence:
14332 ddiv (or ddivu or div or divu)
14333 dsll32 (or dsrl32, dsra32)
14335 if an MPT stall occurs, while the divide is slipping the cpu
14336 pipeline, then the following double shift would end up with an
14339 Workaround: The compiler needs to avoid generating any
14340 sequence with divide followed by extended double shift."
14342 This erratum is also present in "MIPS R4400MC Errata, Processor
14343 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
14344 & 3.0" as errata #10 and #4, respectively.
14346 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14347 (also valid for MIPS R4000MC processors):
14349 "52. R4000SC: This bug does not apply for the R4000PC.
14351 There are two flavors of this bug:
14353 1) If the instruction just after divide takes an RF exception
14354 (tlb-refill, tlb-invalid) and gets an instruction cache
14355 miss (both primary and secondary) and the line which is
14356 currently in secondary cache at this index had the first
14357 data word, where the bits 5..2 are set, then R4000 would
14358 get a wrong result for the div.
14363 ------------------- # end-of page. -tlb-refill
14368 ------------------- # end-of page. -tlb-invalid
14371 2) If the divide is in the taken branch delay slot, where the
14372 target takes RF exception and gets an I-cache miss for the
14373 exception vector or where I-cache miss occurs for the
14374 target address, under the above mentioned scenarios, the
14375 div would get wrong results.
14378 j r2 # to next page mapped or unmapped
14379 div r8,r9 # this bug would be there as long
14380 # as there is an ICache miss and
14381 nop # the "data pattern" is present
14384 beq r0, r0, NextPage # to Next page
14388 This bug is present for div, divu, ddiv, and ddivu
14391 Workaround: For item 1), OS could make sure that the next page
14392 after the divide instruction is also mapped. For item 2), the
14393 compiler could make sure that the divide instruction is not in
14394 the branch delay slot."
14396 These processors have PRId values of 0x00004220 and 0x00004300 for
14397 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
14400 mips_output_division (const char *division
, rtx
*operands
)
14405 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
14407 output_asm_insn (s
, operands
);
14410 if (TARGET_CHECK_ZERO_DIV
)
14414 output_asm_insn (s
, operands
);
14415 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
14417 else if (GENERATE_DIVIDE_TRAPS
)
14419 /* Avoid long replay penalty on load miss by putting the trap before
14422 output_asm_insn ("teq\t%2,%.,7", operands
);
14425 output_asm_insn (s
, operands
);
14426 s
= "teq\t%2,%.,7";
14431 if (flag_delayed_branch
)
14433 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
14434 output_asm_insn (s
, operands
);
14435 s
= "break\t7%)\n1:";
14439 output_asm_insn (s
, operands
);
14440 s
= "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
14447 /* Return the assembly code for MSA DIV_{S,U}.DF or MOD_{S,U}.DF instructions,
14448 which has the operands given by OPERANDS. Add in a divide-by-zero check
14452 mips_msa_output_division (const char *division
, rtx
*operands
)
14457 if (TARGET_CHECK_ZERO_DIV
)
14459 output_asm_insn ("%(bnz.%v0\t%w2,1f", operands
);
14460 output_asm_insn (s
, operands
);
14461 s
= "break\t7%)\n1:";
14466 /* Return true if destination of IN_INSN is used as add source in
14467 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
14468 madd.s dst, x, y, z
14469 madd.s a, dst, b, c */
14472 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14474 int dst_reg
, src_reg
;
14476 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
14477 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
14479 extract_insn (in_insn
);
14480 dst_reg
= REG_P (recog_data
.operand
[0]);
14482 extract_insn (out_insn
);
14483 src_reg
= REG_P (recog_data
.operand
[1]);
14485 if (dst_reg
== src_reg
)
14491 /* Return true if IN_INSN is a multiply-add or multiply-subtract
14492 instruction and if OUT_INSN assigns to the accumulator operand. */
14495 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14497 enum attr_accum_in accum_in
;
14498 int accum_in_opnum
;
14501 if (recog_memoized (in_insn
) < 0)
14504 accum_in
= get_attr_accum_in (in_insn
);
14505 if (accum_in
== ACCUM_IN_NONE
)
14508 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
14510 extract_insn (in_insn
);
14511 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
14512 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
14514 return reg_set_p (accum_in_op
, out_insn
);
14517 /* True if the dependency between OUT_INSN and IN_INSN is on the store
14518 data rather than the address. We need this because the cprestore
14519 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
14520 which causes the default routine to abort. We just return false
14524 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14526 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
14529 return store_data_bypass_p (out_insn
, in_insn
);
14533 /* Variables and flags used in scheduler hooks when tuning for
14537 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
14540 /* If true, then next ALU1/2 instruction will go to ALU1. */
14543 /* If true, then next FALU1/2 unstruction will go to FALU1. */
14546 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
14547 int alu1_core_unit_code
;
14548 int alu2_core_unit_code
;
14549 int falu1_core_unit_code
;
14550 int falu2_core_unit_code
;
14552 /* True if current cycle has a multi instruction.
14553 This flag is used in mips_ls2_dfa_post_advance_cycle. */
14554 bool cycle_has_multi_p
;
14556 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
14557 These are used in mips_ls2_dfa_post_advance_cycle to initialize
14559 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
14560 instruction to go ALU1. */
14561 rtx_insn
*alu1_turn_enabled_insn
;
14562 rtx_insn
*alu2_turn_enabled_insn
;
14563 rtx_insn
*falu1_turn_enabled_insn
;
14564 rtx_insn
*falu2_turn_enabled_insn
;
14567 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
14568 dependencies have no cost, except on the 20Kc where output-dependence
14569 is treated like input-dependence. */
14572 mips_adjust_cost (rtx_insn
*, int dep_type
, rtx_insn
*, int cost
, unsigned int)
14574 if (dep_type
!= 0 && (dep_type
!= REG_DEP_OUTPUT
|| !TUNE_20KC
))
14579 /* Return the number of instructions that can be issued per cycle. */
14582 mips_issue_rate (void)
14586 case PROCESSOR_74KC
:
14587 case PROCESSOR_74KF2_1
:
14588 case PROCESSOR_74KF1_1
:
14589 case PROCESSOR_74KF3_2
:
14590 /* The 74k is not strictly quad-issue cpu, but can be seen as one
14591 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
14592 but in reality only a maximum of 3 insns can be issued as
14593 floating-point loads and stores also require a slot in the
14595 case PROCESSOR_R10000
:
14596 /* All R10K Processors are quad-issue (being the first MIPS
14597 processors to support this feature). */
14600 case PROCESSOR_20KC
:
14601 case PROCESSOR_R4130
:
14602 case PROCESSOR_R5400
:
14603 case PROCESSOR_R5500
:
14604 case PROCESSOR_R5900
:
14605 case PROCESSOR_R7000
:
14606 case PROCESSOR_R9000
:
14607 case PROCESSOR_OCTEON
:
14608 case PROCESSOR_OCTEON2
:
14609 case PROCESSOR_OCTEON3
:
14610 case PROCESSOR_I6400
:
14611 case PROCESSOR_GS264E
:
14614 case PROCESSOR_SB1
:
14615 case PROCESSOR_SB1A
:
14616 /* This is actually 4, but we get better performance if we claim 3.
14617 This is partly because of unwanted speculative code motion with the
14618 larger number, and partly because in most common cases we can't
14619 reach the theoretical max of 4. */
14622 case PROCESSOR_LOONGSON_2E
:
14623 case PROCESSOR_LOONGSON_2F
:
14624 case PROCESSOR_GS464
:
14625 case PROCESSOR_GS464E
:
14626 case PROCESSOR_P5600
:
14627 case PROCESSOR_P6600
:
14630 case PROCESSOR_XLP
:
14631 return (reload_completed
? 4 : 3);
14638 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
14641 mips_ls2_init_dfa_post_cycle_insn (void)
14644 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
14645 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
14649 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
14650 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
14654 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
14655 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
14659 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
14660 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
14663 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
14664 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
14665 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
14666 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
14669 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
14670 Init data used in mips_dfa_post_advance_cycle. */
14673 mips_init_dfa_post_cycle_insn (void)
14675 if (TUNE_LOONGSON_2EF
)
14676 mips_ls2_init_dfa_post_cycle_insn ();
14679 /* Initialize STATE when scheduling for Loongson 2E/2F.
14680 Support round-robin dispatch scheme by enabling only one of
14681 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
14685 mips_ls2_dfa_post_advance_cycle (state_t state
)
14687 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
14689 /* Though there are no non-pipelined ALU1 insns,
14690 we can get an instruction of type 'multi' before reload. */
14691 gcc_assert (mips_ls2
.cycle_has_multi_p
);
14692 mips_ls2
.alu1_turn_p
= false;
14695 mips_ls2
.cycle_has_multi_p
= false;
14697 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
14698 /* We have a non-pipelined alu instruction in the core,
14699 adjust round-robin counter. */
14700 mips_ls2
.alu1_turn_p
= true;
14702 if (mips_ls2
.alu1_turn_p
)
14704 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
14705 gcc_unreachable ();
14709 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
14710 gcc_unreachable ();
14713 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
14715 /* There are no non-pipelined FALU1 insns. */
14716 gcc_unreachable ();
14717 mips_ls2
.falu1_turn_p
= false;
14720 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
14721 /* We have a non-pipelined falu instruction in the core,
14722 adjust round-robin counter. */
14723 mips_ls2
.falu1_turn_p
= true;
14725 if (mips_ls2
.falu1_turn_p
)
14727 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
14728 gcc_unreachable ();
14732 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
14733 gcc_unreachable ();
14737 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
14738 This hook is being called at the start of each cycle. */
14741 mips_dfa_post_advance_cycle (void)
14743 if (TUNE_LOONGSON_2EF
)
14744 mips_ls2_dfa_post_advance_cycle (curr_state
);
14747 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
14748 be as wide as the scheduling freedom in the DFA. */
14751 mips_multipass_dfa_lookahead (void)
14753 /* Can schedule up to 4 of the 6 function units in any one cycle. */
14757 if (TUNE_LOONGSON_2EF
|| TUNE_GS464
|| TUNE_GS464E
)
14760 if (TUNE_OCTEON
|| TUNE_GS264E
)
14763 if (TUNE_P5600
|| TUNE_P6600
|| TUNE_I6400
)
14769 /* Remove the instruction at index LOWER from ready queue READY and
14770 reinsert it in front of the instruction at index HIGHER. LOWER must
14774 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
14776 rtx_insn
*new_head
;
14779 new_head
= ready
[lower
];
14780 for (i
= lower
; i
< higher
; i
++)
14781 ready
[i
] = ready
[i
+ 1];
14782 ready
[i
] = new_head
;
14785 /* If the priority of the instruction at POS2 in the ready queue READY
14786 is within LIMIT units of that of the instruction at POS1, swap the
14787 instructions if POS2 is not already less than POS1. */
14790 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
14793 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
14797 temp
= ready
[pos1
];
14798 ready
[pos1
] = ready
[pos2
];
14799 ready
[pos2
] = temp
;
14803 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
14804 that may clobber hi or lo. */
14805 static rtx_insn
*mips_macc_chains_last_hilo
;
14807 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
14808 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
14811 mips_macc_chains_record (rtx_insn
*insn
)
14813 if (get_attr_may_clobber_hilo (insn
))
14814 mips_macc_chains_last_hilo
= insn
;
14817 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
14818 has NREADY elements, looking for a multiply-add or multiply-subtract
14819 instruction that is cumulative with mips_macc_chains_last_hilo.
14820 If there is one, promote it ahead of anything else that might
14821 clobber hi or lo. */
14824 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
14828 if (mips_macc_chains_last_hilo
!= 0)
14829 for (i
= nready
- 1; i
>= 0; i
--)
14830 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
14832 for (j
= nready
- 1; j
> i
; j
--)
14833 if (recog_memoized (ready
[j
]) >= 0
14834 && get_attr_may_clobber_hilo (ready
[j
]))
14836 mips_promote_ready (ready
, i
, j
);
14843 /* The last instruction to be scheduled. */
14844 static rtx_insn
*vr4130_last_insn
;
14846 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
14847 points to an rtx that is initially an instruction. Nullify the rtx
14848 if the instruction uses the value of register X. */
14851 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14856 insn_ptr
= (rtx
*) data
;
14859 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
14863 /* Return true if there is true register dependence between vr4130_last_insn
14867 vr4130_true_reg_dependence_p (rtx insn
)
14869 note_stores (PATTERN (vr4130_last_insn
),
14870 vr4130_true_reg_dependence_p_1
, &insn
);
14874 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
14875 the ready queue and that INSN2 is the instruction after it, return
14876 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
14877 in which INSN1 and INSN2 can probably issue in parallel, but for
14878 which (INSN2, INSN1) should be less sensitive to instruction
14879 alignment than (INSN1, INSN2). See 4130.md for more details. */
14882 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
14884 sd_iterator_def sd_it
;
14887 /* Check for the following case:
14889 1) there is some other instruction X with an anti dependence on INSN1;
14890 2) X has a higher priority than INSN2; and
14891 3) X is an arithmetic instruction (and thus has no unit restrictions).
14893 If INSN1 is the last instruction blocking X, it would better to
14894 choose (INSN1, X) over (INSN2, INSN1). */
14895 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
14896 if (DEP_TYPE (dep
) == REG_DEP_ANTI
14897 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
14898 && recog_memoized (DEP_CON (dep
)) >= 0
14899 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
14902 if (vr4130_last_insn
!= 0
14903 && recog_memoized (insn1
) >= 0
14904 && recog_memoized (insn2
) >= 0)
14906 /* See whether INSN1 and INSN2 use different execution units,
14907 or if they are both ALU-type instructions. If so, they can
14908 probably execute in parallel. */
14909 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
14910 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
14911 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
14913 /* If only one of the instructions has a dependence on
14914 vr4130_last_insn, prefer to schedule the other one first. */
14915 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
14916 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
14917 if (dep1_p
!= dep2_p
)
14920 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
14921 is not an ALU-type instruction and if INSN1 uses the same
14922 execution unit. (Note that if this condition holds, we already
14923 know that INSN2 uses a different execution unit.) */
14924 if (class1
!= VR4130_CLASS_ALU
14925 && recog_memoized (vr4130_last_insn
) >= 0
14926 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
14933 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
14934 queue with at least two instructions. Swap the first two if
14935 vr4130_swap_insns_p says that it could be worthwhile. */
14938 vr4130_reorder (rtx_insn
**ready
, int nready
)
14940 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
14941 mips_promote_ready (ready
, nready
- 2, nready
- 1);
14944 /* Record whether last 74k AGEN instruction was a load or store. */
14945 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
14947 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
14948 resets to TYPE_UNKNOWN state. */
14951 mips_74k_agen_init (rtx_insn
*insn
)
14953 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
14954 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
14957 enum attr_type type
= get_attr_type (insn
);
14958 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
14959 mips_last_74k_agen_insn
= type
;
14963 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
14964 loads to be grouped together, and multiple stores to be grouped
14965 together. Swap things around in the ready queue to make this happen. */
14968 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
14971 int store_pos
, load_pos
;
14976 for (i
= nready
- 1; i
>= 0; i
--)
14978 rtx_insn
*insn
= ready
[i
];
14979 if (USEFUL_INSN_P (insn
))
14980 switch (get_attr_type (insn
))
14983 if (store_pos
== -1)
14988 if (load_pos
== -1)
14997 if (load_pos
== -1 || store_pos
== -1)
15000 switch (mips_last_74k_agen_insn
)
15003 /* Prefer to schedule loads since they have a higher latency. */
15005 /* Swap loads to the front of the queue. */
15006 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
15009 /* Swap stores to the front of the queue. */
15010 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
15017 /* Implement TARGET_SCHED_INIT. */
15020 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15021 int max_ready ATTRIBUTE_UNUSED
)
15023 mips_macc_chains_last_hilo
= 0;
15024 vr4130_last_insn
= 0;
15025 mips_74k_agen_init (NULL
);
15027 /* When scheduling for Loongson2, branch instructions go to ALU1,
15028 therefore basic block is most likely to start with round-robin counter
15029 pointed to ALU2. */
15030 mips_ls2
.alu1_turn_p
= false;
15031 mips_ls2
.falu1_turn_p
= true;
15034 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
15037 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15038 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
15040 if (!reload_completed
15041 && TUNE_MACC_CHAINS
15043 mips_macc_chains_reorder (ready
, *nreadyp
);
15045 if (reload_completed
15047 && !TARGET_VR4130_ALIGN
15049 vr4130_reorder (ready
, *nreadyp
);
15052 mips_74k_agen_reorder (ready
, *nreadyp
);
15055 /* Implement TARGET_SCHED_REORDER. */
15058 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15059 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
15061 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
15062 return mips_issue_rate ();
15065 /* Implement TARGET_SCHED_REORDER2. */
15068 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15069 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
15071 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
15072 return cached_can_issue_more
;
15075 /* Update round-robin counters for ALU1/2 and FALU1/2. */
15078 mips_ls2_variable_issue (rtx_insn
*insn
)
15080 if (mips_ls2
.alu1_turn_p
)
15082 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
15083 mips_ls2
.alu1_turn_p
= false;
15087 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
15088 mips_ls2
.alu1_turn_p
= true;
15091 if (mips_ls2
.falu1_turn_p
)
15093 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
15094 mips_ls2
.falu1_turn_p
= false;
15098 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
15099 mips_ls2
.falu1_turn_p
= true;
15102 if (recog_memoized (insn
) >= 0)
15103 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
15106 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15109 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15110 rtx_insn
*insn
, int more
)
15112 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
15113 if (USEFUL_INSN_P (insn
))
15115 if (get_attr_type (insn
) != TYPE_GHOST
)
15117 if (!reload_completed
&& TUNE_MACC_CHAINS
)
15118 mips_macc_chains_record (insn
);
15119 vr4130_last_insn
= insn
;
15121 mips_74k_agen_init (insn
);
15122 else if (TUNE_LOONGSON_2EF
)
15123 mips_ls2_variable_issue (insn
);
15126 /* Instructions of type 'multi' should all be split before
15127 the second scheduling pass. */
15128 gcc_assert (!reload_completed
15129 || recog_memoized (insn
) < 0
15130 || get_attr_type (insn
) != TYPE_MULTI
);
15132 cached_can_issue_more
= more
;
15136 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
15137 return the first operand of the associated PREF or PREFX insn. */
15140 mips_prefetch_cookie (rtx write
, rtx locality
)
15142 /* store_streamed / load_streamed. */
15143 if (INTVAL (locality
) <= 0)
15144 return GEN_INT (INTVAL (write
) + 4);
15146 /* store / load. */
15147 if (INTVAL (locality
) <= 2)
15150 /* store_retained / load_retained. */
15151 return GEN_INT (INTVAL (write
) + 6);
15154 /* Loongson EXT2 only implements pref hint=0 (prefetch for load) and hint=1
15155 (prefetch for store), other hint just scale to hint = 0 and hint = 1. */
15158 mips_loongson_ext2_prefetch_cookie (rtx write
, rtx
)
15161 if (INTVAL (write
) == 1)
15162 return GEN_INT (INTVAL (write
));
15165 if (INTVAL (write
) == 0)
15166 return GEN_INT (INTVAL (write
));
15168 gcc_unreachable ();
15172 /* Flags that indicate when a built-in function is available.
15174 BUILTIN_AVAIL_NON_MIPS16
15175 The function is available on the current target if !TARGET_MIPS16.
15177 BUILTIN_AVAIL_MIPS16
15178 The function is available on the current target if TARGET_MIPS16. */
15179 #define BUILTIN_AVAIL_NON_MIPS16 1
15180 #define BUILTIN_AVAIL_MIPS16 2
15182 /* Declare an availability predicate for built-in functions that
15183 require non-MIPS16 mode and also require COND to be true.
15184 NAME is the main part of the predicate's name. */
15185 #define AVAIL_NON_MIPS16(NAME, COND) \
15186 static unsigned int \
15187 mips_builtin_avail_##NAME (void) \
15189 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
15192 /* Declare an availability predicate for built-in functions that
15193 support both MIPS16 and non-MIPS16 code and also require COND
15194 to be true. NAME is the main part of the predicate's name. */
15195 #define AVAIL_ALL(NAME, COND) \
15196 static unsigned int \
15197 mips_builtin_avail_##NAME (void) \
15199 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
15202 /* This structure describes a single built-in function. */
15203 struct mips_builtin_description
{
15204 /* The code of the main .md file instruction. See mips_builtin_type
15205 for more information. */
15206 enum insn_code icode
;
15208 /* The floating-point comparison code to use with ICODE, if any. */
15209 enum mips_fp_condition cond
;
15211 /* The name of the built-in function. */
15214 /* Specifies how the function should be expanded. */
15215 enum mips_builtin_type builtin_type
;
15217 /* The function's prototype. */
15218 enum mips_function_type function_type
;
15220 /* Whether the function is available. */
15221 unsigned int (*avail
) (void);
15224 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
15225 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
15226 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
15227 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
15228 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
15229 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
15230 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
15231 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
15232 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
15233 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_MMI
)
15234 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
15235 AVAIL_NON_MIPS16 (msa
, TARGET_MSA
)
15237 /* Construct a mips_builtin_description from the given arguments.
15239 INSN is the name of the associated instruction pattern, without the
15240 leading CODE_FOR_mips_.
15242 CODE is the floating-point condition code associated with the
15243 function. It can be 'f' if the field is not applicable.
15245 NAME is the name of the function itself, without the leading
15248 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
15250 AVAIL is the name of the availability predicate, without the leading
15251 mips_builtin_avail_. */
15252 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
15253 FUNCTION_TYPE, AVAIL) \
15254 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
15255 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
15256 mips_builtin_avail_ ## AVAIL }
15258 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
15259 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
15260 are as for MIPS_BUILTIN. */
15261 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15262 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
15264 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
15265 are subject to mips_builtin_avail_<AVAIL>. */
15266 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
15267 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
15268 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
15269 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
15270 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
15272 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
15273 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
15274 while the any and all forms are subject to mips_builtin_avail_mips3d. */
15275 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
15276 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
15277 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
15279 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
15280 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
15282 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
15283 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
15285 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
15286 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
15289 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
15290 are subject to mips_builtin_avail_mips3d. */
15291 #define CMP_4S_BUILTINS(INSN, COND) \
15292 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
15293 MIPS_BUILTIN_CMP_ANY, \
15294 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
15295 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
15296 MIPS_BUILTIN_CMP_ALL, \
15297 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
15299 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
15300 instruction requires mips_builtin_avail_<AVAIL>. */
15301 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
15302 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
15303 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15305 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
15306 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15309 /* Define all the built-in functions related to C.cond.fmt condition COND. */
15310 #define CMP_BUILTINS(COND) \
15311 MOVTF_BUILTINS (c, COND, paired_single), \
15312 MOVTF_BUILTINS (cabs, COND, mips3d), \
15313 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
15314 CMP_PS_BUILTINS (c, COND, paired_single), \
15315 CMP_PS_BUILTINS (cabs, COND, mips3d), \
15316 CMP_4S_BUILTINS (c, COND), \
15317 CMP_4S_BUILTINS (cabs, COND)
15319 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
15320 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
15321 and AVAIL are as for MIPS_BUILTIN. */
15322 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15323 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15324 FUNCTION_TYPE, AVAIL)
15326 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
15327 branch instruction. AVAIL is as for MIPS_BUILTIN. */
15328 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
15329 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
15330 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
15332 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
15333 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15334 builtin_description field. */
15335 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
15336 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
15337 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
15338 FUNCTION_TYPE, mips_builtin_avail_loongson }
15340 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
15341 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15342 builtin_description field. */
15343 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
15344 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
15346 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
15347 We use functions of this form when the same insn can be usefully applied
15348 to more than one datatype. */
15349 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
15350 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
15352 /* Define an MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15353 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15355 #define MSA_BUILTIN(INSN, FUNCTION_TYPE) \
15356 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15357 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15358 FUNCTION_TYPE, mips_builtin_avail_msa }
15360 /* Define a remapped MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15361 for instruction CODE_FOR_msa_<INSN2>. FUNCTION_TYPE is
15362 a builtin_description field. */
15363 #define MSA_BUILTIN_REMAP(INSN, INSN2, FUNCTION_TYPE) \
15364 { CODE_FOR_msa_ ## INSN2, MIPS_FP_COND_f, \
15365 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15366 FUNCTION_TYPE, mips_builtin_avail_msa }
15368 /* Define an MSA MIPS_BUILTIN_MSA_TEST_BRANCH function __builtin_msa_<INSN>
15369 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15371 #define MSA_BUILTIN_TEST_BRANCH(INSN, FUNCTION_TYPE) \
15372 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15373 "__builtin_msa_" #INSN, MIPS_BUILTIN_MSA_TEST_BRANCH, \
15374 FUNCTION_TYPE, mips_builtin_avail_msa }
15376 /* Define an MSA MIPS_BUILTIN_DIRECT_NO_TARGET function __builtin_msa_<INSN>
15377 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15379 #define MSA_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE) \
15380 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15381 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15382 FUNCTION_TYPE, mips_builtin_avail_msa }
15384 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
15385 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
15386 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
15387 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
15388 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
15389 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
15390 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
15391 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
15393 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
15394 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
15395 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
15396 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
15397 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
15398 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
15399 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
15400 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
15401 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
15402 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
15403 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
15404 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
15405 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
15406 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
15407 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
15408 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
15409 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
15410 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
15411 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
15412 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
15413 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
15414 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
15415 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
15416 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
15417 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
15418 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
15419 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
15420 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
15421 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
15422 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
15424 #define CODE_FOR_msa_adds_s_b CODE_FOR_ssaddv16qi3
15425 #define CODE_FOR_msa_adds_s_h CODE_FOR_ssaddv8hi3
15426 #define CODE_FOR_msa_adds_s_w CODE_FOR_ssaddv4si3
15427 #define CODE_FOR_msa_adds_s_d CODE_FOR_ssaddv2di3
15428 #define CODE_FOR_msa_adds_u_b CODE_FOR_usaddv16qi3
15429 #define CODE_FOR_msa_adds_u_h CODE_FOR_usaddv8hi3
15430 #define CODE_FOR_msa_adds_u_w CODE_FOR_usaddv4si3
15431 #define CODE_FOR_msa_adds_u_d CODE_FOR_usaddv2di3
15432 #define CODE_FOR_msa_addv_b CODE_FOR_addv16qi3
15433 #define CODE_FOR_msa_addv_h CODE_FOR_addv8hi3
15434 #define CODE_FOR_msa_addv_w CODE_FOR_addv4si3
15435 #define CODE_FOR_msa_addv_d CODE_FOR_addv2di3
15436 #define CODE_FOR_msa_addvi_b CODE_FOR_addv16qi3
15437 #define CODE_FOR_msa_addvi_h CODE_FOR_addv8hi3
15438 #define CODE_FOR_msa_addvi_w CODE_FOR_addv4si3
15439 #define CODE_FOR_msa_addvi_d CODE_FOR_addv2di3
15440 #define CODE_FOR_msa_and_v CODE_FOR_andv16qi3
15441 #define CODE_FOR_msa_andi_b CODE_FOR_andv16qi3
15442 #define CODE_FOR_msa_bmnz_v CODE_FOR_msa_bmnz_b
15443 #define CODE_FOR_msa_bmnzi_b CODE_FOR_msa_bmnz_b
15444 #define CODE_FOR_msa_bmz_v CODE_FOR_msa_bmz_b
15445 #define CODE_FOR_msa_bmzi_b CODE_FOR_msa_bmz_b
15446 #define CODE_FOR_msa_bnz_v CODE_FOR_msa_bnz_v_b
15447 #define CODE_FOR_msa_bz_v CODE_FOR_msa_bz_v_b
15448 #define CODE_FOR_msa_bsel_v CODE_FOR_msa_bsel_b
15449 #define CODE_FOR_msa_bseli_b CODE_FOR_msa_bsel_b
15450 #define CODE_FOR_msa_ceqi_b CODE_FOR_msa_ceq_b
15451 #define CODE_FOR_msa_ceqi_h CODE_FOR_msa_ceq_h
15452 #define CODE_FOR_msa_ceqi_w CODE_FOR_msa_ceq_w
15453 #define CODE_FOR_msa_ceqi_d CODE_FOR_msa_ceq_d
15454 #define CODE_FOR_msa_clti_s_b CODE_FOR_msa_clt_s_b
15455 #define CODE_FOR_msa_clti_s_h CODE_FOR_msa_clt_s_h
15456 #define CODE_FOR_msa_clti_s_w CODE_FOR_msa_clt_s_w
15457 #define CODE_FOR_msa_clti_s_d CODE_FOR_msa_clt_s_d
15458 #define CODE_FOR_msa_clti_u_b CODE_FOR_msa_clt_u_b
15459 #define CODE_FOR_msa_clti_u_h CODE_FOR_msa_clt_u_h
15460 #define CODE_FOR_msa_clti_u_w CODE_FOR_msa_clt_u_w
15461 #define CODE_FOR_msa_clti_u_d CODE_FOR_msa_clt_u_d
15462 #define CODE_FOR_msa_clei_s_b CODE_FOR_msa_cle_s_b
15463 #define CODE_FOR_msa_clei_s_h CODE_FOR_msa_cle_s_h
15464 #define CODE_FOR_msa_clei_s_w CODE_FOR_msa_cle_s_w
15465 #define CODE_FOR_msa_clei_s_d CODE_FOR_msa_cle_s_d
15466 #define CODE_FOR_msa_clei_u_b CODE_FOR_msa_cle_u_b
15467 #define CODE_FOR_msa_clei_u_h CODE_FOR_msa_cle_u_h
15468 #define CODE_FOR_msa_clei_u_w CODE_FOR_msa_cle_u_w
15469 #define CODE_FOR_msa_clei_u_d CODE_FOR_msa_cle_u_d
15470 #define CODE_FOR_msa_div_s_b CODE_FOR_divv16qi3
15471 #define CODE_FOR_msa_div_s_h CODE_FOR_divv8hi3
15472 #define CODE_FOR_msa_div_s_w CODE_FOR_divv4si3
15473 #define CODE_FOR_msa_div_s_d CODE_FOR_divv2di3
15474 #define CODE_FOR_msa_div_u_b CODE_FOR_udivv16qi3
15475 #define CODE_FOR_msa_div_u_h CODE_FOR_udivv8hi3
15476 #define CODE_FOR_msa_div_u_w CODE_FOR_udivv4si3
15477 #define CODE_FOR_msa_div_u_d CODE_FOR_udivv2di3
15478 #define CODE_FOR_msa_fadd_w CODE_FOR_addv4sf3
15479 #define CODE_FOR_msa_fadd_d CODE_FOR_addv2df3
15480 #define CODE_FOR_msa_fexdo_w CODE_FOR_vec_pack_trunc_v2df
15481 #define CODE_FOR_msa_ftrunc_s_w CODE_FOR_fix_truncv4sfv4si2
15482 #define CODE_FOR_msa_ftrunc_s_d CODE_FOR_fix_truncv2dfv2di2
15483 #define CODE_FOR_msa_ftrunc_u_w CODE_FOR_fixuns_truncv4sfv4si2
15484 #define CODE_FOR_msa_ftrunc_u_d CODE_FOR_fixuns_truncv2dfv2di2
15485 #define CODE_FOR_msa_ffint_s_w CODE_FOR_floatv4siv4sf2
15486 #define CODE_FOR_msa_ffint_s_d CODE_FOR_floatv2div2df2
15487 #define CODE_FOR_msa_ffint_u_w CODE_FOR_floatunsv4siv4sf2
15488 #define CODE_FOR_msa_ffint_u_d CODE_FOR_floatunsv2div2df2
15489 #define CODE_FOR_msa_fsub_w CODE_FOR_subv4sf3
15490 #define CODE_FOR_msa_fsub_d CODE_FOR_subv2df3
15491 #define CODE_FOR_msa_fmadd_w CODE_FOR_fmav4sf4
15492 #define CODE_FOR_msa_fmadd_d CODE_FOR_fmav2df4
15493 #define CODE_FOR_msa_fmsub_w CODE_FOR_fnmav4sf4
15494 #define CODE_FOR_msa_fmsub_d CODE_FOR_fnmav2df4
15495 #define CODE_FOR_msa_fmul_w CODE_FOR_mulv4sf3
15496 #define CODE_FOR_msa_fmul_d CODE_FOR_mulv2df3
15497 #define CODE_FOR_msa_fdiv_w CODE_FOR_divv4sf3
15498 #define CODE_FOR_msa_fdiv_d CODE_FOR_divv2df3
15499 #define CODE_FOR_msa_fmax_w CODE_FOR_smaxv4sf3
15500 #define CODE_FOR_msa_fmax_d CODE_FOR_smaxv2df3
15501 #define CODE_FOR_msa_fmin_w CODE_FOR_sminv4sf3
15502 #define CODE_FOR_msa_fmin_d CODE_FOR_sminv2df3
15503 #define CODE_FOR_msa_fsqrt_w CODE_FOR_sqrtv4sf2
15504 #define CODE_FOR_msa_fsqrt_d CODE_FOR_sqrtv2df2
15505 #define CODE_FOR_msa_max_s_b CODE_FOR_smaxv16qi3
15506 #define CODE_FOR_msa_max_s_h CODE_FOR_smaxv8hi3
15507 #define CODE_FOR_msa_max_s_w CODE_FOR_smaxv4si3
15508 #define CODE_FOR_msa_max_s_d CODE_FOR_smaxv2di3
15509 #define CODE_FOR_msa_maxi_s_b CODE_FOR_smaxv16qi3
15510 #define CODE_FOR_msa_maxi_s_h CODE_FOR_smaxv8hi3
15511 #define CODE_FOR_msa_maxi_s_w CODE_FOR_smaxv4si3
15512 #define CODE_FOR_msa_maxi_s_d CODE_FOR_smaxv2di3
15513 #define CODE_FOR_msa_max_u_b CODE_FOR_umaxv16qi3
15514 #define CODE_FOR_msa_max_u_h CODE_FOR_umaxv8hi3
15515 #define CODE_FOR_msa_max_u_w CODE_FOR_umaxv4si3
15516 #define CODE_FOR_msa_max_u_d CODE_FOR_umaxv2di3
15517 #define CODE_FOR_msa_maxi_u_b CODE_FOR_umaxv16qi3
15518 #define CODE_FOR_msa_maxi_u_h CODE_FOR_umaxv8hi3
15519 #define CODE_FOR_msa_maxi_u_w CODE_FOR_umaxv4si3
15520 #define CODE_FOR_msa_maxi_u_d CODE_FOR_umaxv2di3
15521 #define CODE_FOR_msa_min_s_b CODE_FOR_sminv16qi3
15522 #define CODE_FOR_msa_min_s_h CODE_FOR_sminv8hi3
15523 #define CODE_FOR_msa_min_s_w CODE_FOR_sminv4si3
15524 #define CODE_FOR_msa_min_s_d CODE_FOR_sminv2di3
15525 #define CODE_FOR_msa_mini_s_b CODE_FOR_sminv16qi3
15526 #define CODE_FOR_msa_mini_s_h CODE_FOR_sminv8hi3
15527 #define CODE_FOR_msa_mini_s_w CODE_FOR_sminv4si3
15528 #define CODE_FOR_msa_mini_s_d CODE_FOR_sminv2di3
15529 #define CODE_FOR_msa_min_u_b CODE_FOR_uminv16qi3
15530 #define CODE_FOR_msa_min_u_h CODE_FOR_uminv8hi3
15531 #define CODE_FOR_msa_min_u_w CODE_FOR_uminv4si3
15532 #define CODE_FOR_msa_min_u_d CODE_FOR_uminv2di3
15533 #define CODE_FOR_msa_mini_u_b CODE_FOR_uminv16qi3
15534 #define CODE_FOR_msa_mini_u_h CODE_FOR_uminv8hi3
15535 #define CODE_FOR_msa_mini_u_w CODE_FOR_uminv4si3
15536 #define CODE_FOR_msa_mini_u_d CODE_FOR_uminv2di3
15537 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15538 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15539 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15540 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15541 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15542 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15543 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15544 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15545 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15546 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15547 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15548 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15549 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15550 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15551 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15552 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15553 #define CODE_FOR_msa_mulv_b CODE_FOR_mulv16qi3
15554 #define CODE_FOR_msa_mulv_h CODE_FOR_mulv8hi3
15555 #define CODE_FOR_msa_mulv_w CODE_FOR_mulv4si3
15556 #define CODE_FOR_msa_mulv_d CODE_FOR_mulv2di3
15557 #define CODE_FOR_msa_nlzc_b CODE_FOR_clzv16qi2
15558 #define CODE_FOR_msa_nlzc_h CODE_FOR_clzv8hi2
15559 #define CODE_FOR_msa_nlzc_w CODE_FOR_clzv4si2
15560 #define CODE_FOR_msa_nlzc_d CODE_FOR_clzv2di2
15561 #define CODE_FOR_msa_nor_v CODE_FOR_msa_nor_b
15562 #define CODE_FOR_msa_or_v CODE_FOR_iorv16qi3
15563 #define CODE_FOR_msa_ori_b CODE_FOR_iorv16qi3
15564 #define CODE_FOR_msa_nori_b CODE_FOR_msa_nor_b
15565 #define CODE_FOR_msa_pcnt_b CODE_FOR_popcountv16qi2
15566 #define CODE_FOR_msa_pcnt_h CODE_FOR_popcountv8hi2
15567 #define CODE_FOR_msa_pcnt_w CODE_FOR_popcountv4si2
15568 #define CODE_FOR_msa_pcnt_d CODE_FOR_popcountv2di2
15569 #define CODE_FOR_msa_xor_v CODE_FOR_xorv16qi3
15570 #define CODE_FOR_msa_xori_b CODE_FOR_xorv16qi3
15571 #define CODE_FOR_msa_sll_b CODE_FOR_vashlv16qi3
15572 #define CODE_FOR_msa_sll_h CODE_FOR_vashlv8hi3
15573 #define CODE_FOR_msa_sll_w CODE_FOR_vashlv4si3
15574 #define CODE_FOR_msa_sll_d CODE_FOR_vashlv2di3
15575 #define CODE_FOR_msa_slli_b CODE_FOR_vashlv16qi3
15576 #define CODE_FOR_msa_slli_h CODE_FOR_vashlv8hi3
15577 #define CODE_FOR_msa_slli_w CODE_FOR_vashlv4si3
15578 #define CODE_FOR_msa_slli_d CODE_FOR_vashlv2di3
15579 #define CODE_FOR_msa_sra_b CODE_FOR_vashrv16qi3
15580 #define CODE_FOR_msa_sra_h CODE_FOR_vashrv8hi3
15581 #define CODE_FOR_msa_sra_w CODE_FOR_vashrv4si3
15582 #define CODE_FOR_msa_sra_d CODE_FOR_vashrv2di3
15583 #define CODE_FOR_msa_srai_b CODE_FOR_vashrv16qi3
15584 #define CODE_FOR_msa_srai_h CODE_FOR_vashrv8hi3
15585 #define CODE_FOR_msa_srai_w CODE_FOR_vashrv4si3
15586 #define CODE_FOR_msa_srai_d CODE_FOR_vashrv2di3
15587 #define CODE_FOR_msa_srl_b CODE_FOR_vlshrv16qi3
15588 #define CODE_FOR_msa_srl_h CODE_FOR_vlshrv8hi3
15589 #define CODE_FOR_msa_srl_w CODE_FOR_vlshrv4si3
15590 #define CODE_FOR_msa_srl_d CODE_FOR_vlshrv2di3
15591 #define CODE_FOR_msa_srli_b CODE_FOR_vlshrv16qi3
15592 #define CODE_FOR_msa_srli_h CODE_FOR_vlshrv8hi3
15593 #define CODE_FOR_msa_srli_w CODE_FOR_vlshrv4si3
15594 #define CODE_FOR_msa_srli_d CODE_FOR_vlshrv2di3
15595 #define CODE_FOR_msa_subv_b CODE_FOR_subv16qi3
15596 #define CODE_FOR_msa_subv_h CODE_FOR_subv8hi3
15597 #define CODE_FOR_msa_subv_w CODE_FOR_subv4si3
15598 #define CODE_FOR_msa_subv_d CODE_FOR_subv2di3
15599 #define CODE_FOR_msa_subvi_b CODE_FOR_subv16qi3
15600 #define CODE_FOR_msa_subvi_h CODE_FOR_subv8hi3
15601 #define CODE_FOR_msa_subvi_w CODE_FOR_subv4si3
15602 #define CODE_FOR_msa_subvi_d CODE_FOR_subv2di3
15604 #define CODE_FOR_msa_move_v CODE_FOR_movv16qi
15606 #define CODE_FOR_msa_vshf_b CODE_FOR_vec_permv16qi
15607 #define CODE_FOR_msa_vshf_h CODE_FOR_vec_permv8hi
15608 #define CODE_FOR_msa_vshf_w CODE_FOR_vec_permv4si
15609 #define CODE_FOR_msa_vshf_d CODE_FOR_vec_permv2di
15611 #define CODE_FOR_msa_ilvod_d CODE_FOR_msa_ilvl_d
15612 #define CODE_FOR_msa_ilvev_d CODE_FOR_msa_ilvr_d
15613 #define CODE_FOR_msa_pckod_d CODE_FOR_msa_ilvl_d
15614 #define CODE_FOR_msa_pckev_d CODE_FOR_msa_ilvr_d
15616 #define CODE_FOR_msa_ldi_b CODE_FOR_msa_ldiv16qi
15617 #define CODE_FOR_msa_ldi_h CODE_FOR_msa_ldiv8hi
15618 #define CODE_FOR_msa_ldi_w CODE_FOR_msa_ldiv4si
15619 #define CODE_FOR_msa_ldi_d CODE_FOR_msa_ldiv2di
15621 static const struct mips_builtin_description mips_builtins
[] = {
15622 #define MIPS_GET_FCSR 0
15623 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
15624 #define MIPS_SET_FCSR 1
15625 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
15627 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15628 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15629 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15630 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15631 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
15632 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
15633 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
15634 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
15636 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
15637 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15638 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15639 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15640 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15642 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
15643 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
15644 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15645 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
15646 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
15647 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15649 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
15650 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
15651 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15652 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
15653 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
15654 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15656 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
15658 /* Built-in functions for the SB-1 processor. */
15659 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
15661 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
15662 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15663 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15664 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15665 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15666 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15667 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15668 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15669 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15670 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15671 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15672 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15673 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15674 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15675 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
15676 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
15677 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
15678 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
15679 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
15680 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
15681 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
15682 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
15683 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
15684 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15685 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15686 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15687 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15688 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15689 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15690 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15691 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15692 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
15693 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15694 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15695 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15696 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
15697 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15698 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15699 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15700 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
15701 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
15702 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15703 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
15704 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
15705 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
15706 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15707 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
15708 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
15709 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15710 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15711 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15712 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15713 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15714 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15715 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15716 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15717 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15718 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15719 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15720 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15721 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
15722 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
15723 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15724 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15725 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15726 BPOSGE_BUILTIN (32, dsp
),
15728 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
15729 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
15730 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15731 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15732 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15733 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15734 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15735 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15736 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15737 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15738 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15739 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15740 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15741 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15742 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15743 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15744 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
15745 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
15746 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
15747 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15748 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
15749 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
15750 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
15751 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15752 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15753 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15754 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15755 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15756 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15757 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15758 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15759 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15760 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15761 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15762 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15764 /* Built-in functions for the DSP ASE (32-bit only). */
15765 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15766 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15767 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15768 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15769 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15770 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15771 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15772 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15773 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15774 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15775 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15776 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15777 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15778 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15779 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15780 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15781 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15782 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15783 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15784 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
15785 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
15786 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15787 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
15788 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15789 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
15790 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
15791 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
15793 /* Built-in functions for the DSP ASE (64-bit only). */
15794 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
15796 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
15797 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15798 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15799 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15800 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15801 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15802 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15803 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15804 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15805 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15807 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
15808 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
15809 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
15810 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
15811 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15812 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15813 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15814 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15815 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15816 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15817 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
15818 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
15819 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15820 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15821 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15822 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15823 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
15824 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15825 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15826 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15827 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
15828 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15829 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15830 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15831 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15832 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15833 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15834 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15835 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15836 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15837 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15838 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15839 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15840 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15841 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15842 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15843 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15844 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15845 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
15846 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
15847 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15848 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15849 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15850 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15851 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15852 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15853 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15854 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15855 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
15856 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15857 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15858 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15859 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15860 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
15861 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
15862 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15863 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15864 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15865 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
15866 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15867 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
15868 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
15869 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15870 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15871 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15872 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15873 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15874 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15875 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15876 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15877 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15878 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15879 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15880 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15881 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15882 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15883 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15884 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15885 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15886 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15887 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15888 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15889 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
15890 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
15891 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15892 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15893 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15894 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15895 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15896 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15897 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15898 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15899 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15900 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15901 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15902 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15903 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15904 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15905 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15906 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15908 /* Sundry other built-in functions. */
15909 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
),
15911 /* Built-in functions for MSA. */
15912 MSA_BUILTIN (sll_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15913 MSA_BUILTIN (sll_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15914 MSA_BUILTIN (sll_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15915 MSA_BUILTIN (sll_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15916 MSA_BUILTIN (slli_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15917 MSA_BUILTIN (slli_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15918 MSA_BUILTIN (slli_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15919 MSA_BUILTIN (slli_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15920 MSA_BUILTIN (sra_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15921 MSA_BUILTIN (sra_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15922 MSA_BUILTIN (sra_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15923 MSA_BUILTIN (sra_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15924 MSA_BUILTIN (srai_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15925 MSA_BUILTIN (srai_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15926 MSA_BUILTIN (srai_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15927 MSA_BUILTIN (srai_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15928 MSA_BUILTIN (srar_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15929 MSA_BUILTIN (srar_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15930 MSA_BUILTIN (srar_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15931 MSA_BUILTIN (srar_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15932 MSA_BUILTIN (srari_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15933 MSA_BUILTIN (srari_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15934 MSA_BUILTIN (srari_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15935 MSA_BUILTIN (srari_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15936 MSA_BUILTIN (srl_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15937 MSA_BUILTIN (srl_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15938 MSA_BUILTIN (srl_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15939 MSA_BUILTIN (srl_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15940 MSA_BUILTIN (srli_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15941 MSA_BUILTIN (srli_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15942 MSA_BUILTIN (srli_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15943 MSA_BUILTIN (srli_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15944 MSA_BUILTIN (srlr_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15945 MSA_BUILTIN (srlr_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15946 MSA_BUILTIN (srlr_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15947 MSA_BUILTIN (srlr_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15948 MSA_BUILTIN (srlri_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15949 MSA_BUILTIN (srlri_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15950 MSA_BUILTIN (srlri_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15951 MSA_BUILTIN (srlri_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15952 MSA_BUILTIN (bclr_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15953 MSA_BUILTIN (bclr_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15954 MSA_BUILTIN (bclr_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15955 MSA_BUILTIN (bclr_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15956 MSA_BUILTIN (bclri_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15957 MSA_BUILTIN (bclri_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15958 MSA_BUILTIN (bclri_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15959 MSA_BUILTIN (bclri_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15960 MSA_BUILTIN (bset_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15961 MSA_BUILTIN (bset_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15962 MSA_BUILTIN (bset_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15963 MSA_BUILTIN (bset_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15964 MSA_BUILTIN (bseti_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15965 MSA_BUILTIN (bseti_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15966 MSA_BUILTIN (bseti_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15967 MSA_BUILTIN (bseti_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15968 MSA_BUILTIN (bneg_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15969 MSA_BUILTIN (bneg_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15970 MSA_BUILTIN (bneg_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15971 MSA_BUILTIN (bneg_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15972 MSA_BUILTIN (bnegi_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15973 MSA_BUILTIN (bnegi_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15974 MSA_BUILTIN (bnegi_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15975 MSA_BUILTIN (bnegi_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15976 MSA_BUILTIN (binsl_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
15977 MSA_BUILTIN (binsl_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI
),
15978 MSA_BUILTIN (binsl_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI
),
15979 MSA_BUILTIN (binsl_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI
),
15980 MSA_BUILTIN (binsli_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
15981 MSA_BUILTIN (binsli_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI
),
15982 MSA_BUILTIN (binsli_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI
),
15983 MSA_BUILTIN (binsli_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI
),
15984 MSA_BUILTIN (binsr_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
15985 MSA_BUILTIN (binsr_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI
),
15986 MSA_BUILTIN (binsr_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI
),
15987 MSA_BUILTIN (binsr_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI
),
15988 MSA_BUILTIN (binsri_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
15989 MSA_BUILTIN (binsri_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI
),
15990 MSA_BUILTIN (binsri_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI
),
15991 MSA_BUILTIN (binsri_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI
),
15992 MSA_BUILTIN (addv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15993 MSA_BUILTIN (addv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15994 MSA_BUILTIN (addv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15995 MSA_BUILTIN (addv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15996 MSA_BUILTIN (addvi_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15997 MSA_BUILTIN (addvi_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15998 MSA_BUILTIN (addvi_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15999 MSA_BUILTIN (addvi_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16000 MSA_BUILTIN (subv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16001 MSA_BUILTIN (subv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16002 MSA_BUILTIN (subv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16003 MSA_BUILTIN (subv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16004 MSA_BUILTIN (subvi_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16005 MSA_BUILTIN (subvi_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16006 MSA_BUILTIN (subvi_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16007 MSA_BUILTIN (subvi_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16008 MSA_BUILTIN (max_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16009 MSA_BUILTIN (max_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16010 MSA_BUILTIN (max_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16011 MSA_BUILTIN (max_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16012 MSA_BUILTIN (maxi_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16013 MSA_BUILTIN (maxi_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16014 MSA_BUILTIN (maxi_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16015 MSA_BUILTIN (maxi_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16016 MSA_BUILTIN (max_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16017 MSA_BUILTIN (max_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16018 MSA_BUILTIN (max_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16019 MSA_BUILTIN (max_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16020 MSA_BUILTIN (maxi_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16021 MSA_BUILTIN (maxi_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
16022 MSA_BUILTIN (maxi_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
16023 MSA_BUILTIN (maxi_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
16024 MSA_BUILTIN (min_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16025 MSA_BUILTIN (min_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16026 MSA_BUILTIN (min_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16027 MSA_BUILTIN (min_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16028 MSA_BUILTIN (mini_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16029 MSA_BUILTIN (mini_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16030 MSA_BUILTIN (mini_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16031 MSA_BUILTIN (mini_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16032 MSA_BUILTIN (min_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16033 MSA_BUILTIN (min_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16034 MSA_BUILTIN (min_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16035 MSA_BUILTIN (min_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16036 MSA_BUILTIN (mini_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16037 MSA_BUILTIN (mini_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
16038 MSA_BUILTIN (mini_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
16039 MSA_BUILTIN (mini_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
16040 MSA_BUILTIN (max_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16041 MSA_BUILTIN (max_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16042 MSA_BUILTIN (max_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16043 MSA_BUILTIN (max_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16044 MSA_BUILTIN (min_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16045 MSA_BUILTIN (min_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16046 MSA_BUILTIN (min_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16047 MSA_BUILTIN (min_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16048 MSA_BUILTIN (ceq_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16049 MSA_BUILTIN (ceq_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16050 MSA_BUILTIN (ceq_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16051 MSA_BUILTIN (ceq_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16052 MSA_BUILTIN (ceqi_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16053 MSA_BUILTIN (ceqi_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16054 MSA_BUILTIN (ceqi_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16055 MSA_BUILTIN (ceqi_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16056 MSA_BUILTIN (clt_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16057 MSA_BUILTIN (clt_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16058 MSA_BUILTIN (clt_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16059 MSA_BUILTIN (clt_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16060 MSA_BUILTIN (clti_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16061 MSA_BUILTIN (clti_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16062 MSA_BUILTIN (clti_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16063 MSA_BUILTIN (clti_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16064 MSA_BUILTIN (clt_u_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16065 MSA_BUILTIN (clt_u_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16066 MSA_BUILTIN (clt_u_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16067 MSA_BUILTIN (clt_u_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16068 MSA_BUILTIN (clti_u_b
, MIPS_V16QI_FTYPE_UV16QI_UQI
),
16069 MSA_BUILTIN (clti_u_h
, MIPS_V8HI_FTYPE_UV8HI_UQI
),
16070 MSA_BUILTIN (clti_u_w
, MIPS_V4SI_FTYPE_UV4SI_UQI
),
16071 MSA_BUILTIN (clti_u_d
, MIPS_V2DI_FTYPE_UV2DI_UQI
),
16072 MSA_BUILTIN (cle_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16073 MSA_BUILTIN (cle_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16074 MSA_BUILTIN (cle_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16075 MSA_BUILTIN (cle_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16076 MSA_BUILTIN (clei_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16077 MSA_BUILTIN (clei_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16078 MSA_BUILTIN (clei_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16079 MSA_BUILTIN (clei_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16080 MSA_BUILTIN (cle_u_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16081 MSA_BUILTIN (cle_u_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16082 MSA_BUILTIN (cle_u_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16083 MSA_BUILTIN (cle_u_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16084 MSA_BUILTIN (clei_u_b
, MIPS_V16QI_FTYPE_UV16QI_UQI
),
16085 MSA_BUILTIN (clei_u_h
, MIPS_V8HI_FTYPE_UV8HI_UQI
),
16086 MSA_BUILTIN (clei_u_w
, MIPS_V4SI_FTYPE_UV4SI_UQI
),
16087 MSA_BUILTIN (clei_u_d
, MIPS_V2DI_FTYPE_UV2DI_UQI
),
16088 MSA_BUILTIN (ld_b
, MIPS_V16QI_FTYPE_CVPOINTER_SI
),
16089 MSA_BUILTIN (ld_h
, MIPS_V8HI_FTYPE_CVPOINTER_SI
),
16090 MSA_BUILTIN (ld_w
, MIPS_V4SI_FTYPE_CVPOINTER_SI
),
16091 MSA_BUILTIN (ld_d
, MIPS_V2DI_FTYPE_CVPOINTER_SI
),
16092 MSA_NO_TARGET_BUILTIN (st_b
, MIPS_VOID_FTYPE_V16QI_CVPOINTER_SI
),
16093 MSA_NO_TARGET_BUILTIN (st_h
, MIPS_VOID_FTYPE_V8HI_CVPOINTER_SI
),
16094 MSA_NO_TARGET_BUILTIN (st_w
, MIPS_VOID_FTYPE_V4SI_CVPOINTER_SI
),
16095 MSA_NO_TARGET_BUILTIN (st_d
, MIPS_VOID_FTYPE_V2DI_CVPOINTER_SI
),
16096 MSA_BUILTIN (sat_s_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16097 MSA_BUILTIN (sat_s_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16098 MSA_BUILTIN (sat_s_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16099 MSA_BUILTIN (sat_s_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16100 MSA_BUILTIN (sat_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16101 MSA_BUILTIN (sat_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
16102 MSA_BUILTIN (sat_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
16103 MSA_BUILTIN (sat_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
16104 MSA_BUILTIN (add_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16105 MSA_BUILTIN (add_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16106 MSA_BUILTIN (add_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16107 MSA_BUILTIN (add_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16108 MSA_BUILTIN (adds_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16109 MSA_BUILTIN (adds_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16110 MSA_BUILTIN (adds_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16111 MSA_BUILTIN (adds_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16112 MSA_BUILTIN (adds_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16113 MSA_BUILTIN (adds_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16114 MSA_BUILTIN (adds_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16115 MSA_BUILTIN (adds_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16116 MSA_BUILTIN (adds_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16117 MSA_BUILTIN (adds_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16118 MSA_BUILTIN (adds_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16119 MSA_BUILTIN (adds_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16120 MSA_BUILTIN (ave_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16121 MSA_BUILTIN (ave_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16122 MSA_BUILTIN (ave_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16123 MSA_BUILTIN (ave_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16124 MSA_BUILTIN (ave_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16125 MSA_BUILTIN (ave_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16126 MSA_BUILTIN (ave_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16127 MSA_BUILTIN (ave_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16128 MSA_BUILTIN (aver_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16129 MSA_BUILTIN (aver_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16130 MSA_BUILTIN (aver_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16131 MSA_BUILTIN (aver_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16132 MSA_BUILTIN (aver_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16133 MSA_BUILTIN (aver_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16134 MSA_BUILTIN (aver_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16135 MSA_BUILTIN (aver_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16136 MSA_BUILTIN (subs_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16137 MSA_BUILTIN (subs_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16138 MSA_BUILTIN (subs_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16139 MSA_BUILTIN (subs_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16140 MSA_BUILTIN (subs_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16141 MSA_BUILTIN (subs_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16142 MSA_BUILTIN (subs_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16143 MSA_BUILTIN (subs_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16144 MSA_BUILTIN (subsuu_s_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16145 MSA_BUILTIN (subsuu_s_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16146 MSA_BUILTIN (subsuu_s_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16147 MSA_BUILTIN (subsuu_s_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16148 MSA_BUILTIN (subsus_u_b
, MIPS_UV16QI_FTYPE_UV16QI_V16QI
),
16149 MSA_BUILTIN (subsus_u_h
, MIPS_UV8HI_FTYPE_UV8HI_V8HI
),
16150 MSA_BUILTIN (subsus_u_w
, MIPS_UV4SI_FTYPE_UV4SI_V4SI
),
16151 MSA_BUILTIN (subsus_u_d
, MIPS_UV2DI_FTYPE_UV2DI_V2DI
),
16152 MSA_BUILTIN (asub_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16153 MSA_BUILTIN (asub_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16154 MSA_BUILTIN (asub_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16155 MSA_BUILTIN (asub_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16156 MSA_BUILTIN (asub_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16157 MSA_BUILTIN (asub_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16158 MSA_BUILTIN (asub_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16159 MSA_BUILTIN (asub_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16160 MSA_BUILTIN (mulv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16161 MSA_BUILTIN (mulv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16162 MSA_BUILTIN (mulv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16163 MSA_BUILTIN (mulv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16164 MSA_BUILTIN (maddv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16165 MSA_BUILTIN (maddv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16166 MSA_BUILTIN (maddv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16167 MSA_BUILTIN (maddv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16168 MSA_BUILTIN (msubv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16169 MSA_BUILTIN (msubv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16170 MSA_BUILTIN (msubv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16171 MSA_BUILTIN (msubv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16172 MSA_BUILTIN (div_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16173 MSA_BUILTIN (div_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16174 MSA_BUILTIN (div_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16175 MSA_BUILTIN (div_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16176 MSA_BUILTIN (div_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16177 MSA_BUILTIN (div_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16178 MSA_BUILTIN (div_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16179 MSA_BUILTIN (div_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16180 MSA_BUILTIN (hadd_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16181 MSA_BUILTIN (hadd_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16182 MSA_BUILTIN (hadd_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16183 MSA_BUILTIN (hadd_u_h
, MIPS_UV8HI_FTYPE_UV16QI_UV16QI
),
16184 MSA_BUILTIN (hadd_u_w
, MIPS_UV4SI_FTYPE_UV8HI_UV8HI
),
16185 MSA_BUILTIN (hadd_u_d
, MIPS_UV2DI_FTYPE_UV4SI_UV4SI
),
16186 MSA_BUILTIN (hsub_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16187 MSA_BUILTIN (hsub_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16188 MSA_BUILTIN (hsub_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16189 MSA_BUILTIN (hsub_u_h
, MIPS_V8HI_FTYPE_UV16QI_UV16QI
),
16190 MSA_BUILTIN (hsub_u_w
, MIPS_V4SI_FTYPE_UV8HI_UV8HI
),
16191 MSA_BUILTIN (hsub_u_d
, MIPS_V2DI_FTYPE_UV4SI_UV4SI
),
16192 MSA_BUILTIN (mod_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16193 MSA_BUILTIN (mod_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16194 MSA_BUILTIN (mod_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16195 MSA_BUILTIN (mod_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16196 MSA_BUILTIN (mod_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16197 MSA_BUILTIN (mod_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16198 MSA_BUILTIN (mod_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16199 MSA_BUILTIN (mod_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16200 MSA_BUILTIN (dotp_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16201 MSA_BUILTIN (dotp_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16202 MSA_BUILTIN (dotp_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16203 MSA_BUILTIN (dotp_u_h
, MIPS_UV8HI_FTYPE_UV16QI_UV16QI
),
16204 MSA_BUILTIN (dotp_u_w
, MIPS_UV4SI_FTYPE_UV8HI_UV8HI
),
16205 MSA_BUILTIN (dotp_u_d
, MIPS_UV2DI_FTYPE_UV4SI_UV4SI
),
16206 MSA_BUILTIN (dpadd_s_h
, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI
),
16207 MSA_BUILTIN (dpadd_s_w
, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI
),
16208 MSA_BUILTIN (dpadd_s_d
, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI
),
16209 MSA_BUILTIN (dpadd_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV16QI_UV16QI
),
16210 MSA_BUILTIN (dpadd_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV8HI_UV8HI
),
16211 MSA_BUILTIN (dpadd_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV4SI_UV4SI
),
16212 MSA_BUILTIN (dpsub_s_h
, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI
),
16213 MSA_BUILTIN (dpsub_s_w
, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI
),
16214 MSA_BUILTIN (dpsub_s_d
, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI
),
16215 MSA_BUILTIN (dpsub_u_h
, MIPS_V8HI_FTYPE_V8HI_UV16QI_UV16QI
),
16216 MSA_BUILTIN (dpsub_u_w
, MIPS_V4SI_FTYPE_V4SI_UV8HI_UV8HI
),
16217 MSA_BUILTIN (dpsub_u_d
, MIPS_V2DI_FTYPE_V2DI_UV4SI_UV4SI
),
16218 MSA_BUILTIN (sld_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_SI
),
16219 MSA_BUILTIN (sld_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_SI
),
16220 MSA_BUILTIN (sld_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_SI
),
16221 MSA_BUILTIN (sld_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_SI
),
16222 MSA_BUILTIN (sldi_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_UQI
),
16223 MSA_BUILTIN (sldi_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_UQI
),
16224 MSA_BUILTIN (sldi_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_UQI
),
16225 MSA_BUILTIN (sldi_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_UQI
),
16226 MSA_BUILTIN (splat_b
, MIPS_V16QI_FTYPE_V16QI_SI
),
16227 MSA_BUILTIN (splat_h
, MIPS_V8HI_FTYPE_V8HI_SI
),
16228 MSA_BUILTIN (splat_w
, MIPS_V4SI_FTYPE_V4SI_SI
),
16229 MSA_BUILTIN (splat_d
, MIPS_V2DI_FTYPE_V2DI_SI
),
16230 MSA_BUILTIN (splati_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16231 MSA_BUILTIN (splati_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16232 MSA_BUILTIN (splati_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16233 MSA_BUILTIN (splati_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16234 MSA_BUILTIN (pckev_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16235 MSA_BUILTIN (pckev_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16236 MSA_BUILTIN (pckev_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16237 MSA_BUILTIN (pckev_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16238 MSA_BUILTIN (pckod_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16239 MSA_BUILTIN (pckod_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16240 MSA_BUILTIN (pckod_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16241 MSA_BUILTIN (pckod_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16242 MSA_BUILTIN (ilvl_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16243 MSA_BUILTIN (ilvl_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16244 MSA_BUILTIN (ilvl_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16245 MSA_BUILTIN (ilvl_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16246 MSA_BUILTIN (ilvr_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16247 MSA_BUILTIN (ilvr_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16248 MSA_BUILTIN (ilvr_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16249 MSA_BUILTIN (ilvr_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16250 MSA_BUILTIN (ilvev_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16251 MSA_BUILTIN (ilvev_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16252 MSA_BUILTIN (ilvev_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16253 MSA_BUILTIN (ilvev_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16254 MSA_BUILTIN (ilvod_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16255 MSA_BUILTIN (ilvod_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16256 MSA_BUILTIN (ilvod_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16257 MSA_BUILTIN (ilvod_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16258 MSA_BUILTIN (vshf_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16259 MSA_BUILTIN (vshf_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16260 MSA_BUILTIN (vshf_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16261 MSA_BUILTIN (vshf_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16262 MSA_BUILTIN (and_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16263 MSA_BUILTIN (andi_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16264 MSA_BUILTIN (or_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16265 MSA_BUILTIN (ori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16266 MSA_BUILTIN (nor_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16267 MSA_BUILTIN (nori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16268 MSA_BUILTIN (xor_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16269 MSA_BUILTIN (xori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16270 MSA_BUILTIN (bmnz_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16271 MSA_BUILTIN (bmnzi_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16272 MSA_BUILTIN (bmz_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16273 MSA_BUILTIN (bmzi_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16274 MSA_BUILTIN (bsel_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16275 MSA_BUILTIN (bseli_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16276 MSA_BUILTIN (shf_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16277 MSA_BUILTIN (shf_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16278 MSA_BUILTIN (shf_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16279 MSA_BUILTIN_TEST_BRANCH (bnz_v
, MIPS_SI_FTYPE_UV16QI
),
16280 MSA_BUILTIN_TEST_BRANCH (bz_v
, MIPS_SI_FTYPE_UV16QI
),
16281 MSA_BUILTIN (fill_b
, MIPS_V16QI_FTYPE_SI
),
16282 MSA_BUILTIN (fill_h
, MIPS_V8HI_FTYPE_SI
),
16283 MSA_BUILTIN (fill_w
, MIPS_V4SI_FTYPE_SI
),
16284 MSA_BUILTIN (fill_d
, MIPS_V2DI_FTYPE_DI
),
16285 MSA_BUILTIN (pcnt_b
, MIPS_V16QI_FTYPE_V16QI
),
16286 MSA_BUILTIN (pcnt_h
, MIPS_V8HI_FTYPE_V8HI
),
16287 MSA_BUILTIN (pcnt_w
, MIPS_V4SI_FTYPE_V4SI
),
16288 MSA_BUILTIN (pcnt_d
, MIPS_V2DI_FTYPE_V2DI
),
16289 MSA_BUILTIN (nloc_b
, MIPS_V16QI_FTYPE_V16QI
),
16290 MSA_BUILTIN (nloc_h
, MIPS_V8HI_FTYPE_V8HI
),
16291 MSA_BUILTIN (nloc_w
, MIPS_V4SI_FTYPE_V4SI
),
16292 MSA_BUILTIN (nloc_d
, MIPS_V2DI_FTYPE_V2DI
),
16293 MSA_BUILTIN (nlzc_b
, MIPS_V16QI_FTYPE_V16QI
),
16294 MSA_BUILTIN (nlzc_h
, MIPS_V8HI_FTYPE_V8HI
),
16295 MSA_BUILTIN (nlzc_w
, MIPS_V4SI_FTYPE_V4SI
),
16296 MSA_BUILTIN (nlzc_d
, MIPS_V2DI_FTYPE_V2DI
),
16297 MSA_BUILTIN (copy_s_b
, MIPS_SI_FTYPE_V16QI_UQI
),
16298 MSA_BUILTIN (copy_s_h
, MIPS_SI_FTYPE_V8HI_UQI
),
16299 MSA_BUILTIN (copy_s_w
, MIPS_SI_FTYPE_V4SI_UQI
),
16300 MSA_BUILTIN (copy_s_d
, MIPS_DI_FTYPE_V2DI_UQI
),
16301 MSA_BUILTIN (copy_u_b
, MIPS_USI_FTYPE_V16QI_UQI
),
16302 MSA_BUILTIN (copy_u_h
, MIPS_USI_FTYPE_V8HI_UQI
),
16303 MSA_BUILTIN_REMAP (copy_u_w
, copy_s_w
, MIPS_USI_FTYPE_V4SI_UQI
),
16304 MSA_BUILTIN_REMAP (copy_u_d
, copy_s_d
, MIPS_UDI_FTYPE_V2DI_UQI
),
16305 MSA_BUILTIN (insert_b
, MIPS_V16QI_FTYPE_V16QI_UQI_SI
),
16306 MSA_BUILTIN (insert_h
, MIPS_V8HI_FTYPE_V8HI_UQI_SI
),
16307 MSA_BUILTIN (insert_w
, MIPS_V4SI_FTYPE_V4SI_UQI_SI
),
16308 MSA_BUILTIN (insert_d
, MIPS_V2DI_FTYPE_V2DI_UQI_DI
),
16309 MSA_BUILTIN (insve_b
, MIPS_V16QI_FTYPE_V16QI_UQI_V16QI
),
16310 MSA_BUILTIN (insve_h
, MIPS_V8HI_FTYPE_V8HI_UQI_V8HI
),
16311 MSA_BUILTIN (insve_w
, MIPS_V4SI_FTYPE_V4SI_UQI_V4SI
),
16312 MSA_BUILTIN (insve_d
, MIPS_V2DI_FTYPE_V2DI_UQI_V2DI
),
16313 MSA_BUILTIN_TEST_BRANCH (bnz_b
, MIPS_SI_FTYPE_UV16QI
),
16314 MSA_BUILTIN_TEST_BRANCH (bnz_h
, MIPS_SI_FTYPE_UV8HI
),
16315 MSA_BUILTIN_TEST_BRANCH (bnz_w
, MIPS_SI_FTYPE_UV4SI
),
16316 MSA_BUILTIN_TEST_BRANCH (bnz_d
, MIPS_SI_FTYPE_UV2DI
),
16317 MSA_BUILTIN_TEST_BRANCH (bz_b
, MIPS_SI_FTYPE_UV16QI
),
16318 MSA_BUILTIN_TEST_BRANCH (bz_h
, MIPS_SI_FTYPE_UV8HI
),
16319 MSA_BUILTIN_TEST_BRANCH (bz_w
, MIPS_SI_FTYPE_UV4SI
),
16320 MSA_BUILTIN_TEST_BRANCH (bz_d
, MIPS_SI_FTYPE_UV2DI
),
16321 MSA_BUILTIN (ldi_b
, MIPS_V16QI_FTYPE_HI
),
16322 MSA_BUILTIN (ldi_h
, MIPS_V8HI_FTYPE_HI
),
16323 MSA_BUILTIN (ldi_w
, MIPS_V4SI_FTYPE_HI
),
16324 MSA_BUILTIN (ldi_d
, MIPS_V2DI_FTYPE_HI
),
16325 MSA_BUILTIN (fcaf_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16326 MSA_BUILTIN (fcaf_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16327 MSA_BUILTIN (fcor_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16328 MSA_BUILTIN (fcor_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16329 MSA_BUILTIN (fcun_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16330 MSA_BUILTIN (fcun_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16331 MSA_BUILTIN (fcune_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16332 MSA_BUILTIN (fcune_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16333 MSA_BUILTIN (fcueq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16334 MSA_BUILTIN (fcueq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16335 MSA_BUILTIN (fceq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16336 MSA_BUILTIN (fceq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16337 MSA_BUILTIN (fcne_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16338 MSA_BUILTIN (fcne_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16339 MSA_BUILTIN (fclt_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16340 MSA_BUILTIN (fclt_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16341 MSA_BUILTIN (fcult_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16342 MSA_BUILTIN (fcult_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16343 MSA_BUILTIN (fcle_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16344 MSA_BUILTIN (fcle_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16345 MSA_BUILTIN (fcule_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16346 MSA_BUILTIN (fcule_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16347 MSA_BUILTIN (fsaf_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16348 MSA_BUILTIN (fsaf_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16349 MSA_BUILTIN (fsor_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16350 MSA_BUILTIN (fsor_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16351 MSA_BUILTIN (fsun_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16352 MSA_BUILTIN (fsun_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16353 MSA_BUILTIN (fsune_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16354 MSA_BUILTIN (fsune_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16355 MSA_BUILTIN (fsueq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16356 MSA_BUILTIN (fsueq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16357 MSA_BUILTIN (fseq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16358 MSA_BUILTIN (fseq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16359 MSA_BUILTIN (fsne_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16360 MSA_BUILTIN (fsne_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16361 MSA_BUILTIN (fslt_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16362 MSA_BUILTIN (fslt_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16363 MSA_BUILTIN (fsult_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16364 MSA_BUILTIN (fsult_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16365 MSA_BUILTIN (fsle_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16366 MSA_BUILTIN (fsle_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16367 MSA_BUILTIN (fsule_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16368 MSA_BUILTIN (fsule_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16369 MSA_BUILTIN (fadd_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16370 MSA_BUILTIN (fadd_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16371 MSA_BUILTIN (fsub_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16372 MSA_BUILTIN (fsub_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16373 MSA_BUILTIN (fmul_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16374 MSA_BUILTIN (fmul_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16375 MSA_BUILTIN (fdiv_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16376 MSA_BUILTIN (fdiv_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16377 MSA_BUILTIN (fmadd_w
, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF
),
16378 MSA_BUILTIN (fmadd_d
, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF
),
16379 MSA_BUILTIN (fmsub_w
, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF
),
16380 MSA_BUILTIN (fmsub_d
, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF
),
16381 MSA_BUILTIN (fexp2_w
, MIPS_V4SF_FTYPE_V4SF_V4SI
),
16382 MSA_BUILTIN (fexp2_d
, MIPS_V2DF_FTYPE_V2DF_V2DI
),
16383 MSA_BUILTIN (fexdo_h
, MIPS_V8HI_FTYPE_V4SF_V4SF
),
16384 MSA_BUILTIN (fexdo_w
, MIPS_V4SF_FTYPE_V2DF_V2DF
),
16385 MSA_BUILTIN (ftq_h
, MIPS_V8HI_FTYPE_V4SF_V4SF
),
16386 MSA_BUILTIN (ftq_w
, MIPS_V4SI_FTYPE_V2DF_V2DF
),
16387 MSA_BUILTIN (fmin_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16388 MSA_BUILTIN (fmin_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16389 MSA_BUILTIN (fmin_a_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16390 MSA_BUILTIN (fmin_a_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16391 MSA_BUILTIN (fmax_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16392 MSA_BUILTIN (fmax_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16393 MSA_BUILTIN (fmax_a_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16394 MSA_BUILTIN (fmax_a_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16395 MSA_BUILTIN (mul_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16396 MSA_BUILTIN (mul_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16397 MSA_BUILTIN (mulr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16398 MSA_BUILTIN (mulr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16399 MSA_BUILTIN (madd_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16400 MSA_BUILTIN (madd_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16401 MSA_BUILTIN (maddr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16402 MSA_BUILTIN (maddr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16403 MSA_BUILTIN (msub_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16404 MSA_BUILTIN (msub_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16405 MSA_BUILTIN (msubr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16406 MSA_BUILTIN (msubr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16407 MSA_BUILTIN (fclass_w
, MIPS_V4SI_FTYPE_V4SF
),
16408 MSA_BUILTIN (fclass_d
, MIPS_V2DI_FTYPE_V2DF
),
16409 MSA_BUILTIN (fsqrt_w
, MIPS_V4SF_FTYPE_V4SF
),
16410 MSA_BUILTIN (fsqrt_d
, MIPS_V2DF_FTYPE_V2DF
),
16411 MSA_BUILTIN (frcp_w
, MIPS_V4SF_FTYPE_V4SF
),
16412 MSA_BUILTIN (frcp_d
, MIPS_V2DF_FTYPE_V2DF
),
16413 MSA_BUILTIN (frint_w
, MIPS_V4SF_FTYPE_V4SF
),
16414 MSA_BUILTIN (frint_d
, MIPS_V2DF_FTYPE_V2DF
),
16415 MSA_BUILTIN (frsqrt_w
, MIPS_V4SF_FTYPE_V4SF
),
16416 MSA_BUILTIN (frsqrt_d
, MIPS_V2DF_FTYPE_V2DF
),
16417 MSA_BUILTIN (flog2_w
, MIPS_V4SF_FTYPE_V4SF
),
16418 MSA_BUILTIN (flog2_d
, MIPS_V2DF_FTYPE_V2DF
),
16419 MSA_BUILTIN (fexupl_w
, MIPS_V4SF_FTYPE_V8HI
),
16420 MSA_BUILTIN (fexupl_d
, MIPS_V2DF_FTYPE_V4SF
),
16421 MSA_BUILTIN (fexupr_w
, MIPS_V4SF_FTYPE_V8HI
),
16422 MSA_BUILTIN (fexupr_d
, MIPS_V2DF_FTYPE_V4SF
),
16423 MSA_BUILTIN (ffql_w
, MIPS_V4SF_FTYPE_V8HI
),
16424 MSA_BUILTIN (ffql_d
, MIPS_V2DF_FTYPE_V4SI
),
16425 MSA_BUILTIN (ffqr_w
, MIPS_V4SF_FTYPE_V8HI
),
16426 MSA_BUILTIN (ffqr_d
, MIPS_V2DF_FTYPE_V4SI
),
16427 MSA_BUILTIN (ftint_s_w
, MIPS_V4SI_FTYPE_V4SF
),
16428 MSA_BUILTIN (ftint_s_d
, MIPS_V2DI_FTYPE_V2DF
),
16429 MSA_BUILTIN (ftint_u_w
, MIPS_UV4SI_FTYPE_V4SF
),
16430 MSA_BUILTIN (ftint_u_d
, MIPS_UV2DI_FTYPE_V2DF
),
16431 MSA_BUILTIN (ftrunc_s_w
, MIPS_V4SI_FTYPE_V4SF
),
16432 MSA_BUILTIN (ftrunc_s_d
, MIPS_V2DI_FTYPE_V2DF
),
16433 MSA_BUILTIN (ftrunc_u_w
, MIPS_UV4SI_FTYPE_V4SF
),
16434 MSA_BUILTIN (ftrunc_u_d
, MIPS_UV2DI_FTYPE_V2DF
),
16435 MSA_BUILTIN (ffint_s_w
, MIPS_V4SF_FTYPE_V4SI
),
16436 MSA_BUILTIN (ffint_s_d
, MIPS_V2DF_FTYPE_V2DI
),
16437 MSA_BUILTIN (ffint_u_w
, MIPS_V4SF_FTYPE_UV4SI
),
16438 MSA_BUILTIN (ffint_u_d
, MIPS_V2DF_FTYPE_UV2DI
),
16439 MSA_NO_TARGET_BUILTIN (ctcmsa
, MIPS_VOID_FTYPE_UQI_SI
),
16440 MSA_BUILTIN (cfcmsa
, MIPS_SI_FTYPE_UQI
),
16441 MSA_BUILTIN (move_v
, MIPS_V16QI_FTYPE_V16QI
),
16444 /* Index I is the function declaration for mips_builtins[I], or null if the
16445 function isn't defined on this target. */
16446 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
16447 /* Get the index I of the function declaration for mips_builtin_decls[I]
16448 using the instruction code or return null if not defined for the target. */
16449 static GTY(()) int mips_get_builtin_decl_index
[NUM_INSN_CODES
];
16451 /* MODE is a vector mode whose elements have type TYPE. Return the type
16452 of the vector itself. */
16455 mips_builtin_vector_type (tree type
, machine_mode mode
)
16457 static tree types
[2 * (int) MAX_MACHINE_MODE
];
16460 mode_index
= (int) mode
;
16462 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
16463 mode_index
+= MAX_MACHINE_MODE
;
16465 if (types
[mode_index
] == NULL_TREE
)
16466 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
16467 return types
[mode_index
];
16470 /* Return a type for 'const volatile void *'. */
16473 mips_build_cvpointer_type (void)
16477 if (cache
== NULL_TREE
)
16478 cache
= build_pointer_type (build_qualified_type
16480 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
16484 /* Source-level argument types. */
16485 #define MIPS_ATYPE_VOID void_type_node
16486 #define MIPS_ATYPE_INT integer_type_node
16487 #define MIPS_ATYPE_POINTER ptr_type_node
16488 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
16490 /* Standard mode-based argument types. */
16491 #define MIPS_ATYPE_QI intQI_type_node
16492 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
16493 #define MIPS_ATYPE_HI intHI_type_node
16494 #define MIPS_ATYPE_SI intSI_type_node
16495 #define MIPS_ATYPE_USI unsigned_intSI_type_node
16496 #define MIPS_ATYPE_DI intDI_type_node
16497 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
16498 #define MIPS_ATYPE_SF float_type_node
16499 #define MIPS_ATYPE_DF double_type_node
16501 /* Vector argument types. */
16502 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
16503 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
16504 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
16505 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
16506 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
16507 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
16509 #define MIPS_ATYPE_V2DI \
16510 mips_builtin_vector_type (long_long_integer_type_node, V2DImode)
16511 #define MIPS_ATYPE_V4SI mips_builtin_vector_type (intSI_type_node, V4SImode)
16512 #define MIPS_ATYPE_V8HI mips_builtin_vector_type (intHI_type_node, V8HImode)
16513 #define MIPS_ATYPE_V16QI mips_builtin_vector_type (intQI_type_node, V16QImode)
16514 #define MIPS_ATYPE_V2DF mips_builtin_vector_type (double_type_node, V2DFmode)
16515 #define MIPS_ATYPE_V4SF mips_builtin_vector_type (float_type_node, V4SFmode)
16517 #define MIPS_ATYPE_UV2DI \
16518 mips_builtin_vector_type (long_long_unsigned_type_node, V2DImode)
16519 #define MIPS_ATYPE_UV4SI \
16520 mips_builtin_vector_type (unsigned_intSI_type_node, V4SImode)
16521 #define MIPS_ATYPE_UV8HI \
16522 mips_builtin_vector_type (unsigned_intHI_type_node, V8HImode)
16523 #define MIPS_ATYPE_UV16QI \
16524 mips_builtin_vector_type (unsigned_intQI_type_node, V16QImode)
16526 #define MIPS_ATYPE_UV2SI \
16527 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
16528 #define MIPS_ATYPE_UV4HI \
16529 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
16530 #define MIPS_ATYPE_UV8QI \
16531 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
16533 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
16534 their associated MIPS_ATYPEs. */
16535 #define MIPS_FTYPE_ATYPES1(A, B) \
16536 MIPS_ATYPE_##A, MIPS_ATYPE_##B
16538 #define MIPS_FTYPE_ATYPES2(A, B, C) \
16539 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
16541 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
16542 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
16544 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
16545 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
16548 /* Return the function type associated with function prototype TYPE. */
16551 mips_build_function_type (enum mips_function_type type
)
16553 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
16555 if (types
[(int) type
] == NULL_TREE
)
16558 #define DEF_MIPS_FTYPE(NUM, ARGS) \
16559 case MIPS_FTYPE_NAME##NUM ARGS: \
16560 types[(int) type] \
16561 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
16564 #include "config/mips/mips-ftypes.def"
16565 #undef DEF_MIPS_FTYPE
16567 gcc_unreachable ();
16570 return types
[(int) type
];
16573 /* Implement TARGET_INIT_BUILTINS. */
16576 mips_init_builtins (void)
16578 const struct mips_builtin_description
*d
;
16581 /* Iterate through all of the bdesc arrays, initializing all of the
16582 builtin functions. */
16583 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
16585 d
= &mips_builtins
[i
];
16588 mips_builtin_decls
[i
]
16589 = add_builtin_function (d
->name
,
16590 mips_build_function_type (d
->function_type
),
16591 i
, BUILT_IN_MD
, NULL
, NULL
);
16592 mips_get_builtin_decl_index
[d
->icode
] = i
;
16597 /* Implement TARGET_BUILTIN_DECL. */
16600 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
16602 if (code
>= ARRAY_SIZE (mips_builtins
))
16603 return error_mark_node
;
16604 return mips_builtin_decls
[code
];
16607 /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION. */
16610 mips_builtin_vectorized_function (unsigned int fn
, tree type_out
, tree type_in
)
16612 machine_mode in_mode
, out_mode
;
16615 if (TREE_CODE (type_out
) != VECTOR_TYPE
16616 || TREE_CODE (type_in
) != VECTOR_TYPE
16620 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
16621 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
16622 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
16623 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
16625 /* INSN is the name of the associated instruction pattern, without
16626 the leading CODE_FOR_. */
16627 #define MIPS_GET_BUILTIN(INSN) \
16628 mips_builtin_decls[mips_get_builtin_decl_index[CODE_FOR_##INSN]]
16632 case BUILT_IN_SQRT
:
16633 if (out_mode
== DFmode
&& out_n
== 2
16634 && in_mode
== DFmode
&& in_n
== 2)
16635 return MIPS_GET_BUILTIN (msa_fsqrt_d
);
16637 case BUILT_IN_SQRTF
:
16638 if (out_mode
== SFmode
&& out_n
== 4
16639 && in_mode
== SFmode
&& in_n
== 4)
16640 return MIPS_GET_BUILTIN (msa_fsqrt_w
);
16649 /* Take argument ARGNO from EXP's argument list and convert it into
16650 an expand operand. Store the operand in *OP. */
16653 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
16654 unsigned int argno
)
16659 arg
= CALL_EXPR_ARG (exp
, argno
);
16660 value
= expand_normal (arg
);
16661 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
16664 /* Expand instruction ICODE as part of a built-in function sequence.
16665 Use the first NOPS elements of OPS as the instruction's operands.
16666 HAS_TARGET_P is true if operand 0 is a target; it is false if the
16667 instruction has no target.
16669 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
16672 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
16673 struct expand_operand
*ops
, bool has_target_p
)
16675 machine_mode imode
;
16676 int rangelo
= 0, rangehi
= 0, error_opno
= 0;
16681 /* The third operand of these instructions is in SImode, so we need to
16682 bring the corresponding builtin argument from QImode into SImode. */
16683 case CODE_FOR_loongson_pshufh
:
16684 case CODE_FOR_loongson_psllh
:
16685 case CODE_FOR_loongson_psllw
:
16686 case CODE_FOR_loongson_psrah
:
16687 case CODE_FOR_loongson_psraw
:
16688 case CODE_FOR_loongson_psrlh
:
16689 case CODE_FOR_loongson_psrlw
:
16690 gcc_assert (has_target_p
&& nops
== 3 && ops
[2].mode
== QImode
);
16691 sireg
= gen_reg_rtx (SImode
);
16692 emit_insn (gen_zero_extendqisi2 (sireg
,
16693 force_reg (QImode
, ops
[2].value
)));
16694 ops
[2].value
= sireg
;
16695 ops
[2].mode
= SImode
;
16698 case CODE_FOR_msa_addvi_b
:
16699 case CODE_FOR_msa_addvi_h
:
16700 case CODE_FOR_msa_addvi_w
:
16701 case CODE_FOR_msa_addvi_d
:
16702 case CODE_FOR_msa_clti_u_b
:
16703 case CODE_FOR_msa_clti_u_h
:
16704 case CODE_FOR_msa_clti_u_w
:
16705 case CODE_FOR_msa_clti_u_d
:
16706 case CODE_FOR_msa_clei_u_b
:
16707 case CODE_FOR_msa_clei_u_h
:
16708 case CODE_FOR_msa_clei_u_w
:
16709 case CODE_FOR_msa_clei_u_d
:
16710 case CODE_FOR_msa_maxi_u_b
:
16711 case CODE_FOR_msa_maxi_u_h
:
16712 case CODE_FOR_msa_maxi_u_w
:
16713 case CODE_FOR_msa_maxi_u_d
:
16714 case CODE_FOR_msa_mini_u_b
:
16715 case CODE_FOR_msa_mini_u_h
:
16716 case CODE_FOR_msa_mini_u_w
:
16717 case CODE_FOR_msa_mini_u_d
:
16718 case CODE_FOR_msa_subvi_b
:
16719 case CODE_FOR_msa_subvi_h
:
16720 case CODE_FOR_msa_subvi_w
:
16721 case CODE_FOR_msa_subvi_d
:
16722 gcc_assert (has_target_p
&& nops
== 3);
16723 /* We only generate a vector of constants iff the second argument
16724 is an immediate. We also validate the range of the immediate. */
16725 if (CONST_INT_P (ops
[2].value
))
16729 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16731 ops
[2].mode
= ops
[0].mode
;
16732 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16733 INTVAL (ops
[2].value
));
16740 case CODE_FOR_msa_ceqi_b
:
16741 case CODE_FOR_msa_ceqi_h
:
16742 case CODE_FOR_msa_ceqi_w
:
16743 case CODE_FOR_msa_ceqi_d
:
16744 case CODE_FOR_msa_clti_s_b
:
16745 case CODE_FOR_msa_clti_s_h
:
16746 case CODE_FOR_msa_clti_s_w
:
16747 case CODE_FOR_msa_clti_s_d
:
16748 case CODE_FOR_msa_clei_s_b
:
16749 case CODE_FOR_msa_clei_s_h
:
16750 case CODE_FOR_msa_clei_s_w
:
16751 case CODE_FOR_msa_clei_s_d
:
16752 case CODE_FOR_msa_maxi_s_b
:
16753 case CODE_FOR_msa_maxi_s_h
:
16754 case CODE_FOR_msa_maxi_s_w
:
16755 case CODE_FOR_msa_maxi_s_d
:
16756 case CODE_FOR_msa_mini_s_b
:
16757 case CODE_FOR_msa_mini_s_h
:
16758 case CODE_FOR_msa_mini_s_w
:
16759 case CODE_FOR_msa_mini_s_d
:
16760 gcc_assert (has_target_p
&& nops
== 3);
16761 /* We only generate a vector of constants iff the second argument
16762 is an immediate. We also validate the range of the immediate. */
16763 if (CONST_INT_P (ops
[2].value
))
16767 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16769 ops
[2].mode
= ops
[0].mode
;
16770 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16771 INTVAL (ops
[2].value
));
16778 case CODE_FOR_msa_andi_b
:
16779 case CODE_FOR_msa_ori_b
:
16780 case CODE_FOR_msa_nori_b
:
16781 case CODE_FOR_msa_xori_b
:
16782 gcc_assert (has_target_p
&& nops
== 3);
16783 if (!CONST_INT_P (ops
[2].value
))
16785 ops
[2].mode
= ops
[0].mode
;
16786 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16787 INTVAL (ops
[2].value
));
16790 case CODE_FOR_msa_bmzi_b
:
16791 case CODE_FOR_msa_bmnzi_b
:
16792 case CODE_FOR_msa_bseli_b
:
16793 gcc_assert (has_target_p
&& nops
== 4);
16794 if (!CONST_INT_P (ops
[3].value
))
16796 ops
[3].mode
= ops
[0].mode
;
16797 ops
[3].value
= mips_gen_const_int_vector (ops
[3].mode
,
16798 INTVAL (ops
[3].value
));
16801 case CODE_FOR_msa_fill_b
:
16802 case CODE_FOR_msa_fill_h
:
16803 case CODE_FOR_msa_fill_w
:
16804 case CODE_FOR_msa_fill_d
:
16805 /* Map the built-ins to vector fill operations. We need fix up the mode
16806 for the element being inserted. */
16807 gcc_assert (has_target_p
&& nops
== 2);
16808 imode
= GET_MODE_INNER (ops
[0].mode
);
16809 ops
[1].value
= lowpart_subreg (imode
, ops
[1].value
, ops
[1].mode
);
16810 ops
[1].mode
= imode
;
16813 case CODE_FOR_msa_ilvl_b
:
16814 case CODE_FOR_msa_ilvl_h
:
16815 case CODE_FOR_msa_ilvl_w
:
16816 case CODE_FOR_msa_ilvl_d
:
16817 case CODE_FOR_msa_ilvr_b
:
16818 case CODE_FOR_msa_ilvr_h
:
16819 case CODE_FOR_msa_ilvr_w
:
16820 case CODE_FOR_msa_ilvr_d
:
16821 case CODE_FOR_msa_ilvev_b
:
16822 case CODE_FOR_msa_ilvev_h
:
16823 case CODE_FOR_msa_ilvev_w
:
16824 case CODE_FOR_msa_ilvod_b
:
16825 case CODE_FOR_msa_ilvod_h
:
16826 case CODE_FOR_msa_ilvod_w
:
16827 case CODE_FOR_msa_pckev_b
:
16828 case CODE_FOR_msa_pckev_h
:
16829 case CODE_FOR_msa_pckev_w
:
16830 case CODE_FOR_msa_pckod_b
:
16831 case CODE_FOR_msa_pckod_h
:
16832 case CODE_FOR_msa_pckod_w
:
16833 /* Swap the operands 1 and 2 for interleave operations. Built-ins follow
16834 convention of ISA, which have op1 as higher component and op2 as lower
16835 component. However, the VEC_PERM op in tree and vec_concat in RTL
16836 expects first operand to be lower component, because of which this
16837 swap is needed for builtins. */
16838 gcc_assert (has_target_p
&& nops
== 3);
16839 std::swap (ops
[1], ops
[2]);
16842 case CODE_FOR_msa_slli_b
:
16843 case CODE_FOR_msa_slli_h
:
16844 case CODE_FOR_msa_slli_w
:
16845 case CODE_FOR_msa_slli_d
:
16846 case CODE_FOR_msa_srai_b
:
16847 case CODE_FOR_msa_srai_h
:
16848 case CODE_FOR_msa_srai_w
:
16849 case CODE_FOR_msa_srai_d
:
16850 case CODE_FOR_msa_srli_b
:
16851 case CODE_FOR_msa_srli_h
:
16852 case CODE_FOR_msa_srli_w
:
16853 case CODE_FOR_msa_srli_d
:
16854 gcc_assert (has_target_p
&& nops
== 3);
16855 if (CONST_INT_P (ops
[2].value
))
16858 rangehi
= GET_MODE_UNIT_BITSIZE (ops
[0].mode
) - 1;
16859 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16861 ops
[2].mode
= ops
[0].mode
;
16862 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16863 INTVAL (ops
[2].value
));
16870 case CODE_FOR_msa_insert_b
:
16871 case CODE_FOR_msa_insert_h
:
16872 case CODE_FOR_msa_insert_w
:
16873 case CODE_FOR_msa_insert_d
:
16874 /* Map the built-ins to insert operations. We need to swap operands,
16875 fix up the mode for the element being inserted, and generate
16876 a bit mask for vec_merge. */
16877 gcc_assert (has_target_p
&& nops
== 4);
16878 std::swap (ops
[1], ops
[2]);
16879 std::swap (ops
[1], ops
[3]);
16880 imode
= GET_MODE_INNER (ops
[0].mode
);
16881 ops
[1].value
= lowpart_subreg (imode
, ops
[1].value
, ops
[1].mode
);
16882 ops
[1].mode
= imode
;
16884 rangehi
= GET_MODE_NUNITS (ops
[0].mode
) - 1;
16885 if (CONST_INT_P (ops
[3].value
)
16886 && IN_RANGE (INTVAL (ops
[3].value
), rangelo
, rangehi
))
16887 ops
[3].value
= GEN_INT (1 << INTVAL (ops
[3].value
));
16892 case CODE_FOR_msa_insve_b
:
16893 case CODE_FOR_msa_insve_h
:
16894 case CODE_FOR_msa_insve_w
:
16895 case CODE_FOR_msa_insve_d
:
16896 /* Map the built-ins to element insert operations. We need to swap
16897 operands and generate a bit mask. */
16898 gcc_assert (has_target_p
&& nops
== 4);
16899 std::swap (ops
[1], ops
[2]);
16900 std::swap (ops
[1], ops
[3]);
16902 rangehi
= GET_MODE_NUNITS (ops
[0].mode
) - 1;
16903 if (CONST_INT_P (ops
[3].value
)
16904 && IN_RANGE (INTVAL (ops
[3].value
), rangelo
, rangehi
))
16905 ops
[3].value
= GEN_INT (1 << INTVAL (ops
[3].value
));
16910 case CODE_FOR_msa_shf_b
:
16911 case CODE_FOR_msa_shf_h
:
16912 case CODE_FOR_msa_shf_w
:
16913 case CODE_FOR_msa_shf_w_f
:
16914 gcc_assert (has_target_p
&& nops
== 3);
16915 ops
[2].value
= mips_gen_const_int_vector_shuffle (ops
[0].mode
,
16916 INTVAL (ops
[2].value
));
16919 case CODE_FOR_msa_vshf_b
:
16920 case CODE_FOR_msa_vshf_h
:
16921 case CODE_FOR_msa_vshf_w
:
16922 case CODE_FOR_msa_vshf_d
:
16923 gcc_assert (has_target_p
&& nops
== 4);
16924 std::swap (ops
[1], ops
[3]);
16931 if (error_opno
!= 0)
16933 error ("argument %d to the built-in must be a constant"
16934 " in range %d to %d", error_opno
, rangelo
, rangehi
);
16935 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
16937 else if (!maybe_expand_insn (icode
, nops
, ops
))
16939 error ("invalid argument to built-in function");
16940 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
16942 return has_target_p
? ops
[0].value
: const0_rtx
;
16945 /* Expand a floating-point comparison for built-in function call EXP.
16946 The first NARGS arguments are the values to be compared. ICODE is
16947 the .md pattern that does the comparison and COND is the condition
16948 that is being tested. Return an rtx for the result. */
16951 mips_expand_builtin_compare_1 (enum insn_code icode
,
16952 enum mips_fp_condition cond
,
16953 tree exp
, int nargs
)
16955 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
16959 /* The instruction should have a target operand, an operand for each
16960 argument, and an operand for COND. */
16961 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
16963 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
16965 create_fixed_operand (&ops
[opno
++], output
);
16966 for (argno
= 0; argno
< nargs
; argno
++)
16967 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
16968 create_integer_operand (&ops
[opno
++], (int) cond
);
16969 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
16972 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
16973 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
16974 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
16975 suggests a good place to put the result. */
16978 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
16981 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
16984 /* Map any target to operand 0. */
16987 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
16989 /* Map the arguments to the other operands. */
16990 gcc_assert (opno
+ call_expr_nargs (exp
)
16991 == insn_data
[icode
].n_generator_args
);
16992 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
16993 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
16995 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
16998 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
16999 function; TYPE says which. EXP is the CALL_EXPR that calls the
17000 function, ICODE is the instruction that should be used to compare
17001 the first two arguments, and COND is the condition it should test.
17002 TARGET, if nonnull, suggests a good place to put the result. */
17005 mips_expand_builtin_movtf (enum mips_builtin_type type
,
17006 enum insn_code icode
, enum mips_fp_condition cond
,
17007 rtx target
, tree exp
)
17009 struct expand_operand ops
[4];
17012 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
17013 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
17014 if (type
== MIPS_BUILTIN_MOVT
)
17016 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
17017 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
17021 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
17022 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
17024 create_fixed_operand (&ops
[3], cmp_result
);
17025 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
17029 /* Expand an MSA built-in for a compare and branch instruction specified by
17030 ICODE, set a general-purpose register to 1 if the branch was taken,
17034 mips_expand_builtin_msa_test_branch (enum insn_code icode
, tree exp
)
17036 struct expand_operand ops
[3];
17038 rtx_code_label
*true_label
, *done_label
;
17041 true_label
= gen_label_rtx ();
17042 done_label
= gen_label_rtx ();
17044 create_input_operand (&ops
[0], true_label
, TYPE_MODE (TREE_TYPE (exp
)));
17045 mips_prepare_builtin_arg (&ops
[1], exp
, 0);
17046 create_fixed_operand (&ops
[2], const0_rtx
);
17048 /* Make sure that the operand 1 is a REG. */
17049 if (GET_CODE (ops
[1].value
) != REG
)
17050 ops
[1].value
= force_reg (ops
[1].mode
, ops
[1].value
);
17052 if ((cbranch
= maybe_gen_insn (icode
, 3, ops
)) == NULL_RTX
)
17053 error ("failed to expand built-in function");
17055 cmp_result
= gen_reg_rtx (SImode
);
17057 /* First assume that CMP_RESULT is false. */
17058 mips_emit_move (cmp_result
, const0_rtx
);
17060 /* Branch to TRUE_LABEL if CBRANCH is taken and DONE_LABEL otherwise. */
17061 emit_jump_insn (cbranch
);
17062 emit_jump_insn (gen_jump (done_label
));
17065 /* Set CMP_RESULT to true if the branch was taken. */
17066 emit_label (true_label
);
17067 mips_emit_move (cmp_result
, const1_rtx
);
17069 emit_label (done_label
);
17073 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
17074 into TARGET otherwise. Return TARGET. */
17077 mips_builtin_branch_and_move (rtx condition
, rtx target
,
17078 rtx value_if_true
, rtx value_if_false
)
17080 rtx_code_label
*true_label
, *done_label
;
17082 true_label
= gen_label_rtx ();
17083 done_label
= gen_label_rtx ();
17085 /* First assume that CONDITION is false. */
17086 mips_emit_move (target
, value_if_false
);
17088 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
17089 emit_jump_insn (gen_condjump (condition
, true_label
));
17090 emit_jump_insn (gen_jump (done_label
));
17093 /* Fix TARGET if CONDITION is true. */
17094 emit_label (true_label
);
17095 mips_emit_move (target
, value_if_true
);
17097 emit_label (done_label
);
17101 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
17102 the CALL_EXPR that calls the function, ICODE is the code of the
17103 comparison instruction, and COND is the condition it should test.
17104 TARGET, if nonnull, suggests a good place to put the boolean result. */
17107 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
17108 enum insn_code icode
, enum mips_fp_condition cond
,
17109 rtx target
, tree exp
)
17111 rtx offset
, condition
, cmp_result
;
17113 if (target
== 0 || GET_MODE (target
) != SImode
)
17114 target
= gen_reg_rtx (SImode
);
17115 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
17116 call_expr_nargs (exp
));
17118 /* If the comparison sets more than one register, we define the result
17119 to be 0 if all registers are false and -1 if all registers are true.
17120 The value of the complete result is indeterminate otherwise. */
17121 switch (builtin_type
)
17123 case MIPS_BUILTIN_CMP_ALL
:
17124 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
17125 return mips_builtin_branch_and_move (condition
, target
,
17126 const0_rtx
, const1_rtx
);
17128 case MIPS_BUILTIN_CMP_UPPER
:
17129 case MIPS_BUILTIN_CMP_LOWER
:
17130 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
17131 condition
= gen_single_cc (cmp_result
, offset
);
17132 return mips_builtin_branch_and_move (condition
, target
,
17133 const1_rtx
, const0_rtx
);
17136 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
17137 return mips_builtin_branch_and_move (condition
, target
,
17138 const1_rtx
, const0_rtx
);
17142 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
17143 if nonnull, suggests a good place to put the boolean result. */
17146 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
17148 rtx condition
, cmp_result
;
17151 if (target
== 0 || GET_MODE (target
) != SImode
)
17152 target
= gen_reg_rtx (SImode
);
17154 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
17156 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
17161 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
17162 return mips_builtin_branch_and_move (condition
, target
,
17163 const1_rtx
, const0_rtx
);
17166 /* Implement TARGET_EXPAND_BUILTIN. */
17169 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
17170 machine_mode mode
, int ignore
)
17173 unsigned int fcode
, avail
;
17174 const struct mips_builtin_description
*d
;
17176 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
17177 fcode
= DECL_FUNCTION_CODE (fndecl
);
17178 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
17179 d
= &mips_builtins
[fcode
];
17180 avail
= d
->avail ();
17181 gcc_assert (avail
!= 0);
17182 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
17184 error ("built-in function %qE not supported for MIPS16",
17185 DECL_NAME (fndecl
));
17186 return ignore
? const0_rtx
: CONST0_RTX (mode
);
17188 switch (d
->builtin_type
)
17190 case MIPS_BUILTIN_DIRECT
:
17191 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
17193 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
17194 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
17196 case MIPS_BUILTIN_MOVT
:
17197 case MIPS_BUILTIN_MOVF
:
17198 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
17199 d
->cond
, target
, exp
);
17201 case MIPS_BUILTIN_CMP_ANY
:
17202 case MIPS_BUILTIN_CMP_ALL
:
17203 case MIPS_BUILTIN_CMP_UPPER
:
17204 case MIPS_BUILTIN_CMP_LOWER
:
17205 case MIPS_BUILTIN_CMP_SINGLE
:
17206 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
17207 d
->cond
, target
, exp
);
17209 case MIPS_BUILTIN_MSA_TEST_BRANCH
:
17210 return mips_expand_builtin_msa_test_branch (d
->icode
, exp
);
17212 case MIPS_BUILTIN_BPOSGE32
:
17213 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
17215 gcc_unreachable ();
17218 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
17219 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
17220 struct mips16_constant
{
17221 struct mips16_constant
*next
;
17223 rtx_code_label
*label
;
17227 /* Information about an incomplete MIPS16 constant pool. FIRST is the
17228 first constant, HIGHEST_ADDRESS is the highest address that the first
17229 byte of the pool can have, and INSN_ADDRESS is the current instruction
17231 struct mips16_constant_pool
{
17232 struct mips16_constant
*first
;
17233 int highest_address
;
17237 /* Add constant VALUE to POOL and return its label. MODE is the
17238 value's mode (used for CONST_INTs, etc.). */
17240 static rtx_code_label
*
17241 mips16_add_constant (struct mips16_constant_pool
*pool
,
17242 rtx value
, machine_mode mode
)
17244 struct mips16_constant
**p
, *c
;
17245 bool first_of_size_p
;
17247 /* See whether the constant is already in the pool. If so, return the
17248 existing label, otherwise leave P pointing to the place where the
17249 constant should be added.
17251 Keep the pool sorted in increasing order of mode size so that we can
17252 reduce the number of alignments needed. */
17253 first_of_size_p
= true;
17254 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
17256 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
17257 return (*p
)->label
;
17258 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
17260 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
17261 first_of_size_p
= false;
17264 /* In the worst case, the constant needed by the earliest instruction
17265 will end up at the end of the pool. The entire pool must then be
17266 accessible from that instruction.
17268 When adding the first constant, set the pool's highest address to
17269 the address of the first out-of-range byte. Adjust this address
17270 downwards each time a new constant is added. */
17271 if (pool
->first
== 0)
17272 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
17273 of the instruction with the lowest two bits clear. The base PC
17274 value for LDPC has the lowest three bits clear. Assume the worst
17275 case here; namely that the PC-relative instruction occupies the
17276 last 2 bytes in an aligned word. */
17277 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
17278 pool
->highest_address
-= GET_MODE_SIZE (mode
);
17279 if (first_of_size_p
)
17280 /* Take into account the worst possible padding due to alignment. */
17281 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
17283 /* Create a new entry. */
17284 c
= XNEW (struct mips16_constant
);
17287 c
->label
= gen_label_rtx ();
17294 /* Output constant VALUE after instruction INSN and return the last
17295 instruction emitted. MODE is the mode of the constant. */
17298 mips16_emit_constants_1 (machine_mode mode
, rtx value
, rtx_insn
*insn
)
17300 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
17302 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
17303 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
17306 if (SCALAR_FLOAT_MODE_P (mode
))
17307 return emit_insn_after (gen_consttable_float (value
), insn
);
17309 if (VECTOR_MODE_P (mode
))
17313 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
17314 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
17315 CONST_VECTOR_ELT (value
, i
), insn
);
17319 gcc_unreachable ();
17322 /* Dump out the constants in CONSTANTS after INSN. Record the initial
17323 label number in the `consttable' and `consttable_end' insns emitted
17324 at the beginning and the end of the constant pool respectively, so
17325 that individual pools can be uniquely marked as data for the purpose
17329 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
17331 int label_num
= constants
? CODE_LABEL_NUMBER (constants
->label
) : 0;
17332 struct mips16_constant
*c
, *next
;
17337 insn
= emit_insn_after (gen_consttable (GEN_INT (label_num
)), insn
);
17338 for (c
= constants
; c
!= NULL
; c
= next
)
17340 /* If necessary, increase the alignment of PC. */
17341 if (align
< GET_MODE_SIZE (c
->mode
))
17343 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
17344 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
17346 align
= GET_MODE_SIZE (c
->mode
);
17348 insn
= emit_label_after (c
->label
, insn
);
17349 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
17355 insn
= emit_insn_after (gen_consttable_end (GEN_INT (label_num
)), insn
);
17357 emit_barrier_after (insn
);
17360 /* Return the length of instruction INSN. */
17363 mips16_insn_length (rtx_insn
*insn
)
17365 if (JUMP_TABLE_DATA_P (insn
))
17367 rtx body
= PATTERN (insn
);
17368 if (GET_CODE (body
) == ADDR_VEC
)
17369 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
17370 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
17371 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
17373 gcc_unreachable ();
17375 return get_attr_length (insn
);
17378 /* If *X is a symbolic constant that refers to the constant pool, add
17379 the constant to POOL and rewrite *X to use the constant's label. */
17382 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
17385 rtx_code_label
*label
;
17387 split_const (*x
, &base
, &offset
);
17388 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
17390 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
17391 get_pool_mode (base
));
17392 base
= gen_rtx_LABEL_REF (Pmode
, label
);
17393 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
17397 /* Rewrite INSN so that constant pool references refer to the constant's
17401 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
17403 subrtx_ptr_iterator::array_type array
;
17404 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
17408 if (force_to_mem_operand (*loc
, Pmode
))
17410 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
17411 validate_change (insn
, loc
, mem
, false);
17416 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
17417 iter
.skip_subrtxes ();
17421 if (TARGET_MIPS16_TEXT_LOADS
)
17422 mips16_rewrite_pool_constant (pool
, loc
);
17423 if (GET_CODE (*loc
) == CONST
17424 /* Don't rewrite the __mips16_rdwr symbol. */
17425 || (GET_CODE (*loc
) == UNSPEC
17426 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
17427 iter
.skip_subrtxes ();
17432 /* Return whether CFG is used in mips_reorg. */
17435 mips_cfg_in_reorg (void)
17437 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17438 || TARGET_RELAX_PIC_CALLS
);
17441 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
17442 otherwise assume that they are already split. */
17445 mips16_lay_out_constants (bool split_p
)
17447 struct mips16_constant_pool pool
;
17448 rtx_insn
*insn
, *barrier
;
17450 if (!TARGET_MIPS16_PCREL_LOADS
)
17455 if (mips_cfg_in_reorg ())
17456 split_all_insns ();
17458 split_all_insns_noflow ();
17461 memset (&pool
, 0, sizeof (pool
));
17462 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17464 /* Rewrite constant pool references in INSN. */
17465 if (USEFUL_INSN_P (insn
))
17466 mips16_rewrite_pool_refs (insn
, &pool
);
17468 pool
.insn_address
+= mips16_insn_length (insn
);
17470 if (pool
.first
!= NULL
)
17472 /* If there are no natural barriers between the first user of
17473 the pool and the highest acceptable address, we'll need to
17474 create a new instruction to jump around the constant pool.
17475 In the worst case, this instruction will be 4 bytes long.
17477 If it's too late to do this transformation after INSN,
17478 do it immediately before INSN. */
17479 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
17481 rtx_code_label
*label
;
17484 label
= gen_label_rtx ();
17486 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
17487 JUMP_LABEL (jump
) = label
;
17488 LABEL_NUSES (label
) = 1;
17489 barrier
= emit_barrier_after (jump
);
17491 emit_label_after (label
, barrier
);
17492 pool
.insn_address
+= 4;
17495 /* See whether the constant pool is now out of range of the first
17496 user. If so, output the constants after the previous barrier.
17497 Note that any instructions between BARRIER and INSN (inclusive)
17498 will use negative offsets to refer to the pool. */
17499 if (pool
.insn_address
> pool
.highest_address
)
17501 mips16_emit_constants (pool
.first
, barrier
);
17505 else if (BARRIER_P (insn
))
17509 mips16_emit_constants (pool
.first
, get_last_insn ());
17512 /* Return true if it is worth r10k_simplify_address's while replacing
17513 an address with X. We are looking for constants, and for addresses
17514 at a known offset from the incoming stack pointer. */
17517 r10k_simplified_address_p (rtx x
)
17519 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
17521 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
17524 /* X is an expression that appears in INSN. Try to use the UD chains
17525 to simplify it, returning the simplified form on success and the
17526 original form otherwise. Replace the incoming value of $sp with
17527 virtual_incoming_args_rtx (which should never occur in X otherwise). */
17530 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
17532 rtx newx
, op0
, op1
, set
, note
;
17533 rtx_insn
*def_insn
;
17535 struct df_link
*defs
;
17540 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17541 if (op0
!= XEXP (x
, 0))
17542 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
17543 op0
, GET_MODE (XEXP (x
, 0)));
17545 else if (BINARY_P (x
))
17547 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17548 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
17549 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
17550 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
17552 else if (GET_CODE (x
) == LO_SUM
)
17554 /* LO_SUMs can be offset from HIGHs, if we know they won't
17555 overflow. See mips_classify_address for the rationale behind
17557 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17558 if (GET_CODE (op0
) == HIGH
)
17559 newx
= XEXP (x
, 1);
17561 else if (REG_P (x
))
17563 /* Uses are recorded by regno_reg_rtx, not X itself. */
17564 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
17566 defs
= DF_REF_CHAIN (use
);
17568 /* Require a single definition. */
17569 if (defs
&& defs
->next
== NULL
)
17572 if (DF_REF_IS_ARTIFICIAL (def
))
17574 /* Replace the incoming value of $sp with
17575 virtual_incoming_args_rtx. */
17576 if (x
== stack_pointer_rtx
17577 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
17578 newx
= virtual_incoming_args_rtx
;
17580 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
17583 /* Make sure that DEF_INSN is a single set of REG. */
17584 def_insn
= DF_REF_INSN (def
);
17585 if (NONJUMP_INSN_P (def_insn
))
17587 set
= single_set (def_insn
);
17588 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
17590 /* Prefer to use notes, since the def-use chains
17591 are often shorter. */
17592 note
= find_reg_equal_equiv_note (def_insn
);
17594 newx
= XEXP (note
, 0);
17596 newx
= SET_SRC (set
);
17597 newx
= r10k_simplify_address (newx
, def_insn
);
17603 if (newx
&& r10k_simplified_address_p (newx
))
17608 /* Return true if ADDRESS is known to be an uncached address
17609 on R10K systems. */
17612 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
17614 unsigned HOST_WIDE_INT upper
;
17616 /* Check for KSEG1. */
17617 if (address
+ 0x60000000 < 0x20000000)
17620 /* Check for uncached XKPHYS addresses. */
17621 if (Pmode
== DImode
)
17623 upper
= (address
>> 40) & 0xf9ffff;
17624 if (upper
== 0x900000 || upper
== 0xb80000)
17630 /* Return true if we can prove that an access to address X in instruction
17631 INSN would be safe from R10K speculation. This X is a general
17632 expression; it might not be a legitimate address. */
17635 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
17638 HOST_WIDE_INT offset_val
;
17640 x
= r10k_simplify_address (x
, insn
);
17642 /* Check for references to the stack frame. It doesn't really matter
17643 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
17644 allows us to assume that accesses to any part of the eventual frame
17645 is safe from speculation at any point in the function. */
17646 mips_split_plus (x
, &base
, &offset_val
);
17647 if (base
== virtual_incoming_args_rtx
17648 && offset_val
>= -cfun
->machine
->frame
.total_size
17649 && offset_val
< cfun
->machine
->frame
.args_size
)
17652 /* Check for uncached addresses. */
17653 if (CONST_INT_P (x
))
17654 return r10k_uncached_address_p (INTVAL (x
));
17656 /* Check for accesses to a static object. */
17657 split_const (x
, &base
, &offset
);
17658 return offset_within_block_p (base
, INTVAL (offset
));
17661 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
17662 an in-range access to an automatic variable, or to an object with
17663 a link-time-constant address. */
17666 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
17668 poly_int64 bitoffset
, bitsize
;
17669 tree inner
, var_offset
;
17671 int unsigned_p
, reverse_p
, volatile_p
;
17673 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
17674 &unsigned_p
, &reverse_p
, &volatile_p
);
17675 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
17678 offset
+= bitoffset
/ BITS_PER_UNIT
;
17679 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
17682 /* Return true if X contains a MEM that is not safe from R10K speculation.
17683 INSN is the instruction that contains X. */
17686 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
17688 subrtx_var_iterator::array_type array
;
17689 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
17694 if ((MEM_EXPR (mem
)
17695 && MEM_OFFSET_KNOWN_P (mem
)
17696 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
17697 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
17698 iter
.skip_subrtxes ();
17706 /* A note_stores callback for which DATA points to an instruction pointer.
17707 If *DATA is nonnull, make it null if it X contains a MEM that is not
17708 safe from R10K speculation. */
17711 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
17714 rtx_insn
**insn_ptr
;
17716 insn_ptr
= (rtx_insn
**) data
;
17717 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
17721 /* X is the pattern of a call instruction. Return true if the call is
17722 not to a declared function. */
17725 r10k_needs_protection_p_call (const_rtx x
)
17727 subrtx_iterator::array_type array
;
17728 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
17730 const_rtx mem
= *iter
;
17733 const_rtx addr
= XEXP (mem
, 0);
17734 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
17735 iter
.skip_subrtxes ();
17743 /* Return true if instruction INSN needs to be protected by an R10K
17747 r10k_needs_protection_p (rtx_insn
*insn
)
17750 return r10k_needs_protection_p_call (PATTERN (insn
));
17752 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
17754 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
17755 return insn
== NULL_RTX
;
17758 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
17761 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
17762 edge is unconditional. */
17765 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
17770 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
17771 if (!single_succ_p (e
->src
)
17772 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
17773 || (e
->flags
& EDGE_COMPLEX
) != 0)
17778 /* Implement -mr10k-cache-barrier= for the current function. */
17781 r10k_insert_cache_barriers (void)
17783 int *rev_post_order
;
17786 sbitmap protected_bbs
;
17787 rtx_insn
*insn
, *end
;
17788 rtx unprotected_region
;
17792 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
17796 /* Calculate dominators. */
17797 calculate_dominance_info (CDI_DOMINATORS
);
17799 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
17800 X is protected by a cache barrier. */
17801 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
17802 bitmap_clear (protected_bbs
);
17804 /* Iterate over the basic blocks in reverse post-order. */
17805 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
17806 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
17807 for (i
= 0; i
< n
; i
++)
17809 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
17811 /* If this block is only reached by unconditional edges, and if the
17812 source of every edge is protected, the beginning of the block is
17814 if (r10k_protected_bb_p (bb
, protected_bbs
))
17815 unprotected_region
= NULL_RTX
;
17817 unprotected_region
= pc_rtx
;
17818 end
= NEXT_INSN (BB_END (bb
));
17820 /* UNPROTECTED_REGION is:
17822 - null if we are processing a protected region,
17823 - pc_rtx if we are processing an unprotected region but have
17824 not yet found the first instruction in it
17825 - the first instruction in an unprotected region otherwise. */
17826 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
17828 if (unprotected_region
&& USEFUL_INSN_P (insn
))
17830 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
17831 /* This CACHE instruction protects the following code. */
17832 unprotected_region
= NULL_RTX
;
17835 /* See if INSN is the first instruction in this
17836 unprotected region. */
17837 if (unprotected_region
== pc_rtx
)
17838 unprotected_region
= insn
;
17840 /* See if INSN needs to be protected. If so,
17841 we must insert a cache barrier somewhere between
17842 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
17843 clear which position is better performance-wise,
17844 but as a tie-breaker, we assume that it is better
17845 to allow delay slots to be back-filled where
17846 possible, and that it is better not to insert
17847 barriers in the middle of already-scheduled code.
17848 We therefore insert the barrier at the beginning
17850 if (r10k_needs_protection_p (insn
))
17852 emit_insn_before (gen_r10k_cache_barrier (),
17853 as_a
<rtx_insn
*> (unprotected_region
));
17854 unprotected_region
= NULL_RTX
;
17860 /* The called function is not required to protect the exit path.
17861 The code that follows a call is therefore unprotected. */
17862 unprotected_region
= pc_rtx
;
17865 /* Record whether the end of this block is protected. */
17866 if (unprotected_region
== NULL_RTX
)
17867 bitmap_set_bit (protected_bbs
, bb
->index
);
17869 XDELETEVEC (rev_post_order
);
17871 sbitmap_free (protected_bbs
);
17873 free_dominance_info (CDI_DOMINATORS
);
17876 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
17877 otherwise. If INSN has two call rtx, then store the second one in
17881 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
17886 if (!CALL_P (insn
))
17889 x
= PATTERN (insn
);
17890 if (GET_CODE (x
) == PARALLEL
)
17892 /* Calls returning complex values have two CALL rtx. Look for the second
17893 one here, and return it via the SECOND_CALL arg. */
17894 x2
= XVECEXP (x
, 0, 1);
17895 if (GET_CODE (x2
) == SET
)
17897 if (GET_CODE (x2
) == CALL
)
17900 x
= XVECEXP (x
, 0, 0);
17902 if (GET_CODE (x
) == SET
)
17904 gcc_assert (GET_CODE (x
) == CALL
);
17909 /* REG is set in DEF. See if the definition is one of the ways we load a
17910 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
17911 If it is, return the symbol reference of the function, otherwise return
17914 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
17915 the values of source registers, otherwise treat such registers as
17916 having an unknown value. */
17919 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
17921 rtx_insn
*def_insn
;
17924 if (DF_REF_IS_ARTIFICIAL (def
))
17927 def_insn
= DF_REF_INSN (def
);
17928 set
= single_set (def_insn
);
17929 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
17931 rtx note
, src
, symbol
;
17933 /* First see whether the source is a plain symbol. This is used
17934 when calling symbols that are not lazily bound. */
17935 src
= SET_SRC (set
);
17936 if (GET_CODE (src
) == SYMBOL_REF
)
17939 /* Handle %call16 references. */
17940 symbol
= mips_strip_unspec_call (src
);
17943 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
17947 /* If we have something more complicated, look for a
17948 REG_EQUAL or REG_EQUIV note. */
17949 note
= find_reg_equal_equiv_note (def_insn
);
17950 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
17951 return XEXP (note
, 0);
17953 /* Follow at most one simple register copy. Such copies are
17954 interesting in cases like:
17958 locally_binding_fn (...);
17963 locally_binding_fn (...);
17965 locally_binding_fn (...);
17967 where the load of locally_binding_fn can legitimately be
17968 hoisted or shared. However, we do not expect to see complex
17969 chains of copies, so a full worklist solution to the problem
17970 would probably be overkill. */
17971 if (recurse_p
&& REG_P (src
))
17972 return mips_find_pic_call_symbol (def_insn
, src
, false);
17978 /* Find the definition of the use of REG in INSN. See if the definition
17979 is one of the ways we load a register with a symbol address for a
17980 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
17981 of the function, otherwise return NULL_RTX. RECURSE_P is as for
17982 mips_pic_call_symbol_from_set. */
17985 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
17988 struct df_link
*defs
;
17991 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
17994 defs
= DF_REF_CHAIN (use
);
17997 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
18001 /* If we have more than one definition, they need to be identical. */
18002 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
18006 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
18007 if (!rtx_equal_p (symbol
, other
))
18014 /* Replace the args_size operand of the call expression CALL with the
18015 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
18018 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
18022 args_size
= XEXP (call
, 1);
18023 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
18024 gen_rtvec (2, args_size
, symbol
),
18028 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
18029 if instead of the arg_size argument it contains the call attributes. If
18030 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
18031 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
18035 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
18037 rtx args_size
, symbol
;
18039 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
18042 args_size
= operands
[args_size_opno
];
18043 if (GET_CODE (args_size
) != UNSPEC
)
18045 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
18047 symbol
= XVECEXP (args_size
, 0, 1);
18048 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
18050 operands
[args_size_opno
] = symbol
;
18054 /* Use DF to annotate PIC indirect calls with the function symbol they
18058 mips_annotate_pic_calls (void)
18063 FOR_EACH_BB_FN (bb
, cfun
)
18064 FOR_BB_INSNS (bb
, insn
)
18066 rtx call
, reg
, symbol
, second_call
;
18069 call
= mips_call_expr_from_insn (insn
, &second_call
);
18072 gcc_assert (MEM_P (XEXP (call
, 0)));
18073 reg
= XEXP (XEXP (call
, 0), 0);
18077 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
18080 mips_annotate_pic_call_expr (call
, symbol
);
18082 mips_annotate_pic_call_expr (second_call
, symbol
);
18087 /* A temporary variable used by note_uses callbacks, etc. */
18088 static rtx_insn
*mips_sim_insn
;
18090 /* A structure representing the state of the processor pipeline.
18091 Used by the mips_sim_* family of functions. */
18093 /* The maximum number of instructions that can be issued in a cycle.
18094 (Caches mips_issue_rate.) */
18095 unsigned int issue_rate
;
18097 /* The current simulation time. */
18100 /* How many more instructions can be issued in the current cycle. */
18101 unsigned int insns_left
;
18103 /* LAST_SET[X].INSN is the last instruction to set register X.
18104 LAST_SET[X].TIME is the time at which that instruction was issued.
18105 INSN is null if no instruction has yet set register X. */
18109 } last_set
[FIRST_PSEUDO_REGISTER
];
18111 /* The pipeline's current DFA state. */
18115 /* Reset STATE to the initial simulation state. */
18118 mips_sim_reset (struct mips_sim
*state
)
18120 curr_state
= state
->dfa_state
;
18123 state
->insns_left
= state
->issue_rate
;
18124 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
18125 state_reset (curr_state
);
18127 targetm
.sched
.init (0, false, 0);
18128 advance_state (curr_state
);
18131 /* Initialize STATE before its first use. DFA_STATE points to an
18132 allocated but uninitialized DFA state. */
18135 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
18137 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
18138 targetm
.sched
.init_dfa_pre_cycle_insn ();
18140 if (targetm
.sched
.init_dfa_post_cycle_insn
)
18141 targetm
.sched
.init_dfa_post_cycle_insn ();
18143 state
->issue_rate
= mips_issue_rate ();
18144 state
->dfa_state
= dfa_state
;
18145 mips_sim_reset (state
);
18148 /* Advance STATE by one clock cycle. */
18151 mips_sim_next_cycle (struct mips_sim
*state
)
18153 curr_state
= state
->dfa_state
;
18156 state
->insns_left
= state
->issue_rate
;
18157 advance_state (curr_state
);
18160 /* Advance simulation state STATE until instruction INSN can read
18164 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
18166 unsigned int regno
, end_regno
;
18168 end_regno
= END_REGNO (reg
);
18169 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
18170 if (state
->last_set
[regno
].insn
!= 0)
18174 t
= (state
->last_set
[regno
].time
18175 + insn_latency (state
->last_set
[regno
].insn
, insn
));
18176 while (state
->time
< t
)
18177 mips_sim_next_cycle (state
);
18181 /* A note_uses callback. For each register in *X, advance simulation
18182 state DATA until mips_sim_insn can read the register's value. */
18185 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
18187 subrtx_var_iterator::array_type array
;
18188 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
18190 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
18193 /* Advance simulation state STATE until all of INSN's register
18194 dependencies are satisfied. */
18197 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
18199 mips_sim_insn
= insn
;
18200 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
18203 /* Advance simulation state STATE until the units required by
18204 instruction INSN are available. */
18207 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
18211 tmp_state
= alloca (state_size ());
18212 while (state
->insns_left
== 0
18213 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
18214 state_transition (tmp_state
, insn
) >= 0))
18215 mips_sim_next_cycle (state
);
18218 /* Advance simulation state STATE until INSN is ready to issue. */
18221 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18223 mips_sim_wait_regs (state
, insn
);
18224 mips_sim_wait_units (state
, insn
);
18227 /* mips_sim_insn has just set X. Update the LAST_SET array
18228 in simulation state DATA. */
18231 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
18233 struct mips_sim
*state
;
18235 state
= (struct mips_sim
*) data
;
18238 unsigned int regno
, end_regno
;
18240 end_regno
= END_REGNO (x
);
18241 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
18243 state
->last_set
[regno
].insn
= mips_sim_insn
;
18244 state
->last_set
[regno
].time
= state
->time
;
18249 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
18250 can issue immediately (i.e., that mips_sim_wait_insn has already
18254 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18256 curr_state
= state
->dfa_state
;
18258 state_transition (curr_state
, insn
);
18259 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
18260 state
->insns_left
);
18262 mips_sim_insn
= insn
;
18263 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
18266 /* Simulate issuing a NOP in state STATE. */
18269 mips_sim_issue_nop (struct mips_sim
*state
)
18271 if (state
->insns_left
== 0)
18272 mips_sim_next_cycle (state
);
18273 state
->insns_left
--;
18276 /* Update simulation state STATE so that it's ready to accept the instruction
18277 after INSN. INSN should be part of the main rtl chain, not a member of a
18281 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18283 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
18285 mips_sim_issue_nop (state
);
18287 switch (GET_CODE (SEQ_BEGIN (insn
)))
18291 /* We can't predict the processor state after a call or label. */
18292 mips_sim_reset (state
);
18296 /* The delay slots of branch likely instructions are only executed
18297 when the branch is taken. Therefore, if the caller has simulated
18298 the delay slot instruction, STATE does not really reflect the state
18299 of the pipeline for the instruction after the delay slot. Also,
18300 branch likely instructions tend to incur a penalty when not taken,
18301 so there will probably be an extra delay between the branch and
18302 the instruction after the delay slot. */
18303 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
18304 mips_sim_reset (state
);
18312 /* Use simulator state STATE to calculate the execution time of
18313 instruction sequence SEQ. */
18315 static unsigned int
18316 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
18318 mips_sim_reset (state
);
18319 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
18321 mips_sim_wait_insn (state
, insn
);
18322 mips_sim_issue_insn (state
, insn
);
18324 return state
->time
;
18327 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
18328 setting SETTING, using STATE to simulate instruction sequences. */
18330 static unsigned int
18331 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
18333 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
18336 machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
18337 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
18338 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
18340 /* If the target provides mulsidi3_32bit then that's the most likely
18341 consumer of the result. Test for bypasses. */
18342 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
18344 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
18345 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
18348 unsigned int time
= mips_seq_time (state
, get_insns ());
18353 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
18354 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
18355 Prefer MULT -- which is shorter -- in the event of a tie. */
18358 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
18360 if (TARGET_MIPS16
|| !ISA_HAS_HILO
)
18361 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
18362 registers then there is no reason to zero them, arbitrarily choose to
18363 say that "MULT $0,$0" would be faster. */
18364 mips_tuning_info
.fast_mult_zero_zero_p
= true;
18367 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
18368 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
18369 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
18373 /* Set up costs based on the current architecture and tuning settings. */
18376 mips_set_tuning_info (void)
18378 if (mips_tuning_info
.initialized_p
18379 && mips_tuning_info
.arch
== mips_arch
18380 && mips_tuning_info
.tune
== mips_tune
18381 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
18384 mips_tuning_info
.arch
= mips_arch
;
18385 mips_tuning_info
.tune
= mips_tune
;
18386 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
18387 mips_tuning_info
.initialized_p
= true;
18391 struct mips_sim state
;
18392 mips_sim_init (&state
, alloca (state_size ()));
18394 mips_set_fast_mult_zero_zero_p (&state
);
18399 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
18402 mips_expand_to_rtl_hook (void)
18404 /* We need to call this at a point where we can safely create sequences
18405 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
18406 need to call it at a point where the DFA infrastructure is not
18407 already in use, so we can't just call it lazily on demand.
18409 At present, mips_tuning_info is only needed during post-expand
18410 RTL passes such as split_insns, so this hook should be early enough.
18411 We may need to move the call elsewhere if mips_tuning_info starts
18412 to be used for other things (such as rtx_costs, or expanders that
18413 could be called during gimple optimization). */
18414 mips_set_tuning_info ();
18417 /* The VR4130 pipeline issues aligned pairs of instructions together,
18418 but it stalls the second instruction if it depends on the first.
18419 In order to cut down the amount of logic required, this dependence
18420 check is not based on a full instruction decode. Instead, any non-SPECIAL
18421 instruction is assumed to modify the register specified by bits 20-16
18422 (which is usually the "rt" field).
18424 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
18425 input, so we can end up with a false dependence between the branch
18426 and its delay slot. If this situation occurs in instruction INSN,
18427 try to avoid it by swapping rs and rt. */
18430 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
18432 rtx_insn
*first
, *second
;
18434 first
= SEQ_BEGIN (insn
);
18435 second
= SEQ_END (insn
);
18437 && NONJUMP_INSN_P (second
)
18438 && GET_CODE (PATTERN (first
)) == SET
18439 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
18440 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
18442 /* Check for the right kind of condition. */
18443 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
18444 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
18445 && REG_P (XEXP (cond
, 0))
18446 && REG_P (XEXP (cond
, 1))
18447 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
18448 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
18450 /* SECOND mentions the rt register but not the rs register. */
18451 rtx tmp
= XEXP (cond
, 0);
18452 XEXP (cond
, 0) = XEXP (cond
, 1);
18453 XEXP (cond
, 1) = tmp
;
18458 /* Implement -mvr4130-align. Go through each basic block and simulate the
18459 processor pipeline. If we find that a pair of instructions could execute
18460 in parallel, and the first of those instructions is not 8-byte aligned,
18461 insert a nop to make it aligned. */
18464 vr4130_align_insns (void)
18466 struct mips_sim state
;
18467 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
18472 /* LAST is the last instruction before INSN to have a nonzero length.
18473 LAST2 is the last such instruction before LAST. */
18477 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
18480 mips_sim_init (&state
, alloca (state_size ()));
18481 for (insn
= get_insns (); insn
!= 0; insn
= next
)
18483 unsigned int length
;
18485 next
= NEXT_INSN (insn
);
18487 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
18488 This isn't really related to the alignment pass, but we do it on
18489 the fly to avoid a separate instruction walk. */
18490 vr4130_avoid_branch_rt_conflict (insn
);
18492 length
= get_attr_length (insn
);
18493 if (length
> 0 && USEFUL_INSN_P (insn
))
18494 FOR_EACH_SUBINSN (subinsn
, insn
)
18496 mips_sim_wait_insn (&state
, subinsn
);
18498 /* If we want this instruction to issue in parallel with the
18499 previous one, make sure that the previous instruction is
18500 aligned. There are several reasons why this isn't worthwhile
18501 when the second instruction is a call:
18503 - Calls are less likely to be performance critical,
18504 - There's a good chance that the delay slot can execute
18505 in parallel with the call.
18506 - The return address would then be unaligned.
18508 In general, if we're going to insert a nop between instructions
18509 X and Y, it's better to insert it immediately after X. That
18510 way, if the nop makes Y aligned, it will also align any labels
18511 between X and Y. */
18512 if (state
.insns_left
!= state
.issue_rate
18513 && !CALL_P (subinsn
))
18515 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
18517 /* SUBINSN is the first instruction in INSN and INSN is
18518 aligned. We want to align the previous instruction
18519 instead, so insert a nop between LAST2 and LAST.
18521 Note that LAST could be either a single instruction
18522 or a branch with a delay slot. In the latter case,
18523 LAST, like INSN, is already aligned, but the delay
18524 slot must have some extra delay that stops it from
18525 issuing at the same time as the branch. We therefore
18526 insert a nop before the branch in order to align its
18528 gcc_assert (last2
);
18529 emit_insn_after (gen_nop (), last2
);
18532 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
18534 /* SUBINSN is the delay slot of INSN, but INSN is
18535 currently unaligned. Insert a nop between
18536 LAST and INSN to align it. */
18538 emit_insn_after (gen_nop (), last
);
18542 mips_sim_issue_insn (&state
, subinsn
);
18544 mips_sim_finish_insn (&state
, insn
);
18546 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
18547 length
= get_attr_length (insn
);
18550 /* If the instruction is an asm statement or multi-instruction
18551 mips.md patern, the length is only an estimate. Insert an
18552 8 byte alignment after it so that the following instructions
18553 can be handled correctly. */
18554 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
18555 && (recog_memoized (insn
) < 0 || length
>= 8))
18557 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
18558 next
= NEXT_INSN (next
);
18559 mips_sim_next_cycle (&state
);
18562 else if (length
& 4)
18563 aligned_p
= !aligned_p
;
18568 /* See whether INSN is an aligned label. */
18569 if (LABEL_P (insn
) && label_to_alignment (insn
).levels
[0].log
>= 3)
18575 /* This structure records that the current function has a LO_SUM
18576 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
18577 the largest offset applied to BASE by all such LO_SUMs. */
18578 struct mips_lo_sum_offset
{
18580 HOST_WIDE_INT offset
;
18583 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
18586 mips_hash_base (rtx base
)
18588 int do_not_record_p
;
18590 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
18593 /* Hashtable helpers. */
18595 struct mips_lo_sum_offset_hasher
: free_ptr_hash
<mips_lo_sum_offset
>
18597 typedef rtx_def
*compare_type
;
18598 static inline hashval_t
hash (const mips_lo_sum_offset
*);
18599 static inline bool equal (const mips_lo_sum_offset
*, const rtx_def
*);
18602 /* Hash-table callbacks for mips_lo_sum_offsets. */
18605 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset
*entry
)
18607 return mips_hash_base (entry
->base
);
18611 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset
*entry
,
18612 const rtx_def
*value
)
18614 return rtx_equal_p (entry
->base
, value
);
18617 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
18619 /* Look up symbolic constant X in HTAB, which is a hash table of
18620 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
18621 paired with a recorded LO_SUM, otherwise record X in the table. */
18624 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
18625 enum insert_option option
)
18628 mips_lo_sum_offset
**slot
;
18629 struct mips_lo_sum_offset
*entry
;
18631 /* Split X into a base and offset. */
18632 split_const (x
, &base
, &offset
);
18633 if (UNSPEC_ADDRESS_P (base
))
18634 base
= UNSPEC_ADDRESS (base
);
18636 /* Look up the base in the hash table. */
18637 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
18641 entry
= (struct mips_lo_sum_offset
*) *slot
;
18642 if (option
== INSERT
)
18646 entry
= XNEW (struct mips_lo_sum_offset
);
18647 entry
->base
= base
;
18648 entry
->offset
= INTVAL (offset
);
18653 if (INTVAL (offset
) > entry
->offset
)
18654 entry
->offset
= INTVAL (offset
);
18657 return INTVAL (offset
) <= entry
->offset
;
18660 /* Search X for LO_SUMs and record them in HTAB. */
18663 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
18665 subrtx_iterator::array_type array
;
18666 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
18667 if (GET_CODE (*iter
) == LO_SUM
)
18668 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
18671 /* Return true if INSN is a SET of an orphaned high-part relocation.
18672 HTAB is a hash table of mips_lo_sum_offsets that describes all the
18673 LO_SUMs in the current function. */
18676 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
18678 enum mips_symbol_type type
;
18681 set
= single_set (insn
);
18684 /* Check for %his. */
18686 if (GET_CODE (x
) == HIGH
18687 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
18688 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
18690 /* Check for local %gots (and %got_pages, which is redundant but OK). */
18691 if (GET_CODE (x
) == UNSPEC
18692 && XINT (x
, 1) == UNSPEC_LOAD_GOT
18693 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
18694 SYMBOL_CONTEXT_LEA
, &type
)
18695 && type
== SYMBOL_GOTOFF_PAGE
)
18696 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
18701 /* Subroutine of mips_avoid_hazard. We classify unconditional branches
18702 of interest for the P6600 for performance reasons. We're interested
18703 in differentiating BALC from JIC, JIALC and BC. */
18705 static enum mips_ucbranch_type
18706 mips_classify_branch_p6600 (rtx_insn
*insn
)
18708 /* We ignore sequences here as they represent a filled delay slot. */
18710 || !USEFUL_INSN_P (insn
)
18711 || GET_CODE (PATTERN (insn
)) == SEQUENCE
)
18712 return UC_UNDEFINED
;
18714 if (get_attr_jal (insn
) == JAL_INDIRECT
/* JIC and JIALC. */
18715 || get_attr_type (insn
) == TYPE_JUMP
) /* BC. */
18718 if (CALL_P (insn
) && get_attr_jal (insn
) == JAL_DIRECT
)
18721 return UC_UNDEFINED
;
18724 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
18725 INSN and a previous instruction, avoid it by inserting nops after
18728 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
18729 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
18730 before using the value of that register. *HILO_DELAY counts the
18731 number of instructions since the last hilo hazard (that is,
18732 the number of instructions since the last MFLO or MFHI).
18734 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
18735 for the next instruction.
18737 LO_REG is an rtx for the LO register, used in dependence checking. */
18740 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
18741 rtx
*delayed_reg
, rtx lo_reg
, bool *fs_delay
)
18746 pattern
= PATTERN (insn
);
18748 /* Do not put the whole function in .set noreorder if it contains
18749 an asm statement. We don't know whether there will be hazards
18750 between the asm statement and the gcc-generated code. */
18751 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
18752 cfun
->machine
->all_noreorder_p
= false;
18754 /* Ignore zero-length instructions (barriers and the like). */
18755 ninsns
= get_attr_length (insn
) / 4;
18759 /* Work out how many nops are needed. Note that we only care about
18760 registers that are explicitly mentioned in the instruction's pattern.
18761 It doesn't matter that calls use the argument registers or that they
18762 clobber hi and lo. */
18763 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
18764 nops
= 2 - *hilo_delay
;
18765 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
18767 /* If processing a forbidden slot hazard then a NOP is required if the
18768 branch instruction was not in a sequence (as the sequence would
18769 imply it is not actually a compact branch anyway) and the current
18770 insn is not an inline asm, and can't go in a delay slot. */
18771 else if (*fs_delay
&& get_attr_can_delay (insn
) == CAN_DELAY_NO
18772 && GET_CODE (PATTERN (after
)) != SEQUENCE
18773 && GET_CODE (pattern
) != ASM_INPUT
18774 && asm_noperands (pattern
) < 0)
18776 /* The P6600's branch predictor can handle static sequences of back-to-back
18777 branches in the following cases:
18779 (1) BALC followed by any conditional compact branch
18780 (2) BALC followed by BALC
18782 Any other combinations of compact branches will incur performance
18783 penalty. Inserting a no-op only costs space as the dispatch unit will
18784 disregard the nop. */
18785 else if (TUNE_P6600
&& TARGET_CB_MAYBE
&& !optimize_size
18786 && ((mips_classify_branch_p6600 (after
) == UC_BALC
18787 && mips_classify_branch_p6600 (insn
) == UC_OTHER
)
18788 || (mips_classify_branch_p6600 (insn
) == UC_BALC
18789 && mips_classify_branch_p6600 (after
) == UC_OTHER
)))
18794 /* Insert the nops between this instruction and the previous one.
18795 Each new nop takes us further from the last hilo hazard. */
18796 *hilo_delay
+= nops
;
18798 /* Move to the next real instruction if we are inserting a NOP and this
18799 instruction is a call with debug information. The reason being that
18800 we can't separate the call from the debug info. */
18801 rtx_insn
*real_after
= after
;
18802 if (real_after
&& nops
&& CALL_P (real_after
))
18804 && (NOTE_P (NEXT_INSN (real_after
))
18805 || BARRIER_P (NEXT_INSN (real_after
))))
18806 real_after
= NEXT_INSN (real_after
);
18809 emit_insn_after (gen_hazard_nop (), real_after
);
18811 /* Set up the state for the next instruction. */
18812 *hilo_delay
+= ninsns
;
18815 if (INSN_CODE (insn
) >= 0)
18816 switch (get_attr_hazard (insn
))
18819 /* For the P6600, flag some unconditional branches as having a
18820 pseudo-forbidden slot. This will cause additional nop insertion
18821 or SEQUENCE breaking as required. This is for performance
18822 reasons not correctness. */
18826 && mips_classify_branch_p6600 (insn
) == UC_OTHER
)
18830 case HAZARD_FORBIDDEN_SLOT
:
18831 if (TARGET_CB_MAYBE
)
18840 set
= single_set (insn
);
18842 *delayed_reg
= SET_DEST (set
);
18847 /* A SEQUENCE is breakable iff the branch inside it has a compact form
18848 and the target has compact branches. */
18851 mips_breakable_sequence_p (rtx_insn
*insn
)
18853 return (insn
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
18855 && get_attr_compact_form (SEQ_BEGIN (insn
)) != COMPACT_FORM_NEVER
);
18858 /* Remove a SEQUENCE and replace it with the delay slot instruction
18859 followed by the branch and return the instruction in the delay slot.
18860 Return the first of the two new instructions.
18861 Subroutine of mips_reorg_process_insns. */
18864 mips_break_sequence (rtx_insn
*insn
)
18866 rtx_insn
*before
= PREV_INSN (insn
);
18867 rtx_insn
*branch
= SEQ_BEGIN (insn
);
18868 rtx_insn
*ds
= SEQ_END (insn
);
18869 remove_insn (insn
);
18870 add_insn_after (ds
, before
, NULL
);
18871 add_insn_after (branch
, ds
, NULL
);
18875 /* Go through the instruction stream and insert nops where necessary.
18876 Also delete any high-part relocations whose partnering low parts
18877 are now all dead. See if the whole function can then be put into
18878 .set noreorder and .set nomacro. */
18881 mips_reorg_process_insns (void)
18883 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
18884 rtx lo_reg
, delayed_reg
;
18888 /* Force all instructions to be split into their final form. */
18889 split_all_insns_noflow ();
18891 /* Recalculate instruction lengths without taking nops into account. */
18892 cfun
->machine
->ignore_hazard_length_p
= true;
18893 shorten_branches (get_insns ());
18895 cfun
->machine
->all_noreorder_p
= true;
18897 /* We don't track MIPS16 PC-relative offsets closely enough to make
18898 a good job of "set .noreorder" code in MIPS16 mode. */
18900 cfun
->machine
->all_noreorder_p
= false;
18902 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
18903 if (!TARGET_EXPLICIT_RELOCS
)
18904 cfun
->machine
->all_noreorder_p
= false;
18906 /* Profiled functions can't be all noreorder because the profiler
18907 support uses assembler macros. */
18909 cfun
->machine
->all_noreorder_p
= false;
18911 /* Code compiled with -mfix-vr4120, -mfix-r5900, -mfix-rm7000 or
18912 -mfix-24k can't be all noreorder because we rely on the assembler
18913 to work around some errata. The R5900 target has several bugs. */
18914 if (TARGET_FIX_VR4120
18915 || TARGET_FIX_RM7000
18917 || TARGET_FIX_R5900
)
18918 cfun
->machine
->all_noreorder_p
= false;
18920 /* The same is true for -mfix-vr4130 if we might generate MFLO or
18921 MFHI instructions. Note that we avoid using MFLO and MFHI if
18922 the VR4130 MACC and DMACC instructions are available instead;
18923 see the *mfhilo_{si,di}_macc patterns. */
18924 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
18925 cfun
->machine
->all_noreorder_p
= false;
18927 mips_offset_table
htab (37);
18929 /* Make a first pass over the instructions, recording all the LO_SUMs. */
18930 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
18931 FOR_EACH_SUBINSN (subinsn
, insn
)
18932 if (USEFUL_INSN_P (subinsn
))
18934 rtx body
= PATTERN (insn
);
18935 int noperands
= asm_noperands (body
);
18936 if (noperands
>= 0)
18938 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
18939 bool *used
= XALLOCAVEC (bool, noperands
);
18940 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
18942 get_referenced_operands (string
, used
, noperands
);
18943 for (int i
= 0; i
< noperands
; ++i
)
18945 mips_record_lo_sums (ops
[i
], &htab
);
18948 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
18954 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
18957 /* Make a second pass over the instructions. Delete orphaned
18958 high-part relocations or turn them into NOPs. Avoid hazards
18959 by inserting NOPs. */
18960 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
18962 next_insn
= NEXT_INSN (insn
);
18963 if (USEFUL_INSN_P (insn
))
18965 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
18967 rtx_insn
*next_active
= next_active_insn (insn
);
18968 /* Undo delay slots to avoid bubbles if the next instruction can
18969 be placed in a forbidden slot or the cost of adding an
18970 explicit NOP in a forbidden slot is OK and if the SEQUENCE is
18971 safely breakable. */
18972 if (TARGET_CB_MAYBE
18973 && mips_breakable_sequence_p (insn
)
18974 && INSN_P (SEQ_BEGIN (insn
))
18975 && INSN_P (SEQ_END (insn
))
18977 && INSN_P (next_active
)
18978 && GET_CODE (PATTERN (next_active
)) != SEQUENCE
18979 && get_attr_can_delay (next_active
) == CAN_DELAY_YES
)
18980 || !optimize_size
))
18982 /* To hide a potential pipeline bubble, if we scan backwards
18983 from the current SEQUENCE and find that there is a load
18984 of a value that is used in the CTI and there are no
18985 dependencies between the CTI and instruction in the delay
18986 slot, break the sequence so the load delay is hidden. */
18988 CLEAR_HARD_REG_SET (uses
);
18989 note_uses (&PATTERN (SEQ_BEGIN (insn
)), record_hard_reg_uses
,
18991 HARD_REG_SET delay_sets
;
18992 CLEAR_HARD_REG_SET (delay_sets
);
18993 note_stores (PATTERN (SEQ_END (insn
)), record_hard_reg_sets
,
18996 rtx_insn
*prev
= prev_active_insn (insn
);
18998 && GET_CODE (PATTERN (prev
)) == SET
18999 && MEM_P (SET_SRC (PATTERN (prev
))))
19002 CLEAR_HARD_REG_SET (sets
);
19003 note_stores (PATTERN (prev
), record_hard_reg_sets
,
19006 /* Re-order if safe. */
19007 if (!hard_reg_set_intersect_p (delay_sets
, uses
)
19008 && hard_reg_set_intersect_p (uses
, sets
))
19010 next_insn
= mips_break_sequence (insn
);
19011 /* Need to process the hazards of the newly
19012 introduced instructions. */
19017 /* If we find an orphaned high-part relocation in a delay
19018 slot then we can convert to a compact branch and get
19019 the orphaned high part deleted. */
19020 if (mips_orphaned_high_part_p (&htab
, SEQ_END (insn
)))
19022 next_insn
= mips_break_sequence (insn
);
19023 /* Need to process the hazards of the newly
19024 introduced instructions. */
19029 /* If we find an orphaned high-part relocation in a delay
19030 slot, it's easier to turn that instruction into a NOP than
19031 to delete it. The delay slot will be a NOP either way. */
19032 FOR_EACH_SUBINSN (subinsn
, insn
)
19033 if (INSN_P (subinsn
))
19035 if (mips_orphaned_high_part_p (&htab
, subinsn
))
19037 PATTERN (subinsn
) = gen_nop ();
19038 INSN_CODE (subinsn
) = CODE_FOR_nop
;
19040 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
19041 &delayed_reg
, lo_reg
, &fs_delay
);
19047 /* INSN is a single instruction. Delete it if it's an
19048 orphaned high-part relocation. */
19049 if (mips_orphaned_high_part_p (&htab
, insn
))
19050 delete_insn (insn
);
19051 /* Also delete cache barriers if the last instruction
19052 was an annulled branch. INSN will not be speculatively
19054 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
19056 && JUMP_P (SEQ_BEGIN (last_insn
))
19057 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
19058 delete_insn (insn
);
19061 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
19062 &delayed_reg
, lo_reg
, &fs_delay
);
19063 /* When a compact branch introduces a forbidden slot hazard
19064 and the next useful instruction is a SEQUENCE of a jump
19065 and a non-nop instruction in the delay slot, remove the
19066 sequence and replace it with the delay slot instruction
19067 then the jump to clear the forbidden slot hazard.
19069 For the P6600, this optimisation solves the performance
19070 penalty associated with BALC followed by a delay slot
19071 branch. We do not set fs_delay as we do not want
19072 the full logic of a forbidden slot; the penalty exists
19073 only against branches not the full class of forbidden
19074 slot instructions. */
19076 if (fs_delay
|| (TUNE_P6600
19078 && mips_classify_branch_p6600 (insn
)
19081 /* Search onwards from the current position looking for
19082 a SEQUENCE. We are looking for pipeline hazards here
19083 and do not need to worry about labels or barriers as
19084 the optimization only undoes delay slot filling which
19085 only affects the order of the branch and its delay
19087 rtx_insn
*next
= next_active_insn (insn
);
19089 && USEFUL_INSN_P (next
)
19090 && GET_CODE (PATTERN (next
)) == SEQUENCE
19091 && mips_breakable_sequence_p (next
))
19094 next_insn
= mips_break_sequence (next
);
19095 /* Need to process the hazards of the newly
19096 introduced instructions. */
19107 /* Return true if the function has a long branch instruction. */
19110 mips_has_long_branch_p (void)
19112 rtx_insn
*insn
, *subinsn
;
19115 /* We need up-to-date instruction lengths. */
19116 shorten_branches (get_insns ());
19118 /* Look for a branch that is longer than normal. The normal length for
19119 non-MIPS16 branches is 8, because the length includes the delay slot.
19120 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
19121 but they have no delay slot. */
19122 normal_length
= (TARGET_MIPS16
? 4 : 8);
19123 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19124 FOR_EACH_SUBINSN (subinsn
, insn
)
19125 if (JUMP_P (subinsn
)
19126 && get_attr_length (subinsn
) > normal_length
19127 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
19133 /* If we are using a GOT, but have not decided to use a global pointer yet,
19134 see whether we need one to implement long branches. Convert the ghost
19135 global-pointer instructions into real ones if so. */
19138 mips_expand_ghost_gp_insns (void)
19140 /* Quick exit if we already know that we will or won't need a
19142 if (!TARGET_USE_GOT
19143 || cfun
->machine
->global_pointer
== INVALID_REGNUM
19144 || mips_must_initialize_gp_p ())
19147 /* Run a full check for long branches. */
19148 if (!mips_has_long_branch_p ())
19151 /* We've now established that we need $gp. */
19152 cfun
->machine
->must_initialize_gp_p
= true;
19153 split_all_insns_noflow ();
19158 /* Subroutine of mips_reorg to manage passes that require DF. */
19161 mips_df_reorg (void)
19163 /* Create def-use chains. */
19164 df_set_flags (DF_EQ_NOTES
);
19165 df_chain_add_problem (DF_UD_CHAIN
);
19168 if (TARGET_RELAX_PIC_CALLS
)
19169 mips_annotate_pic_calls ();
19171 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
19172 r10k_insert_cache_barriers ();
19174 df_finish_pass (false);
19177 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
19178 called very late in mips_reorg, but the caller is required to run
19179 mips16_lay_out_constants on the result. */
19182 mips16_load_branch_target (rtx dest
, rtx src
)
19184 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
19188 if (mips_cfun_has_cprestore_slot_p ())
19189 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
19191 mips_emit_move (dest
, pic_offset_table_rtx
);
19192 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
19193 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
19194 emit_insn (gen_rtx_SET (dest
,
19195 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
19196 emit_insn (gen_rtx_SET (dest
, gen_rtx_LO_SUM (Pmode
, dest
, low
)));
19200 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
19201 mips_emit_move (dest
, src
);
19205 /* If we're compiling a MIPS16 function, look for and split any long branches.
19206 This must be called after all other instruction modifications in
19210 mips16_split_long_branches (void)
19212 bool something_changed
;
19214 if (!TARGET_MIPS16
)
19217 /* Loop until the alignments for all targets are sufficient. */
19221 rtx_jump_insn
*jump_insn
;
19223 shorten_branches (get_insns ());
19224 something_changed
= false;
19225 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19226 if ((jump_insn
= dyn_cast
<rtx_jump_insn
*> (insn
))
19227 && get_attr_length (jump_insn
) > 4
19228 && (any_condjump_p (jump_insn
) || any_uncondjump_p (jump_insn
)))
19230 rtx old_label
, temp
, saved_temp
;
19231 rtx_code_label
*new_label
;
19233 rtx_insn
*jump
, *jump_sequence
;
19237 /* Free up a MIPS16 register by saving it in $1. */
19238 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
19239 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
19240 emit_move_insn (saved_temp
, temp
);
19242 /* Load the branch target into TEMP. */
19243 old_label
= JUMP_LABEL (jump_insn
);
19244 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
19245 mips16_load_branch_target (temp
, target
);
19247 /* Jump to the target and restore the register's
19249 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
19250 (temp
, temp
, saved_temp
)));
19251 JUMP_LABEL (jump
) = old_label
;
19252 LABEL_NUSES (old_label
)++;
19254 /* Rewrite any symbolic references that are supposed to use
19255 a PC-relative constant pool. */
19256 mips16_lay_out_constants (false);
19258 if (simplejump_p (jump_insn
))
19259 /* We're going to replace INSN with a longer form. */
19263 /* Create a branch-around label for the original
19265 new_label
= gen_label_rtx ();
19266 emit_label (new_label
);
19269 jump_sequence
= get_insns ();
19272 emit_insn_after (jump_sequence
, jump_insn
);
19274 invert_jump (jump_insn
, new_label
, false);
19276 delete_insn (jump_insn
);
19277 something_changed
= true;
19280 while (something_changed
);
19283 /* Insert a `.insn' assembly pseudo-op after any labels followed by
19284 a MIPS16 constant pool or no insn at all. This is needed so that
19285 targets that have been optimized away are still marked as code
19286 and therefore branches that remained and point to them are known
19287 to retain the ISA mode and as such can be successfully assembled. */
19290 mips_insert_insn_pseudos (void)
19292 bool insn_pseudo_needed
= TRUE
;
19295 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
19296 switch (GET_CODE (insn
))
19299 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
19300 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE
)
19302 insn_pseudo_needed
= TRUE
;
19305 /* Fall through. */
19308 case JUMP_TABLE_DATA
:
19309 insn_pseudo_needed
= FALSE
;
19312 if (insn_pseudo_needed
)
19314 emit_insn_after (gen_insn_pseudo (), insn
);
19315 insn_pseudo_needed
= FALSE
;
19323 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
19328 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
19329 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
19330 to date if the CFG is available. */
19331 if (mips_cfg_in_reorg ())
19332 compute_bb_for_insn ();
19333 mips16_lay_out_constants (true);
19334 if (mips_cfg_in_reorg ())
19337 free_bb_for_insn ();
19341 /* We use a machine specific pass to do a second machine dependent reorg
19342 pass after delay branch scheduling. */
19344 static unsigned int
19345 mips_machine_reorg2 (void)
19347 mips_reorg_process_insns ();
19349 && TARGET_EXPLICIT_RELOCS
19351 && TARGET_VR4130_ALIGN
)
19352 vr4130_align_insns ();
19353 if (mips_expand_ghost_gp_insns ())
19354 /* The expansion could invalidate some of the VR4130 alignment
19355 optimizations, but this should be an extremely rare case anyhow. */
19356 mips_reorg_process_insns ();
19357 mips16_split_long_branches ();
19358 mips_insert_insn_pseudos ();
19364 const pass_data pass_data_mips_machine_reorg2
=
19366 RTL_PASS
, /* type */
19367 "mach2", /* name */
19368 OPTGROUP_NONE
, /* optinfo_flags */
19369 TV_MACH_DEP
, /* tv_id */
19370 0, /* properties_required */
19371 0, /* properties_provided */
19372 0, /* properties_destroyed */
19373 0, /* todo_flags_start */
19374 0, /* todo_flags_finish */
19377 class pass_mips_machine_reorg2
: public rtl_opt_pass
19380 pass_mips_machine_reorg2(gcc::context
*ctxt
)
19381 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
19384 /* opt_pass methods: */
19385 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
19387 }; // class pass_mips_machine_reorg2
19389 } // anon namespace
19392 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
19394 return new pass_mips_machine_reorg2 (ctxt
);
19398 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
19399 in order to avoid duplicating too much logic from elsewhere. */
19402 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
19403 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
19406 rtx this_rtx
, temp1
, temp2
, fnaddr
;
19408 bool use_sibcall_p
;
19410 /* Pretend to be a post-reload pass while generating rtl. */
19411 reload_completed
= 1;
19413 /* Mark the end of the (empty) prologue. */
19414 emit_note (NOTE_INSN_PROLOGUE_END
);
19416 /* Determine if we can use a sibcall to call FUNCTION directly. */
19417 fnaddr
= XEXP (DECL_RTL (function
), 0);
19418 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
19419 && const_call_insn_operand (fnaddr
, Pmode
));
19421 /* Determine if we need to load FNADDR from the GOT. */
19423 && (mips_got_symbol_type_p
19424 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
19426 /* Pick a global pointer. Use a call-clobbered register if
19427 TARGET_CALL_SAVED_GP. */
19428 cfun
->machine
->global_pointer
19429 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
19430 cfun
->machine
->must_initialize_gp_p
= true;
19431 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
19433 /* Set up the global pointer for n32 or n64 abicalls. */
19434 mips_emit_loadgp ();
19437 /* We need two temporary registers in some cases. */
19438 temp1
= gen_rtx_REG (Pmode
, 2);
19439 temp2
= gen_rtx_REG (Pmode
, 3);
19441 /* Find out which register contains the "this" pointer. */
19442 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
19443 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
19445 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
19447 /* Add DELTA to THIS_RTX. */
19450 rtx offset
= GEN_INT (delta
);
19451 if (!SMALL_OPERAND (delta
))
19453 mips_emit_move (temp1
, offset
);
19456 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
19459 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
19460 if (vcall_offset
!= 0)
19464 /* Set TEMP1 to *THIS_RTX. */
19465 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
19467 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
19468 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
19470 /* Load the offset and add it to THIS_RTX. */
19471 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
19472 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
19475 /* Jump to the target function. Use a sibcall if direct jumps are
19476 allowed, otherwise load the address into a register first. */
19479 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
19480 SIBLING_CALL_P (insn
) = 1;
19484 /* This is messy. GAS treats "la $25,foo" as part of a call
19485 sequence and may allow a global "foo" to be lazily bound.
19486 The general move patterns therefore reject this combination.
19488 In this context, lazy binding would actually be OK
19489 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
19490 TARGET_CALL_SAVED_GP; see mips_load_call_address.
19491 We must therefore load the address via a temporary
19492 register if mips_dangerous_for_la25_p.
19494 If we jump to the temporary register rather than $25,
19495 the assembler can use the move insn to fill the jump's
19498 We can use the same technique for MIPS16 code, where $25
19499 is not a valid JR register. */
19500 if (TARGET_USE_PIC_FN_ADDR_REG
19502 && !mips_dangerous_for_la25_p (fnaddr
))
19503 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
19504 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
19506 if (TARGET_USE_PIC_FN_ADDR_REG
19507 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
19508 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
19509 emit_jump_insn (gen_indirect_jump (temp1
));
19512 /* Run just enough of rest_of_compilation. This sequence was
19513 "borrowed" from alpha.c. */
19514 insn
= get_insns ();
19515 split_all_insns_noflow ();
19516 mips16_lay_out_constants (true);
19517 shorten_branches (insn
);
19518 final_start_function (insn
, file
, 1);
19519 final (insn
, file
, 1);
19520 final_end_function ();
19522 /* Clean up the vars set above. Note that final_end_function resets
19523 the global pointer for us. */
19524 reload_completed
= 0;
19528 /* The last argument passed to mips_set_compression_mode,
19529 or negative if the function hasn't been called yet. */
19530 static unsigned int old_compression_mode
= -1;
19532 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
19533 which is either MASK_MIPS16 or MASK_MICROMIPS. */
19536 mips_set_compression_mode (unsigned int compression_mode
)
19539 if (compression_mode
== old_compression_mode
)
19542 /* Restore base settings of various flags. */
19543 target_flags
= mips_base_target_flags
;
19544 flag_schedule_insns
= mips_base_schedule_insns
;
19545 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
19546 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
19547 str_align_loops
= mips_base_align_loops
;
19548 str_align_jumps
= mips_base_align_jumps
;
19549 str_align_functions
= mips_base_align_functions
;
19550 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
19551 target_flags
|= compression_mode
;
19553 if (compression_mode
& MASK_MIPS16
)
19555 /* Switch to MIPS16 mode. */
19556 target_flags
|= MASK_MIPS16
;
19558 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
19559 target_flags
&= ~MASK_SYNCI
;
19561 /* Don't run the scheduler before reload, since it tends to
19562 increase register pressure. */
19563 flag_schedule_insns
= 0;
19565 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
19566 the whole function to be in a single section. */
19567 flag_reorder_blocks_and_partition
= 0;
19569 /* Don't move loop invariants, because it tends to increase
19570 register pressure. It also introduces an extra move in cases
19571 where the constant is the first operand in a two-operand binary
19572 instruction, or when it forms a register argument to a functon
19574 flag_move_loop_invariants
= 0;
19576 target_flags
|= MASK_EXPLICIT_RELOCS
;
19578 /* Experiments suggest we get the best overall section-anchor
19579 results from using the range of an unextended LW or SW. Code
19580 that makes heavy use of byte or short accesses can do better
19581 with ranges of 0...31 and 0...63 respectively, but most code is
19582 sensitive to the range of LW and SW instead. */
19583 targetm
.min_anchor_offset
= 0;
19584 targetm
.max_anchor_offset
= 127;
19586 targetm
.const_anchor
= 0;
19588 /* MIPS16 has no BAL instruction. */
19589 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
19591 /* The R4000 errata don't apply to any known MIPS16 cores.
19592 It's simpler to make the R4000 fixes and MIPS16 mode
19593 mutually exclusive. */
19594 target_flags
&= ~MASK_FIX_R4000
;
19596 if (flag_pic
&& !TARGET_OLDABI
)
19597 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
19600 sorry ("MIPS16 -mxgot code");
19602 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
19603 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
19606 sorry ("MSA MIPS16 code");
19610 /* Switch to microMIPS or the standard encoding. */
19612 if (TARGET_MICROMIPS
)
19613 /* Avoid branch likely. */
19614 target_flags
&= ~MASK_BRANCHLIKELY
;
19616 /* Provide default values for align_* for 64-bit targets. */
19619 if (flag_align_loops
&& !str_align_loops
)
19620 str_align_loops
= "8";
19621 if (flag_align_jumps
&& !str_align_jumps
)
19622 str_align_jumps
= "8";
19623 if (flag_align_functions
&& !str_align_functions
)
19624 str_align_functions
= "8";
19627 targetm
.min_anchor_offset
= -32768;
19628 targetm
.max_anchor_offset
= 32767;
19630 targetm
.const_anchor
= 0x8000;
19633 /* (Re)initialize MIPS target internals for new ISA. */
19634 mips_init_relocs ();
19636 if (compression_mode
& MASK_MIPS16
)
19638 if (!mips16_globals
)
19639 mips16_globals
= save_target_globals_default_opts ();
19641 restore_target_globals (mips16_globals
);
19643 else if (compression_mode
& MASK_MICROMIPS
)
19645 if (!micromips_globals
)
19646 micromips_globals
= save_target_globals_default_opts ();
19648 restore_target_globals (micromips_globals
);
19651 restore_target_globals (&default_target_globals
);
19653 old_compression_mode
= compression_mode
;
19656 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
19657 function should use the MIPS16 or microMIPS ISA and switch modes
19661 mips_set_current_function (tree fndecl
)
19663 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
19666 /* Allocate a chunk of memory for per-function machine-dependent data. */
19668 static struct machine_function
*
19669 mips_init_machine_status (void)
19671 return ggc_cleared_alloc
<machine_function
> ();
19674 /* Return the processor associated with the given ISA level, or null
19675 if the ISA isn't valid. */
19677 static const struct mips_cpu_info
*
19678 mips_cpu_info_from_isa (int isa
)
19682 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
19683 if (mips_cpu_info_table
[i
].isa
== isa
)
19684 return mips_cpu_info_table
+ i
;
19689 /* Return a mips_cpu_info entry determined by an option valued
19692 static const struct mips_cpu_info
*
19693 mips_cpu_info_from_opt (int opt
)
19697 case MIPS_ARCH_OPTION_FROM_ABI
:
19698 /* 'from-abi' selects the most compatible architecture for the
19699 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
19700 ABIs. For the EABIs, we have to decide whether we're using
19701 the 32-bit or 64-bit version. */
19702 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
19703 : ABI_NEEDS_64BIT_REGS
? 3
19704 : (TARGET_64BIT
? 3 : 1));
19706 case MIPS_ARCH_OPTION_NATIVE
:
19707 gcc_unreachable ();
19710 return &mips_cpu_info_table
[opt
];
19714 /* Return a default mips_cpu_info entry, given that no -march= option
19715 was explicitly specified. */
19717 static const struct mips_cpu_info
*
19718 mips_default_arch (void)
19720 #if defined (MIPS_CPU_STRING_DEFAULT)
19722 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
19723 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
19724 return mips_cpu_info_table
+ i
;
19725 gcc_unreachable ();
19726 #elif defined (MIPS_ISA_DEFAULT)
19727 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
19729 /* 'from-abi' makes a good default: you get whatever the ABI
19731 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
19735 /* Set up globals to generate code for the ISA or processor
19736 described by INFO. */
19739 mips_set_architecture (const struct mips_cpu_info
*info
)
19743 mips_arch_info
= info
;
19744 mips_arch
= info
->cpu
;
19745 mips_isa
= info
->isa
;
19749 mips_isa_rev
= (mips_isa
& 31) + 1;
19753 /* Likewise for tuning. */
19756 mips_set_tune (const struct mips_cpu_info
*info
)
19760 mips_tune_info
= info
;
19761 mips_tune
= info
->cpu
;
19765 /* Implement TARGET_OPTION_OVERRIDE. */
19768 mips_option_override (void)
19770 int i
, start
, regno
, mode
;
19772 if (global_options_set
.x_mips_isa_option
)
19773 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
19775 #ifdef SUBTARGET_OVERRIDE_OPTIONS
19776 SUBTARGET_OVERRIDE_OPTIONS
;
19779 /* MIPS16 and microMIPS cannot coexist. */
19780 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
19781 error ("unsupported combination: %s", "-mips16 -mmicromips");
19783 /* Prohibit Paired-Single and MSA combination. This is software restriction
19784 rather than architectural. */
19785 if (ISA_HAS_MSA
&& TARGET_PAIRED_SINGLE_FLOAT
)
19786 error ("unsupported combination: %s", "-mmsa -mpaired-single");
19788 /* Save the base compression state and process flags as though we
19789 were generating uncompressed code. */
19790 mips_base_compression_flags
= TARGET_COMPRESSION
;
19791 target_flags
&= ~TARGET_COMPRESSION
;
19793 /* -mno-float overrides -mhard-float and -msoft-float. */
19794 if (TARGET_NO_FLOAT
)
19796 target_flags
|= MASK_SOFT_FLOAT_ABI
;
19797 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
19800 if (TARGET_FLIP_MIPS16
)
19801 TARGET_INTERLINK_COMPRESSED
= 1;
19803 /* Set the small data limit. */
19804 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
19806 : MIPS_DEFAULT_GVALUE
);
19808 /* The following code determines the architecture and register size.
19809 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
19810 The GAS and GCC code should be kept in sync as much as possible. */
19812 if (global_options_set
.x_mips_arch_option
)
19813 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
19815 if (mips_isa_option_info
!= 0)
19817 if (mips_arch_info
== 0)
19818 mips_set_architecture (mips_isa_option_info
);
19819 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
19820 error ("%<-%s%> conflicts with the other architecture options, "
19821 "which specify a %s processor",
19822 mips_isa_option_info
->name
,
19823 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
19826 if (mips_arch_info
== 0)
19827 mips_set_architecture (mips_default_arch ());
19829 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
19830 error ("%<-march=%s%> is not compatible with the selected ABI",
19831 mips_arch_info
->name
);
19833 /* Optimize for mips_arch, unless -mtune selects a different processor. */
19834 if (global_options_set
.x_mips_tune_option
)
19835 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
19837 if (mips_tune_info
== 0)
19838 mips_set_tune (mips_arch_info
);
19840 if ((target_flags_explicit
& MASK_64BIT
) != 0)
19842 /* The user specified the size of the integer registers. Make sure
19843 it agrees with the ABI and ISA. */
19844 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
19845 error ("%<-mgp64%> used with a 32-bit processor");
19846 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
19847 error ("%<-mgp32%> used with a 64-bit ABI");
19848 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
19849 error ("%<-mgp64%> used with a 32-bit ABI");
19853 /* Infer the integer register size from the ABI and processor.
19854 Restrict ourselves to 32-bit registers if that's all the
19855 processor has, or if the ABI cannot handle 64-bit registers. */
19856 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
19857 target_flags
&= ~MASK_64BIT
;
19859 target_flags
|= MASK_64BIT
;
19862 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
19864 if (mips_isa_rev
>= 6 && !TARGET_FLOAT64
)
19865 error ("the %qs architecture does not support %<-mfp32%>",
19866 mips_arch_info
->name
);
19867 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
19868 error ("unsupported combination: %s", "-mfp64 -msingle-float");
19869 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
19870 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
19871 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
19873 if (!ISA_HAS_MXHC1
)
19874 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
19875 " the target supports the mfhc1 and mthc1 instructions");
19876 else if (mips_abi
!= ABI_32
)
19877 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
19883 /* -msingle-float selects 32-bit float registers. On r6 and later,
19884 -mdouble-float selects 64-bit float registers, since the old paired
19885 register model is not supported. In other cases the float registers
19886 should be the same size as the integer ones. */
19887 if (mips_isa_rev
>= 6 && TARGET_DOUBLE_FLOAT
&& !TARGET_FLOATXX
)
19888 target_flags
|= MASK_FLOAT64
;
19889 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
19890 target_flags
|= MASK_FLOAT64
;
19891 else if (mips_abi
== ABI_32
&& ISA_HAS_MSA
&& !TARGET_FLOATXX
)
19892 target_flags
|= MASK_FLOAT64
;
19894 target_flags
&= ~MASK_FLOAT64
;
19897 if (mips_abi
!= ABI_32
&& TARGET_FLOATXX
)
19898 error ("%<-mfpxx%> can only be used with the o32 ABI");
19899 else if (TARGET_FLOAT64
&& TARGET_FLOATXX
)
19900 error ("unsupported combination: %s", "-mfp64 -mfpxx");
19901 else if (ISA_MIPS1
&& !TARGET_FLOAT32
)
19902 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info
->name
);
19903 else if (TARGET_FLOATXX
&& !mips_lra_flag
)
19904 error ("%<-mfpxx%> requires %<-mlra%>");
19906 /* End of code shared with GAS. */
19908 /* The R5900 FPU only supports single precision. */
19909 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
19910 error ("unsupported combination: %s",
19911 "-march=r5900 -mhard-float -mdouble-float");
19913 /* If a -mlong* option was given, check that it matches the ABI,
19914 otherwise infer the -mlong* setting from the other options. */
19915 if ((target_flags_explicit
& MASK_LONG64
) != 0)
19919 if (mips_abi
== ABI_N32
)
19920 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
19921 else if (mips_abi
== ABI_32
)
19922 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
19923 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
19924 /* We have traditionally allowed non-abicalls code to use
19925 an LP64 form of o64. However, it would take a bit more
19926 effort to support the combination of 32-bit GOT entries
19927 and 64-bit pointers, so we treat the abicalls case as
19929 error ("the combination of %qs and %qs is incompatible with %qs",
19930 "-mabi=o64", "-mabicalls", "-mlong64");
19934 if (mips_abi
== ABI_64
)
19935 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
19940 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
19941 target_flags
|= MASK_LONG64
;
19943 target_flags
&= ~MASK_LONG64
;
19946 if (!TARGET_OLDABI
)
19947 flag_pcc_struct_return
= 0;
19949 /* Decide which rtx_costs structure to use. */
19951 mips_cost
= &mips_rtx_cost_optimize_size
;
19953 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
19955 /* If the user hasn't specified a branch cost, use the processor's
19957 if (mips_branch_cost
== 0)
19958 mips_branch_cost
= mips_cost
->branch_cost
;
19960 /* If neither -mbranch-likely nor -mno-branch-likely was given
19961 on the command line, set MASK_BRANCHLIKELY based on the target
19962 architecture and tuning flags. Annulled delay slots are a
19963 size win, so we only consider the processor-specific tuning
19964 for !optimize_size. */
19965 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
19967 if (ISA_HAS_BRANCHLIKELY
19969 && (mips_tune_info
->tune_flags
19970 & PTF_AVOID_BRANCHLIKELY_SIZE
) == 0)
19973 && (mips_tune_info
->tune_flags
19974 & PTF_AVOID_BRANCHLIKELY_SPEED
) == 0)
19975 || (mips_tune_info
->tune_flags
19976 & PTF_AVOID_BRANCHLIKELY_ALWAYS
) == 0))
19977 target_flags
|= MASK_BRANCHLIKELY
;
19979 target_flags
&= ~MASK_BRANCHLIKELY
;
19981 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
19982 warning (0, "the %qs architecture does not support branch-likely"
19983 " instructions", mips_arch_info
->name
);
19985 /* If the user hasn't specified -mimadd or -mno-imadd set
19986 MASK_IMADD based on the target architecture and tuning
19988 if ((target_flags_explicit
& MASK_IMADD
) == 0)
19990 if (ISA_HAS_MADD_MSUB
&&
19991 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
19992 target_flags
|= MASK_IMADD
;
19994 target_flags
&= ~MASK_IMADD
;
19996 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
19997 warning (0, "the %qs architecture does not support madd or msub"
19998 " instructions", mips_arch_info
->name
);
20000 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
20001 line, set MASK_ODD_SPREG based on the ISA and ABI. */
20002 if ((target_flags_explicit
& MASK_ODD_SPREG
) == 0)
20004 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
20005 if (!ISA_HAS_ODD_SPREG
|| TARGET_FLOATXX
)
20006 target_flags
&= ~MASK_ODD_SPREG
;
20008 target_flags
|= MASK_ODD_SPREG
;
20010 else if (TARGET_ODD_SPREG
&& !ISA_HAS_ODD_SPREG
)
20011 warning (0, "the %qs architecture does not support odd single-precision"
20012 " registers", mips_arch_info
->name
);
20014 if (!TARGET_ODD_SPREG
&& TARGET_64BIT
)
20016 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
20017 /* Allow compilation to continue further even though invalid output
20018 will be produced. */
20019 target_flags
|= MASK_ODD_SPREG
;
20022 if (!ISA_HAS_COMPACT_BRANCHES
&& mips_cb
== MIPS_CB_ALWAYS
)
20024 error ("unsupported combination: %qs%s %s",
20025 mips_arch_info
->name
, TARGET_MICROMIPS
? " -mmicromips" : "",
20026 "-mcompact-branches=always");
20028 else if (!ISA_HAS_DELAY_SLOTS
&& mips_cb
== MIPS_CB_NEVER
)
20030 error ("unsupported combination: %qs%s %s",
20031 mips_arch_info
->name
, TARGET_MICROMIPS
? " -mmicromips" : "",
20032 "-mcompact-branches=never");
20035 /* Require explicit relocs for MIPS R6 onwards. This enables simplification
20036 of the compact branch and jump support through the backend. */
20037 if (!TARGET_EXPLICIT_RELOCS
&& mips_isa_rev
>= 6)
20039 error ("unsupported combination: %qs %s",
20040 mips_arch_info
->name
, "-mno-explicit-relocs");
20043 /* The effect of -mabicalls isn't defined for the EABI. */
20044 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
20046 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
20047 target_flags
&= ~MASK_ABICALLS
;
20050 /* PIC requires -mabicalls. */
20053 if (mips_abi
== ABI_EABI
)
20054 error ("cannot generate position-independent code for %qs",
20056 else if (!TARGET_ABICALLS
)
20057 error ("position-independent code requires %qs", "-mabicalls");
20060 if (TARGET_ABICALLS_PIC2
)
20061 /* We need to set flag_pic for executables as well as DSOs
20062 because we may reference symbols that are not defined in
20063 the final executable. (MIPS does not use things like
20064 copy relocs, for example.)
20066 There is a body of code that uses __PIC__ to distinguish
20067 between -mabicalls and -mno-abicalls code. The non-__PIC__
20068 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
20069 long as any indirect jumps use $25. */
20072 /* -mvr4130-align is a "speed over size" optimization: it usually produces
20073 faster code, but at the expense of more nops. Enable it at -O3 and
20075 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
20076 target_flags
|= MASK_VR4130_ALIGN
;
20078 /* Prefer a call to memcpy over inline code when optimizing for size,
20079 though see MOVE_RATIO in mips.h. */
20080 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
20081 target_flags
|= MASK_MEMCPY
;
20083 /* If we have a nonzero small-data limit, check that the -mgpopt
20084 setting is consistent with the other target flags. */
20085 if (mips_small_data_threshold
> 0)
20089 if (!TARGET_EXPLICIT_RELOCS
)
20090 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
20092 TARGET_LOCAL_SDATA
= false;
20093 TARGET_EXTERN_SDATA
= false;
20097 if (TARGET_VXWORKS_RTP
)
20098 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
20100 if (TARGET_ABICALLS
)
20101 warning (0, "cannot use small-data accesses for %qs",
20106 /* Set NaN and ABS defaults. */
20107 if (mips_nan
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
20108 mips_nan
= MIPS_IEEE_754_2008
;
20109 if (mips_abs
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
20110 mips_abs
= MIPS_IEEE_754_2008
;
20112 /* Check for IEEE 754 legacy/2008 support. */
20113 if ((mips_nan
== MIPS_IEEE_754_LEGACY
20114 || mips_abs
== MIPS_IEEE_754_LEGACY
)
20115 && !ISA_HAS_IEEE_754_LEGACY
)
20116 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
20117 mips_arch_info
->name
,
20118 mips_nan
== MIPS_IEEE_754_LEGACY
? "nan" : "abs");
20120 if ((mips_nan
== MIPS_IEEE_754_2008
20121 || mips_abs
== MIPS_IEEE_754_2008
)
20122 && !ISA_HAS_IEEE_754_2008
)
20123 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
20124 mips_arch_info
->name
,
20125 mips_nan
== MIPS_IEEE_754_2008
? "nan" : "abs");
20127 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
20128 for all its floating point. */
20129 if (mips_nan
!= MIPS_IEEE_754_2008
)
20131 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
20132 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
20133 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
20136 /* Make sure that the user didn't turn off paired single support when
20137 MIPS-3D support is requested. */
20139 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
20140 && !TARGET_PAIRED_SINGLE_FLOAT
)
20141 error ("%<-mips3d%> requires %<-mpaired-single%>");
20143 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
20145 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
20147 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
20148 and TARGET_HARD_FLOAT_ABI are both true. */
20149 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
20151 error ("%qs must be used with %qs",
20152 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
20153 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
20154 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
20158 /* Make sure that when ISA_HAS_MSA is true, TARGET_FLOAT64 and
20159 TARGET_HARD_FLOAT_ABI and both true. */
20160 if (ISA_HAS_MSA
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
20161 error ("%<-mmsa%> must be used with %<-mfp64%> and %<-mhard-float%>");
20163 /* Make sure that -mpaired-single is only used on ISAs that support it.
20164 We must disable it otherwise since it relies on other ISA properties
20165 like ISA_HAS_8CC having their normal values. */
20166 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
20168 error ("the %qs architecture does not support paired-single"
20169 " instructions", mips_arch_info
->name
);
20170 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
20174 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
20175 && !TARGET_CACHE_BUILTIN
)
20177 error ("%qs requires a target that provides the %qs instruction",
20178 "-mr10k-cache-barrier", "cache");
20179 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
20182 /* If TARGET_DSPR2, enable TARGET_DSP. */
20186 if (TARGET_DSP
&& mips_isa_rev
>= 6)
20188 error ("the %qs architecture does not support DSP instructions",
20189 mips_arch_info
->name
);
20190 TARGET_DSP
= false;
20191 TARGET_DSPR2
= false;
20194 /* Make sure that when TARGET_LOONGSON_MMI is true, TARGET_HARD_FLOAT_ABI
20195 is true. In o32 pairs of floating-point registers provide 64-bit
20197 if (TARGET_LOONGSON_MMI
&& !TARGET_HARD_FLOAT_ABI
)
20198 error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>");
20200 /* If TARGET_LOONGSON_EXT2, enable TARGET_LOONGSON_EXT. */
20201 if (TARGET_LOONGSON_EXT2
)
20203 /* Make sure that when TARGET_LOONGSON_EXT2 is true, TARGET_LOONGSON_EXT
20204 is true. If a user explicitly says -mloongson-ext2 -mno-loongson-ext
20205 then that is an error. */
20206 if (!TARGET_LOONGSON_EXT
20207 && (target_flags_explicit
& MASK_LOONGSON_EXT
) != 0)
20208 error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
20209 target_flags
|= MASK_LOONGSON_EXT
;
20212 /* .eh_frame addresses should be the same width as a C pointer.
20213 Most MIPS ABIs support only one pointer size, so the assembler
20214 will usually know exactly how big an .eh_frame address is.
20216 Unfortunately, this is not true of the 64-bit EABI. The ABI was
20217 originally defined to use 64-bit pointers (i.e. it is LP64), and
20218 this is still the default mode. However, we also support an n32-like
20219 ILP32 mode, which is selected by -mlong32. The problem is that the
20220 assembler has traditionally not had an -mlong option, so it has
20221 traditionally not known whether we're using the ILP32 or LP64 form.
20223 As it happens, gas versions up to and including 2.19 use _32-bit_
20224 addresses for EABI64 .cfi_* directives. This is wrong for the
20225 default LP64 mode, so we can't use the directives by default.
20226 Moreover, since gas's current behavior is at odds with gcc's
20227 default behavior, it seems unwise to rely on future versions
20228 of gas behaving the same way. We therefore avoid using .cfi
20229 directives for -mlong32 as well. */
20230 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
20231 flag_dwarf2_cfi_asm
= 0;
20233 /* .cfi_* directives generate a read-only section, so fall back on
20234 manual .eh_frame creation if we need the section to be writable. */
20235 if (TARGET_WRITABLE_EH_FRAME
)
20236 flag_dwarf2_cfi_asm
= 0;
20238 mips_init_print_operand_punct ();
20240 /* Set up array to map GCC register number to debug register number.
20241 Ignore the special purpose register numbers. */
20243 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
20245 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
20246 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
20247 mips_dwarf_regno
[i
] = i
;
20249 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
20252 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
20253 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
20254 mips_dbx_regno
[i
] = i
+ start
;
20256 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
20257 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
20258 mips_dbx_regno
[i
] = i
+ start
;
20260 /* Accumulator debug registers use big-endian ordering. */
20261 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
20262 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
20263 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
20264 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
20265 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
20267 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
20268 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
20271 /* Set up mips_hard_regno_mode_ok. */
20272 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
20273 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
20274 mips_hard_regno_mode_ok_p
[mode
][regno
]
20275 = mips_hard_regno_mode_ok_uncached (regno
, (machine_mode
) mode
);
20277 /* Function to allocate machine-dependent function status. */
20278 init_machine_status
= &mips_init_machine_status
;
20280 /* Default to working around R4000 errata only if the processor
20281 was selected explicitly. */
20282 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
20283 && strcmp (mips_arch_info
->name
, "r4000") == 0)
20284 target_flags
|= MASK_FIX_R4000
;
20286 /* Default to working around R4400 errata only if the processor
20287 was selected explicitly. */
20288 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
20289 && strcmp (mips_arch_info
->name
, "r4400") == 0)
20290 target_flags
|= MASK_FIX_R4400
;
20292 /* Default to working around R5900 errata only if the processor
20293 was selected explicitly. */
20294 if ((target_flags_explicit
& MASK_FIX_R5900
) == 0
20295 && strcmp (mips_arch_info
->name
, "r5900") == 0)
20296 target_flags
|= MASK_FIX_R5900
;
20298 /* Default to working around R10000 errata only if the processor
20299 was selected explicitly. */
20300 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
20301 && strcmp (mips_arch_info
->name
, "r10000") == 0)
20302 target_flags
|= MASK_FIX_R10000
;
20304 /* Make sure that branch-likely instructions available when using
20305 -mfix-r10000. The instructions are not available if either:
20307 1. -mno-branch-likely was passed.
20308 2. The selected ISA does not support branch-likely and
20309 the command line does not include -mbranch-likely. */
20310 if (TARGET_FIX_R10000
20311 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
20312 ? !ISA_HAS_BRANCHLIKELY
20313 : !TARGET_BRANCHLIKELY
))
20314 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
20316 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
20318 warning (0, "the %qs architecture does not support the synci "
20319 "instruction", mips_arch_info
->name
);
20320 target_flags
&= ~MASK_SYNCI
;
20323 /* Only optimize PIC indirect calls if they are actually required. */
20324 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
20325 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
20327 /* Save base state of options. */
20328 mips_base_target_flags
= target_flags
;
20329 mips_base_schedule_insns
= flag_schedule_insns
;
20330 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
20331 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
20332 mips_base_align_loops
= str_align_loops
;
20333 mips_base_align_jumps
= str_align_jumps
;
20334 mips_base_align_functions
= str_align_functions
;
20336 /* Now select the ISA mode.
20338 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
20339 later if required. */
20340 mips_set_compression_mode (0);
20342 /* We register a second machine specific reorg pass after delay slot
20343 filling. Registering the pass must be done at start up. It's
20344 convenient to do it here. */
20345 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
20346 struct register_pass_info insert_pass_mips_machine_reorg2
=
20348 new_pass
, /* pass */
20349 "dbr", /* reference_pass_name */
20350 1, /* ref_pass_instance_number */
20351 PASS_POS_INSERT_AFTER
/* po_op */
20353 register_pass (&insert_pass_mips_machine_reorg2
);
20355 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
20356 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
20358 mips_register_frame_header_opt ();
20361 /* Swap the register information for registers I and I + 1, which
20362 currently have the wrong endianness. Note that the registers'
20363 fixedness and call-clobberedness might have been set on the
20367 mips_swap_registers (unsigned int i
)
20372 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
20373 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
20375 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
20376 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
20377 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
20378 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
20384 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
20387 mips_conditional_register_usage (void)
20392 /* These DSP control register fields are global. */
20393 global_regs
[CCDSP_PO_REGNUM
] = 1;
20394 global_regs
[CCDSP_SC_REGNUM
] = 1;
20397 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20398 reg_class_contents
[(int) DSP_ACC_REGS
]);
20401 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20402 reg_class_contents
[(int) MD_REGS
]);
20404 if (!TARGET_HARD_FLOAT
)
20406 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20407 reg_class_contents
[(int) FP_REGS
]);
20408 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20409 reg_class_contents
[(int) ST_REGS
]);
20411 else if (!ISA_HAS_8CC
)
20413 /* We only have a single condition-code register. We implement
20414 this by fixing all the condition-code registers and generating
20415 RTL that refers directly to ST_REG_FIRST. */
20416 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20417 reg_class_contents
[(int) ST_REGS
]);
20419 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
20420 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
20424 /* In MIPS16 mode, we prohibit the unused $s registers, since they
20425 are call-saved, and saving them via a MIPS16 register would
20426 probably waste more time than just reloading the value.
20428 We permit the $t temporary registers when optimizing for speed
20429 but not when optimizing for space because using them results in
20430 code that is larger (but faster) then not using them. We do
20431 allow $24 (t8) because it is used in CMP and CMPI instructions
20432 and $25 (t9) because it is used as the function call address in
20435 fixed_regs
[18] = call_used_regs
[18] = 1;
20436 fixed_regs
[19] = call_used_regs
[19] = 1;
20437 fixed_regs
[20] = call_used_regs
[20] = 1;
20438 fixed_regs
[21] = call_used_regs
[21] = 1;
20439 fixed_regs
[22] = call_used_regs
[22] = 1;
20440 fixed_regs
[23] = call_used_regs
[23] = 1;
20441 fixed_regs
[26] = call_used_regs
[26] = 1;
20442 fixed_regs
[27] = call_used_regs
[27] = 1;
20443 fixed_regs
[30] = call_used_regs
[30] = 1;
20446 fixed_regs
[8] = call_used_regs
[8] = 1;
20447 fixed_regs
[9] = call_used_regs
[9] = 1;
20448 fixed_regs
[10] = call_used_regs
[10] = 1;
20449 fixed_regs
[11] = call_used_regs
[11] = 1;
20450 fixed_regs
[12] = call_used_regs
[12] = 1;
20451 fixed_regs
[13] = call_used_regs
[13] = 1;
20452 fixed_regs
[14] = call_used_regs
[14] = 1;
20453 fixed_regs
[15] = call_used_regs
[15] = 1;
20456 /* Do not allow HI and LO to be treated as register operands.
20457 There are no MTHI or MTLO instructions (or any real need
20458 for them) and one-way registers cannot easily be reloaded. */
20459 AND_COMPL_HARD_REG_SET (operand_reg_set
,
20460 reg_class_contents
[(int) MD_REGS
]);
20462 /* $f20-$f23 are call-clobbered for n64. */
20463 if (mips_abi
== ABI_64
)
20466 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
20467 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
20469 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
20470 for n32 and o32 FP64. */
20471 if (mips_abi
== ABI_N32
20472 || (mips_abi
== ABI_32
20473 && TARGET_FLOAT64
))
20476 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
20477 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
20479 /* Make sure that double-register accumulator values are correctly
20480 ordered for the current endianness. */
20481 if (TARGET_LITTLE_ENDIAN
)
20483 unsigned int regno
;
20485 mips_swap_registers (MD_REG_FIRST
);
20486 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
20487 mips_swap_registers (regno
);
20491 /* Implement EH_USES. */
20494 mips_eh_uses (unsigned int regno
)
20496 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
20498 /* We need to force certain registers to be live in order to handle
20499 PIC long branches correctly. See mips_must_initialize_gp_p for
20501 if (mips_cfun_has_cprestore_slot_p ())
20503 if (regno
== CPRESTORE_SLOT_REGNUM
)
20508 if (cfun
->machine
->global_pointer
== regno
)
20516 /* Implement EPILOGUE_USES. */
20519 mips_epilogue_uses (unsigned int regno
)
20521 /* Say that the epilogue uses the return address register. Note that
20522 in the case of sibcalls, the values "used by the epilogue" are
20523 considered live at the start of the called function. */
20524 if (regno
== RETURN_ADDR_REGNUM
)
20527 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
20528 See the comment above load_call<mode> for details. */
20529 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
20532 /* An interrupt handler must preserve some registers that are
20533 ordinarily call-clobbered. */
20534 if (cfun
->machine
->interrupt_handler_p
20535 && mips_interrupt_extra_call_saved_reg_p (regno
))
20541 /* Return true if INSN needs to be wrapped in ".set noat".
20542 INSN has NOPERANDS operands, stored in OPVEC. */
20545 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
20547 if (recog_memoized (insn
) >= 0)
20549 subrtx_iterator::array_type array
;
20550 for (int i
= 0; i
< noperands
; i
++)
20551 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
20552 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
20558 /* Implement FINAL_PRESCAN_INSN. Mark MIPS16 inline constant pools
20559 as data for the purpose of disassembly. For simplicity embed the
20560 pool's initial label number in the local symbol produced so that
20561 multiple pools within a single function end up marked with unique
20562 symbols. The label number is carried by the `consttable' insn
20563 emitted at the beginning of each pool. */
20566 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
20569 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
20570 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE
)
20571 mips_set_text_contents_type (asm_out_file
, "__pool_",
20572 INTVAL (XVECEXP (PATTERN (insn
), 0, 0)),
20575 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
20576 mips_push_asm_switch (&mips_noat
);
20579 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. Reset text marking to
20580 code after a MIPS16 inline constant pool. Like with the beginning
20581 of a pool table use the pool's initial label number to keep symbols
20582 unique. The label number is carried by the `consttable_end' insn
20583 emitted at the end of each pool. */
20586 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
20587 rtx
*opvec
, int noperands
)
20589 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
20590 mips_pop_asm_switch (&mips_noat
);
20593 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
20594 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE_END
)
20595 mips_set_text_contents_type (asm_out_file
, "__pend_",
20596 INTVAL (XVECEXP (PATTERN (insn
), 0, 0)),
20600 /* Return the function that is used to expand the <u>mulsidi3 pattern.
20601 EXT_CODE is the code of the extension used. Return NULL if widening
20602 multiplication shouldn't be used. */
20605 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
20609 signed_p
= ext_code
== SIGN_EXTEND
;
20612 /* Don't use widening multiplication with MULT when we have DMUL. Even
20613 with the extension of its input operands DMUL is faster. Note that
20614 the extension is not needed for signed multiplication. In order to
20615 ensure that we always remove the redundant sign-extension in this
20616 case we still expand mulsidi3 for DMUL. */
20617 if (ISA_HAS_R6DMUL
)
20618 return signed_p
? gen_mulsidi3_64bit_r6dmul
: NULL
;
20620 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
20623 ? gen_mulsidi3_64bit_mips16
20624 : gen_umulsidi3_64bit_mips16
);
20625 if (TARGET_FIX_R4000
)
20627 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
20632 return (signed_p
? gen_mulsidi3_32bit_r6
: gen_umulsidi3_32bit_r6
);
20635 ? gen_mulsidi3_32bit_mips16
20636 : gen_umulsidi3_32bit_mips16
);
20637 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
20638 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
20639 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
20643 /* Return true if PATTERN matches the kind of instruction generated by
20644 umips_build_save_restore. SAVE_P is true for store. */
20647 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
20651 HOST_WIDE_INT first_offset
= 0;
20652 rtx first_base
= 0;
20653 unsigned int regmask
= 0;
20655 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
20657 rtx set
, reg
, mem
, this_base
;
20658 HOST_WIDE_INT this_offset
;
20660 /* Check that we have a SET. */
20661 set
= XVECEXP (pattern
, 0, n
);
20662 if (GET_CODE (set
) != SET
)
20665 /* Check that the SET is a load (if restoring) or a store
20667 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
20668 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
20671 /* Check that the address is the sum of base and a possibly-zero
20672 constant offset. Determine if the offset is in range. */
20673 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
20674 if (!REG_P (this_base
))
20679 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
20681 first_base
= this_base
;
20682 first_offset
= this_offset
;
20686 /* Check that the save slots are consecutive. */
20687 if (REGNO (this_base
) != REGNO (first_base
)
20688 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
20692 /* Check that SET's other operand is a register. */
20693 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
20697 regmask
|= 1 << REGNO (reg
);
20700 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
20701 if (regmask
== umips_swm_mask
[i
])
20707 /* Return the assembly instruction for microMIPS LWM or SWM.
20708 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
20711 umips_output_save_restore (bool save_p
, rtx pattern
)
20713 static char buffer
[300];
20716 HOST_WIDE_INT offset
;
20717 rtx base
, mem
, set
, last_set
, last_reg
;
20719 /* Parse the pattern. */
20720 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
20722 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
20724 n
= XVECLEN (pattern
, 0);
20726 set
= XVECEXP (pattern
, 0, 0);
20727 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
20728 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
20730 last_set
= XVECEXP (pattern
, 0, n
- 1);
20731 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
20733 if (REGNO (last_reg
) == 31)
20736 gcc_assert (n
<= 9);
20740 s
+= sprintf (s
, "%s,", reg_names
[16]);
20742 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
20744 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
20747 if (REGNO (last_reg
) == 31)
20748 s
+= sprintf (s
, "%s,", reg_names
[31]);
20750 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
20754 /* Return true if MEM1 and MEM2 use the same base register, and the
20755 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
20756 register into (from) which the contents of MEM1 will be loaded
20757 (stored), depending on the value of LOAD_P.
20758 SWAP_P is true when the 1st and 2nd instructions are swapped. */
20761 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
20762 rtx first_reg
, rtx mem1
, rtx mem2
)
20765 HOST_WIDE_INT offset1
, offset2
;
20767 if (!MEM_P (mem1
) || !MEM_P (mem2
))
20770 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
20771 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
20773 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
20776 /* Avoid invalid load pair instructions. */
20777 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
20780 /* We must avoid this case for anti-dependence.
20783 first_reg is $2, but the base is $3. */
20786 && REGNO (first_reg
) + 1 == REGNO (base1
))
20789 if (offset2
!= offset1
+ 4)
20792 if (!UMIPS_12BIT_OFFSET_P (offset1
))
20799 mips_load_store_bonding_p (rtx
*operands
, machine_mode mode
, bool load_p
)
20801 rtx reg1
, reg2
, mem1
, mem2
, base1
, base2
;
20802 enum reg_class rc1
, rc2
;
20803 HOST_WIDE_INT offset1
, offset2
;
20807 reg1
= operands
[0];
20808 reg2
= operands
[2];
20809 mem1
= operands
[1];
20810 mem2
= operands
[3];
20814 reg1
= operands
[1];
20815 reg2
= operands
[3];
20816 mem1
= operands
[0];
20817 mem2
= operands
[2];
20820 if (mips_address_insns (XEXP (mem1
, 0), mode
, false) == 0
20821 || mips_address_insns (XEXP (mem2
, 0), mode
, false) == 0)
20824 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
20825 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
20827 /* Base regs do not match. */
20828 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
20831 /* Either of the loads is clobbering base register. It is legitimate to bond
20832 loads if second load clobbers base register. However, hardware does not
20833 support such bonding. */
20835 && (REGNO (reg1
) == REGNO (base1
)
20836 || (REGNO (reg2
) == REGNO (base1
))))
20839 /* Loading in same registers. */
20841 && REGNO (reg1
) == REGNO (reg2
))
20844 /* The loads/stores are not of same type. */
20845 rc1
= REGNO_REG_CLASS (REGNO (reg1
));
20846 rc2
= REGNO_REG_CLASS (REGNO (reg2
));
20848 && !reg_class_subset_p (rc1
, rc2
)
20849 && !reg_class_subset_p (rc2
, rc1
))
20852 if (abs (offset1
- offset2
) != GET_MODE_SIZE (mode
))
20858 /* OPERANDS describes the operands to a pair of SETs, in the order
20859 dest1, src1, dest2, src2. Return true if the operands can be used
20860 in an LWP or SWP instruction; LOAD_P says which. */
20863 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
20865 rtx reg1
, reg2
, mem1
, mem2
;
20869 reg1
= operands
[0];
20870 reg2
= operands
[2];
20871 mem1
= operands
[1];
20872 mem2
= operands
[3];
20876 reg1
= operands
[1];
20877 reg2
= operands
[3];
20878 mem1
= operands
[0];
20879 mem2
= operands
[2];
20882 if (REGNO (reg2
) == REGNO (reg1
) + 1)
20883 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
20885 if (REGNO (reg1
) == REGNO (reg2
) + 1)
20886 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
20891 /* Return the assembly instruction for a microMIPS LWP or SWP in which
20892 the first register is REG and the first memory slot is MEM.
20893 LOAD_P is true for LWP. */
20896 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
20898 rtx ops
[] = {reg
, mem
};
20901 output_asm_insn ("lwp\t%0,%1", ops
);
20903 output_asm_insn ("swp\t%0,%1", ops
);
20906 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
20907 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
20910 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
20912 rtx reg1
, reg2
, mem1
, mem2
;
20915 reg1
= operands
[0];
20916 reg2
= operands
[2];
20917 mem1
= operands
[1];
20918 mem2
= operands
[3];
20922 reg1
= operands
[1];
20923 reg2
= operands
[3];
20924 mem1
= operands
[0];
20925 mem2
= operands
[2];
20928 if (REGNO (reg2
) == REGNO (reg1
) + 1)
20930 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
20934 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
20935 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
20938 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
20941 umips_movep_target_p (rtx reg1
, rtx reg2
)
20943 int regno1
, regno2
, pair
;
20945 static const int match
[8] = {
20946 0x00000060, /* 5, 6 */
20947 0x000000a0, /* 5, 7 */
20948 0x000000c0, /* 6, 7 */
20949 0x00200010, /* 4, 21 */
20950 0x00400010, /* 4, 22 */
20951 0x00000030, /* 4, 5 */
20952 0x00000050, /* 4, 6 */
20953 0x00000090 /* 4, 7 */
20956 if (!REG_P (reg1
) || !REG_P (reg2
))
20959 regno1
= REGNO (reg1
);
20960 regno2
= REGNO (reg2
);
20962 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
20965 pair
= (1 << regno1
) | (1 << regno2
);
20967 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
20968 if (pair
== match
[i
])
20974 /* Return the size in bytes of the trampoline code, padded to
20975 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
20976 function address immediately follow. */
20979 mips_trampoline_code_size (void)
20981 if (TARGET_USE_PIC_FN_ADDR_REG
)
20983 else if (ptr_mode
== DImode
)
20985 else if (ISA_HAS_LOAD_DELAY
)
20991 /* Implement TARGET_TRAMPOLINE_INIT. */
20994 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
20996 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
20999 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
21001 /* Work out the offsets of the pointers from the start of the
21002 trampoline code. */
21003 end_addr_offset
= mips_trampoline_code_size ();
21004 static_chain_offset
= end_addr_offset
;
21005 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
21007 /* Get pointers to the beginning and end of the code block. */
21008 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
21009 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
21011 #define OP(X) gen_int_mode (X, SImode)
21013 /* Build up the code in TRAMPOLINE. */
21015 if (TARGET_USE_PIC_FN_ADDR_REG
)
21017 /* $25 contains the address of the trampoline. Emit code of the form:
21019 l[wd] $1, target_function_offset($25)
21020 l[wd] $static_chain, static_chain_offset($25)
21023 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
21024 target_function_offset
,
21025 PIC_FUNCTION_ADDR_REGNUM
));
21026 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
21027 static_chain_offset
,
21028 PIC_FUNCTION_ADDR_REGNUM
));
21029 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
21030 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
21032 else if (ptr_mode
== DImode
)
21034 /* It's too cumbersome to create the full 64-bit address, so let's
21040 1: l[wd] $25, target_function_offset - 12($31)
21041 l[wd] $static_chain, static_chain_offset - 12($31)
21045 where 12 is the offset of "1:" from the start of the code block. */
21046 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
21047 trampoline
[i
++] = OP (MIPS_BAL (1));
21048 trampoline
[i
++] = OP (MIPS_NOP
);
21049 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
21050 target_function_offset
- 12,
21051 RETURN_ADDR_REGNUM
));
21052 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
21053 static_chain_offset
- 12,
21054 RETURN_ADDR_REGNUM
));
21055 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
21056 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
21060 /* If the target has load delays, emit:
21062 lui $1, %hi(end_addr)
21063 lw $25, %lo(end_addr + ...)($1)
21064 lw $static_chain, %lo(end_addr + ...)($1)
21070 lui $1, %hi(end_addr)
21071 lw $25, %lo(end_addr + ...)($1)
21073 lw $static_chain, %lo(end_addr + ...)($1). */
21075 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
21076 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
21077 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
21078 NULL
, false, OPTAB_WIDEN
);
21079 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
21080 NULL
, false, OPTAB_WIDEN
);
21081 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
21083 /* Emit the LUI. */
21084 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
21085 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
21086 NULL
, false, OPTAB_WIDEN
);
21088 /* Emit the load of the target function. */
21089 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
21090 target_function_offset
- end_addr_offset
,
21092 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
21093 NULL
, false, OPTAB_WIDEN
);
21095 /* Emit the JR here, if we can. */
21096 if (!ISA_HAS_LOAD_DELAY
)
21097 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
21099 /* Emit the load of the static chain register. */
21100 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
21101 static_chain_offset
- end_addr_offset
,
21103 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
21104 NULL
, false, OPTAB_WIDEN
);
21106 /* Emit the JR, if we couldn't above. */
21107 if (ISA_HAS_LOAD_DELAY
)
21109 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
21110 trampoline
[i
++] = OP (MIPS_NOP
);
21116 /* If we are using compact branches we don't have delay slots so
21117 place the instruction that was in the delay slot before the JRC
21120 if (TARGET_CB_ALWAYS
)
21123 temp
= trampoline
[i
-2];
21124 trampoline
[i
-2] = trampoline
[i
-1];
21125 trampoline
[i
-1] = temp
;
21128 /* Copy the trampoline code. Leave any padding uninitialized. */
21129 for (j
= 0; j
< i
; j
++)
21131 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
21132 mips_emit_move (mem
, trampoline
[j
]);
21135 /* Set up the static chain pointer field. */
21136 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
21137 mips_emit_move (mem
, chain_value
);
21139 /* Set up the target function field. */
21140 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
21141 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
21143 /* Flush the code part of the trampoline. */
21144 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
21145 emit_insn (gen_clear_cache (addr
, end_addr
));
21148 /* Implement FUNCTION_PROFILER. */
21150 void mips_function_profiler (FILE *file
)
21153 sorry ("mips16 function profiling");
21154 if (TARGET_LONG_CALLS
)
21156 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
21157 if (Pmode
== DImode
)
21158 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
21160 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
21162 mips_push_asm_switch (&mips_noat
);
21163 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
21164 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
21165 /* _mcount treats $2 as the static chain register. */
21166 if (cfun
->static_chain_decl
!= NULL
)
21167 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
21168 reg_names
[STATIC_CHAIN_REGNUM
]);
21169 if (TARGET_MCOUNT_RA_ADDRESS
)
21171 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
21172 ra save location. */
21173 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
21174 /* ra not saved, pass zero. */
21175 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
21177 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
21178 Pmode
== DImode
? "dla" : "la", reg_names
[12],
21179 cfun
->machine
->frame
.ra_fp_offset
,
21180 reg_names
[STACK_POINTER_REGNUM
]);
21182 if (!TARGET_NEWABI
)
21184 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
21185 TARGET_64BIT
? "dsubu" : "subu",
21186 reg_names
[STACK_POINTER_REGNUM
],
21187 reg_names
[STACK_POINTER_REGNUM
],
21188 Pmode
== DImode
? 16 : 8);
21190 if (TARGET_LONG_CALLS
)
21191 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
21193 fprintf (file
, "\tjal\t_mcount\n");
21194 mips_pop_asm_switch (&mips_noat
);
21195 /* _mcount treats $2 as the static chain register. */
21196 if (cfun
->static_chain_decl
!= NULL
)
21197 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
21201 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
21202 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
21203 when TARGET_LOONGSON_MMI is true. */
21205 static unsigned HOST_WIDE_INT
21206 mips_shift_truncation_mask (machine_mode mode
)
21208 if (TARGET_LOONGSON_MMI
&& VECTOR_MODE_P (mode
))
21211 return GET_MODE_BITSIZE (mode
) - 1;
21214 /* Implement TARGET_PREPARE_PCH_SAVE. */
21217 mips_prepare_pch_save (void)
21219 /* We are called in a context where the current compression vs.
21220 non-compression setting should be irrelevant. The question then is:
21221 which setting makes most sense at load time?
21223 The PCH is loaded before the first token is read. We should never have
21224 switched into a compression mode by that point, and thus should not have
21225 populated mips16_globals or micromips_globals. Nor can we load the
21226 entire contents of mips16_globals or micromips_globals from the PCH file,
21227 because they contain a combination of GGC and non-GGC data.
21229 There is therefore no point in trying save the GGC part of
21230 mips16_globals/micromips_globals to the PCH file, or to preserve a
21231 compression setting across the PCH save and load. The loading compiler
21232 would not have access to the non-GGC parts of mips16_globals or
21233 micromips_globals (either from the PCH file, or from a copy that the
21234 loading compiler generated itself) and would have to call target_reinit
21237 It therefore seems best to switch back to non-MIPS16 mode and
21238 non-microMIPS mode to save time, and to ensure that mips16_globals and
21239 micromips_globals remain null after a PCH load. */
21240 mips_set_compression_mode (0);
21241 mips16_globals
= 0;
21242 micromips_globals
= 0;
21245 /* Generate or test for an insn that supports a constant permutation. */
21247 #define MAX_VECT_LEN 16
21249 struct expand_vec_perm_d
21251 rtx target
, op0
, op1
;
21252 unsigned char perm
[MAX_VECT_LEN
];
21253 machine_mode vmode
;
21254 unsigned char nelt
;
21259 /* Construct (set target (vec_select op0 (parallel perm))) and
21260 return true if that's a valid instruction in the active ISA. */
21263 mips_expand_vselect (rtx target
, rtx op0
,
21264 const unsigned char *perm
, unsigned nelt
)
21266 rtx rperm
[MAX_VECT_LEN
], x
;
21270 for (i
= 0; i
< nelt
; ++i
)
21271 rperm
[i
] = GEN_INT (perm
[i
]);
21273 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
21274 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
21275 x
= gen_rtx_SET (target
, x
);
21277 insn
= emit_insn (x
);
21278 if (recog_memoized (insn
) < 0)
21280 remove_insn (insn
);
21286 /* Similar, but generate a vec_concat from op0 and op1 as well. */
21289 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
21290 const unsigned char *perm
, unsigned nelt
)
21292 machine_mode v2mode
;
21295 if (!GET_MODE_2XWIDER_MODE (GET_MODE (op0
)).exists (&v2mode
))
21297 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
21298 return mips_expand_vselect (target
, x
, perm
, nelt
);
21301 /* Recognize patterns for even-odd extraction. */
21304 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
21306 unsigned i
, odd
, nelt
= d
->nelt
;
21307 rtx t0
, t1
, t2
, t3
;
21309 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_MMI
))
21311 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
21318 for (i
= 1; i
< nelt
; ++i
)
21319 if (d
->perm
[i
] != i
* 2 + odd
)
21325 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
21326 t0
= gen_reg_rtx (d
->vmode
);
21327 t1
= gen_reg_rtx (d
->vmode
);
21331 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
21332 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
21334 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
21336 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
21340 t2
= gen_reg_rtx (d
->vmode
);
21341 t3
= gen_reg_rtx (d
->vmode
);
21342 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
21343 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
21344 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
21345 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
21347 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
21349 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
21353 gcc_unreachable ();
21358 /* Recognize patterns for the Loongson PSHUFH instruction. */
21361 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
21366 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_MMI
))
21368 if (d
->vmode
!= V4HImode
)
21373 /* Convert the selector into the packed 8-bit form for pshufh. */
21374 /* Recall that loongson is little-endian only. No big-endian
21375 adjustment required. */
21376 for (i
= mask
= 0; i
< 4; i
++)
21377 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
21378 rmask
= force_reg (SImode
, GEN_INT (mask
));
21380 if (d
->one_vector_p
)
21381 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
21384 rtx t0
, t1
, x
, merge
, rmerge
[4];
21386 t0
= gen_reg_rtx (V4HImode
);
21387 t1
= gen_reg_rtx (V4HImode
);
21388 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
21389 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
21391 for (i
= 0; i
< 4; ++i
)
21392 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
21393 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
21394 merge
= force_reg (V4HImode
, merge
);
21396 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
21397 emit_insn (gen_rtx_SET (t1
, x
));
21399 x
= gen_rtx_NOT (V4HImode
, merge
);
21400 x
= gen_rtx_AND (V4HImode
, x
, t0
);
21401 emit_insn (gen_rtx_SET (t0
, x
));
21403 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
21404 emit_insn (gen_rtx_SET (d
->target
, x
));
21410 /* Recognize broadcast patterns for the Loongson. */
21413 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
21418 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_MMI
))
21420 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
21421 if (d
->vmode
!= V8QImode
)
21423 if (!d
->one_vector_p
)
21427 for (i
= 1; i
< 8; ++i
)
21428 if (d
->perm
[i
] != elt
)
21434 /* With one interleave we put two of the desired element adjacent. */
21435 t0
= gen_reg_rtx (V8QImode
);
21437 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
21439 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
21441 /* Shuffle that one HImode element into all locations. */
21444 t1
= gen_reg_rtx (V4HImode
);
21445 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
21446 force_reg (SImode
, GEN_INT (elt
))));
21448 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
21452 /* Construct (set target (vec_select op0 (parallel selector))) and
21453 return true if that's a valid instruction in the active ISA. */
21456 mips_expand_msa_shuffle (struct expand_vec_perm_d
*d
)
21458 rtx x
, elts
[MAX_VECT_LEN
];
21466 for (i
= 0; i
< d
->nelt
; i
++)
21467 elts
[i
] = GEN_INT (d
->perm
[i
]);
21469 v
= gen_rtvec_v (d
->nelt
, elts
);
21470 x
= gen_rtx_PARALLEL (VOIDmode
, v
);
21472 if (!mips_const_vector_shuffle_set_p (x
, d
->vmode
))
21475 x
= gen_rtx_VEC_SELECT (d
->vmode
, d
->op0
, x
);
21476 x
= gen_rtx_SET (d
->target
, x
);
21478 insn
= emit_insn (x
);
21479 if (recog_memoized (insn
) < 0)
21481 remove_insn (insn
);
21488 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
21490 unsigned int i
, nelt
= d
->nelt
;
21491 unsigned char perm2
[MAX_VECT_LEN
];
21493 if (d
->one_vector_p
)
21495 /* Try interleave with alternating operands. */
21496 memcpy (perm2
, d
->perm
, sizeof(perm2
));
21497 for (i
= 1; i
< nelt
; i
+= 2)
21499 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
21504 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
21508 /* Try again with swapped operands. */
21509 for (i
= 0; i
< nelt
; ++i
)
21510 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
21511 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
21515 if (mips_expand_vpc_loongson_even_odd (d
))
21517 if (mips_expand_vpc_loongson_pshufh (d
))
21519 if (mips_expand_vpc_loongson_bcast (d
))
21521 if (mips_expand_msa_shuffle (d
))
21526 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
21529 mips_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
21530 rtx op1
, const vec_perm_indices
&sel
)
21532 struct expand_vec_perm_d d
;
21533 int i
, nelt
, which
;
21534 unsigned char orig_perm
[MAX_VECT_LEN
];
21542 gcc_assert (VECTOR_MODE_P (vmode
));
21543 d
.nelt
= nelt
= GET_MODE_NUNITS (vmode
);
21544 d
.testing_p
= !target
;
21546 /* This is overly conservative, but ensures we don't get an
21547 uninitialized warning on ORIG_PERM. */
21548 memset (orig_perm
, 0, MAX_VECT_LEN
);
21549 for (i
= which
= 0; i
< nelt
; ++i
)
21551 int ei
= sel
[i
] & (2 * nelt
- 1);
21552 which
|= (ei
< nelt
? 1 : 2);
21555 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
21563 d
.one_vector_p
= false;
21564 if (d
.testing_p
|| !rtx_equal_p (d
.op0
, d
.op1
))
21569 for (i
= 0; i
< nelt
; ++i
)
21570 d
.perm
[i
] &= nelt
- 1;
21572 d
.one_vector_p
= true;
21577 d
.one_vector_p
= true;
21583 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
21584 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
21585 if (!d
.one_vector_p
)
21586 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
21589 ok
= mips_expand_vec_perm_const_1 (&d
);
21594 ok
= mips_expand_vec_perm_const_1 (&d
);
21596 /* If we were given a two-vector permutation which just happened to
21597 have both input vectors equal, we folded this into a one-vector
21598 permutation. There are several loongson patterns that are matched
21599 via direct vec_select+vec_concat expansion, but we do not have
21600 support in mips_expand_vec_perm_const_1 to guess the adjustment
21601 that should be made for a single operand. Just try again with
21602 the original permutation. */
21603 if (!ok
&& which
== 3)
21607 d
.one_vector_p
= false;
21608 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
21609 ok
= mips_expand_vec_perm_const_1 (&d
);
21615 /* Implement TARGET_SCHED_REASSOCIATION_WIDTH. */
21618 mips_sched_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
21621 if (MSA_SUPPORTED_MODE_P (mode
))
21626 /* Expand an integral vector unpack operation. */
21629 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
21631 machine_mode imode
= GET_MODE (operands
[1]);
21632 rtx (*unpack
) (rtx
, rtx
, rtx
);
21633 rtx (*cmpFunc
) (rtx
, rtx
, rtx
);
21634 rtx tmp
, dest
, zero
;
21641 if (BYTES_BIG_ENDIAN
!= high_p
)
21642 unpack
= gen_msa_ilvl_w
;
21644 unpack
= gen_msa_ilvr_w
;
21646 cmpFunc
= gen_msa_clt_s_w
;
21650 if (BYTES_BIG_ENDIAN
!= high_p
)
21651 unpack
= gen_msa_ilvl_h
;
21653 unpack
= gen_msa_ilvr_h
;
21655 cmpFunc
= gen_msa_clt_s_h
;
21659 if (BYTES_BIG_ENDIAN
!= high_p
)
21660 unpack
= gen_msa_ilvl_b
;
21662 unpack
= gen_msa_ilvr_b
;
21664 cmpFunc
= gen_msa_clt_s_b
;
21668 gcc_unreachable ();
21674 /* Extract sign extention for each element comparing each element
21675 with immediate zero. */
21676 tmp
= gen_reg_rtx (imode
);
21677 emit_insn (cmpFunc (tmp
, operands
[1], CONST0_RTX (imode
)));
21680 tmp
= force_reg (imode
, CONST0_RTX (imode
));
21682 dest
= gen_reg_rtx (imode
);
21684 emit_insn (unpack (dest
, operands
[1], tmp
));
21685 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
21693 unpack
= gen_loongson_punpckhbh
;
21695 unpack
= gen_loongson_punpcklbh
;
21696 cmpFunc
= gen_loongson_pcmpgtb
;
21700 unpack
= gen_loongson_punpckhhw
;
21702 unpack
= gen_loongson_punpcklhw
;
21703 cmpFunc
= gen_loongson_pcmpgth
;
21706 gcc_unreachable ();
21709 zero
= force_reg (imode
, CONST0_RTX (imode
));
21714 tmp
= gen_reg_rtx (imode
);
21715 emit_insn (cmpFunc (tmp
, zero
, operands
[1]));
21718 dest
= gen_reg_rtx (imode
);
21719 emit_insn (unpack (dest
, operands
[1], tmp
));
21721 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
21724 /* Construct and return PARALLEL RTX with CONST_INTs for HIGH (high_p == TRUE)
21725 or LOW (high_p == FALSE) half of a vector for mode MODE. */
21728 mips_msa_vec_parallel_const_half (machine_mode mode
, bool high_p
)
21730 int nunits
= GET_MODE_NUNITS (mode
);
21731 rtvec v
= rtvec_alloc (nunits
/ 2);
21735 if (BYTES_BIG_ENDIAN
)
21736 base
= high_p
? 0 : nunits
/ 2;
21738 base
= high_p
? nunits
/ 2 : 0;
21740 for (i
= 0; i
< nunits
/ 2; i
++)
21741 RTVEC_ELT (v
, i
) = GEN_INT (base
+ i
);
21743 return gen_rtx_PARALLEL (VOIDmode
, v
);
21746 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
21749 mips_constant_elt_p (rtx x
)
21751 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
21754 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
21757 mips_expand_vi_broadcast (machine_mode vmode
, rtx target
, rtx elt
)
21759 struct expand_vec_perm_d d
;
21763 if (elt
!= const0_rtx
)
21764 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
21766 elt
= gen_lowpart (DImode
, elt
);
21768 t1
= gen_reg_rtx (vmode
);
21772 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
21775 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
21778 gcc_unreachable ();
21781 memset (&d
, 0, sizeof (d
));
21786 d
.nelt
= GET_MODE_NUNITS (vmode
);
21787 d
.one_vector_p
= true;
21789 ok
= mips_expand_vec_perm_const_1 (&d
);
21793 /* Return a const_int vector of VAL with mode MODE. */
21796 mips_gen_const_int_vector (machine_mode mode
, HOST_WIDE_INT val
)
21798 rtx c
= gen_int_mode (val
, GET_MODE_INNER (mode
));
21799 return gen_const_vec_duplicate (mode
, c
);
21802 /* Return a vector of repeated 4-element sets generated from
21803 immediate VAL in mode MODE. */
21806 mips_gen_const_int_vector_shuffle (machine_mode mode
, int val
)
21808 int nunits
= GET_MODE_NUNITS (mode
);
21809 int nsets
= nunits
/ 4;
21810 rtx elts
[MAX_VECT_LEN
];
21814 /* Generate a const_int vector replicating the same 4-element set
21815 from an immediate. */
21816 for (j
= 0; j
< nsets
; j
++, set
= 4 * j
)
21817 for (i
= 0; i
< 4; i
++)
21818 elts
[set
+ i
] = GEN_INT (set
+ ((val
>> (2 * i
)) & 0x3));
21820 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nunits
, elts
));
21823 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
21824 elements of VALS with zeros, copy the constant vector to TARGET. */
21827 mips_expand_vi_constant (machine_mode vmode
, unsigned nelt
,
21828 rtx target
, rtx vals
)
21830 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
21833 for (i
= 0; i
< nelt
; ++i
)
21835 rtx elem
= RTVEC_ELT (vec
, i
);
21836 if (!mips_constant_elt_p (elem
))
21837 RTVEC_ELT (vec
, i
) = CONST0_RTX (GET_MODE (elem
));
21840 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
21844 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
21847 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
21849 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
21851 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
21852 GEN_INT (one_var
)));
21855 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
21858 mips_expand_vi_general (machine_mode vmode
, machine_mode imode
,
21859 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
21861 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
21862 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
21865 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
21867 for (i
= 0; i
< nelt
; ++i
)
21869 rtx x
= XVECEXP (vals
, 0, i
);
21870 if (!mips_constant_elt_p (x
))
21871 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
21874 emit_move_insn (target
, mem
);
21877 /* Expand a vector initialization. */
21880 mips_expand_vector_init (rtx target
, rtx vals
)
21882 machine_mode vmode
= GET_MODE (target
);
21883 machine_mode imode
= GET_MODE_INNER (vmode
);
21884 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
21885 unsigned nvar
= 0, one_var
= -1u;
21886 bool all_same
= true;
21889 for (i
= 0; i
< nelt
; ++i
)
21891 x
= XVECEXP (vals
, 0, i
);
21892 if (!mips_constant_elt_p (x
))
21893 nvar
++, one_var
= i
;
21894 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
21902 rtx same
= XVECEXP (vals
, 0, 0);
21905 if (CONST_INT_P (same
) && nvar
== 0
21906 && mips_signed_immediate_p (INTVAL (same
), 10, 0))
21914 temp
= gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0));
21915 emit_move_insn (target
, temp
);
21919 gcc_unreachable ();
21922 temp
= gen_reg_rtx (imode
);
21923 if (imode
== GET_MODE (same
))
21925 else if (GET_MODE_SIZE (imode
) >= UNITS_PER_WORD
)
21926 temp2
= simplify_gen_subreg (imode
, same
, GET_MODE (same
), 0);
21928 temp2
= lowpart_subreg (imode
, same
, GET_MODE (same
));
21929 emit_move_insn (temp
, temp2
);
21937 mips_emit_move (target
, gen_rtx_VEC_DUPLICATE (vmode
, temp
));
21941 emit_insn (gen_msa_splati_w_f_scalar (target
, temp
));
21945 emit_insn (gen_msa_splati_d_f_scalar (target
, temp
));
21949 gcc_unreachable ();
21954 emit_move_insn (target
, CONST0_RTX (vmode
));
21956 for (i
= 0; i
< nelt
; ++i
)
21958 rtx temp
= gen_reg_rtx (imode
);
21959 emit_move_insn (temp
, XVECEXP (vals
, 0, i
));
21963 emit_insn (gen_vec_setv16qi (target
, temp
, GEN_INT (i
)));
21967 emit_insn (gen_vec_setv8hi (target
, temp
, GEN_INT (i
)));
21971 emit_insn (gen_vec_setv4si (target
, temp
, GEN_INT (i
)));
21975 emit_insn (gen_vec_setv2di (target
, temp
, GEN_INT (i
)));
21979 emit_insn (gen_vec_setv4sf (target
, temp
, GEN_INT (i
)));
21983 emit_insn (gen_vec_setv2df (target
, temp
, GEN_INT (i
)));
21987 gcc_unreachable ();
21994 /* Load constants from the pool, or whatever's handy. */
21997 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
22001 /* For two-part initialization, always use CONCAT. */
22004 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
22005 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
22006 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
22007 emit_insn (gen_rtx_SET (target
, x
));
22011 /* Loongson is the only cpu with vectors with more elements. */
22012 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_MMI
);
22014 /* If all values are identical, broadcast the value. */
22017 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
22021 /* If we've only got one non-variable V4HImode, use PINSRH. */
22022 if (nvar
== 1 && vmode
== V4HImode
)
22024 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
22028 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
22031 /* Expand a vector reduction. */
22034 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
22036 machine_mode vmode
= GET_MODE (in
);
22037 unsigned char perm2
[2];
22038 rtx last
, next
, fold
, x
;
22042 fold
= gen_reg_rtx (vmode
);
22046 /* Use PUL/PLU to produce { L, H } op { H, L }.
22047 By reversing the pair order, rather than a pure interleave high,
22048 we avoid erroneous exceptional conditions that we might otherwise
22049 produce from the computation of H op H. */
22052 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
22057 /* Use interleave to produce { H, L } op { H, H }. */
22058 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
22062 /* Perform the first reduction with interleave,
22063 and subsequent reductions with shifts. */
22064 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
22066 next
= gen_reg_rtx (vmode
);
22067 emit_insn (gen (next
, last
, fold
));
22070 fold
= gen_reg_rtx (vmode
);
22071 x
= force_reg (SImode
, GEN_INT (16));
22072 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
22076 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
22078 next
= gen_reg_rtx (vmode
);
22079 emit_insn (gen (next
, last
, fold
));
22082 fold
= gen_reg_rtx (vmode
);
22083 x
= force_reg (SImode
, GEN_INT (16));
22084 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
22086 next
= gen_reg_rtx (vmode
);
22087 emit_insn (gen (next
, last
, fold
));
22090 fold
= gen_reg_rtx (vmode
);
22091 x
= force_reg (SImode
, GEN_INT (8));
22092 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
22096 gcc_unreachable ();
22099 emit_insn (gen (target
, last
, fold
));
22102 /* Expand a vector minimum/maximum. */
22105 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
22106 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
22108 machine_mode vmode
= GET_MODE (target
);
22111 tc
= gen_reg_rtx (vmode
);
22112 t0
= gen_reg_rtx (vmode
);
22113 t1
= gen_reg_rtx (vmode
);
22116 emit_insn (cmp (tc
, op0
, op1
));
22118 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
22119 emit_insn (gen_rtx_SET (t0
, x
));
22121 x
= gen_rtx_NOT (vmode
, tc
);
22122 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
22123 emit_insn (gen_rtx_SET (t1
, x
));
22125 x
= gen_rtx_IOR (vmode
, t0
, t1
);
22126 emit_insn (gen_rtx_SET (target
, x
));
22129 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
22132 mips_hard_regno_caller_save_mode (unsigned int regno
,
22133 unsigned int nregs
,
22136 /* For performance, avoid saving/restoring upper parts of a register
22137 by returning MODE as save mode when the mode is known. */
22138 if (mode
== VOIDmode
)
22139 return choose_hard_reg_mode (regno
, nregs
, false);
22144 /* Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and
22145 store the result -1 or 0 in DEST. */
22148 mips_expand_msa_cmp (rtx dest
, enum rtx_code cond
, rtx op0
, rtx op1
)
22150 machine_mode cmp_mode
= GET_MODE (op0
);
22152 bool negate
= false;
22163 cond
= reverse_condition (cond
);
22176 std::swap (op0
, op1
);
22177 cond
= swap_condition (cond
);
22180 gcc_unreachable ();
22182 mips_emit_binary (cond
, dest
, op0
, op1
);
22184 emit_move_insn (dest
, gen_rtx_NOT (GET_MODE (dest
), dest
));
22199 case LTGT
: cond
= NE
; break;
22200 case UNGE
: cond
= UNLE
; std::swap (op0
, op1
); break;
22201 case UNGT
: cond
= UNLT
; std::swap (op0
, op1
); break;
22202 case LE
: unspec
= UNSPEC_MSA_FSLE
; break;
22203 case LT
: unspec
= UNSPEC_MSA_FSLT
; break;
22204 case GE
: unspec
= UNSPEC_MSA_FSLE
; std::swap (op0
, op1
); break;
22205 case GT
: unspec
= UNSPEC_MSA_FSLT
; std::swap (op0
, op1
); break;
22207 gcc_unreachable ();
22210 mips_emit_binary (cond
, dest
, op0
, op1
);
22213 rtx x
= gen_rtx_UNSPEC (GET_MODE (dest
),
22214 gen_rtvec (2, op0
, op1
), unspec
);
22215 emit_insn (gen_rtx_SET (dest
, x
));
22220 gcc_unreachable ();
22225 /* Expand VEC_COND_EXPR, where:
22226 MODE is mode of the result
22227 VIMODE equivalent integer mode
22228 OPERANDS operands of VEC_COND_EXPR. */
22231 mips_expand_vec_cond_expr (machine_mode mode
, machine_mode vimode
,
22234 rtx cond
= operands
[3];
22235 rtx cmp_op0
= operands
[4];
22236 rtx cmp_op1
= operands
[5];
22237 rtx cmp_res
= gen_reg_rtx (vimode
);
22239 mips_expand_msa_cmp (cmp_res
, GET_CODE (cond
), cmp_op0
, cmp_op1
);
22241 /* We handle the following cases:
22242 1) r = a CMP b ? -1 : 0
22243 2) r = a CMP b ? -1 : v
22244 3) r = a CMP b ? v : 0
22245 4) r = a CMP b ? v1 : v2 */
22247 /* Case (1) above. We only move the results. */
22248 if (operands
[1] == CONSTM1_RTX (vimode
)
22249 && operands
[2] == CONST0_RTX (vimode
))
22250 emit_move_insn (operands
[0], cmp_res
);
22253 rtx src1
= gen_reg_rtx (vimode
);
22254 rtx src2
= gen_reg_rtx (vimode
);
22255 rtx mask
= gen_reg_rtx (vimode
);
22258 /* Move the vector result to use it as a mask. */
22259 emit_move_insn (mask
, cmp_res
);
22261 if (register_operand (operands
[1], mode
))
22263 rtx xop1
= operands
[1];
22264 if (mode
!= vimode
)
22266 xop1
= gen_reg_rtx (vimode
);
22267 emit_move_insn (xop1
, gen_rtx_SUBREG (vimode
, operands
[1], 0));
22269 emit_move_insn (src1
, xop1
);
22273 gcc_assert (operands
[1] == CONSTM1_RTX (vimode
));
22274 /* Case (2) if the below doesn't move the mask to src2. */
22275 emit_move_insn (src1
, mask
);
22278 if (register_operand (operands
[2], mode
))
22280 rtx xop2
= operands
[2];
22281 if (mode
!= vimode
)
22283 xop2
= gen_reg_rtx (vimode
);
22284 emit_move_insn (xop2
, gen_rtx_SUBREG (vimode
, operands
[2], 0));
22286 emit_move_insn (src2
, xop2
);
22290 gcc_assert (operands
[2] == CONST0_RTX (mode
));
22291 /* Case (3) if the above didn't move the mask to src1. */
22292 emit_move_insn (src2
, mask
);
22295 /* We deal with case (4) if the mask wasn't moved to either src1 or src2.
22296 In any case, we eventually do vector mask-based copy. */
22297 bsel
= gen_rtx_IOR (vimode
,
22298 gen_rtx_AND (vimode
,
22299 gen_rtx_NOT (vimode
, mask
), src2
),
22300 gen_rtx_AND (vimode
, mask
, src1
));
22301 /* The result is placed back to a register with the mask. */
22302 emit_insn (gen_rtx_SET (mask
, bsel
));
22303 emit_move_insn (operands
[0], gen_rtx_SUBREG (mode
, mask
, 0));
22307 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
22310 mips_case_values_threshold (void)
22312 /* In MIPS16 mode using a larger case threshold generates smaller code. */
22313 if (TARGET_MIPS16
&& optimize_size
)
22316 return default_case_values_threshold ();
22319 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
22322 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
22324 if (!TARGET_HARD_FLOAT_ABI
)
22326 tree exceptions_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22327 tree fcsr_orig_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22328 tree fcsr_mod_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22329 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
22330 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
22331 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
22332 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22333 fcsr_orig_var
, get_fcsr_hold_call
);
22334 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
22335 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
22336 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22337 fcsr_mod_var
, hold_mod_val
);
22338 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
22339 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
22340 hold_assign_orig
, hold_assign_mod
);
22341 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
22342 set_fcsr_hold_call
);
22344 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
22346 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
22347 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22348 exceptions_var
, get_fcsr_update_call
);
22349 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
22350 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
22351 set_fcsr_update_call
);
22352 tree atomic_feraiseexcept
22353 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
22354 tree int_exceptions_var
= fold_convert (integer_type_node
,
22356 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
22357 1, int_exceptions_var
);
22358 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
22359 atomic_feraiseexcept_call
);
22362 /* Implement TARGET_SPILL_CLASS. */
22365 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
22366 machine_mode mode ATTRIBUTE_UNUSED
)
22373 /* Implement TARGET_LRA_P. */
22378 return mips_lra_flag
;
22381 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
22384 mips_ira_change_pseudo_allocno_class (int regno
, reg_class_t allocno_class
,
22385 reg_class_t best_class ATTRIBUTE_UNUSED
)
22387 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
22388 to memory if an FPR is present in the allocno class. It is rare that
22389 we actually need to place an integer mode value in an FPR so where
22390 possible limit the allocation to GR_REGS. This will slightly pessimize
22391 code that involves integer to/from float conversions as these will have
22392 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
22393 sometimes only partially eliminated. We choose to take this penalty
22394 in order to eliminate usage of FPRs in code that does not use floating
22397 This change has a similar effect to increasing the cost of FPR->GPR
22398 register moves for integer modes so that they are higher than the cost
22399 of memory but changing the allocno class is more reliable.
22401 This is also similar to forbidding integer mode values in FPRs entirely
22402 but this would lead to an inconsistency in the integer to/from float
22403 instructions that say integer mode values must be placed in FPRs. */
22404 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno
)) && allocno_class
== ALL_REGS
)
22406 return allocno_class
;
22409 /* Implement TARGET_PROMOTE_FUNCTION_MODE */
22411 /* This function is equivalent to default_promote_function_mode_always_promote
22412 except that it returns a promoted mode even if type is NULL_TREE. This is
22413 needed by libcalls which have no type (only a mode) such as fixed conversion
22414 routines that take a signed or unsigned char/short argument and convert it
22415 to a fixed type. */
22417 static machine_mode
22418 mips_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
22420 int *punsignedp ATTRIBUTE_UNUSED
,
22421 const_tree fntype ATTRIBUTE_UNUSED
,
22422 int for_return ATTRIBUTE_UNUSED
)
22426 if (type
!= NULL_TREE
)
22427 return promote_mode (type
, mode
, punsignedp
);
22429 unsignedp
= *punsignedp
;
22430 PROMOTE_MODE (mode
, unsignedp
, type
);
22431 *punsignedp
= unsignedp
;
22435 /* Implement TARGET_TRULY_NOOP_TRUNCATION. */
22438 mips_truly_noop_truncation (poly_uint64 outprec
, poly_uint64 inprec
)
22440 return !TARGET_64BIT
|| inprec
<= 32 || outprec
> 32;
22443 /* Implement TARGET_CONSTANT_ALIGNMENT. */
22445 static HOST_WIDE_INT
22446 mips_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
22448 if (TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
22449 return MAX (align
, BITS_PER_WORD
);
22453 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
22455 static unsigned HOST_WIDE_INT
22456 mips_asan_shadow_offset (void)
22461 /* Implement TARGET_STARTING_FRAME_OFFSET. See mips_compute_frame_info
22462 for details about the frame layout. */
22464 static HOST_WIDE_INT
22465 mips_starting_frame_offset (void)
22467 if (FRAME_GROWS_DOWNWARD
)
22469 return crtl
->outgoing_args_size
+ MIPS_GP_SAVE_AREA_SIZE
;
22472 /* Initialize the GCC target structure. */
22473 #undef TARGET_ASM_ALIGNED_HI_OP
22474 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
22475 #undef TARGET_ASM_ALIGNED_SI_OP
22476 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
22477 #undef TARGET_ASM_ALIGNED_DI_OP
22478 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
22480 #undef TARGET_OPTION_OVERRIDE
22481 #define TARGET_OPTION_OVERRIDE mips_option_override
22483 #undef TARGET_LEGITIMIZE_ADDRESS
22484 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
22486 #undef TARGET_ASM_FUNCTION_PROLOGUE
22487 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
22488 #undef TARGET_ASM_FUNCTION_EPILOGUE
22489 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
22490 #undef TARGET_ASM_SELECT_RTX_SECTION
22491 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
22492 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
22493 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
22495 #undef TARGET_SCHED_INIT
22496 #define TARGET_SCHED_INIT mips_sched_init
22497 #undef TARGET_SCHED_REORDER
22498 #define TARGET_SCHED_REORDER mips_sched_reorder
22499 #undef TARGET_SCHED_REORDER2
22500 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
22501 #undef TARGET_SCHED_VARIABLE_ISSUE
22502 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
22503 #undef TARGET_SCHED_ADJUST_COST
22504 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
22505 #undef TARGET_SCHED_ISSUE_RATE
22506 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
22507 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
22508 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
22509 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
22510 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
22511 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
22512 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
22513 mips_multipass_dfa_lookahead
22514 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
22515 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
22516 mips_small_register_classes_for_mode_p
22518 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
22519 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
22521 #undef TARGET_INSERT_ATTRIBUTES
22522 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
22523 #undef TARGET_MERGE_DECL_ATTRIBUTES
22524 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
22525 #undef TARGET_CAN_INLINE_P
22526 #define TARGET_CAN_INLINE_P mips_can_inline_p
22527 #undef TARGET_SET_CURRENT_FUNCTION
22528 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
22530 #undef TARGET_VALID_POINTER_MODE
22531 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
22532 #undef TARGET_REGISTER_MOVE_COST
22533 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
22534 #undef TARGET_REGISTER_PRIORITY
22535 #define TARGET_REGISTER_PRIORITY mips_register_priority
22536 #undef TARGET_MEMORY_MOVE_COST
22537 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
22538 #undef TARGET_RTX_COSTS
22539 #define TARGET_RTX_COSTS mips_rtx_costs
22540 #undef TARGET_ADDRESS_COST
22541 #define TARGET_ADDRESS_COST mips_address_cost
22543 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
22544 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P mips_no_speculation_in_delay_slots_p
22546 #undef TARGET_IN_SMALL_DATA_P
22547 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
22549 #undef TARGET_MACHINE_DEPENDENT_REORG
22550 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
22552 #undef TARGET_PREFERRED_RELOAD_CLASS
22553 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
22555 #undef TARGET_EXPAND_TO_RTL_HOOK
22556 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
22557 #undef TARGET_ASM_FILE_START
22558 #define TARGET_ASM_FILE_START mips_file_start
22559 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
22560 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
22561 #undef TARGET_ASM_CODE_END
22562 #define TARGET_ASM_CODE_END mips_code_end
22564 #undef TARGET_INIT_LIBFUNCS
22565 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
22567 #undef TARGET_BUILD_BUILTIN_VA_LIST
22568 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
22569 #undef TARGET_EXPAND_BUILTIN_VA_START
22570 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
22571 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
22572 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
22574 #undef TARGET_PROMOTE_FUNCTION_MODE
22575 #define TARGET_PROMOTE_FUNCTION_MODE mips_promote_function_mode
22576 #undef TARGET_FUNCTION_VALUE
22577 #define TARGET_FUNCTION_VALUE mips_function_value
22578 #undef TARGET_LIBCALL_VALUE
22579 #define TARGET_LIBCALL_VALUE mips_libcall_value
22580 #undef TARGET_FUNCTION_VALUE_REGNO_P
22581 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
22582 #undef TARGET_RETURN_IN_MEMORY
22583 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
22584 #undef TARGET_RETURN_IN_MSB
22585 #define TARGET_RETURN_IN_MSB mips_return_in_msb
22587 #undef TARGET_ASM_OUTPUT_MI_THUNK
22588 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
22589 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
22590 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
22592 #undef TARGET_PRINT_OPERAND
22593 #define TARGET_PRINT_OPERAND mips_print_operand
22594 #undef TARGET_PRINT_OPERAND_ADDRESS
22595 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
22596 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
22597 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
22599 #undef TARGET_SETUP_INCOMING_VARARGS
22600 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
22601 #undef TARGET_STRICT_ARGUMENT_NAMING
22602 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
22603 #undef TARGET_MUST_PASS_IN_STACK
22604 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
22605 #undef TARGET_PASS_BY_REFERENCE
22606 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
22607 #undef TARGET_CALLEE_COPIES
22608 #define TARGET_CALLEE_COPIES mips_callee_copies
22609 #undef TARGET_ARG_PARTIAL_BYTES
22610 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
22611 #undef TARGET_FUNCTION_ARG
22612 #define TARGET_FUNCTION_ARG mips_function_arg
22613 #undef TARGET_FUNCTION_ARG_ADVANCE
22614 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
22615 #undef TARGET_FUNCTION_ARG_PADDING
22616 #define TARGET_FUNCTION_ARG_PADDING mips_function_arg_padding
22617 #undef TARGET_FUNCTION_ARG_BOUNDARY
22618 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
22619 #undef TARGET_GET_RAW_RESULT_MODE
22620 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
22621 #undef TARGET_GET_RAW_ARG_MODE
22622 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
22624 #undef TARGET_MODE_REP_EXTENDED
22625 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
22627 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
22628 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
22629 mips_builtin_vectorized_function
22630 #undef TARGET_VECTOR_MODE_SUPPORTED_P
22631 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
22633 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22634 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
22636 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
22637 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
22638 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
22639 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
22640 mips_autovectorize_vector_sizes
22642 #undef TARGET_INIT_BUILTINS
22643 #define TARGET_INIT_BUILTINS mips_init_builtins
22644 #undef TARGET_BUILTIN_DECL
22645 #define TARGET_BUILTIN_DECL mips_builtin_decl
22646 #undef TARGET_EXPAND_BUILTIN
22647 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
22649 #undef TARGET_HAVE_TLS
22650 #define TARGET_HAVE_TLS HAVE_AS_TLS
22652 #undef TARGET_CANNOT_FORCE_CONST_MEM
22653 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
22655 #undef TARGET_LEGITIMATE_CONSTANT_P
22656 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
22658 #undef TARGET_ENCODE_SECTION_INFO
22659 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
22661 #undef TARGET_ATTRIBUTE_TABLE
22662 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
22663 /* All our function attributes are related to how out-of-line copies should
22664 be compiled or called. They don't in themselves prevent inlining. */
22665 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
22666 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
22668 #undef TARGET_EXTRA_LIVE_ON_ENTRY
22669 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
22671 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
22672 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
22673 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
22674 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
22676 #undef TARGET_COMP_TYPE_ATTRIBUTES
22677 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
22679 #ifdef HAVE_AS_DTPRELWORD
22680 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
22681 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
22683 #undef TARGET_DWARF_REGISTER_SPAN
22684 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
22685 #undef TARGET_DWARF_FRAME_REG_MODE
22686 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
22688 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
22689 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
22691 #undef TARGET_LEGITIMATE_ADDRESS_P
22692 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
22694 #undef TARGET_FRAME_POINTER_REQUIRED
22695 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
22697 #undef TARGET_CAN_ELIMINATE
22698 #define TARGET_CAN_ELIMINATE mips_can_eliminate
22700 #undef TARGET_CONDITIONAL_REGISTER_USAGE
22701 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
22703 #undef TARGET_TRAMPOLINE_INIT
22704 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
22706 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
22707 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
22709 #undef TARGET_SHIFT_TRUNCATION_MASK
22710 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
22712 #undef TARGET_PREPARE_PCH_SAVE
22713 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
22715 #undef TARGET_VECTORIZE_VEC_PERM_CONST
22716 #define TARGET_VECTORIZE_VEC_PERM_CONST mips_vectorize_vec_perm_const
22718 #undef TARGET_SCHED_REASSOCIATION_WIDTH
22719 #define TARGET_SCHED_REASSOCIATION_WIDTH mips_sched_reassociation_width
22721 #undef TARGET_CASE_VALUES_THRESHOLD
22722 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
22724 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
22725 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
22727 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
22728 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
22730 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
22731 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
22732 mips_use_by_pieces_infrastructure_p
22734 #undef TARGET_SPILL_CLASS
22735 #define TARGET_SPILL_CLASS mips_spill_class
22736 #undef TARGET_LRA_P
22737 #define TARGET_LRA_P mips_lra_p
22738 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
22739 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
22741 #undef TARGET_HARD_REGNO_SCRATCH_OK
22742 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
22744 #undef TARGET_HARD_REGNO_NREGS
22745 #define TARGET_HARD_REGNO_NREGS mips_hard_regno_nregs
22746 #undef TARGET_HARD_REGNO_MODE_OK
22747 #define TARGET_HARD_REGNO_MODE_OK mips_hard_regno_mode_ok
22749 #undef TARGET_MODES_TIEABLE_P
22750 #define TARGET_MODES_TIEABLE_P mips_modes_tieable_p
22752 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
22753 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
22754 mips_hard_regno_call_part_clobbered
22756 /* The architecture reserves bit 0 for MIPS16 so use bit 1 for descriptors. */
22757 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
22758 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2
22760 #undef TARGET_SECONDARY_MEMORY_NEEDED
22761 #define TARGET_SECONDARY_MEMORY_NEEDED mips_secondary_memory_needed
22763 #undef TARGET_CAN_CHANGE_MODE_CLASS
22764 #define TARGET_CAN_CHANGE_MODE_CLASS mips_can_change_mode_class
22766 #undef TARGET_TRULY_NOOP_TRUNCATION
22767 #define TARGET_TRULY_NOOP_TRUNCATION mips_truly_noop_truncation
22769 #undef TARGET_CONSTANT_ALIGNMENT
22770 #define TARGET_CONSTANT_ALIGNMENT mips_constant_alignment
22772 #undef TARGET_ASAN_SHADOW_OFFSET
22773 #define TARGET_ASAN_SHADOW_OFFSET mips_asan_shadow_offset
22775 #undef TARGET_STARTING_FRAME_OFFSET
22776 #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset
22778 struct gcc_target targetm
= TARGET_INITIALIZER
;
22780 #include "gt-mips.h"