gcc/config/mips/sb1.md

   1 ;; Copyright (C) 2004-2020 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19 ;; DFA-based pipeline description for Broadcom SB-1
  20 ;;
  21
  22 ;; The Broadcom SB-1 core is 4-way superscalar, in-order.  It has 2 load/store
  23 ;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP
  24 ;; pipes, and 1 MDMX pipes.  It can issue 2 ls insns and 2 exe/fpu/mdmx insns
  25 ;; each cycle.
  26
  27 ;; We model the 4-way issue by ordering unit choices.  The possible choices are
  28 ;; {ex1,fp1}|{ex0,fp0}|ls1|ls0.  Instructions issue to the first eligible unit
  29 ;; in the list in most cases.  Non-indexed load/stores issue to ls0 first.
  30 ;; simple alu operations issue to ls1 if it is still available, and their
  31 ;; operands are ready (no co-issue with loads), otherwise to the first
  32 ;; available ex unit.
  33
  34 ;; When exceptions are enabled, can only issue FP insns to fp1.  This is
  35 ;; to ensure that instructions complete in order.  The -mfp-exceptions option
  36 ;; can be used to specify whether the system has FP exceptions enabled or not.
  37
  38 ;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
  39 ;; insn can issue per cycle (fp1).
  40
  41 ;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register
  42 ;; file.  As a result, once an MDMX insn is issued, no FP insns can be issued
  43 ;; for 3 cycles.  When an FP insn is issued, no MDMX insn can be issued for
  44 ;; 5 cycles.  This is currently not handled because there is no MDMX insn
  45 ;; support as yet.
  46
  47 ;;
  48 ;; We use two automata.  sb1_cpu_div is for the integer divides, which are
  49 ;; not pipelined.  sb1_cpu is for everything else.
  50 ;;
  51 (define_automaton "sb1_cpu, sb1_cpu_div")
  52
  53 ;; Load/store function units.
  54 (define_cpu_unit "sb1_ls0" "sb1_cpu")
  55 (define_cpu_unit "sb1_ls1" "sb1_cpu")
  56
  57 ;; CPU function units.
  58 (define_cpu_unit "sb1_ex0" "sb1_cpu")
  59 (define_cpu_unit "sb1_ex1" "sb1_cpu")
  60
  61 ;; The divide unit is not pipelined, and blocks hi/lo reads and writes.
  62 (define_cpu_unit "sb1_div" "sb1_cpu_div")
  63 ;; DMULT block any multiply from issuing in the next cycle.
  64 (define_cpu_unit "sb1_mul" "sb1_cpu")
  65
  66 ;; Floating-point units.
  67 (define_cpu_unit "sb1_fp0" "sb1_cpu")
  68 (define_cpu_unit "sb1_fp1" "sb1_cpu")
  69
  70 ;; Can only issue to one of the ex and fp pipes at a time.
  71 (exclusion_set "sb1_ex0" "sb1_fp0")
  72 (exclusion_set "sb1_ex1" "sb1_fp1")
  73
  74 ;; Define an SB-1 specific attribute to simplify some FP descriptions.
  75 ;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are
  76 ;; disabled.
  77
  78 (define_attr "sb1_fp_pipes" "one,two"
  79   (cond [(and (match_test "TARGET_FLOAT64")
  80               (not (match_test "TARGET_FP_EXCEPTIONS")))
  81          (const_string "two")]
  82         (const_string "one")))
  83
  84 ;; Define reservations for common combinations.
  85
  86 ;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
  87 ;; effectively re-issuing the operation every 4 cycles.  This means that we
  88 ;; can have at most 4 long-cycle operations per pipe.
  89
  90 ;; ??? The fdiv operations should be e.g.
  91 ;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7
  92 ;; but the DFA is too large when we do that.  Perhaps have to use scheduler
  93 ;; hooks here.
  94
  95 ;; ??? Try limiting scheduler to 2 long latency operations, and see if this
  96 ;; results in a usable DFA, and whether it helps code performance.
  97
  98 ;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3")
  99 ;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3")
 100
 101 ;;
 102 ;; The ordering of the instruction-execution-path/resource-usage
 103 ;; descriptions (also known as reservation RTL) is roughly ordered
 104 ;; based on the define attribute RTL for the "type" classification.
 105 ;; When modifying, remember that the first test that matches is the
 106 ;; reservation used!
 107 ;;
 108
 109 (define_insn_reservation "ir_sb1_unknown" 1
 110   (and (eq_attr "cpu" "sb1,sb1a")
 111        (eq_attr "type" "unknown,multi,atomic,syncloop"))
 112   "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1")
 113
 114 ;; predicted taken branch causes 2 cycle ifetch bubble.  predicted not
 115 ;; taken branch causes 0 cycle ifetch bubble.  mispredicted branch causes 8
 116 ;; cycle ifetch bubble.  We assume all branches predicted not taken.
 117
 118 ;; ??? This assumption that branches are predicated not taken should be
 119 ;; investigated.  Maybe using 2 here will give better results.
 120
 121 (define_insn_reservation "ir_sb1_branch" 0
 122   (and (eq_attr "cpu" "sb1,sb1a")
 123        (eq_attr "type" "branch,jump,call"))
 124   "sb1_ex0")
 125
 126 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
 127 ;; register as destination.
 128
 129 ;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on
 130 ;; an EX unit.  Cannot co-issue if the dependent insn executes on an LS unit.
 131 ;; SB-1A can always co-issue here.
 132
 133 ;; A load normally has a latency of zero cycles.  In some cases, dependent
 134 ;; insns can be issued in the same cycle.  However, a value of 1 gives
 135 ;; better performance in empirical testing.
 136
 137 (define_insn_reservation "ir_sb1_load" 1
 138   (and (eq_attr "cpu" "sb1")
 139        (eq_attr "type" "load,prefetch"))
 140   "sb1_ls0 | sb1_ls1")
 141
 142 (define_insn_reservation "ir_sb1a_load" 0
 143   (and (eq_attr "cpu" "sb1a")
 144        (eq_attr "type" "load,prefetch"))
 145   "sb1_ls0 | sb1_ls1")
 146
 147 ;; Cannot co-issue fpload with fp exe when in 32-bit mode.
 148
 149 (define_insn_reservation "ir_sb1_fpload" 0
 150   (and (eq_attr "cpu" "sb1,sb1a")
 151        (and (eq_attr "type" "fpload")
 152             (match_test "TARGET_FLOAT64")))
 153   "sb1_ls0 | sb1_ls1")
 154
 155 (define_insn_reservation "ir_sb1_fpload_32bitfp" 1
 156   (and (eq_attr "cpu" "sb1,sb1a")
 157        (and (eq_attr "type" "fpload")
 158             (not (match_test "TARGET_FLOAT64"))))
 159   "sb1_ls0 | sb1_ls1")
 160
 161 ;; Indexed loads can only execute on LS1 pipe.
 162
 163 (define_insn_reservation "ir_sb1_fpidxload" 0
 164   (and (eq_attr "cpu" "sb1,sb1a")
 165        (and (eq_attr "type" "fpidxload")
 166             (match_test "TARGET_FLOAT64")))
 167   "sb1_ls1")
 168
 169 (define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
 170   (and (eq_attr "cpu" "sb1,sb1a")
 171        (and (eq_attr "type" "fpidxload")
 172             (not (match_test "TARGET_FLOAT64"))))
 173   "sb1_ls1")
 174
 175 ;; prefx can only execute on the ls1 pipe.
 176
 177 (define_insn_reservation "ir_sb1_prefetchx" 0
 178   (and (eq_attr "cpu" "sb1,sb1a")
 179        (eq_attr "type" "prefetchx"))
 180   "sb1_ls1")
 181
 182 ;; ??? There is a 4.5 cycle latency if a store is followed by a load, and
 183 ;; there is a RAW dependency.
 184
 185 (define_insn_reservation "ir_sb1_store" 1
 186   (and (eq_attr "cpu" "sb1,sb1a")
 187        (eq_attr "type" "store"))
 188   "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0")
 189
 190 (define_insn_reservation "ir_sb1_fpstore" 1
 191   (and (eq_attr "cpu" "sb1,sb1a")
 192        (eq_attr "type" "fpstore"))
 193   "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
 194
 195 ;; Indexed stores can only execute on LS1 pipe.
 196
 197 (define_insn_reservation "ir_sb1_fpidxstore" 1
 198   (and (eq_attr "cpu" "sb1,sb1a")
 199        (eq_attr "type" "fpidxstore"))
 200   "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
 201
 202 ;; Load latencies are 3 cycles for one load to another load or store (address
 203 ;; only).  This is 0 cycles for one load to a store using it as the data
 204 ;; written.
 205
 206 ;; This assumes that if a load is dependent on a previous insn, then it must
 207 ;; be an address dependence.
 208
 209 (define_bypass 3
 210   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
 211    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
 212   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
 213    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
 214
 215 (define_bypass 3
 216   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
 217    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
 218   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
 219   "!mips_store_data_bypass_p")
 220
 221 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
 222
 223 ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
 224 ;; insn, to a store (for data), and to an xfer insn.  It has 1 cycle latency to
 225 ;; another LS insn (excluding store data).  A simple alu insn issued on an EX
 226 ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
 227 ;; store data), otherwise a latency of 1 cycle.
 228
 229 ;; ??? We cannot handle latencies properly for simple alu instructions
 230 ;; within the DFA pipeline model.  Latencies can be defined only from one
 231 ;; insn reservation to another.  We can't make them depend on which function
 232 ;; unit was used.  This isn't a DFA flaw.  There is a conflict here, as we
 233 ;; need to know the latency before we can determine which unit will be
 234 ;; available, but we need to know which unit it is issued to before we can
 235 ;; compute the latency.  Perhaps this can be handled via scheduler hooks.
 236 ;; This needs to be investigated.
 237
 238 ;; ??? Optimal scheduling taking the LS units into account seems to require
 239 ;; a pre-scheduling pass.  We need to determine which instructions feed results
 240 ;; into store/load addresses, and thus benefit most from being issued to the
 241 ;; LS unit.  Also, we need to prune the list to ensure we don't overschedule
 242 ;; insns to the LS unit, and that we don't conflict with insns that need LS1
 243 ;; such as indexed loads.  We then need to emit nops to ensure that simple
 244 ;; alu instructions that are not supposed to be scheduled to LS1 don't
 245 ;; accidentally end up there because LS1 is free when they are issued.  This
 246 ;; will be a lot of work, and it isn't clear how useful it will be.
 247
 248 ;; Empirical testing shows that 2 gives the best result.
 249
 250 (define_insn_reservation "ir_sb1_simple_alu" 2
 251   (and (eq_attr "cpu" "sb1")
 252        (eq_attr "type" "const,arith,logical,move,signext"))
 253   "sb1_ls1 | sb1_ex1 | sb1_ex0")
 254
 255 ;; On SB-1A, simple alu instructions cannot execute on the LS1 unit, and we
 256 ;; have none of the above problems.
 257
 258 (define_insn_reservation "ir_sb1a_simple_alu" 1
 259   (and (eq_attr "cpu" "sb1a")
 260        (eq_attr "type" "const,arith,logical,move,signext"))
 261   "sb1_ex1 | sb1_ex0")
 262
 263 ;; ??? condmove also includes some FP instructions that execute on the FP
 264 ;; units.  This needs to be clarified.
 265
 266 (define_insn_reservation "ir_sb1_alu" 1
 267   (and (eq_attr "cpu" "sb1,sb1a")
 268        (eq_attr "type" "condmove,nop,shift"))
 269   "sb1_ex1 | sb1_ex0")
 270
 271 ;; These are type arith/darith that only execute on the EX0 unit.
 272
 273 (define_insn_reservation "ir_sb1_alu_0" 1
 274   (and (eq_attr "cpu" "sb1,sb1a")
 275        (eq_attr "type" "slt,clz,trap"))
 276   "sb1_ex0")
 277
 278 ;; An alu insn issued on an EX unit has a latency of 5 cycles when the
 279 ;; result goes to a LS unit (excluding store data).
 280
 281 ;; This assumes that if a load is dependent on a previous insn, then it must
 282 ;; be an address dependence.
 283
 284 (define_bypass 5
 285   "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
 286   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
 287    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
 288
 289 (define_bypass 5
 290   "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
 291   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
 292   "!mips_store_data_bypass_p")
 293
 294 ;; mf{hi,lo} is 1 cycle.
 295
 296 (define_insn_reservation "ir_sb1_mfhi" 1
 297   (and (eq_attr "cpu" "sb1,sb1a")
 298        (eq_attr "type" "mfhi"))
 299   "sb1_ex1")
 300
 301 (define_insn_reservation "ir_sb1_mflo" 1
 302   (and (eq_attr "cpu" "sb1,sb1a")
 303        (eq_attr "type" "mflo"))
 304   "sb1_ex1")
 305
 306 ;; mt{hi,lo} to mul/div is 4 cycles.
 307
 308 (define_insn_reservation "ir_sb1_mthilo" 4
 309   (and (eq_attr "cpu" "sb1,sb1a")
 310        (eq_attr "type" "mthi,mtlo"))
 311   "sb1_ex1")
 312
 313 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
 314
 315 (define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo")
 316
 317 ;; multiply latency to an EX operation is 3 cycles.
 318
 319 ;; ??? Should check whether we need to make multiply conflict with moves
 320 ;; to/from hilo registers.
 321
 322 (define_insn_reservation "ir_sb1_mulsi" 3
 323   (and (eq_attr "cpu" "sb1,sb1a")
 324        (and (eq_attr "type" "imul,imul3,imadd")
 325             (eq_attr "mode" "SI")))
 326   "sb1_ex1+sb1_mul")
 327
 328 ;; muldi to mfhi is 4 cycles.
 329 ;; Blocks any other multiply insn issue for 1 cycle.
 330
 331 (define_insn_reservation "ir_sb1_muldi" 4
 332   (and (eq_attr "cpu" "sb1,sb1a")
 333        (and (eq_attr "type" "imul,imul3")
 334             (eq_attr "mode" "DI")))
 335   "sb1_ex1+sb1_mul, sb1_mul")
 336
 337 ;; muldi to mflo is 3 cycles.
 338
 339 (define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo")
 340
 341 ;;  mul latency is 7 cycles if the result is used by any LS insn.
 342
 343 ;; This assumes that if a load is dependent on a previous insn, then it must
 344 ;; be an address dependence.
 345
 346 (define_bypass 7
 347   "ir_sb1_mulsi,ir_sb1_muldi"
 348   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
 349    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
 350
 351 (define_bypass 7
 352   "ir_sb1_mulsi,ir_sb1_muldi"
 353   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
 354   "!mips_store_data_bypass_p")
 355
 356 ;; The divide unit is not pipelined.  Divide busy is asserted in the 4th
 357 ;; cycle, and then deasserted on the latency cycle.  So only one divide at
 358 ;; a time, but the first/last 4 cycles can overlap.
 359
 360 ;; ??? All divides block writes to hi/lo regs.  hi/lo regs are written 4 cycles
 361 ;; after the latency cycle for divides (e.g. 40/72).  dmult writes lo in
 362 ;; cycle 7, and hi in cycle 8.  All other insns write hi/lo regs in cycle 7.
 363 ;; Default for output dependencies is the difference in latencies, which is
 364 ;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should
 365 ;; stall for 33 cycles.  This does not seem significant enough to worry about.
 366
 367 (define_insn_reservation "ir_sb1_divsi" 36
 368   (and (eq_attr "cpu" "sb1,sb1a")
 369        (and (eq_attr "type" "idiv")
 370             (eq_attr "mode" "SI")))
 371   "sb1_ex1, nothing*3, sb1_div*32")
 372
 373 (define_insn_reservation "ir_sb1_divdi" 68
 374   (and (eq_attr "cpu" "sb1,sb1a")
 375        (and (eq_attr "type" "idiv")
 376             (eq_attr "mode" "DI")))
 377   "sb1_ex1, nothing*3, sb1_div*64")
 378
 379 (define_insn_reservation "ir_sb1_fpu_2pipes" 4
 380   (and (eq_attr "cpu" "sb1,sb1a")
 381        (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
 382             (eq_attr "sb1_fp_pipes" "two")))
 383   "sb1_fp1 | sb1_fp0")
 384
 385 (define_insn_reservation "ir_sb1_fpu_1pipe" 4
 386   (and (eq_attr "cpu" "sb1,sb1a")
 387        (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
 388             (eq_attr "sb1_fp_pipes" "one")))
 389   "sb1_fp1")
 390
 391 (define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8
 392   (and (eq_attr "cpu" "sb1,sb1a")
 393        (and (eq_attr "type" "frdiv2,frsqrt2")
 394             (eq_attr "sb1_fp_pipes" "two")))
 395   "sb1_fp1 | sb1_fp0")
 396
 397 (define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8
 398   (and (eq_attr "cpu" "sb1,sb1a")
 399        (and (eq_attr "type" "frdiv2,frsqrt2")
 400             (eq_attr "sb1_fp_pipes" "one")))
 401   "sb1_fp1")
 402
 403 ;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency
 404 ;; otherwise.
 405
 406 ;; ??? Blocks issue of another non-madd/msub after 4 cycles.
 407
 408 (define_insn_reservation "ir_sb1_fmadd_2pipes" 8
 409   (and (eq_attr "cpu" "sb1,sb1a")
 410        (and (eq_attr "type" "fmadd")
 411             (eq_attr "sb1_fp_pipes" "two")))
 412   "sb1_fp1 | sb1_fp0")
 413
 414 (define_insn_reservation "ir_sb1_fmadd_1pipe" 8
 415   (and (eq_attr "cpu" "sb1,sb1a")
 416        (and (eq_attr "type" "fmadd")
 417             (eq_attr "sb1_fp_pipes" "one")))
 418   "sb1_fp1")
 419
 420 (define_insn_reservation "ir_sb1_fcmp" 4
 421   (and (eq_attr "cpu" "sb1,sb1a")
 422        (eq_attr "type" "fcmp"))
 423   "sb1_fp1")
 424
 425 ;; mtc1 latency 5 cycles.
 426
 427 (define_insn_reservation "ir_sb1_mtxfer" 5
 428   (and (eq_attr "cpu" "sb1,sb1a")
 429        (eq_attr "type" "mtc"))
 430   "sb1_fp0")
 431
 432 ;; mfc1 latency 1 cycle.
 433
 434 (define_insn_reservation "ir_sb1_mfxfer" 1
 435   (and (eq_attr "cpu" "sb1,sb1a")
 436        (eq_attr "type" "mfc"))
 437   "sb1_fp0")
 438
 439 ;; ??? Can deliver at most 1 result per every 6 cycles because of issue
 440 ;; restrictions.
 441
 442 (define_insn_reservation "ir_sb1_divsf_2pipes" 24
 443   (and (eq_attr "cpu" "sb1,sb1a")
 444        (and (eq_attr "type" "fdiv")
 445             (and (eq_attr "mode" "SF")
 446                  (eq_attr "sb1_fp_pipes" "two"))))
 447   "sb1_fp1 | sb1_fp0")
 448
 449 (define_insn_reservation "ir_sb1_divsf_1pipe" 24
 450   (and (eq_attr "cpu" "sb1,sb1a")
 451        (and (eq_attr "type" "fdiv")
 452             (and (eq_attr "mode" "SF")
 453                  (eq_attr "sb1_fp_pipes" "one"))))
 454   "sb1_fp1")
 455
 456 ;; ??? Can deliver at most 1 result per every 8 cycles because of issue
 457 ;; restrictions.
 458
 459 (define_insn_reservation "ir_sb1_divdf_2pipes" 32
 460   (and (eq_attr "cpu" "sb1,sb1a")
 461        (and (eq_attr "type" "fdiv")
 462             (and (eq_attr "mode" "DF")
 463                  (eq_attr "sb1_fp_pipes" "two"))))
 464   "sb1_fp1 | sb1_fp0")
 465
 466 (define_insn_reservation "ir_sb1_divdf_1pipe" 32
 467   (and (eq_attr "cpu" "sb1,sb1a")
 468        (and (eq_attr "type" "fdiv")
 469             (and (eq_attr "mode" "DF")
 470                  (eq_attr "sb1_fp_pipes" "one"))))
 471   "sb1_fp1")
 472
 473 ;; ??? Can deliver at most 1 result per every 3 cycles because of issue
 474 ;; restrictions.
 475
 476 (define_insn_reservation "ir_sb1_recipsf_2pipes" 12
 477   (and (eq_attr "cpu" "sb1,sb1a")
 478        (and (eq_attr "type" "frdiv")
 479             (and (eq_attr "mode" "SF")
 480                  (eq_attr "sb1_fp_pipes" "two"))))
 481   "sb1_fp1 | sb1_fp0")
 482
 483 (define_insn_reservation "ir_sb1_recipsf_1pipe" 12
 484   (and (eq_attr "cpu" "sb1,sb1a")
 485        (and (eq_attr "type" "frdiv")
 486             (and (eq_attr "mode" "SF")
 487                  (eq_attr "sb1_fp_pipes" "one"))))
 488   "sb1_fp1")
 489
 490 ;; ??? Can deliver at most 1 result per every 5 cycles because of issue
 491 ;; restrictions.
 492
 493 (define_insn_reservation "ir_sb1_recipdf_2pipes" 20
 494   (and (eq_attr "cpu" "sb1,sb1a")
 495        (and (eq_attr "type" "frdiv")
 496             (and (eq_attr "mode" "DF")
 497                  (eq_attr "sb1_fp_pipes" "two"))))
 498   "sb1_fp1 | sb1_fp0")
 499
 500 (define_insn_reservation "ir_sb1_recipdf_1pipe" 20
 501   (and (eq_attr "cpu" "sb1,sb1a")
 502        (and (eq_attr "type" "frdiv")
 503             (and (eq_attr "mode" "DF")
 504                  (eq_attr "sb1_fp_pipes" "one"))))
 505   "sb1_fp1")
 506
 507 ;; ??? Can deliver at most 1 result per every 7 cycles because of issue
 508 ;; restrictions.
 509
 510 (define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28
 511   (and (eq_attr "cpu" "sb1,sb1a")
 512        (and (eq_attr "type" "fsqrt")
 513             (and (eq_attr "mode" "SF")
 514                  (eq_attr "sb1_fp_pipes" "two"))))
 515   "sb1_fp1 | sb1_fp0")
 516
 517 (define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28
 518   (and (eq_attr "cpu" "sb1,sb1a")
 519        (and (eq_attr "type" "fsqrt")
 520             (and (eq_attr "mode" "SF")
 521                  (eq_attr "sb1_fp_pipes" "one"))))
 522   "sb1_fp1")
 523
 524 ;; ??? Can deliver at most 1 result per every 10 cycles because of issue
 525 ;; restrictions.
 526
 527 (define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40
 528   (and (eq_attr "cpu" "sb1,sb1a")
 529        (and (eq_attr "type" "fsqrt")
 530             (and (eq_attr "mode" "DF")
 531                  (eq_attr "sb1_fp_pipes" "two"))))
 532   "sb1_fp1 | sb1_fp0")
 533
 534 (define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40
 535   (and (eq_attr "cpu" "sb1,sb1a")
 536        (and (eq_attr "type" "fsqrt")
 537             (and (eq_attr "mode" "DF")
 538                  (eq_attr "sb1_fp_pipes" "one"))))
 539   "sb1_fp1")
 540
 541 ;; ??? Can deliver at most 1 result per every 4 cycles because of issue
 542 ;; restrictions.
 543
 544 (define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16
 545   (and (eq_attr "cpu" "sb1,sb1a")
 546        (and (eq_attr "type" "frsqrt")
 547             (and (eq_attr "mode" "SF")
 548                  (eq_attr "sb1_fp_pipes" "two"))))
 549   "sb1_fp1 | sb1_fp0")
 550
 551 (define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16
 552   (and (eq_attr "cpu" "sb1,sb1a")
 553        (and (eq_attr "type" "frsqrt")
 554             (and (eq_attr "mode" "SF")
 555                  (eq_attr "sb1_fp_pipes" "one"))))
 556   "sb1_fp1")
 557
 558 ;; ??? Can deliver at most 1 result per every 7 cycles because of issue
 559 ;; restrictions.
 560
 561 (define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28
 562   (and (eq_attr "cpu" "sb1,sb1a")
 563        (and (eq_attr "type" "frsqrt")
 564             (and (eq_attr "mode" "DF")
 565                  (eq_attr "sb1_fp_pipes" "two"))))
 566   "sb1_fp1 | sb1_fp0")
 567
 568 (define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28
 569   (and (eq_attr "cpu" "sb1,sb1a")
 570        (and (eq_attr "type" "frsqrt")
 571             (and (eq_attr "mode" "DF")
 572                  (eq_attr "sb1_fp_pipes" "one"))))
 573   "sb1_fp1")