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1 /* Definitions of target machine for GNU compiler, for the pdp-11
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #define CONSTANT_POOL_BEFORE_FUNCTION 0
22
23 /* check whether load_fpu_reg or not */
24 #define LOAD_FPU_REG_P(x) ((x) >= AC0_REGNUM && (x) <= AC3_REGNUM)
25 #define NO_LOAD_FPU_REG_P(x) ((x) == AC4_REGNUM || (x) == AC5_REGNUM)
26 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x))
27 #define CPU_REG_P(x) ((x) <= PC_REGNUM)
28
29 /* Names to predefine in the preprocessor for this target machine. */
30
31 #define TARGET_CPU_CPP_BUILTINS() \
32 do \
33 { \
34 builtin_define_std ("pdp11"); \
35 if (TARGET_INT16) \
36 builtin_define_with_int_value ("__pdp11_int", 16); \
37 else \
38 builtin_define_with_int_value ("__pdp11_int", 32); \
39 if (TARGET_40) \
40 builtin_define_with_int_value ("__pdp11_model", 40); \
41 else if (TARGET_45) \
42 builtin_define_with_int_value ("__pdp11_model", 45); \
43 else \
44 builtin_define_with_int_value ("__pdp11_model", 10); \
45 if (TARGET_FPU) \
46 builtin_define ("__pdp11_fpu"); \
47 if (TARGET_AC0) \
48 builtin_define ("__pdp11_ac0"); \
49 } \
50 while (0)
51
52
53 /* Generate DBX debugging information. */
54
55 #define DBX_DEBUGGING_INFO
56
57 #define TARGET_40_PLUS (TARGET_40 || TARGET_45)
58 #define TARGET_10 (! TARGET_40_PLUS)
59
60 #define TARGET_UNIX_ASM_DEFAULT 0
61
62 /* "Dialect" just distinguishes between standard DEC mnemonics, which
63 are also used by the GNU assembler, vs. Unix mnemonics and float
64 register names. So it is tied to the -munit-asm option, and treats
65 -mgnu-asm and -mdec-asm as equivalent (both are dialect zero). */
66 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0)
67
68 \f
69
70 /* TYPE SIZES */
71 #define SHORT_TYPE_SIZE 16
72 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32)
73 #define LONG_TYPE_SIZE 32
74 #define LONG_LONG_TYPE_SIZE 64
75
76 /* In earlier versions, FLOAT_TYPE_SIZE was selectable as 32 or 64,
77 but that conflicts with Fortran language rules. Since there is no
78 obvious reason why we should have that feature -- other targets
79 generally don't have float and double the same size -- I've removed
80 it. Note that it continues to be true (for now) that arithmetic is
81 always done with 64-bit values, i.e., the FPU is always in "double"
82 mode. */
83 #define FLOAT_TYPE_SIZE 32
84 #define DOUBLE_TYPE_SIZE 64
85 #define LONG_DOUBLE_TYPE_SIZE 64
86
87 /* machine types from ansi */
88 #define SIZE_TYPE "short unsigned int" /* definition of size_t */
89 #define WCHAR_TYPE "short int" /* or long int???? */
90 #define WCHAR_TYPE_SIZE 16
91
92 #define PTRDIFF_TYPE "short int"
93
94 /* target machine storage layout */
95
96 /* Define this if most significant bit is lowest numbered
97 in instructions that operate on numbered bit-fields. */
98 #define BITS_BIG_ENDIAN 0
99
100 /* Define this if most significant byte of a word is the lowest numbered. */
101 #define BYTES_BIG_ENDIAN 0
102
103 /* Define this if most significant word of a multiword number is first. */
104 #define WORDS_BIG_ENDIAN 1
105
106 /* Define that floats are in VAX order, not high word first as for ints. */
107 #define FLOAT_WORDS_BIG_ENDIAN 0
108
109 /* Width of a word, in units (bytes).
110
111 UNITS OR BYTES - seems like units */
112 #define UNITS_PER_WORD 2
113
114 /* This machine doesn't use IEEE floats. */
115 /* Because the pdp11 (at least Unix) convention for 32-bit ints is
116 big endian, opposite for what you need for float, the vax float
117 conversion routines aren't actually used directly. But the underlying
118 format is indeed the vax/pdp11 float format. */
119 extern const struct real_format pdp11_f_format;
120 extern const struct real_format pdp11_d_format;
121
122 /* Maximum sized of reasonable data type -- DImode ...*/
123 #define MAX_FIXED_MODE_SIZE 64
124
125 /* Allocation boundary (in *bits*) for storing pointers in memory. */
126 #define POINTER_BOUNDARY 16
127
128 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
129 #define PARM_BOUNDARY 16
130
131 /* Boundary (in *bits*) on which stack pointer should be aligned. */
132 #define STACK_BOUNDARY 16
133
134 /* Allocation boundary (in *bits*) for the code of a function. */
135 #define FUNCTION_BOUNDARY 16
136
137 /* Alignment of field after `int : 0' in a structure. */
138 #define EMPTY_FIELD_BOUNDARY 16
139
140 /* No data type wants to be aligned rounder than this. */
141 #define BIGGEST_ALIGNMENT 16
142
143 /* Define this if move instructions will actually fail to work
144 when given unaligned data. */
145 #define STRICT_ALIGNMENT 1
146 \f
147 /* Standard register usage. */
148
149 /* Number of actual hardware registers.
150 The hardware registers are assigned numbers for the compiler
151 from 0 to just below FIRST_PSEUDO_REGISTER.
152 All registers that the compiler knows about must be given numbers,
153 even those that are not normally considered general registers.
154
155 we have 8 integer registers, plus 6 float
156 (don't use scratch float !) */
157
158 /* 1 for registers that have pervasive standard uses
159 and are not available for the register allocator.
160
161 On the pdp, these are:
162 Reg 7 = pc;
163 reg 6 = sp;
164 reg 5 = fp; not necessarily!
165 */
166
167 #define FIXED_REGISTERS \
168 {0, 0, 0, 0, 0, 0, 1, 1, \
169 0, 0, 0, 0, 0, 0, 1, 1, \
170 1 }
171
172
173
174 /* 1 for registers not available across function calls.
175 These must include the FIXED_REGISTERS and also any
176 registers that can be used without being saved.
177 The latter must include the registers where values are returned
178 and the register where structure-value addresses are passed.
179 Aside from that, you can include as many other registers as you like. */
180
181 /* don't know about fp */
182 #define CALL_USED_REGISTERS \
183 {1, 1, 0, 0, 0, 0, 1, 1, \
184 0, 0, 0, 0, 0, 0, 1, 1, \
185 1 }
186
187
188 /* Specify the registers used for certain standard purposes.
189 The values of these macros are register numbers. */
190
191 /* Register in which static-chain is passed to a function. */
192 /* ??? - i don't want to give up a reg for this! */
193 #define STATIC_CHAIN_REGNUM 4
194 \f
195 /* Define the classes of registers for register constraints in the
196 machine description. Also define ranges of constants.
197
198 One of the classes must always be named ALL_REGS and include all hard regs.
199 If there is more than one class, another class must be named NO_REGS
200 and contain no registers.
201
202 The name GENERAL_REGS must be the name of a class (or an alias for
203 another name such as ALL_REGS). This is the class of registers
204 that is allowed by "g" or "r" in a register constraint.
205 Also, registers outside this class are allocated only when
206 instructions express preferences for them.
207
208 The classes must be numbered in nondecreasing order; that is,
209 a larger-numbered class must never be contained completely
210 in a smaller-numbered class.
211
212 For any two classes, it is very desirable that there be another
213 class that represents their union. */
214
215 /* The pdp has a couple of classes:
216
217 MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication
218 (even numbered do 32-bit multiply)
219 GENERAL_REGS is all cpu
220 LOAD_FPU_REGS is the first four cpu regs, they are easier to load
221 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
222 FPU_REGS is all fpu regs
223 CC_REGS is the condition codes (CPU and FPU)
224 */
225
226 enum reg_class
227 { NO_REGS,
228 NOTR0_REG,
229 NOTR1_REG,
230 NOTR2_REG,
231 NOTR3_REG,
232 NOTR4_REG,
233 NOTR5_REG,
234 NOTSP_REG,
235 MUL_REGS,
236 GENERAL_REGS,
237 LOAD_FPU_REGS,
238 NO_LOAD_FPU_REGS,
239 FPU_REGS,
240 CC_REGS,
241 ALL_REGS,
242 LIM_REG_CLASSES };
243
244 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
245
246 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */
247 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
248
249 /* Give names of register classes as strings for dump file. */
250
251 #define REG_CLASS_NAMES \
252 { "NO_REGS", \
253 "NOTR0_REG", \
254 "NOTR1_REG", \
255 "NOTR2_REG", \
256 "NOTR3_REG", \
257 "NOTR4_REG", \
258 "NOTR5_REG", \
259 "SP_REG", \
260 "MUL_REGS", \
261 "GENERAL_REGS", \
262 "LOAD_FPU_REGS", \
263 "NO_LOAD_FPU_REGS", \
264 "FPU_REGS", \
265 "CC_REGS", \
266 "ALL_REGS" }
267
268 /* Define which registers fit in which classes.
269 This is an initializer for a vector of HARD_REG_SET
270 of length N_REG_CLASSES. */
271
272 #define REG_CLASS_CONTENTS \
273 { {0x00000}, /* NO_REGS */ \
274 {0x000fe}, /* NOTR0_REG */ \
275 {0x000fd}, /* NOTR1_REG */ \
276 {0x000fb}, /* NOTR2_REG */ \
277 {0x000f7}, /* NOTR3_REG */ \
278 {0x000ef}, /* NOTR4_REG */ \
279 {0x000df}, /* NOTR5_REG */ \
280 {0x000bf}, /* NOTSP_REG */ \
281 {0x0002a}, /* MUL_REGS */ \
282 {0x040ff}, /* GENERAL_REGS */ \
283 {0x00f00}, /* LOAD_FPU_REGS */ \
284 {0x03000}, /* NO_LOAD_FPU_REGS */ \
285 {0x03f00}, /* FPU_REGS */ \
286 {0x18000}, /* CC_REGS */ \
287 {0x1ffff}} /* ALL_REGS */
288
289 /* The same information, inverted:
290 Return the class number of the smallest class containing
291 reg number REGNO. This could be a conditional expression
292 or could index an array. */
293
294 #define REGNO_REG_CLASS(REGNO) pdp11_regno_reg_class (REGNO)
295
296 /* The class value for index registers, and the one for base regs. */
297 #define INDEX_REG_CLASS GENERAL_REGS
298 #define BASE_REG_CLASS GENERAL_REGS
299
300 /* Return TRUE if the class is a CPU register. */
301 #define CPU_REG_CLASS(CLASS) \
302 (CLASS >= NOTR0_REG && CLASS <= GENERAL_REGS)
303
304 /* Return the maximum number of consecutive registers
305 needed to represent mode MODE in a register of class CLASS. */
306 #define CLASS_MAX_NREGS(CLASS, MODE) \
307 (CPU_REG_CLASS (CLASS) ? \
308 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \
309 1 \
310 )
311 \f
312 /* Stack layout; function entry, exit and calling. */
313
314 /* Define this if pushing a word on the stack
315 makes the stack pointer a smaller address. */
316 #define STACK_GROWS_DOWNWARD 1
317
318 /* Define this to nonzero if the nominal address of the stack frame
319 is at the high-address end of the local variables;
320 that is, each additional local variable allocated
321 goes at a more negative offset in the frame.
322 */
323 #define FRAME_GROWS_DOWNWARD 1
324
325 #define PUSH_ROUNDING(BYTES) pdp11_push_rounding (BYTES)
326
327 /* current_first_parm_offset stores the # of registers pushed on the
328 stack */
329 extern int current_first_parm_offset;
330
331 /* Offset of first parameter from the argument pointer register value. */
332 #define FIRST_PARM_OFFSET(FNDECL) 0
333
334 /* Define how to find the value returned by a function.
335 VALTYPE is the data type of the value (as a tree).
336 If the precise function being called is known, FUNC is its FUNCTION_DECL;
337 otherwise, FUNC is 0. */
338 #define BASE_RETURN_VALUE_REG(MODE) \
339 (FLOAT_MODE_P (MODE) ? AC0_REGNUM : RETVAL_REGNUM)
340
341 /* 1 if N is a possible register number for function argument passing.
342 - not used on pdp */
343
344 #define FUNCTION_ARG_REGNO_P(N) 0
345 \f
346 /* Define a data type for recording info about an argument list
347 during the scan of that argument list. This data type should
348 hold all necessary information about the function itself
349 and about the args processed so far, enough to enable macros
350 such as FUNCTION_ARG to determine where the next arg should go.
351
352 */
353
354 #define CUMULATIVE_ARGS int
355
356 /* Initialize a variable CUM of type CUMULATIVE_ARGS
357 for a call to a function whose data type is FNTYPE.
358 For a library call, FNTYPE is 0.
359
360 ...., the offset normally starts at 0, but starts at 1 word
361 when the function gets a structure-value-address as an
362 invisible first argument. */
363
364 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
365 ((CUM) = 0)
366
367 /* Output assembler code to FILE to increment profiler label # LABELNO
368 for profiling a function entry. */
369
370 #define FUNCTION_PROFILER(FILE, LABELNO)
371
372 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
373 the stack pointer does not matter. The value is tested only in
374 functions that have frame pointers.
375 No definition is equivalent to always zero. */
376
377 #define EXIT_IGNORE_STACK 1
378
379 /* Definitions for register eliminations.
380
381 This is an array of structures. Each structure initializes one pair
382 of eliminable registers. The "from" register number is given first,
383 followed by "to". Eliminations of the same "from" register are listed
384 in order of preference.
385
386 There are two registers that can be eliminated on the pdp11. The
387 arg pointer can be replaced by the frame pointer; the frame pointer
388 can often be replaced by the stack pointer. */
389
390 #define ELIMINABLE_REGS \
391 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
392 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
393 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
394
395 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
396 ((OFFSET) = pdp11_initial_elimination_offset ((FROM), (TO)))
397
398 \f
399 /* Addressing modes, and classification of registers for them. */
400
401 #define HAVE_POST_INCREMENT 1
402
403 #define HAVE_PRE_DECREMENT 1
404
405 /* Macros to check register numbers against specific register classes. */
406
407 /* These assume that REGNO is a hard or pseudo reg number.
408 They give nonzero only if REGNO is a hard reg of the suitable class
409 or a pseudo reg currently allocated to a suitable hard reg.
410 Since they use reg_renumber, they are safe only once reg_renumber
411 has been allocated, which happens in reginfo.c during register
412 allocation. */
413
414 #define REGNO_OK_FOR_BASE_P(REGNO) \
415 ((REGNO) <= PC_REGNUM || (unsigned) reg_renumber[REGNO] <= PC_REGNUM || \
416 (REGNO) == ARG_POINTER_REGNUM || (REGNO) == FRAME_POINTER_REGNUM)
417
418 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P (REGNO)
419
420 /* Now macros that check whether X is a register and also,
421 strictly, whether it is in a specified class.
422 */
423
424
425 \f
426 /* Maximum number of registers that can appear in a valid memory address. */
427
428 #define MAX_REGS_PER_ADDRESS 1
429
430 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
431 and check its validity for a certain class.
432 We have two alternate definitions for each of them.
433 The usual definition accepts all pseudo regs; the other rejects
434 them unless they have been allocated suitable hard regs.
435 The symbol REG_OK_STRICT causes the latter definition to be used.
436
437 Most source files want to accept pseudo regs in the hope that
438 they will get allocated to the class that the insn wants them to be in.
439 Source files for reload pass need to be strict.
440 After reload, it makes no difference, since pseudo regs have
441 been eliminated by then. */
442
443 #ifndef REG_OK_STRICT
444
445 /* Nonzero if X is a hard reg that can be used as an index
446 or if it is a pseudo reg. */
447 #define REG_OK_FOR_INDEX_P(X) (1)
448 /* Nonzero if X is a hard reg that can be used as a base reg
449 or if it is a pseudo reg. */
450 #define REG_OK_FOR_BASE_P(X) (1)
451
452 #else
453
454 /* Nonzero if X is a hard reg that can be used as an index. */
455 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
456 /* Nonzero if X is a hard reg that can be used as a base reg. */
457 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
458
459 #endif
460 \f
461 /* Specify the machine mode that this machine uses
462 for the index in the tablejump instruction. */
463 #define CASE_VECTOR_MODE HImode
464
465 /* Define this if a raw index is all that is needed for a
466 `tablejump' insn. */
467 #define CASE_TAKES_INDEX_RAW
468
469 /* Define this as 1 if `char' should by default be signed; else as 0. */
470 #define DEFAULT_SIGNED_CHAR 1
471
472 /* Max number of bytes we can move from memory to memory
473 in one reasonably fast instruction.
474 */
475 #define MOVE_MAX 2
476
477 /* Max number of insns to use for inline move rather than library
478 call. */
479 #define MOVE_RATIO(speed) 6
480
481 /* Nonzero if access to memory by byte is no faster than by word. */
482 #define SLOW_BYTE_ACCESS 1
483
484 /* Do not break .stabs pseudos into continuations. */
485 #define DBX_CONTIN_LENGTH 0
486
487 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE,
488 return the mode to be used for the comparison. */
489
490 #define SELECT_CC_MODE(OP,X,Y) pdp11_cc_mode (OP, X, Y)
491
492 /* Enable compare elimination pass. */
493 #undef TARGET_FLAGS_REGNUM
494 #define TARGET_FLAGS_REGNUM CC_REGNUM
495
496 /* Specify the CC registers. TODO: is this for "type 1" CC handling only? */
497 #undef TARGET_FIXED_CONDITION_CODE_REGS
498 #define TARGET_FIXED_CONDITION_CODE_REGS pdp11_fixed_cc_regs
499
500 /* Specify the machine mode that pointers have.
501 After generation of rtl, the compiler makes no further distinction
502 between pointers and any other objects of this machine mode. */
503 #define Pmode HImode
504
505 /* A function address in a call instruction
506 is a word address (for indexing purposes)
507 so give the MEM rtx a word's mode. */
508 #define FUNCTION_MODE HImode
509
510 /* Define this if addresses of constant functions
511 shouldn't be put through pseudo regs where they can be cse'd.
512 Desirable on machines where ordinary constants are expensive
513 but a CALL with constant address is cheap. */
514 /* #define NO_FUNCTION_CSE */
515
516 \f
517 /* Control the assembler format that we output. */
518
519 /* Output to assembler file text saying following lines
520 may contain character constants, extra white space, comments, etc. */
521
522 #define ASM_APP_ON ""
523
524 /* Output to assembler file text saying following lines
525 no longer contain unusual constructs. */
526
527 #define ASM_APP_OFF ""
528
529 /* Output before read-only data. */
530
531 #define TEXT_SECTION_ASM_OP \
532 ((TARGET_DEC_ASM) ? "\t.psect\tcode,i,ro,con" : "\t.text")
533
534 /* Output before writable data. */
535
536 #define DATA_SECTION_ASM_OP \
537 ((TARGET_DEC_ASM) ? "\t.psect\tdata,d,rw,con" : "\t.data")
538
539 /* Output before read-only data. Same as read-write data for non-DEC
540 assemblers because they don't know about .rodata. */
541
542 #define READONLY_DATA_SECTION_ASM_OP \
543 ((TARGET_DEC_ASM) ? "\t.psect\trodata,d,ro,con" : "\t.data")
544
545 /* How to refer to registers in assembler output.
546 This sequence is indexed by compiler's hard-register-number (see above). */
547
548 #define REGISTER_NAMES \
549 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \
550 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5", "ap", "cc", \
551 "fcc" }
552
553 /* Globalizing directive for a label. */
554 #define GLOBAL_ASM_OP "\t.globl\t"
555
556 /* The prefix to add to user-visible assembler symbols. For the DEC
557 assembler case, this is not used. */
558
559 #define USER_LABEL_PREFIX "_"
560
561 /* Line separators. */
562
563 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
564 ((C) == '\n' || (!TARGET_DEC_ASM && (C) == ';'))
565
566 /* This is how to store into the string LABEL
567 the symbol_ref name of an internal numbered label where
568 PREFIX is the class of label and NUM is the number within the class.
569 This is suitable for output with `assemble_name'. */
570
571 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
572 pdp11_gen_int_label ((LABEL), (PREFIX), (NUM))
573
574 /* Emit a string. */
575
576 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
577 output_ascii (FILE, P, SIZE)
578
579 /* Print a label reference, with _ prefix if not DEC. */
580
581 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
582 pdp11_output_labelref ((STREAM), (NAME))
583
584 /* Equate a symbol to an expression. */
585
586 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
587 pdp11_output_def (STREAM, NAME, VALUE)
588
589 /* Mark a reference to an external symbol. Needed for DEC assembler. */
590
591 #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) \
592 if (TARGET_DEC_ASM) \
593 fprintf ((STREAM), "\t.globl\t%s\n", (NAME))
594
595 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
596 if (TARGET_DEC_ASM) \
597 fprintf ((STREAM), ".title\t%s\n", (NAME))
598
599 /* This is how to output an element of a case-vector that is absolute. */
600
601 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
602 pdp11_output_addr_vec_elt (FILE, VALUE)
603
604 /* This is how to output an assembler line that says to advance the
605 location counter to a multiple of 2**LOG bytes. Only values 0 and
606 1 should appear, but due to PR87795 larger values (which are not
607 supported) can also appear. So we treat all alignment of LOG >= 1
608 as word (2 byte) alignment.
609 */
610
611 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
612 if (LOG != 0) \
613 fprintf (FILE, "\t.even\n")
614
615 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
616 if (TARGET_DEC_ASM) \
617 fprintf (FILE, "\t.blkb\t%o\n", (SIZE) & 0xffff); \
618 else \
619 fprintf (FILE, "\t.=.+ %#o\n", (SIZE) & 0xffff);
620
621 /* This says how to output an assembler line
622 to define a global common symbol. */
623
624 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
625 pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, true)
626
627 /* This says how to output an assembler line
628 to define a local common symbol. */
629
630 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
631 pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, false)
632
633 /* Print a memory address as an operand to reference that memory location. */
634
635 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
636 print_operand_address (FILE, ADDR)
637
638 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
639 fprintf (FILE, "\tmov\t%s,-(sp)\n", reg_names[REGNO])
640
641 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
642 fprintf (FILE, "\tmov\t(sp)+,%s\n", reg_names[REGNO])
643
644 #define TRAMPOLINE_SIZE 8
645 #define TRAMPOLINE_ALIGNMENT 16
646
647 #define BRANCH_COST(speed_p, predictable_p) 1
648
649 #define COMPARE_FLAG_MODE HImode
650
651 /* May be overridden by command option processing. */
652 #define TARGET_HAVE_NAMED_SECTIONS false
653
654 /* pdp11-unknown-aout target has no support of C99 runtime */
655 #undef TARGET_LIBC_HAS_FUNCTION
656 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function