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1 ;; Machine description for RISC-V 'V' Extension for GNU compiler.
2 ;; Copyright (C) 2022-2024 Free Software Foundation, Inc.
3 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
4
5 ;; This file is part of GCC.
6
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;; This file describes the RISC-V 'V' Extension, Version 1.0.
22 ;;
23 ;; This file include :
24 ;;
25 ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
26 ;; - Auto-vectorization (autovec.md)
27 ;; - Optimization (autovec-opt.md)
28
29 (include "vector-iterators.md")
30
31 (define_constants [
32 (INVALID_ATTRIBUTE 255)
33 (X0_REGNUM 0)
34 ])
35
36 ;; True if the type is RVV instructions that include VTYPE
37 ;; global status register in the use op list.
38 ;; We known VTYPE has 4 fields: SEW, LMUL, TA, MA.
39 ;; The instruction need any of VTYPE field is set as true
40 ;; in this attribute.
41 (define_attr "has_vtype_op" "false,true"
42 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
43 vldux,vldox,vstux,vstox,vldff,\
44 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
45 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
46 vsalu,vaalu,vsmul,vsshift,vnclip,\
47 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
48 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
49 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
50 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
51 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
52 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
53 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
54 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
55 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\
56 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
57 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
58 (const_string "true")]
59 (const_string "false")))
60
61 ;; True if the type is RVV instructions that include VL
62 ;; global status register in the use op list.
63 ;; The instruction need vector length to be specified is set
64 ;; in this attribute.
65 (define_attr "has_vl_op" "false,true"
66 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
67 vldux,vldox,vstux,vstox,vldff,\
68 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
69 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
70 vsalu,vaalu,vsmul,vsshift,vnclip,\
71 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
72 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
73 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
74 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
75 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
76 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
77 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
78 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
79 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\
80 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
81 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
82 (const_string "true")]
83 (const_string "false")))
84
85 ;; The default SEW of RVV instruction. This attribute doesn't mean the instruction
86 ;; is necessary to require SEW check for example vlm.v which require ratio to
87 ;; check. However, we need default value of SEW for vsetvl instruction since there
88 ;; is no field for ratio in the vsetvl instruction encoding.
89 (define_attr "sew" ""
90 (cond [(eq_attr "mode" "RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
91 RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
92 RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\
93 RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\
94 RVVM1x6QI,RVVMF2x6QI,RVVMF4x6QI,RVVMF8x6QI,\
95 RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\
96 RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
97 RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
98 RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
99 V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
100 V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
101 (const_int 8)
102 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
103 RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
104 RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\
105 RVVM1x6HI,RVVMF2x6HI,RVVMF4x6HI,\
106 RVVM1x5HI,RVVMF2x5HI,RVVMF4x5HI,\
107 RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\
108 RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\
109 RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\
110 RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\
111 RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\
112 RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\
113 RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,\
114 RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\
115 RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\
116 RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\
117 RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4x2HF,\
118 V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,\
119 V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF")
120 (const_int 16)
121 (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\
122 RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\
123 RVVM1x8SI,RVVMF2x8SI,\
124 RVVM1x7SI,RVVMF2x7SI,\
125 RVVM1x6SI,RVVMF2x6SI,\
126 RVVM1x5SI,RVVMF2x5SI,\
127 RVVMF2x4SI,RVVMF2x3SI,\
128 RVVM2x4SI,RVVM1x4SI,\
129 RVVM2x3SI,RVVM1x3SI,\
130 RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\
131 RVVM1x8SF,RVVMF2x8SF,\
132 RVVM1x7SF,RVVMF2x7SF,\
133 RVVM1x6SF,RVVMF2x6SF,\
134 RVVM1x5SF,RVVMF2x5SF,\
135 RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\
136 RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\
137 RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\
138 V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,\
139 V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF")
140 (const_int 32)
141 (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\
142 RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\
143 RVVM1x8DI,RVVM1x7DI,RVVM1x6DI,RVVM1x5DI,\
144 RVVM2x4DI,RVVM1x4DI,\
145 RVVM2x3DI,RVVM1x3DI,\
146 RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,\
147 RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\
148 RVVM2x4DF,RVVM1x4DF,\
149 RVVM2x3DF,RVVM1x3DF,\
150 RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\
151 V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,\
152 V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
153 (const_int 64)]
154 (const_int INVALID_ATTRIBUTE)))
155
156 ;; Ditto to LMUL.
157 (define_attr "vlmul" ""
158 (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::LMUL_8")
159 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4")
160 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2")
161 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1")
162 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "riscv_vector::LMUL_F2")
163 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "riscv_vector::LMUL_F4")
164 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "riscv_vector::LMUL_F8")
165 (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8")
166 (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4")
167 (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2")
168 (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1")
169 (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2")
170 (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4")
171 (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8")
172 (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4")
173 (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2")
174 (eq_attr "mode" "RVVM1HF") (symbol_ref "riscv_vector::LMUL_1")
175 (eq_attr "mode" "RVVMF2HF") (symbol_ref "riscv_vector::LMUL_F2")
176 (eq_attr "mode" "RVVMF4HF") (symbol_ref "riscv_vector::LMUL_F4")
177 (eq_attr "mode" "RVVM8SI") (symbol_ref "riscv_vector::LMUL_8")
178 (eq_attr "mode" "RVVM4SI") (symbol_ref "riscv_vector::LMUL_4")
179 (eq_attr "mode" "RVVM2SI") (symbol_ref "riscv_vector::LMUL_2")
180 (eq_attr "mode" "RVVM1SI") (symbol_ref "riscv_vector::LMUL_1")
181 (eq_attr "mode" "RVVMF2SI") (symbol_ref "riscv_vector::LMUL_F2")
182 (eq_attr "mode" "RVVM8SF") (symbol_ref "riscv_vector::LMUL_8")
183 (eq_attr "mode" "RVVM4SF") (symbol_ref "riscv_vector::LMUL_4")
184 (eq_attr "mode" "RVVM2SF") (symbol_ref "riscv_vector::LMUL_2")
185 (eq_attr "mode" "RVVM1SF") (symbol_ref "riscv_vector::LMUL_1")
186 (eq_attr "mode" "RVVMF2SF") (symbol_ref "riscv_vector::LMUL_F2")
187 (eq_attr "mode" "RVVM8DI") (symbol_ref "riscv_vector::LMUL_8")
188 (eq_attr "mode" "RVVM4DI") (symbol_ref "riscv_vector::LMUL_4")
189 (eq_attr "mode" "RVVM2DI") (symbol_ref "riscv_vector::LMUL_2")
190 (eq_attr "mode" "RVVM1DI") (symbol_ref "riscv_vector::LMUL_1")
191 (eq_attr "mode" "RVVM8DF") (symbol_ref "riscv_vector::LMUL_8")
192 (eq_attr "mode" "RVVM4DF") (symbol_ref "riscv_vector::LMUL_4")
193 (eq_attr "mode" "RVVM2DF") (symbol_ref "riscv_vector::LMUL_2")
194 (eq_attr "mode" "RVVM1DF") (symbol_ref "riscv_vector::LMUL_1")
195 (eq_attr "mode" "RVVM1x8QI") (symbol_ref "riscv_vector::LMUL_1")
196 (eq_attr "mode" "RVVMF2x8QI") (symbol_ref "riscv_vector::LMUL_F2")
197 (eq_attr "mode" "RVVMF4x8QI") (symbol_ref "riscv_vector::LMUL_F4")
198 (eq_attr "mode" "RVVMF8x8QI") (symbol_ref "riscv_vector::LMUL_F8")
199 (eq_attr "mode" "RVVM1x7QI") (symbol_ref "riscv_vector::LMUL_1")
200 (eq_attr "mode" "RVVMF2x7QI") (symbol_ref "riscv_vector::LMUL_F2")
201 (eq_attr "mode" "RVVMF4x7QI") (symbol_ref "riscv_vector::LMUL_F4")
202 (eq_attr "mode" "RVVMF8x7QI") (symbol_ref "riscv_vector::LMUL_F8")
203 (eq_attr "mode" "RVVM1x6QI") (symbol_ref "riscv_vector::LMUL_1")
204 (eq_attr "mode" "RVVMF2x6QI") (symbol_ref "riscv_vector::LMUL_F2")
205 (eq_attr "mode" "RVVMF4x6QI") (symbol_ref "riscv_vector::LMUL_F4")
206 (eq_attr "mode" "RVVMF8x6QI") (symbol_ref "riscv_vector::LMUL_F8")
207 (eq_attr "mode" "RVVM1x5QI") (symbol_ref "riscv_vector::LMUL_1")
208 (eq_attr "mode" "RVVMF2x5QI") (symbol_ref "riscv_vector::LMUL_F2")
209 (eq_attr "mode" "RVVMF4x5QI") (symbol_ref "riscv_vector::LMUL_F4")
210 (eq_attr "mode" "RVVMF8x5QI") (symbol_ref "riscv_vector::LMUL_F8")
211 (eq_attr "mode" "RVVM2x4QI") (symbol_ref "riscv_vector::LMUL_2")
212 (eq_attr "mode" "RVVM1x4QI") (symbol_ref "riscv_vector::LMUL_1")
213 (eq_attr "mode" "RVVMF2x4QI") (symbol_ref "riscv_vector::LMUL_F2")
214 (eq_attr "mode" "RVVMF4x4QI") (symbol_ref "riscv_vector::LMUL_F4")
215 (eq_attr "mode" "RVVMF8x4QI") (symbol_ref "riscv_vector::LMUL_F8")
216 (eq_attr "mode" "RVVM2x3QI") (symbol_ref "riscv_vector::LMUL_2")
217 (eq_attr "mode" "RVVM1x3QI") (symbol_ref "riscv_vector::LMUL_1")
218 (eq_attr "mode" "RVVMF2x3QI") (symbol_ref "riscv_vector::LMUL_F2")
219 (eq_attr "mode" "RVVMF4x3QI") (symbol_ref "riscv_vector::LMUL_F4")
220 (eq_attr "mode" "RVVMF8x3QI") (symbol_ref "riscv_vector::LMUL_F8")
221 (eq_attr "mode" "RVVM4x2QI") (symbol_ref "riscv_vector::LMUL_4")
222 (eq_attr "mode" "RVVM2x2QI") (symbol_ref "riscv_vector::LMUL_2")
223 (eq_attr "mode" "RVVM1x2QI") (symbol_ref "riscv_vector::LMUL_1")
224 (eq_attr "mode" "RVVMF2x2QI") (symbol_ref "riscv_vector::LMUL_F2")
225 (eq_attr "mode" "RVVMF4x2QI") (symbol_ref "riscv_vector::LMUL_F4")
226 (eq_attr "mode" "RVVMF8x2QI") (symbol_ref "riscv_vector::LMUL_F8")
227 (eq_attr "mode" "RVVM1x8HI") (symbol_ref "riscv_vector::LMUL_1")
228 (eq_attr "mode" "RVVMF2x8HI") (symbol_ref "riscv_vector::LMUL_F2")
229 (eq_attr "mode" "RVVMF4x8HI") (symbol_ref "riscv_vector::LMUL_F4")
230 (eq_attr "mode" "RVVM1x7HI") (symbol_ref "riscv_vector::LMUL_1")
231 (eq_attr "mode" "RVVMF2x7HI") (symbol_ref "riscv_vector::LMUL_F2")
232 (eq_attr "mode" "RVVMF4x7HI") (symbol_ref "riscv_vector::LMUL_F4")
233 (eq_attr "mode" "RVVM1x6HI") (symbol_ref "riscv_vector::LMUL_1")
234 (eq_attr "mode" "RVVMF2x6HI") (symbol_ref "riscv_vector::LMUL_F2")
235 (eq_attr "mode" "RVVMF4x6HI") (symbol_ref "riscv_vector::LMUL_F4")
236 (eq_attr "mode" "RVVM1x5HI") (symbol_ref "riscv_vector::LMUL_1")
237 (eq_attr "mode" "RVVMF2x5HI") (symbol_ref "riscv_vector::LMUL_F2")
238 (eq_attr "mode" "RVVMF4x5HI") (symbol_ref "riscv_vector::LMUL_F4")
239 (eq_attr "mode" "RVVM2x4HI") (symbol_ref "riscv_vector::LMUL_2")
240 (eq_attr "mode" "RVVM1x4HI") (symbol_ref "riscv_vector::LMUL_1")
241 (eq_attr "mode" "RVVMF2x4HI") (symbol_ref "riscv_vector::LMUL_F2")
242 (eq_attr "mode" "RVVMF4x4HI") (symbol_ref "riscv_vector::LMUL_F4")
243 (eq_attr "mode" "RVVM2x3HI") (symbol_ref "riscv_vector::LMUL_2")
244 (eq_attr "mode" "RVVM1x3HI") (symbol_ref "riscv_vector::LMUL_1")
245 (eq_attr "mode" "RVVMF2x3HI") (symbol_ref "riscv_vector::LMUL_F2")
246 (eq_attr "mode" "RVVMF4x3HI") (symbol_ref "riscv_vector::LMUL_F4")
247 (eq_attr "mode" "RVVM4x2HI") (symbol_ref "riscv_vector::LMUL_4")
248 (eq_attr "mode" "RVVM2x2HI") (symbol_ref "riscv_vector::LMUL_2")
249 (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1")
250 (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2")
251 (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4")
252 (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1")
253 (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2")
254 (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4")
255 (eq_attr "mode" "RVVM1x7HF") (symbol_ref "riscv_vector::LMUL_1")
256 (eq_attr "mode" "RVVMF2x7HF") (symbol_ref "riscv_vector::LMUL_F2")
257 (eq_attr "mode" "RVVMF4x7HF") (symbol_ref "riscv_vector::LMUL_F4")
258 (eq_attr "mode" "RVVM1x6HF") (symbol_ref "riscv_vector::LMUL_1")
259 (eq_attr "mode" "RVVMF2x6HF") (symbol_ref "riscv_vector::LMUL_F2")
260 (eq_attr "mode" "RVVMF4x6HF") (symbol_ref "riscv_vector::LMUL_F4")
261 (eq_attr "mode" "RVVM1x5HF") (symbol_ref "riscv_vector::LMUL_1")
262 (eq_attr "mode" "RVVMF2x5HF") (symbol_ref "riscv_vector::LMUL_F2")
263 (eq_attr "mode" "RVVMF4x5HF") (symbol_ref "riscv_vector::LMUL_F4")
264 (eq_attr "mode" "RVVM2x4HF") (symbol_ref "riscv_vector::LMUL_2")
265 (eq_attr "mode" "RVVM1x4HF") (symbol_ref "riscv_vector::LMUL_1")
266 (eq_attr "mode" "RVVMF2x4HF") (symbol_ref "riscv_vector::LMUL_F2")
267 (eq_attr "mode" "RVVMF4x4HF") (symbol_ref "riscv_vector::LMUL_F4")
268 (eq_attr "mode" "RVVM2x3HF") (symbol_ref "riscv_vector::LMUL_2")
269 (eq_attr "mode" "RVVM1x3HF") (symbol_ref "riscv_vector::LMUL_1")
270 (eq_attr "mode" "RVVMF2x3HF") (symbol_ref "riscv_vector::LMUL_F2")
271 (eq_attr "mode" "RVVMF4x3HF") (symbol_ref "riscv_vector::LMUL_F4")
272 (eq_attr "mode" "RVVM4x2HF") (symbol_ref "riscv_vector::LMUL_4")
273 (eq_attr "mode" "RVVM2x2HF") (symbol_ref "riscv_vector::LMUL_2")
274 (eq_attr "mode" "RVVM1x2HF") (symbol_ref "riscv_vector::LMUL_1")
275 (eq_attr "mode" "RVVMF2x2HF") (symbol_ref "riscv_vector::LMUL_F2")
276 (eq_attr "mode" "RVVMF4x2HF") (symbol_ref "riscv_vector::LMUL_F4")
277 (eq_attr "mode" "RVVM1x8SI") (symbol_ref "riscv_vector::LMUL_1")
278 (eq_attr "mode" "RVVMF2x8SI") (symbol_ref "riscv_vector::LMUL_F2")
279 (eq_attr "mode" "RVVM1x7SI") (symbol_ref "riscv_vector::LMUL_1")
280 (eq_attr "mode" "RVVMF2x7SI") (symbol_ref "riscv_vector::LMUL_F2")
281 (eq_attr "mode" "RVVM1x6SI") (symbol_ref "riscv_vector::LMUL_1")
282 (eq_attr "mode" "RVVMF2x6SI") (symbol_ref "riscv_vector::LMUL_F2")
283 (eq_attr "mode" "RVVM1x5SI") (symbol_ref "riscv_vector::LMUL_1")
284 (eq_attr "mode" "RVVMF2x5SI") (symbol_ref "riscv_vector::LMUL_F2")
285 (eq_attr "mode" "RVVM2x4SI") (symbol_ref "riscv_vector::LMUL_2")
286 (eq_attr "mode" "RVVM1x4SI") (symbol_ref "riscv_vector::LMUL_1")
287 (eq_attr "mode" "RVVMF2x4SI") (symbol_ref "riscv_vector::LMUL_F2")
288 (eq_attr "mode" "RVVM2x3SI") (symbol_ref "riscv_vector::LMUL_2")
289 (eq_attr "mode" "RVVM1x3SI") (symbol_ref "riscv_vector::LMUL_1")
290 (eq_attr "mode" "RVVMF2x3SI") (symbol_ref "riscv_vector::LMUL_F2")
291 (eq_attr "mode" "RVVM4x2SI") (symbol_ref "riscv_vector::LMUL_4")
292 (eq_attr "mode" "RVVM2x2SI") (symbol_ref "riscv_vector::LMUL_2")
293 (eq_attr "mode" "RVVM1x2SI") (symbol_ref "riscv_vector::LMUL_1")
294 (eq_attr "mode" "RVVMF2x2SI") (symbol_ref "riscv_vector::LMUL_F2")
295 (eq_attr "mode" "RVVM1x8SF") (symbol_ref "riscv_vector::LMUL_1")
296 (eq_attr "mode" "RVVMF2x8SF") (symbol_ref "riscv_vector::LMUL_F2")
297 (eq_attr "mode" "RVVM1x7SF") (symbol_ref "riscv_vector::LMUL_1")
298 (eq_attr "mode" "RVVMF2x7SF") (symbol_ref "riscv_vector::LMUL_F2")
299 (eq_attr "mode" "RVVM1x6SF") (symbol_ref "riscv_vector::LMUL_1")
300 (eq_attr "mode" "RVVMF2x6SF") (symbol_ref "riscv_vector::LMUL_F2")
301 (eq_attr "mode" "RVVM1x5SF") (symbol_ref "riscv_vector::LMUL_1")
302 (eq_attr "mode" "RVVMF2x5SF") (symbol_ref "riscv_vector::LMUL_F2")
303 (eq_attr "mode" "RVVM2x4SF") (symbol_ref "riscv_vector::LMUL_2")
304 (eq_attr "mode" "RVVM1x4SF") (symbol_ref "riscv_vector::LMUL_1")
305 (eq_attr "mode" "RVVMF2x4SF") (symbol_ref "riscv_vector::LMUL_F2")
306 (eq_attr "mode" "RVVM2x3SF") (symbol_ref "riscv_vector::LMUL_2")
307 (eq_attr "mode" "RVVM1x3SF") (symbol_ref "riscv_vector::LMUL_1")
308 (eq_attr "mode" "RVVMF2x3SF") (symbol_ref "riscv_vector::LMUL_F2")
309 (eq_attr "mode" "RVVM4x2SF") (symbol_ref "riscv_vector::LMUL_4")
310 (eq_attr "mode" "RVVM2x2SF") (symbol_ref "riscv_vector::LMUL_2")
311 (eq_attr "mode" "RVVM1x2SF") (symbol_ref "riscv_vector::LMUL_1")
312 (eq_attr "mode" "RVVMF2x2SF") (symbol_ref "riscv_vector::LMUL_F2")
313 (eq_attr "mode" "RVVM1x8DI") (symbol_ref "riscv_vector::LMUL_1")
314 (eq_attr "mode" "RVVM1x7DI") (symbol_ref "riscv_vector::LMUL_1")
315 (eq_attr "mode" "RVVM1x6DI") (symbol_ref "riscv_vector::LMUL_1")
316 (eq_attr "mode" "RVVM1x5DI") (symbol_ref "riscv_vector::LMUL_1")
317 (eq_attr "mode" "RVVM2x4DI") (symbol_ref "riscv_vector::LMUL_2")
318 (eq_attr "mode" "RVVM1x4DI") (symbol_ref "riscv_vector::LMUL_1")
319 (eq_attr "mode" "RVVM2x3DI") (symbol_ref "riscv_vector::LMUL_2")
320 (eq_attr "mode" "RVVM1x3DI") (symbol_ref "riscv_vector::LMUL_1")
321 (eq_attr "mode" "RVVM4x2DI") (symbol_ref "riscv_vector::LMUL_4")
322 (eq_attr "mode" "RVVM2x2DI") (symbol_ref "riscv_vector::LMUL_2")
323 (eq_attr "mode" "RVVM1x2DI") (symbol_ref "riscv_vector::LMUL_1")
324 (eq_attr "mode" "RVVM1x8DF") (symbol_ref "riscv_vector::LMUL_1")
325 (eq_attr "mode" "RVVM1x7DF") (symbol_ref "riscv_vector::LMUL_1")
326 (eq_attr "mode" "RVVM1x6DF") (symbol_ref "riscv_vector::LMUL_1")
327 (eq_attr "mode" "RVVM1x5DF") (symbol_ref "riscv_vector::LMUL_1")
328 (eq_attr "mode" "RVVM2x4DF") (symbol_ref "riscv_vector::LMUL_2")
329 (eq_attr "mode" "RVVM1x4DF") (symbol_ref "riscv_vector::LMUL_1")
330 (eq_attr "mode" "RVVM2x3DF") (symbol_ref "riscv_vector::LMUL_2")
331 (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1")
332 (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4")
333 (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2")
334 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
335
336 ;; VLS modes.
337 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
338 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
339 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
340 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
341 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
342 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
343 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
344 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
345 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
346 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
347 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
348 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
349 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
350 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
351 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
352 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
353 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
354 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_V16HImode)")
355 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_V32HImode)")
356 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_V64HImode)")
357 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E_V128HImode)")
358 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E_V256HImode)")
359 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E_V512HImode)")
360 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(E_V1024HImode)")
361 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(E_V2048HImode)")
362 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V1SImode)")
363 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V2SImode)")
364 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
365 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V8SImode)")
366 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_V16SImode)")
367 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_V32SImode)")
368 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_V64SImode)")
369 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E_V128SImode)")
370 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E_V256SImode)")
371 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E_V512SImode)")
372 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(E_V1024SImode)")
373 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V1DImode)")
374 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
375 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V4DImode)")
376 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V8DImode)")
377 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_V16DImode)")
378 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_V32DImode)")
379 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_V64DImode)")
380 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E_V128DImode)")
381 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E_V256DImode)")
382 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E_V512DImode)")
383 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V1HFmode)")
384 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V2HFmode)")
385 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V4HFmode)")
386 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V8HFmode)")
387 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_V16HFmode)")
388 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_V32HFmode)")
389 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_V64HFmode)")
390 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E_V128HFmode)")
391 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E_V256HFmode)")
392 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E_V512HFmode)")
393 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(E_V1024HFmode)")
394 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(E_V2048HFmode)")
395 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V1SFmode)")
396 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V2SFmode)")
397 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V4SFmode)")
398 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V8SFmode)")
399 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_V16SFmode)")
400 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_V32SFmode)")
401 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_V64SFmode)")
402 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E_V128SFmode)")
403 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E_V256SFmode)")
404 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E_V512SFmode)")
405 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(E_V1024SFmode)")
406 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V1DFmode)")
407 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V2DFmode)")
408 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V4DFmode)")
409 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V8DFmode)")
410 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_V16DFmode)")
411 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_V32DFmode)")
412 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_V64DFmode)")
413 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E_V128DFmode)")
414 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E_V256DFmode)")
415 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E_V512DFmode)")]
416 (const_int INVALID_ATTRIBUTE)))
417
418 ;; It is valid for instruction that require sew/lmul ratio.
419 (define_attr "ratio" ""
420 (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
421 vialu,vshift,vicmp,vimul,vidiv,vsalu,\
422 vext,viwalu,viwmul,vicalu,vnshift,\
423 vimuladd,vimerge,vaalu,vsmul,vsshift,\
424 vnclip,viminmax,viwmuladd,vmffs,vmsfs,\
425 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
426 vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
427 vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
428 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
429 vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
430 viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
431 vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
432 vislide1up,vislide1down,vfslide1up,vfslide1down,\
433 vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox,\
434 vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll,\
435 vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
436 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
437 vsm3me,vsm3c")
438 (const_int INVALID_ATTRIBUTE)
439 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
440 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
441 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
442 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (const_int 8)
443 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (const_int 16)
444 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (const_int 32)
445 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (const_int 64)
446 (eq_attr "mode" "RVVM8HI") (const_int 2)
447 (eq_attr "mode" "RVVM4HI") (const_int 4)
448 (eq_attr "mode" "RVVM2HI") (const_int 8)
449 (eq_attr "mode" "RVVM1HI") (const_int 16)
450 (eq_attr "mode" "RVVMF2HI") (const_int 32)
451 (eq_attr "mode" "RVVMF4HI") (const_int 64)
452 (eq_attr "mode" "RVVM8HF") (const_int 2)
453 (eq_attr "mode" "RVVM4HF") (const_int 4)
454 (eq_attr "mode" "RVVM2HF") (const_int 8)
455 (eq_attr "mode" "RVVM1HF") (const_int 16)
456 (eq_attr "mode" "RVVMF2HF") (const_int 32)
457 (eq_attr "mode" "RVVMF4HF") (const_int 64)
458 (eq_attr "mode" "RVVM8SI") (const_int 4)
459 (eq_attr "mode" "RVVM4SI") (const_int 8)
460 (eq_attr "mode" "RVVM2SI") (const_int 16)
461 (eq_attr "mode" "RVVM1SI") (const_int 32)
462 (eq_attr "mode" "RVVMF2SI") (const_int 64)
463 (eq_attr "mode" "RVVM8SF") (const_int 4)
464 (eq_attr "mode" "RVVM4SF") (const_int 8)
465 (eq_attr "mode" "RVVM2SF") (const_int 16)
466 (eq_attr "mode" "RVVM1SF") (const_int 32)
467 (eq_attr "mode" "RVVMF2SF") (const_int 64)
468 (eq_attr "mode" "RVVM8DI") (const_int 8)
469 (eq_attr "mode" "RVVM4DI") (const_int 16)
470 (eq_attr "mode" "RVVM2DI") (const_int 32)
471 (eq_attr "mode" "RVVM1DI") (const_int 64)
472 (eq_attr "mode" "RVVM8DF") (const_int 8)
473 (eq_attr "mode" "RVVM4DF") (const_int 16)
474 (eq_attr "mode" "RVVM2DF") (const_int 32)
475 (eq_attr "mode" "RVVM1DF") (const_int 64)
476 (eq_attr "mode" "RVVM1x8QI") (const_int 8)
477 (eq_attr "mode" "RVVMF2x8QI") (const_int 16)
478 (eq_attr "mode" "RVVMF4x8QI") (const_int 32)
479 (eq_attr "mode" "RVVMF8x8QI") (const_int 64)
480 (eq_attr "mode" "RVVM1x7QI") (const_int 8)
481 (eq_attr "mode" "RVVMF2x7QI") (const_int 16)
482 (eq_attr "mode" "RVVMF4x7QI") (const_int 32)
483 (eq_attr "mode" "RVVMF8x7QI") (const_int 64)
484 (eq_attr "mode" "RVVM1x6QI") (const_int 8)
485 (eq_attr "mode" "RVVMF2x6QI") (const_int 16)
486 (eq_attr "mode" "RVVMF4x6QI") (const_int 32)
487 (eq_attr "mode" "RVVMF8x6QI") (const_int 64)
488 (eq_attr "mode" "RVVM1x5QI") (const_int 8)
489 (eq_attr "mode" "RVVMF2x5QI") (const_int 16)
490 (eq_attr "mode" "RVVMF4x5QI") (const_int 32)
491 (eq_attr "mode" "RVVMF8x5QI") (const_int 64)
492 (eq_attr "mode" "RVVM2x4QI") (const_int 4)
493 (eq_attr "mode" "RVVM1x4QI") (const_int 8)
494 (eq_attr "mode" "RVVMF2x4QI") (const_int 16)
495 (eq_attr "mode" "RVVMF4x4QI") (const_int 32)
496 (eq_attr "mode" "RVVMF8x4QI") (const_int 64)
497 (eq_attr "mode" "RVVM2x3QI") (const_int 4)
498 (eq_attr "mode" "RVVM1x3QI") (const_int 8)
499 (eq_attr "mode" "RVVMF2x3QI") (const_int 16)
500 (eq_attr "mode" "RVVMF4x3QI") (const_int 32)
501 (eq_attr "mode" "RVVMF8x3QI") (const_int 64)
502 (eq_attr "mode" "RVVM4x2QI") (const_int 2)
503 (eq_attr "mode" "RVVM2x2QI") (const_int 4)
504 (eq_attr "mode" "RVVM1x2QI") (const_int 8)
505 (eq_attr "mode" "RVVMF2x2QI") (const_int 16)
506 (eq_attr "mode" "RVVMF4x2QI") (const_int 32)
507 (eq_attr "mode" "RVVMF8x2QI") (const_int 64)
508 (eq_attr "mode" "RVVM1x8HI") (const_int 16)
509 (eq_attr "mode" "RVVMF2x8HI") (const_int 32)
510 (eq_attr "mode" "RVVMF4x8HI") (const_int 64)
511 (eq_attr "mode" "RVVM1x7HI") (const_int 16)
512 (eq_attr "mode" "RVVMF2x7HI") (const_int 32)
513 (eq_attr "mode" "RVVMF4x7HI") (const_int 64)
514 (eq_attr "mode" "RVVM1x6HI") (const_int 16)
515 (eq_attr "mode" "RVVMF2x6HI") (const_int 32)
516 (eq_attr "mode" "RVVMF4x6HI") (const_int 64)
517 (eq_attr "mode" "RVVM1x5HI") (const_int 16)
518 (eq_attr "mode" "RVVMF2x5HI") (const_int 32)
519 (eq_attr "mode" "RVVMF4x5HI") (const_int 64)
520 (eq_attr "mode" "RVVM2x4HI") (const_int 8)
521 (eq_attr "mode" "RVVM1x4HI") (const_int 16)
522 (eq_attr "mode" "RVVMF2x4HI") (const_int 32)
523 (eq_attr "mode" "RVVMF4x4HI") (const_int 64)
524 (eq_attr "mode" "RVVM2x3HI") (const_int 8)
525 (eq_attr "mode" "RVVM1x3HI") (const_int 16)
526 (eq_attr "mode" "RVVMF2x3HI") (const_int 32)
527 (eq_attr "mode" "RVVMF4x3HI") (const_int 64)
528 (eq_attr "mode" "RVVM4x2HI") (const_int 4)
529 (eq_attr "mode" "RVVM2x2HI") (const_int 8)
530 (eq_attr "mode" "RVVM1x2HI") (const_int 16)
531 (eq_attr "mode" "RVVMF2x2HI") (const_int 32)
532 (eq_attr "mode" "RVVMF4x2HI") (const_int 64)
533 (eq_attr "mode" "RVVM1x8HF") (const_int 16)
534 (eq_attr "mode" "RVVMF2x8HF") (const_int 32)
535 (eq_attr "mode" "RVVMF4x8HF") (const_int 64)
536 (eq_attr "mode" "RVVM1x7HF") (const_int 16)
537 (eq_attr "mode" "RVVMF2x7HF") (const_int 32)
538 (eq_attr "mode" "RVVMF4x7HF") (const_int 64)
539 (eq_attr "mode" "RVVM1x6HF") (const_int 16)
540 (eq_attr "mode" "RVVMF2x6HF") (const_int 32)
541 (eq_attr "mode" "RVVMF4x6HF") (const_int 64)
542 (eq_attr "mode" "RVVM1x5HF") (const_int 16)
543 (eq_attr "mode" "RVVMF2x5HF") (const_int 32)
544 (eq_attr "mode" "RVVMF4x5HF") (const_int 64)
545 (eq_attr "mode" "RVVM2x4HF") (const_int 8)
546 (eq_attr "mode" "RVVM1x4HF") (const_int 16)
547 (eq_attr "mode" "RVVMF2x4HF") (const_int 32)
548 (eq_attr "mode" "RVVMF4x4HF") (const_int 64)
549 (eq_attr "mode" "RVVM2x3HF") (const_int 8)
550 (eq_attr "mode" "RVVM1x3HF") (const_int 16)
551 (eq_attr "mode" "RVVMF2x3HF") (const_int 32)
552 (eq_attr "mode" "RVVMF4x3HF") (const_int 64)
553 (eq_attr "mode" "RVVM4x2HF") (const_int 4)
554 (eq_attr "mode" "RVVM2x2HF") (const_int 8)
555 (eq_attr "mode" "RVVM1x2HF") (const_int 16)
556 (eq_attr "mode" "RVVMF2x2HF") (const_int 32)
557 (eq_attr "mode" "RVVMF4x2HF") (const_int 64)
558 (eq_attr "mode" "RVVM1x8SI") (const_int 32)
559 (eq_attr "mode" "RVVMF2x8SI") (const_int 64)
560 (eq_attr "mode" "RVVM1x7SI") (const_int 32)
561 (eq_attr "mode" "RVVMF2x7SI") (const_int 64)
562 (eq_attr "mode" "RVVM1x6SI") (const_int 32)
563 (eq_attr "mode" "RVVMF2x6SI") (const_int 64)
564 (eq_attr "mode" "RVVM1x5SI") (const_int 32)
565 (eq_attr "mode" "RVVMF2x5SI") (const_int 64)
566 (eq_attr "mode" "RVVM2x4SI") (const_int 16)
567 (eq_attr "mode" "RVVM1x4SI") (const_int 32)
568 (eq_attr "mode" "RVVMF2x4SI") (const_int 64)
569 (eq_attr "mode" "RVVM2x3SI") (const_int 16)
570 (eq_attr "mode" "RVVM1x3SI") (const_int 32)
571 (eq_attr "mode" "RVVMF2x3SI") (const_int 64)
572 (eq_attr "mode" "RVVM4x2SI") (const_int 8)
573 (eq_attr "mode" "RVVM2x2SI") (const_int 16)
574 (eq_attr "mode" "RVVM1x2SI") (const_int 32)
575 (eq_attr "mode" "RVVMF2x2SI") (const_int 64)
576 (eq_attr "mode" "RVVM1x8SF") (const_int 32)
577 (eq_attr "mode" "RVVMF2x8SF") (const_int 64)
578 (eq_attr "mode" "RVVM1x7SF") (const_int 32)
579 (eq_attr "mode" "RVVMF2x7SF") (const_int 64)
580 (eq_attr "mode" "RVVM1x6SF") (const_int 32)
581 (eq_attr "mode" "RVVMF2x6SF") (const_int 64)
582 (eq_attr "mode" "RVVM1x5SF") (const_int 32)
583 (eq_attr "mode" "RVVMF2x5SF") (const_int 64)
584 (eq_attr "mode" "RVVM2x4SF") (const_int 16)
585 (eq_attr "mode" "RVVM1x4SF") (const_int 32)
586 (eq_attr "mode" "RVVMF2x4SF") (const_int 64)
587 (eq_attr "mode" "RVVM2x3SF") (const_int 16)
588 (eq_attr "mode" "RVVM1x3SF") (const_int 32)
589 (eq_attr "mode" "RVVMF2x3SF") (const_int 64)
590 (eq_attr "mode" "RVVM4x2SF") (const_int 8)
591 (eq_attr "mode" "RVVM2x2SF") (const_int 16)
592 (eq_attr "mode" "RVVM1x2SF") (const_int 32)
593 (eq_attr "mode" "RVVMF2x2SF") (const_int 64)
594 (eq_attr "mode" "RVVM1x8DI") (const_int 64)
595 (eq_attr "mode" "RVVM1x7DI") (const_int 64)
596 (eq_attr "mode" "RVVM1x6DI") (const_int 64)
597 (eq_attr "mode" "RVVM1x5DI") (const_int 64)
598 (eq_attr "mode" "RVVM2x4DI") (const_int 32)
599 (eq_attr "mode" "RVVM1x4DI") (const_int 64)
600 (eq_attr "mode" "RVVM2x3DI") (const_int 32)
601 (eq_attr "mode" "RVVM1x3DI") (const_int 64)
602 (eq_attr "mode" "RVVM4x2DI") (const_int 16)
603 (eq_attr "mode" "RVVM2x2DI") (const_int 32)
604 (eq_attr "mode" "RVVM1x2DI") (const_int 64)
605 (eq_attr "mode" "RVVM1x8DF") (const_int 64)
606 (eq_attr "mode" "RVVM1x7DF") (const_int 64)
607 (eq_attr "mode" "RVVM1x6DF") (const_int 64)
608 (eq_attr "mode" "RVVM1x5DF") (const_int 64)
609 (eq_attr "mode" "RVVM2x4DF") (const_int 32)
610 (eq_attr "mode" "RVVM1x4DF") (const_int 64)
611 (eq_attr "mode" "RVVM2x3DF") (const_int 32)
612 (eq_attr "mode" "RVVM1x3DF") (const_int 64)
613 (eq_attr "mode" "RVVM4x2DF") (const_int 16)
614 (eq_attr "mode" "RVVM2x2DF") (const_int 32)
615 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
616
617 ;; VLS modes.
618 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
619 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
620 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
621 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
622 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
623 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
624 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
625 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
626 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
627 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
628 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
629 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
630 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
631 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
632 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
633 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
634 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V8HImode)")
635 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_V16HImode)")
636 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_V32HImode)")
637 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_V64HImode)")
638 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E_V128HImode)")
639 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E_V256HImode)")
640 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E_V512HImode)")
641 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(E_V1024HImode)")
642 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(E_V2048HImode)")
643 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V1SImode)")
644 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V2SImode)")
645 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V4SImode)")
646 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V8SImode)")
647 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_V16SImode)")
648 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_V32SImode)")
649 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_V64SImode)")
650 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E_V128SImode)")
651 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E_V256SImode)")
652 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E_V512SImode)")
653 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(E_V1024SImode)")
654 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V1DImode)")
655 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V2DImode)")
656 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V4DImode)")
657 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V8DImode)")
658 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_V16DImode)")
659 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_V32DImode)")
660 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_V64DImode)")
661 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E_V128DImode)")
662 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E_V256DImode)")
663 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E_V512DImode)")
664 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V1HFmode)")
665 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V2HFmode)")
666 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V4HFmode)")
667 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V8HFmode)")
668 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_V16HFmode)")
669 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_V32HFmode)")
670 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_V64HFmode)")
671 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E_V128HFmode)")
672 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E_V256HFmode)")
673 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E_V512HFmode)")
674 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(E_V1024HFmode)")
675 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(E_V2048HFmode)")
676 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V1SFmode)")
677 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V2SFmode)")
678 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V4SFmode)")
679 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V8SFmode)")
680 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_V16SFmode)")
681 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_V32SFmode)")
682 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_V64SFmode)")
683 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E_V128SFmode)")
684 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E_V256SFmode)")
685 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E_V512SFmode)")
686 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(E_V1024SFmode)")
687 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V1DFmode)")
688 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V2DFmode)")
689 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V4DFmode)")
690 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V8DFmode)")
691 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_V16DFmode)")
692 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_V32DFmode)")
693 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_V64DFmode)")
694 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E_V128DFmode)")
695 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E_V256DFmode)")
696 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E_V512DFmode)")]
697 (const_int INVALID_ATTRIBUTE)))
698
699 ;; The index of operand[] to get the merge op.
700 (define_attr "merge_op_idx" ""
701 (cond [(eq_attr "type" "vlde,vimov,vfmov,vldm,vlds,vmalu,vldux,vldox,vicmp,\
702 vialu,vshift,viminmax,vimul,vidiv,vsalu,vext,viwalu,\
703 viwmul,vnshift,vaalu,vsmul,vsshift,vnclip,vmsfs,\
704 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
705 vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
706 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
707 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
708 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
709 vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
710 vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh")
711 (const_int 2)
712
713 (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
714 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
715 (const_int 1)
716
717 (eq_attr "type" "vimuladd,vfmuladd")
718 (const_int 5)]
719 (const_int INVALID_ATTRIBUTE)))
720
721 ;; The index of operand[] represents the machine mode of the instruction.
722 (define_attr "mode_idx" ""
723 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\
724 vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\
725 vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\
726 vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\
727 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
728 vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
729 vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
730 vgather,vcompress,vmov,vnclip,vnshift")
731 (const_int 0)
732
733 (eq_attr "type" "vimovvx,vfmovvf")
734 (const_int 1)
735
736 (eq_attr "type" "vssegte,vmpop,vmffs")
737 (const_int 2)
738
739 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
740 vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo")
741 (const_int 3)
742
743 (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
744 (const_int 4)]
745 (const_int INVALID_ATTRIBUTE)))
746
747 ;; The index of operand[] to get the avl op.
748 (define_attr "vl_op_idx" ""
749 (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
750 vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,vldff,\
751 vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
752 vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\
753 vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\
754 vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c")
755 (const_int 4)
756
757 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
758 ;; wheras it is pred_strided_load if operands[3] is vector mode.
759 (eq_attr "type" "vlds")
760 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
761 (const_int 5)
762 (const_int 4))
763
764 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
765 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
766 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
767 vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
768 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
769 vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
770 vror,vwsll,vclmul,vclmulh")
771 (const_int 5)
772
773 (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd")
774 (const_int 6)
775
776 (eq_attr "type" "vmpop,vmffs,vmidx,vssegte,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
777 vaesz,vsm4r")
778 (const_int 3)]
779 (const_int INVALID_ATTRIBUTE)))
780
781 ;; The tail policy op value.
782 (define_attr "ta" ""
783 (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
784 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
785 vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
786 vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\
787 vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c")
788 (symbol_ref "riscv_vector::get_ta(operands[5])")
789
790 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
791 ;; wheras it is pred_strided_load if operands[3] is vector mode.
792 (eq_attr "type" "vlds")
793 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
794 (symbol_ref "riscv_vector::get_ta(operands[6])")
795 (symbol_ref "riscv_vector::get_ta(operands[5])"))
796
797 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
798 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
799 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
800 vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
801 vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
802 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
803 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh")
804 (symbol_ref "riscv_vector::get_ta(operands[6])")
805
806 (eq_attr "type" "vimuladd,vfmuladd")
807 (symbol_ref "riscv_vector::get_ta(operands[7])")
808
809 (eq_attr "type" "vmidx,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,vsm4r")
810 (symbol_ref "riscv_vector::get_ta(operands[4])")]
811 (const_int INVALID_ATTRIBUTE)))
812
813 ;; The mask policy op value.
814 (define_attr "ma" ""
815 (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\
816 vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
817 vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8")
818 (symbol_ref "riscv_vector::get_ma(operands[6])")
819
820 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
821 ;; wheras it is pred_strided_load if operands[3] is vector mode.
822 (eq_attr "type" "vlds")
823 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
824 (symbol_ref "riscv_vector::get_ma(operands[7])")
825 (symbol_ref "riscv_vector::get_ma(operands[6])"))
826
827 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
828 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
829 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
830 vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
831 vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
832 viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
833 vror,vwsll,vclmul,vclmulh")
834 (symbol_ref "riscv_vector::get_ma(operands[7])")
835
836 (eq_attr "type" "vimuladd,vfmuladd")
837 (symbol_ref "riscv_vector::get_ma(operands[8])")
838
839 (eq_attr "type" "vmsfs,vmidx")
840 (symbol_ref "riscv_vector::get_ma(operands[5])")]
841 (const_int INVALID_ATTRIBUTE)))
842
843 ;; The avl type value.
844 (define_attr "avl_type_idx" ""
845 (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vfmov,vext,vimerge,\
846 vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
847 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
848 vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
849 vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8")
850 (const_int 7)
851 (eq_attr "type" "vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\
852 vsm4r")
853 (const_int 5)
854
855 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
856 ;; wheras it is pred_strided_load if operands[3] is vector mode.
857 (eq_attr "type" "vlds")
858 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
859 (const_int 8)
860 (const_int 7))
861
862 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
863 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
864 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
865 vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
866 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
867 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll")
868 (const_int 8)
869 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vclmul,vclmulh")
870 (const_int 5)
871
872 (eq_attr "type" "vimuladd,vfmuladd")
873 (const_int 9)
874
875 (eq_attr "type" "vmsfs,vmidx,vcompress,vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,\
876 vsm4k,vsm3me,vsm3c")
877 (const_int 6)
878
879 (eq_attr "type" "vmpop,vmffs,vssegte,vclz,vctz")
880 (const_int 4)]
881 (const_int INVALID_ATTRIBUTE)))
882
883 ;; Defines rounding mode of an fixed-point operation.
884
885 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
886 (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
887 (cond
888 [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
889 (const_string "rnu")
890
891 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
892 (const_string "rne")
893
894 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
895 (const_string "rdn")
896
897 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
898 (const_string "rod")]
899 (const_string "none"))]
900 (const_string "none")))
901
902 ;; Defines rounding mode of an floating-point operation.
903 (define_attr "frm_mode" ""
904 (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
905 (symbol_ref "riscv_vector::FRM_DYN")]
906 (symbol_ref "riscv_vector::FRM_NONE")))
907
908 ;; -----------------------------------------------------------------
909 ;; ---- Miscellaneous Operations
910 ;; -----------------------------------------------------------------
911
912 (define_insn "@vundefined<mode>"
913 [(set (match_operand:V 0 "register_operand" "=vr")
914 (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
915 "TARGET_VECTOR"
916 ""
917 [(set_attr "type" "vector")])
918
919 (define_insn "@vundefined<mode>"
920 [(set (match_operand:VB 0 "register_operand" "=vr")
921 (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
922 "TARGET_VECTOR"
923 ""
924 [(set_attr "type" "vector")])
925
926 (define_insn "@vundefined<mode>"
927 [(set (match_operand:VT 0 "register_operand" "=vr")
928 (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
929 "TARGET_VECTOR"
930 ""
931 [(set_attr "type" "vector")])
932
933 (define_expand "@vreinterpret<mode>"
934 [(set (match_operand:V 0 "register_operand")
935 (match_operand 1 "vector_any_register_operand"))]
936 "TARGET_VECTOR"
937 {
938 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
939 DONE;
940 }
941 )
942
943 (define_expand "@vreinterpret<mode>"
944 [(set (match_operand:VB 0 "register_operand")
945 (match_operand 1 "vector_any_register_operand"))]
946 "TARGET_VECTOR"
947 {
948 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
949 DONE;
950 }
951 )
952
953 ;; This pattern is used to hold the AVL operand for
954 ;; RVV instructions that implicity use VLMAX AVL.
955 ;; RVV instruction implicitly use GPR that is ultimately
956 ;; defined by this pattern is safe for VSETVL pass emit
957 ;; a vsetvl instruction modify this register after RA.
958 ;; Case 1:
959 ;; vlmax_avl a5
960 ;; ... (across many blocks)
961 ;; vadd (implicit use a5) ====> emit: vsetvl a5,zero
962 ;; Case 2:
963 ;; vlmax_avl a5
964 ;; ... (across many blocks)
965 ;; mv a6,a5
966 ;; ... (across many blocks)
967 ;; vadd (implicit use a6) ====> emit: vsetvl a6,zero
968 ;; Case 3:
969 ;; vlmax_avl a5
970 ;; ... (across many blocks)
971 ;; store mem,a5 (spill)
972 ;; ... (across many blocks)
973 ;; load a7,mem (spill)
974 ;; ... (across many blocks)
975 ;; vadd (implicit use a7) ====> emit: vsetvl a7,zero
976 ;; Such cases are all safe for VSETVL PASS to emit a vsetvl
977 ;; instruction that modifies the AVL operand.
978 (define_insn "@vlmax_avl<mode>"
979 [(set (match_operand:P 0 "register_operand" "=r")
980 (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
981 "TARGET_VECTOR"
982 ""
983 [(set_attr "type" "vsetvl_pre")]
984 )
985
986 ;; Set VXRM
987 (define_insn "vxrmsi"
988 [(set (reg:SI VXRM_REGNUM)
989 (match_operand:SI 0 "const_int_operand" "i"))]
990 "TARGET_VECTOR"
991 "csrwi\tvxrm,%0"
992 [(set_attr "type" "wrvxrm")
993 (set_attr "mode" "SI")])
994
995 ;; Set FRM
996 (define_insn "fsrmsi_backup"
997 [(set (match_operand:SI 0 "register_operand" "=r,r")
998 (reg:SI FRM_REGNUM))
999 (set (reg:SI FRM_REGNUM)
1000 (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
1001 "TARGET_VECTOR"
1002 "@
1003 fsrm\t%0,%1
1004 fsrmi\t%0,%1"
1005 [(set_attr "type" "wrfrm,wrfrm")
1006 (set_attr "mode" "SI")]
1007 )
1008
1009 (define_insn "fsrmsi_restore"
1010 [(set (reg:SI FRM_REGNUM)
1011 (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
1012 "TARGET_VECTOR"
1013 "@
1014 fsrm\t%0
1015 fsrmi\t%0"
1016 [(set_attr "type" "wrfrm,wrfrm")
1017 (set_attr "mode" "SI")]
1018 )
1019
1020 ;; The volatile fsrmsi restore is used for the exit point for the
1021 ;; dynamic mode switching. It will generate one volatile fsrm a5
1022 ;; which won't be eliminated.
1023 (define_insn "fsrmsi_restore_volatile"
1024 [(set (reg:SI FRM_REGNUM)
1025 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1026 UNSPECV_FRM_RESTORE_EXIT))]
1027 "TARGET_VECTOR"
1028 "fsrm\t%0"
1029 [(set_attr "type" "wrfrm")
1030 (set_attr "mode" "SI")]
1031 )
1032
1033 ;; Read FRM
1034 (define_insn "frrmsi"
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (reg:SI FRM_REGNUM))]
1037 "TARGET_VECTOR"
1038 "frrm\t%0"
1039 [(set_attr "type" "rdfrm")
1040 (set_attr "mode" "SI")]
1041 )
1042
1043 ;; -----------------------------------------------------------------
1044 ;; ---- Moves Operations
1045 ;; -----------------------------------------------------------------
1046
1047 (define_expand "mov<mode>"
1048 [(set (match_operand:V 0 "reg_or_mem_operand")
1049 (match_operand:V 1 "general_operand"))]
1050 "TARGET_VECTOR"
1051 {
1052 /* For whole register move, we transform the pattern into the format
1053 that excludes the clobber of scratch register.
1054
1055 We include clobber of a scalar scratch register which is going to be
1056 used for emit of vsetvl instruction after reload_completed since we
1057 need vsetvl instruction to set VL/VTYPE global status for fractional
1058 vector load/store.
1059
1060 For example:
1061 [(set (match_operand:RVVMF8QI v24)
1062 (match_operand:RVVMF8QI (mem: a4)))
1063 (clobber (scratch:SI a5))]
1064 ====>> vsetvl a5,zero,e8,mf8
1065 ====>> vle8.v v24,(a4)
1066
1067 Philosophy:
1068
1069 - Clobber a scalar scratch register for each mov<mode>.
1070
1071 - Classify the machine_mode mode = <MODE>mode into 2 class:
1072 Whole register move and fractional register move.
1073
1074 - Transform and remove scratch clobber register for whole
1075 register move so that we can avoid occupying the scalar
1076 registers.
1077
1078 - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
1079 before spilling. The clobber scratch is used by spilling fractional
1080 registers in IRA/LRA so it's too early. */
1081
1082 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1083 DONE;
1084 })
1085
1086 ;; This pattern is used for code-gen for whole register load/stores.
1087 ;; Also applicable for all register moves.
1088 ;; Fractional vector modes load/store are not allowed to match this pattern.
1089 ;; Mask modes load/store are not allowed to match this pattern.
1090 ;; We seperate "*mov<mode>" into "*mov<mode>_whole" and "*mov<mode>_fract" because
1091 ;; we don't want to include fractional load/store in "*mov<mode>" which will
1092 ;; create unexpected patterns in LRA.
1093 ;; For example:
1094 ;; ira rtl:
1095 ;; (insn 20 19 9 2 (set (reg/v:RVVMF4QI 97 v1 [ v1 ])
1096 ;; (reg:RVVMF4QI 134 [ _1 ])) "rvv.c":9:22 571 {*movvnx2qi_fract}
1097 ;; (nil))
1098 ;; When the value of pseudo register 134 of the insn above is discovered already
1099 ;; spilled in the memory during LRA.
1100 ;; LRA will reload this pattern into a memory load instruction pattern.
1101 ;; Because RVVMF4QI is a fractional vector, we want LRA reload this pattern into
1102 ;; (insn 20 19 9 2 (parallel [
1103 ;; (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1104 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8]))
1105 ;; (clobber (reg:SI 14 a4 [149]))])
1106 ;; So that we could be able to emit vsetvl instruction using clobber sratch a4.
1107 ;; To let LRA generate the expected pattern, we should exclude fractional vector
1108 ;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern into:
1109 ;; (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1110 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8])))
1111 ;; which is not the pattern we want.
1112 ;; According the facts above, we make "*mov<mode>_whole" includes load/store/move for whole
1113 ;; vector modes according to '-march' and "*mov<mode>_fract" only include fractional vector modes.
1114 (define_insn "*mov<mode>_whole"
1115 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr")
1116 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " m,vr,vr"))]
1117 "TARGET_VECTOR"
1118 "@
1119 vl%m1re<sew>.v\t%0,%1
1120 vs%m1r.v\t%1,%0
1121 vmv%m1r.v\t%0,%1"
1122 [(set_attr "type" "vldr,vstr,vmov")
1123 (set_attr "mode" "<MODE>")])
1124
1125 (define_insn "*mov<mode>_fract"
1126 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1127 (match_operand:V_FRACT 1 "register_operand" " vr"))]
1128 "TARGET_VECTOR"
1129 "vmv1r.v\t%0,%1"
1130 [(set_attr "type" "vmov")
1131 (set_attr "mode" "<MODE>")])
1132
1133 (define_expand "mov<mode>"
1134 [(set (match_operand:VB 0 "reg_or_mem_operand")
1135 (match_operand:VB 1 "general_operand"))]
1136 "TARGET_VECTOR"
1137 {
1138 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1139 DONE;
1140 })
1141
1142 (define_insn "*mov<mode>"
1143 [(set (match_operand:VB 0 "register_operand" "=vr")
1144 (match_operand:VB 1 "register_operand" " vr"))]
1145 "TARGET_VECTOR"
1146 "vmv1r.v\t%0,%1"
1147 [(set_attr "type" "vmov")
1148 (set_attr "mode" "<MODE>")])
1149
1150 (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
1151 [(parallel
1152 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
1153 (match_operand:V_FRACT 1 "reg_or_mem_operand"))
1154 (clobber (match_scratch:P 2))])]
1155 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1156 {})
1157
1158 (define_expand "@mov<VB:mode><P:mode>_lra"
1159 [(parallel
1160 [(set (match_operand:VB 0 "reg_or_mem_operand")
1161 (match_operand:VB 1 "reg_or_mem_operand"))
1162 (clobber (match_scratch:P 2))])]
1163 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1164 {})
1165
1166 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
1167 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
1168 (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
1169 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1170 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1171 "#"
1172 "&& reload_completed"
1173 [(const_int 0)]
1174 {
1175 if (REG_P (operands[0]) && REG_P (operands[1]))
1176 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1177 else
1178 {
1179 riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
1180 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<V_FRACT:MODE>mode),
1181 riscv_vector::UNARY_OP, operands, operands[2]);
1182 }
1183 DONE;
1184 }
1185 [(set_attr "type" "vector")]
1186 )
1187
1188 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
1189 [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
1190 (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
1191 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1192 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1193 "#"
1194 "&& reload_completed"
1195 [(const_int 0)]
1196 {
1197 if (REG_P (operands[0]) && REG_P (operands[1]))
1198 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1199 else
1200 {
1201 riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
1202 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<VB:MODE>mode),
1203 riscv_vector::UNARY_MASK_OP, operands, operands[2]);
1204 }
1205 DONE;
1206 }
1207 [(set_attr "type" "vector")]
1208 )
1209
1210 ;; Define tuple modes data movement.
1211 ;; operands[2] is used to save the offset of each subpart.
1212 ;; operands[3] is used to calculate the address for each subpart.
1213 ;; operands[4] is VL of vsevli instruction.
1214 (define_expand "mov<mode>"
1215 [(parallel [(set (match_operand:VT 0 "reg_or_mem_operand")
1216 (match_operand:VT 1 "general_operand"))
1217 (clobber (match_dup 2))
1218 (clobber (match_dup 3))
1219 (clobber (match_dup 4))])]
1220 "TARGET_VECTOR"
1221 {
1222 /* Need to force register if mem <- !reg. */
1223 if (MEM_P (operands[0]) && !REG_P (operands[1]))
1224 operands[1] = force_reg (<MODE>mode, operands[1]);
1225
1226 if (GET_CODE (operands[1]) == CONST_VECTOR)
1227 {
1228 riscv_vector::expand_tuple_move (operands);
1229 DONE;
1230 }
1231
1232 operands[2] = gen_rtx_SCRATCH (Pmode);
1233 operands[3] = gen_rtx_SCRATCH (Pmode);
1234 operands[4] = gen_rtx_SCRATCH (Pmode);
1235 })
1236
1237 (define_insn_and_split "*mov<VT:mode>_<P:mode>"
1238 [(set (match_operand:VT 0 "reg_or_mem_operand" "=vr,vr, m")
1239 (match_operand:VT 1 "reg_or_mem_operand" " vr, m,vr"))
1240 (clobber (match_scratch:P 2 "=X,&r,&r"))
1241 (clobber (match_scratch:P 3 "=X,&r,&r"))
1242 (clobber (match_scratch:P 4 "=X,&r,&r"))]
1243 "TARGET_VECTOR"
1244 "#"
1245 "&& reload_completed"
1246 [(const_int 0)]
1247 {
1248 riscv_vector::expand_tuple_move (operands);
1249 DONE;
1250 }
1251 [(set_attr "type" "vmov,vlde,vste")
1252 (set_attr "mode" "<VT:MODE>")
1253 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1254 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))])
1255
1256 ;; -----------------------------------------------------------------
1257 ;; ---- VLS Moves Operations
1258 ;; -----------------------------------------------------------------
1259
1260 (define_expand "mov<mode>"
1261 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1262 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1263 "TARGET_VECTOR"
1264 {
1265 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1266 DONE;
1267 })
1268
1269 (define_insn_and_split "*mov<mode>"
1270 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
1271 (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
1272 "TARGET_VECTOR
1273 && (register_operand (operands[0], <MODE>mode)
1274 || register_operand (operands[1], <MODE>mode))"
1275 "@
1276 #
1277 #
1278 vmv%m1r.v\t%0,%1"
1279 "&& reload_completed
1280 && (!register_operand (operands[0], <MODE>mode)
1281 || !register_operand (operands[1], <MODE>mode))"
1282 [(const_int 0)]
1283 {
1284 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1285 gcc_assert (ok_p);
1286 DONE;
1287 }
1288 [(set_attr "type" "vmov")]
1289 )
1290
1291 (define_expand "mov<mode>"
1292 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1293 (match_operand:VLS_AVL_REG 1 "general_operand"))]
1294 "TARGET_VECTOR"
1295 {
1296 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1297 gcc_assert (ok_p);
1298 DONE;
1299 })
1300
1301 (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
1302 [(parallel
1303 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1304 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
1305 (clobber (match_scratch:P 2))])]
1306 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1307 {})
1308
1309 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
1310 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
1311 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
1312 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1313 "TARGET_VECTOR && (lra_in_progress || reload_completed)
1314 && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
1315 || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
1316 "#"
1317 "&& reload_completed"
1318 [(const_int 0)]
1319 {
1320 if (REG_P (operands[0]) && REG_P (operands[1]))
1321 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1322 else
1323 {
1324 emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
1325 Pmode));
1326 unsigned insn_flags
1327 = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
1328 ? riscv_vector::UNARY_MASK_OP
1329 : riscv_vector::UNARY_OP;
1330 riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
1331 insn_flags, operands, operands[2]);
1332 }
1333 DONE;
1334 }
1335 [(set_attr "type" "vmov")]
1336 )
1337
1338 (define_insn "*mov<mode>_vls"
1339 [(set (match_operand:VLS 0 "register_operand" "=vr")
1340 (match_operand:VLS 1 "register_operand" " vr"))]
1341 "TARGET_VECTOR"
1342 "vmv%m1r.v\t%0,%1"
1343 [(set_attr "type" "vmov")
1344 (set_attr "mode" "<MODE>")])
1345
1346 (define_insn "*mov<mode>_vls"
1347 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1348 (match_operand:VLSB 1 "register_operand" " vr"))]
1349 "TARGET_VECTOR"
1350 "vmv1r.v\t%0,%1"
1351 [(set_attr "type" "vmov")
1352 (set_attr "mode" "<MODE>")])
1353
1354 ;; According to RVV ISA:
1355 ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,
1356 ;; either the element is transferred successfully or an address misaligned exception is raised on that element.
1357 (define_expand "movmisalign<mode>"
1358 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1359 (match_operand:V_VLS 1 "general_operand"))]
1360 "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
1361 {
1362 emit_move_insn (operands[0], operands[1]);
1363 DONE;
1364 }
1365 )
1366
1367 ;; -----------------------------------------------------------------
1368 ;; ---- Duplicate Operations
1369 ;; -----------------------------------------------------------------
1370
1371 (define_expand "vec_duplicate<mode>"
1372 [(set (match_operand:V_VLS 0 "register_operand")
1373 (vec_duplicate:V_VLS
1374 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1375 "TARGET_VECTOR"
1376 {
1377 /* Early expand DImode broadcast in RV32 system to avoid RA reload
1378 generate (set (reg) (vec_duplicate:DI)). */
1379 if (maybe_gt (GET_MODE_SIZE (<VEL>mode), GET_MODE_SIZE (Pmode)))
1380 {
1381 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1382 riscv_vector::UNARY_OP, operands);
1383 DONE;
1384 }
1385 /* Otherwise, allow it fall into general vec_duplicate pattern
1386 which allow us to have vv->vx combine optimization in later pass. */
1387 })
1388
1389 ;; According to GCC internal:
1390 ;; This pattern only handles duplicates of non-constant inputs.
1391 ;; Constant vectors go through the movm pattern instead.
1392 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
1393 (define_insn_and_split "*vec_duplicate<mode>"
1394 [(set (match_operand:V_VLS 0 "register_operand")
1395 (vec_duplicate:V_VLS
1396 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1397 "TARGET_VECTOR && can_create_pseudo_p ()"
1398 "#"
1399 "&& 1"
1400 [(const_int 0)]
1401 {
1402 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1403 riscv_vector::UNARY_OP, operands);
1404 DONE;
1405 }
1406 [(set_attr "type" "vector")]
1407 )
1408
1409 ;; -----------------------------------------------------------------
1410 ;; ---- 6. Configuration-Setting Instructions
1411 ;; -----------------------------------------------------------------
1412 ;; Includes:
1413 ;; - 6.1 vsetvli/vsetivl/vsetvl instructions
1414 ;; -----------------------------------------------------------------
1415
1416 ;; we dont't define vsetvli as unspec_volatile which has side effects.
1417 ;; This instruction can be scheduled by the instruction scheduler.
1418 ;; This means these instructions will be deleted when
1419 ;; there is no instructions using vl or vtype in the following.
1420 ;; rd | rs1 | AVL value | Effect on vl
1421 ;; - | !x0 | x[rs1] | Normal stripmining
1422 ;; !x0 | x0 | ~0 | Set vl to VLMAX
1423 ;; operands[0]: VL.
1424 ;; operands[1]: AVL.
1425 ;; operands[2]: SEW
1426 ;; operands[3]: LMUL
1427 ;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
1428 ;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
1429
1430 ;; We define 2 types of "vsetvl*" instruction patterns:
1431
1432 ;; - "@vsetvl<mode>" is a parallel format which has side effects.
1433
1434 ;; - "@vsetvl<mode>_no_side_effects" has no side effects.
1435
1436 ;; - "@vsetvl<mode>" is used by "vsetvl" intrinsics and "insert-vsetvl" PASS.
1437
1438 ;; - "@vsetvl<mode>_no_side_effects" is used by GCC standard patterns.
1439
1440 ;; - "@vsetvl<mode>" includes VL/VTYPE global registers status (define set)
1441 ;; and each RVV instruction includes VL/VTYPE global registers status (use)
1442 ;; so that we can guarantee each RVV instruction can execute with correct
1443 ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
1444
1445 ;; - "@vsetvl<mode>_no_side_effects" has no side effects and excludes VL/VTYPE
1446 ;; global registers status (define set). It's only used by GCC standard pattern
1447 ;; expansion. For example: "mov<mode>" pattern for fractional vector modes which
1448 ;; need to set VL/VTYPE. Then we could manually call this pattern to gain benefits
1449 ;; from the optimization of each GCC internal PASS.
1450
1451 ;; 1. void foo (float *in, float *out)
1452 ;; {
1453 ;; vfloat32mf2_t v = *(vfloat32mf2_t*)in;
1454 ;; *(vfloat32mf2_t*)out = v;
1455 ;; }
1456 ;; We could eliminate the second "vsetvl" by calling "@vsetvl<mode>_no_side_effects".
1457 ;;
1458 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1459 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; vsetvli a4,zero,e32,mf2,ta,ma
1460 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1461 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; --
1462 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1463 ;; ret ;; ret
1464
1465 ;; 2. void foo (int8_t *in, int8_t *out, int M)
1466 ;; {
1467 ;; for (int i = 0; i < M; i++){
1468 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1469 ;; *(vint8mf2_t*)(out + i) = v;
1470 ;; }
1471 ;; }
1472 ;;
1473 ;; Hoist "vsetvl" instruction in LICM:
1474 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1475 ;; - ;; vsetvli a4,zero,e32,mf2,ta,ma
1476 ;; LOOP: ;; LOOP:
1477 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1478 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1479 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1480 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1481
1482 ;; However, it may produce wrong codegen if we exclude VL/VTYPE in "vsevl<mode>".
1483 ;; 3. void foo (int8_t *in, int8_t *out, int32_t *in2, int32_t *out2, int M)
1484 ;; {
1485 ;; for (int i = 0; i < M; i++){
1486 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1487 ;; vint32mf2_t v2 = *(vint32mf2_t*)(in + i + i);
1488 ;; *(vint8mf2_t*)(out + i) = v;
1489 ;; *(vint32mf2_t*)(out + i + i) = v2;
1490 ;; }
1491 ;; }
1492 ;;
1493 ;; vsetvli a6,zero,e8,mf2,ta,ma
1494 ;; vsetvli a2,zero,e32,mf2,ta,ma
1495 ;; LOOP:
1496 ;; vle8.v v25,(a0)
1497 ;; vle32.v v24,(a5)
1498 ;; addi a0,a0,1
1499 ;; vse8.v v25,(a1)
1500 ;; vse32.v v24,(a3)
1501 ;;
1502 ;; Both vle8.v and vle32.v are using the wrong VL/VTYPE status.
1503 ;; We leave it to "insert-vsetvl" PASS to correct this situation.
1504
1505 ;; The "insert-vsetvl" PASS mechanism:
1506 ;; 1. Before "insert-vsetvl" PASS, only RVV instructions are generated
1507 ;; by GCC standard pattern expansion has the corresponding "vsetvl".
1508 ;; We exploit each GCC internal optimization pass to optimize the "vsetvl".
1509 ;; 2. Correct the VL/VTYPE status for each GCC standard pattern RVV instructions.
1510 ;; Insert vsetvl for each RVV instructions that has no VL/VTYPE status if necessary.
1511 ;; For example: RVV intrinsics.
1512 ;; 3. Optimize "vsetvl" instructions.
1513
1514 (define_insn "@vsetvl<mode>"
1515 [(set (match_operand:P 0 "register_operand" "=r")
1516 (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
1517 (match_operand 2 "const_int_operand" "i")
1518 (match_operand 3 "const_int_operand" "i")
1519 (match_operand 4 "const_int_operand" "i")
1520 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
1521 (set (reg:SI VL_REGNUM)
1522 (unspec:SI [(match_dup 1)
1523 (match_dup 2)
1524 (match_dup 3)] UNSPEC_VSETVL))
1525 (set (reg:SI VTYPE_REGNUM)
1526 (unspec:SI [(match_dup 2)
1527 (match_dup 3)
1528 (match_dup 4)
1529 (match_dup 5)] UNSPEC_VSETVL))]
1530 "TARGET_VECTOR"
1531 "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
1532 [(set_attr "type" "vsetvl")
1533 (set_attr "mode" "<MODE>")
1534 (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
1535 (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
1536 (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
1537 (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
1538
1539 ;; vsetvl zero,zero,vtype instruction.
1540 ;; This pattern has no side effects and does not set X0 register.
1541 (define_insn "vsetvl_vtype_change_only"
1542 [(set (reg:SI VTYPE_REGNUM)
1543 (unspec:SI
1544 [(match_operand 0 "const_int_operand" "i")
1545 (match_operand 1 "const_int_operand" "i")
1546 (match_operand 2 "const_int_operand" "i")
1547 (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
1548 "TARGET_VECTOR"
1549 "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
1550 [(set_attr "type" "vsetvl")
1551 (set_attr "mode" "SI")
1552 (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
1553 (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
1554 (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
1555 (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
1556
1557 ;; vsetvl zero,rs1,vtype instruction.
1558 ;; The reason we need this pattern since we should avoid setting X0 register
1559 ;; in vsetvl instruction pattern.
1560 (define_insn "@vsetvl_discard_result<mode>"
1561 [(set (reg:SI VL_REGNUM)
1562 (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
1563 (match_operand 1 "const_int_operand" "i")
1564 (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
1565 (set (reg:SI VTYPE_REGNUM)
1566 (unspec:SI [(match_dup 1)
1567 (match_dup 2)
1568 (match_operand 3 "const_int_operand" "i")
1569 (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
1570 "TARGET_VECTOR"
1571 "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
1572 [(set_attr "type" "vsetvl")
1573 (set_attr "mode" "<MODE>")
1574 (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
1575 (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
1576 (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
1577 (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
1578
1579 ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
1580 ;; Since we have many optmization passes from "expand" to "reload_completed",
1581 ;; such pattern can allow us gain benefits of these optimizations.
1582 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
1583 [(set (match_operand:P 0 "register_operand" "=r")
1584 (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
1585 (match_operand 2 "const_int_operand" "i")
1586 (match_operand 3 "const_int_operand" "i")
1587 (match_operand 4 "const_int_operand" "i")
1588 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
1589 "TARGET_VECTOR"
1590 "#"
1591 "&& epilogue_completed"
1592 [(parallel
1593 [(set (match_dup 0)
1594 (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
1595 (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
1596 (set (reg:SI VL_REGNUM)
1597 (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
1598 (set (reg:SI VTYPE_REGNUM)
1599 (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
1600 (match_dup 5)] UNSPEC_VSETVL))])]
1601 ""
1602 [(set_attr "type" "vsetvl")
1603 (set_attr "mode" "SI")])
1604
1605 ;; This pattern use to combine bellow two insns and then further remove
1606 ;; unnecessary sign_extend operations:
1607 ;; (set (reg:DI 134 [ _1 ])
1608 ;; (unspec:DI [
1609 ;; (const_int 19 [0x13])
1610 ;; (const_int 8 [0x8])
1611 ;; (const_int 5 [0x5])
1612 ;; (const_int 2 [0x2]) repeated x2
1613 ;; ] UNSPEC_VSETVL))
1614 ;; (set (reg/v:DI 135 [ <retval> ])
1615 ;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))
1616 ;;
1617 ;; The reason we can remove signe_extend is because currently the vl value
1618 ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
1619 ;; bits 17 to 63 (including 31) are always 0, so there is no change after
1620 ;; sign_extend. Note that for HI and QI modes we cannot do this.
1621 ;; Of course, if the range of instructions returned by vsetvl later expands
1622 ;; to 32bits, then this combine pattern needs to be removed. But that could be
1623 ;; a long time from now.
1624 (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
1625 [(set (match_operand:DI 0 "register_operand")
1626 (sign_extend:DI
1627 (subreg:SI
1628 (unspec:DI [(match_operand:P 1 "vector_length_operand")
1629 (match_operand 2 "const_int_operand")
1630 (match_operand 3 "const_int_operand")
1631 (match_operand 4 "const_int_operand")
1632 (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))]
1633 "TARGET_VECTOR && TARGET_64BIT"
1634 "#"
1635 "&& 1"
1636 [(set (match_dup 0)
1637 (unspec:DI [(match_dup 1)
1638 (match_dup 2)
1639 (match_dup 3)
1640 (match_dup 4)
1641 (match_dup 5)] UNSPEC_VSETVL))]
1642 ""
1643 [(set_attr "type" "vsetvl")
1644 (set_attr "mode" "SI")])
1645
1646 ;; RVV machine description matching format
1647 ;; (define_insn ""
1648 ;; [(set (match_operand:MODE 0)
1649 ;; (if_then_else:MODE
1650 ;; (unspec:<MODE:VM>
1651 ;; [(match_operand:<VM> 1 "vector_mask_operand")
1652 ;; (match_operand N + 4 "vector_length_operand")
1653 ;; (match_operand N + 5 "const_int_operand")
1654 ;; (match_operand N + 6 "const_int_operand")
1655 ;; (reg:SI VL_REGNUM)
1656 ;; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1657 ;; (instruction operation:MODE
1658 ;; (match_operand 3
1659 ;; (match_operand 4
1660 ;; (match_operand 5
1661 ;; ................
1662 ;; (match_operand N + 3)
1663 ;; (match_operand:MODE 2 "vector_reg_or_const0_operand")))]
1664 ;;
1665 ;; (unspec:[........] UNSPEC_VPREDICATE) is a predicate wrapper.
1666 ;; Include mask predicate && length predicate && vector policy.
1667
1668 ;; -------------------------------------------------------------------------------
1669 ;; ---- Predicated Mov
1670 ;; -------------------------------------------------------------------------------
1671 ;; Includes:
1672 ;; - 7.4. Vector Unit-Stride Instructions
1673 ;; - 11.15 Vector Integer Merge Instructions
1674 ;; - 11.16 Vector Integer Move Instructions
1675 ;; - 13.16 Vector Floating-Point Move Instruction
1676 ;; - 15.1 Vector Mask-Register Logical Instructions
1677 ;; -------------------------------------------------------------------------------
1678
1679 ;; vle.v/vse.v/vmv.v.v.
1680 ;; For vle.v/vmv.v.v, we may need merge and mask operand.
1681 ;; For vse.v, we don't need merge operand, so it should always match "vu".
1682 ;; constraint alternative 0 ~ 1 match vle.v.
1683 ;; constraint alternative 2 match vse.v.
1684 ;; constraint alternative 3 match vmv.v.v.
1685
1686 ;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
1687 (define_expand "@pred_mov<mode>"
1688 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1689 (if_then_else:V_VLS
1690 (unspec:<VM>
1691 [(match_operand:<VM> 1 "vector_mask_operand")
1692 (match_operand 4 "vector_length_operand")
1693 (match_operand 5 "const_int_operand")
1694 (match_operand 6 "const_int_operand")
1695 (match_operand 7 "const_int_operand")
1696 (reg:SI VL_REGNUM)
1697 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1698 (match_operand:V_VLS 3 "vector_move_operand")
1699 (match_operand:V_VLS 2 "vector_merge_operand")))]
1700 "TARGET_VECTOR"
1701 {})
1702
1703 ;; vle.v/vse.v,vmv.v.v
1704 (define_insn_and_split "*pred_mov<mode>"
1705 [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr")
1706 (if_then_else:V_VLS
1707 (unspec:<VM>
1708 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1")
1709 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
1710 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
1711 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
1712 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
1713 (reg:SI VL_REGNUM)
1714 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1715 (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr")
1716 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))]
1717 "(TARGET_VECTOR
1718 && (register_operand (operands[0], <MODE>mode)
1719 || register_operand (operands[3], <MODE>mode)))"
1720 "@
1721 vle<sew>.v\t%0,%3%p1
1722 vle<sew>.v\t%0,%3
1723 vle<sew>.v\t%0,%3,%1.t
1724 vse<sew>.v\t%3,%0%p1
1725 vmv.v.v\t%0,%3
1726 vmv.v.v\t%0,%3"
1727 "&& register_operand (operands[0], <MODE>mode)
1728 && register_operand (operands[3], <MODE>mode)
1729 && satisfies_constraint_vu (operands[2])
1730 && INTVAL (operands[7]) == riscv_vector::VLMAX"
1731 [(set (match_dup 0) (match_dup 3))]
1732 ""
1733 [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
1734 (set_attr "mode" "<MODE>")])
1735
1736 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
1737 ;; memory operand as input which will produce inferior codegen.
1738 (define_insn "@pred_store<mode>"
1739 [(set (match_operand:V 0 "memory_operand" "+m")
1740 (if_then_else:V
1741 (unspec:<VM>
1742 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
1743 (match_operand 3 "vector_length_operand" " rK")
1744 (match_operand 4 "const_int_operand" " i")
1745 (reg:SI VL_REGNUM)
1746 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1747 (match_operand:V 2 "register_operand" " vr")
1748 (match_dup 0)))]
1749 "TARGET_VECTOR"
1750 "vse<sew>.v\t%2,%0%p1"
1751 [(set_attr "type" "vste")
1752 (set_attr "mode" "<MODE>")
1753 (set (attr "avl_type_idx") (const_int 4))
1754 (set_attr "vl_op_idx" "3")])
1755
1756 ;; vlm.v/vsm.v/vmclr.m/vmset.m.
1757 ;; constraint alternative 0 match vlm.v.
1758 ;; constraint alternative 1 match vsm.v.
1759 ;; constraint alternative 3 match vmclr.m.
1760 ;; constraint alternative 4 match vmset.m.
1761 (define_insn_and_split "@pred_mov<mode>"
1762 [(set (match_operand:VB_VLS 0 "nonimmediate_operand" "=vr, m, vr, vr, vr")
1763 (if_then_else:VB_VLS
1764 (unspec:VB_VLS
1765 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
1766 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
1767 (match_operand 5 "const_int_operand" " i, i, i, i, i")
1768 (reg:SI VL_REGNUM)
1769 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1770 (match_operand:VB_VLS 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
1771 (match_operand:VB_VLS 2 "vector_undef_operand" " vu, vu, vu, vu, vu")))]
1772 "TARGET_VECTOR"
1773 "@
1774 vlm.v\t%0,%3
1775 vsm.v\t%3,%0
1776 vmmv.m\t%0,%3
1777 vmclr.m\t%0
1778 vmset.m\t%0"
1779 "&& register_operand (operands[0], <MODE>mode)
1780 && register_operand (operands[3], <MODE>mode)
1781 && INTVAL (operands[5]) == riscv_vector::VLMAX"
1782 [(set (match_dup 0) (match_dup 3))]
1783 ""
1784 [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
1785 (set_attr "mode" "<MODE>")])
1786
1787 ;; Dedicated pattern for vsm.v instruction since we can't reuse pred_mov pattern to include
1788 ;; memory operand as input which will produce inferior codegen.
1789 (define_insn "@pred_store<mode>"
1790 [(set (match_operand:VB 0 "memory_operand" "+m")
1791 (if_then_else:VB
1792 (unspec:VB
1793 [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
1794 (match_operand 3 "vector_length_operand" " rK")
1795 (match_operand 4 "const_int_operand" " i")
1796 (reg:SI VL_REGNUM)
1797 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1798 (match_operand:VB 2 "register_operand" " vr")
1799 (match_dup 0)))]
1800 "TARGET_VECTOR"
1801 "vsm.v\t%2,%0"
1802 [(set_attr "type" "vstm")
1803 (set_attr "mode" "<MODE>")
1804 (set (attr "avl_type_idx") (const_int 4))
1805 (set_attr "vl_op_idx" "3")])
1806
1807 (define_insn "@pred_merge<mode>"
1808 [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
1809 (if_then_else:V_VLS
1810 (unspec:<VM>
1811 [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
1812 (match_operand 6 "const_int_operand" " i, i, i, i")
1813 (match_operand 7 "const_int_operand" " i, i, i, i")
1814 (reg:SI VL_REGNUM)
1815 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1816 (vec_merge:V_VLS
1817 (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi")
1818 (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr")
1819 (match_operand:<VM> 4 "register_operand" " vm,vm,vm,vm"))
1820 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))]
1821 "TARGET_VECTOR"
1822 "vmerge.v%o3m\t%0,%2,%v3,%4"
1823 [(set_attr "type" "vimerge")
1824 (set_attr "mode" "<MODE>")])
1825
1826 (define_insn "@pred_merge<mode>_scalar"
1827 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
1828 (if_then_else:V_VLSI_QHS
1829 (unspec:<VM>
1830 [(match_operand 5 "vector_length_operand" " rK,rK")
1831 (match_operand 6 "const_int_operand" " i, i")
1832 (match_operand 7 "const_int_operand" " i, i")
1833 (reg:SI VL_REGNUM)
1834 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1835 (vec_merge:V_VLSI_QHS
1836 (vec_duplicate:V_VLSI_QHS
1837 (match_operand:<VEL> 3 "register_operand" " r, r"))
1838 (match_operand:V_VLSI_QHS 2 "register_operand" " vr,vr")
1839 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1840 (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
1841 "TARGET_VECTOR"
1842 "vmerge.vxm\t%0,%2,%3,%4"
1843 [(set_attr "type" "vimerge")
1844 (set_attr "mode" "<MODE>")])
1845
1846 (define_expand "@pred_merge<mode>_scalar"
1847 [(set (match_operand:V_VLSI_D 0 "register_operand")
1848 (if_then_else:V_VLSI_D
1849 (unspec:<VM>
1850 [(match_operand 5 "vector_length_operand")
1851 (match_operand 6 "const_int_operand")
1852 (match_operand 7 "const_int_operand")
1853 (reg:SI VL_REGNUM)
1854 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1855 (vec_merge:V_VLSI_D
1856 (vec_duplicate:V_VLSI_D
1857 (match_operand:<VEL> 3 "reg_or_int_operand"))
1858 (match_operand:V_VLSI_D 2 "register_operand")
1859 (match_operand:<VM> 4 "register_operand"))
1860 (match_operand:V_VLSI_D 1 "vector_merge_operand")))]
1861 "TARGET_VECTOR"
1862 {
1863 if (riscv_vector::sew64_scalar_helper (
1864 operands,
1865 /* scalar op */&operands[3],
1866 /* vl */operands[5],
1867 <MODE>mode,
1868 riscv_vector::simm5_p (operands[3]),
1869 [] (rtx *operands, rtx boardcast_scalar) {
1870 emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
1871 operands[2], boardcast_scalar, operands[4], operands[5],
1872 operands[6], operands[7]));
1873 },
1874 (riscv_vector::avl_type) INTVAL (operands[7])))
1875 DONE;
1876 })
1877
1878 (define_insn "*pred_merge<mode>_scalar"
1879 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1880 (if_then_else:V_VLSI_D
1881 (unspec:<VM>
1882 [(match_operand 5 "vector_length_operand" " rK,rK")
1883 (match_operand 6 "const_int_operand" " i, i")
1884 (match_operand 7 "const_int_operand" " i, i")
1885 (reg:SI VL_REGNUM)
1886 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1887 (vec_merge:V_VLSI_D
1888 (vec_duplicate:V_VLSI_D
1889 (match_operand:<VEL> 3 "register_operand" " r, r"))
1890 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1891 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1892 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1893 "TARGET_VECTOR"
1894 "vmerge.vxm\t%0,%2,%3,%4"
1895 [(set_attr "type" "vimerge")
1896 (set_attr "mode" "<MODE>")])
1897
1898 (define_insn "*pred_merge<mode>_extended_scalar"
1899 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1900 (if_then_else:V_VLSI_D
1901 (unspec:<VM>
1902 [(match_operand 5 "vector_length_operand" " rK,rK")
1903 (match_operand 6 "const_int_operand" " i, i")
1904 (match_operand 7 "const_int_operand" " i, i")
1905 (reg:SI VL_REGNUM)
1906 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1907 (vec_merge:V_VLSI_D
1908 (vec_duplicate:V_VLSI_D
1909 (sign_extend:<VEL>
1910 (match_operand:<VSUBEL> 3 "register_operand" " r, r")))
1911 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1912 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1913 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1914 "TARGET_VECTOR && !TARGET_64BIT"
1915 "vmerge.vxm\t%0,%2,%3,%4"
1916 [(set_attr "type" "vimerge")
1917 (set_attr "mode" "<MODE>")])
1918
1919 ;; -------------------------------------------------------------------------------
1920 ;; ---- Predicated Broadcast
1921 ;; -------------------------------------------------------------------------------
1922 ;; Includes:
1923 ;; - 7.5. Vector Strided Instructions (zero stride)
1924 ;; - 11.16 Vector Integer Move Instructions (vmv.v.x)
1925 ;; - 13.16 Vector Floating-Point Move Instruction (vfmv.v.f)
1926 ;; - 16.1 Integer Scalar Move Instructions (vmv.s.x)
1927 ;; - 16.2 Floating-Point Scalar Move Instructions (vfmv.s.f)
1928 ;; -------------------------------------------------------------------------------
1929
1930 ;; According to RVV ISA, vector-scalar instruction doesn't support
1931 ;; operand fetched from 2 consecutive registers, so we should use
1932 ;; vlse.v which is a memory access to broadcast a DImode scalar into a vector.
1933 ;;
1934 ;; Since the optimization flow in GCC is as follows:
1935 ;; expand --> LICM (Loop invariant) --> split.
1936 ;; To use LICM optimization, we postpone generation of vlse.v to split stage since
1937 ;; a memory access instruction can not be optimized by LICM (Loop invariant).
1938 (define_expand "@pred_broadcast<mode>"
1939 [(set (match_operand:V_VLS 0 "register_operand")
1940 (if_then_else:V_VLS
1941 (unspec:<VM>
1942 [(match_operand:<VM> 1 "vector_broadcast_mask_operand")
1943 (match_operand 4 "vector_length_operand")
1944 (match_operand 5 "const_int_operand")
1945 (match_operand 6 "const_int_operand")
1946 (match_operand 7 "const_int_operand")
1947 (reg:SI VL_REGNUM)
1948 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1949 (vec_duplicate:V_VLS
1950 (match_operand:<VEL> 3 "direct_broadcast_operand"))
1951 (match_operand:V_VLS 2 "vector_merge_operand")))]
1952 "TARGET_VECTOR"
1953 {
1954 /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar. */
1955 if (satisfies_constraint_Wdm (operands[3]))
1956 {
1957 if (satisfies_constraint_Wb1 (operands[1]))
1958 {
1959 /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA) */
1960 if (satisfies_constraint_vu (operands[2]))
1961 operands[1] = CONSTM1_RTX (<VM>mode);
1962 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
1963 {
1964 /* Case 2: vmv.s.x (TU, x == memory) ==>
1965 vl = 0 or 1; + vlse.v (TU) in RV32 system */
1966 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
1967 operands[1] = CONSTM1_RTX (<VM>mode);
1968 }
1969 else
1970 /* Case 3: load x (memory) to register. */
1971 operands[3] = force_reg (<VEL>mode, operands[3]);
1972 }
1973 }
1974 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
1975 && (immediate_operand (operands[3], Pmode)
1976 || (CONST_POLY_INT_P (operands[3])
1977 && known_ge (rtx_to_poly_int64 (operands[3]), 0U)
1978 && known_le (rtx_to_poly_int64 (operands[3]), GET_MODE_SIZE (<MODE>mode)))))
1979 {
1980 rtx tmp = gen_reg_rtx (Pmode);
1981 poly_int64 value = rtx_to_poly_int64 (operands[3]);
1982 emit_move_insn (tmp, gen_int_mode (value, Pmode));
1983 operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode, tmp);
1984 }
1985 else
1986 operands[3] = force_reg (<VEL>mode, operands[3]);
1987 })
1988
1989 (define_insn_and_split "*pred_broadcast<mode>"
1990 [(set (match_operand:V_VLSI 0 "register_operand" "=vr, vr, vd, vd, vr, vr, vr, vr")
1991 (if_then_else:V_VLSI
1992 (unspec:<VM>
1993 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
1994 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
1995 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
1996 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
1997 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
1998 (reg:SI VL_REGNUM)
1999 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2000 (vec_duplicate:V_VLSI
2001 (match_operand:<VEL> 3 "direct_broadcast_operand" " r, r,Wdm,Wdm,Wdm,Wdm, r, r"))
2002 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2003 "TARGET_VECTOR"
2004 "@
2005 vmv.v.x\t%0,%3
2006 vmv.v.x\t%0,%3
2007 vlse<sew>.v\t%0,%3,zero,%1.t
2008 vlse<sew>.v\t%0,%3,zero,%1.t
2009 vlse<sew>.v\t%0,%3,zero
2010 vlse<sew>.v\t%0,%3,zero
2011 vmv.s.x\t%0,%3
2012 vmv.s.x\t%0,%3"
2013 "(register_operand (operands[3], <VEL>mode)
2014 || CONST_POLY_INT_P (operands[3]))
2015 && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
2016 [(set (match_dup 0)
2017 (if_then_else:V_VLSI (unspec:<VM> [(match_dup 1) (match_dup 4)
2018 (match_dup 5) (match_dup 6) (match_dup 7)
2019 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2020 (vec_duplicate:V_VLSI (match_dup 3))
2021 (match_dup 2)))]
2022 {
2023 gcc_assert (can_create_pseudo_p ());
2024 if (CONST_POLY_INT_P (operands[3]))
2025 {
2026 rtx tmp = gen_reg_rtx (<VEL>mode);
2027 emit_move_insn (tmp, operands[3]);
2028 operands[3] = tmp;
2029 }
2030 rtx m = assign_stack_local (<VEL>mode, GET_MODE_SIZE (<VEL>mode),
2031 GET_MODE_ALIGNMENT (<VEL>mode));
2032 m = validize_mem (m);
2033 emit_move_insn (m, operands[3]);
2034 m = gen_rtx_MEM (<VEL>mode, force_reg (Pmode, XEXP (m, 0)));
2035 operands[3] = m;
2036
2037 /* For SEW = 64 in RV32 system, we expand vmv.s.x:
2038 andi a2,a2,1
2039 vsetvl zero,a2,e64
2040 vlse64.v */
2041 if (satisfies_constraint_Wb1 (operands[1]))
2042 {
2043 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2044 operands[1] = CONSTM1_RTX (<VM>mode);
2045 }
2046 }
2047 [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
2048 (set_attr "mode" "<MODE>")])
2049
2050 (define_insn "*pred_broadcast<mode>"
2051 [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr")
2052 (if_then_else:V_VLSF_ZVFHMIN
2053 (unspec:<VM>
2054 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2055 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2056 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2057 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2058 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2059 (reg:SI VL_REGNUM)
2060 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2061 (vec_duplicate:V_VLSF_ZVFHMIN
2062 (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
2063 (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2064 "TARGET_VECTOR"
2065 "@
2066 vfmv.v.f\t%0,%3
2067 vfmv.v.f\t%0,%3
2068 vlse<sew>.v\t%0,%3,zero,%1.t
2069 vlse<sew>.v\t%0,%3,zero,%1.t
2070 vlse<sew>.v\t%0,%3,zero
2071 vlse<sew>.v\t%0,%3,zero
2072 vfmv.s.f\t%0,%3
2073 vfmv.s.f\t%0,%3"
2074 [(set_attr "type" "vfmov,vfmov,vlds,vlds,vlds,vlds,vfmovfv,vfmovfv")
2075 (set_attr "mode" "<MODE>")])
2076
2077 (define_insn "*pred_broadcast<mode>_extended_scalar"
2078 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vr, vr, vr, vr")
2079 (if_then_else:V_VLSI_D
2080 (unspec:<VM>
2081 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
2082 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2083 (match_operand 5 "const_int_operand" " i, i, i, i")
2084 (match_operand 6 "const_int_operand" " i, i, i, i")
2085 (match_operand 7 "const_int_operand" " i, i, i, i")
2086 (reg:SI VL_REGNUM)
2087 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2088 (vec_duplicate:V_VLSI_D
2089 (sign_extend:<VEL>
2090 (match_operand:<VSUBEL> 3 "register_operand" " r, r, r, r")))
2091 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2092 "TARGET_VECTOR && !TARGET_64BIT"
2093 "@
2094 vmv.v.x\t%0,%3
2095 vmv.v.x\t%0,%3
2096 vmv.s.x\t%0,%3
2097 vmv.s.x\t%0,%3"
2098 [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
2099 (set_attr "mode" "<MODE>")])
2100
2101 (define_insn "*pred_broadcast<mode>_zero"
2102 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2103 (if_then_else:V_VLS
2104 (unspec:<VM>
2105 [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1, Wb1")
2106 (match_operand 4 "vector_length_operand" " rK, rK")
2107 (match_operand 5 "const_int_operand" " i, i")
2108 (match_operand 6 "const_int_operand" " i, i")
2109 (match_operand 7 "const_int_operand" " i, i")
2110 (reg:SI VL_REGNUM)
2111 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2112 (match_operand:V_VLS 3 "vector_const_0_operand" "Wc0, Wc0")
2113 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2114 "TARGET_VECTOR"
2115 "vmv.s.x\t%0,zero"
2116 [(set_attr "type" "vimovxv,vimovxv")
2117 (set_attr "mode" "<MODE>")])
2118
2119 ;; Because (vec_duplicate imm) will be converted to (const_vector imm),
2120 ;; This pattern is used to handle this case.
2121 (define_insn "*pred_broadcast<mode>_imm"
2122 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2123 (if_then_else:V_VLS
2124 (unspec:<VM>
2125 [(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1, Wc1")
2126 (match_operand 4 "vector_length_operand" " rK, rK")
2127 (match_operand 5 "const_int_operand" " i, i")
2128 (match_operand 6 "const_int_operand" " i, i")
2129 (match_operand 7 "const_int_operand" " i, i")
2130 (reg:SI VL_REGNUM)
2131 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2132 (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
2133 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2134 "TARGET_VECTOR"
2135 "vmv.v.i\t%0,%v3"
2136 [(set_attr "type" "vimov,vimov")
2137 (set_attr "mode" "<MODE>")])
2138
2139 ;; -------------------------------------------------------------------------------
2140 ;; ---- Predicated Strided loads/stores
2141 ;; -------------------------------------------------------------------------------
2142 ;; Includes:
2143 ;; - 7.5. Vector Strided Instructions
2144 ;; -------------------------------------------------------------------------------
2145
2146 (define_insn "@pred_strided_load<mode>"
2147 [(set (match_operand:V 0 "register_operand" "=vr, vr, vd, vr, vr, vd")
2148 (if_then_else:V
2149 (unspec:<VM>
2150 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, vm")
2151 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2152 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2153 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2154 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2155 (reg:SI VL_REGNUM)
2156 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2157 (unspec:V
2158 [(match_operand:V 3 "memory_operand" " m, m, m, m, m, m")
2159 (match_operand 4 "<V:stride_predicate>" "<V:stride_load_constraint>")] UNSPEC_STRIDED)
2160 (match_operand:V 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))]
2161 "TARGET_VECTOR"
2162 "@
2163 vlse<sew>.v\t%0,%3,%z4%p1
2164 vlse<sew>.v\t%0,%3,%z4
2165 vlse<sew>.v\t%0,%3,%z4,%1.t
2166 vle<sew>.v\t%0,%3%p1
2167 vle<sew>.v\t%0,%3
2168 vle<sew>.v\t%0,%3,%1.t"
2169 [(set_attr "type" "vlds")
2170 (set_attr "mode" "<MODE>")])
2171
2172 (define_insn "@pred_strided_store<mode>"
2173 [(set (match_operand:V 0 "memory_operand" "+m, m")
2174 (if_then_else:V
2175 (unspec:<VM>
2176 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
2177 (match_operand 4 "vector_length_operand" " rK, rK")
2178 (match_operand 5 "const_int_operand" " i, i")
2179 (reg:SI VL_REGNUM)
2180 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2181 (unspec:V
2182 [(match_operand 2 "<V:stride_predicate>" "<V:stride_store_constraint>")
2183 (match_operand:V 3 "register_operand" " vr, vr")] UNSPEC_STRIDED)
2184 (match_dup 0)))]
2185 "TARGET_VECTOR"
2186 "@
2187 vsse<sew>.v\t%3,%0,%z2%p1
2188 vse<sew>.v\t%3,%0%p1"
2189 [(set_attr "type" "vsts")
2190 (set_attr "mode" "<MODE>")
2191 (set (attr "avl_type_idx") (const_int 5))])
2192
2193 ;; -------------------------------------------------------------------------------
2194 ;; ---- Predicated indexed loads/stores
2195 ;; -------------------------------------------------------------------------------
2196 ;; Includes:
2197 ;; - 7.6. Vector Indexed Instructions
2198 ;; -------------------------------------------------------------------------------
2199
2200 ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
2201 (define_insn "@pred_indexed_<order>load<mode>_same_eew"
2202 [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr")
2203 (if_then_else:VINDEXED
2204 (unspec:<VM>
2205 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
2206 (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
2207 (match_operand 6 "const_int_operand" " i, i, i, i")
2208 (match_operand 7 "const_int_operand" " i, i, i, i")
2209 (match_operand 8 "const_int_operand" " i, i, i, i")
2210 (reg:SI VL_REGNUM)
2211 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2212 (unspec:VINDEXED
2213 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ")
2214 (mem:BLK (scratch))
2215 (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
2216 (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))]
2217 "TARGET_VECTOR"
2218 "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
2219 [(set_attr "type" "vld<order>x")
2220 (set_attr "mode" "<MODE>")])
2221
2222 ;; DEST eew is greater than SOURCE eew.
2223 (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
2224 [(set (match_operand:VEEWEXT2 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
2225 (if_then_else:VEEWEXT2
2226 (unspec:<VM>
2227 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
2228 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2229 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
2230 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
2231 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
2232 (reg:SI VL_REGNUM)
2233 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2234 (unspec:VEEWEXT2
2235 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
2236 (mem:BLK (scratch))
2237 (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] ORDER)
2238 (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
2239 "TARGET_VECTOR"
2240 "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
2241 [(set_attr "type" "vld<order>x")
2242 (set_attr "mode" "<MODE>")
2243 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
2244
2245 (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
2246 [(set (match_operand:VEEWEXT4 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
2247 (if_then_else:VEEWEXT4
2248 (unspec:<VM>
2249 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
2250 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2251 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
2252 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
2253 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
2254 (reg:SI VL_REGNUM)
2255 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2256 (unspec:VEEWEXT4
2257 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
2258 (mem:BLK (scratch))
2259 (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")] ORDER)
2260 (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
2261 "TARGET_VECTOR"
2262 "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
2263 [(set_attr "type" "vld<order>x")
2264 (set_attr "mode" "<MODE>")
2265 (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")])
2266
2267 (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
2268 [(set (match_operand:VEEWEXT8 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr")
2269 (if_then_else:VEEWEXT8
2270 (unspec:<VM>
2271 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1")
2272 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2273 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2274 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2275 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2276 (reg:SI VL_REGNUM)
2277 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2278 (unspec:VEEWEXT8
2279 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2280 (mem:BLK (scratch))
2281 (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" "W87,W87,W87,W87, vr, vr")] ORDER)
2282 (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))]
2283 "TARGET_VECTOR"
2284 "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
2285 [(set_attr "type" "vld<order>x")
2286 (set_attr "mode" "<MODE>")
2287 (set_attr "group_overlap" "W87,W87,W87,W87,none,none")])
2288
2289 ;; DEST eew is smaller than SOURCE eew.
2290 (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
2291 [(set (match_operand:VEEWTRUNC2 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2292 (if_then_else:VEEWTRUNC2
2293 (unspec:<VM>
2294 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2295 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2296 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2297 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2298 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2299 (reg:SI VL_REGNUM)
2300 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2301 (unspec:VEEWTRUNC2
2302 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2303 (mem:BLK (scratch))
2304 (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2305 (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2306 "TARGET_VECTOR"
2307 "vl<order>xei<double_ext_sew>.v\t%0,(%z3),%4%p1"
2308 [(set_attr "type" "vld<order>x")
2309 (set_attr "mode" "<MODE>")])
2310
2311 (define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
2312 [(set (match_operand:VEEWTRUNC4 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2313 (if_then_else:VEEWTRUNC4
2314 (unspec:<VM>
2315 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2316 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2317 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2318 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2319 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2320 (reg:SI VL_REGNUM)
2321 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2322 (unspec:VEEWTRUNC4
2323 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2324 (mem:BLK (scratch))
2325 (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2326 (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2327 "TARGET_VECTOR"
2328 "vl<order>xei<quad_ext_sew>.v\t%0,(%z3),%4%p1"
2329 [(set_attr "type" "vld<order>x")
2330 (set_attr "mode" "<MODE>")])
2331
2332 (define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
2333 [(set (match_operand:VEEWTRUNC8 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2334 (if_then_else:VEEWTRUNC8
2335 (unspec:<VM>
2336 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2337 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2338 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2339 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2340 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2341 (reg:SI VL_REGNUM)
2342 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2343 (unspec:VEEWTRUNC8
2344 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2345 (mem:BLK (scratch))
2346 (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2347 (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2348 "TARGET_VECTOR"
2349 "vl<order>xei<oct_ext_sew>.v\t%0,(%z3),%4%p1"
2350 [(set_attr "type" "vld<order>x")
2351 (set_attr "mode" "<MODE>")])
2352
2353 (define_insn "@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
2354 [(set (mem:BLK (scratch))
2355 (unspec:BLK
2356 [(unspec:<VM>
2357 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2358 (match_operand 4 "vector_length_operand" " rK")
2359 (match_operand 5 "const_int_operand" " i")
2360 (reg:SI VL_REGNUM)
2361 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2362 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2363 (match_operand:RATIO64I 2 "register_operand" " vr")
2364 (match_operand:RATIO64 3 "register_operand" " vr")] ORDER))]
2365 "TARGET_VECTOR"
2366 "vs<order>xei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
2367 [(set_attr "type" "vst<order>x")
2368 (set_attr "mode" "<RATIO64:MODE>")])
2369
2370 (define_insn "@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
2371 [(set (mem:BLK (scratch))
2372 (unspec:BLK
2373 [(unspec:<VM>
2374 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2375 (match_operand 4 "vector_length_operand" " rK")
2376 (match_operand 5 "const_int_operand" " i")
2377 (reg:SI VL_REGNUM)
2378 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2379 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2380 (match_operand:RATIO32I 2 "register_operand" " vr")
2381 (match_operand:RATIO32 3 "register_operand" " vr")] ORDER))]
2382 "TARGET_VECTOR"
2383 "vs<order>xei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
2384 [(set_attr "type" "vst<order>x")
2385 (set_attr "mode" "<RATIO32:MODE>")])
2386
2387 (define_insn "@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
2388 [(set (mem:BLK (scratch))
2389 (unspec:BLK
2390 [(unspec:<VM>
2391 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2392 (match_operand 4 "vector_length_operand" " rK")
2393 (match_operand 5 "const_int_operand" " i")
2394 (reg:SI VL_REGNUM)
2395 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2396 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2397 (match_operand:RATIO16I 2 "register_operand" " vr")
2398 (match_operand:RATIO16 3 "register_operand" " vr")] ORDER))]
2399 "TARGET_VECTOR"
2400 "vs<order>xei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
2401 [(set_attr "type" "vst<order>x")
2402 (set_attr "mode" "<RATIO16:MODE>")])
2403
2404 (define_insn "@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
2405 [(set (mem:BLK (scratch))
2406 (unspec:BLK
2407 [(unspec:<VM>
2408 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2409 (match_operand 4 "vector_length_operand" " rK")
2410 (match_operand 5 "const_int_operand" " i")
2411 (reg:SI VL_REGNUM)
2412 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2413 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2414 (match_operand:RATIO8I 2 "register_operand" " vr")
2415 (match_operand:RATIO8 3 "register_operand" " vr")] ORDER))]
2416 "TARGET_VECTOR"
2417 "vs<order>xei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
2418 [(set_attr "type" "vst<order>x")
2419 (set_attr "mode" "<RATIO8:MODE>")])
2420
2421 (define_insn "@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
2422 [(set (mem:BLK (scratch))
2423 (unspec:BLK
2424 [(unspec:<VM>
2425 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2426 (match_operand 4 "vector_length_operand" " rK")
2427 (match_operand 5 "const_int_operand" " i")
2428 (reg:SI VL_REGNUM)
2429 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2430 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2431 (match_operand:RATIO4I 2 "register_operand" " vr")
2432 (match_operand:RATIO4 3 "register_operand" " vr")] ORDER))]
2433 "TARGET_VECTOR"
2434 "vs<order>xei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
2435 [(set_attr "type" "vst<order>x")
2436 (set_attr "mode" "<RATIO4:MODE>")])
2437
2438 (define_insn "@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
2439 [(set (mem:BLK (scratch))
2440 (unspec:BLK
2441 [(unspec:<VM>
2442 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2443 (match_operand 4 "vector_length_operand" " rK")
2444 (match_operand 5 "const_int_operand" " i")
2445 (reg:SI VL_REGNUM)
2446 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2447 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2448 (match_operand:RATIO2I 2 "register_operand" " vr")
2449 (match_operand:RATIO2 3 "register_operand" " vr")] ORDER))]
2450 "TARGET_VECTOR"
2451 "vs<order>xei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
2452 [(set_attr "type" "vst<order>x")
2453 (set_attr "mode" "<RATIO2:MODE>")])
2454
2455 (define_insn "@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
2456 [(set (mem:BLK (scratch))
2457 (unspec:BLK
2458 [(unspec:<VM>
2459 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2460 (match_operand 4 "vector_length_operand" " rK")
2461 (match_operand 5 "const_int_operand" " i")
2462 (reg:SI VL_REGNUM)
2463 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2464 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2465 (match_operand:RATIO1 2 "register_operand" " vr")
2466 (match_operand:RATIO1 3 "register_operand" " vr")] ORDER))]
2467 "TARGET_VECTOR"
2468 "vs<order>xei<RATIO1:sew>.v\t%3,(%z1),%2%p0"
2469 [(set_attr "type" "vst<order>x")
2470 (set_attr "mode" "<RATIO1:MODE>")])
2471
2472 ;; -------------------------------------------------------------------------------
2473 ;; ---- Predicated integer binary operations
2474 ;; -------------------------------------------------------------------------------
2475 ;; Includes:
2476 ;; - 11.1 Vector Single-Width Integer Add and Subtract
2477 ;; - 11.4 Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
2478 ;; - 11.5 Vector Bitwise Logical Instructions
2479 ;; - 11.6 Vector Single-Width Bit Shift Instructions
2480 ;; - 11.9 Vector Integer Min/Max Instructions
2481 ;; - 11.10 Vector Single-Width Integer Multiply Instructions
2482 ;; - 11.11 Vector Integer Divide Instructions
2483 ;; -------------------------------------------------------------------------------
2484
2485 (define_insn "@pred_<optab><mode>"
2486 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
2487 (if_then_else:V_VLSI
2488 (unspec:<VM>
2489 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
2490 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2491 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2492 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2493 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2494 (reg:SI VL_REGNUM)
2495 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2496 (any_int_binop:V_VLSI
2497 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
2498 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
2499 (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
2500 "TARGET_VECTOR"
2501 "@
2502 v<insn>.vv\t%0,%3,%4%p1
2503 v<insn>.vv\t%0,%3,%4%p1
2504 v<insn>.vv\t%0,%3,%4%p1
2505 v<insn>.vv\t%0,%3,%4%p1
2506 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2507 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2508 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2509 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2510 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2511 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2512 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2513 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
2514 [(set_attr "type" "<int_binop_insn_type>")
2515 (set_attr "mode" "<MODE>")])
2516
2517 ;; vx instructions patterns.
2518 ;; Note: Unlike vv patterns, we should split them since they are variant.
2519 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
2520 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
2521 (define_insn "@pred_<optab><mode>_scalar"
2522 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
2523 (if_then_else:V_VLSI
2524 (unspec:<VM>
2525 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
2526 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK, rK, rK")
2527 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2528 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2529 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2530 (reg:SI VL_REGNUM)
2531 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2532 (any_shift:V_VLSI
2533 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
2534 (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
2535 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
2536 "TARGET_VECTOR"
2537 "v<insn>.v%o4\t%0,%3,%4%p1"
2538 [(set_attr "type" "vshift")
2539 (set_attr "mode" "<MODE>")])
2540
2541 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
2542 (define_insn "@pred_<optab><mode>_scalar"
2543 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2544 (if_then_else:V_VLSI_QHS
2545 (unspec:<VM>
2546 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2547 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2548 (match_operand 6 "const_int_operand" " i, i, i, i")
2549 (match_operand 7 "const_int_operand" " i, i, i, i")
2550 (match_operand 8 "const_int_operand" " i, i, i, i")
2551 (reg:SI VL_REGNUM)
2552 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2553 (any_commutative_binop:V_VLSI_QHS
2554 (vec_duplicate:V_VLSI_QHS
2555 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2556 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2557 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2558 "TARGET_VECTOR"
2559 "v<insn>.vx\t%0,%3,%z4%p1"
2560 [(set_attr "type" "<int_binop_insn_type>")
2561 (set_attr "mode" "<MODE>")])
2562
2563 (define_insn "@pred_<optab><mode>_scalar"
2564 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2565 (if_then_else:V_VLSI_QHS
2566 (unspec:<VM>
2567 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2568 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2569 (match_operand 6 "const_int_operand" " i, i, i, i")
2570 (match_operand 7 "const_int_operand" " i, i, i, i")
2571 (match_operand 8 "const_int_operand" " i, i, i, i")
2572 (reg:SI VL_REGNUM)
2573 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2574 (any_non_commutative_binop:V_VLSI_QHS
2575 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
2576 (vec_duplicate:V_VLSI_QHS
2577 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2578 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2579 "TARGET_VECTOR"
2580 "v<insn>.vx\t%0,%3,%z4%p1"
2581 [(set_attr "type" "<int_binop_insn_type>")
2582 (set_attr "mode" "<MODE>")])
2583
2584 (define_insn "@pred_sub<mode>_reverse_scalar"
2585 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2586 (if_then_else:V_VLSI_QHS
2587 (unspec:<VM>
2588 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2589 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2590 (match_operand 6 "const_int_operand" " i, i, i, i")
2591 (match_operand 7 "const_int_operand" " i, i, i, i")
2592 (match_operand 8 "const_int_operand" " i, i, i, i")
2593 (reg:SI VL_REGNUM)
2594 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2595 (minus:V_VLSI_QHS
2596 (vec_duplicate:V_VLSI_QHS
2597 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2598 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2599 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2600 "TARGET_VECTOR"
2601 "vrsub.vx\t%0,%3,%z4%p1"
2602 [(set_attr "type" "vialu")
2603 (set_attr "mode" "<MODE>")])
2604
2605 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
2606 ;; we need to deal with SEW = 64 in RV32 system.
2607 (define_expand "@pred_<optab><mode>_scalar"
2608 [(set (match_operand:V_VLSI_D 0 "register_operand")
2609 (if_then_else:V_VLSI_D
2610 (unspec:<VM>
2611 [(match_operand:<VM> 1 "vector_mask_operand")
2612 (match_operand 5 "vector_length_operand")
2613 (match_operand 6 "const_int_operand")
2614 (match_operand 7 "const_int_operand")
2615 (match_operand 8 "const_int_operand")
2616 (reg:SI VL_REGNUM)
2617 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2618 (any_commutative_binop:V_VLSI_D
2619 (vec_duplicate:V_VLSI_D
2620 (match_operand:<VEL> 4 "reg_or_int_operand"))
2621 (match_operand:V_VLSI_D 3 "register_operand"))
2622 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2623 "TARGET_VECTOR"
2624 {
2625 if (riscv_vector::sew64_scalar_helper (
2626 operands,
2627 /* scalar op */&operands[4],
2628 /* vl */operands[5],
2629 <MODE>mode,
2630 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2631 [] (rtx *operands, rtx boardcast_scalar) {
2632 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2633 operands[2], operands[3], boardcast_scalar, operands[5],
2634 operands[6], operands[7], operands[8]));
2635 },
2636 (riscv_vector::avl_type) INTVAL (operands[8])))
2637 DONE;
2638 })
2639
2640 (define_insn "*pred_<optab><mode>_scalar"
2641 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2642 (if_then_else:V_VLSI_D
2643 (unspec:<VM>
2644 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2645 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2646 (match_operand 6 "const_int_operand" " i, i, i, i")
2647 (match_operand 7 "const_int_operand" " i, i, i, i")
2648 (match_operand 8 "const_int_operand" " i, i, i, i")
2649 (reg:SI VL_REGNUM)
2650 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2651 (any_commutative_binop:V_VLSI_D
2652 (vec_duplicate:V_VLSI_D
2653 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2654 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2655 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2656 "TARGET_VECTOR"
2657 "v<insn>.vx\t%0,%3,%z4%p1"
2658 [(set_attr "type" "<int_binop_insn_type>")
2659 (set_attr "mode" "<MODE>")])
2660
2661 (define_insn "*pred_<optab><mode>_extended_scalar"
2662 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2663 (if_then_else:V_VLSI_D
2664 (unspec:<VM>
2665 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2666 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2667 (match_operand 6 "const_int_operand" " i, i, i, i")
2668 (match_operand 7 "const_int_operand" " i, i, i, i")
2669 (match_operand 8 "const_int_operand" " i, i, i, i")
2670 (reg:SI VL_REGNUM)
2671 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2672 (any_commutative_binop:V_VLSI_D
2673 (vec_duplicate:V_VLSI_D
2674 (sign_extend:<VEL>
2675 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2676 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2677 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2678 "TARGET_VECTOR && !TARGET_64BIT"
2679 "v<insn>.vx\t%0,%3,%z4%p1"
2680 [(set_attr "type" "<int_binop_insn_type>")
2681 (set_attr "mode" "<MODE>")])
2682
2683 (define_expand "@pred_<optab><mode>_scalar"
2684 [(set (match_operand:V_VLSI_D 0 "register_operand")
2685 (if_then_else:V_VLSI_D
2686 (unspec:<VM>
2687 [(match_operand:<VM> 1 "vector_mask_operand")
2688 (match_operand 5 "vector_length_operand")
2689 (match_operand 6 "const_int_operand")
2690 (match_operand 7 "const_int_operand")
2691 (match_operand 8 "const_int_operand")
2692 (reg:SI VL_REGNUM)
2693 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2694 (any_non_commutative_binop:V_VLSI_D
2695 (match_operand:V_VLSI_D 3 "register_operand")
2696 (vec_duplicate:V_VLSI_D
2697 (match_operand:<VEL> 4 "reg_or_int_operand")))
2698 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2699 "TARGET_VECTOR"
2700 {
2701 if (riscv_vector::sew64_scalar_helper (
2702 operands,
2703 /* scalar op */&operands[4],
2704 /* vl */operands[5],
2705 <MODE>mode,
2706 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2707 [] (rtx *operands, rtx boardcast_scalar) {
2708 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2709 operands[2], operands[3], boardcast_scalar, operands[5],
2710 operands[6], operands[7], operands[8]));
2711 },
2712 (riscv_vector::avl_type) INTVAL (operands[8])))
2713 DONE;
2714 })
2715
2716 (define_insn "*pred_<optab><mode>_scalar"
2717 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2718 (if_then_else:V_VLSI_D
2719 (unspec:<VM>
2720 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2721 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2722 (match_operand 6 "const_int_operand" " i, i, i, i")
2723 (match_operand 7 "const_int_operand" " i, i, i, i")
2724 (match_operand 8 "const_int_operand" " i, i, i, i")
2725 (reg:SI VL_REGNUM)
2726 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2727 (any_non_commutative_binop:V_VLSI_D
2728 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2729 (vec_duplicate:V_VLSI_D
2730 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2731 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2732 "TARGET_VECTOR"
2733 "v<insn>.vx\t%0,%3,%z4%p1"
2734 [(set_attr "type" "<int_binop_insn_type>")
2735 (set_attr "mode" "<MODE>")])
2736
2737 (define_insn "*pred_<optab><mode>_extended_scalar"
2738 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2739 (if_then_else:V_VLSI_D
2740 (unspec:<VM>
2741 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2742 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2743 (match_operand 6 "const_int_operand" " i, i, i, i")
2744 (match_operand 7 "const_int_operand" " i, i, i, i")
2745 (match_operand 8 "const_int_operand" " i, i, i, i")
2746 (reg:SI VL_REGNUM)
2747 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2748 (any_non_commutative_binop:V_VLSI_D
2749 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2750 (vec_duplicate:V_VLSI_D
2751 (sign_extend:<VEL>
2752 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
2753 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2754 "TARGET_VECTOR && !TARGET_64BIT"
2755 "v<insn>.vx\t%0,%3,%z4%p1"
2756 [(set_attr "type" "<int_binop_insn_type>")
2757 (set_attr "mode" "<MODE>")])
2758
2759 (define_expand "@pred_sub<mode>_reverse_scalar"
2760 [(set (match_operand:V_VLSI_D 0 "register_operand")
2761 (if_then_else:V_VLSI_D
2762 (unspec:<VM>
2763 [(match_operand:<VM> 1 "vector_mask_operand")
2764 (match_operand 5 "vector_length_operand")
2765 (match_operand 6 "const_int_operand")
2766 (match_operand 7 "const_int_operand")
2767 (match_operand 8 "const_int_operand")
2768 (reg:SI VL_REGNUM)
2769 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2770 (minus:V_VLSI_D
2771 (vec_duplicate:V_VLSI_D
2772 (match_operand:<VEL> 4 "reg_or_int_operand"))
2773 (match_operand:V_VLSI_D 3 "register_operand"))
2774 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2775 "TARGET_VECTOR"
2776 {
2777 if (riscv_vector::sew64_scalar_helper (
2778 operands,
2779 /* scalar op */&operands[4],
2780 /* vl */operands[5],
2781 <MODE>mode,
2782 riscv_vector::neg_simm5_p (operands[4]),
2783 [] (rtx *operands, rtx boardcast_scalar) {
2784 emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
2785 operands[2], boardcast_scalar, operands[3], operands[5],
2786 operands[6], operands[7], operands[8]));
2787 },
2788 (riscv_vector::avl_type) INTVAL (operands[8])))
2789 DONE;
2790 })
2791
2792 (define_insn "*pred_sub<mode>_reverse_scalar"
2793 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2794 (if_then_else:V_VLSI_D
2795 (unspec:<VM>
2796 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2797 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2798 (match_operand 6 "const_int_operand" " i, i, i, i")
2799 (match_operand 7 "const_int_operand" " i, i, i, i")
2800 (match_operand 8 "const_int_operand" " i, i, i, i")
2801 (reg:SI VL_REGNUM)
2802 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2803 (minus:V_VLSI_D
2804 (vec_duplicate:V_VLSI_D
2805 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2806 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2807 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2808 "TARGET_VECTOR"
2809 "vrsub.vx\t%0,%3,%z4%p1"
2810 [(set_attr "type" "vialu")
2811 (set_attr "mode" "<MODE>")])
2812
2813 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
2814 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2815 (if_then_else:V_VLSI_D
2816 (unspec:<VM>
2817 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2818 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2819 (match_operand 6 "const_int_operand" " i, i, i, i")
2820 (match_operand 7 "const_int_operand" " i, i, i, i")
2821 (match_operand 8 "const_int_operand" " i, i, i, i")
2822 (reg:SI VL_REGNUM)
2823 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2824 (minus:V_VLSI_D
2825 (vec_duplicate:V_VLSI_D
2826 (sign_extend:<VEL>
2827 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2828 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2829 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2830 "TARGET_VECTOR && !TARGET_64BIT"
2831 "vrsub.vx\t%0,%3,%z4%p1"
2832 [(set_attr "type" "vialu")
2833 (set_attr "mode" "<MODE>")])
2834
2835 ;; Multiply High instructions.
2836 (define_insn "@pred_mulh<v_su><mode>"
2837 [(set (match_operand:VFULLI 0 "register_operand" "=vd,vd, vr, vr")
2838 (if_then_else:VFULLI
2839 (unspec:<VM>
2840 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2841 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2842 (match_operand 6 "const_int_operand" " i, i, i, i")
2843 (match_operand 7 "const_int_operand" " i, i, i, i")
2844 (match_operand 8 "const_int_operand" " i, i, i, i")
2845 (reg:SI VL_REGNUM)
2846 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2847 (unspec:VFULLI
2848 [(match_operand:VFULLI 3 "register_operand" "vr,vr, vr, vr")
2849 (match_operand:VFULLI 4 "register_operand" "vr,vr, vr, vr")] VMULH)
2850 (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2851 "TARGET_VECTOR"
2852 "vmulh<v_su>.vv\t%0,%3,%4%p1"
2853 [(set_attr "type" "vimul")
2854 (set_attr "mode" "<MODE>")])
2855
2856 (define_insn "@pred_mulh<v_su><mode>_scalar"
2857 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2858 (if_then_else:VI_QHS
2859 (unspec:<VM>
2860 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2861 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2862 (match_operand 6 "const_int_operand" " i, i, i, i")
2863 (match_operand 7 "const_int_operand" " i, i, i, i")
2864 (match_operand 8 "const_int_operand" " i, i, i, i")
2865 (reg:SI VL_REGNUM)
2866 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2867 (unspec:VI_QHS
2868 [(vec_duplicate:VI_QHS
2869 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2870 (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2871 (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2872 "TARGET_VECTOR"
2873 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2874 [(set_attr "type" "vimul")
2875 (set_attr "mode" "<MODE>")])
2876
2877 (define_expand "@pred_mulh<v_su><mode>_scalar"
2878 [(set (match_operand:VFULLI_D 0 "register_operand")
2879 (if_then_else:VFULLI_D
2880 (unspec:<VM>
2881 [(match_operand:<VM> 1 "vector_mask_operand")
2882 (match_operand 5 "vector_length_operand")
2883 (match_operand 6 "const_int_operand")
2884 (match_operand 7 "const_int_operand")
2885 (match_operand 8 "const_int_operand")
2886 (reg:SI VL_REGNUM)
2887 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2888 (unspec:VFULLI_D
2889 [(vec_duplicate:VFULLI_D
2890 (match_operand:<VEL> 4 "reg_or_int_operand"))
2891 (match_operand:VFULLI_D 3 "register_operand")] VMULH)
2892 (match_operand:VFULLI_D 2 "vector_merge_operand")))]
2893 "TARGET_VECTOR"
2894 {
2895 if (riscv_vector::sew64_scalar_helper (
2896 operands,
2897 /* scalar op */&operands[4],
2898 /* vl */operands[5],
2899 <MODE>mode,
2900 false,
2901 [] (rtx *operands, rtx boardcast_scalar) {
2902 emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
2903 operands[2], operands[3], boardcast_scalar, operands[5],
2904 operands[6], operands[7], operands[8]));
2905 },
2906 (riscv_vector::avl_type) INTVAL (operands[8])))
2907 DONE;
2908 })
2909
2910 (define_insn "*pred_mulh<v_su><mode>_scalar"
2911 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2912 (if_then_else:VFULLI_D
2913 (unspec:<VM>
2914 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2915 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2916 (match_operand 6 "const_int_operand" " i, i, i, i")
2917 (match_operand 7 "const_int_operand" " i, i, i, i")
2918 (match_operand 8 "const_int_operand" " i, i, i, i")
2919 (reg:SI VL_REGNUM)
2920 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2921 (unspec:VFULLI_D
2922 [(vec_duplicate:VFULLI_D
2923 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2924 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2925 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2926 "TARGET_VECTOR"
2927 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2928 [(set_attr "type" "vimul")
2929 (set_attr "mode" "<MODE>")])
2930
2931 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
2932 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2933 (if_then_else:VFULLI_D
2934 (unspec:<VM>
2935 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2936 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2937 (match_operand 6 "const_int_operand" " i, i, i, i")
2938 (match_operand 7 "const_int_operand" " i, i, i, i")
2939 (match_operand 8 "const_int_operand" " i, i, i, i")
2940 (reg:SI VL_REGNUM)
2941 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2942 (unspec:VFULLI_D
2943 [(vec_duplicate:VFULLI_D
2944 (sign_extend:<VEL>
2945 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2946 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2947 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2948 "TARGET_VECTOR && !TARGET_64BIT"
2949 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2950 [(set_attr "type" "vimul")
2951 (set_attr "mode" "<MODE>")])
2952
2953 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2954 (define_insn "@pred_adc<mode>"
2955 [(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
2956 (if_then_else:VI
2957 (unspec:<VM>
2958 [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
2959 (match_operand 6 "const_int_operand" " i, i, i, i")
2960 (match_operand 7 "const_int_operand" " i, i, i, i")
2961 (reg:SI VL_REGNUM)
2962 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2963 (unspec:VI
2964 [(plus:VI
2965 (match_operand:VI 2 "register_operand" "vr,vr,vr,vr")
2966 (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
2967 (match_operand:<VM> 4 "register_operand" "vm,vm,vm,vm")] UNSPEC_VADC)
2968 (match_operand:VI 1 "vector_merge_operand" "vu, 0,vu, 0")))]
2969 "TARGET_VECTOR"
2970 "vadc.v%o3m\t%0,%2,%v3,%4"
2971 [(set_attr "type" "vicalu")
2972 (set_attr "mode" "<MODE>")
2973 (set_attr "merge_op_idx" "1")
2974 (set_attr "vl_op_idx" "5")
2975 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
2976 (set (attr "avl_type_idx") (const_int 7))])
2977
2978 (define_insn "@pred_sbc<mode>"
2979 [(set (match_operand:VI 0 "register_operand" "=vd,vd")
2980 (if_then_else:VI
2981 (unspec:<VM>
2982 [(match_operand 5 "vector_length_operand" "rK,rK")
2983 (match_operand 6 "const_int_operand" " i, i")
2984 (match_operand 7 "const_int_operand" " i, i")
2985 (reg:SI VL_REGNUM)
2986 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2987 (unspec:VI
2988 [(minus:VI
2989 (match_operand:VI 2 "register_operand" "vr,vr")
2990 (match_operand:VI 3 "register_operand" "vr,vr"))
2991 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
2992 (match_operand:VI 1 "vector_merge_operand" "vu, 0")))]
2993 "TARGET_VECTOR"
2994 "vsbc.vvm\t%0,%2,%3,%4"
2995 [(set_attr "type" "vicalu")
2996 (set_attr "mode" "<MODE>")
2997 (set_attr "merge_op_idx" "1")
2998 (set_attr "vl_op_idx" "5")
2999 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3000 (set (attr "avl_type_idx") (const_int 7))])
3001
3002 (define_insn "@pred_adc<mode>_scalar"
3003 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3004 (if_then_else:VI_QHS
3005 (unspec:<VM>
3006 [(match_operand 5 "vector_length_operand" "rK,rK")
3007 (match_operand 6 "const_int_operand" " i, i")
3008 (match_operand 7 "const_int_operand" " i, i")
3009 (reg:SI VL_REGNUM)
3010 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3011 (unspec:VI_QHS
3012 [(plus:VI_QHS
3013 (vec_duplicate:VI_QHS
3014 (match_operand:<VEL> 3 "register_operand" " r, r"))
3015 (match_operand:VI_QHS 2 "register_operand" "vr,vr"))
3016 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3017 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3018 "TARGET_VECTOR"
3019 "vadc.vxm\t%0,%2,%3,%4"
3020 [(set_attr "type" "vicalu")
3021 (set_attr "mode" "<MODE>")
3022 (set_attr "merge_op_idx" "1")
3023 (set_attr "vl_op_idx" "5")
3024 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3025 (set (attr "avl_type_idx") (const_int 7))])
3026
3027 (define_insn "@pred_sbc<mode>_scalar"
3028 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3029 (if_then_else:VI_QHS
3030 (unspec:<VM>
3031 [(match_operand 5 "vector_length_operand" "rK,rK")
3032 (match_operand 6 "const_int_operand" " i, i")
3033 (match_operand 7 "const_int_operand" " i, i")
3034 (reg:SI VL_REGNUM)
3035 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3036 (unspec:VI_QHS
3037 [(minus:VI_QHS
3038 (match_operand:VI_QHS 2 "register_operand" "vr,vr")
3039 (vec_duplicate:VI_QHS
3040 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3041 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3042 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3043 "TARGET_VECTOR"
3044 "vsbc.vxm\t%0,%2,%z3,%4"
3045 [(set_attr "type" "vicalu")
3046 (set_attr "mode" "<MODE>")
3047 (set_attr "merge_op_idx" "1")
3048 (set_attr "vl_op_idx" "5")
3049 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3050 (set (attr "avl_type_idx") (const_int 7))])
3051
3052 (define_expand "@pred_adc<mode>_scalar"
3053 [(set (match_operand:VI_D 0 "register_operand")
3054 (if_then_else:VI_D
3055 (unspec:<VM>
3056 [(match_operand 5 "vector_length_operand")
3057 (match_operand 6 "const_int_operand")
3058 (match_operand 7 "const_int_operand")
3059 (reg:SI VL_REGNUM)
3060 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3061 (unspec:VI_D
3062 [(plus:VI_D
3063 (vec_duplicate:VI_D
3064 (match_operand:<VEL> 3 "reg_or_int_operand"))
3065 (match_operand:VI_D 2 "register_operand"))
3066 (match_operand:<VM> 4 "register_operand")] UNSPEC_VADC)
3067 (match_operand:VI_D 1 "vector_merge_operand")))]
3068 "TARGET_VECTOR"
3069 {
3070 if (riscv_vector::sew64_scalar_helper (
3071 operands,
3072 /* scalar op */&operands[3],
3073 /* vl */operands[5],
3074 <MODE>mode,
3075 riscv_vector::simm5_p (operands[3]),
3076 [] (rtx *operands, rtx boardcast_scalar) {
3077 emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
3078 operands[2], boardcast_scalar, operands[4], operands[5],
3079 operands[6], operands[7]));
3080 },
3081 (riscv_vector::avl_type) INTVAL (operands[7])))
3082 DONE;
3083 })
3084
3085 (define_insn "*pred_adc<mode>_scalar"
3086 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3087 (if_then_else:VI_D
3088 (unspec:<VM>
3089 [(match_operand 5 "vector_length_operand" "rK,rK")
3090 (match_operand 6 "const_int_operand" " i, i")
3091 (match_operand 7 "const_int_operand" " i, i")
3092 (reg:SI VL_REGNUM)
3093 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3094 (unspec:VI_D
3095 [(plus:VI_D
3096 (vec_duplicate:VI_D
3097 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
3098 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3099 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3100 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3101 "TARGET_VECTOR"
3102 "vadc.vxm\t%0,%2,%z3,%4"
3103 [(set_attr "type" "vicalu")
3104 (set_attr "mode" "<MODE>")
3105 (set_attr "merge_op_idx" "1")
3106 (set_attr "vl_op_idx" "5")
3107 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3108 (set (attr "avl_type_idx") (const_int 7))])
3109
3110 (define_insn "*pred_adc<mode>_extended_scalar"
3111 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3112 (if_then_else:VI_D
3113 (unspec:<VM>
3114 [(match_operand 5 "vector_length_operand" "rK,rK")
3115 (match_operand 6 "const_int_operand" " i, i")
3116 (match_operand 7 "const_int_operand" " i, i")
3117 (reg:SI VL_REGNUM)
3118 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3119 (unspec:VI_D
3120 [(plus:VI_D
3121 (vec_duplicate:VI_D
3122 (sign_extend:<VEL>
3123 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
3124 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3125 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3126 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3127 "TARGET_VECTOR && !TARGET_64BIT"
3128 "vadc.vxm\t%0,%2,%z3,%4"
3129 [(set_attr "type" "vicalu")
3130 (set_attr "mode" "<MODE>")
3131 (set_attr "merge_op_idx" "1")
3132 (set_attr "vl_op_idx" "5")
3133 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3134 (set (attr "avl_type_idx") (const_int 7))])
3135
3136 (define_expand "@pred_sbc<mode>_scalar"
3137 [(set (match_operand:VI_D 0 "register_operand")
3138 (if_then_else:VI_D
3139 (unspec:<VM>
3140 [(match_operand 5 "vector_length_operand")
3141 (match_operand 6 "const_int_operand")
3142 (match_operand 7 "const_int_operand")
3143 (reg:SI VL_REGNUM)
3144 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3145 (unspec:VI_D
3146 [(minus:VI_D
3147 (match_operand:VI_D 2 "register_operand")
3148 (vec_duplicate:VI_D
3149 (match_operand:<VEL> 3 "reg_or_int_operand")))
3150 (match_operand:<VM> 4 "register_operand")] UNSPEC_VSBC)
3151 (match_operand:VI_D 1 "vector_merge_operand")))]
3152 "TARGET_VECTOR"
3153 {
3154 if (riscv_vector::sew64_scalar_helper (
3155 operands,
3156 /* scalar op */&operands[3],
3157 /* vl */operands[5],
3158 <MODE>mode,
3159 false,
3160 [] (rtx *operands, rtx boardcast_scalar) {
3161 emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
3162 operands[2], boardcast_scalar, operands[4], operands[5],
3163 operands[6], operands[7]));
3164 },
3165 (riscv_vector::avl_type) INTVAL (operands[7])))
3166 DONE;
3167 })
3168
3169 (define_insn "*pred_sbc<mode>_scalar"
3170 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3171 (if_then_else:VI_D
3172 (unspec:<VM>
3173 [(match_operand 5 "vector_length_operand" "rK,rK")
3174 (match_operand 6 "const_int_operand" " i, i")
3175 (match_operand 7 "const_int_operand" " i, i")
3176 (reg:SI VL_REGNUM)
3177 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3178 (unspec:VI_D
3179 [(minus:VI_D
3180 (match_operand:VI_D 2 "register_operand" "vr,vr")
3181 (vec_duplicate:VI_D
3182 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3183 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3184 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3185 "TARGET_VECTOR"
3186 "vsbc.vxm\t%0,%2,%z3,%4"
3187 [(set_attr "type" "vicalu")
3188 (set_attr "mode" "<MODE>")
3189 (set_attr "merge_op_idx" "1")
3190 (set_attr "vl_op_idx" "5")
3191 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3192 (set (attr "avl_type_idx") (const_int 7))])
3193
3194 (define_insn "*pred_sbc<mode>_extended_scalar"
3195 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3196 (if_then_else:VI_D
3197 (unspec:<VM>
3198 [(match_operand 5 "vector_length_operand" "rK,rK")
3199 (match_operand 6 "const_int_operand" " i, i")
3200 (match_operand 7 "const_int_operand" " i, i")
3201 (reg:SI VL_REGNUM)
3202 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3203 (unspec:VI_D
3204 [(minus:VI_D
3205 (match_operand:VI_D 2 "register_operand" "vr,vr")
3206 (vec_duplicate:VI_D
3207 (sign_extend:<VEL>
3208 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
3209 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3210 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3211 "TARGET_VECTOR && !TARGET_64BIT"
3212 "vsbc.vxm\t%0,%2,%z3,%4"
3213 [(set_attr "type" "vicalu")
3214 (set_attr "mode" "<MODE>")
3215 (set_attr "merge_op_idx" "1")
3216 (set_attr "vl_op_idx" "5")
3217 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3218 (set (attr "avl_type_idx") (const_int 7))])
3219
3220 (define_insn "@pred_madc<mode>"
3221 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3222 (unspec:<VM>
3223 [(plus:VI
3224 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3225 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3226 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3227 (unspec:<VM>
3228 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3229 (match_operand 5 "const_int_operand" " i, i, i")
3230 (reg:SI VL_REGNUM)
3231 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3232 "TARGET_VECTOR"
3233 "vmadc.v%o2m\t%0,%1,%v2,%3"
3234 [(set_attr "type" "vicalu")
3235 (set_attr "mode" "<MODE>")
3236 (set_attr "vl_op_idx" "4")
3237 (set (attr "avl_type_idx") (const_int 5))])
3238
3239 (define_insn "@pred_msbc<mode>"
3240 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
3241 (unspec:<VM>
3242 [(minus:VI
3243 (match_operand:VI 1 "register_operand" " 0, vr, vr")
3244 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
3245 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3246 (unspec:<VM>
3247 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3248 (match_operand 5 "const_int_operand" " i, i, i")
3249 (reg:SI VL_REGNUM)
3250 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3251 "TARGET_VECTOR"
3252 "vmsbc.vvm\t%0,%1,%2,%3"
3253 [(set_attr "type" "vicalu")
3254 (set_attr "mode" "<MODE>")
3255 (set_attr "vl_op_idx" "4")
3256 (set (attr "avl_type_idx") (const_int 5))])
3257
3258 (define_insn "@pred_madc<mode>_scalar"
3259 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3260 (unspec:<VM>
3261 [(plus:VI_QHS
3262 (vec_duplicate:VI_QHS
3263 (match_operand:<VEL> 2 "register_operand" " r, r"))
3264 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3265 (match_operand:<VM> 3 "register_operand" " vm, vm")
3266 (unspec:<VM>
3267 [(match_operand 4 "vector_length_operand" " rK, rK")
3268 (match_operand 5 "const_int_operand" " i, i")
3269 (reg:SI VL_REGNUM)
3270 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3271 "TARGET_VECTOR"
3272 "vmadc.vxm\t%0,%1,%2,%3"
3273 [(set_attr "type" "vicalu")
3274 (set_attr "mode" "<MODE>")
3275 (set_attr "vl_op_idx" "4")
3276 (set (attr "avl_type_idx") (const_int 5))])
3277
3278 (define_insn "@pred_msbc<mode>_scalar"
3279 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3280 (unspec:<VM>
3281 [(minus:VI_QHS
3282 (vec_duplicate:VI_QHS
3283 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3284 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3285 (match_operand:<VM> 3 "register_operand" " vm, vm")
3286 (unspec:<VM>
3287 [(match_operand 4 "vector_length_operand" " rK, rK")
3288 (match_operand 5 "const_int_operand" " i, i")
3289 (reg:SI VL_REGNUM)
3290 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3291 "TARGET_VECTOR"
3292 "vmsbc.vxm\t%0,%1,%z2,%3"
3293 [(set_attr "type" "vicalu")
3294 (set_attr "mode" "<MODE>")
3295 (set_attr "vl_op_idx" "4")
3296 (set (attr "avl_type_idx") (const_int 5))])
3297
3298 (define_expand "@pred_madc<mode>_scalar"
3299 [(set (match_operand:<VM> 0 "register_operand")
3300 (unspec:<VM>
3301 [(plus:VI_D
3302 (vec_duplicate:VI_D
3303 (match_operand:<VEL> 2 "reg_or_int_operand"))
3304 (match_operand:VI_D 1 "register_operand"))
3305 (match_operand:<VM> 3 "register_operand")
3306 (unspec:<VM>
3307 [(match_operand 4 "vector_length_operand")
3308 (match_operand 5 "const_int_operand")
3309 (reg:SI VL_REGNUM)
3310 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3311 "TARGET_VECTOR"
3312 {
3313 if (riscv_vector::sew64_scalar_helper (
3314 operands,
3315 /* scalar op */&operands[2],
3316 /* vl */operands[4],
3317 <MODE>mode,
3318 riscv_vector::simm5_p (operands[2]),
3319 [] (rtx *operands, rtx boardcast_scalar) {
3320 emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
3321 boardcast_scalar, operands[3], operands[4], operands[5]));
3322 },
3323 (riscv_vector::avl_type) INTVAL (operands[5])))
3324 DONE;
3325 })
3326
3327 (define_insn "*pred_madc<mode>_scalar"
3328 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3329 (unspec:<VM>
3330 [(plus:VI_D
3331 (vec_duplicate:VI_D
3332 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3333 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3334 (match_operand:<VM> 3 "register_operand" " vm, vm")
3335 (unspec:<VM>
3336 [(match_operand 4 "vector_length_operand" " rK, rK")
3337 (match_operand 5 "const_int_operand" " i, i")
3338 (reg:SI VL_REGNUM)
3339 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3340 "TARGET_VECTOR"
3341 "vmadc.vxm\t%0,%1,%z2,%3"
3342 [(set_attr "type" "vicalu")
3343 (set_attr "mode" "<MODE>")
3344 (set_attr "vl_op_idx" "4")
3345 (set (attr "avl_type_idx") (const_int 5))])
3346
3347 (define_insn "*pred_madc<mode>_extended_scalar"
3348 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3349 (unspec:<VM>
3350 [(plus:VI_D
3351 (vec_duplicate:VI_D
3352 (sign_extend:<VEL>
3353 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3354 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3355 (match_operand:<VM> 3 "register_operand" " vm, vm")
3356 (unspec:<VM>
3357 [(match_operand 4 "vector_length_operand" " rK, rK")
3358 (match_operand 5 "const_int_operand" " i, i")
3359 (reg:SI VL_REGNUM)
3360 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3361 "TARGET_VECTOR && !TARGET_64BIT"
3362 "vmadc.vxm\t%0,%1,%z2,%3"
3363 [(set_attr "type" "vicalu")
3364 (set_attr "mode" "<MODE>")
3365 (set_attr "vl_op_idx" "4")
3366 (set (attr "avl_type_idx") (const_int 5))])
3367
3368 (define_expand "@pred_msbc<mode>_scalar"
3369 [(set (match_operand:<VM> 0 "register_operand")
3370 (unspec:<VM>
3371 [(minus:VI_D
3372 (vec_duplicate:VI_D
3373 (match_operand:<VEL> 2 "reg_or_int_operand"))
3374 (match_operand:VI_D 1 "register_operand"))
3375 (match_operand:<VM> 3 "register_operand")
3376 (unspec:<VM>
3377 [(match_operand 4 "vector_length_operand")
3378 (match_operand 5 "const_int_operand")
3379 (reg:SI VL_REGNUM)
3380 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3381 "TARGET_VECTOR"
3382 {
3383 if (riscv_vector::sew64_scalar_helper (
3384 operands,
3385 /* scalar op */&operands[2],
3386 /* vl */operands[4],
3387 <MODE>mode,
3388 false,
3389 [] (rtx *operands, rtx boardcast_scalar) {
3390 emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
3391 boardcast_scalar, operands[3], operands[4], operands[5]));
3392 },
3393 (riscv_vector::avl_type) INTVAL (operands[5])))
3394 DONE;
3395 })
3396
3397 (define_insn "*pred_msbc<mode>_scalar"
3398 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3399 (unspec:<VM>
3400 [(minus:VI_D
3401 (vec_duplicate:VI_D
3402 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3403 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3404 (match_operand:<VM> 3 "register_operand" " vm, vm")
3405 (unspec:<VM>
3406 [(match_operand 4 "vector_length_operand" " rK, rK")
3407 (match_operand 5 "const_int_operand" " i, i")
3408 (reg:SI VL_REGNUM)
3409 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3410 "TARGET_VECTOR"
3411 "vmsbc.vxm\t%0,%1,%z2,%3"
3412 [(set_attr "type" "vicalu")
3413 (set_attr "mode" "<MODE>")
3414 (set_attr "vl_op_idx" "4")
3415 (set (attr "avl_type_idx") (const_int 5))])
3416
3417 (define_insn "*pred_msbc<mode>_extended_scalar"
3418 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3419 (unspec:<VM>
3420 [(minus:VI_D
3421 (vec_duplicate:VI_D
3422 (sign_extend:<VEL>
3423 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3424 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3425 (match_operand:<VM> 3 "register_operand" " vm, vm")
3426 (unspec:<VM>
3427 [(match_operand 4 "vector_length_operand" " rK, rK")
3428 (match_operand 5 "const_int_operand" " i, i")
3429 (reg:SI VL_REGNUM)
3430 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3431 "TARGET_VECTOR && !TARGET_64BIT"
3432 "vmsbc.vxm\t%0,%1,%z2,%3"
3433 [(set_attr "type" "vicalu")
3434 (set_attr "mode" "<MODE>")
3435 (set_attr "vl_op_idx" "4")
3436 (set (attr "avl_type_idx") (const_int 5))])
3437
3438 (define_insn "@pred_madc<mode>_overflow"
3439 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3440 (unspec:<VM>
3441 [(plus:VI
3442 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3443 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3444 (unspec:<VM>
3445 [(match_operand 3 "vector_length_operand" " rK, rK, rK")
3446 (match_operand 4 "const_int_operand" " i, i, i")
3447 (reg:SI VL_REGNUM)
3448 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3449 "TARGET_VECTOR"
3450 "vmadc.v%o2\t%0,%1,%v2"
3451 [(set_attr "type" "vicalu")
3452 (set_attr "mode" "<MODE>")
3453 (set_attr "vl_op_idx" "3")
3454 (set (attr "avl_type_idx") (const_int 4))])
3455
3456 (define_insn "@pred_msbc<mode>_overflow"
3457 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
3458 (unspec:<VM>
3459 [(minus:VI
3460 (match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
3461 (match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
3462 (unspec:<VM>
3463 [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
3464 (match_operand 4 "const_int_operand" " i, i, i, i")
3465 (reg:SI VL_REGNUM)
3466 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3467 "TARGET_VECTOR"
3468 "vmsbc.vv\t%0,%1,%2"
3469 [(set_attr "type" "vicalu")
3470 (set_attr "mode" "<MODE>")
3471 (set_attr "vl_op_idx" "3")
3472 (set (attr "avl_type_idx") (const_int 4))])
3473
3474 (define_insn "@pred_madc<mode>_overflow_scalar"
3475 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3476 (unspec:<VM>
3477 [(plus:VI_QHS
3478 (vec_duplicate:VI_QHS
3479 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3480 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3481 (unspec:<VM>
3482 [(match_operand 3 "vector_length_operand" " rK, rK")
3483 (match_operand 4 "const_int_operand" " i, i")
3484 (reg:SI VL_REGNUM)
3485 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3486 "TARGET_VECTOR"
3487 "vmadc.vx\t%0,%1,%z2"
3488 [(set_attr "type" "vicalu")
3489 (set_attr "mode" "<MODE>")
3490 (set_attr "vl_op_idx" "3")
3491 (set (attr "avl_type_idx") (const_int 4))])
3492
3493 (define_insn "@pred_msbc<mode>_overflow_scalar"
3494 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3495 (unspec:<VM>
3496 [(minus:VI_QHS
3497 (vec_duplicate:VI_QHS
3498 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3499 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3500 (unspec:<VM>
3501 [(match_operand 3 "vector_length_operand" " rK, rK")
3502 (match_operand 4 "const_int_operand" " i, i")
3503 (reg:SI VL_REGNUM)
3504 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3505 "TARGET_VECTOR"
3506 "vmsbc.vx\t%0,%1,%z2"
3507 [(set_attr "type" "vicalu")
3508 (set_attr "mode" "<MODE>")
3509 (set_attr "vl_op_idx" "3")
3510 (set (attr "avl_type_idx") (const_int 4))])
3511
3512 (define_expand "@pred_madc<mode>_overflow_scalar"
3513 [(set (match_operand:<VM> 0 "register_operand")
3514 (unspec:<VM>
3515 [(plus:VI_D
3516 (vec_duplicate:VI_D
3517 (match_operand:<VEL> 2 "reg_or_int_operand"))
3518 (match_operand:VI_D 1 "register_operand"))
3519 (unspec:<VM>
3520 [(match_operand 3 "vector_length_operand")
3521 (match_operand 4 "const_int_operand")
3522 (reg:SI VL_REGNUM)
3523 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3524 "TARGET_VECTOR"
3525 {
3526 if (riscv_vector::sew64_scalar_helper (
3527 operands,
3528 /* scalar op */&operands[2],
3529 /* vl */operands[3],
3530 <MODE>mode,
3531 riscv_vector::simm5_p (operands[2]),
3532 [] (rtx *operands, rtx boardcast_scalar) {
3533 emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
3534 boardcast_scalar, operands[3], operands[4]));
3535 },
3536 (riscv_vector::avl_type) INTVAL (operands[4])))
3537 DONE;
3538 })
3539
3540 (define_insn "*pred_madc<mode>_overflow_scalar"
3541 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3542 (unspec:<VM>
3543 [(plus:VI_D
3544 (vec_duplicate:VI_D
3545 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3546 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3547 (unspec:<VM>
3548 [(match_operand 3 "vector_length_operand" " rK, rK")
3549 (match_operand 4 "const_int_operand" " i, i")
3550 (reg:SI VL_REGNUM)
3551 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3552 "TARGET_VECTOR"
3553 "vmadc.vx\t%0,%1,%z2"
3554 [(set_attr "type" "vicalu")
3555 (set_attr "mode" "<MODE>")
3556 (set_attr "vl_op_idx" "3")
3557 (set (attr "avl_type_idx") (const_int 4))])
3558
3559 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
3560 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3561 (unspec:<VM>
3562 [(plus:VI_D
3563 (vec_duplicate:VI_D
3564 (sign_extend:<VEL>
3565 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3566 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3567 (unspec:<VM>
3568 [(match_operand 3 "vector_length_operand" " rK, rK")
3569 (match_operand 4 "const_int_operand" " i, i")
3570 (reg:SI VL_REGNUM)
3571 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3572 "TARGET_VECTOR && !TARGET_64BIT"
3573 "vmadc.vx\t%0,%1,%z2"
3574 [(set_attr "type" "vicalu")
3575 (set_attr "mode" "<MODE>")
3576 (set_attr "vl_op_idx" "3")
3577 (set (attr "avl_type_idx") (const_int 4))])
3578
3579 (define_expand "@pred_msbc<mode>_overflow_scalar"
3580 [(set (match_operand:<VM> 0 "register_operand")
3581 (unspec:<VM>
3582 [(minus:VI_D
3583 (vec_duplicate:VI_D
3584 (match_operand:<VEL> 2 "reg_or_int_operand"))
3585 (match_operand:VI_D 1 "register_operand"))
3586 (unspec:<VM>
3587 [(match_operand 3 "vector_length_operand")
3588 (match_operand 4 "const_int_operand")
3589 (reg:SI VL_REGNUM)
3590 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3591 "TARGET_VECTOR"
3592 {
3593 if (riscv_vector::sew64_scalar_helper (
3594 operands,
3595 /* scalar op */&operands[2],
3596 /* vl */operands[3],
3597 <MODE>mode,
3598 false,
3599 [] (rtx *operands, rtx boardcast_scalar) {
3600 emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
3601 boardcast_scalar, operands[3], operands[4]));
3602 },
3603 (riscv_vector::avl_type) INTVAL (operands[4])))
3604 DONE;
3605 })
3606
3607 (define_insn "*pred_msbc<mode>_overflow_scalar"
3608 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3609 (unspec:<VM>
3610 [(minus:VI_D
3611 (vec_duplicate:VI_D
3612 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3613 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3614 (unspec:<VM>
3615 [(match_operand 3 "vector_length_operand" " rK, rK")
3616 (match_operand 4 "const_int_operand" " i, i")
3617 (reg:SI VL_REGNUM)
3618 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3619 "TARGET_VECTOR"
3620 "vmsbc.vx\t%0,%1,%z2"
3621 [(set_attr "type" "vicalu")
3622 (set_attr "mode" "<MODE>")
3623 (set_attr "vl_op_idx" "3")
3624 (set (attr "avl_type_idx") (const_int 4))])
3625
3626 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
3627 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3628 (unspec:<VM>
3629 [(minus:VI_D
3630 (vec_duplicate:VI_D
3631 (sign_extend:<VEL>
3632 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3633 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3634 (unspec:<VM>
3635 [(match_operand 3 "vector_length_operand" " rK, rK")
3636 (match_operand 4 "const_int_operand" " i, i")
3637 (reg:SI VL_REGNUM)
3638 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3639 "TARGET_VECTOR && !TARGET_64BIT"
3640 "vmsbc.vx\t%0,%1,%z2"
3641 [(set_attr "type" "vicalu")
3642 (set_attr "mode" "<MODE>")
3643 (set_attr "vl_op_idx" "3")
3644 (set (attr "avl_type_idx") (const_int 4))])
3645
3646 ;; -------------------------------------------------------------------------------
3647 ;; ---- Predicated integer unary operations
3648 ;; -------------------------------------------------------------------------------
3649 ;; Includes:
3650 ;; - vneg.v/vnot.v
3651 ;; -------------------------------------------------------------------------------
3652
3653 (define_insn "@pred_<optab><mode>"
3654 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
3655 (if_then_else:V_VLSI
3656 (unspec:<VM>
3657 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3658 (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
3659 (match_operand 5 "const_int_operand" " i, i, i, i")
3660 (match_operand 6 "const_int_operand" " i, i, i, i")
3661 (match_operand 7 "const_int_operand" " i, i, i, i")
3662 (reg:SI VL_REGNUM)
3663 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3664 (any_int_unop:V_VLSI
3665 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
3666 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3667 "TARGET_VECTOR"
3668 "v<insn>.v\t%0,%3%p1"
3669 [(set_attr "type" "vialu")
3670 (set_attr "mode" "<MODE>")
3671 (set_attr "vl_op_idx" "4")
3672 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3673 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3674 (set (attr "avl_type_idx") (const_int 7))])
3675
3676 ;; -------------------------------------------------------------------------------
3677 ;; ---- Predicated integer widening binary operations
3678 ;; -------------------------------------------------------------------------------
3679 ;; Includes:
3680 ;; - 11.2 Vector Widening Integer Add/Subtract
3681 ;; - 11.3 Vector Integer Extension
3682 ;; - 11.12 Vector Widening Integer Multiply Instructions
3683 ;; -------------------------------------------------------------------------------
3684
3685 ;; Vector Double-Widening Sign-extend and Zero-extend.
3686 (define_insn "@pred_<optab><mode>_vf2"
3687 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3688 (if_then_else:VWEXTI
3689 (unspec:<VM>
3690 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3691 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3692 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3693 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3694 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3695 (reg:SI VL_REGNUM)
3696 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3697 (any_extend:VWEXTI
3698 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3699 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3700 "TARGET_VECTOR"
3701 "v<sz>ext.vf2\t%0,%3%p1"
3702 [(set_attr "type" "vext")
3703 (set_attr "mode" "<MODE>")
3704 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3705
3706 ;; Vector Quad-Widening Sign-extend and Zero-extend.
3707 (define_insn "@pred_<optab><mode>_vf4"
3708 [(set (match_operand:VQEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3709 (if_then_else:VQEXTI
3710 (unspec:<VM>
3711 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3712 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3713 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
3714 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
3715 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
3716 (reg:SI VL_REGNUM)
3717 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3718 (any_extend:VQEXTI
3719 (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr"))
3720 (match_operand:VQEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3721 "TARGET_VECTOR"
3722 "v<sz>ext.vf4\t%0,%3%p1"
3723 [(set_attr "type" "vext")
3724 (set_attr "mode" "<MODE>")
3725 (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")])
3726
3727 ;; Vector Oct-Widening Sign-extend and Zero-extend.
3728 (define_insn "@pred_<optab><mode>_vf8"
3729 [(set (match_operand:VOEXTI 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr")
3730 (if_then_else:VOEXTI
3731 (unspec:<VM>
3732 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3733 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3734 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
3735 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3736 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3737 (reg:SI VL_REGNUM)
3738 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3739 (any_extend:VOEXTI
3740 (match_operand:<V_OCT_TRUNC> 3 "register_operand" "W87,W87,W87,W87, vr, vr"))
3741 (match_operand:VOEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))]
3742 "TARGET_VECTOR"
3743 "v<sz>ext.vf8\t%0,%3%p1"
3744 [(set_attr "type" "vext")
3745 (set_attr "mode" "<MODE>")
3746 (set_attr "group_overlap" "W87,W87,W87,W87,none,none")])
3747
3748 ;; Vector Widening Add/Subtract/Multiply.
3749 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
3750 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3751 (if_then_else:VWEXTI
3752 (unspec:<VM>
3753 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3754 (match_operand 5 "vector_length_operand" " rK, rK")
3755 (match_operand 6 "const_int_operand" " i, i")
3756 (match_operand 7 "const_int_operand" " i, i")
3757 (match_operand 8 "const_int_operand" " i, i")
3758 (reg:SI VL_REGNUM)
3759 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3760 (any_widen_binop:VWEXTI
3761 (any_extend:VWEXTI
3762 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3763 (any_extend:VWEXTI
3764 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3765 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3766 "TARGET_VECTOR"
3767 "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
3768 [(set_attr "type" "vi<widen_binop_insn_type>")
3769 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3770
3771 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
3772 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3773 (if_then_else:VWEXTI
3774 (unspec:<VM>
3775 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3776 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3777 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3778 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3779 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3780 (reg:SI VL_REGNUM)
3781 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3782 (any_widen_binop:VWEXTI
3783 (any_extend:VWEXTI
3784 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3785 (any_extend:VWEXTI
3786 (vec_duplicate:<V_DOUBLE_TRUNC>
3787 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ"))))
3788 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3789 "TARGET_VECTOR"
3790 "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
3791 [(set_attr "type" "vi<widen_binop_insn_type>")
3792 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3793 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3794
3795 (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
3796 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
3797 (if_then_else:VWEXTI
3798 (unspec:<VM>
3799 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
3800 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3801 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3802 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3803 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3804 (reg:SI VL_REGNUM)
3805 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3806 (minus:VWEXTI
3807 (match_operand:VWEXTI 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr")
3808 (any_extend:VWEXTI
3809 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr")))
3810 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
3811 "TARGET_VECTOR"
3812 "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
3813 [(set_attr "type" "viwalu")
3814 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3815 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
3816
3817 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
3818 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
3819 (if_then_else:VWEXTI
3820 (unspec:<VM>
3821 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
3822 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3823 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3824 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3825 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3826 (reg:SI VL_REGNUM)
3827 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3828 (plus:VWEXTI
3829 (any_extend:VWEXTI
3830 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr"))
3831 (match_operand:VWEXTI 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr"))
3832 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
3833 "TARGET_VECTOR"
3834 "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
3835 [(set_attr "type" "viwalu")
3836 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3837 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
3838
3839 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
3840 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
3841 (if_then_else:VWEXTI
3842 (unspec:<VM>
3843 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3844 (match_operand 5 "vector_length_operand" " rK, rK")
3845 (match_operand 6 "const_int_operand" " i, i")
3846 (match_operand 7 "const_int_operand" " i, i")
3847 (match_operand 8 "const_int_operand" " i, i")
3848 (reg:SI VL_REGNUM)
3849 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3850 (plus_minus:VWEXTI
3851 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3852 (any_extend:VWEXTI
3853 (vec_duplicate:<V_DOUBLE_TRUNC>
3854 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3855 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3856 "TARGET_VECTOR"
3857 "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
3858 [(set_attr "type" "vi<widen_binop_insn_type>")
3859 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3860
3861 (define_insn "@pred_widen_mulsu<mode>"
3862 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3863 (if_then_else:VWEXTI
3864 (unspec:<VM>
3865 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3866 (match_operand 5 "vector_length_operand" " rK, rK")
3867 (match_operand 6 "const_int_operand" " i, i")
3868 (match_operand 7 "const_int_operand" " i, i")
3869 (match_operand 8 "const_int_operand" " i, i")
3870 (reg:SI VL_REGNUM)
3871 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3872 (mult:VWEXTI
3873 (sign_extend:VWEXTI
3874 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3875 (zero_extend:VWEXTI
3876 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3877 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3878 "TARGET_VECTOR"
3879 "vwmulsu.vv\t%0,%3,%4%p1"
3880 [(set_attr "type" "viwmul")
3881 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3882
3883 (define_insn "@pred_widen_mulsu<mode>_scalar"
3884 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3885 (if_then_else:VWEXTI
3886 (unspec:<VM>
3887 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3888 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3889 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3890 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3891 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3892 (reg:SI VL_REGNUM)
3893 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3894 (mult:VWEXTI
3895 (sign_extend:VWEXTI
3896 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3897 (zero_extend:VWEXTI
3898 (vec_duplicate:<V_DOUBLE_TRUNC>
3899 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ"))))
3900 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3901 "TARGET_VECTOR"
3902 "vwmulsu.vx\t%0,%3,%z4%p1"
3903 [(set_attr "type" "viwmul")
3904 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3905 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3906
3907 ;; vwcvt<u>.x.x.v
3908 (define_insn "@pred_<optab><mode>"
3909 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3910 (if_then_else:VWEXTI
3911 (unspec:<VM>
3912 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3913 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3914 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3915 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3916 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3917 (reg:SI VL_REGNUM)
3918 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3919 (plus:VWEXTI
3920 (any_extend:VWEXTI
3921 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3922 (vec_duplicate:VWEXTI
3923 (reg:<VEL> X0_REGNUM)))
3924 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3925 "TARGET_VECTOR"
3926 "vwcvt<u>.x.x.v\t%0,%3%p1"
3927 [(set_attr "type" "viwalu")
3928 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3929 (set_attr "vl_op_idx" "4")
3930 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3931 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3932 (set (attr "avl_type_idx") (const_int 7))
3933 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3934
3935 ;; -------------------------------------------------------------------------------
3936 ;; ---- Predicated integer Narrowing operations
3937 ;; -------------------------------------------------------------------------------
3938 ;; Includes:
3939 ;; - 11.7 Vector Narrowing Integer Right Shift Instructions
3940 ;; -------------------------------------------------------------------------------
3941
3942 ;; The destination EEW is smaller than the source EEW and the overlap is in the
3943 ;; lowest-numbered part of the source register group
3944 ;; e.g, when LMUL = 1, vnsrl.wi v0,v0,3 is legal but a destination of v1 is not.
3945 (define_insn "@pred_narrow_<optab><mode>"
3946 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
3947 (if_then_else:<V_DOUBLE_TRUNC>
3948 (unspec:<VM>
3949 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
3950 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
3951 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3952 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3953 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3954 (reg:SI VL_REGNUM)
3955 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3956 (truncate:<V_DOUBLE_TRUNC>
3957 (any_shiftrt:VWEXTI
3958 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
3959 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")))
3960 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
3961 "TARGET_VECTOR"
3962 "vn<insn>.w%o4\t%0,%3,%v4%p1"
3963 [(set_attr "type" "vnshift")
3964 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3965
3966 (define_insn "@pred_narrow_<optab><mode>_scalar"
3967 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
3968 (if_then_else:<V_DOUBLE_TRUNC>
3969 (unspec:<VM>
3970 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
3971 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3972 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3973 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3974 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
3975 (reg:SI VL_REGNUM)
3976 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3977 (truncate:<V_DOUBLE_TRUNC>
3978 (any_shiftrt:VWEXTI
3979 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
3980 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
3981 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
3982 "TARGET_VECTOR"
3983 "vn<insn>.w%o4\t%0,%3,%4%p1"
3984 [(set_attr "type" "vnshift")
3985 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3986
3987 ;; vncvt.x.x.w
3988 (define_insn "@pred_trunc<mode>"
3989 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
3990 (if_then_else:<V_DOUBLE_TRUNC>
3991 (unspec:<VM>
3992 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
3993 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3994 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
3995 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3996 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3997 (reg:SI VL_REGNUM)
3998 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3999 (truncate:<V_DOUBLE_TRUNC>
4000 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
4001 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4002 "TARGET_VECTOR"
4003 "vncvt.x.x.w\t%0,%3%p1"
4004 [(set_attr "type" "vnshift")
4005 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4006 (set_attr "vl_op_idx" "4")
4007 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4008 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4009 (set (attr "avl_type_idx") (const_int 7))])
4010
4011 ;; -------------------------------------------------------------------------------
4012 ;; ---- Predicated fixed-point operations
4013 ;; -------------------------------------------------------------------------------
4014 ;; Includes:
4015 ;; - 12.1 Vector Single-Width Saturating Add and Subtract
4016 ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract
4017 ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
4018 ;; - 12.4 Vector Single-Width Scaling Shift Instructions
4019 ;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
4020 ;; -------------------------------------------------------------------------------
4021
4022 ;; Saturating Add and Subtract
4023 (define_insn "@pred_<optab><mode>"
4024 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
4025 (if_then_else:VI
4026 (unspec:<VM>
4027 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
4028 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4029 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
4030 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4031 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4032 (reg:SI VL_REGNUM)
4033 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4034 (any_sat_int_binop:VI
4035 (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
4036 (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
4037 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4038 "TARGET_VECTOR"
4039 "@
4040 v<insn>.vv\t%0,%3,%4%p1
4041 v<insn>.vv\t%0,%3,%4%p1
4042 v<insn>.vv\t%0,%3,%4%p1
4043 v<insn>.vv\t%0,%3,%4%p1
4044 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4045 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4046 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4047 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
4048 [(set_attr "type" "<int_binop_insn_type>")
4049 (set_attr "mode" "<MODE>")])
4050
4051 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4052 (define_insn "@pred_<optab><mode>_scalar"
4053 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4054 (if_then_else:VI_QHS
4055 (unspec:<VM>
4056 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4057 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4058 (match_operand 6 "const_int_operand" " i, i, i, i")
4059 (match_operand 7 "const_int_operand" " i, i, i, i")
4060 (match_operand 8 "const_int_operand" " i, i, i, i")
4061 (reg:SI VL_REGNUM)
4062 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4063 (sat_int_plus_binop:VI_QHS
4064 (vec_duplicate:VI_QHS
4065 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4066 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr"))
4067 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4068 "TARGET_VECTOR"
4069 "v<insn>.vx\t%0,%3,%4%p1"
4070 [(set_attr "type" "<int_binop_insn_type>")
4071 (set_attr "mode" "<MODE>")])
4072
4073 (define_insn "@pred_<optab><mode>_scalar"
4074 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4075 (if_then_else:VI_QHS
4076 (unspec:<VM>
4077 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4078 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4079 (match_operand 6 "const_int_operand" " i, i, i, i")
4080 (match_operand 7 "const_int_operand" " i, i, i, i")
4081 (match_operand 8 "const_int_operand" " i, i, i, i")
4082 (reg:SI VL_REGNUM)
4083 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4084 (sat_int_minus_binop:VI_QHS
4085 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4086 (vec_duplicate:VI_QHS
4087 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4088 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4089 "TARGET_VECTOR"
4090 "v<insn>.vx\t%0,%3,%4%p1"
4091 [(set_attr "type" "<int_binop_insn_type>")
4092 (set_attr "mode" "<MODE>")])
4093
4094 (define_expand "@pred_<optab><mode>_scalar"
4095 [(set (match_operand:VI_D 0 "register_operand")
4096 (if_then_else:VI_D
4097 (unspec:<VM>
4098 [(match_operand:<VM> 1 "vector_mask_operand")
4099 (match_operand 5 "vector_length_operand")
4100 (match_operand 6 "const_int_operand")
4101 (match_operand 7 "const_int_operand")
4102 (match_operand 8 "const_int_operand")
4103 (reg:SI VL_REGNUM)
4104 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4105 (sat_int_plus_binop:VI_D
4106 (vec_duplicate:VI_D
4107 (match_operand:<VEL> 4 "reg_or_int_operand"))
4108 (match_operand:VI_D 3 "register_operand"))
4109 (match_operand:VI_D 2 "vector_merge_operand")))]
4110 "TARGET_VECTOR"
4111 {
4112 if (riscv_vector::sew64_scalar_helper (
4113 operands,
4114 /* scalar op */&operands[4],
4115 /* vl */operands[5],
4116 <MODE>mode,
4117 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4118 [] (rtx *operands, rtx boardcast_scalar) {
4119 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4120 operands[2], operands[3], boardcast_scalar, operands[5],
4121 operands[6], operands[7], operands[8]));
4122 },
4123 (riscv_vector::avl_type) INTVAL (operands[8])))
4124 DONE;
4125 })
4126
4127 (define_insn "*pred_<optab><mode>_scalar"
4128 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4129 (if_then_else:VI_D
4130 (unspec:<VM>
4131 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4132 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4133 (match_operand 6 "const_int_operand" " i, i, i, i")
4134 (match_operand 7 "const_int_operand" " i, i, i, i")
4135 (match_operand 8 "const_int_operand" " i, i, i, i")
4136 (reg:SI VL_REGNUM)
4137 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4138 (sat_int_plus_binop:VI_D
4139 (vec_duplicate:VI_D
4140 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4141 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4142 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4143 "TARGET_VECTOR"
4144 "v<insn>.vx\t%0,%3,%4%p1"
4145 [(set_attr "type" "<int_binop_insn_type>")
4146 (set_attr "mode" "<MODE>")])
4147
4148 (define_insn "*pred_<optab><mode>_extended_scalar"
4149 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4150 (if_then_else:VI_D
4151 (unspec:<VM>
4152 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4153 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4154 (match_operand 6 "const_int_operand" " i, i, i, i")
4155 (match_operand 7 "const_int_operand" " i, i, i, i")
4156 (match_operand 8 "const_int_operand" " i, i, i, i")
4157 (reg:SI VL_REGNUM)
4158 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4159 (sat_int_plus_binop:VI_D
4160 (vec_duplicate:VI_D
4161 (sign_extend:<VEL>
4162 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))
4163 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4164 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4165 "TARGET_VECTOR && !TARGET_64BIT"
4166 "v<insn>.vx\t%0,%3,%4%p1"
4167 [(set_attr "type" "<int_binop_insn_type>")
4168 (set_attr "mode" "<MODE>")])
4169
4170 (define_expand "@pred_<optab><mode>_scalar"
4171 [(set (match_operand:VI_D 0 "register_operand")
4172 (if_then_else:VI_D
4173 (unspec:<VM>
4174 [(match_operand:<VM> 1 "vector_mask_operand")
4175 (match_operand 5 "vector_length_operand")
4176 (match_operand 6 "const_int_operand")
4177 (match_operand 7 "const_int_operand")
4178 (match_operand 8 "const_int_operand")
4179 (reg:SI VL_REGNUM)
4180 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4181 (sat_int_minus_binop:VI_D
4182 (match_operand:VI_D 3 "register_operand")
4183 (vec_duplicate:VI_D
4184 (match_operand:<VEL> 4 "reg_or_int_operand")))
4185 (match_operand:VI_D 2 "vector_merge_operand")))]
4186 "TARGET_VECTOR"
4187 {
4188 if (riscv_vector::sew64_scalar_helper (
4189 operands,
4190 /* scalar op */&operands[4],
4191 /* vl */operands[5],
4192 <MODE>mode,
4193 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4194 [] (rtx *operands, rtx boardcast_scalar) {
4195 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4196 operands[2], operands[3], boardcast_scalar, operands[5],
4197 operands[6], operands[7], operands[8]));
4198 },
4199 (riscv_vector::avl_type) INTVAL (operands[8])))
4200 DONE;
4201 })
4202
4203 (define_insn "*pred_<optab><mode>_scalar"
4204 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4205 (if_then_else:VI_D
4206 (unspec:<VM>
4207 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4208 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4209 (match_operand 6 "const_int_operand" " i, i, i, i")
4210 (match_operand 7 "const_int_operand" " i, i, i, i")
4211 (match_operand 8 "const_int_operand" " i, i, i, i")
4212 (reg:SI VL_REGNUM)
4213 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4214 (sat_int_minus_binop:VI_D
4215 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4216 (vec_duplicate:VI_D
4217 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4218 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4219 "TARGET_VECTOR"
4220 "v<insn>.vx\t%0,%3,%4%p1"
4221 [(set_attr "type" "<int_binop_insn_type>")
4222 (set_attr "mode" "<MODE>")])
4223
4224 (define_insn "*pred_<optab><mode>_extended_scalar"
4225 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4226 (if_then_else:VI_D
4227 (unspec:<VM>
4228 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4229 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4230 (match_operand 6 "const_int_operand" " i, i, i, i")
4231 (match_operand 7 "const_int_operand" " i, i, i, i")
4232 (match_operand 8 "const_int_operand" " i, i, i, i")
4233 (reg:SI VL_REGNUM)
4234 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4235 (sat_int_minus_binop:VI_D
4236 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4237 (vec_duplicate:VI_D
4238 (sign_extend:<VEL>
4239 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r"))))
4240 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4241 "TARGET_VECTOR && !TARGET_64BIT"
4242 "v<insn>.vx\t%0,%3,%4%p1"
4243 [(set_attr "type" "<int_binop_insn_type>")
4244 (set_attr "mode" "<MODE>")])
4245
4246 (define_insn "@pred_<sat_op><mode>"
4247 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr")
4248 (if_then_else:VI
4249 (unspec:<VM>
4250 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4251 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4252 (match_operand 6 "const_int_operand" " i, i, i, i")
4253 (match_operand 7 "const_int_operand" " i, i, i, i")
4254 (match_operand 8 "const_int_operand" " i, i, i, i")
4255 (match_operand 9 "const_int_operand" " i, i, i, i")
4256 (reg:SI VL_REGNUM)
4257 (reg:SI VTYPE_REGNUM)
4258 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4259 (unspec:VI
4260 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4261 (match_operand:VI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
4262 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4263 "TARGET_VECTOR"
4264 "v<sat_op>.vv\t%0,%3,%4%p1"
4265 [(set_attr "type" "<sat_insn_type>")
4266 (set_attr "mode" "<MODE>")])
4267
4268 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4269 (define_insn "@pred_<sat_op><mode>_scalar"
4270 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr, vd, vr")
4271 (if_then_else:VI_QHS
4272 (unspec:<VM>
4273 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4274 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4275 (match_operand 6 "const_int_operand" " i, i, i, i")
4276 (match_operand 7 "const_int_operand" " i, i, i, i")
4277 (match_operand 8 "const_int_operand" " i, i, i, i")
4278 (match_operand 9 "const_int_operand" " i, i, i, i")
4279 (reg:SI VL_REGNUM)
4280 (reg:SI VTYPE_REGNUM)
4281 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4282 (unspec:VI_QHS
4283 [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4284 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4285 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4286 "TARGET_VECTOR"
4287 "v<sat_op>.vx\t%0,%3,%z4%p1"
4288 [(set_attr "type" "<sat_insn_type>")
4289 (set_attr "mode" "<MODE>")])
4290
4291 (define_insn "@pred_<sat_op><mode>_scalar"
4292 [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
4293 (if_then_else:VI
4294 (unspec:<VM>
4295 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4296 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4297 (match_operand 6 "const_int_operand" " i, i, i, i")
4298 (match_operand 7 "const_int_operand" " i, i, i, i")
4299 (match_operand 8 "const_int_operand" " i, i, i, i")
4300 (match_operand 9 "const_int_operand" " i, i, i, i")
4301 (reg:SI VL_REGNUM)
4302 (reg:SI VTYPE_REGNUM)
4303 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4304 (unspec:VI
4305 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4306 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
4307 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4308 "TARGET_VECTOR"
4309 "v<sat_op>.v%o4\t%0,%3,%4%p1"
4310 [(set_attr "type" "<sat_insn_type>")
4311 (set_attr "mode" "<MODE>")])
4312
4313 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4314 ;; we need to deal with SEW = 64 in RV32 system.
4315 (define_expand "@pred_<sat_op><mode>_scalar"
4316 [(set (match_operand:VI_D 0 "register_operand")
4317 (if_then_else:VI_D
4318 (unspec:<VM>
4319 [(match_operand:<VM> 1 "vector_mask_operand")
4320 (match_operand 5 "vector_length_operand")
4321 (match_operand 6 "const_int_operand")
4322 (match_operand 7 "const_int_operand")
4323 (match_operand 8 "const_int_operand")
4324 (match_operand 9 "const_int_operand")
4325 (reg:SI VL_REGNUM)
4326 (reg:SI VTYPE_REGNUM)
4327 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4328 (unspec:VI_D
4329 [(match_operand:VI_D 3 "register_operand")
4330 (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
4331 (match_operand:VI_D 2 "vector_merge_operand")))]
4332 "TARGET_VECTOR"
4333 {
4334 if (riscv_vector::sew64_scalar_helper (
4335 operands,
4336 /* scalar op */&operands[4],
4337 /* vl */operands[5],
4338 <MODE>mode,
4339 false,
4340 [] (rtx *operands, rtx boardcast_scalar) {
4341 emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
4342 operands[2], operands[3], boardcast_scalar, operands[5],
4343 operands[6], operands[7], operands[8], operands[9]));
4344 },
4345 (riscv_vector::avl_type) INTVAL (operands[8])))
4346 DONE;
4347 })
4348
4349 (define_insn "*pred_<sat_op><mode>_scalar"
4350 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4351 (if_then_else:VI_D
4352 (unspec:<VM>
4353 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4354 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4355 (match_operand 6 "const_int_operand" " i, i, i, i")
4356 (match_operand 7 "const_int_operand" " i, i, i, i")
4357 (match_operand 8 "const_int_operand" " i, i, i, i")
4358 (match_operand 9 "const_int_operand" " i, i, i, i")
4359 (reg:SI VL_REGNUM)
4360 (reg:SI VTYPE_REGNUM)
4361 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4362 (unspec:VI_D
4363 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4364 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4365 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4366 "TARGET_VECTOR"
4367 "v<sat_op>.vx\t%0,%3,%z4%p1"
4368 [(set_attr "type" "<sat_insn_type>")
4369 (set_attr "mode" "<MODE>")])
4370
4371 (define_insn "*pred_<sat_op><mode>_extended_scalar"
4372 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4373 (if_then_else:VI_D
4374 (unspec:<VM>
4375 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4376 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4377 (match_operand 6 "const_int_operand" " i, i, i, i")
4378 (match_operand 7 "const_int_operand" " i, i, i, i")
4379 (match_operand 8 "const_int_operand" " i, i, i, i")
4380 (match_operand 9 "const_int_operand" " i, i, i, i")
4381 (reg:SI VL_REGNUM)
4382 (reg:SI VTYPE_REGNUM)
4383 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4384 (unspec:VI_D
4385 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4386 (sign_extend:<VEL>
4387 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
4388 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4389 "TARGET_VECTOR && !TARGET_64BIT"
4390 "v<sat_op>.vx\t%0,%3,%z4%p1"
4391 [(set_attr "type" "<sat_insn_type>")
4392 (set_attr "mode" "<MODE>")])
4393
4394 ;; CLIP
4395 (define_insn "@pred_narrow_clip<v_su><mode>"
4396 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4397 (if_then_else:<V_DOUBLE_TRUNC>
4398 (unspec:<VM>
4399 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4400 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4401 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4402 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4403 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4404 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4405 (reg:SI VL_REGNUM)
4406 (reg:SI VTYPE_REGNUM)
4407 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4408 (unspec:<V_DOUBLE_TRUNC>
4409 [(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4410 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
4411 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4412 "TARGET_VECTOR"
4413 "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
4414 [(set_attr "type" "vnclip")
4415 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4416
4417 (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
4418 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4419 (if_then_else:<V_DOUBLE_TRUNC>
4420 (unspec:<VM>
4421 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4422 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4423 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4424 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4425 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4426 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
4427 (reg:SI VL_REGNUM)
4428 (reg:SI VTYPE_REGNUM)
4429 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4430 (unspec:<V_DOUBLE_TRUNC>
4431 [(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4432 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
4433 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4434 "TARGET_VECTOR"
4435 "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
4436 [(set_attr "type" "vnclip")
4437 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4438
4439 ;; -------------------------------------------------------------------------------
4440 ;; ---- Predicated integer comparison operations
4441 ;; -------------------------------------------------------------------------------
4442 ;; Includes:
4443 ;; - 11.8 Vector Integer Comparision Instructions
4444 ;; -------------------------------------------------------------------------------
4445
4446 (define_expand "@pred_cmp<mode>"
4447 [(set (match_operand:<VM> 0 "register_operand")
4448 (if_then_else:<VM>
4449 (unspec:<VM>
4450 [(match_operand:<VM> 1 "vector_mask_operand")
4451 (match_operand 6 "vector_length_operand")
4452 (match_operand 7 "const_int_operand")
4453 (match_operand 8 "const_int_operand")
4454 (reg:SI VL_REGNUM)
4455 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4456 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4457 [(match_operand:V_VLSI 4 "register_operand")
4458 (match_operand:V_VLSI 5 "vector_arith_operand")])
4459 (match_operand:<VM> 2 "vector_merge_operand")))]
4460 "TARGET_VECTOR"
4461 {})
4462
4463 (define_insn "*pred_cmp<mode>_merge_tie_mask"
4464 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4465 (if_then_else:<VM>
4466 (unspec:<VM>
4467 [(match_operand:<VM> 1 "register_operand" " 0")
4468 (match_operand 5 "vector_length_operand" " rK")
4469 (match_operand 6 "const_int_operand" " i")
4470 (match_operand 7 "const_int_operand" " i")
4471 (reg:SI VL_REGNUM)
4472 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4473 (match_operator:<VM> 2 "comparison_except_ltge_operator"
4474 [(match_operand:V_VLSI 3 "register_operand" " vr")
4475 (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")])
4476 (match_dup 1)))]
4477 "TARGET_VECTOR"
4478 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4479 [(set_attr "type" "vicmp")
4480 (set_attr "mode" "<MODE>")
4481 (set_attr "merge_op_idx" "1")
4482 (set_attr "vl_op_idx" "5")
4483 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4484 (set (attr "avl_type_idx") (const_int 7))])
4485
4486 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4487 (define_insn "*pred_cmp<mode>"
4488 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
4489 (if_then_else:<VM>
4490 (unspec:<VM>
4491 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4492 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4493 (match_operand 7 "const_int_operand" " i, i, i, i")
4494 (match_operand 8 "const_int_operand" " i, i, i, i")
4495 (reg:SI VL_REGNUM)
4496 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4497 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4498 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
4499 (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")])
4500 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4501 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4502 "vms%B3.v%o5\t%0,%4,%v5%p1"
4503 [(set_attr "type" "vicmp")
4504 (set_attr "mode" "<MODE>")])
4505
4506 ;; We use early-clobber for source LMUL > dest LMUL.
4507 (define_insn "*pred_cmp<mode>_narrow"
4508 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4509 (if_then_else:<VM>
4510 (unspec:<VM>
4511 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4512 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4513 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4514 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4515 (reg:SI VL_REGNUM)
4516 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4517 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4518 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4519 (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")])
4520 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4521 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4522 "vms%B3.v%o5\t%0,%4,%v5%p1"
4523 [(set_attr "type" "vicmp")
4524 (set_attr "mode" "<MODE>")])
4525
4526 (define_expand "@pred_ltge<mode>"
4527 [(set (match_operand:<VM> 0 "register_operand")
4528 (if_then_else:<VM>
4529 (unspec:<VM>
4530 [(match_operand:<VM> 1 "vector_mask_operand")
4531 (match_operand 6 "vector_length_operand")
4532 (match_operand 7 "const_int_operand")
4533 (match_operand 8 "const_int_operand")
4534 (reg:SI VL_REGNUM)
4535 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4536 (match_operator:<VM> 3 "ltge_operator"
4537 [(match_operand:V_VLSI 4 "register_operand")
4538 (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
4539 (match_operand:<VM> 2 "vector_merge_operand")))]
4540 "TARGET_VECTOR"
4541 {})
4542
4543 (define_insn "*pred_ltge<mode>_merge_tie_mask"
4544 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4545 (if_then_else:<VM>
4546 (unspec:<VM>
4547 [(match_operand:<VM> 1 "register_operand" " 0")
4548 (match_operand 5 "vector_length_operand" " rK")
4549 (match_operand 6 "const_int_operand" " i")
4550 (match_operand 7 "const_int_operand" " i")
4551 (reg:SI VL_REGNUM)
4552 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4553 (match_operator:<VM> 2 "ltge_operator"
4554 [(match_operand:V_VLSI 3 "register_operand" " vr")
4555 (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
4556 (match_dup 1)))]
4557 "TARGET_VECTOR"
4558 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4559 [(set_attr "type" "vicmp")
4560 (set_attr "mode" "<MODE>")
4561 (set_attr "merge_op_idx" "1")
4562 (set_attr "vl_op_idx" "5")
4563 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4564 (set (attr "avl_type_idx") (const_int 7))])
4565
4566 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4567 (define_insn "*pred_ltge<mode>"
4568 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
4569 (if_then_else:<VM>
4570 (unspec:<VM>
4571 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4572 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4573 (match_operand 7 "const_int_operand" " i, i, i, i")
4574 (match_operand 8 "const_int_operand" " i, i, i, i")
4575 (reg:SI VL_REGNUM)
4576 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4577 (match_operator:<VM> 3 "ltge_operator"
4578 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
4579 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")])
4580 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4581 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4582 "vms%B3.v%o5\t%0,%4,%v5%p1"
4583 [(set_attr "type" "vicmp")
4584 (set_attr "mode" "<MODE>")])
4585
4586 ;; We use early-clobber for source LMUL > dest LMUL.
4587 (define_insn "*pred_ltge<mode>_narrow"
4588 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4589 (if_then_else:<VM>
4590 (unspec:<VM>
4591 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4592 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4593 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4594 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4595 (reg:SI VL_REGNUM)
4596 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4597 (match_operator:<VM> 3 "ltge_operator"
4598 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4599 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")])
4600 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4601 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4602 "vms%B3.v%o5\t%0,%4,%v5%p1"
4603 [(set_attr "type" "vicmp")
4604 (set_attr "mode" "<MODE>")])
4605
4606 (define_expand "@pred_cmp<mode>_scalar"
4607 [(set (match_operand:<VM> 0 "register_operand")
4608 (if_then_else:<VM>
4609 (unspec:<VM>
4610 [(match_operand:<VM> 1 "vector_mask_operand")
4611 (match_operand 6 "vector_length_operand")
4612 (match_operand 7 "const_int_operand")
4613 (match_operand 8 "const_int_operand")
4614 (reg:SI VL_REGNUM)
4615 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4616 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4617 [(match_operand:V_VLSI_QHS 4 "register_operand")
4618 (vec_duplicate:V_VLSI_QHS
4619 (match_operand:<VEL> 5 "register_operand"))])
4620 (match_operand:<VM> 2 "vector_merge_operand")))]
4621 "TARGET_VECTOR"
4622 {})
4623
4624 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4625 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4626 (if_then_else:<VM>
4627 (unspec:<VM>
4628 [(match_operand:<VM> 1 "register_operand" " 0")
4629 (match_operand 5 "vector_length_operand" " rK")
4630 (match_operand 6 "const_int_operand" " i")
4631 (match_operand 7 "const_int_operand" " i")
4632 (reg:SI VL_REGNUM)
4633 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4634 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4635 [(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
4636 (vec_duplicate:V_VLSI_QHS
4637 (match_operand:<VEL> 4 "register_operand" " r"))])
4638 (match_dup 1)))]
4639 "TARGET_VECTOR"
4640 "vms%B2.vx\t%0,%3,%4,v0.t"
4641 [(set_attr "type" "vicmp")
4642 (set_attr "mode" "<MODE>")
4643 (set_attr "merge_op_idx" "1")
4644 (set_attr "vl_op_idx" "5")
4645 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4646 (set (attr "avl_type_idx") (const_int 7))])
4647
4648 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4649 (define_insn "*pred_cmp<mode>_scalar"
4650 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4651 (if_then_else:<VM>
4652 (unspec:<VM>
4653 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4654 (match_operand 6 "vector_length_operand" " rK, rK")
4655 (match_operand 7 "const_int_operand" " i, i")
4656 (match_operand 8 "const_int_operand" " i, i")
4657 (reg:SI VL_REGNUM)
4658 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4659 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4660 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")
4661 (vec_duplicate:V_VLSI_QHS
4662 (match_operand:<VEL> 5 "register_operand" " r, r"))])
4663 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4664 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4665 "vms%B3.vx\t%0,%4,%5%p1"
4666 [(set_attr "type" "vicmp")
4667 (set_attr "mode" "<MODE>")])
4668
4669 ;; We use early-clobber for source LMUL > dest LMUL.
4670 (define_insn "*pred_cmp<mode>_scalar_narrow"
4671 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4672 (if_then_else:<VM>
4673 (unspec:<VM>
4674 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4675 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4676 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4677 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4678 (reg:SI VL_REGNUM)
4679 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4680 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4681 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
4682 (vec_duplicate:V_VLSI_QHS
4683 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4684 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4685 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4686 "vms%B3.vx\t%0,%4,%5%p1"
4687 [(set_attr "type" "vicmp")
4688 (set_attr "mode" "<MODE>")])
4689
4690 (define_expand "@pred_eqne<mode>_scalar"
4691 [(set (match_operand:<VM> 0 "register_operand")
4692 (if_then_else:<VM>
4693 (unspec:<VM>
4694 [(match_operand:<VM> 1 "vector_mask_operand")
4695 (match_operand 6 "vector_length_operand")
4696 (match_operand 7 "const_int_operand")
4697 (match_operand 8 "const_int_operand")
4698 (reg:SI VL_REGNUM)
4699 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4700 (match_operator:<VM> 3 "equality_operator"
4701 [(vec_duplicate:V_VLSI_QHS
4702 (match_operand:<VEL> 5 "register_operand"))
4703 (match_operand:V_VLSI_QHS 4 "register_operand")])
4704 (match_operand:<VM> 2 "vector_merge_operand")))]
4705 "TARGET_VECTOR"
4706 {})
4707
4708 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4709 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4710 (if_then_else:<VM>
4711 (unspec:<VM>
4712 [(match_operand:<VM> 1 "register_operand" " 0")
4713 (match_operand 5 "vector_length_operand" " rK")
4714 (match_operand 6 "const_int_operand" " i")
4715 (match_operand 7 "const_int_operand" " i")
4716 (reg:SI VL_REGNUM)
4717 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4718 (match_operator:<VM> 2 "equality_operator"
4719 [(vec_duplicate:V_VLSI_QHS
4720 (match_operand:<VEL> 4 "register_operand" " r"))
4721 (match_operand:V_VLSI_QHS 3 "register_operand" " vr")])
4722 (match_dup 1)))]
4723 "TARGET_VECTOR"
4724 "vms%B2.vx\t%0,%3,%4,v0.t"
4725 [(set_attr "type" "vicmp")
4726 (set_attr "mode" "<MODE>")
4727 (set_attr "merge_op_idx" "1")
4728 (set_attr "vl_op_idx" "5")
4729 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4730 (set (attr "avl_type_idx") (const_int 7))])
4731
4732 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4733 (define_insn "*pred_eqne<mode>_scalar"
4734 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4735 (if_then_else:<VM>
4736 (unspec:<VM>
4737 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4738 (match_operand 6 "vector_length_operand" " rK, rK")
4739 (match_operand 7 "const_int_operand" " i, i")
4740 (match_operand 8 "const_int_operand" " i, i")
4741 (reg:SI VL_REGNUM)
4742 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4743 (match_operator:<VM> 3 "equality_operator"
4744 [(vec_duplicate:V_VLSI_QHS
4745 (match_operand:<VEL> 5 "register_operand" " r, r"))
4746 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")])
4747 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4748 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4749 "vms%B3.vx\t%0,%4,%5%p1"
4750 [(set_attr "type" "vicmp")
4751 (set_attr "mode" "<MODE>")])
4752
4753 ;; We use early-clobber for source LMUL > dest LMUL.
4754 (define_insn "*pred_eqne<mode>_scalar_narrow"
4755 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4756 (if_then_else:<VM>
4757 (unspec:<VM>
4758 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4759 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4760 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4761 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4762 (reg:SI VL_REGNUM)
4763 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4764 (match_operator:<VM> 3 "equality_operator"
4765 [(vec_duplicate:V_VLSI_QHS
4766 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4767 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")])
4768 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4769 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4770 "vms%B3.vx\t%0,%4,%5%p1"
4771 [(set_attr "type" "vicmp")
4772 (set_attr "mode" "<MODE>")])
4773
4774 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4775 ;; we need to deal with SEW = 64 in RV32 system.
4776 (define_expand "@pred_cmp<mode>_scalar"
4777 [(set (match_operand:<VM> 0 "register_operand")
4778 (if_then_else:<VM>
4779 (unspec:<VM>
4780 [(match_operand:<VM> 1 "vector_mask_operand")
4781 (match_operand 6 "vector_length_operand")
4782 (match_operand 7 "const_int_operand")
4783 (match_operand 8 "const_int_operand")
4784 (reg:SI VL_REGNUM)
4785 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4786 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4787 [(match_operand:V_VLSI_D 4 "register_operand")
4788 (vec_duplicate:V_VLSI_D
4789 (match_operand:<VEL> 5 "reg_or_int_operand"))])
4790 (match_operand:<VM> 2 "vector_merge_operand")))]
4791 "TARGET_VECTOR"
4792 {
4793 enum rtx_code code = GET_CODE (operands[3]);
4794 if (riscv_vector::sew64_scalar_helper (
4795 operands,
4796 /* scalar op */&operands[5],
4797 /* vl */operands[6],
4798 <MODE>mode,
4799 riscv_vector::has_vi_variant_p (code, operands[5]),
4800 code == LT || code == LTU ?
4801 [] (rtx *operands, rtx boardcast_scalar) {
4802 emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
4803 operands[2], operands[3], operands[4], boardcast_scalar,
4804 operands[6], operands[7], operands[8]));
4805 }
4806 :
4807 [] (rtx *operands, rtx boardcast_scalar) {
4808 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4809 operands[2], operands[3], operands[4], boardcast_scalar,
4810 operands[6], operands[7], operands[8]));
4811 },
4812 (riscv_vector::avl_type) INTVAL (operands[8])))
4813 DONE;
4814 })
4815
4816 (define_expand "@pred_eqne<mode>_scalar"
4817 [(set (match_operand:<VM> 0 "register_operand")
4818 (if_then_else:<VM>
4819 (unspec:<VM>
4820 [(match_operand:<VM> 1 "vector_mask_operand")
4821 (match_operand 6 "vector_length_operand")
4822 (match_operand 7 "const_int_operand")
4823 (match_operand 8 "const_int_operand")
4824 (reg:SI VL_REGNUM)
4825 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4826 (match_operator:<VM> 3 "equality_operator"
4827 [(vec_duplicate:V_VLSI_D
4828 (match_operand:<VEL> 5 "reg_or_int_operand"))
4829 (match_operand:V_VLSI_D 4 "register_operand")])
4830 (match_operand:<VM> 2 "vector_merge_operand")))]
4831 "TARGET_VECTOR"
4832 {
4833 enum rtx_code code = GET_CODE (operands[3]);
4834 if (riscv_vector::sew64_scalar_helper (
4835 operands,
4836 /* scalar op */&operands[5],
4837 /* vl */operands[6],
4838 <MODE>mode,
4839 riscv_vector::has_vi_variant_p (code, operands[5]),
4840 [] (rtx *operands, rtx boardcast_scalar) {
4841 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4842 operands[2], operands[3], operands[4], boardcast_scalar,
4843 operands[6], operands[7], operands[8]));
4844 },
4845 (riscv_vector::avl_type) INTVAL (operands[8])))
4846 DONE;
4847 })
4848
4849 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4850 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4851 (if_then_else:<VM>
4852 (unspec:<VM>
4853 [(match_operand:<VM> 1 "register_operand" " 0")
4854 (match_operand 5 "vector_length_operand" " rK")
4855 (match_operand 6 "const_int_operand" " i")
4856 (match_operand 7 "const_int_operand" " i")
4857 (reg:SI VL_REGNUM)
4858 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4859 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4860 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4861 (vec_duplicate:V_VLSI_D
4862 (match_operand:<VEL> 4 "register_operand" " r"))])
4863 (match_dup 1)))]
4864 "TARGET_VECTOR"
4865 "vms%B2.vx\t%0,%3,%4,v0.t"
4866 [(set_attr "type" "vicmp")
4867 (set_attr "mode" "<MODE>")
4868 (set_attr "merge_op_idx" "1")
4869 (set_attr "vl_op_idx" "5")
4870 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4871 (set (attr "avl_type_idx") (const_int 7))])
4872
4873 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4874 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4875 (if_then_else:<VM>
4876 (unspec:<VM>
4877 [(match_operand:<VM> 1 "register_operand" " 0")
4878 (match_operand 5 "vector_length_operand" " rK")
4879 (match_operand 6 "const_int_operand" " i")
4880 (match_operand 7 "const_int_operand" " i")
4881 (reg:SI VL_REGNUM)
4882 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4883 (match_operator:<VM> 2 "equality_operator"
4884 [(vec_duplicate:V_VLSI_D
4885 (match_operand:<VEL> 4 "register_operand" " r"))
4886 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
4887 (match_dup 1)))]
4888 "TARGET_VECTOR"
4889 "vms%B2.vx\t%0,%3,%4,v0.t"
4890 [(set_attr "type" "vicmp")
4891 (set_attr "mode" "<MODE>")
4892 (set_attr "merge_op_idx" "1")
4893 (set_attr "vl_op_idx" "5")
4894 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4895 (set (attr "avl_type_idx") (const_int 7))])
4896
4897 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4898 (define_insn "*pred_cmp<mode>_scalar"
4899 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4900 (if_then_else:<VM>
4901 (unspec:<VM>
4902 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4903 (match_operand 6 "vector_length_operand" " rK, rK")
4904 (match_operand 7 "const_int_operand" " i, i")
4905 (match_operand 8 "const_int_operand" " i, i")
4906 (reg:SI VL_REGNUM)
4907 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4908 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4909 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
4910 (vec_duplicate:V_VLSI_D
4911 (match_operand:<VEL> 5 "register_operand" " r, r"))])
4912 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4913 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4914 "vms%B3.vx\t%0,%4,%5%p1"
4915 [(set_attr "type" "vicmp")
4916 (set_attr "mode" "<MODE>")])
4917
4918 ;; We use early-clobber for source LMUL > dest LMUL.
4919 (define_insn "*pred_cmp<mode>_scalar_narrow"
4920 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4921 (if_then_else:<VM>
4922 (unspec:<VM>
4923 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4924 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4925 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4926 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4927 (reg:SI VL_REGNUM)
4928 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4929 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4930 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
4931 (vec_duplicate:V_VLSI_D
4932 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4933 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4934 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4935 "vms%B3.vx\t%0,%4,%5%p1"
4936 [(set_attr "type" "vicmp")
4937 (set_attr "mode" "<MODE>")])
4938
4939 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4940 (define_insn "*pred_eqne<mode>_scalar"
4941 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4942 (if_then_else:<VM>
4943 (unspec:<VM>
4944 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4945 (match_operand 6 "vector_length_operand" " rK, rK")
4946 (match_operand 7 "const_int_operand" " i, i")
4947 (match_operand 8 "const_int_operand" " i, i")
4948 (reg:SI VL_REGNUM)
4949 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4950 (match_operator:<VM> 3 "equality_operator"
4951 [(vec_duplicate:V_VLSI_D
4952 (match_operand:<VEL> 5 "register_operand" " r, r"))
4953 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
4954 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4955 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4956 "vms%B3.vx\t%0,%4,%5%p1"
4957 [(set_attr "type" "vicmp")
4958 (set_attr "mode" "<MODE>")])
4959
4960 ;; We use early-clobber for source LMUL > dest LMUL.
4961 (define_insn "*pred_eqne<mode>_scalar_narrow"
4962 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4963 (if_then_else:<VM>
4964 (unspec:<VM>
4965 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4966 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4967 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4968 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4969 (reg:SI VL_REGNUM)
4970 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4971 (match_operator:<VM> 3 "equality_operator"
4972 [(vec_duplicate:V_VLSI_D
4973 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4974 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
4975 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4976 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4977 "vms%B3.vx\t%0,%4,%5%p1"
4978 [(set_attr "type" "vicmp")
4979 (set_attr "mode" "<MODE>")])
4980
4981 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
4982 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4983 (if_then_else:<VM>
4984 (unspec:<VM>
4985 [(match_operand:<VM> 1 "register_operand" " 0")
4986 (match_operand 5 "vector_length_operand" " rK")
4987 (match_operand 6 "const_int_operand" " i")
4988 (match_operand 7 "const_int_operand" " i")
4989 (reg:SI VL_REGNUM)
4990 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4991 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4992 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4993 (vec_duplicate:V_VLSI_D
4994 (sign_extend:<VEL>
4995 (match_operand:<VSUBEL> 4 "register_operand" " r")))])
4996 (match_dup 1)))]
4997 "TARGET_VECTOR && !TARGET_64BIT"
4998 "vms%B2.vx\t%0,%3,%4,v0.t"
4999 [(set_attr "type" "vicmp")
5000 (set_attr "mode" "<MODE>")
5001 (set_attr "merge_op_idx" "1")
5002 (set_attr "vl_op_idx" "5")
5003 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5004 (set (attr "avl_type_idx") (const_int 7))])
5005
5006 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5007 (define_insn "*pred_cmp<mode>_extended_scalar"
5008 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
5009 (if_then_else:<VM>
5010 (unspec:<VM>
5011 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
5012 (match_operand 6 "vector_length_operand" " rK, rK")
5013 (match_operand 7 "const_int_operand" " i, i")
5014 (match_operand 8 "const_int_operand" " i, i")
5015 (reg:SI VL_REGNUM)
5016 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5017 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5018 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
5019 (vec_duplicate:V_VLSI_D
5020 (sign_extend:<VEL>
5021 (match_operand:<VSUBEL> 5 "register_operand" " r, r")))])
5022 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
5023 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
5024 "vms%B3.vx\t%0,%4,%5%p1"
5025 [(set_attr "type" "vicmp")
5026 (set_attr "mode" "<MODE>")])
5027
5028 (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
5029 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5030 (if_then_else:<VM>
5031 (unspec:<VM>
5032 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5033 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5034 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5035 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5036 (reg:SI VL_REGNUM)
5037 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5038 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5039 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5040 (vec_duplicate:V_VLSI_D
5041 (sign_extend:<VEL>
5042 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))])
5043 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5044 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
5045 "vms%B3.vx\t%0,%4,%5%p1"
5046 [(set_attr "type" "vicmp")
5047 (set_attr "mode" "<MODE>")])
5048
5049 (define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
5050 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5051 (if_then_else:<VM>
5052 (unspec:<VM>
5053 [(match_operand:<VM> 1 "register_operand" " 0")
5054 (match_operand 5 "vector_length_operand" " rK")
5055 (match_operand 6 "const_int_operand" " i")
5056 (match_operand 7 "const_int_operand" " i")
5057 (reg:SI VL_REGNUM)
5058 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5059 (match_operator:<VM> 2 "equality_operator"
5060 [(vec_duplicate:V_VLSI_D
5061 (sign_extend:<VEL>
5062 (match_operand:<VSUBEL> 4 "register_operand" " r")))
5063 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
5064 (match_dup 1)))]
5065 "TARGET_VECTOR && !TARGET_64BIT"
5066 "vms%B2.vx\t%0,%3,%4,v0.t"
5067 [(set_attr "type" "vicmp")
5068 (set_attr "mode" "<MODE>")
5069 (set_attr "merge_op_idx" "1")
5070 (set_attr "vl_op_idx" "5")
5071 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5072 (set (attr "avl_type_idx") (const_int 7))])
5073
5074 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5075 (define_insn "*pred_eqne<mode>_extended_scalar"
5076 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
5077 (if_then_else:<VM>
5078 (unspec:<VM>
5079 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
5080 (match_operand 6 "vector_length_operand" " rK, rK")
5081 (match_operand 7 "const_int_operand" " i, i")
5082 (match_operand 8 "const_int_operand" " i, i")
5083 (reg:SI VL_REGNUM)
5084 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5085 (match_operator:<VM> 3 "equality_operator"
5086 [(vec_duplicate:V_VLSI_D
5087 (sign_extend:<VEL>
5088 (match_operand:<VSUBEL> 5 "register_operand" " r, r")))
5089 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
5090 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
5091 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
5092 "vms%B3.vx\t%0,%4,%5%p1"
5093 [(set_attr "type" "vicmp")
5094 (set_attr "mode" "<MODE>")])
5095
5096 (define_insn "*pred_eqne<mode>_extended_scalar_narrow"
5097 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5098 (if_then_else:<VM>
5099 (unspec:<VM>
5100 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5101 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5102 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5103 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5104 (reg:SI VL_REGNUM)
5105 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5106 (match_operator:<VM> 3 "equality_operator"
5107 [(vec_duplicate:V_VLSI_D
5108 (sign_extend:<VEL>
5109 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))
5110 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
5111 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5112 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
5113 "vms%B3.vx\t%0,%4,%5%p1"
5114 [(set_attr "type" "vicmp")
5115 (set_attr "mode" "<MODE>")])
5116
5117 ;; GE, vmsge.vx/vmsgeu.vx
5118 ;;
5119 ;; unmasked va >= x
5120 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x
5121 ;; - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
5122 ;;
5123 ;; masked va >= x, vd != v0
5124 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5125 ;; - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
5126 ;;
5127 ;; masked va >= x, vd == v0
5128 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5129 ;; - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
5130 (define_expand "@pred_ge<mode>_scalar"
5131 [(set (match_operand:<VM> 0 "register_operand")
5132 (if_then_else:<VM>
5133 (unspec:<VM>
5134 [(match_operand:<VM> 1 "vector_mask_operand")
5135 (match_operand 6 "vector_length_operand")
5136 (match_operand 7 "const_int_operand")
5137 (match_operand 8 "const_int_operand")
5138 (reg:SI VL_REGNUM)
5139 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5140 (match_operator:<VM> 3 "ge_operator"
5141 [(match_operand:V_VLSI 4 "register_operand")
5142 (vec_duplicate:V_VLSI
5143 (match_operand:<VEL> 5 "reg_or_int_operand"))])
5144 (match_operand:<VM> 2 "vector_merge_operand")))]
5145 "TARGET_VECTOR"
5146 {
5147 enum rtx_code code = GET_CODE (operands[3]);
5148 rtx undef = RVV_VUNDEF (<VM>mode);
5149 rtx tmp = gen_reg_rtx (<VM>mode);
5150 if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
5151 {
5152 /* If vmsgeu with 0 immediate, expand it to vmset. */
5153 if (satisfies_constraint_Wc1 (operands[1]))
5154 emit_insn (
5155 gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
5156 CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
5157 else
5158 {
5159 /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
5160 */
5161 if (rtx_equal_p (operands[1], operands[2]))
5162 emit_move_insn (operands[0], operands[1]);
5163 else if (register_operand (operands[2], <VM>mode))
5164 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5165 CONSTM1_RTX (<VM>mode), undef, operands[1],
5166 operands[2], operands[6], operands[8]));
5167 else
5168 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5169 CONSTM1_RTX (<VM>mode), undef, operands[1],
5170 operands[1], operands[6], operands[8]));
5171 }
5172 }
5173 else if (riscv_vector::neg_simm5_p (operands[5]))
5174 emit_insn (
5175 gen_pred_ltge<mode> (operands[0], operands[1], operands[2], operands[3],
5176 operands[4],
5177 gen_const_vec_duplicate (<MODE>mode, operands[5]),
5178 operands[6], operands[7], operands[8]));
5179 else
5180 {
5181 if (code == GE)
5182 operands[3] = gen_rtx_fmt_ee (LT, <VM>mode, XEXP (operands[3], 0),
5183 XEXP (operands[3], 1));
5184 else
5185 operands[3] = gen_rtx_fmt_ee (LTU, <VM>mode, XEXP (operands[3], 0),
5186 XEXP (operands[3], 1));
5187 if (GET_MODE_BITSIZE (<VEL>mode) <= GET_MODE_BITSIZE (Pmode))
5188 operands[5] = force_reg (<VEL>mode, operands[5]);
5189
5190 if (satisfies_constraint_Wc1 (operands[1]))
5191 {
5192 /* unmasked va >= x
5193 - pseudoinstruction: vmsge{u}.vx vd, va, x
5194 - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */
5195 emit_insn (
5196 gen_pred_cmp<mode>_scalar (tmp, operands[1], operands[2],
5197 operands[3], operands[4], operands[5],
5198 operands[6], operands[7], operands[8]));
5199 emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
5200 undef, tmp, tmp, operands[6], operands[8]));
5201 }
5202 else
5203 {
5204 if (rtx_equal_p (operands[1], operands[2]))
5205 {
5206 /* masked va >= x, vd == v0
5207 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5208 - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */
5209 emit_insn (gen_pred_cmp<mode>_scalar (
5210 tmp, CONSTM1_RTX (<VM>mode), undef, operands[3], operands[4],
5211 operands[5], operands[6], operands[7], operands[8]));
5212 emit_insn (
5213 gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
5214 operands[1], tmp, operands[6], operands[8]));
5215 }
5216 else
5217 {
5218 /* masked va >= x, vd != v0
5219 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5220 - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
5221 */
5222 emit_insn (gen_pred_cmp<mode>_scalar (
5223 tmp, operands[1], operands[2], operands[3], operands[4],
5224 operands[5], operands[6], operands[7], operands[8]));
5225 emit_insn (gen_pred (XOR, <VM>mode, operands[0],
5226 CONSTM1_RTX (<VM>mode), undef, tmp,
5227 operands[1], operands[6], operands[8]));
5228 }
5229 }
5230 }
5231 DONE;
5232 })
5233
5234 ;; -------------------------------------------------------------------------------
5235 ;; ---- Predicated integer ternary operations
5236 ;; -------------------------------------------------------------------------------
5237 ;; Includes:
5238 ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions
5239 ;; -------------------------------------------------------------------------------
5240
5241 (define_expand "@pred_mul_plus<mode>"
5242 [(set (match_operand:V_VLSI 0 "register_operand")
5243 (if_then_else:V_VLSI
5244 (unspec:<VM>
5245 [(match_operand:<VM> 1 "vector_mask_operand")
5246 (match_operand 6 "vector_length_operand")
5247 (match_operand 7 "const_int_operand")
5248 (match_operand 8 "const_int_operand")
5249 (match_operand 9 "const_int_operand")
5250 (reg:SI VL_REGNUM)
5251 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5252 (plus:V_VLSI
5253 (mult:V_VLSI
5254 (match_operand:V_VLSI 2 "register_operand")
5255 (match_operand:V_VLSI 3 "register_operand"))
5256 (match_operand:V_VLSI 4 "register_operand"))
5257 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5258 "TARGET_VECTOR"
5259 {
5260 riscv_vector::prepare_ternary_operands (operands);
5261 })
5262
5263 (define_insn "*pred_mul_plus<mode>_undef"
5264 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5265 (if_then_else:V_VLSI
5266 (unspec:<VM>
5267 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5268 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5269 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5270 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5271 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5272 (reg:SI VL_REGNUM)
5273 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5274 (plus:V_VLSI
5275 (mult:V_VLSI
5276 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5277 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
5278 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
5279 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5280 "TARGET_VECTOR"
5281 "@
5282 vmadd.vv\t%0,%4,%5%p1
5283 vmacc.vv\t%0,%3,%4%p1
5284 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1
5285 vmadd.vv\t%0,%4,%5%p1
5286 vmacc.vv\t%0,%3,%4%p1
5287 vmv.v.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1"
5288 [(set_attr "type" "vimuladd")
5289 (set_attr "mode" "<MODE>")])
5290
5291 (define_insn "*pred_madd<mode>"
5292 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5293 (if_then_else:V_VLSI
5294 (unspec:<VM>
5295 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5296 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5297 (match_operand 6 "const_int_operand" " i, i, i, i")
5298 (match_operand 7 "const_int_operand" " i, i, i, i")
5299 (match_operand 8 "const_int_operand" " i, i, i, i")
5300 (reg:SI VL_REGNUM)
5301 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5302 (plus:V_VLSI
5303 (mult:V_VLSI
5304 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5305 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5306 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5307 (match_dup 2)))]
5308 "TARGET_VECTOR"
5309 "@
5310 vmadd.vv\t%0,%3,%4%p1
5311 vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1
5312 vmadd.vv\t%0,%3,%4%p1
5313 vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
5314 [(set_attr "type" "vimuladd")
5315 (set_attr "mode" "<MODE>")
5316 (set_attr "merge_op_idx" "4")
5317 (set_attr "vl_op_idx" "5")
5318 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5319 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5320 (set (attr "avl_type_idx") (const_int 8))])
5321
5322 (define_insn "*pred_macc<mode>"
5323 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5324 (if_then_else:V_VLSI
5325 (unspec:<VM>
5326 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5327 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5328 (match_operand 6 "const_int_operand" " i, i, i, i")
5329 (match_operand 7 "const_int_operand" " i, i, i, i")
5330 (match_operand 8 "const_int_operand" " i, i, i, i")
5331 (reg:SI VL_REGNUM)
5332 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5333 (plus:V_VLSI
5334 (mult:V_VLSI
5335 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5336 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5337 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5338 (match_dup 4)))]
5339 "TARGET_VECTOR"
5340 "@
5341 vmacc.vv\t%0,%2,%3%p1
5342 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1
5343 vmacc.vv\t%0,%2,%3%p1
5344 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
5345 [(set_attr "type" "vimuladd")
5346 (set_attr "mode" "<MODE>")
5347 (set_attr "merge_op_idx" "2")
5348 (set_attr "vl_op_idx" "5")
5349 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5350 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5351 (set (attr "avl_type_idx") (const_int 8))])
5352
5353 (define_expand "@pred_mul_plus<mode>_scalar"
5354 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5355 (if_then_else:V_VLSI_QHS
5356 (unspec:<VM>
5357 [(match_operand:<VM> 1 "vector_mask_operand")
5358 (match_operand 6 "vector_length_operand")
5359 (match_operand 7 "const_int_operand")
5360 (match_operand 8 "const_int_operand")
5361 (match_operand 9 "const_int_operand")
5362 (reg:SI VL_REGNUM)
5363 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5364 (plus:V_VLSI_QHS
5365 (mult:V_VLSI_QHS
5366 (vec_duplicate:V_VLSI_QHS
5367 (match_operand:<VEL> 2 "register_operand"))
5368 (match_operand:V_VLSI_QHS 3 "register_operand"))
5369 (match_operand:V_VLSI_QHS 4 "register_operand"))
5370 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5371 "TARGET_VECTOR"
5372 {})
5373
5374 (define_insn "*pred_madd<mode>_scalar"
5375 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5376 (if_then_else:V_VLSI
5377 (unspec:<VM>
5378 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5379 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5380 (match_operand 6 "const_int_operand" " i, i, i, i")
5381 (match_operand 7 "const_int_operand" " i, i, i, i")
5382 (match_operand 8 "const_int_operand" " i, i, i, i")
5383 (reg:SI VL_REGNUM)
5384 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5385 (plus:V_VLSI
5386 (mult:V_VLSI
5387 (vec_duplicate:V_VLSI
5388 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5389 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))
5390 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5391 (match_dup 3)))]
5392 "TARGET_VECTOR"
5393 "@
5394 vmadd.vx\t%0,%2,%4%p1
5395 vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1
5396 vmadd.vx\t%0,%2,%4%p1
5397 vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
5398 [(set_attr "type" "vimuladd")
5399 (set_attr "mode" "<MODE>")
5400 (set_attr "merge_op_idx" "4")
5401 (set_attr "vl_op_idx" "5")
5402 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5403 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5404 (set (attr "avl_type_idx") (const_int 8))])
5405
5406 (define_insn "*pred_macc<mode>_scalar"
5407 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5408 (if_then_else:V_VLSI
5409 (unspec:<VM>
5410 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5411 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5412 (match_operand 6 "const_int_operand" " i, i, i, i")
5413 (match_operand 7 "const_int_operand" " i, i, i, i")
5414 (match_operand 8 "const_int_operand" " i, i, i, i")
5415 (reg:SI VL_REGNUM)
5416 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5417 (plus:V_VLSI
5418 (mult:V_VLSI
5419 (vec_duplicate:V_VLSI
5420 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5421 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5422 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5423 (match_dup 4)))]
5424 "TARGET_VECTOR"
5425 "@
5426 vmacc.vx\t%0,%2,%3%p1
5427 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5428 vmacc.vx\t%0,%2,%3%p1
5429 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5430 [(set_attr "type" "vimuladd")
5431 (set_attr "mode" "<MODE>")
5432 (set_attr "merge_op_idx" "2")
5433 (set_attr "vl_op_idx" "5")
5434 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5435 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5436 (set (attr "avl_type_idx") (const_int 8))])
5437
5438 (define_expand "@pred_mul_plus<mode>_scalar"
5439 [(set (match_operand:V_VLSI_D 0 "register_operand")
5440 (if_then_else:V_VLSI_D
5441 (unspec:<VM>
5442 [(match_operand:<VM> 1 "vector_mask_operand")
5443 (match_operand 6 "vector_length_operand")
5444 (match_operand 7 "const_int_operand")
5445 (match_operand 8 "const_int_operand")
5446 (match_operand 9 "const_int_operand")
5447 (reg:SI VL_REGNUM)
5448 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5449 (plus:V_VLSI_D
5450 (mult:V_VLSI_D
5451 (vec_duplicate:V_VLSI_D
5452 (match_operand:<VEL> 2 "reg_or_int_operand"))
5453 (match_operand:V_VLSI_D 3 "register_operand"))
5454 (match_operand:V_VLSI_D 4 "register_operand"))
5455 (match_operand:V_VLSI_D 5 "register_operand")))]
5456 "TARGET_VECTOR"
5457 {
5458 if (riscv_vector::sew64_scalar_helper (
5459 operands,
5460 /* scalar op */&operands[2],
5461 /* vl */operands[6],
5462 <MODE>mode,
5463 false,
5464 [] (rtx *operands, rtx boardcast_scalar) {
5465 emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
5466 boardcast_scalar, operands[3], operands[4], operands[5],
5467 operands[6], operands[7], operands[8], operands[9]));
5468 },
5469 (riscv_vector::avl_type) INTVAL (operands[9])))
5470 DONE;
5471 })
5472
5473 (define_insn "*pred_madd<mode>_extended_scalar"
5474 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5475 (if_then_else:V_VLSI_D
5476 (unspec:<VM>
5477 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5478 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5479 (match_operand 6 "const_int_operand" " i, i, i, i")
5480 (match_operand 7 "const_int_operand" " i, i, i, i")
5481 (match_operand 8 "const_int_operand" " i, i, i, i")
5482 (reg:SI VL_REGNUM)
5483 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5484 (plus:V_VLSI_D
5485 (mult:V_VLSI_D
5486 (vec_duplicate:V_VLSI_D
5487 (sign_extend:<VEL>
5488 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5489 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))
5490 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr"))
5491 (match_dup 3)))]
5492 "TARGET_VECTOR && !TARGET_64BIT"
5493 "@
5494 vmadd.vx\t%0,%2,%4%p1
5495 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1
5496 vmadd.vx\t%0,%2,%4%p1
5497 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
5498 [(set_attr "type" "vimuladd")
5499 (set_attr "mode" "<MODE>")
5500 (set_attr "merge_op_idx" "4")
5501 (set_attr "vl_op_idx" "5")
5502 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5503 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5504 (set (attr "avl_type_idx") (const_int 8))])
5505
5506 (define_insn "*pred_macc<mode>_extended_scalar"
5507 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5508 (if_then_else:V_VLSI_D
5509 (unspec:<VM>
5510 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5511 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5512 (match_operand 6 "const_int_operand" " i, i, i, i")
5513 (match_operand 7 "const_int_operand" " i, i, i, i")
5514 (match_operand 8 "const_int_operand" " i, i, i, i")
5515 (reg:SI VL_REGNUM)
5516 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5517 (plus:V_VLSI_D
5518 (mult:V_VLSI_D
5519 (vec_duplicate:V_VLSI_D
5520 (sign_extend:<VEL>
5521 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5522 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))
5523 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr"))
5524 (match_dup 4)))]
5525 "TARGET_VECTOR && !TARGET_64BIT"
5526 "@
5527 vmacc.vx\t%0,%2,%3%p1
5528 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5529 vmacc.vx\t%0,%2,%3%p1
5530 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5531 [(set_attr "type" "vimuladd")
5532 (set_attr "mode" "<MODE>")
5533 (set_attr "merge_op_idx" "2")
5534 (set_attr "vl_op_idx" "5")
5535 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5536 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5537 (set (attr "avl_type_idx") (const_int 8))])
5538
5539 (define_expand "@pred_minus_mul<mode>"
5540 [(set (match_operand:V_VLSI 0 "register_operand")
5541 (if_then_else:V_VLSI
5542 (unspec:<VM>
5543 [(match_operand:<VM> 1 "vector_mask_operand")
5544 (match_operand 6 "vector_length_operand")
5545 (match_operand 7 "const_int_operand")
5546 (match_operand 8 "const_int_operand")
5547 (match_operand 9 "const_int_operand")
5548 (reg:SI VL_REGNUM)
5549 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5550 (minus:V_VLSI
5551 (match_operand:V_VLSI 4 "register_operand")
5552 (mult:V_VLSI
5553 (match_operand:V_VLSI 2 "register_operand")
5554 (match_operand:V_VLSI 3 "register_operand")))
5555 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5556 "TARGET_VECTOR"
5557 {
5558 riscv_vector::prepare_ternary_operands (operands);
5559 })
5560
5561 (define_insn "*pred_minus_mul<mode>_undef"
5562 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5563 (if_then_else:V_VLSI
5564 (unspec:<VM>
5565 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5566 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5567 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5568 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5569 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5570 (reg:SI VL_REGNUM)
5571 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5572 (minus:V_VLSI
5573 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
5574 (mult:V_VLSI
5575 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5576 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
5577 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5578 "TARGET_VECTOR"
5579 "@
5580 vnmsub.vv\t%0,%4,%5%p1
5581 vnmsac.vv\t%0,%3,%4%p1
5582 vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1
5583 vnmsub.vv\t%0,%4,%5%p1
5584 vnmsac.vv\t%0,%3,%4%p1
5585 vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1"
5586 [(set_attr "type" "vimuladd")
5587 (set_attr "mode" "<MODE>")])
5588
5589 (define_insn "*pred_nmsub<mode>"
5590 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5591 (if_then_else:V_VLSI
5592 (unspec:<VM>
5593 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5594 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5595 (match_operand 6 "const_int_operand" " i, i, i, i")
5596 (match_operand 7 "const_int_operand" " i, i, i, i")
5597 (match_operand 8 "const_int_operand" " i, i, i, i")
5598 (reg:SI VL_REGNUM)
5599 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5600 (minus:V_VLSI
5601 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5602 (mult:V_VLSI
5603 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5604 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5605 (match_dup 2)))]
5606 "TARGET_VECTOR"
5607 "@
5608 vnmsub.vv\t%0,%3,%4%p1
5609 vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1
5610 vnmsub.vv\t%0,%3,%4%p1
5611 vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
5612 [(set_attr "type" "vimuladd")
5613 (set_attr "mode" "<MODE>")
5614 (set_attr "merge_op_idx" "4")
5615 (set_attr "vl_op_idx" "5")
5616 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5617 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5618 (set (attr "avl_type_idx") (const_int 8))])
5619
5620 (define_insn "*pred_nmsac<mode>"
5621 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5622 (if_then_else:V_VLSI
5623 (unspec:<VM>
5624 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5625 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5626 (match_operand 6 "const_int_operand" " i, i, i, i")
5627 (match_operand 7 "const_int_operand" " i, i, i, i")
5628 (match_operand 8 "const_int_operand" " i, i, i, i")
5629 (reg:SI VL_REGNUM)
5630 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5631 (minus:V_VLSI
5632 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5633 (mult:V_VLSI
5634 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5635 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5636 (match_dup 4)))]
5637 "TARGET_VECTOR"
5638 "@
5639 vnmsac.vv\t%0,%2,%3%p1
5640 vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1
5641 vnmsac.vv\t%0,%2,%3%p1
5642 vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
5643 [(set_attr "type" "vimuladd")
5644 (set_attr "mode" "<MODE>")
5645 (set_attr "merge_op_idx" "2")
5646 (set_attr "vl_op_idx" "5")
5647 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5648 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5649 (set (attr "avl_type_idx") (const_int 8))])
5650
5651 (define_expand "@pred_minus_mul<mode>_scalar"
5652 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5653 (if_then_else:V_VLSI_QHS
5654 (unspec:<VM>
5655 [(match_operand:<VM> 1 "vector_mask_operand")
5656 (match_operand 6 "vector_length_operand")
5657 (match_operand 7 "const_int_operand")
5658 (match_operand 8 "const_int_operand")
5659 (match_operand 9 "const_int_operand")
5660 (reg:SI VL_REGNUM)
5661 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5662 (minus:V_VLSI_QHS
5663 (match_operand:V_VLSI_QHS 4 "register_operand")
5664 (mult:V_VLSI_QHS
5665 (vec_duplicate:V_VLSI_QHS
5666 (match_operand:<VEL> 2 "register_operand"))
5667 (match_operand:V_VLSI_QHS 3 "register_operand")))
5668 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5669 "TARGET_VECTOR"
5670 {})
5671
5672 (define_insn "*pred_nmsub<mode>_scalar"
5673 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5674 (if_then_else:V_VLSI
5675 (unspec:<VM>
5676 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5677 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5678 (match_operand 6 "const_int_operand" " i, i, i, i")
5679 (match_operand 7 "const_int_operand" " i, i, i, i")
5680 (match_operand 8 "const_int_operand" " i, i, i, i")
5681 (reg:SI VL_REGNUM)
5682 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5683 (minus:V_VLSI
5684 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5685 (mult:V_VLSI
5686 (vec_duplicate:V_VLSI
5687 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5688 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")))
5689 (match_dup 3)))]
5690 "TARGET_VECTOR"
5691 "@
5692 vnmsub.vx\t%0,%2,%4%p1
5693 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5694 vnmsub.vx\t%0,%2,%4%p1
5695 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5696 [(set_attr "type" "vimuladd")
5697 (set_attr "mode" "<MODE>")
5698 (set_attr "merge_op_idx" "4")
5699 (set_attr "vl_op_idx" "5")
5700 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5701 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5702 (set (attr "avl_type_idx") (const_int 8))])
5703
5704 (define_insn "*pred_nmsac<mode>_scalar"
5705 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5706 (if_then_else:V_VLSI
5707 (unspec:<VM>
5708 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5709 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5710 (match_operand 6 "const_int_operand" " i, i, i, i")
5711 (match_operand 7 "const_int_operand" " i, i, i, i")
5712 (match_operand 8 "const_int_operand" " i, i, i, i")
5713 (reg:SI VL_REGNUM)
5714 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5715 (minus:V_VLSI
5716 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5717 (mult:V_VLSI
5718 (vec_duplicate:V_VLSI
5719 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5720 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5721 (match_dup 4)))]
5722 "TARGET_VECTOR"
5723 "@
5724 vnmsac.vx\t%0,%2,%3%p1
5725 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5726 vnmsac.vx\t%0,%2,%3%p1
5727 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5728 [(set_attr "type" "vimuladd")
5729 (set_attr "mode" "<MODE>")
5730 (set_attr "merge_op_idx" "2")
5731 (set_attr "vl_op_idx" "5")
5732 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5733 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5734 (set (attr "avl_type_idx") (const_int 8))])
5735
5736 (define_expand "@pred_minus_mul<mode>_scalar"
5737 [(set (match_operand:V_VLSI_D 0 "register_operand")
5738 (if_then_else:V_VLSI_D
5739 (unspec:<VM>
5740 [(match_operand:<VM> 1 "vector_mask_operand")
5741 (match_operand 6 "vector_length_operand")
5742 (match_operand 7 "const_int_operand")
5743 (match_operand 8 "const_int_operand")
5744 (match_operand 9 "const_int_operand")
5745 (reg:SI VL_REGNUM)
5746 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5747 (minus:V_VLSI_D
5748 (match_operand:V_VLSI_D 4 "register_operand")
5749 (mult:V_VLSI_D
5750 (vec_duplicate:V_VLSI_D
5751 (match_operand:<VEL> 2 "reg_or_int_operand"))
5752 (match_operand:V_VLSI_D 3 "register_operand")))
5753 (match_operand:V_VLSI_D 5 "register_operand")))]
5754 "TARGET_VECTOR"
5755 {
5756 if (riscv_vector::sew64_scalar_helper (
5757 operands,
5758 /* scalar op */&operands[2],
5759 /* vl */operands[6],
5760 <MODE>mode,
5761 false,
5762 [] (rtx *operands, rtx boardcast_scalar) {
5763 emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
5764 boardcast_scalar, operands[3], operands[4], operands[5],
5765 operands[6], operands[7], operands[8], operands[9]));
5766 },
5767 (riscv_vector::avl_type) INTVAL (operands[9])))
5768 DONE;
5769 })
5770
5771 (define_insn "*pred_nmsub<mode>_extended_scalar"
5772 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5773 (if_then_else:V_VLSI_D
5774 (unspec:<VM>
5775 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5776 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5777 (match_operand 6 "const_int_operand" " i, i, i, i")
5778 (match_operand 7 "const_int_operand" " i, i, i, i")
5779 (match_operand 8 "const_int_operand" " i, i, i, i")
5780 (reg:SI VL_REGNUM)
5781 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5782 (minus:V_VLSI_D
5783 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5784 (mult:V_VLSI_D
5785 (vec_duplicate:V_VLSI_D
5786 (sign_extend:<VEL>
5787 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5788 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")))
5789 (match_dup 3)))]
5790 "TARGET_VECTOR && !TARGET_64BIT"
5791 "@
5792 vnmsub.vx\t%0,%2,%4%p1
5793 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5794 vnmsub.vx\t%0,%2,%4%p1
5795 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5796 [(set_attr "type" "vimuladd")
5797 (set_attr "mode" "<MODE>")
5798 (set_attr "merge_op_idx" "4")
5799 (set_attr "vl_op_idx" "5")
5800 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5801 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5802 (set (attr "avl_type_idx") (const_int 8))])
5803
5804 (define_insn "*pred_nmsac<mode>_extended_scalar"
5805 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5806 (if_then_else:V_VLSI_D
5807 (unspec:<VM>
5808 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5809 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5810 (match_operand 6 "const_int_operand" " i, i, i, i")
5811 (match_operand 7 "const_int_operand" " i, i, i, i")
5812 (match_operand 8 "const_int_operand" " i, i, i, i")
5813 (reg:SI VL_REGNUM)
5814 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5815 (minus:V_VLSI_D
5816 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")
5817 (mult:V_VLSI_D
5818 (vec_duplicate:V_VLSI_D
5819 (sign_extend:<VEL>
5820 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5821 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")))
5822 (match_dup 4)))]
5823 "TARGET_VECTOR && !TARGET_64BIT"
5824 "@
5825 vnmsac.vx\t%0,%2,%3%p1
5826 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5827 vnmsac.vx\t%0,%2,%3%p1
5828 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5829 [(set_attr "type" "vimuladd")
5830 (set_attr "mode" "<MODE>")
5831 (set_attr "merge_op_idx" "2")
5832 (set_attr "vl_op_idx" "5")
5833 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5834 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5835 (set (attr "avl_type_idx") (const_int 8))])
5836
5837 ;; -------------------------------------------------------------------------------
5838 ;; ---- Predicated widen integer ternary operations
5839 ;; -------------------------------------------------------------------------------
5840 ;; Includes:
5841 ;; - 11.14 Vector Widening Integer Multiply-Add Instructions
5842 ;; -------------------------------------------------------------------------------
5843
5844 (define_insn "@pred_widen_mul_plus<su><mode>"
5845 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5846 (if_then_else:VWEXTI
5847 (unspec:<VM>
5848 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5849 (match_operand 5 "vector_length_operand" " rK")
5850 (match_operand 6 "const_int_operand" " i")
5851 (match_operand 7 "const_int_operand" " i")
5852 (match_operand 8 "const_int_operand" " i")
5853 (reg:SI VL_REGNUM)
5854 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5855 (plus:VWEXTI
5856 (mult:VWEXTI
5857 (any_extend:VWEXTI
5858 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5859 (any_extend:VWEXTI
5860 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5861 (match_operand:VWEXTI 2 "register_operand" " 0"))
5862 (match_dup 2)))]
5863 "TARGET_VECTOR"
5864 "vwmacc<u>.vv\t%0,%3,%4%p1"
5865 [(set_attr "type" "viwmuladd")
5866 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5867
5868 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
5869 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
5870 (if_then_else:VWEXTI
5871 (unspec:<VM>
5872 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
5873 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
5874 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
5875 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
5876 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
5877 (reg:SI VL_REGNUM)
5878 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5879 (plus:VWEXTI
5880 (mult:VWEXTI
5881 (any_extend:VWEXTI
5882 (vec_duplicate:<V_DOUBLE_TRUNC>
5883 (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
5884 (any_extend:VWEXTI
5885 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
5886 (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
5887 (match_dup 2)))]
5888 "TARGET_VECTOR"
5889 "vwmacc<u>.vx\t%0,%z3,%4%p1"
5890 [(set_attr "type" "viwmuladd")
5891 (set_attr "mode" "<V_DOUBLE_TRUNC>")
5892 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
5893
5894 (define_insn "@pred_widen_mul_plussu<mode>"
5895 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5896 (if_then_else:VWEXTI
5897 (unspec:<VM>
5898 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5899 (match_operand 5 "vector_length_operand" " rK")
5900 (match_operand 6 "const_int_operand" " i")
5901 (match_operand 7 "const_int_operand" " i")
5902 (match_operand 8 "const_int_operand" " i")
5903 (reg:SI VL_REGNUM)
5904 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5905 (plus:VWEXTI
5906 (mult:VWEXTI
5907 (sign_extend:VWEXTI
5908 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5909 (zero_extend:VWEXTI
5910 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5911 (match_operand:VWEXTI 2 "register_operand" " 0"))
5912 (match_dup 2)))]
5913 "TARGET_VECTOR"
5914 "vwmaccsu.vv\t%0,%3,%4%p1"
5915 [(set_attr "type" "viwmuladd")
5916 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5917
5918 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
5919 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
5920 (if_then_else:VWEXTI
5921 (unspec:<VM>
5922 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
5923 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
5924 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
5925 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
5926 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
5927 (reg:SI VL_REGNUM)
5928 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5929 (plus:VWEXTI
5930 (mult:VWEXTI
5931 (sign_extend:VWEXTI
5932 (vec_duplicate:<V_DOUBLE_TRUNC>
5933 (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
5934 (zero_extend:VWEXTI
5935 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
5936 (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
5937 (match_dup 2)))]
5938 "TARGET_VECTOR"
5939 "vwmaccsu.vx\t%0,%z3,%4%p1"
5940 [(set_attr "type" "viwmuladd")
5941 (set_attr "mode" "<V_DOUBLE_TRUNC>")
5942 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
5943
5944 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
5945 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
5946 (if_then_else:VWEXTI
5947 (unspec:<VM>
5948 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
5949 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
5950 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
5951 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
5952 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
5953 (reg:SI VL_REGNUM)
5954 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5955 (plus:VWEXTI
5956 (mult:VWEXTI
5957 (zero_extend:VWEXTI
5958 (vec_duplicate:<V_DOUBLE_TRUNC>
5959 (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
5960 (sign_extend:VWEXTI
5961 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
5962 (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
5963 (match_dup 2)))]
5964 "TARGET_VECTOR"
5965 "vwmaccus.vx\t%0,%z3,%4%p1"
5966 [(set_attr "type" "viwmuladd")
5967 (set_attr "mode" "<V_DOUBLE_TRUNC>")
5968 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
5969
5970 ;; -------------------------------------------------------------------------------
5971 ;; ---- Predicated BOOL mask operations
5972 ;; -------------------------------------------------------------------------------
5973 ;; Includes:
5974 ;; - 15.1 Vector Mask-Register Logical Instructions
5975 ;; - 15.2 Vector count population in mask vcpop.m
5976 ;; - 15.3 vfirst find-first-set mask bit
5977 ;; - 15.4 vmsbf.m set-before-first mask bit
5978 ;; - 15.5 vmsif.m set-including-first mask bit
5979 ;; - 15.6 vmsof.m set-only-first mask bit
5980 ;; - 15.8 Vector Iota Instruction
5981 ;; - 15.9 Vector Element Index Instruction
5982 ;; -------------------------------------------------------------------------------
5983
5984 ;; We keep this pattern same as pred_mov so that we can gain more optimizations.
5985 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which
5986 ;; is generated by pred_mov.
5987 (define_insn "@pred_<optab><mode>"
5988 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5989 (if_then_else:VB_VLS
5990 (unspec:VB_VLS
5991 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5992 (match_operand 5 "vector_length_operand" " rK")
5993 (match_operand 6 "const_int_operand" " i")
5994 (reg:SI VL_REGNUM)
5995 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5996 (any_bitwise:VB_VLS
5997 (match_operand:VB_VLS 3 "register_operand" " vr")
5998 (match_operand:VB_VLS 4 "register_operand" " vr"))
5999 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6000 "TARGET_VECTOR"
6001 "vm<insn>.mm\t%0,%3,%4"
6002 [(set_attr "type" "vmalu")
6003 (set_attr "mode" "<MODE>")
6004 (set_attr "vl_op_idx" "5")
6005 (set (attr "avl_type_idx") (const_int 6))])
6006
6007 (define_insn "@pred_n<optab><mode>"
6008 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6009 (if_then_else:VB_VLS
6010 (unspec:VB_VLS
6011 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6012 (match_operand 5 "vector_length_operand" " rK")
6013 (match_operand 6 "const_int_operand" " i")
6014 (reg:SI VL_REGNUM)
6015 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6016 (not:VB_VLS
6017 (any_bitwise:VB_VLS
6018 (match_operand:VB_VLS 3 "register_operand" " vr")
6019 (match_operand:VB_VLS 4 "register_operand" " vr")))
6020 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6021 "TARGET_VECTOR"
6022 "vm<ninsn>.mm\t%0,%3,%4"
6023 [(set_attr "type" "vmalu")
6024 (set_attr "mode" "<MODE>")
6025 (set_attr "vl_op_idx" "5")
6026 (set (attr "avl_type_idx") (const_int 6))])
6027
6028 (define_insn "@pred_<optab>not<mode>"
6029 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6030 (if_then_else:VB_VLS
6031 (unspec:VB_VLS
6032 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6033 (match_operand 5 "vector_length_operand" " rK")
6034 (match_operand 6 "const_int_operand" " i")
6035 (reg:SI VL_REGNUM)
6036 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6037 (and_ior:VB_VLS
6038 (match_operand:VB_VLS 3 "register_operand" " vr")
6039 (not:VB_VLS
6040 (match_operand:VB_VLS 4 "register_operand" " vr")))
6041 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6042 "TARGET_VECTOR"
6043 "vm<insn>n.mm\t%0,%3,%4"
6044 [(set_attr "type" "vmalu")
6045 (set_attr "mode" "<MODE>")
6046 (set_attr "vl_op_idx" "5")
6047 (set (attr "avl_type_idx") (const_int 6))])
6048
6049 (define_insn "@pred_not<mode>"
6050 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6051 (if_then_else:VB_VLS
6052 (unspec:VB_VLS
6053 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6054 (match_operand 4 "vector_length_operand" " rK")
6055 (match_operand 5 "const_int_operand" " i")
6056 (reg:SI VL_REGNUM)
6057 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6058 (not:VB_VLS
6059 (match_operand:VB_VLS 3 "register_operand" " vr"))
6060 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6061 "TARGET_VECTOR"
6062 "vmnot.m\t%0,%3"
6063 [(set_attr "type" "vmalu")
6064 (set_attr "mode" "<MODE>")
6065 (set_attr "vl_op_idx" "4")
6066 (set (attr "avl_type_idx") (const_int 5))])
6067
6068 (define_insn "@pred_popcount<VB:mode><P:mode>"
6069 [(set (match_operand:P 0 "register_operand" "=r")
6070 (popcount:P
6071 (unspec:VB
6072 [(and:VB
6073 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6074 (match_operand:VB 2 "register_operand" " vr"))
6075 (match_operand 3 "vector_length_operand" " rK")
6076 (match_operand 4 "const_int_operand" " i")
6077 (reg:SI VL_REGNUM)
6078 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
6079 "TARGET_VECTOR"
6080 "vcpop.m\t%0,%2%p1"
6081 [(set_attr "type" "vmpop")
6082 (set_attr "mode" "<VB:MODE>")])
6083
6084 (define_insn "@pred_ffs<VB:mode><P:mode>"
6085 [(set (match_operand:P 0 "register_operand" "=r")
6086 (plus:P
6087 (ffs:P
6088 (unspec:VB
6089 [(and:VB
6090 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6091 (match_operand:VB 2 "register_operand" " vr"))
6092 (match_operand 3 "vector_length_operand" " rK")
6093 (match_operand 4 "const_int_operand" " i")
6094 (reg:SI VL_REGNUM)
6095 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
6096 (const_int -1)))]
6097 "TARGET_VECTOR"
6098 "vfirst.m\t%0,%2%p1"
6099 [(set_attr "type" "vmffs")
6100 (set_attr "mode" "<VB:MODE>")])
6101
6102 (define_insn "@pred_<misc_op><mode>"
6103 [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
6104 (if_then_else:VB
6105 (unspec:VB
6106 [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
6107 (match_operand 4 "vector_length_operand" " rK, rK")
6108 (match_operand 5 "const_int_operand" " i, i")
6109 (match_operand 6 "const_int_operand" " i, i")
6110 (reg:SI VL_REGNUM)
6111 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6112 (unspec:VB
6113 [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
6114 (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
6115 "TARGET_VECTOR"
6116 "vm<misc_op>.m\t%0,%3%p1"
6117 [(set_attr "type" "vmsfs")
6118 (set_attr "mode" "<MODE>")])
6119
6120 (define_insn "@pred_iota<mode>"
6121 [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
6122 (if_then_else:VI
6123 (unspec:<VM>
6124 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6125 (match_operand 4 "vector_length_operand" " rK, rK")
6126 (match_operand 5 "const_int_operand" " i, i")
6127 (match_operand 6 "const_int_operand" " i, i")
6128 (match_operand 7 "const_int_operand" " i, i")
6129 (reg:SI VL_REGNUM)
6130 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6131 (unspec:VI
6132 [(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
6133 (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
6134 "TARGET_VECTOR"
6135 "viota.m\t%0,%3%p1"
6136 [(set_attr "type" "vmiota")
6137 (set_attr "mode" "<MODE>")])
6138
6139 (define_insn "@pred_series<mode>"
6140 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
6141 (if_then_else:V_VLSI
6142 (unspec:<VM>
6143 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6144 (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
6145 (match_operand 4 "const_int_operand" " i, i, i, i")
6146 (match_operand 5 "const_int_operand" " i, i, i, i")
6147 (match_operand 6 "const_int_operand" " i, i, i, i")
6148 (reg:SI VL_REGNUM)
6149 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6150 (vec_series:V_VLSI (const_int 0) (const_int 1))
6151 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6152 "TARGET_VECTOR"
6153 "vid.v\t%0%p1"
6154 [(set_attr "type" "vmidx")
6155 (set_attr "mode" "<MODE>")])
6156
6157 ;; -------------------------------------------------------------------------------
6158 ;; ---- Predicated floating-point binary operations
6159 ;; -------------------------------------------------------------------------------
6160 ;; Includes:
6161 ;; - 13.2 Vector Single-Width Floating-Point Add/Subtract Instructions
6162 ;; - 13.4 Vector Single-Width Floating-Point Multiply/Divide Instructions
6163 ;; - 13.11 Vector Floating-Point MIN/MAX Instructions
6164 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions
6165 ;; -------------------------------------------------------------------------------
6166
6167 (define_insn "@pred_<optab><mode>"
6168 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6169 (if_then_else:V_VLSF
6170 (unspec:<VM>
6171 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6172 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6173 (match_operand 6 "const_int_operand" " i, i, i, i")
6174 (match_operand 7 "const_int_operand" " i, i, i, i")
6175 (match_operand 8 "const_int_operand" " i, i, i, i")
6176 (match_operand 9 "const_int_operand" " i, i, i, i")
6177 (reg:SI VL_REGNUM)
6178 (reg:SI VTYPE_REGNUM)
6179 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6180 (any_float_binop:V_VLSF
6181 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6182 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6183 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6184 "TARGET_VECTOR"
6185 "vf<insn>.vv\t%0,%3,%4%p1"
6186 [(set_attr "type" "<float_insn_type>")
6187 (set_attr "mode" "<MODE>")
6188 (set (attr "frm_mode")
6189 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6190
6191 (define_insn "@pred_<optab><mode>"
6192 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6193 (if_then_else:V_VLSF
6194 (unspec:<VM>
6195 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6196 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6197 (match_operand 6 "const_int_operand" " i, i, i, i")
6198 (match_operand 7 "const_int_operand" " i, i, i, i")
6199 (match_operand 8 "const_int_operand" " i, i, i, i")
6200 (reg:SI VL_REGNUM)
6201 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6202 (any_float_binop_nofrm:V_VLSF
6203 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6204 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6205 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6206 "TARGET_VECTOR"
6207 "vf<insn>.vv\t%0,%3,%4%p1"
6208 [(set_attr "type" "<float_insn_type>")
6209 (set_attr "mode" "<MODE>")])
6210
6211 (define_insn "@pred_<ieee_fmaxmin_op><mode>"
6212 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6213 (if_then_else:V_VLSF
6214 (unspec:<VM>
6215 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6216 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6217 (match_operand 6 "const_int_operand" " i, i, i, i")
6218 (match_operand 7 "const_int_operand" " i, i, i, i")
6219 (match_operand 8 "const_int_operand" " i, i, i, i")
6220 (reg:SI VL_REGNUM)
6221 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6222 (unspec:V_VLSF
6223 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6224 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
6225 UNSPEC_VFMAXMIN)
6226 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6227 "TARGET_VECTOR"
6228 "v<ieee_fmaxmin_op>.vv\t%0,%3,%4%p1"
6229 [(set_attr "type" "vfminmax")
6230 (set_attr "mode" "<MODE>")])
6231
6232 (define_insn "@pred_<optab><mode>_scalar"
6233 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6234 (if_then_else:VF
6235 (unspec:<VM>
6236 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6237 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6238 (match_operand 6 "const_int_operand" " i, i, i, i")
6239 (match_operand 7 "const_int_operand" " i, i, i, i")
6240 (match_operand 8 "const_int_operand" " i, i, i, i")
6241 (match_operand 9 "const_int_operand" " i, i, i, i")
6242 (reg:SI VL_REGNUM)
6243 (reg:SI VTYPE_REGNUM)
6244 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6245 (commutative_float_binop:VF
6246 (vec_duplicate:VF
6247 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6248 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6249 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6250 "TARGET_VECTOR"
6251 "vf<insn>.vf\t%0,%3,%4%p1"
6252 [(set_attr "type" "<float_insn_type>")
6253 (set_attr "mode" "<MODE>")
6254 (set (attr "frm_mode")
6255 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6256
6257 (define_insn "@pred_<optab><mode>_scalar"
6258 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6259 (if_then_else:VF
6260 (unspec:<VM>
6261 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6262 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6263 (match_operand 6 "const_int_operand" " i, i, i, i")
6264 (match_operand 7 "const_int_operand" " i, i, i, i")
6265 (match_operand 8 "const_int_operand" " i, i, i, i")
6266 (reg:SI VL_REGNUM)
6267 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6268 (commutative_float_binop_nofrm:VF
6269 (vec_duplicate:VF
6270 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6271 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6272 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6273 "TARGET_VECTOR"
6274 "vf<insn>.vf\t%0,%3,%4%p1"
6275 [(set_attr "type" "<float_insn_type>")
6276 (set_attr "mode" "<MODE>")])
6277
6278 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
6279 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6280 (if_then_else:VF
6281 (unspec:<VM>
6282 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6283 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6284 (match_operand 6 "const_int_operand" " i, i, i, i")
6285 (match_operand 7 "const_int_operand" " i, i, i, i")
6286 (match_operand 8 "const_int_operand" " i, i, i, i")
6287 (reg:SI VL_REGNUM)
6288 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6289 (unspec:VF
6290 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6291 (vec_duplicate:VF
6292 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))]
6293 UNSPEC_VFMAXMIN)
6294 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6295 "TARGET_VECTOR"
6296 "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
6297 [(set_attr "type" "vfminmax")
6298 (set_attr "mode" "<MODE>")])
6299
6300 (define_insn "@pred_<optab><mode>_scalar"
6301 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6302 (if_then_else:VF
6303 (unspec:<VM>
6304 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6305 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6306 (match_operand 6 "const_int_operand" " i, i, i, i")
6307 (match_operand 7 "const_int_operand" " i, i, i, i")
6308 (match_operand 8 "const_int_operand" " i, i, i, i")
6309 (match_operand 9 "const_int_operand" " i, i, i, i")
6310 (reg:SI VL_REGNUM)
6311 (reg:SI VTYPE_REGNUM)
6312 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6313 (non_commutative_float_binop:VF
6314 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6315 (vec_duplicate:VF
6316 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
6317 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6318 "TARGET_VECTOR"
6319 "vf<insn>.vf\t%0,%3,%4%p1"
6320 [(set_attr "type" "<float_insn_type>")
6321 (set_attr "mode" "<MODE>")
6322 (set (attr "frm_mode")
6323 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6324
6325 (define_insn "@pred_<optab><mode>_reverse_scalar"
6326 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6327 (if_then_else:VF
6328 (unspec:<VM>
6329 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6330 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6331 (match_operand 6 "const_int_operand" " i, i, i, i")
6332 (match_operand 7 "const_int_operand" " i, i, i, i")
6333 (match_operand 8 "const_int_operand" " i, i, i, i")
6334 (match_operand 9 "const_int_operand" " i, i, i, i")
6335 (reg:SI VL_REGNUM)
6336 (reg:SI VTYPE_REGNUM)
6337 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6338 (non_commutative_float_binop:VF
6339 (vec_duplicate:VF
6340 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6341 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6342 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6343 "TARGET_VECTOR"
6344 "vfr<insn>.vf\t%0,%3,%4%p1"
6345 [(set_attr "type" "<float_insn_type>")
6346 (set_attr "mode" "<MODE>")
6347 (set (attr "frm_mode")
6348 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6349
6350 (define_insn "@pred_<copysign><mode>"
6351 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6352 (if_then_else:V_VLSF
6353 (unspec:<VM>
6354 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6355 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6356 (match_operand 6 "const_int_operand" " i, i, i, i")
6357 (match_operand 7 "const_int_operand" " i, i, i, i")
6358 (match_operand 8 "const_int_operand" " i, i, i, i")
6359 (reg:SI VL_REGNUM)
6360 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6361 (unspec:V_VLSF
6362 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6363 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
6364 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6365 "TARGET_VECTOR"
6366 "vfsgnj<nx>.vv\t%0,%3,%4%p1"
6367 [(set_attr "type" "vfsgnj")
6368 (set_attr "mode" "<MODE>")])
6369
6370 (define_insn "@pred_ncopysign<mode>"
6371 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6372 (if_then_else:VF
6373 (unspec:<VM>
6374 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6375 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6376 (match_operand 6 "const_int_operand" " i, i, i, i")
6377 (match_operand 7 "const_int_operand" " i, i, i, i")
6378 (match_operand 8 "const_int_operand" " i, i, i, i")
6379 (reg:SI VL_REGNUM)
6380 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6381 (neg:VF
6382 (unspec:VF
6383 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6384 (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
6385 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6386 "TARGET_VECTOR"
6387 "vfsgnjn.vv\t%0,%3,%4%p1"
6388 [(set_attr "type" "vfsgnj")
6389 (set_attr "mode" "<MODE>")])
6390
6391 (define_insn "@pred_<copysign><mode>_scalar"
6392 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6393 (if_then_else:V_VLSF
6394 (unspec:<VM>
6395 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6396 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6397 (match_operand 6 "const_int_operand" " i, i, i, i")
6398 (match_operand 7 "const_int_operand" " i, i, i, i")
6399 (match_operand 8 "const_int_operand" " i, i, i, i")
6400 (reg:SI VL_REGNUM)
6401 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6402 (unspec:V_VLSF
6403 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6404 (vec_duplicate:V_VLSF
6405 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
6406 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6407 "TARGET_VECTOR"
6408 "vfsgnj<nx>.vf\t%0,%3,%4%p1"
6409 [(set_attr "type" "vfsgnj")
6410 (set_attr "mode" "<MODE>")])
6411
6412 (define_insn "@pred_ncopysign<mode>_scalar"
6413 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6414 (if_then_else:VF
6415 (unspec:<VM>
6416 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6417 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6418 (match_operand 6 "const_int_operand" " i, i, i, i")
6419 (match_operand 7 "const_int_operand" " i, i, i, i")
6420 (match_operand 8 "const_int_operand" " i, i, i, i")
6421 (reg:SI VL_REGNUM)
6422 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6423 (neg:VF
6424 (unspec:VF
6425 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6426 (vec_duplicate:VF
6427 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
6428 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6429 "TARGET_VECTOR"
6430 "vfsgnjn.vf\t%0,%3,%4%p1"
6431 [(set_attr "type" "vfsgnj")
6432 (set_attr "mode" "<MODE>")])
6433
6434 ;; -------------------------------------------------------------------------------
6435 ;; ---- Predicated floating-point ternary operations
6436 ;; -------------------------------------------------------------------------------
6437 ;; Includes:
6438 ;; - 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6439 ;; -------------------------------------------------------------------------------
6440
6441 (define_expand "@pred_mul_<optab><mode>"
6442 [(set (match_operand:V_VLSF 0 "register_operand")
6443 (if_then_else:V_VLSF
6444 (unspec:<VM>
6445 [(match_operand:<VM> 1 "vector_mask_operand")
6446 (match_operand 6 "vector_length_operand")
6447 (match_operand 7 "const_int_operand")
6448 (match_operand 8 "const_int_operand")
6449 (match_operand 9 "const_int_operand")
6450 (match_operand 10 "const_int_operand")
6451 (reg:SI VL_REGNUM)
6452 (reg:SI VTYPE_REGNUM)
6453 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6454 (plus_minus:V_VLSF
6455 (mult:V_VLSF
6456 (match_operand:V_VLSF 2 "register_operand")
6457 (match_operand:V_VLSF 3 "register_operand"))
6458 (match_operand:V_VLSF 4 "register_operand"))
6459 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6460 "TARGET_VECTOR"
6461 {
6462 riscv_vector::prepare_ternary_operands (operands);
6463 })
6464
6465 (define_insn "*pred_mul_<optab><mode>_undef"
6466 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6467 (if_then_else:V_VLSF
6468 (unspec:<VM>
6469 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6470 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6471 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6472 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6473 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6474 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6475 (reg:SI VL_REGNUM)
6476 (reg:SI VTYPE_REGNUM)
6477 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6478 (plus_minus:V_VLSF
6479 (mult:V_VLSF
6480 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6481 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))
6482 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6483 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6484 "TARGET_VECTOR"
6485 "@
6486 vf<madd_msub>.vv\t%0,%4,%5%p1
6487 vf<macc_msac>.vv\t%0,%3,%4%p1
6488 vmv.v.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1
6489 vf<madd_msub>.vv\t%0,%4,%5%p1
6490 vf<macc_msac>.vv\t%0,%3,%4%p1
6491 vmv.v.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1"
6492 [(set_attr "type" "vfmuladd")
6493 (set_attr "mode" "<MODE>")
6494 (set (attr "frm_mode")
6495 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6496
6497 (define_insn "*pred_<madd_msub><mode>"
6498 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6499 (if_then_else:V_VLSF
6500 (unspec:<VM>
6501 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6502 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6503 (match_operand 6 "const_int_operand" " i, i, i, i")
6504 (match_operand 7 "const_int_operand" " i, i, i, i")
6505 (match_operand 8 "const_int_operand" " i, i, i, i")
6506 (match_operand 9 "const_int_operand" " i, i, i, i")
6507 (reg:SI VL_REGNUM)
6508 (reg:SI VTYPE_REGNUM)
6509 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6510 (plus_minus:V_VLSF
6511 (mult:V_VLSF
6512 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6513 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6514 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6515 (match_dup 2)))]
6516 "TARGET_VECTOR"
6517 "@
6518 vf<madd_msub>.vv\t%0,%3,%4%p1
6519 vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
6520 vf<madd_msub>.vv\t%0,%3,%4%p1
6521 vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
6522 [(set_attr "type" "vfmuladd")
6523 (set_attr "mode" "<MODE>")
6524 (set_attr "merge_op_idx" "4")
6525 (set_attr "vl_op_idx" "5")
6526 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6527 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6528 (set (attr "avl_type_idx") (const_int 8))
6529 (set (attr "frm_mode")
6530 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6531
6532 (define_insn "*pred_<macc_msac><mode>"
6533 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6534 (if_then_else:V_VLSF
6535 (unspec:<VM>
6536 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6537 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6538 (match_operand 6 "const_int_operand" " i, i, i, i")
6539 (match_operand 7 "const_int_operand" " i, i, i, i")
6540 (match_operand 8 "const_int_operand" " i, i, i, i")
6541 (match_operand 9 "const_int_operand" " i, i, i, i")
6542 (reg:SI VL_REGNUM)
6543 (reg:SI VTYPE_REGNUM)
6544 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6545 (plus_minus:V_VLSF
6546 (mult:V_VLSF
6547 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6548 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6549 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6550 (match_dup 4)))]
6551 "TARGET_VECTOR"
6552 "@
6553 vf<macc_msac>.vv\t%0,%2,%3%p1
6554 vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
6555 vf<macc_msac>.vv\t%0,%2,%3%p1
6556 vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
6557 [(set_attr "type" "vfmuladd")
6558 (set_attr "mode" "<MODE>")
6559 (set_attr "merge_op_idx" "2")
6560 (set_attr "vl_op_idx" "5")
6561 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6562 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6563 (set (attr "avl_type_idx") (const_int 8))
6564 (set (attr "frm_mode")
6565 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6566
6567 (define_expand "@pred_mul_<optab><mode>_scalar"
6568 [(set (match_operand:V_VLSF 0 "register_operand")
6569 (if_then_else:V_VLSF
6570 (unspec:<VM>
6571 [(match_operand:<VM> 1 "vector_mask_operand")
6572 (match_operand 6 "vector_length_operand")
6573 (match_operand 7 "const_int_operand")
6574 (match_operand 8 "const_int_operand")
6575 (match_operand 9 "const_int_operand")
6576 (match_operand 10 "const_int_operand")
6577 (reg:SI VL_REGNUM)
6578 (reg:SI VTYPE_REGNUM)
6579 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6580 (plus_minus:V_VLSF
6581 (mult:V_VLSF
6582 (vec_duplicate:V_VLSF
6583 (match_operand:<VEL> 2 "register_operand"))
6584 (match_operand:V_VLSF 3 "register_operand"))
6585 (match_operand:V_VLSF 4 "register_operand"))
6586 (match_operand:V_VLSF 5 "register_operand")))]
6587 "TARGET_VECTOR"
6588 {})
6589
6590 (define_insn "*pred_<madd_msub><mode>_scalar"
6591 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6592 (if_then_else:V_VLSF
6593 (unspec:<VM>
6594 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6595 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6596 (match_operand 6 "const_int_operand" " i, i, i, i")
6597 (match_operand 7 "const_int_operand" " i, i, i, i")
6598 (match_operand 8 "const_int_operand" " i, i, i, i")
6599 (match_operand 9 "const_int_operand" " i, i, i, i")
6600 (reg:SI VL_REGNUM)
6601 (reg:SI VTYPE_REGNUM)
6602 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6603 (plus_minus:V_VLSF
6604 (mult:V_VLSF
6605 (vec_duplicate:V_VLSF
6606 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6607 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))
6608 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6609 (match_dup 3)))]
6610 "TARGET_VECTOR"
6611 "@
6612 vf<madd_msub>.vf\t%0,%2,%4%p1
6613 vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
6614 vf<madd_msub>.vf\t%0,%2,%4%p1
6615 vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
6616 [(set_attr "type" "vfmuladd")
6617 (set_attr "mode" "<MODE>")
6618 (set_attr "merge_op_idx" "4")
6619 (set_attr "vl_op_idx" "5")
6620 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6621 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6622 (set (attr "avl_type_idx") (const_int 8))
6623 (set (attr "frm_mode")
6624 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6625
6626 (define_insn "*pred_<macc_msac><mode>_scalar"
6627 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6628 (if_then_else:V_VLSF
6629 (unspec:<VM>
6630 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6631 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6632 (match_operand 6 "const_int_operand" " i, i, i, i")
6633 (match_operand 7 "const_int_operand" " i, i, i, i")
6634 (match_operand 8 "const_int_operand" " i, i, i, i")
6635 (match_operand 9 "const_int_operand" " i, i, i, i")
6636 (reg:SI VL_REGNUM)
6637 (reg:SI VTYPE_REGNUM)
6638 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6639 (plus_minus:V_VLSF
6640 (mult:V_VLSF
6641 (vec_duplicate:V_VLSF
6642 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6643 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6644 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6645 (match_dup 4)))]
6646 "TARGET_VECTOR"
6647 "@
6648 vf<macc_msac>.vf\t%0,%2,%3%p1
6649 vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
6650 vf<macc_msac>.vf\t%0,%2,%3%p1
6651 vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
6652 [(set_attr "type" "vfmuladd")
6653 (set_attr "mode" "<MODE>")
6654 (set_attr "merge_op_idx" "2")
6655 (set_attr "vl_op_idx" "5")
6656 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6657 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6658 (set (attr "avl_type_idx") (const_int 8))
6659 (set (attr "frm_mode")
6660 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6661
6662 (define_expand "@pred_mul_neg_<optab><mode>"
6663 [(set (match_operand:V_VLSF 0 "register_operand")
6664 (if_then_else:V_VLSF
6665 (unspec:<VM>
6666 [(match_operand:<VM> 1 "vector_mask_operand")
6667 (match_operand 6 "vector_length_operand")
6668 (match_operand 7 "const_int_operand")
6669 (match_operand 8 "const_int_operand")
6670 (match_operand 9 "const_int_operand")
6671 (match_operand 10 "const_int_operand")
6672 (reg:SI VL_REGNUM)
6673 (reg:SI VTYPE_REGNUM)
6674 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6675 (plus_minus:V_VLSF
6676 (neg:V_VLSF
6677 (mult:V_VLSF
6678 (match_operand:V_VLSF 2 "register_operand")
6679 (match_operand:V_VLSF 3 "register_operand")))
6680 (match_operand:V_VLSF 4 "register_operand"))
6681 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6682 "TARGET_VECTOR"
6683 {
6684 riscv_vector::prepare_ternary_operands (operands);
6685 })
6686
6687 (define_insn "*pred_mul_neg_<optab><mode>_undef"
6688 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6689 (if_then_else:V_VLSF
6690 (unspec:<VM>
6691 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6692 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6693 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6694 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6695 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6696 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6697 (reg:SI VL_REGNUM)
6698 (reg:SI VTYPE_REGNUM)
6699 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6700 (plus_minus:V_VLSF
6701 (neg:V_VLSF
6702 (mult:V_VLSF
6703 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6704 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")))
6705 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6706 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6707 "TARGET_VECTOR"
6708 "@
6709 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6710 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6711 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6712 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6713 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6714 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1"
6715 [(set_attr "type" "vfmuladd")
6716 (set_attr "mode" "<MODE>")
6717 (set (attr "frm_mode")
6718 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6719
6720 (define_insn "*pred_<nmsub_nmadd><mode>"
6721 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6722 (if_then_else:V_VLSF
6723 (unspec:<VM>
6724 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6725 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6726 (match_operand 6 "const_int_operand" " i, i, i, i")
6727 (match_operand 7 "const_int_operand" " i, i, i, i")
6728 (match_operand 8 "const_int_operand" " i, i, i, i")
6729 (match_operand 9 "const_int_operand" " i, i, i, i")
6730 (reg:SI VL_REGNUM)
6731 (reg:SI VTYPE_REGNUM)
6732 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6733 (plus_minus:V_VLSF
6734 (neg:V_VLSF
6735 (mult:V_VLSF
6736 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6737 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6738 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6739 (match_dup 2)))]
6740 "TARGET_VECTOR"
6741 "@
6742 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6743 vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6744 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6745 vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
6746 [(set_attr "type" "vfmuladd")
6747 (set_attr "mode" "<MODE>")
6748 (set_attr "merge_op_idx" "4")
6749 (set_attr "vl_op_idx" "5")
6750 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6751 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6752 (set (attr "avl_type_idx") (const_int 8))
6753 (set (attr "frm_mode")
6754 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6755
6756 (define_insn "*pred_<nmsac_nmacc><mode>"
6757 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6758 (if_then_else:V_VLSF
6759 (unspec:<VM>
6760 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6761 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6762 (match_operand 6 "const_int_operand" " i, i, i, i")
6763 (match_operand 7 "const_int_operand" " i, i, i, i")
6764 (match_operand 8 "const_int_operand" " i, i, i, i")
6765 (match_operand 9 "const_int_operand" " i, i, i, i")
6766 (reg:SI VL_REGNUM)
6767 (reg:SI VTYPE_REGNUM)
6768 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6769 (plus_minus:V_VLSF
6770 (neg:V_VLSF
6771 (mult:V_VLSF
6772 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6773 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6774 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6775 (match_dup 4)))]
6776 "TARGET_VECTOR"
6777 "@
6778 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6779 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6780 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6781 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
6782 [(set_attr "type" "vfmuladd")
6783 (set_attr "mode" "<MODE>")
6784 (set_attr "merge_op_idx" "2")
6785 (set_attr "vl_op_idx" "5")
6786 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6787 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6788 (set (attr "avl_type_idx") (const_int 8))
6789 (set (attr "frm_mode")
6790 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6791
6792 (define_expand "@pred_mul_neg_<optab><mode>_scalar"
6793 [(set (match_operand:V_VLSF 0 "register_operand")
6794 (if_then_else:V_VLSF
6795 (unspec:<VM>
6796 [(match_operand:<VM> 1 "vector_mask_operand")
6797 (match_operand 6 "vector_length_operand")
6798 (match_operand 7 "const_int_operand")
6799 (match_operand 8 "const_int_operand")
6800 (match_operand 9 "const_int_operand")
6801 (match_operand 10 "const_int_operand")
6802 (reg:SI VL_REGNUM)
6803 (reg:SI VTYPE_REGNUM)
6804 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6805 (plus_minus:V_VLSF
6806 (neg:V_VLSF
6807 (mult:V_VLSF
6808 (vec_duplicate:V_VLSF
6809 (match_operand:<VEL> 2 "register_operand"))
6810 (match_operand:V_VLSF 3 "register_operand")))
6811 (match_operand:V_VLSF 4 "register_operand"))
6812 (match_operand:V_VLSF 5 "register_operand")))]
6813 "TARGET_VECTOR"
6814 {})
6815
6816 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
6817 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6818 (if_then_else:V_VLSF
6819 (unspec:<VM>
6820 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6821 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6822 (match_operand 6 "const_int_operand" " i, i, i, i")
6823 (match_operand 7 "const_int_operand" " i, i, i, i")
6824 (match_operand 8 "const_int_operand" " i, i, i, i")
6825 (match_operand 9 "const_int_operand" " i, i, i, i")
6826 (reg:SI VL_REGNUM)
6827 (reg:SI VTYPE_REGNUM)
6828 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6829 (plus_minus:V_VLSF
6830 (neg:V_VLSF
6831 (mult:V_VLSF
6832 (vec_duplicate:V_VLSF
6833 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6834 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")))
6835 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6836 (match_dup 3)))]
6837 "TARGET_VECTOR"
6838 "@
6839 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6840 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6841 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6842 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
6843 [(set_attr "type" "vfmuladd")
6844 (set_attr "mode" "<MODE>")
6845 (set_attr "merge_op_idx" "4")
6846 (set_attr "vl_op_idx" "5")
6847 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6848 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6849 (set (attr "avl_type_idx") (const_int 8))
6850 (set (attr "frm_mode")
6851 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6852
6853 (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
6854 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6855 (if_then_else:V_VLSF
6856 (unspec:<VM>
6857 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6858 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6859 (match_operand 6 "const_int_operand" " i, i, i, i")
6860 (match_operand 7 "const_int_operand" " i, i, i, i")
6861 (match_operand 8 "const_int_operand" " i, i, i, i")
6862 (match_operand 9 "const_int_operand" " i, i, i, i")
6863 (reg:SI VL_REGNUM)
6864 (reg:SI VTYPE_REGNUM)
6865 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6866 (plus_minus:V_VLSF
6867 (neg:V_VLSF
6868 (mult:V_VLSF
6869 (vec_duplicate:V_VLSF
6870 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6871 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6872 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6873 (match_dup 4)))]
6874 "TARGET_VECTOR"
6875 "@
6876 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6877 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6878 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6879 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
6880 [(set_attr "type" "vfmuladd")
6881 (set_attr "mode" "<MODE>")
6882 (set_attr "merge_op_idx" "2")
6883 (set_attr "vl_op_idx" "5")
6884 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6885 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6886 (set (attr "avl_type_idx") (const_int 8))
6887 (set (attr "frm_mode")
6888 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6889
6890 ;; -------------------------------------------------------------------------------
6891 ;; ---- Predicated floating-point unary operations
6892 ;; -------------------------------------------------------------------------------
6893 ;; Includes:
6894 ;; - 13.8 Vector Floating-Point Square-Root Instruction
6895 ;; - 13.9 Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6896 ;; - 13.10 Vector Floating-Point Reciprocal Estimate Instruction
6897 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions (vfneg.v/vfabs.v)
6898 ;; - 13.14 Vector Floating-Point Classify Instruction
6899 ;; -------------------------------------------------------------------------------
6900
6901 (define_insn "@pred_<optab><mode>"
6902 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6903 (if_then_else:V_VLSF
6904 (unspec:<VM>
6905 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6906 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6907 (match_operand 5 "const_int_operand" " i, i, i, i")
6908 (match_operand 6 "const_int_operand" " i, i, i, i")
6909 (match_operand 7 "const_int_operand" " i, i, i, i")
6910 (match_operand 8 "const_int_operand" " i, i, i, i")
6911 (reg:SI VL_REGNUM)
6912 (reg:SI VTYPE_REGNUM)
6913 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6914 (any_float_unop:V_VLSF
6915 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6916 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6917 "TARGET_VECTOR"
6918 "vf<insn>.v\t%0,%3%p1"
6919 [(set_attr "type" "<float_insn_type>")
6920 (set_attr "mode" "<MODE>")
6921 (set_attr "vl_op_idx" "4")
6922 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6923 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6924 (set (attr "avl_type_idx") (const_int 7))
6925 (set (attr "frm_mode")
6926 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6927
6928 (define_insn "@pred_<optab><mode>"
6929 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6930 (if_then_else:V_VLSF
6931 (unspec:<VM>
6932 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6933 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6934 (match_operand 5 "const_int_operand" " i, i, i, i")
6935 (match_operand 6 "const_int_operand" " i, i, i, i")
6936 (match_operand 7 "const_int_operand" " i, i, i, i")
6937 (reg:SI VL_REGNUM)
6938 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6939 (any_float_unop_nofrm:V_VLSF
6940 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6941 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6942 "TARGET_VECTOR"
6943 "vf<insn>.v\t%0,%3%p1"
6944 [(set_attr "type" "<float_insn_type>")
6945 (set_attr "mode" "<MODE>")
6946 (set_attr "vl_op_idx" "4")
6947 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6948 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6949 (set (attr "avl_type_idx") (const_int 7))])
6950
6951 (define_insn "@pred_<misc_op><mode>"
6952 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6953 (if_then_else:VF
6954 (unspec:<VM>
6955 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6956 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6957 (match_operand 5 "const_int_operand" " i, i, i, i")
6958 (match_operand 6 "const_int_operand" " i, i, i, i")
6959 (match_operand 7 "const_int_operand" " i, i, i, i")
6960 (reg:SI VL_REGNUM)
6961 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6962 (unspec:VF
6963 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
6964 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6965 "TARGET_VECTOR"
6966 "vf<misc_op>.v\t%0,%3%p1"
6967 [(set_attr "type" "<float_insn_type>")
6968 (set_attr "mode" "<MODE>")])
6969
6970 (define_insn "@pred_<misc_frm_op><mode>"
6971 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6972 (if_then_else:VF
6973 (unspec:<VM>
6974 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6975 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6976 (match_operand 5 "const_int_operand" " i, i, i, i")
6977 (match_operand 6 "const_int_operand" " i, i, i, i")
6978 (match_operand 7 "const_int_operand" " i, i, i, i")
6979 (match_operand 8 "const_int_operand" " i, i, i, i")
6980 (reg:SI VL_REGNUM)
6981 (reg:SI VTYPE_REGNUM)
6982 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6983 (unspec:VF
6984 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
6985 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6986 "TARGET_VECTOR"
6987 "vf<misc_frm_op>.v\t%0,%3%p1"
6988 [(set_attr "type" "<float_frm_insn_type>")
6989 (set_attr "mode" "<MODE>")
6990 (set (attr "frm_mode")
6991 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6992
6993 (define_insn "@pred_class<mode>"
6994 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
6995 (if_then_else:<VCONVERT>
6996 (unspec:<VM>
6997 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6998 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6999 (match_operand 5 "const_int_operand" " i, i, i, i")
7000 (match_operand 6 "const_int_operand" " i, i, i, i")
7001 (match_operand 7 "const_int_operand" " i, i, i, i")
7002 (reg:SI VL_REGNUM)
7003 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7004 (unspec:<VCONVERT>
7005 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
7006 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7007 "TARGET_VECTOR"
7008 "vfclass.v\t%0,%3%p1"
7009 [(set_attr "type" "vfclass")
7010 (set_attr "mode" "<MODE>")])
7011
7012 ;; -------------------------------------------------------------------------------
7013 ;; ---- Predicated floating-point widen binary operations
7014 ;; -------------------------------------------------------------------------------
7015 ;; Includes:
7016 ;; - 13.3 Vector Widening Floating-Point Add/Subtract Instructions
7017 ;; - 13.5 Vector Widening Floating-Point Multiply
7018 ;; -------------------------------------------------------------------------------
7019
7020 ;; Vector Widening Add/Subtract/Multiply.
7021 (define_insn "@pred_dual_widen_<optab><mode>"
7022 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7023 (if_then_else:VWEXTF
7024 (unspec:<VM>
7025 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7026 (match_operand 5 "vector_length_operand" " rK, rK")
7027 (match_operand 6 "const_int_operand" " i, i")
7028 (match_operand 7 "const_int_operand" " i, i")
7029 (match_operand 8 "const_int_operand" " i, i")
7030 (match_operand 9 "const_int_operand" " i, i")
7031 (reg:SI VL_REGNUM)
7032 (reg:SI VTYPE_REGNUM)
7033 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7034 (any_widen_binop:VWEXTF
7035 (float_extend:VWEXTF
7036 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7037 (float_extend:VWEXTF
7038 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7039 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7040 "TARGET_VECTOR"
7041 "vfw<insn>.vv\t%0,%3,%4%p1"
7042 [(set_attr "type" "vf<widen_binop_insn_type>")
7043 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7044 (set (attr "frm_mode")
7045 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7046
7047 (define_insn "@pred_dual_widen_<optab><mode>_scalar"
7048 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7049 (if_then_else:VWEXTF
7050 (unspec:<VM>
7051 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7052 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7053 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7054 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7055 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7056 (match_operand 9 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7057 (reg:SI VL_REGNUM)
7058 (reg:SI VTYPE_REGNUM)
7059 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7060 (any_widen_binop:VWEXTF
7061 (float_extend:VWEXTF
7062 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7063 (float_extend:VWEXTF
7064 (vec_duplicate:<V_DOUBLE_TRUNC>
7065 (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f, f, f, f, f, f, f, f, f, f, f"))))
7066 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7067 "TARGET_VECTOR"
7068 "vfw<insn>.vf\t%0,%3,%4%p1"
7069 [(set_attr "type" "vf<widen_binop_insn_type>")
7070 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7071 (set (attr "frm_mode")
7072 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7073 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7074
7075 (define_insn "@pred_single_widen_add<mode>"
7076 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
7077 (if_then_else:VWEXTF
7078 (unspec:<VM>
7079 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
7080 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7081 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7082 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7083 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7084 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7085 (reg:SI VL_REGNUM)
7086 (reg:SI VTYPE_REGNUM)
7087 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7088 (plus:VWEXTF
7089 (float_extend:VWEXTF
7090 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr"))
7091 (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr"))
7092 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
7093 "TARGET_VECTOR"
7094 "vfwadd.wv\t%0,%3,%4%p1"
7095 [(set_attr "type" "vfwalu")
7096 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7097 (set (attr "frm_mode")
7098 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7099 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
7100
7101 (define_insn "@pred_single_widen_sub<mode>"
7102 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
7103 (if_then_else:VWEXTF
7104 (unspec:<VM>
7105 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
7106 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7107 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7108 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7109 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7110 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7111 (reg:SI VL_REGNUM)
7112 (reg:SI VTYPE_REGNUM)
7113 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7114 (minus:VWEXTF
7115 (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr")
7116 (float_extend:VWEXTF
7117 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr")))
7118 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
7119 "TARGET_VECTOR"
7120 "vfwsub.wv\t%0,%3,%4%p1"
7121 [(set_attr "type" "vfwalu")
7122 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7123 (set (attr "frm_mode")
7124 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7125 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
7126
7127 (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
7128 [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
7129 (if_then_else:VWEXTF
7130 (unspec:<VM>
7131 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7132 (match_operand 5 "vector_length_operand" " rK, rK")
7133 (match_operand 6 "const_int_operand" " i, i")
7134 (match_operand 7 "const_int_operand" " i, i")
7135 (match_operand 8 "const_int_operand" " i, i")
7136 (match_operand 9 "const_int_operand" " i, i")
7137 (reg:SI VL_REGNUM)
7138 (reg:SI VTYPE_REGNUM)
7139 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7140 (plus_minus:VWEXTF
7141 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7142 (float_extend:VWEXTF
7143 (vec_duplicate:<V_DOUBLE_TRUNC>
7144 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7145 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7146 "TARGET_VECTOR"
7147 "vfw<insn>.wf\t%0,%3,%4%p1"
7148 [(set_attr "type" "vf<widen_binop_insn_type>")
7149 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7150 (set (attr "frm_mode")
7151 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7152
7153 ;; -------------------------------------------------------------------------------
7154 ;; ---- Predicated widen floating-point ternary operations
7155 ;; -------------------------------------------------------------------------------
7156 ;; Includes:
7157 ;; - 13.7 Vector Widening Floating-Point Fused Multiply-Add Instructions
7158 ;; -------------------------------------------------------------------------------
7159
7160 (define_insn "@pred_widen_mul_<optab><mode>"
7161 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7162 (if_then_else:VWEXTF
7163 (unspec:<VM>
7164 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7165 (match_operand 5 "vector_length_operand" " rK")
7166 (match_operand 6 "const_int_operand" " i")
7167 (match_operand 7 "const_int_operand" " i")
7168 (match_operand 8 "const_int_operand" " i")
7169 (match_operand 9 "const_int_operand" " i")
7170 (reg:SI VL_REGNUM)
7171 (reg:SI VTYPE_REGNUM)
7172 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7173 (plus_minus:VWEXTF
7174 (mult:VWEXTF
7175 (float_extend:VWEXTF
7176 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7177 (float_extend:VWEXTF
7178 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7179 (match_operand:VWEXTF 2 "register_operand" " 0"))
7180 (match_dup 2)))]
7181 "TARGET_VECTOR"
7182 "vfw<macc_msac>.vv\t%0,%3,%4%p1"
7183 [(set_attr "type" "vfwmuladd")
7184 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7185 (set (attr "frm_mode")
7186 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7187
7188 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
7189 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
7190 (if_then_else:VWEXTF
7191 (unspec:<VM>
7192 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
7193 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
7194 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
7195 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
7196 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
7197 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i")
7198 (reg:SI VL_REGNUM)
7199 (reg:SI VTYPE_REGNUM)
7200 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7201 (plus_minus:VWEXTF
7202 (mult:VWEXTF
7203 (float_extend:VWEXTF
7204 (vec_duplicate:<V_DOUBLE_TRUNC>
7205 (match_operand:<VSUBEL> 3 "register_operand" " f, f, f, f, f, f, f")))
7206 (float_extend:VWEXTF
7207 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
7208 (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
7209 (match_dup 2)))]
7210 "TARGET_VECTOR"
7211 "vfw<macc_msac>.vf\t%0,%3,%4%p1"
7212 [(set_attr "type" "vfwmuladd")
7213 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7214 (set (attr "frm_mode")
7215 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7216 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
7217
7218 (define_insn "@pred_widen_mul_neg_<optab><mode>"
7219 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7220 (if_then_else:VWEXTF
7221 (unspec:<VM>
7222 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7223 (match_operand 5 "vector_length_operand" " rK")
7224 (match_operand 6 "const_int_operand" " i")
7225 (match_operand 7 "const_int_operand" " i")
7226 (match_operand 8 "const_int_operand" " i")
7227 (match_operand 9 "const_int_operand" " i")
7228 (reg:SI VL_REGNUM)
7229 (reg:SI VTYPE_REGNUM)
7230 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7231 (plus_minus:VWEXTF
7232 (neg:VWEXTF
7233 (mult:VWEXTF
7234 (float_extend:VWEXTF
7235 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7236 (float_extend:VWEXTF
7237 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7238 (match_operand:VWEXTF 2 "register_operand" " 0"))
7239 (match_dup 2)))]
7240 "TARGET_VECTOR"
7241 "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
7242 [(set_attr "type" "vfwmuladd")
7243 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7244 (set (attr "frm_mode")
7245 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7246
7247 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
7248 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
7249 (if_then_else:VWEXTF
7250 (unspec:<VM>
7251 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
7252 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
7253 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
7254 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
7255 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
7256 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i")
7257 (reg:SI VL_REGNUM)
7258 (reg:SI VTYPE_REGNUM)
7259 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7260 (plus_minus:VWEXTF
7261 (neg:VWEXTF
7262 (mult:VWEXTF
7263 (float_extend:VWEXTF
7264 (vec_duplicate:<V_DOUBLE_TRUNC>
7265 (match_operand:<VSUBEL> 3 "register_operand" " f, f, f, f, f, f, f")))
7266 (float_extend:VWEXTF
7267 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))))
7268 (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
7269 (match_dup 2)))]
7270 "TARGET_VECTOR"
7271 "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
7272 [(set_attr "type" "vfwmuladd")
7273 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7274 (set (attr "frm_mode")
7275 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7276 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
7277
7278 ;; -------------------------------------------------------------------------------
7279 ;; ---- Predicated floating-point comparison operations
7280 ;; -------------------------------------------------------------------------------
7281 ;; Includes:
7282 ;; - 13.13 Vector Floating-Point Compare Instructions
7283 ;; -------------------------------------------------------------------------------
7284
7285 (define_expand "@pred_cmp<mode>"
7286 [(set (match_operand:<VM> 0 "register_operand")
7287 (if_then_else:<VM>
7288 (unspec:<VM>
7289 [(match_operand:<VM> 1 "vector_mask_operand")
7290 (match_operand 6 "vector_length_operand")
7291 (match_operand 7 "const_int_operand")
7292 (match_operand 8 "const_int_operand")
7293 (reg:SI VL_REGNUM)
7294 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7295 (match_operator:<VM> 3 "signed_order_operator"
7296 [(match_operand:V_VLSF 4 "register_operand")
7297 (match_operand:V_VLSF 5 "register_operand")])
7298 (match_operand:<VM> 2 "vector_merge_operand")))]
7299 "TARGET_VECTOR"
7300 {})
7301
7302 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7303 (define_insn "*pred_cmp<mode>"
7304 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7305 (if_then_else:<VM>
7306 (unspec:<VM>
7307 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7308 (match_operand 6 "vector_length_operand" " rK, rK")
7309 (match_operand 7 "const_int_operand" " i, i")
7310 (match_operand 8 "const_int_operand" " i, i")
7311 (reg:SI VL_REGNUM)
7312 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7313 (match_operator:<VM> 3 "signed_order_operator"
7314 [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
7315 (match_operand:V_VLSF 5 "register_operand" " vr, vr")])
7316 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7317 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7318 "vmf%B3.vv\t%0,%4,%5%p1"
7319 [(set_attr "type" "vfcmp")
7320 (set_attr "mode" "<MODE>")])
7321
7322 (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
7323 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7324 (if_then_else:<VM>
7325 (unspec:<VM>
7326 [(match_operand:<VM> 1 "register_operand" " 0")
7327 (match_operand 5 "vector_length_operand" " rK")
7328 (match_operand 6 "const_int_operand" " i")
7329 (match_operand 7 "const_int_operand" " i")
7330 (reg:SI VL_REGNUM)
7331 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7332 (match_operator:<VM> 2 "signed_order_operator"
7333 [(match_operand:V_VLSF 3 "register_operand" " vr")
7334 (match_operand:V_VLSF 4 "register_operand" " vr")])
7335 (match_dup 1)))]
7336 "TARGET_VECTOR"
7337 "vmf%B2.vv\t%0,%3,%4,v0.t"
7338 [(set_attr "type" "vfcmp")
7339 (set_attr "mode" "<MODE>")
7340 (set_attr "merge_op_idx" "1")
7341 (set_attr "vl_op_idx" "5")
7342 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7343 (set (attr "avl_type_idx") (const_int 7))])
7344
7345 ;; We use early-clobber for source LMUL > dest LMUL.
7346 (define_insn "*pred_cmp<mode>_narrow"
7347 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
7348 (if_then_else:<VM>
7349 (unspec:<VM>
7350 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7351 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
7352 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7353 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7354 (reg:SI VL_REGNUM)
7355 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7356 (match_operator:<VM> 3 "signed_order_operator"
7357 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
7358 (match_operand:V_VLSF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
7359 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
7360 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7361 "vmf%B3.vv\t%0,%4,%5%p1"
7362 [(set_attr "type" "vfcmp")
7363 (set_attr "mode" "<MODE>")])
7364
7365 (define_expand "@pred_cmp<mode>_scalar"
7366 [(set (match_operand:<VM> 0 "register_operand")
7367 (if_then_else:<VM>
7368 (unspec:<VM>
7369 [(match_operand:<VM> 1 "vector_mask_operand")
7370 (match_operand 6 "vector_length_operand")
7371 (match_operand 7 "const_int_operand")
7372 (match_operand 8 "const_int_operand")
7373 (reg:SI VL_REGNUM)
7374 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7375 (match_operator:<VM> 3 "signed_order_operator"
7376 [(match_operand:V_VLSF 4 "register_operand")
7377 (vec_duplicate:V_VLSF
7378 (match_operand:<VEL> 5 "register_operand"))])
7379 (match_operand:<VM> 2 "vector_merge_operand")))]
7380 "TARGET_VECTOR"
7381 {})
7382
7383 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
7384 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7385 (if_then_else:<VM>
7386 (unspec:<VM>
7387 [(match_operand:<VM> 1 "register_operand" " 0")
7388 (match_operand 5 "vector_length_operand" " rK")
7389 (match_operand 6 "const_int_operand" " i")
7390 (match_operand 7 "const_int_operand" " i")
7391 (reg:SI VL_REGNUM)
7392 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7393 (match_operator:<VM> 2 "signed_order_operator"
7394 [(match_operand:V_VLSF 3 "register_operand" " vr")
7395 (vec_duplicate:V_VLSF
7396 (match_operand:<VEL> 4 "register_operand" " f"))])
7397 (match_dup 1)))]
7398 "TARGET_VECTOR"
7399 "vmf%B2.vf\t%0,%3,%4,v0.t"
7400 [(set_attr "type" "vfcmp")
7401 (set_attr "mode" "<MODE>")
7402 (set_attr "merge_op_idx" "1")
7403 (set_attr "vl_op_idx" "5")
7404 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7405 (set (attr "avl_type_idx") (const_int 7))])
7406
7407 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7408 (define_insn "*pred_cmp<mode>_scalar"
7409 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7410 (if_then_else:<VM>
7411 (unspec:<VM>
7412 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7413 (match_operand 6 "vector_length_operand" " rK, rK")
7414 (match_operand 7 "const_int_operand" " i, i")
7415 (match_operand 8 "const_int_operand" " i, i")
7416 (reg:SI VL_REGNUM)
7417 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7418 (match_operator:<VM> 3 "signed_order_operator"
7419 [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
7420 (vec_duplicate:V_VLSF
7421 (match_operand:<VEL> 5 "register_operand" " f, f"))])
7422 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7423 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7424 "vmf%B3.vf\t%0,%4,%5%p1"
7425 [(set_attr "type" "vfcmp")
7426 (set_attr "mode" "<MODE>")])
7427
7428 ;; We use early-clobber for source LMUL > dest LMUL.
7429 (define_insn "*pred_cmp<mode>_scalar_narrow"
7430 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7431 (if_then_else:<VM>
7432 (unspec:<VM>
7433 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7434 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7435 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7436 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7437 (reg:SI VL_REGNUM)
7438 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7439 (match_operator:<VM> 3 "signed_order_operator"
7440 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")
7441 (vec_duplicate:V_VLSF
7442 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
7443 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7444 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7445 "vmf%B3.vf\t%0,%4,%5%p1"
7446 [(set_attr "type" "vfcmp")
7447 (set_attr "mode" "<MODE>")])
7448
7449 (define_expand "@pred_eqne<mode>_scalar"
7450 [(set (match_operand:<VM> 0 "register_operand")
7451 (if_then_else:<VM>
7452 (unspec:<VM>
7453 [(match_operand:<VM> 1 "vector_mask_operand")
7454 (match_operand 6 "vector_length_operand")
7455 (match_operand 7 "const_int_operand")
7456 (match_operand 8 "const_int_operand")
7457 (reg:SI VL_REGNUM)
7458 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7459 (match_operator:<VM> 3 "equality_operator"
7460 [(vec_duplicate:V_VLSF
7461 (match_operand:<VEL> 5 "register_operand"))
7462 (match_operand:V_VLSF 4 "register_operand")])
7463 (match_operand:<VM> 2 "vector_merge_operand")))]
7464 "TARGET_VECTOR"
7465 {})
7466
7467 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
7468 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7469 (if_then_else:<VM>
7470 (unspec:<VM>
7471 [(match_operand:<VM> 1 "register_operand" " 0")
7472 (match_operand 5 "vector_length_operand" " rK")
7473 (match_operand 6 "const_int_operand" " i")
7474 (match_operand 7 "const_int_operand" " i")
7475 (reg:SI VL_REGNUM)
7476 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7477 (match_operator:<VM> 2 "equality_operator"
7478 [(vec_duplicate:V_VLSF
7479 (match_operand:<VEL> 4 "register_operand" " f"))
7480 (match_operand:V_VLSF 3 "register_operand" " vr")])
7481 (match_dup 1)))]
7482 "TARGET_VECTOR"
7483 "vmf%B2.vf\t%0,%3,%4,v0.t"
7484 [(set_attr "type" "vfcmp")
7485 (set_attr "mode" "<MODE>")
7486 (set_attr "merge_op_idx" "1")
7487 (set_attr "vl_op_idx" "5")
7488 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7489 (set (attr "avl_type_idx") (const_int 7))])
7490
7491 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7492 (define_insn "*pred_eqne<mode>_scalar"
7493 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7494 (if_then_else:<VM>
7495 (unspec:<VM>
7496 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7497 (match_operand 6 "vector_length_operand" " rK, rK")
7498 (match_operand 7 "const_int_operand" " i, i")
7499 (match_operand 8 "const_int_operand" " i, i")
7500 (reg:SI VL_REGNUM)
7501 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7502 (match_operator:<VM> 3 "equality_operator"
7503 [(vec_duplicate:V_VLSF
7504 (match_operand:<VEL> 5 "register_operand" " f, f"))
7505 (match_operand:V_VLSF 4 "register_operand" " vr, vr")])
7506 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7507 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7508 "vmf%B3.vf\t%0,%4,%5%p1"
7509 [(set_attr "type" "vfcmp")
7510 (set_attr "mode" "<MODE>")])
7511
7512 ;; We use early-clobber for source LMUL > dest LMUL.
7513 (define_insn "*pred_eqne<mode>_scalar_narrow"
7514 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7515 (if_then_else:<VM>
7516 (unspec:<VM>
7517 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7518 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7519 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7520 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7521 (reg:SI VL_REGNUM)
7522 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7523 (match_operator:<VM> 3 "equality_operator"
7524 [(vec_duplicate:V_VLSF
7525 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
7526 (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
7527 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7528 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7529 "vmf%B3.vf\t%0,%4,%5%p1"
7530 [(set_attr "type" "vfcmp")
7531 (set_attr "mode" "<MODE>")])
7532
7533 ;; -------------------------------------------------------------------------------
7534 ;; ---- Predicated floating-point merge
7535 ;; -------------------------------------------------------------------------------
7536 ;; Includes:
7537 ;; - 13.15 Vector Floating-Point Merge Instruction
7538 ;; -------------------------------------------------------------------------------
7539
7540 (define_insn "@pred_merge<mode>_scalar"
7541 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
7542 (if_then_else:V_VLSF
7543 (unspec:<VM>
7544 [(match_operand 5 "vector_length_operand" " rK,rK")
7545 (match_operand 6 "const_int_operand" " i, i")
7546 (match_operand 7 "const_int_operand" " i, i")
7547 (reg:SI VL_REGNUM)
7548 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7549 (vec_merge:V_VLSF
7550 (vec_duplicate:V_VLSF
7551 (match_operand:<VEL> 3 "register_operand" " f, f"))
7552 (match_operand:V_VLSF 2 "register_operand" " vr,vr")
7553 (match_operand:<VM> 4 "register_operand" " vm,vm"))
7554 (match_operand:V_VLSF 1 "vector_merge_operand" " vu, 0")))]
7555 "TARGET_VECTOR"
7556 "vfmerge.vfm\t%0,%2,%3,%4"
7557 [(set_attr "type" "vfmerge")
7558 (set_attr "mode" "<MODE>")])
7559
7560 ;; -------------------------------------------------------------------------------
7561 ;; ---- Predicated floating-point conversions
7562 ;; -------------------------------------------------------------------------------
7563 ;; Includes:
7564 ;; - 13.17 Single-Width Floating-Point/Integer Type-Convert Instructions
7565 ;; -------------------------------------------------------------------------------
7566
7567 (define_insn "@pred_fcvt_x<v_su>_f<mode>"
7568 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7569 (if_then_else:<VCONVERT>
7570 (unspec:<VM>
7571 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7572 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7573 (match_operand 5 "const_int_operand" " i, i, i, i")
7574 (match_operand 6 "const_int_operand" " i, i, i, i")
7575 (match_operand 7 "const_int_operand" " i, i, i, i")
7576 (match_operand 8 "const_int_operand" " i, i, i, i")
7577 (reg:SI VL_REGNUM)
7578 (reg:SI VTYPE_REGNUM)
7579 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7580 (unspec:<VCONVERT>
7581 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
7582 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7583 "TARGET_VECTOR"
7584 "vfcvt.x<v_su>.f.v\t%0,%3%p1"
7585 [(set_attr "type" "vfcvtftoi")
7586 (set_attr "mode" "<MODE>")
7587 (set (attr "frm_mode")
7588 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7589
7590 (define_insn "@pred_<fix_cvt><mode>"
7591 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7592 (if_then_else:<VCONVERT>
7593 (unspec:<VM>
7594 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7595 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7596 (match_operand 5 "const_int_operand" " i, i, i, i")
7597 (match_operand 6 "const_int_operand" " i, i, i, i")
7598 (match_operand 7 "const_int_operand" " i, i, i, i")
7599 (reg:SI VL_REGNUM)
7600 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7601 (any_fix:<VCONVERT>
7602 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7603 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7604 "TARGET_VECTOR"
7605 "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
7606 [(set_attr "type" "vfcvtftoi")
7607 (set_attr "mode" "<MODE>")])
7608
7609 (define_insn "@pred_<float_cvt><mode>"
7610 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7611 (if_then_else:V_VLSF
7612 (unspec:<VM>
7613 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7614 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7615 (match_operand 5 "const_int_operand" " i, i, i, i")
7616 (match_operand 6 "const_int_operand" " i, i, i, i")
7617 (match_operand 7 "const_int_operand" " i, i, i, i")
7618 (match_operand 8 "const_int_operand" " i, i, i, i")
7619 (reg:SI VL_REGNUM)
7620 (reg:SI VTYPE_REGNUM)
7621 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7622 (any_float:V_VLSF
7623 (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
7624 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7625 "TARGET_VECTOR"
7626 "vfcvt.f.x<u>.v\t%0,%3%p1"
7627 [(set_attr "type" "vfcvtitof")
7628 (set_attr "mode" "<MODE>")
7629 (set (attr "frm_mode")
7630 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7631
7632 ;; -------------------------------------------------------------------------------
7633 ;; ---- Predicated floating-point widen conversions
7634 ;; -------------------------------------------------------------------------------
7635 ;; Includes:
7636 ;; - 13.18 Widening Floating-Point/Integer Type-Convert Instructions
7637 ;; -------------------------------------------------------------------------------
7638
7639 (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
7640 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7641 (if_then_else:VWCONVERTI
7642 (unspec:<VM>
7643 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7644 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7645 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7646 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7647 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7648 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7649 (reg:SI VL_REGNUM)
7650 (reg:SI VTYPE_REGNUM)
7651 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7652 (unspec:VWCONVERTI
7653 [(match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] VFCVTS)
7654 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7655 "TARGET_VECTOR"
7656 "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
7657 [(set_attr "type" "vfwcvtftoi")
7658 (set_attr "mode" "<VNCONVERT>")
7659 (set (attr "frm_mode")
7660 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7661 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7662
7663 (define_insn "@pred_widen_<fix_cvt><mode>"
7664 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7665 (if_then_else:VWCONVERTI
7666 (unspec:<VM>
7667 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7668 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7669 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7670 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7671 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7672 (reg:SI VL_REGNUM)
7673 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7674 (any_fix:VWCONVERTI
7675 (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7676 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7677 "TARGET_VECTOR"
7678 "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
7679 [(set_attr "type" "vfwcvtftoi")
7680 (set_attr "mode" "<VNCONVERT>")
7681 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7682
7683 (define_insn "@pred_widen_<float_cvt><mode>"
7684 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7685 (if_then_else:V_VLSF
7686 (unspec:<VM>
7687 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7688 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7689 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7690 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7691 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7692 (reg:SI VL_REGNUM)
7693 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7694 (any_float:V_VLSF
7695 (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7696 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7697 "TARGET_VECTOR"
7698 "vfwcvt.f.x<u>.v\t%0,%3%p1"
7699 [(set_attr "type" "vfwcvtitof")
7700 (set_attr "mode" "<VNCONVERT>")
7701 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7702
7703 (define_insn "@pred_extend<mode>"
7704 [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7705 (if_then_else:VWEXTF_ZVFHMIN
7706 (unspec:<VM>
7707 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7708 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7709 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7710 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7711 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7712 (reg:SI VL_REGNUM)
7713 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7714 (float_extend:VWEXTF_ZVFHMIN
7715 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7716 (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7717 "TARGET_VECTOR"
7718 "vfwcvt.f.f.v\t%0,%3%p1"
7719 [(set_attr "type" "vfwcvtftof")
7720 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7721 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7722
7723 ;; -------------------------------------------------------------------------------
7724 ;; ---- Predicated floating-point narrow conversions
7725 ;; -------------------------------------------------------------------------------
7726 ;; Includes:
7727 ;; - 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
7728 ;; -------------------------------------------------------------------------------
7729
7730 (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
7731 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7732 (if_then_else:<VNCONVERT>
7733 (unspec:<VM>
7734 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7735 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7736 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7737 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7738 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7739 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7740 (reg:SI VL_REGNUM)
7741 (reg:SI VTYPE_REGNUM)
7742 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7743 (unspec:<VNCONVERT>
7744 [(match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
7745 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7746 "TARGET_VECTOR"
7747 "vfncvt.x<v_su>.f.w\t%0,%3%p1"
7748 [(set_attr "type" "vfncvtftoi")
7749 (set_attr "mode" "<VNCONVERT>")
7750 (set (attr "frm_mode")
7751 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7752
7753 (define_insn "@pred_narrow_<fix_cvt><mode>"
7754 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7755 (if_then_else:<VNCONVERT>
7756 (unspec:<VM>
7757 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7758 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7759 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7760 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7761 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7762 (reg:SI VL_REGNUM)
7763 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7764 (any_fix:<VNCONVERT>
7765 (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7766 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7767 "TARGET_VECTOR"
7768 "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
7769 [(set_attr "type" "vfncvtftoi")
7770 (set_attr "mode" "<VNCONVERT>")])
7771
7772 (define_insn "@pred_narrow_<float_cvt><mode>"
7773 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7774 (if_then_else:<VNCONVERT>
7775 (unspec:<VM>
7776 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7777 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7778 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7779 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7780 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7781 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7782 (reg:SI VL_REGNUM)
7783 (reg:SI VTYPE_REGNUM)
7784 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7785 (any_float:<VNCONVERT>
7786 (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7787 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7788 "TARGET_VECTOR"
7789 "vfncvt.f.x<u>.w\t%0,%3%p1"
7790 [(set_attr "type" "vfncvtitof")
7791 (set_attr "mode" "<VNCONVERT>")
7792 (set (attr "frm_mode")
7793 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7794
7795 (define_insn "@pred_trunc<mode>"
7796 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7797 (if_then_else:<V_DOUBLE_TRUNC>
7798 (unspec:<VM>
7799 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7800 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7801 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7802 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7803 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7804 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7805 (reg:SI VL_REGNUM)
7806 (reg:SI VTYPE_REGNUM)
7807 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7808 (float_truncate:<V_DOUBLE_TRUNC>
7809 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7810 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7811 "TARGET_VECTOR"
7812 "vfncvt.f.f.w\t%0,%3%p1"
7813 [(set_attr "type" "vfncvtftof")
7814 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7815 (set (attr "frm_mode")
7816 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7817
7818 (define_insn "@pred_rod_trunc<mode>"
7819 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7820 (if_then_else:<V_DOUBLE_TRUNC>
7821 (unspec:<VM>
7822 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7823 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7824 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7825 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7826 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7827 (reg:SI VL_REGNUM)
7828 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7829 (unspec:<V_DOUBLE_TRUNC>
7830 [(float_truncate:<V_DOUBLE_TRUNC>
7831 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
7832 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7833 "TARGET_VECTOR"
7834 "vfncvt.rod.f.f.w\t%0,%3%p1"
7835 [(set_attr "type" "vfncvtftof")
7836 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7837
7838 ;; -------------------------------------------------------------------------------
7839 ;; ---- Predicated reduction operations
7840 ;; -------------------------------------------------------------------------------
7841 ;; Includes:
7842 ;; - 14.1 Vector Single-Width Integer Reduction Instructions
7843 ;; - 14.2 Vector Widening Integer Reduction Instructions
7844 ;; - 14.3 Vector Single-Width Floating-Point Reduction Instructions
7845 ;; - 14.4 Vector Widening Floating-Point Reduction Instructions
7846 ;; -------------------------------------------------------------------------------
7847
7848 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7849 (define_insn "@pred_<reduc_op><mode>"
7850 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7851 (unspec:<V_LMUL1>
7852 [(unspec:<VM>
7853 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7854 (match_operand 5 "vector_length_operand" " rK, rK")
7855 (match_operand 6 "const_int_operand" " i, i")
7856 (match_operand 7 "const_int_operand" " i, i")
7857 (reg:SI VL_REGNUM)
7858 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7859 (unspec:<V_LMUL1> [
7860 (match_operand:V_VLSI 3 "register_operand" " vr, vr")
7861 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7862 ] ANY_REDUC)
7863 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7864 "TARGET_VECTOR"
7865 "v<reduc_op>.vs\t%0,%3,%4%p1"
7866 [(set_attr "type" "vired")
7867 (set_attr "mode" "<MODE>")])
7868
7869 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7870 (define_insn "@pred_<reduc_op><mode>"
7871 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7872 (unspec:<V_EXT_LMUL1>
7873 [(unspec:<VM>
7874 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7875 (match_operand 5 "vector_length_operand" " rK, rK")
7876 (match_operand 6 "const_int_operand" " i, i")
7877 (match_operand 7 "const_int_operand" " i, i")
7878 (reg:SI VL_REGNUM)
7879 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7880 (unspec:<V_EXT_LMUL1> [
7881 (match_operand:VI_QHS 3 "register_operand" " vr, vr")
7882 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7883 ] ANY_WREDUC)
7884 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7885 "TARGET_VECTOR"
7886 "v<reduc_op>.vs\t%0,%3,%4%p1"
7887 [(set_attr "type" "viwred")
7888 (set_attr "mode" "<MODE>")])
7889
7890 ;; Float Reduction (vfred(max|min).vs)
7891 (define_insn "@pred_<reduc_op><mode>"
7892 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7893 (unspec:<V_LMUL1>
7894 [(unspec:<VM>
7895 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7896 (match_operand 5 "vector_length_operand" " rK, rK")
7897 (match_operand 6 "const_int_operand" " i, i")
7898 (match_operand 7 "const_int_operand" " i, i")
7899 (reg:SI VL_REGNUM)
7900 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7901 (unspec:<V_LMUL1> [
7902 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7903 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7904 ] ANY_FREDUC)
7905 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7906 "TARGET_VECTOR"
7907 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7908 [(set_attr "type" "vfredu")
7909 (set_attr "mode" "<MODE>")])
7910
7911 ;; Float Reduction Sum (vfred[ou]sum.vs)
7912 (define_insn "@pred_<reduc_op><mode>"
7913 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
7914 (unspec:<V_LMUL1>
7915 [(unspec:<VM>
7916 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7917 (match_operand 5 "vector_length_operand" " rK, rK")
7918 (match_operand 6 "const_int_operand" " i, i")
7919 (match_operand 7 "const_int_operand" " i, i")
7920 (match_operand 8 "const_int_operand" " i, i")
7921 (reg:SI VL_REGNUM)
7922 (reg:SI VTYPE_REGNUM)
7923 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7924 (unspec:<V_LMUL1> [
7925 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7926 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7927 ] ANY_FREDUC_SUM)
7928 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7929 "TARGET_VECTOR"
7930 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7931 [(set_attr "type" "vfred<order>")
7932 (set_attr "mode" "<MODE>")
7933 (set (attr "frm_mode")
7934 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7935
7936 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
7937 (define_insn "@pred_<reduc_op><mode>"
7938 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7939 (unspec:<V_EXT_LMUL1>
7940 [(unspec:<VM>
7941 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7942 (match_operand 5 "vector_length_operand" " rK, rK")
7943 (match_operand 6 "const_int_operand" " i, i")
7944 (match_operand 7 "const_int_operand" " i, i")
7945 (match_operand 8 "const_int_operand" " i, i")
7946 (reg:SI VL_REGNUM)
7947 (reg:SI VTYPE_REGNUM)
7948 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7949 (unspec:<V_EXT_LMUL1> [
7950 (match_operand:VF_HS 3 "register_operand" " vr, vr")
7951 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7952 ] ANY_FWREDUC_SUM)
7953 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7954 "TARGET_VECTOR"
7955 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7956 [(set_attr "type" "vfwred<order>")
7957 (set_attr "mode" "<MODE>")
7958 (set (attr "frm_mode")
7959 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7960
7961 ;; -------------------------------------------------------------------------------
7962 ;; ---- Predicated permutation operations
7963 ;; -------------------------------------------------------------------------------
7964 ;; Includes:
7965 ;; - 16.1 Integer Scalar Move Instructions
7966 ;; - 16.2 Floating-Point Scalar Move Instructions
7967 ;; - 16.3 Vector Slide Instructions
7968 ;; - 16.4 Vector Register Gather Instructions
7969 ;; - 16.5 Vector Compress Instruction
7970 ;; -------------------------------------------------------------------------------
7971
7972 (define_expand "@pred_extract_first<mode>"
7973 [(set (match_operand:<VEL> 0 "register_operand")
7974 (unspec:<VEL>
7975 [(vec_select:<VEL>
7976 (match_operand:V_VLSI 1 "reg_or_mem_operand")
7977 (parallel [(const_int 0)]))
7978 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7979 "TARGET_VECTOR"
7980 {
7981 if (MEM_P (operands[1]))
7982 {
7983 /* Combine vle.v + vmv.x.s ==> lw. */
7984 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
7985 DONE;
7986 }
7987 })
7988
7989 (define_insn_and_split "*pred_extract_first<mode>"
7990 [(set (match_operand:<VEL> 0 "register_operand" "=r")
7991 (unspec:<VEL>
7992 [(vec_select:<VEL>
7993 (match_operand:V_VLSI 1 "register_operand" "vr")
7994 (parallel [(const_int 0)]))
7995 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7996 "TARGET_VECTOR"
7997 "vmv.x.s\t%0,%1"
7998 "known_gt (GET_MODE_BITSIZE (<VEL>mode), GET_MODE_BITSIZE (Pmode))"
7999 [(const_int 0)]
8000 {
8001 /* In rv32 system, we can't use vmv.x.s directly.
8002 Instead, we should generate this following code sequence:
8003 vsrl.vx v16,v8,a0
8004 vmv.x.s a1,v16
8005 vmv.x.s a0,v8 */
8006 rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
8007 rtx high_bits = gen_reg_rtx (<MODE>mode);
8008 emit_insn (gen_pred_scalar (LSHIFTRT, <MODE>mode, high_bits, CONSTM1_RTX (<VM>mode),
8009 RVV_VUNDEF (<MODE>mode), operands[1], nbits, /* vl */ const1_rtx,
8010 gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
8011 gen_int_mode (riscv_vector::MASK_ANY, Pmode),
8012 gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
8013 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8014 gen_highpart (SImode, operands[0]), high_bits));
8015 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8016 gen_lowpart (SImode, operands[0]), operands[1]));
8017 DONE;
8018 }
8019 [(set_attr "type" "vimovvx")
8020 (set_attr "mode" "<MODE>")])
8021
8022 (define_insn "@pred_extract_first_trunc<mode>"
8023 [(set (match_operand:SI 0 "register_operand" "=r")
8024 (truncate:SI
8025 (unspec:<VEL>
8026 [(vec_select:<VEL>
8027 (match_operand:V_VLSI_D 1 "register_operand" "vr")
8028 (parallel [(const_int 0)]))
8029 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
8030 "TARGET_VECTOR"
8031 "vmv.x.s\t%0,%1"
8032 [(set_attr "type" "vimovvx")
8033 (set_attr "mode" "<MODE>")])
8034
8035 (define_expand "@pred_extract_first<mode>"
8036 [(set (match_operand:<VEL> 0 "register_operand")
8037 (unspec:<VEL>
8038 [(vec_select:<VEL>
8039 (match_operand:V_VLSF 1 "reg_or_mem_operand")
8040 (parallel [(const_int 0)]))
8041 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8042 "TARGET_VECTOR"
8043 {
8044 if (MEM_P (operands[1]))
8045 {
8046 /* Combine vle.v + vmv.f.s ==> flw. */
8047 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8048 DONE;
8049 }
8050 })
8051
8052 (define_insn "*pred_extract_first<mode>"
8053 [(set (match_operand:<VEL> 0 "register_operand" "=f")
8054 (unspec:<VEL>
8055 [(vec_select:<VEL>
8056 (match_operand:V_VLSF 1 "register_operand" "vr")
8057 (parallel [(const_int 0)]))
8058 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8059 "TARGET_VECTOR"
8060 "vfmv.f.s\t%0,%1"
8061 [(set_attr "type" "vfmovvf")
8062 (set_attr "mode" "<MODE>")])
8063
8064 ;; vslide instructions
8065 (define_insn "@pred_slide<ud><mode>"
8066 [(set (match_operand:V_VLS 0 "register_operand" "<ud_constraint>")
8067 (unspec:V_VLS
8068 [(unspec:<VM>
8069 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8070 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8071 (match_operand 6 "const_int_operand" " i, i, i, i")
8072 (match_operand 7 "const_int_operand" " i, i, i, i")
8073 (match_operand 8 "const_int_operand" " i, i, i, i")
8074 (reg:SI VL_REGNUM)
8075 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8076 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")
8077 (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr")
8078 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))]
8079 "TARGET_VECTOR"
8080 "vslide<ud>.v%o4\t%0,%3,%4%p1"
8081 [(set_attr "type" "vslide<ud>")
8082 (set_attr "mode" "<MODE>")])
8083
8084 ;; vslide1 instructions
8085 (define_insn "@pred_slide<ud><mode>"
8086 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "<ud_constraint>")
8087 (unspec:V_VLSI_QHS
8088 [(unspec:<VM>
8089 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8090 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8091 (match_operand 6 "const_int_operand" " i, i, i, i")
8092 (match_operand 7 "const_int_operand" " i, i, i, i")
8093 (match_operand 8 "const_int_operand" " i, i, i, i")
8094 (reg:SI VL_REGNUM)
8095 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8096 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")
8097 (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr")
8098 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8099 "TARGET_VECTOR"
8100 "vslide<ud>.vx\t%0,%3,%z4%p1"
8101 [(set_attr "type" "vislide<ud>")
8102 (set_attr "mode" "<MODE>")])
8103
8104 (define_expand "@pred_slide<ud><mode>"
8105 [(set (match_operand:V_VLSI_D 0 "register_operand")
8106 (unspec:V_VLSI_D
8107 [(unspec:<VM>
8108 [(match_operand:<VM> 1 "vector_mask_operand")
8109 (match_operand 5 "reg_or_int_operand")
8110 (match_operand 6 "const_int_operand")
8111 (match_operand 7 "const_int_operand")
8112 (match_operand 8 "const_int_operand")
8113 (reg:SI VL_REGNUM)
8114 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8115 (match_operand:V_VLSI_D 2 "vector_merge_operand")
8116 (match_operand:V_VLSI_D 3 "register_operand")
8117 (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
8118 "TARGET_VECTOR"
8119 {
8120 poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
8121 machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require ();
8122 machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require ();
8123 if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
8124 vsimode, vbimode,
8125 operands))
8126 DONE;
8127 })
8128
8129 (define_insn "*pred_slide<ud><mode>"
8130 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8131 (unspec:V_VLSI_D
8132 [(unspec:<VM>
8133 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8134 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8135 (match_operand 6 "const_int_operand" " i, i, i, i")
8136 (match_operand 7 "const_int_operand" " i, i, i, i")
8137 (match_operand 8 "const_int_operand" " i, i, i, i")
8138 (reg:SI VL_REGNUM)
8139 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8140 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8141 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8142 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8143 "TARGET_VECTOR"
8144 "vslide<ud>.vx\t%0,%3,%z4%p1"
8145 [(set_attr "type" "vislide<ud>")
8146 (set_attr "mode" "<MODE>")])
8147
8148 (define_insn "*pred_slide<ud><mode>_extended"
8149 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8150 (unspec:V_VLSI_D
8151 [(unspec:<VM>
8152 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8153 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8154 (match_operand 6 "const_int_operand" " i, i, i, i")
8155 (match_operand 7 "const_int_operand" " i, i, i, i")
8156 (match_operand 8 "const_int_operand" " i, i, i, i")
8157 (reg:SI VL_REGNUM)
8158 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8159 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8160 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8161 (sign_extend:<VEL>
8162 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
8163 "TARGET_VECTOR && !TARGET_64BIT"
8164 "vslide<ud>.vx\t%0,%3,%z4%p1"
8165 [(set_attr "type" "vislide<ud>")
8166 (set_attr "mode" "<MODE>")])
8167
8168 ;; vfslide1 instructions
8169 (define_insn "@pred_slide<ud><mode>"
8170 [(set (match_operand:V_VLSF 0 "register_operand" "<ud_constraint>")
8171 (unspec:V_VLSF
8172 [(unspec:<VM>
8173 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8174 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8175 (match_operand 6 "const_int_operand" " i, i, i, i")
8176 (match_operand 7 "const_int_operand" " i, i, i, i")
8177 (match_operand 8 "const_int_operand" " i, i, i, i")
8178 (reg:SI VL_REGNUM)
8179 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8180 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")
8181 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
8182 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
8183 "TARGET_VECTOR"
8184 "vfslide<ud>.vf\t%0,%3,%4%p1"
8185 [(set_attr "type" "vfslide<ud>")
8186 (set_attr "mode" "<MODE>")])
8187
8188 ;; vrgather
8189 (define_insn "@pred_gather<mode>"
8190 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8191 (if_then_else:V_VLS
8192 (unspec:<VM>
8193 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8194 (match_operand 5 "vector_length_operand" " rK, rK")
8195 (match_operand 6 "const_int_operand" " i, i")
8196 (match_operand 7 "const_int_operand" " i, i")
8197 (match_operand 8 "const_int_operand" " i, i")
8198 (reg:SI VL_REGNUM)
8199 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8200 (unspec:V_VLS
8201 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8202 (match_operand:<VINDEX> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER)
8203 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8204 "TARGET_VECTOR"
8205 "vrgather.vv\t%0,%3,%4%p1"
8206 [(set_attr "type" "vgather")
8207 (set_attr "mode" "<MODE>")])
8208
8209 (define_insn "@pred_gather<mode>_scalar"
8210 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8211 (if_then_else:V_VLS
8212 (unspec:<VM>
8213 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8214 (match_operand 5 "vector_length_operand" " rK, rK")
8215 (match_operand 6 "const_int_operand" " i, i")
8216 (match_operand 7 "const_int_operand" " i, i")
8217 (match_operand 8 "const_int_operand" " i, i")
8218 (reg:SI VL_REGNUM)
8219 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8220 (unspec:V_VLS
8221 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8222 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER)
8223 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8224 "TARGET_VECTOR"
8225 "vrgather.v%o4\t%0,%3,%4%p1"
8226 [(set_attr "type" "vgather")
8227 (set_attr "mode" "<MODE>")])
8228
8229 ;; vrgatherei16
8230 (define_insn "@pred_gatherei16<mode>"
8231 [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr")
8232 (if_then_else:VEI16
8233 (unspec:<VM>
8234 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8235 (match_operand 5 "vector_length_operand" " rK, rK")
8236 (match_operand 6 "const_int_operand" " i, i")
8237 (match_operand 7 "const_int_operand" " i, i")
8238 (match_operand 8 "const_int_operand" " i, i")
8239 (reg:SI VL_REGNUM)
8240 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8241 (unspec:VEI16
8242 [(match_operand:VEI16 3 "register_operand" " vr, vr")
8243 (match_operand:<VINDEXEI16> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16)
8244 (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))]
8245 "TARGET_VECTOR"
8246 "vrgatherei16.vv\t%0,%3,%4%p1"
8247 [(set_attr "type" "vgather")
8248 (set_attr "mode" "<MODE>")])
8249
8250 ;; vcompress
8251 (define_insn "@pred_compress<mode>"
8252 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8253 (unspec:V_VLS
8254 [(unspec:<VM>
8255 [(match_operand:<VM> 3 "register_operand" " vm, vm")
8256 (match_operand 4 "vector_length_operand" " rK, rK")
8257 (match_operand 5 "const_int_operand" " i, i")
8258 (match_operand 6 "const_int_operand" " i, i")
8259 (reg:SI VL_REGNUM)
8260 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8261 (match_operand:V_VLS 2 "register_operand" " vr, vr")
8262 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))]
8263 "TARGET_VECTOR"
8264 "vcompress.vm\t%0,%2,%3"
8265 [(set_attr "type" "vcompress")
8266 (set_attr "mode" "<MODE>")])
8267
8268 ;; -------------------------------------------------------------------------------
8269 ;; ---- Predicated Fault-Only-First loads
8270 ;; -------------------------------------------------------------------------------
8271 ;; Includes:
8272 ;; - 7.7. Unit-stride Fault-Only-First Loads
8273 ;; -------------------------------------------------------------------------------
8274
8275 (define_insn "read_vlsi"
8276 [(set (match_operand:SI 0 "register_operand" "=r")
8277 (reg:SI VL_REGNUM))]
8278 "TARGET_VECTOR"
8279 "csrr\t%0,vl"
8280 [(set_attr "type" "rdvl")
8281 (set_attr "mode" "SI")])
8282
8283 (define_insn "read_vldi_zero_extend"
8284 [(set (match_operand:DI 0 "register_operand" "=r")
8285 (zero_extend:DI (reg:SI VL_REGNUM)))]
8286 "TARGET_VECTOR && TARGET_64BIT"
8287 "csrr\t%0,vl"
8288 [(set_attr "type" "rdvl")
8289 (set_attr "mode" "DI")])
8290
8291 (define_insn "@pred_fault_load<mode>"
8292 [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
8293 (if_then_else:V
8294 (unspec:<VM>
8295 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
8296 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
8297 (match_operand 5 "const_int_operand" " i, i, i, i")
8298 (match_operand 6 "const_int_operand" " i, i, i, i")
8299 (match_operand 7 "const_int_operand" " i, i, i, i")
8300 (reg:SI VL_REGNUM)
8301 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8302 (unspec:V
8303 [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
8304 (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
8305 (set (reg:SI VL_REGNUM)
8306 (unspec:SI
8307 [(if_then_else:V
8308 (unspec:<VM>
8309 [(match_dup 1) (match_dup 4) (match_dup 5)
8310 (match_dup 6) (match_dup 7)
8311 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8312 (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
8313 (match_dup 2))] UNSPEC_MODIFY_VL))]
8314 "TARGET_VECTOR"
8315 "vle<sew>ff.v\t%0,%3%p1"
8316 [(set_attr "type" "vldff")
8317 (set_attr "mode" "<MODE>")])
8318
8319
8320 ;; -------------------------------------------------------------------------------
8321 ;; ---- Predicated Segment loads/stores
8322 ;; -------------------------------------------------------------------------------
8323 ;; Includes:
8324 ;; - 7.8.1. Vector Unit-Stride Segment Loads and Stores
8325 ;; - 7.8.2. Vector Strided Segment Loads and Stores
8326 ;; - 7.8.3. Vector Indexed Segment Loads and Stores
8327 ;; -------------------------------------------------------------------------------
8328
8329 (define_insn "@pred_unit_strided_load<mode>"
8330 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8331 (if_then_else:VT
8332 (unspec:<VM>
8333 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8334 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8335 (match_operand 5 "const_int_operand" " i, i, i")
8336 (match_operand 6 "const_int_operand" " i, i, i")
8337 (match_operand 7 "const_int_operand" " i, i, i")
8338 (reg:SI VL_REGNUM)
8339 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8340 (unspec:VT
8341 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8342 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED)
8343 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8344 "TARGET_VECTOR"
8345 "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"
8346 [(set_attr "type" "vlsegde")
8347 (set_attr "mode" "<MODE>")])
8348
8349 (define_insn "@pred_unit_strided_store<mode>"
8350 [(set (mem:BLK (scratch))
8351 (unspec:BLK
8352 [(unspec:<VM>
8353 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8354 (match_operand 3 "vector_length_operand" " rK")
8355 (match_operand 4 "const_int_operand" " i")
8356 (reg:SI VL_REGNUM)
8357 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8358 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8359 (match_operand:VT 2 "register_operand" " vr")
8360 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED))]
8361 "TARGET_VECTOR"
8362 "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"
8363 [(set_attr "type" "vssegte")
8364 (set_attr "mode" "<MODE>")])
8365
8366 (define_insn "@pred_strided_load<mode>"
8367 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8368 (if_then_else:VT
8369 (unspec:<VM>
8370 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8371 (match_operand 5 "vector_length_operand" " rK, rK, rK")
8372 (match_operand 6 "const_int_operand" " i, i, i")
8373 (match_operand 7 "const_int_operand" " i, i, i")
8374 (match_operand 8 "const_int_operand" " i, i, i")
8375 (reg:SI VL_REGNUM)
8376 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8377 (unspec:VT
8378 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8379 (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8380 (mem:BLK (scratch))] UNSPEC_STRIDED)
8381 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8382 "TARGET_VECTOR"
8383 "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"
8384 [(set_attr "type" "vlsegds")
8385 (set_attr "mode" "<MODE>")])
8386
8387 (define_insn "@pred_strided_store<mode>"
8388 [(set (mem:BLK (scratch))
8389 (unspec:BLK
8390 [(unspec:<VM>
8391 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8392 (match_operand 4 "vector_length_operand" " rK")
8393 (match_operand 5 "const_int_operand" " i")
8394 (reg:SI VL_REGNUM)
8395 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8396 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8397 (match_operand 2 "pmode_reg_or_0_operand" " rJ")
8398 (match_operand:VT 3 "register_operand" " vr")
8399 (mem:BLK (scratch))] UNSPEC_STRIDED))]
8400 "TARGET_VECTOR"
8401 "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"
8402 [(set_attr "type" "vssegts")
8403 (set_attr "mode" "<MODE>")])
8404
8405 (define_insn "@pred_fault_load<mode>"
8406 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8407 (if_then_else:VT
8408 (unspec:<VM>
8409 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8410 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8411 (match_operand 5 "const_int_operand" " i, i, i")
8412 (match_operand 6 "const_int_operand" " i, i, i")
8413 (match_operand 7 "const_int_operand" " i, i, i")
8414 (reg:SI VL_REGNUM)
8415 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8416 (unspec:VT
8417 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8418 (mem:BLK (scratch))] UNSPEC_VLEFF)
8419 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))
8420 (set (reg:SI VL_REGNUM)
8421 (unspec:SI
8422 [(if_then_else:VT
8423 (unspec:<VM>
8424 [(match_dup 1) (match_dup 4) (match_dup 5)
8425 (match_dup 6) (match_dup 7)
8426 (reg:SI VL_REGNUM)
8427 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8428 (unspec:VT
8429 [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
8430 (match_dup 2))] UNSPEC_MODIFY_VL))]
8431 "TARGET_VECTOR"
8432 "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"
8433 [(set_attr "type" "vlsegdff")
8434 (set_attr "mode" "<MODE>")])
8435
8436 (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
8437 [(set (match_operand:V1T 0 "register_operand" "=&vr, &vr")
8438 (if_then_else:V1T
8439 (unspec:<VM>
8440 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8441 (match_operand 5 "vector_length_operand" " rK, rK")
8442 (match_operand 6 "const_int_operand" " i, i")
8443 (match_operand 7 "const_int_operand" " i, i")
8444 (match_operand 8 "const_int_operand" " i, i")
8445 (reg:SI VL_REGNUM)
8446 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8447 (unspec:V1T
8448 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8449 (mem:BLK (scratch))
8450 (match_operand:RATIO64I 4 "register_operand" " vr, vr")] ORDER)
8451 (match_operand:V1T 2 "vector_merge_operand" " vu, 0")))]
8452 "TARGET_VECTOR"
8453 "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"
8454 [(set_attr "type" "vlsegd<order>x")
8455 (set_attr "mode" "<V1T:MODE>")])
8456
8457 (define_insn "@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
8458 [(set (match_operand:V2T 0 "register_operand" "=&vr, &vr")
8459 (if_then_else:V2T
8460 (unspec:<VM>
8461 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8462 (match_operand 5 "vector_length_operand" " rK, rK")
8463 (match_operand 6 "const_int_operand" " i, i")
8464 (match_operand 7 "const_int_operand" " i, i")
8465 (match_operand 8 "const_int_operand" " i, i")
8466 (reg:SI VL_REGNUM)
8467 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8468 (unspec:V2T
8469 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8470 (mem:BLK (scratch))
8471 (match_operand:RATIO32I 4 "register_operand" " vr, vr")] ORDER)
8472 (match_operand:V2T 2 "vector_merge_operand" " vu, 0")))]
8473 "TARGET_VECTOR"
8474 "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"
8475 [(set_attr "type" "vlsegd<order>x")
8476 (set_attr "mode" "<V2T:MODE>")])
8477
8478 (define_insn "@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
8479 [(set (match_operand:V4T 0 "register_operand" "=&vr, &vr")
8480 (if_then_else:V4T
8481 (unspec:<VM>
8482 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8483 (match_operand 5 "vector_length_operand" " rK, rK")
8484 (match_operand 6 "const_int_operand" " i, i")
8485 (match_operand 7 "const_int_operand" " i, i")
8486 (match_operand 8 "const_int_operand" " i, i")
8487 (reg:SI VL_REGNUM)
8488 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8489 (unspec:V4T
8490 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8491 (mem:BLK (scratch))
8492 (match_operand:RATIO16I 4 "register_operand" " vr, vr")] ORDER)
8493 (match_operand:V4T 2 "vector_merge_operand" " vu, 0")))]
8494 "TARGET_VECTOR"
8495 "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"
8496 [(set_attr "type" "vlsegd<order>x")
8497 (set_attr "mode" "<V4T:MODE>")])
8498
8499 (define_insn "@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
8500 [(set (match_operand:V8T 0 "register_operand" "=&vr, &vr")
8501 (if_then_else:V8T
8502 (unspec:<VM>
8503 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8504 (match_operand 5 "vector_length_operand" " rK, rK")
8505 (match_operand 6 "const_int_operand" " i, i")
8506 (match_operand 7 "const_int_operand" " i, i")
8507 (match_operand 8 "const_int_operand" " i, i")
8508 (reg:SI VL_REGNUM)
8509 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8510 (unspec:V8T
8511 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8512 (mem:BLK (scratch))
8513 (match_operand:RATIO8I 4 "register_operand" " vr, vr")] ORDER)
8514 (match_operand:V8T 2 "vector_merge_operand" " vu, 0")))]
8515 "TARGET_VECTOR"
8516 "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"
8517 [(set_attr "type" "vlsegd<order>x")
8518 (set_attr "mode" "<V8T:MODE>")])
8519
8520 (define_insn "@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
8521 [(set (match_operand:V16T 0 "register_operand" "=&vr, &vr")
8522 (if_then_else:V16T
8523 (unspec:<VM>
8524 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8525 (match_operand 5 "vector_length_operand" " rK, rK")
8526 (match_operand 6 "const_int_operand" " i, i")
8527 (match_operand 7 "const_int_operand" " i, i")
8528 (match_operand 8 "const_int_operand" " i, i")
8529 (reg:SI VL_REGNUM)
8530 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8531 (unspec:V16T
8532 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8533 (mem:BLK (scratch))
8534 (match_operand:RATIO4I 4 "register_operand" " vr, vr")] ORDER)
8535 (match_operand:V16T 2 "vector_merge_operand" " vu, 0")))]
8536 "TARGET_VECTOR"
8537 "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"
8538 [(set_attr "type" "vlsegd<order>x")
8539 (set_attr "mode" "<V16T:MODE>")])
8540
8541 (define_insn "@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
8542 [(set (match_operand:V32T 0 "register_operand" "=&vr, &vr")
8543 (if_then_else:V32T
8544 (unspec:<VM>
8545 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8546 (match_operand 5 "vector_length_operand" " rK, rK")
8547 (match_operand 6 "const_int_operand" " i, i")
8548 (match_operand 7 "const_int_operand" " i, i")
8549 (match_operand 8 "const_int_operand" " i, i")
8550 (reg:SI VL_REGNUM)
8551 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8552 (unspec:V32T
8553 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8554 (mem:BLK (scratch))
8555 (match_operand:RATIO2I 4 "register_operand" " vr, vr")] ORDER)
8556 (match_operand:V32T 2 "vector_merge_operand" " vu, 0")))]
8557 "TARGET_VECTOR"
8558 "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"
8559 [(set_attr "type" "vlsegd<order>x")
8560 (set_attr "mode" "<V32T:MODE>")])
8561
8562 (define_insn "@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
8563 [(set (mem:BLK (scratch))
8564 (unspec:BLK
8565 [(unspec:<VM>
8566 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8567 (match_operand 4 "vector_length_operand" " rK")
8568 (match_operand 5 "const_int_operand" " i")
8569 (reg:SI VL_REGNUM)
8570 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8571 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8572 (match_operand:RATIO64I 2 "register_operand" " vr")
8573 (match_operand:V1T 3 "register_operand" " vr")] ORDER))]
8574 "TARGET_VECTOR"
8575 "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
8576 [(set_attr "type" "vssegt<order>x")
8577 (set_attr "mode" "<V1T:MODE>")])
8578
8579 (define_insn "@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
8580 [(set (mem:BLK (scratch))
8581 (unspec:BLK
8582 [(unspec:<VM>
8583 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8584 (match_operand 4 "vector_length_operand" " rK")
8585 (match_operand 5 "const_int_operand" " i")
8586 (reg:SI VL_REGNUM)
8587 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8588 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8589 (match_operand:RATIO32I 2 "register_operand" " vr")
8590 (match_operand:V2T 3 "register_operand" " vr")] ORDER))]
8591 "TARGET_VECTOR"
8592 "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
8593 [(set_attr "type" "vssegt<order>x")
8594 (set_attr "mode" "<V2T:MODE>")])
8595
8596 (define_insn "@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
8597 [(set (mem:BLK (scratch))
8598 (unspec:BLK
8599 [(unspec:<VM>
8600 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8601 (match_operand 4 "vector_length_operand" " rK")
8602 (match_operand 5 "const_int_operand" " i")
8603 (reg:SI VL_REGNUM)
8604 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8605 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8606 (match_operand:RATIO16I 2 "register_operand" " vr")
8607 (match_operand:V4T 3 "register_operand" " vr")] ORDER))]
8608 "TARGET_VECTOR"
8609 "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
8610 [(set_attr "type" "vssegt<order>x")
8611 (set_attr "mode" "<V4T:MODE>")])
8612
8613 (define_insn "@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
8614 [(set (mem:BLK (scratch))
8615 (unspec:BLK
8616 [(unspec:<VM>
8617 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8618 (match_operand 4 "vector_length_operand" " rK")
8619 (match_operand 5 "const_int_operand" " i")
8620 (reg:SI VL_REGNUM)
8621 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8622 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8623 (match_operand:RATIO8I 2 "register_operand" " vr")
8624 (match_operand:V8T 3 "register_operand" " vr")] ORDER))]
8625 "TARGET_VECTOR"
8626 "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
8627 [(set_attr "type" "vssegt<order>x")
8628 (set_attr "mode" "<V8T:MODE>")])
8629
8630 (define_insn "@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
8631 [(set (mem:BLK (scratch))
8632 (unspec:BLK
8633 [(unspec:<VM>
8634 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8635 (match_operand 4 "vector_length_operand" " rK")
8636 (match_operand 5 "const_int_operand" " i")
8637 (reg:SI VL_REGNUM)
8638 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8639 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8640 (match_operand:RATIO4I 2 "register_operand" " vr")
8641 (match_operand:V16T 3 "register_operand" " vr")] ORDER))]
8642 "TARGET_VECTOR"
8643 "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
8644 [(set_attr "type" "vssegt<order>x")
8645 (set_attr "mode" "<V16T:MODE>")])
8646
8647 (define_insn "@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
8648 [(set (mem:BLK (scratch))
8649 (unspec:BLK
8650 [(unspec:<VM>
8651 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8652 (match_operand 4 "vector_length_operand" " rK")
8653 (match_operand 5 "const_int_operand" " i")
8654 (reg:SI VL_REGNUM)
8655 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8656 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8657 (match_operand:RATIO2I 2 "register_operand" " vr")
8658 (match_operand:V32T 3 "register_operand" " vr")] ORDER))]
8659 "TARGET_VECTOR"
8660 "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
8661 [(set_attr "type" "vssegt<order>x")
8662 (set_attr "mode" "<V32T:MODE>")])
8663
8664 (include "autovec.md")
8665 (include "autovec-opt.md")
Mirror of https://gcc.gnu.org/git/gcc.git