1 ;; Machine description for RISC-V Zc extention.
2 ;; Copyright (C) 2023-2024 Free Software Foundation, Inc.
3 ;; Contributed by Fei Gao (gaofei@eswincomputing.com).
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_insn "@gpr_multi_pop_up_to_ra_<mode>"
22 [(set (reg:X SP_REGNUM)
23 (plus:X (reg:X SP_REGNUM)
24 (match_operand 0 "stack_pop_up_to_ra_operand" "I")))
25 (set (reg:X RETURN_ADDR_REGNUM)
26 (mem:X (plus:X (reg:X SP_REGNUM)
27 (const_int <slot0_offset>))))]
30 [(set_attr "type" "pushpop")])
32 (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
33 [(set (reg:X SP_REGNUM)
34 (plus:X (reg:X SP_REGNUM)
35 (match_operand 0 "stack_pop_up_to_s0_operand" "I")))
36 (set (reg:X S0_REGNUM)
37 (mem:X (plus:X (reg:X SP_REGNUM)
38 (const_int <slot0_offset>))))
39 (set (reg:X RETURN_ADDR_REGNUM)
40 (mem:X (plus:X (reg:X SP_REGNUM)
41 (const_int <slot1_offset>))))]
44 [(set_attr "type" "pushpop")])
46 (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
47 [(set (reg:X SP_REGNUM)
48 (plus:X (reg:X SP_REGNUM)
49 (match_operand 0 "stack_pop_up_to_s1_operand" "I")))
50 (set (reg:X S1_REGNUM)
51 (mem:X (plus:X (reg:X SP_REGNUM)
52 (const_int <slot0_offset>))))
53 (set (reg:X S0_REGNUM)
54 (mem:X (plus:X (reg:X SP_REGNUM)
55 (const_int <slot1_offset>))))
56 (set (reg:X RETURN_ADDR_REGNUM)
57 (mem:X (plus:X (reg:X SP_REGNUM)
58 (const_int <slot2_offset>))))]
60 "cm.pop {ra, s0-s1}, %0"
61 [(set_attr "type" "pushpop")])
63 (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
64 [(set (reg:X SP_REGNUM)
65 (plus:X (reg:X SP_REGNUM)
66 (match_operand 0 "stack_pop_up_to_s2_operand" "I")))
67 (set (reg:X S2_REGNUM)
68 (mem:X (plus:X (reg:X SP_REGNUM)
69 (const_int <slot0_offset>))))
70 (set (reg:X S1_REGNUM)
71 (mem:X (plus:X (reg:X SP_REGNUM)
72 (const_int <slot1_offset>))))
73 (set (reg:X S0_REGNUM)
74 (mem:X (plus:X (reg:X SP_REGNUM)
75 (const_int <slot2_offset>))))
76 (set (reg:X RETURN_ADDR_REGNUM)
77 (mem:X (plus:X (reg:X SP_REGNUM)
78 (const_int <slot3_offset>))))]
80 "cm.pop {ra, s0-s2}, %0"
81 [(set_attr "type" "pushpop")])
83 (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
84 [(set (reg:X SP_REGNUM)
85 (plus:X (reg:X SP_REGNUM)
86 (match_operand 0 "stack_pop_up_to_s3_operand" "I")))
87 (set (reg:X S3_REGNUM)
88 (mem:X (plus:X (reg:X SP_REGNUM)
89 (const_int <slot0_offset>))))
90 (set (reg:X S2_REGNUM)
91 (mem:X (plus:X (reg:X SP_REGNUM)
92 (const_int <slot1_offset>))))
93 (set (reg:X S1_REGNUM)
94 (mem:X (plus:X (reg:X SP_REGNUM)
95 (const_int <slot2_offset>))))
96 (set (reg:X S0_REGNUM)
97 (mem:X (plus:X (reg:X SP_REGNUM)
98 (const_int <slot3_offset>))))
99 (set (reg:X RETURN_ADDR_REGNUM)
100 (mem:X (plus:X (reg:X SP_REGNUM)
101 (const_int <slot4_offset>))))]
103 "cm.pop {ra, s0-s3}, %0"
104 [(set_attr "type" "pushpop")])
106 (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
107 [(set (reg:X SP_REGNUM)
108 (plus:X (reg:X SP_REGNUM)
109 (match_operand 0 "stack_pop_up_to_s4_operand" "I")))
110 (set (reg:X S4_REGNUM)
111 (mem:X (plus:X (reg:X SP_REGNUM)
112 (const_int <slot0_offset>))))
113 (set (reg:X S3_REGNUM)
114 (mem:X (plus:X (reg:X SP_REGNUM)
115 (const_int <slot1_offset>))))
116 (set (reg:X S2_REGNUM)
117 (mem:X (plus:X (reg:X SP_REGNUM)
118 (const_int <slot2_offset>))))
119 (set (reg:X S1_REGNUM)
120 (mem:X (plus:X (reg:X SP_REGNUM)
121 (const_int <slot3_offset>))))
122 (set (reg:X S0_REGNUM)
123 (mem:X (plus:X (reg:X SP_REGNUM)
124 (const_int <slot4_offset>))))
125 (set (reg:X RETURN_ADDR_REGNUM)
126 (mem:X (plus:X (reg:X SP_REGNUM)
127 (const_int <slot5_offset>))))]
129 "cm.pop {ra, s0-s4}, %0"
130 [(set_attr "type" "pushpop")])
132 (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
133 [(set (reg:X SP_REGNUM)
134 (plus:X (reg:X SP_REGNUM)
135 (match_operand 0 "stack_pop_up_to_s5_operand" "I")))
136 (set (reg:X S5_REGNUM)
137 (mem:X (plus:X (reg:X SP_REGNUM)
138 (const_int <slot0_offset>))))
139 (set (reg:X S4_REGNUM)
140 (mem:X (plus:X (reg:X SP_REGNUM)
141 (const_int <slot1_offset>))))
142 (set (reg:X S3_REGNUM)
143 (mem:X (plus:X (reg:X SP_REGNUM)
144 (const_int <slot2_offset>))))
145 (set (reg:X S2_REGNUM)
146 (mem:X (plus:X (reg:X SP_REGNUM)
147 (const_int <slot3_offset>))))
148 (set (reg:X S1_REGNUM)
149 (mem:X (plus:X (reg:X SP_REGNUM)
150 (const_int <slot4_offset>))))
151 (set (reg:X S0_REGNUM)
152 (mem:X (plus:X (reg:X SP_REGNUM)
153 (const_int <slot5_offset>))))
154 (set (reg:X RETURN_ADDR_REGNUM)
155 (mem:X (plus:X (reg:X SP_REGNUM)
156 (const_int <slot6_offset>))))]
158 "cm.pop {ra, s0-s5}, %0"
159 [(set_attr "type" "pushpop")])
161 (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
162 [(set (reg:X SP_REGNUM)
163 (plus:X (reg:X SP_REGNUM)
164 (match_operand 0 "stack_pop_up_to_s6_operand" "I")))
165 (set (reg:X S6_REGNUM)
166 (mem:X (plus:X (reg:X SP_REGNUM)
167 (const_int <slot0_offset>))))
168 (set (reg:X S5_REGNUM)
169 (mem:X (plus:X (reg:X SP_REGNUM)
170 (const_int <slot1_offset>))))
171 (set (reg:X S4_REGNUM)
172 (mem:X (plus:X (reg:X SP_REGNUM)
173 (const_int <slot2_offset>))))
174 (set (reg:X S3_REGNUM)
175 (mem:X (plus:X (reg:X SP_REGNUM)
176 (const_int <slot3_offset>))))
177 (set (reg:X S2_REGNUM)
178 (mem:X (plus:X (reg:X SP_REGNUM)
179 (const_int <slot4_offset>))))
180 (set (reg:X S1_REGNUM)
181 (mem:X (plus:X (reg:X SP_REGNUM)
182 (const_int <slot5_offset>))))
183 (set (reg:X S0_REGNUM)
184 (mem:X (plus:X (reg:X SP_REGNUM)
185 (const_int <slot6_offset>))))
186 (set (reg:X RETURN_ADDR_REGNUM)
187 (mem:X (plus:X (reg:X SP_REGNUM)
188 (const_int <slot7_offset>))))]
190 "cm.pop {ra, s0-s6}, %0"
191 [(set_attr "type" "pushpop")])
193 (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
194 [(set (reg:X SP_REGNUM)
195 (plus:X (reg:X SP_REGNUM)
196 (match_operand 0 "stack_pop_up_to_s7_operand" "I")))
197 (set (reg:X S7_REGNUM)
198 (mem:X (plus:X (reg:X SP_REGNUM)
199 (const_int <slot0_offset>))))
200 (set (reg:X S6_REGNUM)
201 (mem:X (plus:X (reg:X SP_REGNUM)
202 (const_int <slot1_offset>))))
203 (set (reg:X S5_REGNUM)
204 (mem:X (plus:X (reg:X SP_REGNUM)
205 (const_int <slot2_offset>))))
206 (set (reg:X S4_REGNUM)
207 (mem:X (plus:X (reg:X SP_REGNUM)
208 (const_int <slot3_offset>))))
209 (set (reg:X S3_REGNUM)
210 (mem:X (plus:X (reg:X SP_REGNUM)
211 (const_int <slot4_offset>))))
212 (set (reg:X S2_REGNUM)
213 (mem:X (plus:X (reg:X SP_REGNUM)
214 (const_int <slot5_offset>))))
215 (set (reg:X S1_REGNUM)
216 (mem:X (plus:X (reg:X SP_REGNUM)
217 (const_int <slot6_offset>))))
218 (set (reg:X S0_REGNUM)
219 (mem:X (plus:X (reg:X SP_REGNUM)
220 (const_int <slot7_offset>))))
221 (set (reg:X RETURN_ADDR_REGNUM)
222 (mem:X (plus:X (reg:X SP_REGNUM)
223 (const_int <slot8_offset>))))]
225 "cm.pop {ra, s0-s7}, %0"
226 [(set_attr "type" "pushpop")])
228 (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
229 [(set (reg:X SP_REGNUM)
230 (plus:X (reg:X SP_REGNUM)
231 (match_operand 0 "stack_pop_up_to_s8_operand" "I")))
232 (set (reg:X S8_REGNUM)
233 (mem:X (plus:X (reg:X SP_REGNUM)
234 (const_int <slot0_offset>))))
235 (set (reg:X S7_REGNUM)
236 (mem:X (plus:X (reg:X SP_REGNUM)
237 (const_int <slot1_offset>))))
238 (set (reg:X S6_REGNUM)
239 (mem:X (plus:X (reg:X SP_REGNUM)
240 (const_int <slot2_offset>))))
241 (set (reg:X S5_REGNUM)
242 (mem:X (plus:X (reg:X SP_REGNUM)
243 (const_int <slot3_offset>))))
244 (set (reg:X S4_REGNUM)
245 (mem:X (plus:X (reg:X SP_REGNUM)
246 (const_int <slot4_offset>))))
247 (set (reg:X S3_REGNUM)
248 (mem:X (plus:X (reg:X SP_REGNUM)
249 (const_int <slot5_offset>))))
250 (set (reg:X S2_REGNUM)
251 (mem:X (plus:X (reg:X SP_REGNUM)
252 (const_int <slot6_offset>))))
253 (set (reg:X S1_REGNUM)
254 (mem:X (plus:X (reg:X SP_REGNUM)
255 (const_int <slot7_offset>))))
256 (set (reg:X S0_REGNUM)
257 (mem:X (plus:X (reg:X SP_REGNUM)
258 (const_int <slot8_offset>))))
259 (set (reg:X RETURN_ADDR_REGNUM)
260 (mem:X (plus:X (reg:X SP_REGNUM)
261 (const_int <slot9_offset>))))]
263 "cm.pop {ra, s0-s8}, %0"
264 [(set_attr "type" "pushpop")])
266 (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
267 [(set (reg:X SP_REGNUM)
268 (plus:X (reg:X SP_REGNUM)
269 (match_operand 0 "stack_pop_up_to_s9_operand" "I")))
270 (set (reg:X S9_REGNUM)
271 (mem:X (plus:X (reg:X SP_REGNUM)
272 (const_int <slot0_offset>))))
273 (set (reg:X S8_REGNUM)
274 (mem:X (plus:X (reg:X SP_REGNUM)
275 (const_int <slot1_offset>))))
276 (set (reg:X S7_REGNUM)
277 (mem:X (plus:X (reg:X SP_REGNUM)
278 (const_int <slot2_offset>))))
279 (set (reg:X S6_REGNUM)
280 (mem:X (plus:X (reg:X SP_REGNUM)
281 (const_int <slot3_offset>))))
282 (set (reg:X S5_REGNUM)
283 (mem:X (plus:X (reg:X SP_REGNUM)
284 (const_int <slot4_offset>))))
285 (set (reg:X S4_REGNUM)
286 (mem:X (plus:X (reg:X SP_REGNUM)
287 (const_int <slot5_offset>))))
288 (set (reg:X S3_REGNUM)
289 (mem:X (plus:X (reg:X SP_REGNUM)
290 (const_int <slot6_offset>))))
291 (set (reg:X S2_REGNUM)
292 (mem:X (plus:X (reg:X SP_REGNUM)
293 (const_int <slot7_offset>))))
294 (set (reg:X S1_REGNUM)
295 (mem:X (plus:X (reg:X SP_REGNUM)
296 (const_int <slot8_offset>))))
297 (set (reg:X S0_REGNUM)
298 (mem:X (plus:X (reg:X SP_REGNUM)
299 (const_int <slot9_offset>))))
300 (set (reg:X RETURN_ADDR_REGNUM)
301 (mem:X (plus:X (reg:X SP_REGNUM)
302 (const_int <slot10_offset>))))]
304 "cm.pop {ra, s0-s9}, %0"
305 [(set_attr "type" "pushpop")])
307 (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
308 [(set (reg:X SP_REGNUM)
309 (plus:X (reg:X SP_REGNUM)
310 (match_operand 0 "stack_pop_up_to_s11_operand" "I")))
311 (set (reg:X S11_REGNUM)
312 (mem:X (plus:X (reg:X SP_REGNUM)
313 (const_int <slot0_offset>))))
314 (set (reg:X S10_REGNUM)
315 (mem:X (plus:X (reg:X SP_REGNUM)
316 (const_int <slot1_offset>))))
317 (set (reg:X S9_REGNUM)
318 (mem:X (plus:X (reg:X SP_REGNUM)
319 (const_int <slot2_offset>))))
320 (set (reg:X S8_REGNUM)
321 (mem:X (plus:X (reg:X SP_REGNUM)
322 (const_int <slot3_offset>))))
323 (set (reg:X S7_REGNUM)
324 (mem:X (plus:X (reg:X SP_REGNUM)
325 (const_int <slot4_offset>))))
326 (set (reg:X S6_REGNUM)
327 (mem:X (plus:X (reg:X SP_REGNUM)
328 (const_int <slot5_offset>))))
329 (set (reg:X S5_REGNUM)
330 (mem:X (plus:X (reg:X SP_REGNUM)
331 (const_int <slot6_offset>))))
332 (set (reg:X S4_REGNUM)
333 (mem:X (plus:X (reg:X SP_REGNUM)
334 (const_int <slot7_offset>))))
335 (set (reg:X S3_REGNUM)
336 (mem:X (plus:X (reg:X SP_REGNUM)
337 (const_int <slot8_offset>))))
338 (set (reg:X S2_REGNUM)
339 (mem:X (plus:X (reg:X SP_REGNUM)
340 (const_int <slot9_offset>))))
341 (set (reg:X S1_REGNUM)
342 (mem:X (plus:X (reg:X SP_REGNUM)
343 (const_int <slot10_offset>))))
344 (set (reg:X S0_REGNUM)
345 (mem:X (plus:X (reg:X SP_REGNUM)
346 (const_int <slot11_offset>))))
347 (set (reg:X RETURN_ADDR_REGNUM)
348 (mem:X (plus:X (reg:X SP_REGNUM)
349 (const_int <slot12_offset>))))]
351 "cm.pop {ra, s0-s11}, %0"
352 [(set_attr "type" "pushpop")])
354 (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
355 [(set (reg:X SP_REGNUM)
356 (plus:X (reg:X SP_REGNUM)
357 (match_operand 0 "stack_pop_up_to_ra_operand" "I")))
358 (set (reg:X RETURN_ADDR_REGNUM)
359 (mem:X (plus:X (reg:X SP_REGNUM)
360 (const_int <slot0_offset>))))
362 (use (reg:SI RETURN_ADDR_REGNUM))]
365 [(set_attr "type" "pushpop")])
367 (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
368 [(set (reg:X SP_REGNUM)
369 (plus:X (reg:X SP_REGNUM)
370 (match_operand 0 "stack_pop_up_to_s0_operand" "I")))
371 (set (reg:X S0_REGNUM)
372 (mem:X (plus:X (reg:X SP_REGNUM)
373 (const_int <slot0_offset>))))
374 (set (reg:X RETURN_ADDR_REGNUM)
375 (mem:X (plus:X (reg:X SP_REGNUM)
376 (const_int <slot1_offset>))))
378 (use (reg:SI RETURN_ADDR_REGNUM))]
380 "cm.popret {ra, s0}, %0"
381 [(set_attr "type" "pushpop")])
383 (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
384 [(set (reg:X SP_REGNUM)
385 (plus:X (reg:X SP_REGNUM)
386 (match_operand 0 "stack_pop_up_to_s1_operand" "I")))
387 (set (reg:X S1_REGNUM)
388 (mem:X (plus:X (reg:X SP_REGNUM)
389 (const_int <slot0_offset>))))
390 (set (reg:X S0_REGNUM)
391 (mem:X (plus:X (reg:X SP_REGNUM)
392 (const_int <slot1_offset>))))
393 (set (reg:X RETURN_ADDR_REGNUM)
394 (mem:X (plus:X (reg:X SP_REGNUM)
395 (const_int <slot2_offset>))))
397 (use (reg:SI RETURN_ADDR_REGNUM))]
399 "cm.popret {ra, s0-s1}, %0"
400 [(set_attr "type" "pushpop")])
402 (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
403 [(set (reg:X SP_REGNUM)
404 (plus:X (reg:X SP_REGNUM)
405 (match_operand 0 "stack_pop_up_to_s2_operand" "I")))
406 (set (reg:X S2_REGNUM)
407 (mem:X (plus:X (reg:X SP_REGNUM)
408 (const_int <slot0_offset>))))
409 (set (reg:X S1_REGNUM)
410 (mem:X (plus:X (reg:X SP_REGNUM)
411 (const_int <slot1_offset>))))
412 (set (reg:X S0_REGNUM)
413 (mem:X (plus:X (reg:X SP_REGNUM)
414 (const_int <slot2_offset>))))
415 (set (reg:X RETURN_ADDR_REGNUM)
416 (mem:X (plus:X (reg:X SP_REGNUM)
417 (const_int <slot3_offset>))))
419 (use (reg:SI RETURN_ADDR_REGNUM))]
421 "cm.popret {ra, s0-s2}, %0"
422 [(set_attr "type" "pushpop")])
424 (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
425 [(set (reg:X SP_REGNUM)
426 (plus:X (reg:X SP_REGNUM)
427 (match_operand 0 "stack_pop_up_to_s3_operand" "I")))
428 (set (reg:X S3_REGNUM)
429 (mem:X (plus:X (reg:X SP_REGNUM)
430 (const_int <slot0_offset>))))
431 (set (reg:X S2_REGNUM)
432 (mem:X (plus:X (reg:X SP_REGNUM)
433 (const_int <slot1_offset>))))
434 (set (reg:X S1_REGNUM)
435 (mem:X (plus:X (reg:X SP_REGNUM)
436 (const_int <slot2_offset>))))
437 (set (reg:X S0_REGNUM)
438 (mem:X (plus:X (reg:X SP_REGNUM)
439 (const_int <slot3_offset>))))
440 (set (reg:X RETURN_ADDR_REGNUM)
441 (mem:X (plus:X (reg:X SP_REGNUM)
442 (const_int <slot4_offset>))))
444 (use (reg:SI RETURN_ADDR_REGNUM))]
446 "cm.popret {ra, s0-s3}, %0"
447 [(set_attr "type" "pushpop")])
449 (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
450 [(set (reg:X SP_REGNUM)
451 (plus:X (reg:X SP_REGNUM)
452 (match_operand 0 "stack_pop_up_to_s4_operand" "I")))
453 (set (reg:X S4_REGNUM)
454 (mem:X (plus:X (reg:X SP_REGNUM)
455 (const_int <slot0_offset>))))
456 (set (reg:X S3_REGNUM)
457 (mem:X (plus:X (reg:X SP_REGNUM)
458 (const_int <slot1_offset>))))
459 (set (reg:X S2_REGNUM)
460 (mem:X (plus:X (reg:X SP_REGNUM)
461 (const_int <slot2_offset>))))
462 (set (reg:X S1_REGNUM)
463 (mem:X (plus:X (reg:X SP_REGNUM)
464 (const_int <slot3_offset>))))
465 (set (reg:X S0_REGNUM)
466 (mem:X (plus:X (reg:X SP_REGNUM)
467 (const_int <slot4_offset>))))
468 (set (reg:X RETURN_ADDR_REGNUM)
469 (mem:X (plus:X (reg:X SP_REGNUM)
470 (const_int <slot5_offset>))))
472 (use (reg:SI RETURN_ADDR_REGNUM))]
474 "cm.popret {ra, s0-s4}, %0"
475 [(set_attr "type" "pushpop")])
477 (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
478 [(set (reg:X SP_REGNUM)
479 (plus:X (reg:X SP_REGNUM)
480 (match_operand 0 "stack_pop_up_to_s5_operand" "I")))
481 (set (reg:X S5_REGNUM)
482 (mem:X (plus:X (reg:X SP_REGNUM)
483 (const_int <slot0_offset>))))
484 (set (reg:X S4_REGNUM)
485 (mem:X (plus:X (reg:X SP_REGNUM)
486 (const_int <slot1_offset>))))
487 (set (reg:X S3_REGNUM)
488 (mem:X (plus:X (reg:X SP_REGNUM)
489 (const_int <slot2_offset>))))
490 (set (reg:X S2_REGNUM)
491 (mem:X (plus:X (reg:X SP_REGNUM)
492 (const_int <slot3_offset>))))
493 (set (reg:X S1_REGNUM)
494 (mem:X (plus:X (reg:X SP_REGNUM)
495 (const_int <slot4_offset>))))
496 (set (reg:X S0_REGNUM)
497 (mem:X (plus:X (reg:X SP_REGNUM)
498 (const_int <slot5_offset>))))
499 (set (reg:X RETURN_ADDR_REGNUM)
500 (mem:X (plus:X (reg:X SP_REGNUM)
501 (const_int <slot6_offset>))))
503 (use (reg:SI RETURN_ADDR_REGNUM))]
505 "cm.popret {ra, s0-s5}, %0"
506 [(set_attr "type" "pushpop")])
508 (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
509 [(set (reg:X SP_REGNUM)
510 (plus:X (reg:X SP_REGNUM)
511 (match_operand 0 "stack_pop_up_to_s6_operand" "I")))
512 (set (reg:X S6_REGNUM)
513 (mem:X (plus:X (reg:X SP_REGNUM)
514 (const_int <slot0_offset>))))
515 (set (reg:X S5_REGNUM)
516 (mem:X (plus:X (reg:X SP_REGNUM)
517 (const_int <slot1_offset>))))
518 (set (reg:X S4_REGNUM)
519 (mem:X (plus:X (reg:X SP_REGNUM)
520 (const_int <slot2_offset>))))
521 (set (reg:X S3_REGNUM)
522 (mem:X (plus:X (reg:X SP_REGNUM)
523 (const_int <slot3_offset>))))
524 (set (reg:X S2_REGNUM)
525 (mem:X (plus:X (reg:X SP_REGNUM)
526 (const_int <slot4_offset>))))
527 (set (reg:X S1_REGNUM)
528 (mem:X (plus:X (reg:X SP_REGNUM)
529 (const_int <slot5_offset>))))
530 (set (reg:X S0_REGNUM)
531 (mem:X (plus:X (reg:X SP_REGNUM)
532 (const_int <slot6_offset>))))
533 (set (reg:X RETURN_ADDR_REGNUM)
534 (mem:X (plus:X (reg:X SP_REGNUM)
535 (const_int <slot7_offset>))))
537 (use (reg:SI RETURN_ADDR_REGNUM))]
539 "cm.popret {ra, s0-s6}, %0"
540 [(set_attr "type" "pushpop")])
542 (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
543 [(set (reg:X SP_REGNUM)
544 (plus:X (reg:X SP_REGNUM)
545 (match_operand 0 "stack_pop_up_to_s7_operand" "I")))
546 (set (reg:X S7_REGNUM)
547 (mem:X (plus:X (reg:X SP_REGNUM)
548 (const_int <slot0_offset>))))
549 (set (reg:X S6_REGNUM)
550 (mem:X (plus:X (reg:X SP_REGNUM)
551 (const_int <slot1_offset>))))
552 (set (reg:X S5_REGNUM)
553 (mem:X (plus:X (reg:X SP_REGNUM)
554 (const_int <slot2_offset>))))
555 (set (reg:X S4_REGNUM)
556 (mem:X (plus:X (reg:X SP_REGNUM)
557 (const_int <slot3_offset>))))
558 (set (reg:X S3_REGNUM)
559 (mem:X (plus:X (reg:X SP_REGNUM)
560 (const_int <slot4_offset>))))
561 (set (reg:X S2_REGNUM)
562 (mem:X (plus:X (reg:X SP_REGNUM)
563 (const_int <slot5_offset>))))
564 (set (reg:X S1_REGNUM)
565 (mem:X (plus:X (reg:X SP_REGNUM)
566 (const_int <slot6_offset>))))
567 (set (reg:X S0_REGNUM)
568 (mem:X (plus:X (reg:X SP_REGNUM)
569 (const_int <slot7_offset>))))
570 (set (reg:X RETURN_ADDR_REGNUM)
571 (mem:X (plus:X (reg:X SP_REGNUM)
572 (const_int <slot8_offset>))))
574 (use (reg:SI RETURN_ADDR_REGNUM))]
576 "cm.popret {ra, s0-s7}, %0"
577 [(set_attr "type" "pushpop")])
579 (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
580 [(set (reg:X SP_REGNUM)
581 (plus:X (reg:X SP_REGNUM)
582 (match_operand 0 "stack_pop_up_to_s8_operand" "I")))
583 (set (reg:X S8_REGNUM)
584 (mem:X (plus:X (reg:X SP_REGNUM)
585 (const_int <slot0_offset>))))
586 (set (reg:X S7_REGNUM)
587 (mem:X (plus:X (reg:X SP_REGNUM)
588 (const_int <slot1_offset>))))
589 (set (reg:X S6_REGNUM)
590 (mem:X (plus:X (reg:X SP_REGNUM)
591 (const_int <slot2_offset>))))
592 (set (reg:X S5_REGNUM)
593 (mem:X (plus:X (reg:X SP_REGNUM)
594 (const_int <slot3_offset>))))
595 (set (reg:X S4_REGNUM)
596 (mem:X (plus:X (reg:X SP_REGNUM)
597 (const_int <slot4_offset>))))
598 (set (reg:X S3_REGNUM)
599 (mem:X (plus:X (reg:X SP_REGNUM)
600 (const_int <slot5_offset>))))
601 (set (reg:X S2_REGNUM)
602 (mem:X (plus:X (reg:X SP_REGNUM)
603 (const_int <slot6_offset>))))
604 (set (reg:X S1_REGNUM)
605 (mem:X (plus:X (reg:X SP_REGNUM)
606 (const_int <slot7_offset>))))
607 (set (reg:X S0_REGNUM)
608 (mem:X (plus:X (reg:X SP_REGNUM)
609 (const_int <slot8_offset>))))
610 (set (reg:X RETURN_ADDR_REGNUM)
611 (mem:X (plus:X (reg:X SP_REGNUM)
612 (const_int <slot9_offset>))))
614 (use (reg:SI RETURN_ADDR_REGNUM))]
616 "cm.popret {ra, s0-s8}, %0"
617 [(set_attr "type" "pushpop")])
619 (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
620 [(set (reg:X SP_REGNUM)
621 (plus:X (reg:X SP_REGNUM)
622 (match_operand 0 "stack_pop_up_to_s9_operand" "I")))
623 (set (reg:X S9_REGNUM)
624 (mem:X (plus:X (reg:X SP_REGNUM)
625 (const_int <slot0_offset>))))
626 (set (reg:X S8_REGNUM)
627 (mem:X (plus:X (reg:X SP_REGNUM)
628 (const_int <slot1_offset>))))
629 (set (reg:X S7_REGNUM)
630 (mem:X (plus:X (reg:X SP_REGNUM)
631 (const_int <slot2_offset>))))
632 (set (reg:X S6_REGNUM)
633 (mem:X (plus:X (reg:X SP_REGNUM)
634 (const_int <slot3_offset>))))
635 (set (reg:X S5_REGNUM)
636 (mem:X (plus:X (reg:X SP_REGNUM)
637 (const_int <slot4_offset>))))
638 (set (reg:X S4_REGNUM)
639 (mem:X (plus:X (reg:X SP_REGNUM)
640 (const_int <slot5_offset>))))
641 (set (reg:X S3_REGNUM)
642 (mem:X (plus:X (reg:X SP_REGNUM)
643 (const_int <slot6_offset>))))
644 (set (reg:X S2_REGNUM)
645 (mem:X (plus:X (reg:X SP_REGNUM)
646 (const_int <slot7_offset>))))
647 (set (reg:X S1_REGNUM)
648 (mem:X (plus:X (reg:X SP_REGNUM)
649 (const_int <slot8_offset>))))
650 (set (reg:X S0_REGNUM)
651 (mem:X (plus:X (reg:X SP_REGNUM)
652 (const_int <slot9_offset>))))
653 (set (reg:X RETURN_ADDR_REGNUM)
654 (mem:X (plus:X (reg:X SP_REGNUM)
655 (const_int <slot10_offset>))))
657 (use (reg:SI RETURN_ADDR_REGNUM))]
659 "cm.popret {ra, s0-s9}, %0"
660 [(set_attr "type" "pushpop")])
662 (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
663 [(set (reg:X SP_REGNUM)
664 (plus:X (reg:X SP_REGNUM)
665 (match_operand 0 "stack_pop_up_to_s11_operand" "I")))
666 (set (reg:X S11_REGNUM)
667 (mem:X (plus:X (reg:X SP_REGNUM)
668 (const_int <slot0_offset>))))
669 (set (reg:X S10_REGNUM)
670 (mem:X (plus:X (reg:X SP_REGNUM)
671 (const_int <slot1_offset>))))
672 (set (reg:X S9_REGNUM)
673 (mem:X (plus:X (reg:X SP_REGNUM)
674 (const_int <slot2_offset>))))
675 (set (reg:X S8_REGNUM)
676 (mem:X (plus:X (reg:X SP_REGNUM)
677 (const_int <slot3_offset>))))
678 (set (reg:X S7_REGNUM)
679 (mem:X (plus:X (reg:X SP_REGNUM)
680 (const_int <slot4_offset>))))
681 (set (reg:X S6_REGNUM)
682 (mem:X (plus:X (reg:X SP_REGNUM)
683 (const_int <slot5_offset>))))
684 (set (reg:X S5_REGNUM)
685 (mem:X (plus:X (reg:X SP_REGNUM)
686 (const_int <slot6_offset>))))
687 (set (reg:X S4_REGNUM)
688 (mem:X (plus:X (reg:X SP_REGNUM)
689 (const_int <slot7_offset>))))
690 (set (reg:X S3_REGNUM)
691 (mem:X (plus:X (reg:X SP_REGNUM)
692 (const_int <slot8_offset>))))
693 (set (reg:X S2_REGNUM)
694 (mem:X (plus:X (reg:X SP_REGNUM)
695 (const_int <slot9_offset>))))
696 (set (reg:X S1_REGNUM)
697 (mem:X (plus:X (reg:X SP_REGNUM)
698 (const_int <slot10_offset>))))
699 (set (reg:X S0_REGNUM)
700 (mem:X (plus:X (reg:X SP_REGNUM)
701 (const_int <slot11_offset>))))
702 (set (reg:X RETURN_ADDR_REGNUM)
703 (mem:X (plus:X (reg:X SP_REGNUM)
704 (const_int <slot12_offset>))))
706 (use (reg:SI RETURN_ADDR_REGNUM))]
708 "cm.popret {ra, s0-s11}, %0"
709 [(set_attr "type" "pushpop")])
711 (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
712 [(set (reg:X SP_REGNUM)
713 (plus:X (reg:X SP_REGNUM)
714 (match_operand 0 "stack_pop_up_to_ra_operand" "I")))
715 (set (reg:X RETURN_ADDR_REGNUM)
716 (mem:X (plus:X (reg:X SP_REGNUM)
717 (const_int <slot0_offset>))))
718 (set (reg:X A0_REGNUM)
720 (use (reg:X A0_REGNUM))
722 (use (reg:SI RETURN_ADDR_REGNUM))]
724 "cm.popretz {ra}, %0"
725 [(set_attr "type" "pushpop")])
727 (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
728 [(set (reg:X SP_REGNUM)
729 (plus:X (reg:X SP_REGNUM)
730 (match_operand 0 "stack_pop_up_to_s0_operand" "I")))
731 (set (reg:X S0_REGNUM)
732 (mem:X (plus:X (reg:X SP_REGNUM)
733 (const_int <slot0_offset>))))
734 (set (reg:X RETURN_ADDR_REGNUM)
735 (mem:X (plus:X (reg:X SP_REGNUM)
736 (const_int <slot1_offset>))))
737 (set (reg:X A0_REGNUM)
739 (use (reg:X A0_REGNUM))
741 (use (reg:SI RETURN_ADDR_REGNUM))]
743 "cm.popretz {ra, s0}, %0"
744 [(set_attr "type" "pushpop")])
746 (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
747 [(set (reg:X SP_REGNUM)
748 (plus:X (reg:X SP_REGNUM)
749 (match_operand 0 "stack_pop_up_to_s1_operand" "I")))
750 (set (reg:X S1_REGNUM)
751 (mem:X (plus:X (reg:X SP_REGNUM)
752 (const_int <slot0_offset>))))
753 (set (reg:X S0_REGNUM)
754 (mem:X (plus:X (reg:X SP_REGNUM)
755 (const_int <slot1_offset>))))
756 (set (reg:X RETURN_ADDR_REGNUM)
757 (mem:X (plus:X (reg:X SP_REGNUM)
758 (const_int <slot2_offset>))))
759 (set (reg:X A0_REGNUM)
761 (use (reg:X A0_REGNUM))
763 (use (reg:SI RETURN_ADDR_REGNUM))]
765 "cm.popretz {ra, s0-s1}, %0"
766 [(set_attr "type" "pushpop")])
768 (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
769 [(set (reg:X SP_REGNUM)
770 (plus:X (reg:X SP_REGNUM)
771 (match_operand 0 "stack_pop_up_to_s2_operand" "I")))
772 (set (reg:X S2_REGNUM)
773 (mem:X (plus:X (reg:X SP_REGNUM)
774 (const_int <slot0_offset>))))
775 (set (reg:X S1_REGNUM)
776 (mem:X (plus:X (reg:X SP_REGNUM)
777 (const_int <slot1_offset>))))
778 (set (reg:X S0_REGNUM)
779 (mem:X (plus:X (reg:X SP_REGNUM)
780 (const_int <slot2_offset>))))
781 (set (reg:X RETURN_ADDR_REGNUM)
782 (mem:X (plus:X (reg:X SP_REGNUM)
783 (const_int <slot3_offset>))))
784 (set (reg:X A0_REGNUM)
786 (use (reg:X A0_REGNUM))
788 (use (reg:SI RETURN_ADDR_REGNUM))]
790 "cm.popretz {ra, s0-s2}, %0"
791 [(set_attr "type" "pushpop")])
793 (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
794 [(set (reg:X SP_REGNUM)
795 (plus:X (reg:X SP_REGNUM)
796 (match_operand 0 "stack_pop_up_to_s3_operand" "I")))
797 (set (reg:X S3_REGNUM)
798 (mem:X (plus:X (reg:X SP_REGNUM)
799 (const_int <slot0_offset>))))
800 (set (reg:X S2_REGNUM)
801 (mem:X (plus:X (reg:X SP_REGNUM)
802 (const_int <slot1_offset>))))
803 (set (reg:X S1_REGNUM)
804 (mem:X (plus:X (reg:X SP_REGNUM)
805 (const_int <slot2_offset>))))
806 (set (reg:X S0_REGNUM)
807 (mem:X (plus:X (reg:X SP_REGNUM)
808 (const_int <slot3_offset>))))
809 (set (reg:X RETURN_ADDR_REGNUM)
810 (mem:X (plus:X (reg:X SP_REGNUM)
811 (const_int <slot4_offset>))))
812 (set (reg:X A0_REGNUM)
814 (use (reg:X A0_REGNUM))
816 (use (reg:SI RETURN_ADDR_REGNUM))]
818 "cm.popretz {ra, s0-s3}, %0"
819 [(set_attr "type" "pushpop")])
821 (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
822 [(set (reg:X SP_REGNUM)
823 (plus:X (reg:X SP_REGNUM)
824 (match_operand 0 "stack_pop_up_to_s4_operand" "I")))
825 (set (reg:X S4_REGNUM)
826 (mem:X (plus:X (reg:X SP_REGNUM)
827 (const_int <slot0_offset>))))
828 (set (reg:X S3_REGNUM)
829 (mem:X (plus:X (reg:X SP_REGNUM)
830 (const_int <slot1_offset>))))
831 (set (reg:X S2_REGNUM)
832 (mem:X (plus:X (reg:X SP_REGNUM)
833 (const_int <slot2_offset>))))
834 (set (reg:X S1_REGNUM)
835 (mem:X (plus:X (reg:X SP_REGNUM)
836 (const_int <slot3_offset>))))
837 (set (reg:X S0_REGNUM)
838 (mem:X (plus:X (reg:X SP_REGNUM)
839 (const_int <slot4_offset>))))
840 (set (reg:X RETURN_ADDR_REGNUM)
841 (mem:X (plus:X (reg:X SP_REGNUM)
842 (const_int <slot5_offset>))))
843 (set (reg:X A0_REGNUM)
845 (use (reg:X A0_REGNUM))
847 (use (reg:SI RETURN_ADDR_REGNUM))]
849 "cm.popretz {ra, s0-s4}, %0"
850 [(set_attr "type" "pushpop")])
852 (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
853 [(set (reg:X SP_REGNUM)
854 (plus:X (reg:X SP_REGNUM)
855 (match_operand 0 "stack_pop_up_to_s5_operand" "I")))
856 (set (reg:X S5_REGNUM)
857 (mem:X (plus:X (reg:X SP_REGNUM)
858 (const_int <slot0_offset>))))
859 (set (reg:X S4_REGNUM)
860 (mem:X (plus:X (reg:X SP_REGNUM)
861 (const_int <slot1_offset>))))
862 (set (reg:X S3_REGNUM)
863 (mem:X (plus:X (reg:X SP_REGNUM)
864 (const_int <slot2_offset>))))
865 (set (reg:X S2_REGNUM)
866 (mem:X (plus:X (reg:X SP_REGNUM)
867 (const_int <slot3_offset>))))
868 (set (reg:X S1_REGNUM)
869 (mem:X (plus:X (reg:X SP_REGNUM)
870 (const_int <slot4_offset>))))
871 (set (reg:X S0_REGNUM)
872 (mem:X (plus:X (reg:X SP_REGNUM)
873 (const_int <slot5_offset>))))
874 (set (reg:X RETURN_ADDR_REGNUM)
875 (mem:X (plus:X (reg:X SP_REGNUM)
876 (const_int <slot6_offset>))))
877 (set (reg:X A0_REGNUM)
879 (use (reg:X A0_REGNUM))
881 (use (reg:SI RETURN_ADDR_REGNUM))]
883 "cm.popretz {ra, s0-s5}, %0"
884 [(set_attr "type" "pushpop")])
886 (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
887 [(set (reg:X SP_REGNUM)
888 (plus:X (reg:X SP_REGNUM)
889 (match_operand 0 "stack_pop_up_to_s6_operand" "I")))
890 (set (reg:X S6_REGNUM)
891 (mem:X (plus:X (reg:X SP_REGNUM)
892 (const_int <slot0_offset>))))
893 (set (reg:X S5_REGNUM)
894 (mem:X (plus:X (reg:X SP_REGNUM)
895 (const_int <slot1_offset>))))
896 (set (reg:X S4_REGNUM)
897 (mem:X (plus:X (reg:X SP_REGNUM)
898 (const_int <slot2_offset>))))
899 (set (reg:X S3_REGNUM)
900 (mem:X (plus:X (reg:X SP_REGNUM)
901 (const_int <slot3_offset>))))
902 (set (reg:X S2_REGNUM)
903 (mem:X (plus:X (reg:X SP_REGNUM)
904 (const_int <slot4_offset>))))
905 (set (reg:X S1_REGNUM)
906 (mem:X (plus:X (reg:X SP_REGNUM)
907 (const_int <slot5_offset>))))
908 (set (reg:X S0_REGNUM)
909 (mem:X (plus:X (reg:X SP_REGNUM)
910 (const_int <slot6_offset>))))
911 (set (reg:X RETURN_ADDR_REGNUM)
912 (mem:X (plus:X (reg:X SP_REGNUM)
913 (const_int <slot7_offset>))))
914 (set (reg:X A0_REGNUM)
916 (use (reg:X A0_REGNUM))
918 (use (reg:SI RETURN_ADDR_REGNUM))]
920 "cm.popretz {ra, s0-s6}, %0"
921 [(set_attr "type" "pushpop")])
923 (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
924 [(set (reg:X SP_REGNUM)
925 (plus:X (reg:X SP_REGNUM)
926 (match_operand 0 "stack_pop_up_to_s7_operand" "I")))
927 (set (reg:X S7_REGNUM)
928 (mem:X (plus:X (reg:X SP_REGNUM)
929 (const_int <slot0_offset>))))
930 (set (reg:X S6_REGNUM)
931 (mem:X (plus:X (reg:X SP_REGNUM)
932 (const_int <slot1_offset>))))
933 (set (reg:X S5_REGNUM)
934 (mem:X (plus:X (reg:X SP_REGNUM)
935 (const_int <slot2_offset>))))
936 (set (reg:X S4_REGNUM)
937 (mem:X (plus:X (reg:X SP_REGNUM)
938 (const_int <slot3_offset>))))
939 (set (reg:X S3_REGNUM)
940 (mem:X (plus:X (reg:X SP_REGNUM)
941 (const_int <slot4_offset>))))
942 (set (reg:X S2_REGNUM)
943 (mem:X (plus:X (reg:X SP_REGNUM)
944 (const_int <slot5_offset>))))
945 (set (reg:X S1_REGNUM)
946 (mem:X (plus:X (reg:X SP_REGNUM)
947 (const_int <slot6_offset>))))
948 (set (reg:X S0_REGNUM)
949 (mem:X (plus:X (reg:X SP_REGNUM)
950 (const_int <slot7_offset>))))
951 (set (reg:X RETURN_ADDR_REGNUM)
952 (mem:X (plus:X (reg:X SP_REGNUM)
953 (const_int <slot8_offset>))))
954 (set (reg:X A0_REGNUM)
956 (use (reg:X A0_REGNUM))
958 (use (reg:SI RETURN_ADDR_REGNUM))]
960 "cm.popretz {ra, s0-s7}, %0"
961 [(set_attr "type" "pushpop")])
963 (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
964 [(set (reg:X SP_REGNUM)
965 (plus:X (reg:X SP_REGNUM)
966 (match_operand 0 "stack_pop_up_to_s8_operand" "I")))
967 (set (reg:X S8_REGNUM)
968 (mem:X (plus:X (reg:X SP_REGNUM)
969 (const_int <slot0_offset>))))
970 (set (reg:X S7_REGNUM)
971 (mem:X (plus:X (reg:X SP_REGNUM)
972 (const_int <slot1_offset>))))
973 (set (reg:X S6_REGNUM)
974 (mem:X (plus:X (reg:X SP_REGNUM)
975 (const_int <slot2_offset>))))
976 (set (reg:X S5_REGNUM)
977 (mem:X (plus:X (reg:X SP_REGNUM)
978 (const_int <slot3_offset>))))
979 (set (reg:X S4_REGNUM)
980 (mem:X (plus:X (reg:X SP_REGNUM)
981 (const_int <slot4_offset>))))
982 (set (reg:X S3_REGNUM)
983 (mem:X (plus:X (reg:X SP_REGNUM)
984 (const_int <slot5_offset>))))
985 (set (reg:X S2_REGNUM)
986 (mem:X (plus:X (reg:X SP_REGNUM)
987 (const_int <slot6_offset>))))
988 (set (reg:X S1_REGNUM)
989 (mem:X (plus:X (reg:X SP_REGNUM)
990 (const_int <slot7_offset>))))
991 (set (reg:X S0_REGNUM)
992 (mem:X (plus:X (reg:X SP_REGNUM)
993 (const_int <slot8_offset>))))
994 (set (reg:X RETURN_ADDR_REGNUM)
995 (mem:X (plus:X (reg:X SP_REGNUM)
996 (const_int <slot9_offset>))))
997 (set (reg:X A0_REGNUM)
999 (use (reg:X A0_REGNUM))
1001 (use (reg:SI RETURN_ADDR_REGNUM))]
1003 "cm.popretz {ra, s0-s8}, %0"
1004 [(set_attr "type" "pushpop")])
1006 (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
1007 [(set (reg:X SP_REGNUM)
1008 (plus:X (reg:X SP_REGNUM)
1009 (match_operand 0 "stack_pop_up_to_s9_operand" "I")))
1010 (set (reg:X S9_REGNUM)
1011 (mem:X (plus:X (reg:X SP_REGNUM)
1012 (const_int <slot0_offset>))))
1013 (set (reg:X S8_REGNUM)
1014 (mem:X (plus:X (reg:X SP_REGNUM)
1015 (const_int <slot1_offset>))))
1016 (set (reg:X S7_REGNUM)
1017 (mem:X (plus:X (reg:X SP_REGNUM)
1018 (const_int <slot2_offset>))))
1019 (set (reg:X S6_REGNUM)
1020 (mem:X (plus:X (reg:X SP_REGNUM)
1021 (const_int <slot3_offset>))))
1022 (set (reg:X S5_REGNUM)
1023 (mem:X (plus:X (reg:X SP_REGNUM)
1024 (const_int <slot4_offset>))))
1025 (set (reg:X S4_REGNUM)
1026 (mem:X (plus:X (reg:X SP_REGNUM)
1027 (const_int <slot5_offset>))))
1028 (set (reg:X S3_REGNUM)
1029 (mem:X (plus:X (reg:X SP_REGNUM)
1030 (const_int <slot6_offset>))))
1031 (set (reg:X S2_REGNUM)
1032 (mem:X (plus:X (reg:X SP_REGNUM)
1033 (const_int <slot7_offset>))))
1034 (set (reg:X S1_REGNUM)
1035 (mem:X (plus:X (reg:X SP_REGNUM)
1036 (const_int <slot8_offset>))))
1037 (set (reg:X S0_REGNUM)
1038 (mem:X (plus:X (reg:X SP_REGNUM)
1039 (const_int <slot9_offset>))))
1040 (set (reg:X RETURN_ADDR_REGNUM)
1041 (mem:X (plus:X (reg:X SP_REGNUM)
1042 (const_int <slot10_offset>))))
1043 (set (reg:X A0_REGNUM)
1045 (use (reg:X A0_REGNUM))
1047 (use (reg:SI RETURN_ADDR_REGNUM))]
1049 "cm.popretz {ra, s0-s9}, %0"
1050 [(set_attr "type" "pushpop")])
1052 (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
1053 [(set (reg:X SP_REGNUM)
1054 (plus:X (reg:X SP_REGNUM)
1055 (match_operand 0 "stack_pop_up_to_s11_operand" "I")))
1056 (set (reg:X S11_REGNUM)
1057 (mem:X (plus:X (reg:X SP_REGNUM)
1058 (const_int <slot0_offset>))))
1059 (set (reg:X S10_REGNUM)
1060 (mem:X (plus:X (reg:X SP_REGNUM)
1061 (const_int <slot1_offset>))))
1062 (set (reg:X S9_REGNUM)
1063 (mem:X (plus:X (reg:X SP_REGNUM)
1064 (const_int <slot2_offset>))))
1065 (set (reg:X S8_REGNUM)
1066 (mem:X (plus:X (reg:X SP_REGNUM)
1067 (const_int <slot3_offset>))))
1068 (set (reg:X S7_REGNUM)
1069 (mem:X (plus:X (reg:X SP_REGNUM)
1070 (const_int <slot4_offset>))))
1071 (set (reg:X S6_REGNUM)
1072 (mem:X (plus:X (reg:X SP_REGNUM)
1073 (const_int <slot5_offset>))))
1074 (set (reg:X S5_REGNUM)
1075 (mem:X (plus:X (reg:X SP_REGNUM)
1076 (const_int <slot6_offset>))))
1077 (set (reg:X S4_REGNUM)
1078 (mem:X (plus:X (reg:X SP_REGNUM)
1079 (const_int <slot7_offset>))))
1080 (set (reg:X S3_REGNUM)
1081 (mem:X (plus:X (reg:X SP_REGNUM)
1082 (const_int <slot8_offset>))))
1083 (set (reg:X S2_REGNUM)
1084 (mem:X (plus:X (reg:X SP_REGNUM)
1085 (const_int <slot9_offset>))))
1086 (set (reg:X S1_REGNUM)
1087 (mem:X (plus:X (reg:X SP_REGNUM)
1088 (const_int <slot10_offset>))))
1089 (set (reg:X S0_REGNUM)
1090 (mem:X (plus:X (reg:X SP_REGNUM)
1091 (const_int <slot11_offset>))))
1092 (set (reg:X RETURN_ADDR_REGNUM)
1093 (mem:X (plus:X (reg:X SP_REGNUM)
1094 (const_int <slot12_offset>))))
1095 (set (reg:X A0_REGNUM)
1097 (use (reg:X A0_REGNUM))
1099 (use (reg:SI RETURN_ADDR_REGNUM))]
1101 "cm.popretz {ra, s0-s11}, %0"
1102 [(set_attr "type" "pushpop")])
1104 (define_insn "@gpr_multi_push_up_to_ra_<mode>"
1105 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1106 (const_int <slot0_offset>)))
1107 (reg:X RETURN_ADDR_REGNUM))
1108 (set (reg:X SP_REGNUM)
1109 (plus:X (reg:X SP_REGNUM)
1110 (match_operand 0 "stack_push_up_to_ra_operand" "I")))]
1113 [(set_attr "type" "pushpop")])
1115 (define_insn "@gpr_multi_push_up_to_s0_<mode>"
1116 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1117 (const_int <slot0_offset>)))
1119 (set (mem:X (plus:X (reg:X SP_REGNUM)
1120 (const_int <slot1_offset>)))
1121 (reg:X RETURN_ADDR_REGNUM))
1122 (set (reg:X SP_REGNUM)
1123 (plus:X (reg:X SP_REGNUM)
1124 (match_operand 0 "stack_push_up_to_s0_operand" "I")))]
1126 "cm.push {ra, s0}, %0"
1127 [(set_attr "type" "pushpop")])
1129 (define_insn "@gpr_multi_push_up_to_s1_<mode>"
1130 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1131 (const_int <slot0_offset>)))
1133 (set (mem:X (plus:X (reg:X SP_REGNUM)
1134 (const_int <slot1_offset>)))
1136 (set (mem:X (plus:X (reg:X SP_REGNUM)
1137 (const_int <slot2_offset>)))
1138 (reg:X RETURN_ADDR_REGNUM))
1139 (set (reg:X SP_REGNUM)
1140 (plus:X (reg:X SP_REGNUM)
1141 (match_operand 0 "stack_push_up_to_s1_operand" "I")))]
1143 "cm.push {ra, s0-s1}, %0"
1144 [(set_attr "type" "pushpop")])
1146 (define_insn "@gpr_multi_push_up_to_s2_<mode>"
1147 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1148 (const_int <slot0_offset>)))
1150 (set (mem:X (plus:X (reg:X SP_REGNUM)
1151 (const_int <slot1_offset>)))
1153 (set (mem:X (plus:X (reg:X SP_REGNUM)
1154 (const_int <slot2_offset>)))
1156 (set (mem:X (plus:X (reg:X SP_REGNUM)
1157 (const_int <slot3_offset>)))
1158 (reg:X RETURN_ADDR_REGNUM))
1159 (set (reg:X SP_REGNUM)
1160 (plus:X (reg:X SP_REGNUM)
1161 (match_operand 0 "stack_push_up_to_s2_operand" "I")))]
1163 "cm.push {ra, s0-s2}, %0"
1164 [(set_attr "type" "pushpop")])
1166 (define_insn "@gpr_multi_push_up_to_s3_<mode>"
1167 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1168 (const_int <slot0_offset>)))
1170 (set (mem:X (plus:X (reg:X SP_REGNUM)
1171 (const_int <slot1_offset>)))
1173 (set (mem:X (plus:X (reg:X SP_REGNUM)
1174 (const_int <slot2_offset>)))
1176 (set (mem:X (plus:X (reg:X SP_REGNUM)
1177 (const_int <slot3_offset>)))
1179 (set (mem:X (plus:X (reg:X SP_REGNUM)
1180 (const_int <slot4_offset>)))
1181 (reg:X RETURN_ADDR_REGNUM))
1182 (set (reg:X SP_REGNUM)
1183 (plus:X (reg:X SP_REGNUM)
1184 (match_operand 0 "stack_push_up_to_s3_operand" "I")))]
1186 "cm.push {ra, s0-s3}, %0"
1187 [(set_attr "type" "pushpop")])
1189 (define_insn "@gpr_multi_push_up_to_s4_<mode>"
1190 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1191 (const_int <slot0_offset>)))
1193 (set (mem:X (plus:X (reg:X SP_REGNUM)
1194 (const_int <slot1_offset>)))
1196 (set (mem:X (plus:X (reg:X SP_REGNUM)
1197 (const_int <slot2_offset>)))
1199 (set (mem:X (plus:X (reg:X SP_REGNUM)
1200 (const_int <slot3_offset>)))
1202 (set (mem:X (plus:X (reg:X SP_REGNUM)
1203 (const_int <slot4_offset>)))
1205 (set (mem:X (plus:X (reg:X SP_REGNUM)
1206 (const_int <slot5_offset>)))
1207 (reg:X RETURN_ADDR_REGNUM))
1208 (set (reg:X SP_REGNUM)
1209 (plus:X (reg:X SP_REGNUM)
1210 (match_operand 0 "stack_push_up_to_s4_operand" "I")))]
1212 "cm.push {ra, s0-s4}, %0"
1213 [(set_attr "type" "pushpop")])
1215 (define_insn "@gpr_multi_push_up_to_s5_<mode>"
1216 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1217 (const_int <slot0_offset>)))
1219 (set (mem:X (plus:X (reg:X SP_REGNUM)
1220 (const_int <slot1_offset>)))
1222 (set (mem:X (plus:X (reg:X SP_REGNUM)
1223 (const_int <slot2_offset>)))
1225 (set (mem:X (plus:X (reg:X SP_REGNUM)
1226 (const_int <slot3_offset>)))
1228 (set (mem:X (plus:X (reg:X SP_REGNUM)
1229 (const_int <slot4_offset>)))
1231 (set (mem:X (plus:X (reg:X SP_REGNUM)
1232 (const_int <slot5_offset>)))
1234 (set (mem:X (plus:X (reg:X SP_REGNUM)
1235 (const_int <slot6_offset>)))
1236 (reg:X RETURN_ADDR_REGNUM))
1237 (set (reg:X SP_REGNUM)
1238 (plus:X (reg:X SP_REGNUM)
1239 (match_operand 0 "stack_push_up_to_s5_operand" "I")))]
1241 "cm.push {ra, s0-s5}, %0"
1242 [(set_attr "type" "pushpop")])
1244 (define_insn "@gpr_multi_push_up_to_s6_<mode>"
1245 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1246 (const_int <slot0_offset>)))
1248 (set (mem:X (plus:X (reg:X SP_REGNUM)
1249 (const_int <slot1_offset>)))
1251 (set (mem:X (plus:X (reg:X SP_REGNUM)
1252 (const_int <slot2_offset>)))
1254 (set (mem:X (plus:X (reg:X SP_REGNUM)
1255 (const_int <slot3_offset>)))
1257 (set (mem:X (plus:X (reg:X SP_REGNUM)
1258 (const_int <slot4_offset>)))
1260 (set (mem:X (plus:X (reg:X SP_REGNUM)
1261 (const_int <slot5_offset>)))
1263 (set (mem:X (plus:X (reg:X SP_REGNUM)
1264 (const_int <slot6_offset>)))
1266 (set (mem:X (plus:X (reg:X SP_REGNUM)
1267 (const_int <slot7_offset>)))
1268 (reg:X RETURN_ADDR_REGNUM))
1269 (set (reg:X SP_REGNUM)
1270 (plus:X (reg:X SP_REGNUM)
1271 (match_operand 0 "stack_push_up_to_s6_operand" "I")))]
1273 "cm.push {ra, s0-s6}, %0"
1274 [(set_attr "type" "pushpop")])
1276 (define_insn "@gpr_multi_push_up_to_s7_<mode>"
1277 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1278 (const_int <slot0_offset>)))
1280 (set (mem:X (plus:X (reg:X SP_REGNUM)
1281 (const_int <slot1_offset>)))
1283 (set (mem:X (plus:X (reg:X SP_REGNUM)
1284 (const_int <slot2_offset>)))
1286 (set (mem:X (plus:X (reg:X SP_REGNUM)
1287 (const_int <slot3_offset>)))
1289 (set (mem:X (plus:X (reg:X SP_REGNUM)
1290 (const_int <slot4_offset>)))
1292 (set (mem:X (plus:X (reg:X SP_REGNUM)
1293 (const_int <slot5_offset>)))
1295 (set (mem:X (plus:X (reg:X SP_REGNUM)
1296 (const_int <slot6_offset>)))
1298 (set (mem:X (plus:X (reg:X SP_REGNUM)
1299 (const_int <slot7_offset>)))
1301 (set (mem:X (plus:X (reg:X SP_REGNUM)
1302 (const_int <slot8_offset>)))
1303 (reg:X RETURN_ADDR_REGNUM))
1304 (set (reg:X SP_REGNUM)
1305 (plus:X (reg:X SP_REGNUM)
1306 (match_operand 0 "stack_push_up_to_s7_operand" "I")))]
1308 "cm.push {ra, s0-s7}, %0"
1309 [(set_attr "type" "pushpop")])
1311 (define_insn "@gpr_multi_push_up_to_s8_<mode>"
1312 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1313 (const_int <slot0_offset>)))
1315 (set (mem:X (plus:X (reg:X SP_REGNUM)
1316 (const_int <slot1_offset>)))
1318 (set (mem:X (plus:X (reg:X SP_REGNUM)
1319 (const_int <slot2_offset>)))
1321 (set (mem:X (plus:X (reg:X SP_REGNUM)
1322 (const_int <slot3_offset>)))
1324 (set (mem:X (plus:X (reg:X SP_REGNUM)
1325 (const_int <slot4_offset>)))
1327 (set (mem:X (plus:X (reg:X SP_REGNUM)
1328 (const_int <slot5_offset>)))
1330 (set (mem:X (plus:X (reg:X SP_REGNUM)
1331 (const_int <slot6_offset>)))
1333 (set (mem:X (plus:X (reg:X SP_REGNUM)
1334 (const_int <slot7_offset>)))
1336 (set (mem:X (plus:X (reg:X SP_REGNUM)
1337 (const_int <slot8_offset>)))
1339 (set (mem:X (plus:X (reg:X SP_REGNUM)
1340 (const_int <slot9_offset>)))
1341 (reg:X RETURN_ADDR_REGNUM))
1342 (set (reg:X SP_REGNUM)
1343 (plus:X (reg:X SP_REGNUM)
1344 (match_operand 0 "stack_push_up_to_s8_operand" "I")))]
1346 "cm.push {ra, s0-s8}, %0"
1347 [(set_attr "type" "pushpop")])
1349 (define_insn "@gpr_multi_push_up_to_s9_<mode>"
1350 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1351 (const_int <slot0_offset>)))
1353 (set (mem:X (plus:X (reg:X SP_REGNUM)
1354 (const_int <slot1_offset>)))
1356 (set (mem:X (plus:X (reg:X SP_REGNUM)
1357 (const_int <slot2_offset>)))
1359 (set (mem:X (plus:X (reg:X SP_REGNUM)
1360 (const_int <slot3_offset>)))
1362 (set (mem:X (plus:X (reg:X SP_REGNUM)
1363 (const_int <slot4_offset>)))
1365 (set (mem:X (plus:X (reg:X SP_REGNUM)
1366 (const_int <slot5_offset>)))
1368 (set (mem:X (plus:X (reg:X SP_REGNUM)
1369 (const_int <slot6_offset>)))
1371 (set (mem:X (plus:X (reg:X SP_REGNUM)
1372 (const_int <slot7_offset>)))
1374 (set (mem:X (plus:X (reg:X SP_REGNUM)
1375 (const_int <slot8_offset>)))
1377 (set (mem:X (plus:X (reg:X SP_REGNUM)
1378 (const_int <slot9_offset>)))
1380 (set (mem:X (plus:X (reg:X SP_REGNUM)
1381 (const_int <slot10_offset>)))
1382 (reg:X RETURN_ADDR_REGNUM))
1383 (set (reg:X SP_REGNUM)
1384 (plus:X (reg:X SP_REGNUM)
1385 (match_operand 0 "stack_push_up_to_s9_operand" "I")))]
1387 "cm.push {ra, s0-s9}, %0"
1388 [(set_attr "type" "pushpop")])
1390 (define_insn "@gpr_multi_push_up_to_s11_<mode>"
1391 [(set (mem:X (plus:X (reg:X SP_REGNUM)
1392 (const_int <slot0_offset>)))
1394 (set (mem:X (plus:X (reg:X SP_REGNUM)
1395 (const_int <slot1_offset>)))
1397 (set (mem:X (plus:X (reg:X SP_REGNUM)
1398 (const_int <slot2_offset>)))
1400 (set (mem:X (plus:X (reg:X SP_REGNUM)
1401 (const_int <slot3_offset>)))
1403 (set (mem:X (plus:X (reg:X SP_REGNUM)
1404 (const_int <slot4_offset>)))
1406 (set (mem:X (plus:X (reg:X SP_REGNUM)
1407 (const_int <slot5_offset>)))
1409 (set (mem:X (plus:X (reg:X SP_REGNUM)
1410 (const_int <slot6_offset>)))
1412 (set (mem:X (plus:X (reg:X SP_REGNUM)
1413 (const_int <slot7_offset>)))
1415 (set (mem:X (plus:X (reg:X SP_REGNUM)
1416 (const_int <slot8_offset>)))
1418 (set (mem:X (plus:X (reg:X SP_REGNUM)
1419 (const_int <slot9_offset>)))
1421 (set (mem:X (plus:X (reg:X SP_REGNUM)
1422 (const_int <slot10_offset>)))
1424 (set (mem:X (plus:X (reg:X SP_REGNUM)
1425 (const_int <slot11_offset>)))
1427 (set (mem:X (plus:X (reg:X SP_REGNUM)
1428 (const_int <slot12_offset>)))
1429 (reg:X RETURN_ADDR_REGNUM))
1430 (set (reg:X SP_REGNUM)
1431 (plus:X (reg:X SP_REGNUM)
1432 (match_operand 0 "stack_push_up_to_s11_operand" "I")))]
1434 "cm.push {ra, s0-s11}, %0"
1435 [(set_attr "type" "pushpop")])
1438 (define_insn "*mva01s<X:mode>"
1439 [(set (match_operand:X 0 "a0a1_reg_operand" "=r")
1440 (match_operand:X 1 "zcmp_mv_sreg_operand" "r"))
1441 (set (match_operand:X 2 "a0a1_reg_operand" "=r")
1442 (match_operand:X 3 "zcmp_mv_sreg_operand" "r"))]
1444 && (REGNO (operands[2]) != REGNO (operands[0]))"
1445 { return (REGNO (operands[0]) == A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; }
1446 [(set_attr "mode" "<X:MODE>")
1447 (set_attr "type" "mvpair")])
1449 (define_insn "*mvsa01<X:mode>"
1450 [(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r")
1451 (match_operand:X 1 "a0a1_reg_operand" "r"))
1452 (set (match_operand:X 2 "zcmp_mv_sreg_operand" "=r")
1453 (match_operand:X 3 "a0a1_reg_operand" "r"))]
1455 && (REGNO (operands[0]) != REGNO (operands[2]))
1456 && (REGNO (operands[1]) != REGNO (operands[3]))"
1457 { return (REGNO (operands[1]) == A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; }
1458 [(set_attr "mode" "<X:MODE>")
1459 (set_attr "type" "mvpair")])