gcc/config/rs6000/8540.md

   1 ;; Pipeline description for Motorola PowerPC 8540 processor.
   2 ;;   Copyright (C) 2003-2020 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 3, or (at your
   9 ;; option) any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
  21 (define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
  22
  23 ;; We don't simulate general issue queue (GIC).  If we have SU insn
  24 ;; and then SU1 insn, they cannot be issued on the same cycle
  25 ;; (although SU1 insn and then SU insn can be issued) because the SU
  26 ;; insn will go to SU1 from GIC0 entry.  Fortunately, the first cycle
  27 ;; multipass insn scheduling will find the situation and issue the SU1
  28 ;; insn and then the SU insn.
  29 (define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1"   "ppc8540_most")
  30
  31 ;; We could describe completion buffers slots in combination with the
  32 ;; retirement units and the order of completion but the result
  33 ;; automaton would behave in the same way because we cannot describe
  34 ;; real latency time with taking in order completion into account.
  35 ;; Actually we could define the real latency time by querying reserved
  36 ;; automaton units but the current scheduler uses latency time before
  37 ;; issuing insns and making any reservations.
  38 ;;
  39 ;; So our description is aimed to achieve a insn schedule in which the
  40 ;; insns would not wait in the completion buffer.
  41 (define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
  42
  43 ;; Branch unit:
  44 (define_cpu_unit "ppc8540_bu" "ppc8540_most")
  45
  46 ;; SU:
  47 (define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
  48
  49 ;; We could describe here MU subunits for float multiply, float add
  50 ;; etc.  But the result automaton would behave the same way as the
  51 ;; described one pipeline below because MU can start only one insn
  52 ;; per cycle.  Actually we could simplify the automaton more not
  53 ;; describing stages 1-3, the result automata would be the same.
  54 (define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
  55 (define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
  56
  57 ;; The following unit is used to describe non-pipelined division.
  58 (define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
  59
  60 ;; Here we simplified LSU unit description not describing the stages.
  61 (define_cpu_unit "ppc8540_lsu" "ppc8540_most")
  62
  63 ;; The following units are used to make automata deterministic
  64 (define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
  65 (define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
  66 (define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
  67 (define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
  68
  69 ;; The following sets to make automata deterministic when option ndfa is used.
  70 (presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
  71 (presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
  72 (presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
  73 (presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
  74
  75 ;; Some useful abbreviations.
  76 (define_reservation "ppc8540_decode"
  77     "ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0")
  78 (define_reservation "ppc8540_issue"
  79     "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
  80 (define_reservation "ppc8540_retire"
  81    "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
  82 (define_reservation "ppc8540_su_stage0"
  83    "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
  84
  85 ;; Simple SU insns
  86 (define_insn_reservation "ppc8540_su" 1
  87   (and (eq_attr "type" "integer,add,logical,insert,cmp,\
  88                         shift,trap,cntlz,exts,isel")
  89        (eq_attr "cpu" "ppc8540,ppc8548"))
  90   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
  91
  92 (define_insn_reservation "ppc8540_two" 1
  93   (and (eq_attr "type" "two")
  94        (eq_attr "cpu" "ppc8540,ppc8548"))
  95   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
  96    ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
  97
  98 (define_insn_reservation "ppc8540_three" 1
  99   (and (eq_attr "type" "three")
 100        (eq_attr "cpu" "ppc8540,ppc8548"))
 101   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
 102    ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
 103    ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
 104
 105 ;; Branch.  Actually this latency time is not used by the scheduler.
 106 (define_insn_reservation "ppc8540_branch" 1
 107   (and (eq_attr "type" "jmpreg,branch,isync")
 108        (eq_attr "cpu" "ppc8540,ppc8548"))
 109   "ppc8540_decode,ppc8540_bu,ppc8540_retire")
 110
 111 ;; Multiply
 112 (define_insn_reservation "ppc8540_multiply" 4
 113   (and (eq_attr "type" "mul")
 114        (eq_attr "cpu" "ppc8540,ppc8548"))
 115   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
 116    ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
 117
 118 ;; Divide.  We use the average latency time here.  We omit reserving a
 119 ;; retire unit because of the result automata will be huge.  We ignore
 120 ;; reservation of miu_stage3 here because we use the average latency
 121 ;; time.
 122 (define_insn_reservation "ppc8540_divide" 14
 123   (and (eq_attr "type" "div")
 124        (eq_attr "cpu" "ppc8540,ppc8548"))
 125   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
 126    ppc8540_mu_div*13")
 127
 128 ;; CR logical
 129 (define_insn_reservation "ppc8540_cr_logical" 1
 130   (and (eq_attr "type" "cr_logical")
 131        (eq_attr "cpu" "ppc8540,ppc8548"))
 132   "ppc8540_decode,ppc8540_bu,ppc8540_retire")
 133
 134 ;; Mfcr
 135 (define_insn_reservation "ppc8540_mfcr" 1
 136   (and (eq_attr "type" "mfcr")
 137        (eq_attr "cpu" "ppc8540,ppc8548"))
 138   "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
 139
 140 ;; Mtcrf
 141 (define_insn_reservation "ppc8540_mtcrf" 1
 142   (and (eq_attr "type" "mtcr")
 143        (eq_attr "cpu" "ppc8540,ppc8548"))
 144   "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
 145
 146 ;; Mtjmpr
 147 (define_insn_reservation "ppc8540_mtjmpr" 1
 148   (and (eq_attr "type" "mtjmpr,mfjmpr")
 149        (eq_attr "cpu" "ppc8540,ppc8548"))
 150   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
 151
 152 ;; Loads
 153 (define_insn_reservation "ppc8540_load" 3
 154   (and (eq_attr "type" "load,load_l,sync")
 155        (eq_attr "cpu" "ppc8540,ppc8548"))
 156   "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
 157
 158 ;; Stores.
 159 (define_insn_reservation "ppc8540_store" 3
 160   (and (eq_attr "type" "store,store_c")
 161        (eq_attr "cpu" "ppc8540,ppc8548"))
 162   "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
 163
 164 ;; Simple FP
 165 (define_insn_reservation "ppc8540_simple_float" 1
 166   (and (eq_attr "type" "fpsimple")
 167        (eq_attr "cpu" "ppc8540,ppc8548"))
 168   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
 169
 170 ;; FP
 171 (define_insn_reservation "ppc8540_float" 4
 172   (and (eq_attr "type" "fp")
 173        (eq_attr "cpu" "ppc8540,ppc8548"))
 174   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
 175    ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
 176
 177 ;; float divides.  We omit reserving a retire unit and miu_stage3
 178 ;; because of the result automata will be huge.
 179 (define_insn_reservation "ppc8540_float_vector_divide" 29
 180   (and (eq_attr "type" "vecfdiv")
 181        (eq_attr "cpu" "ppc8540,ppc8548"))
 182   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
 183    ppc8540_mu_div*28")
 184
 185 ;; Simple vector
 186 (define_insn_reservation "ppc8540_simple_vector" 1
 187   (and (eq_attr "type" "vecsimple,veclogical,vecmove")
 188        (eq_attr "cpu" "ppc8540,ppc8548"))
 189   "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
 190
 191 ;; Simple vector compare
 192 (define_insn_reservation "ppc8540_simple_vector_compare" 1
 193   (and (eq_attr "type" "veccmpsimple")
 194        (eq_attr "cpu" "ppc8540,ppc8548"))
 195   "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
 196
 197 ;; Vector compare
 198 (define_insn_reservation "ppc8540_vector_compare" 1
 199   (and (eq_attr "type" "veccmp,veccmpfx")
 200        (eq_attr "cpu" "ppc8540,ppc8548"))
 201   "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
 202
 203 ;; evsplatfi evsplati
 204 (define_insn_reservation "ppc8540_vector_perm" 1
 205   (and (eq_attr "type" "vecperm")
 206        (eq_attr "cpu" "ppc8540,ppc8548"))
 207   "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
 208
 209 ;; Vector float
 210 (define_insn_reservation "ppc8540_float_vector" 4
 211   (and (eq_attr "type" "vecfloat")
 212        (eq_attr "cpu" "ppc8540,ppc8548"))
 213   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
 214    ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
 215
 216 ;; Vector divides: Use the average.  We omit reserving a retire unit
 217 ;; because of the result automata will be huge.  We ignore reservation
 218 ;; of miu_stage3 here because we use the average latency time.
 219 (define_insn_reservation "ppc8540_vector_divide" 14
 220   (and (eq_attr "type" "vecdiv")
 221        (eq_attr "cpu" "ppc8540,ppc8548"))
 222   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
 223    ppc8540_mu_div*13")
 224
 225 ;; Complex vector.
 226 (define_insn_reservation "ppc8540_complex_vector" 4
 227   (and (eq_attr "type" "veccomplex")
 228        (eq_attr "cpu" "ppc8540,ppc8548"))
 229   "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
 230    ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
 231
 232 ;; Vector load
 233 (define_insn_reservation "ppc8540_vector_load" 3
 234   (and (eq_attr "type" "vecload")
 235        (eq_attr "cpu" "ppc8540,ppc8548"))
 236   "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
 237
 238 ;; Vector store
 239 (define_insn_reservation "ppc8540_vector_store" 3
 240   (and (eq_attr "type" "vecstore")
 241        (eq_attr "cpu" "ppc8540,ppc8548"))
 242   "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")