gcc/config/rs6000/e500mc64.md

   1 ;; Pipeline description for Freescale PowerPC e500mc64 core.
   2 ;;   Copyright (C) 2009-2014 Free Software Foundation, Inc.
   3 ;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20 ;;
  21 ;; e500mc64 64-bit SU(2), LSU, FPU, BPU
  22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
  23
  24 (define_automaton "e500mc64_most,e500mc64_long,e500mc64_retire")
  25 (define_cpu_unit "e500mc64_decode_0,e500mc64_decode_1" "e500mc64_most")
  26 (define_cpu_unit "e500mc64_issue_0,e500mc64_issue_1"   "e500mc64_most")
  27 (define_cpu_unit "e500mc64_retire_0,e500mc64_retire_1" "e500mc64_retire")
  28
  29 ;; SU.
  30 (define_cpu_unit "e500mc64_su0_stage0,e500mc64_su1_stage0" "e500mc64_most")
  31
  32 ;; MU.
  33 (define_cpu_unit "e500mc64_mu_stage0,e500mc64_mu_stage1" "e500mc64_most")
  34 (define_cpu_unit "e500mc64_mu_stage2,e500mc64_mu_stage3" "e500mc64_most")
  35
  36 ;; Non-pipelined division.
  37 (define_cpu_unit "e500mc64_mu_div" "e500mc64_long")
  38
  39 ;; LSU.
  40 (define_cpu_unit "e500mc64_lsu" "e500mc64_most")
  41
  42 ;; FPU.
  43 (define_cpu_unit "e500mc64_fpu" "e500mc64_most")
  44
  45 ;; Branch unit.
  46 (define_cpu_unit "e500mc64_bu" "e500mc64_most")
  47
  48 ;; The following units are used to make the automata deterministic.
  49 (define_cpu_unit "present_e500mc64_decode_0" "e500mc64_most")
  50 (define_cpu_unit "present_e500mc64_issue_0" "e500mc64_most")
  51 (define_cpu_unit "present_e500mc64_retire_0" "e500mc64_retire")
  52 (define_cpu_unit "present_e500mc64_su0_stage0" "e500mc64_most")
  53
  54 ;; The following sets to make automata deterministic when option ndfa is used.
  55 (presence_set "present_e500mc64_decode_0" "e500mc64_decode_0")
  56 (presence_set "present_e500mc64_issue_0" "e500mc64_issue_0")
  57 (presence_set "present_e500mc64_retire_0" "e500mc64_retire_0")
  58 (presence_set "present_e500mc64_su0_stage0" "e500mc64_su0_stage0")
  59
  60 ;; Some useful abbreviations.
  61 (define_reservation "e500mc64_decode"
  62     "e500mc64_decode_0|e500mc64_decode_1+present_e500mc64_decode_0")
  63 (define_reservation "e500mc64_issue"
  64     "e500mc64_issue_0|e500mc64_issue_1+present_e500mc64_issue_0")
  65 (define_reservation "e500mc64_retire"
  66    "e500mc64_retire_0|e500mc64_retire_1+present_e500mc64_retire_0")
  67 (define_reservation "e500mc64_su_stage0"
  68    "e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0")
  69
  70 ;; Simple SU insns.
  71 (define_insn_reservation "e500mc64_su" 1
  72   (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
  73             (and (eq_attr "type" "shift")
  74                  (eq_attr "dot" "no")
  75                  (eq_attr "var_shift" "no")))
  76        (eq_attr "cpu" "ppce500mc64"))
  77   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
  78
  79 (define_insn_reservation "e500mc64_su2" 2
  80   (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
  81             (and (eq_attr "type" "shift")
  82                  (eq_attr "dot" "yes")
  83                  (eq_attr "var_shift" "no")))
  84        (eq_attr "cpu" "ppce500mc64"))
  85   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
  86
  87 (define_insn_reservation "e500mc64_delayed" 2
  88   (and (eq_attr "type" "shift")
  89        (eq_attr "var_shift" "yes")
  90        (eq_attr "cpu" "ppce500mc64"))
  91   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
  92
  93 (define_insn_reservation "e500mc64_two" 2
  94   (and (eq_attr "type" "two")
  95        (eq_attr "cpu" "ppce500mc64"))
  96   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
  97    e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
  98
  99 (define_insn_reservation "e500mc64_three" 3
 100   (and (eq_attr "type" "three")
 101        (eq_attr "cpu" "ppce500mc64"))
 102   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
 103    e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
 104    e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
 105
 106 ;; Multiply.
 107 (define_insn_reservation "e500mc64_multiply" 4
 108   (and (eq_attr "type" "mul")
 109        (eq_attr "cpu" "ppce500mc64"))
 110   "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
 111    e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
 112
 113 ;; Divide. We use the average latency time here.
 114 (define_insn_reservation "e500mc64_divide" 14
 115   (and (eq_attr "type" "div")
 116        (eq_attr "cpu" "ppce500mc64"))
 117   "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
 118    e500mc64_mu_div*13")
 119
 120 ;; Branch.
 121 (define_insn_reservation "e500mc64_branch" 1
 122   (and (eq_attr "type" "jmpreg,branch,isync")
 123        (eq_attr "cpu" "ppce500mc64"))
 124   "e500mc64_decode,e500mc64_bu,e500mc64_retire")
 125
 126 ;; CR logical.
 127 (define_insn_reservation "e500mc64_cr_logical" 1
 128   (and (eq_attr "type" "cr_logical,delayed_cr")
 129        (eq_attr "cpu" "ppce500mc64"))
 130   "e500mc64_decode,e500mc64_bu,e500mc64_retire")
 131
 132 ;; Mfcr.
 133 (define_insn_reservation "e500mc64_mfcr" 4
 134   (and (eq_attr "type" "mfcr")
 135        (eq_attr "cpu" "ppce500mc64"))
 136   "e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0,e500mc64_su1_stage0*3+e500mc64_retire")
 137
 138 ;; Mtcrf.
 139 (define_insn_reservation "e500mc64_mtcrf" 1
 140   (and (eq_attr "type" "mtcr")
 141        (eq_attr "cpu" "ppce500mc64"))
 142   "e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0+e500mc64_retire")
 143
 144 ;; Mtjmpr.
 145 (define_insn_reservation "e500mc64_mtjmpr" 1
 146   (and (eq_attr "type" "mtjmpr,mfjmpr")
 147        (eq_attr "cpu" "ppce500mc64"))
 148   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
 149
 150 ;; Brinc.
 151 (define_insn_reservation "e500mc64_brinc" 1
 152   (and (eq_attr "type" "brinc")
 153        (eq_attr "cpu" "ppce500mc64"))
 154   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
 155
 156 ;; Loads.
 157 (define_insn_reservation "e500mc64_load" 3
 158   (and (eq_attr "type" "load,load_l,sync")
 159        (eq_attr "cpu" "ppce500mc64"))
 160   "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
 161
 162 (define_insn_reservation "e500mc64_fpload" 4
 163   (and (eq_attr "type" "fpload")
 164        (eq_attr "cpu" "ppce500mc64"))
 165   "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
 166
 167 ;; Stores.
 168 (define_insn_reservation "e500mc64_store" 3
 169   (and (eq_attr "type" "store,store_c")
 170        (eq_attr "cpu" "ppce500mc64"))
 171   "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
 172
 173 (define_insn_reservation "e500mc64_fpstore" 3
 174   (and (eq_attr "type" "fpstore")
 175        (eq_attr "cpu" "ppce500mc64"))
 176   "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
 177
 178 ;; The following ignores the retire unit to avoid a large automata.
 179
 180 ;; FP.
 181 (define_insn_reservation "e500mc64_float" 7
 182   (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
 183        (eq_attr "cpu" "ppce500mc64"))
 184   "e500mc64_decode,e500mc64_issue+e500mc64_fpu")
 185 ; "e500mc64_decode,e500mc64_issue+e500mc64_fpu,nothing*5,e500mc64_retire")
 186
 187 ;; FP divides are not pipelined.
 188 (define_insn_reservation "e500mc64_sdiv" 20
 189   (and (eq_attr "type" "sdiv")
 190        (eq_attr "cpu" "ppce500mc64"))
 191   "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*19")
 192
 193 (define_insn_reservation "e500mc64_ddiv" 35
 194   (and (eq_attr "type" "ddiv")
 195        (eq_attr "cpu" "ppce500mc64"))
 196   "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*34")