1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2024 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have 64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return 1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand 0 "register_operand")
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (!HARD_REGISTER_P (op))
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return 1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand 0 "register_operand")
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (!HARD_REGISTER_P (op))
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand 0 "register_operand")
111 op = SUBREG_REG (op);
116 if (!HARD_REGISTER_P (op))
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return 1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand 0 "register_operand")
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (!HARD_REGISTER_P (op))
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return 1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand 0 "register_operand")
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (!HARD_REGISTER_P (op))
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return 1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand 0 "register_operand")
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (!HARD_REGISTER_P (op))
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return 1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand 0 "register_operand")
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return 1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return 1 if operand is constant -1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return 1 if op is a signed 5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
217 ;; Return 1 if op is an unsigned 1-bit constant integer.
218 (define_predicate "u1bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1")))
222 ;; Return 1 if op is a unsigned 3-bit constant integer.
223 (define_predicate "u3bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
227 ;; Return 1 if op is a unsigned 5-bit constant integer.
228 (define_predicate "u5bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
232 ;; Return 1 if op is a unsigned 6-bit constant integer.
233 (define_predicate "u6bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
237 ;; Return 1 if op is an unsigned 7-bit constant integer.
238 (define_predicate "u7bit_cint_operand"
239 (and (match_code "const_int")
240 (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
242 ;; Return 1 if op is a unsigned 8-bit constant integer.
243 (define_predicate "u8bit_cint_operand"
244 (and (match_code "const_int")
245 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
247 ;; Return 1 if op is a signed 8-bit constant integer.
248 ;; Integer multiplication complete more quickly
249 (define_predicate "s8bit_cint_operand"
250 (and (match_code "const_int")
251 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
253 ;; Return 1 if op is a unsigned 10-bit constant integer.
254 (define_predicate "u10bit_cint_operand"
255 (and (match_code "const_int")
256 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
258 ;; Return 1 if op is a constant integer that can fit in a D field.
259 (define_predicate "short_cint_operand"
260 (and (match_code "const_int")
261 (match_test "satisfies_constraint_I (op)")))
263 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
264 (define_predicate "u_short_cint_operand"
265 (and (match_code "const_int")
266 (match_test "satisfies_constraint_K (op)")))
268 ;; Return 1 if op is a constant integer that is a signed 16-bit constant
269 ;; shifted left 16 bits
270 (define_predicate "upper16_cint_operand"
271 (and (match_code "const_int")
272 (match_test "satisfies_constraint_L (op)")))
274 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
275 (define_predicate "non_short_cint_operand"
276 (and (match_code "const_int")
277 (match_test "(unsigned HOST_WIDE_INT)
278 (INTVAL (op) + 0x8000) >= 0x10000")))
280 ;; Return 1 if op is a 32-bit constant signed integer
281 (define_predicate "s32bit_cint_operand"
282 (and (match_code "const_int")
283 (match_test "(0x80000000 + UINTVAL (op)) >> 32 == 0")))
285 ;; Return 1 if op is a constant 32-bit unsigned
286 (define_predicate "c32bit_cint_operand"
287 (and (match_code "const_int")
288 (match_test "((UINTVAL (op) >> 32) == 0)")))
290 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
291 (define_predicate "exact_log2_cint_operand"
292 (and (match_code "const_int")
293 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
295 ;; Match op = 0 or op = 1.
296 (define_predicate "const_0_to_1_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
300 ;; Match op = -1, op = 0, or op = 1.
301 (define_predicate "const_m1_to_1_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op), -1, 1)")))
306 (define_predicate "const_0_to_3_operand"
307 (and (match_code "const_int")
308 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
310 ;; Match op = 2 or op = 3.
311 (define_predicate "const_2_to_3_operand"
312 (and (match_code "const_int")
313 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
316 (define_predicate "const_0_to_7_operand"
317 (and (match_code "const_int")
318 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
321 (define_predicate "const_0_to_12_operand"
322 (and (match_code "const_int")
323 (match_test "IN_RANGE (INTVAL (op), 0, 12)")))
326 (define_predicate "const_0_to_15_operand"
327 (and (match_code "const_int")
328 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
330 ;; Return 1 if op is a 34-bit constant integer.
331 (define_predicate "cint34_operand"
332 (match_code "const_int")
334 if (!TARGET_PREFIXED)
337 return SIGNED_INTEGER_34BIT_P (INTVAL (op));
340 ;; Return 1 if op is a register that is not special.
341 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
342 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
343 ;; the fact that SFmode is represented as DFmode in the VSX registers.
344 (define_predicate "gpc_reg_operand"
345 (match_operand 0 "register_operand")
349 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
352 op = SUBREG_REG (op);
358 if (!HARD_REGISTER_P (op))
361 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
364 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
367 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
370 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
371 ;; allow floating point or vector registers. Since vector registers are not
372 ;; allowed, we don't have to reject SFmode/SImode subregs.
373 (define_predicate "int_reg_operand"
374 (match_operand 0 "register_operand")
378 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
381 op = SUBREG_REG (op);
387 if (!HARD_REGISTER_P (op))
390 return INT_REGNO_P (REGNO (op));
393 ;; Like int_reg_operand, but don't return true for pseudo registers
394 ;; We don't have to check for SF SUBREGS because pseudo registers
395 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
396 (define_predicate "int_reg_operand_not_pseudo"
397 (match_operand 0 "register_operand")
400 op = SUBREG_REG (op);
405 if (!HARD_REGISTER_P (op))
408 return INT_REGNO_P (REGNO (op));
411 ;; Like int_reg_operand, but only return true for base registers
412 (define_predicate "base_reg_operand"
413 (match_operand 0 "int_reg_operand")
416 op = SUBREG_REG (op);
421 return (REGNO (op) != FIRST_GPR_REGNO);
425 ;; Return true if this is a traditional floating point register
426 (define_predicate "fpr_reg_operand"
427 (match_code "reg,subreg")
432 op = SUBREG_REG (op);
438 if (!HARD_REGISTER_NUM_P (r))
441 return FP_REGNO_P (r);
444 ;; Return 1 if op is a general purpose register that is an even register
445 ;; which suitable for a load/store quad operation
446 ;; Subregs are not allowed here because when they are combine can
447 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
448 ;; think the innermost reg needs reloading, in TImode instead of
449 ;; PTImode. So reload will choose a reg in TImode which has no
450 ;; requirement that the reg be even.
451 (define_predicate "quad_int_reg_operand"
456 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
460 if (!HARD_REGISTER_NUM_P (r))
463 return (INT_REGNO_P (r) && ((r & 1) == 0));
466 ;; Return 1 if op is a register that is a condition register field.
467 (define_predicate "cc_reg_operand"
468 (match_operand 0 "register_operand")
471 op = SUBREG_REG (op);
476 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
479 return CR_REGNO_P (REGNO (op));
482 ;; Return 1 if op is a register that is a condition register field not cr0.
483 (define_predicate "cc_reg_not_cr0_operand"
484 (match_operand 0 "register_operand")
487 op = SUBREG_REG (op);
492 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
495 return CR_REGNO_NOT_CR0_P (REGNO (op));
498 ;; Return 1 if op is a constant integer valid for D field
499 ;; or non-special register.
500 (define_predicate "reg_or_short_operand"
501 (if_then_else (match_code "const_int")
502 (match_operand 0 "short_cint_operand")
503 (match_operand 0 "gpc_reg_operand")))
505 ;; Return 1 if op is a constant integer valid for DS field
506 ;; or non-special register.
507 (define_predicate "reg_or_aligned_short_operand"
508 (if_then_else (match_code "const_int")
509 (and (match_operand 0 "short_cint_operand")
510 (match_test "!(INTVAL (op) & 3)"))
511 (match_operand 0 "gpc_reg_operand")))
513 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
514 ;; or non-special register.
515 (define_predicate "reg_or_u_short_operand"
516 (if_then_else (match_code "const_int")
517 (match_operand 0 "u_short_cint_operand")
518 (match_operand 0 "gpc_reg_operand")))
520 ;; Return 1 if op is any constant integer or a non-special register.
521 (define_predicate "reg_or_cint_operand"
522 (ior (match_code "const_int")
523 (match_operand 0 "gpc_reg_operand")))
525 ;; Return 1 if op is constant zero or a non-special register.
526 (define_predicate "reg_or_zero_operand"
527 (ior (match_operand 0 "zero_constant")
528 (match_operand 0 "gpc_reg_operand")))
530 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
531 (define_predicate "add_cint_operand"
532 (and (match_code "const_int")
533 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
534 + (mode == SImode ? 0x80000000 : 0x80008000))
535 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
537 ;; Return 1 if op is a constant integer valid for addition
538 ;; or non-special register.
539 (define_predicate "reg_or_add_cint_operand"
540 (if_then_else (match_code "const_int")
541 (match_operand 0 "add_cint_operand")
542 (match_operand 0 "gpc_reg_operand")))
544 ;; Return 1 if op is a constant integer valid for subtraction
545 ;; or non-special register.
546 (define_predicate "reg_or_sub_cint_operand"
547 (if_then_else (match_code "const_int")
548 (match_test "(unsigned HOST_WIDE_INT)
549 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
550 < (unsigned HOST_WIDE_INT) 0x100000000ll")
551 (match_operand 0 "gpc_reg_operand")))
553 ;; Return 1 if op is any 32-bit unsigned constant integer
554 ;; or non-special register.
555 (define_predicate "reg_or_logical_cint_operand"
556 (if_then_else (match_code "const_int")
557 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
559 || ((INTVAL (op) & GET_MODE_MASK (mode)
560 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
561 (match_operand 0 "gpc_reg_operand")))
563 ;; Like reg_or_logical_cint_operand, but allow vsx registers
564 (define_predicate "vsx_reg_or_cint_operand"
565 (ior (match_operand 0 "vsx_register_operand")
566 (match_operand 0 "reg_or_logical_cint_operand")))
568 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
569 ;; with no more than one instruction per word.
570 (define_predicate "easy_fp_constant"
571 (match_code "const_double")
573 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
575 /* Consider all constants with -msoft-float to be easy when regs are
576 32-bit and thus can be loaded with a maximum of 2 insns. For
577 64-bit avoid long dependent insn sequences. */
578 if (TARGET_SOFT_FLOAT)
580 if (!TARGET_POWERPC64)
583 int size = GET_MODE_SIZE (mode);
587 int load_from_mem_insns = 2;
589 load_from_mem_insns++;
590 if (TARGET_CMODEL != CMODEL_SMALL)
591 load_from_mem_insns++;
592 if (num_insns_constant (op, mode) <= load_from_mem_insns)
596 /* 0.0D is not all zero bits. */
597 if (DECIMAL_FLOAT_MODE_P (mode))
600 /* The constant 0.0 is easy under VSX. */
601 if (TARGET_VSX && op == CONST0_RTX (mode))
604 /* Constants that can be generated with ISA 3.1 instructions are easy. */
605 vec_const_128bit_type vsx_const;
606 if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const))
608 if (constant_generates_lxvkq (&vsx_const))
611 if (constant_generates_xxspltiw (&vsx_const))
614 if (constant_generates_xxspltidp (&vsx_const))
618 /* Otherwise consider floating point constants hard, so that the
619 constant gets pushed to memory during the early RTL phases. This
620 has the advantage that double precision constants that can be
621 represented in single precision without a loss of precision will
622 use single precision loads. */
626 ;; Return 1 if the operand is a 64-bit floating point scalar constant or a
627 ;; vector constant that can be loaded to a VSX register with one prefixed
628 ;; instruction, such as XXSPLTIDP or XXSPLTIW.
630 ;; In addition regular constants, we also recognize constants formed with the
631 ;; VEC_DUPLICATE insn from scalar constants.
633 ;; We don't handle scalar integer constants here because the assumption is the
634 ;; normal integer constants will be loaded into GPR registers. For the
635 ;; constants that need to be loaded into vector registers, the instructions
636 ;; don't work well with TImode variables assigned a constant. This is because
637 ;; the 64-bit scalar constants are splatted into both halves of the register.
639 (define_predicate "vsx_prefixed_constant"
640 (match_code "const_double,const_vector,vec_duplicate")
642 /* If we can generate the constant with a few Altivec instructions, don't
643 generate a prefixed instruction. */
644 if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode))
647 /* Do we have prefixed instructions and are VSX registers available? Is the
648 constant recognized? */
649 if (!TARGET_PREFIXED || !TARGET_VSX)
652 vec_const_128bit_type vsx_const;
653 if (!vec_const_128bit_to_bytes (op, mode, &vsx_const))
656 if (constant_generates_xxspltiw (&vsx_const))
659 if (constant_generates_xxspltidp (&vsx_const))
665 ;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
666 ;; via the LXVKQ instruction.
668 (define_predicate "easy_vector_constant_ieee128"
669 (match_code "const_vector,const_double")
671 vec_const_128bit_type vsx_const;
673 /* Can we generate the LXVKQ instruction? */
674 if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10
678 return (vec_const_128bit_to_bytes (op, mode, &vsx_const)
679 && constant_generates_lxvkq (&vsx_const) != 0);
682 ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
683 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
685 (define_predicate "xxspltib_constant_split"
686 (match_code "const_vector,vec_duplicate,const_int")
691 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
694 return num_insns > 1;
697 ;; Return true if the operand is a constant that can be loaded with a vspltisw
698 ;; instruction and then a vupkhsw instruction.
700 (define_predicate "vspltisw_vupkhsw_constant_split"
701 (and (match_code "const_vector")
702 (match_test "vspltisw_vupkhsw_constant_p (op, mode)")))
704 ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB
707 (define_predicate "xxspltib_constant_nosplit"
708 (match_code "const_vector,vec_duplicate,const_int")
713 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
716 return num_insns == 1;
719 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
720 ;; vector register without using memory.
721 (define_predicate "easy_vector_constant"
722 (match_code "const_vector")
724 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
729 if (zero_constant (op, mode) || all_ones_constant (op, mode))
732 /* Constants that can be generated with ISA 3.1 instructions are
734 vec_const_128bit_type vsx_const;
735 if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const))
737 if (constant_generates_lxvkq (&vsx_const))
740 if (constant_generates_xxspltiw (&vsx_const))
743 if (constant_generates_xxspltidp (&vsx_const))
748 && xxspltib_constant_p (op, mode, &num_insns, &value))
751 /* V2DI constant within RANGE (-16, 15) can be synthesized with a
752 vspltisw and a vupkhsw. */
753 if (vspltisw_vupkhsw_constant_p (op, mode, &value))
756 return easy_altivec_constant (op, mode);
762 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
763 (define_predicate "easy_vector_constant_add_self"
764 (and (match_code "const_vector")
765 (and (match_test "TARGET_ALTIVEC")
766 (match_test "easy_altivec_constant (op, mode)")))
770 if (mode == V2DImode || mode == V2DFmode)
772 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
773 val = const_vector_elt_as_int (op, elt);
774 val = sext_hwi (val, 8);
775 return EASY_VECTOR_15_ADD_SELF (val);
778 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
779 (define_predicate "easy_vector_constant_msb"
780 (and (match_code "const_vector")
781 (and (match_test "TARGET_ALTIVEC")
782 (match_test "easy_altivec_constant (op, mode)")
783 (match_test "vspltis_shifted (op) == 0")))
786 int elt, sz = easy_altivec_constant (op, mode);
787 machine_mode inner = GET_MODE_INNER (mode);
788 int isz = GET_MODE_SIZE (inner);
789 if (mode == V2DImode || mode == V2DFmode)
791 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
794 if (const_vector_elt_as_int (op, elt) != 0)
796 elt += (BYTES_BIG_ENDIAN ? -1 : 1) * (sz - isz) / isz;
799 inner = smallest_int_mode_for_size (sz * BITS_PER_UNIT);
800 val = const_vector_elt_as_int (op, elt);
801 return EASY_VECTOR_MSB (val, inner);
804 ;; Return true if this is an easy altivec constant that we form
806 (define_predicate "easy_vector_constant_vsldoi"
807 (and (match_code "const_vector")
808 (and (match_test "TARGET_ALTIVEC")
809 (and (match_test "easy_altivec_constant (op, mode)")
810 (match_test "vspltis_shifted (op) != 0")))))
812 ;; Return true if this is a vector constant and each byte in
814 (define_predicate "const_vector_each_byte_same"
815 (match_code "const_vector")
818 if (!const_vec_duplicate_p (op, &elt))
821 machine_mode emode = GET_MODE_INNER (mode);
822 unsigned HOST_WIDE_INT eval;
823 if (CONST_INT_P (elt))
825 else if (CONST_DOUBLE_AS_FLOAT_P (elt))
827 gcc_assert (emode == SFmode || emode == DFmode);
829 real_to_target (l, CONST_DOUBLE_REAL_VALUE (elt), emode);
830 /* real_to_target puts 32-bit pieces in each long. */
831 eval = zext_hwi (l[0], 32);
832 eval |= zext_hwi (l[1], 32) << 32;
837 unsigned int esize = GET_MODE_SIZE (emode);
838 unsigned char byte0 = eval & 0xff;
839 for (unsigned int i = 1; i < esize; i++)
841 eval >>= BITS_PER_UNIT;
842 if (byte0 != (eval & 0xff))
849 ;; Return 1 if operand is a vector int register or is either a vector constant
850 ;; of all 0 bits of a vector constant of all 1 bits.
851 (define_predicate "vector_int_reg_or_same_bit"
852 (match_code "reg,subreg,const_vector")
854 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
857 else if (REG_P (op) || SUBREG_P (op))
858 return vint_operand (op, mode);
861 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
864 ;; Return 1 if operand is 0.0.
865 (define_predicate "zero_fp_constant"
866 (and (match_code "const_double")
867 (match_test "SCALAR_FLOAT_MODE_P (mode)
868 && op == CONST0_RTX (mode)")))
870 ;; Return 1 if the operand is in volatile memory. Note that during the
871 ;; RTL generation phase, memory_operand does not return TRUE for volatile
872 ;; memory references. So this function allows us to recognize volatile
873 ;; references where it's safe.
874 (define_predicate "volatile_mem_operand"
875 (and (match_code "mem")
876 (match_test "MEM_VOLATILE_P (op)")
877 (if_then_else (match_test "reload_completed")
878 (match_operand 0 "memory_operand")
879 (match_test "memory_address_p (mode, XEXP (op, 0))"))))
881 ;; Return 1 if the operand is a volatile or non-volatile memory operand.
882 (define_predicate "any_memory_operand"
883 (ior (match_operand 0 "memory_operand")
884 (match_operand 0 "volatile_mem_operand")))
886 ;; Return 1 if the operand is an offsettable memory operand.
887 (define_predicate "offsettable_mem_operand"
888 (and (match_operand 0 "any_memory_operand")
889 (match_test "offsettable_nonstrict_memref_p (op)")))
891 ;; Return 1 if the operand is a simple offsettable memory operand
892 ;; that does not include pre-increment, post-increment, etc.
893 (define_predicate "simple_offsettable_mem_operand"
894 (match_operand 0 "offsettable_mem_operand")
896 rtx addr = XEXP (op, 0);
898 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
901 if (!CONSTANT_P (XEXP (addr, 1)))
904 return base_reg_operand (XEXP (addr, 0), Pmode);
907 ;; Return 1 if the operand is suitable for load/store quad memory.
908 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
909 (define_predicate "quad_memory_operand"
912 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
915 if (GET_MODE_SIZE (mode) != 16 || MEM_ALIGN (op) < 128)
918 return quad_address_p (XEXP (op, 0), mode, false);
921 ;; Return 1 if the operand is suitable for load/store to vector registers with
922 ;; d-form addressing (register+offset), which was added in ISA 3.0.
923 ;; Unlike quad_memory_operand, we do not have to check for alignment.
924 (define_predicate "vsx_quad_dform_memory_operand"
927 if (!TARGET_P9_VECTOR)
930 return quad_address_p (XEXP (op, 0), mode, false);
933 ;; Return 1 if the operand is an indexed or indirect memory operand.
934 (define_predicate "indexed_or_indirect_operand"
938 if (VECTOR_MEM_ALTIVEC_P (mode)
939 && GET_CODE (op) == AND
940 && CONST_INT_P (XEXP (op, 1))
941 && INTVAL (XEXP (op, 1)) == -16)
944 return indexed_or_indirect_address (op, mode);
947 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
948 ;; moves are supported.
949 (define_predicate "reg_or_indexed_operand"
950 (match_code "mem,reg,subreg")
953 return indexed_or_indirect_operand (op, mode);
954 else if (TARGET_DIRECT_MOVE)
955 return register_operand (op, mode);
960 ;; Return 1 if the operand is an indexed or indirect memory operand with an
961 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
962 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
963 ;; while VSX uses the full address and traps)
964 (define_predicate "altivec_indexed_or_indirect_operand"
968 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
969 && GET_CODE (op) == AND
970 && CONST_INT_P (XEXP (op, 1))
971 && INTVAL (XEXP (op, 1)) == -16)
972 return indexed_or_indirect_address (XEXP (op, 0), mode);
977 ;; Return 1 if the operand is an indexed or indirect address.
978 (define_special_predicate "indexed_or_indirect_address"
979 (and (match_test "REG_P (op)
980 || (GET_CODE (op) == PLUS
981 /* Omit testing REG_P (XEXP (op, 0)). */
982 && REG_P (XEXP (op, 1)))")
983 (match_operand 0 "address_operand")))
985 ;; Return 1 if the operand is an index-form address.
986 (define_special_predicate "indexed_address"
987 (match_test "(GET_CODE (op) == PLUS
988 && REG_P (XEXP (op, 0))
989 && REG_P (XEXP (op, 1)))"))
991 ;; Return 1 if the operand is a MEM with an update-form address. This may
992 ;; also include update-indexed form.
993 (define_special_predicate "update_address_mem"
994 (match_test "(MEM_P (op)
995 && (GET_CODE (XEXP (op, 0)) == PRE_INC
996 || GET_CODE (XEXP (op, 0)) == PRE_DEC
997 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
999 ;; Anything that matches memory_operand but does not update the address.
1000 (define_predicate "non_update_memory_operand"
1003 if (update_address_mem (op, mode))
1005 return memory_operand (op, mode);
1008 ;; Return 1 if the operand is a MEM with an indexed-form address.
1009 (define_special_predicate "indexed_address_mem"
1010 (match_test "(MEM_P (op)
1011 && (indexed_address (XEXP (op, 0), mode)
1012 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
1013 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
1015 ;; Return 1 if the operand is either a non-special register or can be used
1016 ;; as the operand of a `mode' add insn.
1017 (define_predicate "add_operand"
1018 (if_then_else (match_code "const_int")
1019 (match_test "satisfies_constraint_I (op)
1020 || satisfies_constraint_L (op)
1021 || satisfies_constraint_eI (op)")
1022 (match_operand 0 "gpc_reg_operand")))
1024 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
1025 (define_predicate "adde_operand"
1026 (if_then_else (match_code "const_int")
1027 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
1028 (match_operand 0 "gpc_reg_operand")))
1030 ;; Return 1 if OP is a constant but not a valid add_operand.
1031 (define_predicate "non_add_cint_operand"
1032 (and (match_code "const_int")
1033 (not (match_operand 0 "add_operand"))))
1035 ;; Return 1 if the operand is a constant that can be used as the operand
1036 ;; of an AND, OR or XOR.
1037 (define_predicate "logical_const_operand"
1038 (match_code "const_int")
1042 opl = INTVAL (op) & GET_MODE_MASK (mode);
1044 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1045 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1048 ;; Return 1 if the operand is a non-special register or a constant that
1049 ;; can be used as the operand of an AND, OR or XOR.
1050 (define_predicate "logical_operand"
1051 (ior (match_operand 0 "gpc_reg_operand")
1052 (match_operand 0 "logical_const_operand")))
1054 ;; Return 1 if op is a constant that is not a logical operand, but could
1055 ;; be split into one.
1056 (define_predicate "non_logical_cint_operand"
1057 (and (match_code "const_int,const_wide_int")
1058 (and (not (match_operand 0 "logical_operand"))
1059 (match_operand 0 "reg_or_logical_cint_operand"))))
1061 ;; Return 1 if the operand is either a non-special register or a
1062 ;; constant that can be used as the operand of a logical AND.
1063 (define_predicate "and_operand"
1064 (ior (and (match_code "const_int")
1065 (match_test "rs6000_is_valid_and_mask (op, mode)"))
1066 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
1067 (match_operand 0 "gpc_reg_operand")
1068 (match_operand 0 "logical_operand"))))
1070 ;; Return 1 if the operand is either a logical operand or a short cint operand.
1071 (define_predicate "scc_eq_operand"
1072 (ior (match_operand 0 "logical_operand")
1073 (match_operand 0 "short_cint_operand")))
1075 ;; Return 1 if the operand is a general non-special register or memory operand.
1076 (define_predicate "reg_or_mem_operand"
1077 (ior (match_operand 0 "gpc_reg_operand")
1078 (match_operand 0 "any_memory_operand")
1079 (and (match_code "mem")
1080 (match_test "macho_lo_sum_memory_operand (op, mode)"))))
1082 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
1083 (define_predicate "zero_reg_mem_operand"
1084 (ior (and (match_test "TARGET_VSX")
1085 (match_operand 0 "zero_fp_constant"))
1086 (match_operand 0 "reg_or_mem_operand")))
1088 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
1089 ;; data types inside of a vector that scalar instructions operate on
1090 (define_predicate "vsx_scalar_64bit"
1091 (match_code "const_int")
1093 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
1096 ;; Return 1 if the operand is a general register or memory operand without
1097 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
1099 (define_predicate "lwa_operand"
1100 (match_code "reg,subreg,mem")
1102 rtx inner, addr, offset;
1105 if (reload_completed && SUBREG_P (inner))
1106 inner = SUBREG_REG (inner);
1108 if (gpc_reg_operand (inner, mode))
1110 if (!any_memory_operand (inner, mode))
1113 addr = XEXP (inner, 0);
1115 /* The LWA instruction uses the DS-form instruction format which requires
1116 that the bottom two bits of the offset must be 0. The prefixed PLWA does
1117 not have this restriction. While the actual load from memory is 32-bits,
1118 we pass in DImode here to test for using a DS instruction. */
1119 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
1122 if (GET_CODE (addr) == PRE_INC
1123 || GET_CODE (addr) == PRE_DEC
1124 || (GET_CODE (addr) == PRE_MODIFY
1125 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1127 if (GET_CODE (addr) == LO_SUM
1128 && REG_P (XEXP (addr, 0))
1129 && GET_CODE (XEXP (addr, 1)) == CONST)
1130 addr = XEXP (XEXP (addr, 1), 0);
1131 if (GET_CODE (addr) != PLUS)
1133 offset = XEXP (addr, 1);
1134 if (!CONST_INT_P (offset))
1136 return INTVAL (offset) % 4 == 0;
1139 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1140 (define_predicate "symbol_ref_operand"
1141 (and (match_code "symbol_ref")
1142 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1143 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1145 ;; Return 1 if op is an operand that can be loaded via the GOT.
1146 ;; or non-special register field no cr0
1147 (define_predicate "got_operand"
1148 (match_code "symbol_ref,const,label_ref"))
1150 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1151 ;; excluding labels involving addition.
1152 (define_predicate "got_no_const_operand"
1153 (match_code "symbol_ref,label_ref"))
1155 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1156 (define_predicate "rs6000_tls_symbol_ref"
1157 (and (match_code "symbol_ref")
1158 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1160 ;; Return 1 for the CONST_INT or UNSPEC second CALL operand.
1161 ;; Prevents unwanted substitution of the unspec got_reg arg.
1162 (define_predicate "unspec_tls"
1163 (match_code "const_int,unspec")
1165 if (CONST_INT_P (op))
1167 if (XINT (op, 1) == UNSPEC_TLSGD)
1168 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx;
1169 if (XINT (op, 1) == UNSPEC_TLSLD)
1170 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx;
1174 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1175 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1176 (define_predicate "call_operand"
1177 (if_then_else (match_code "reg")
1178 (match_test "REGNO (op) == LR_REGNO
1179 || REGNO (op) == CTR_REGNO
1180 || !HARD_REGISTER_P (op)")
1181 (match_code "symbol_ref")))
1183 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1184 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
1185 (define_predicate "indirect_call_operand"
1186 (match_code "reg,unspec")
1189 return (REGNO (op) == LR_REGNO
1190 || REGNO (op) == CTR_REGNO);
1191 if (GET_CODE (op) == UNSPEC)
1193 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1195 op = XVECEXP (op, 0, 0);
1196 return REG_P (op) && REGNO (op) == CTR_REGNO;
1201 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1203 (define_predicate "current_file_function_operand"
1204 (and (match_code "symbol_ref")
1205 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1206 && (SYMBOL_REF_LOCAL_P (op)
1207 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1208 && !decl_replaceable_p (current_function_decl,
1209 opt_for_fn (current_function_decl,
1210 flag_semantic_interposition))))
1211 && !((DEFAULT_ABI == ABI_AIX
1212 || DEFAULT_ABI == ABI_ELFv2)
1213 && (SYMBOL_REF_EXTERNAL_P (op)
1214 || SYMBOL_REF_WEAK (op)))
1215 && !(DEFAULT_ABI == ABI_ELFv2
1216 && SYMBOL_REF_DECL (op) != NULL
1217 && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL
1218 && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op))
1219 != rs6000_pcrel_p ()))")))
1221 ;; Return 1 if this operand is a valid input for a move insn.
1222 (define_predicate "input_operand"
1223 (match_code "symbol_ref,const,reg,subreg,mem,
1224 const_double,const_wide_int,const_vector,const_int")
1226 /* Memory is always valid. */
1227 if (any_memory_operand (op, mode))
1230 /* For floating-point, easy constants are valid. */
1231 if (SCALAR_FLOAT_MODE_P (mode)
1232 && easy_fp_constant (op, mode))
1235 /* Allow any integer constant. */
1236 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op))
1239 /* Allow easy vector constants. */
1240 if (GET_CODE (op) == CONST_VECTOR
1241 && easy_vector_constant (op, mode))
1244 /* For floating-point or multi-word mode, the only remaining valid type
1246 if (SCALAR_FLOAT_MODE_P (mode)
1247 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1248 return register_operand (op, mode);
1250 /* We don't allow moving the carry bit around. */
1251 if (ca_operand (op, mode))
1254 /* The only cases left are integral modes one word or smaller (we
1255 do not get called for MODE_CC values). These can be in any
1257 if (register_operand (op, mode))
1260 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1262 if (DEFAULT_ABI == ABI_V4
1263 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST)
1264 && small_data_operand (op, Pmode))
1270 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1271 (define_predicate "splat_input_operand"
1272 (match_code "reg,subreg,mem")
1278 else if (mode == DImode)
1280 else if (mode == SImode && TARGET_P9_VECTOR)
1282 else if (mode == SFmode && TARGET_P9_VECTOR)
1289 rtx addr = XEXP (op, 0);
1291 if (! volatile_ok && MEM_VOLATILE_P (op))
1294 if (lra_in_progress || reload_completed)
1295 return indexed_or_indirect_address (addr, vmode);
1297 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1299 return gpc_reg_operand (op, mode);
1302 ;; Return 1 if this operand is valid for a MMA assemble accumulator insn.
1303 (define_special_predicate "mma_assemble_input_operand"
1304 (match_test "(mode == V16QImode
1305 && (vsx_register_operand (op, mode)
1307 && (indexed_or_indirect_address (XEXP (op, 0), mode)
1308 || quad_address_p (XEXP (op, 0), mode, false)))))"))
1310 ;; Return 1 if this operand is valid for an MMA disassemble insn.
1311 (define_predicate "mma_disassemble_output_operand"
1312 (match_code "reg,subreg,mem")
1316 rtx addr = XEXP (op, 0);
1317 return indexed_or_indirect_address (addr, mode)
1318 || quad_address_p (addr, mode, false);
1322 op = SUBREG_REG (op);
1324 return vsx_register_operand (op, mode);
1327 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1328 (define_predicate "rotate_mask_operator"
1329 (match_code "rotate,ashift,lshiftrt"))
1331 ;; Return true if operand is boolean operator.
1332 (define_predicate "boolean_operator"
1333 (match_code "and,ior,xor"))
1335 ;; Return true if operand is OR-form of boolean operator.
1336 (define_predicate "boolean_or_operator"
1337 (match_code "ior,xor"))
1339 ;; Return true if operand is an equality operator.
1340 (define_special_predicate "equality_operator"
1341 (match_code "eq,ne"))
1343 ;; Return 1 if OP is a comparison operation that is valid for a branch
1344 ;; instruction. We check the opcode against the mode of the CC value.
1345 ;; validate_condition_mode is an assertion.
1346 (define_predicate "branch_comparison_operator"
1347 (and (match_operand 0 "comparison_operator")
1348 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1349 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1350 (if_then_else (match_test "flag_finite_math_only")
1351 (match_code "lt,le,gt,ge,eq,ne,unordered,ordered")
1352 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered"))
1353 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne"))
1354 (match_test "validate_condition_mode (GET_CODE (op),
1355 GET_MODE (XEXP (op, 0))),
1358 ;; Return 1 if OP is a comparison that needs an extra instruction to do (a
1359 ;; crlogical or an extra branch).
1360 (define_predicate "extra_insn_branch_comparison_operator"
1361 (and (match_operand 0 "comparison_operator")
1362 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1363 (match_code "ltgt,le,ge,unlt,ungt,uneq")
1364 (match_test "validate_condition_mode (GET_CODE (op),
1365 GET_MODE (XEXP (op, 0))),
1368 ;; Return 1 if OP is an unsigned comparison operator.
1369 (define_predicate "unsigned_comparison_operator"
1370 (match_code "ltu,gtu,leu,geu"))
1372 ;; Return 1 if OP is a signed comparison operator.
1373 (define_predicate "signed_comparison_operator"
1374 (match_code "lt,gt,le,ge"))
1376 ;; Return 1 if OP is a signed comparison or an equality operator.
1377 (define_predicate "signed_or_equality_comparison_operator"
1378 (ior (match_operand 0 "equality_operator")
1379 (match_operand 0 "signed_comparison_operator")))
1381 ;; Return 1 if OP is an unsigned comparison or an equality operator.
1382 (define_predicate "unsigned_or_equality_comparison_operator"
1383 (ior (match_operand 0 "equality_operator")
1384 (match_operand 0 "unsigned_comparison_operator")))
1386 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1387 ;; it must be a positive comparison.
1388 (define_predicate "scc_comparison_operator"
1389 (and (match_operand 0 "branch_comparison_operator")
1390 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1392 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1394 (define_predicate "scc_rev_comparison_operator"
1395 (and (match_operand 0 "branch_comparison_operator")
1396 (match_code "ne,le,ge,leu,geu,ordered")))
1398 ;; Return 1 if OP is a comparison operator suitable for floating point
1399 ;; vector/scalar comparisons that generate a -1/0 mask.
1400 (define_predicate "fpmask_comparison_operator"
1401 (match_code "eq,gt,ge"))
1403 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1404 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1405 ;; fpmask_comparison_operator).
1406 (define_predicate "invert_fpmask_comparison_operator"
1407 (match_code "ne,unlt,unle"))
1409 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1410 ;; comparisons that generate a -1/0 mask.
1411 (define_predicate "vecint_comparison_operator"
1412 (match_code "eq,gt,gtu"))
1414 ;; Return 1 if OP is a comparison operation that is valid for a branch
1415 ;; insn, which is true if the corresponding bit in the CC register is set.
1416 (define_predicate "branch_positive_comparison_operator"
1417 (and (match_operand 0 "branch_comparison_operator")
1418 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1420 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1422 (define_predicate "save_world_operation"
1423 (match_code "parallel")
1428 int count = XVECLEN (op, 0);
1434 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1435 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1438 for (i=1; i <= 18; i++)
1440 elt = XVECEXP (op, 0, index++);
1441 if (GET_CODE (elt) != SET
1442 || !MEM_P (SET_DEST (elt))
1443 || !memory_operand (SET_DEST (elt), DFmode)
1444 || !REG_P (SET_SRC (elt))
1445 || GET_MODE (SET_SRC (elt)) != DFmode)
1449 for (i=1; i <= 12; i++)
1451 elt = XVECEXP (op, 0, index++);
1452 if (GET_CODE (elt) != SET
1453 || !MEM_P (SET_DEST (elt))
1454 || !REG_P (SET_SRC (elt))
1455 || GET_MODE (SET_SRC (elt)) != V4SImode)
1459 for (i=1; i <= 19; i++)
1461 elt = XVECEXP (op, 0, index++);
1462 if (GET_CODE (elt) != SET
1463 || !MEM_P (SET_DEST (elt))
1464 || !memory_operand (SET_DEST (elt), Pmode)
1465 || !REG_P (SET_SRC (elt))
1466 || GET_MODE (SET_SRC (elt)) != Pmode)
1470 elt = XVECEXP (op, 0, index++);
1471 if (GET_CODE (elt) != SET
1472 || !MEM_P (SET_DEST (elt))
1473 || !memory_operand (SET_DEST (elt), Pmode)
1474 || !REG_P (SET_SRC (elt))
1475 || REGNO (SET_SRC (elt)) != CR2_REGNO
1476 || GET_MODE (SET_SRC (elt)) != Pmode)
1479 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1480 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1485 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1487 (define_predicate "restore_world_operation"
1488 (match_code "parallel")
1493 int count = XVECLEN (op, 0);
1499 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1500 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1501 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1504 elt = XVECEXP (op, 0, index++);
1505 if (GET_CODE (elt) != SET
1506 || !MEM_P (SET_SRC (elt))
1507 || !memory_operand (SET_SRC (elt), Pmode)
1508 || !REG_P (SET_DEST (elt))
1509 || REGNO (SET_DEST (elt)) != CR2_REGNO
1510 || GET_MODE (SET_DEST (elt)) != Pmode)
1513 for (i=1; i <= 19; i++)
1515 elt = XVECEXP (op, 0, index++);
1516 if (GET_CODE (elt) != SET
1517 || !MEM_P (SET_SRC (elt))
1518 || !memory_operand (SET_SRC (elt), Pmode)
1519 || !REG_P (SET_DEST (elt))
1520 || GET_MODE (SET_DEST (elt)) != Pmode)
1524 for (i=1; i <= 12; i++)
1526 elt = XVECEXP (op, 0, index++);
1527 if (GET_CODE (elt) != SET
1528 || !MEM_P (SET_SRC (elt))
1529 || !REG_P (SET_DEST (elt))
1530 || GET_MODE (SET_DEST (elt)) != V4SImode)
1534 for (i=1; i <= 18; i++)
1536 elt = XVECEXP (op, 0, index++);
1537 if (GET_CODE (elt) != SET
1538 || !MEM_P (SET_SRC (elt))
1539 || !memory_operand (SET_SRC (elt), DFmode)
1540 || !REG_P (SET_DEST (elt))
1541 || GET_MODE (SET_DEST (elt)) != DFmode)
1545 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1546 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1547 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1548 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1549 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1554 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1555 (define_predicate "vrsave_operation"
1556 (match_code "parallel")
1558 int count = XVECLEN (op, 0);
1559 unsigned int dest_regno, src_regno;
1563 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1564 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1565 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1566 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1569 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1570 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1572 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1575 for (i = 1; i < count; i++)
1577 rtx elt = XVECEXP (op, 0, i);
1579 if (GET_CODE (elt) != CLOBBER
1580 && GET_CODE (elt) != SET)
1587 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1588 (define_predicate "mfcr_operation"
1589 (match_code "parallel")
1591 int count = XVECLEN (op, 0);
1594 /* Perform a quick check so we don't blow up below. */
1596 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1597 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1598 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1601 for (i = 0; i < count; i++)
1603 rtx exp = XVECEXP (op, 0, i);
1608 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1610 if (!REG_P (src_reg)
1611 || GET_MODE (src_reg) != CCmode
1612 || ! CR_REGNO_P (REGNO (src_reg)))
1615 if (GET_CODE (exp) != SET
1616 || !REG_P (SET_DEST (exp))
1617 || GET_MODE (SET_DEST (exp)) != SImode
1618 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1620 unspec = SET_SRC (exp);
1621 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1623 if (GET_CODE (unspec) != UNSPEC
1624 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1625 || XVECLEN (unspec, 0) != 2
1626 || XVECEXP (unspec, 0, 0) != src_reg
1627 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1628 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1634 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1635 (define_predicate "mtcrf_operation"
1636 (match_code "parallel")
1638 int count = XVECLEN (op, 0);
1642 /* Perform a quick check so we don't blow up below. */
1644 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1645 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1646 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1648 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1650 if (!REG_P (src_reg)
1651 || GET_MODE (src_reg) != SImode
1652 || ! INT_REGNO_P (REGNO (src_reg)))
1655 for (i = 0; i < count; i++)
1657 rtx exp = XVECEXP (op, 0, i);
1661 if (GET_CODE (exp) != SET
1662 || !REG_P (SET_DEST (exp))
1663 || GET_MODE (SET_DEST (exp)) != CCmode
1664 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1666 unspec = SET_SRC (exp);
1667 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1669 if (GET_CODE (unspec) != UNSPEC
1670 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1671 || XVECLEN (unspec, 0) != 2
1672 || XVECEXP (unspec, 0, 0) != src_reg
1673 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1674 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1680 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1681 (define_predicate "crsave_operation"
1682 (match_code "parallel")
1684 int count = XVECLEN (op, 0);
1687 for (i = 1; i < count; i++)
1689 rtx exp = XVECEXP (op, 0, i);
1691 if (GET_CODE (exp) != USE
1692 || !REG_P (XEXP (exp, 0))
1693 || GET_MODE (XEXP (exp, 0)) != CCmode
1694 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1700 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1701 (define_predicate "lmw_operation"
1702 (match_code "parallel")
1704 int count = XVECLEN (op, 0);
1705 unsigned int dest_regno;
1707 unsigned int base_regno;
1708 HOST_WIDE_INT offset;
1711 /* Perform a quick check so we don't blow up below. */
1713 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1714 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1715 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
1718 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1719 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1722 || count != 32 - (int) dest_regno)
1725 if (legitimate_indirect_address_p (src_addr, 0))
1728 base_regno = REGNO (src_addr);
1729 if (base_regno == 0)
1732 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1734 offset = INTVAL (XEXP (src_addr, 1));
1735 base_regno = REGNO (XEXP (src_addr, 0));
1740 for (i = 0; i < count; i++)
1742 rtx elt = XVECEXP (op, 0, i);
1745 HOST_WIDE_INT newoffset;
1747 if (GET_CODE (elt) != SET
1748 || !REG_P (SET_DEST (elt))
1749 || GET_MODE (SET_DEST (elt)) != SImode
1750 || REGNO (SET_DEST (elt)) != dest_regno + i
1751 || !MEM_P (SET_SRC (elt))
1752 || GET_MODE (SET_SRC (elt)) != SImode)
1754 newaddr = XEXP (SET_SRC (elt), 0);
1755 if (legitimate_indirect_address_p (newaddr, 0))
1760 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1762 addr_reg = XEXP (newaddr, 0);
1763 newoffset = INTVAL (XEXP (newaddr, 1));
1767 if (REGNO (addr_reg) != base_regno
1768 || newoffset != offset + 4 * i)
1775 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1776 (define_predicate "stmw_operation"
1777 (match_code "parallel")
1779 int count = XVECLEN (op, 0);
1780 unsigned int src_regno;
1782 unsigned int base_regno;
1783 HOST_WIDE_INT offset;
1786 /* Perform a quick check so we don't blow up below. */
1788 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1789 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
1790 || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
1793 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1794 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1797 || count != 32 - (int) src_regno)
1800 if (legitimate_indirect_address_p (dest_addr, 0))
1803 base_regno = REGNO (dest_addr);
1804 if (base_regno == 0)
1807 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1809 offset = INTVAL (XEXP (dest_addr, 1));
1810 base_regno = REGNO (XEXP (dest_addr, 0));
1815 for (i = 0; i < count; i++)
1817 rtx elt = XVECEXP (op, 0, i);
1820 HOST_WIDE_INT newoffset;
1822 if (GET_CODE (elt) != SET
1823 || !REG_P (SET_SRC (elt))
1824 || GET_MODE (SET_SRC (elt)) != SImode
1825 || REGNO (SET_SRC (elt)) != src_regno + i
1826 || !MEM_P (SET_DEST (elt))
1827 || GET_MODE (SET_DEST (elt)) != SImode)
1829 newaddr = XEXP (SET_DEST (elt), 0);
1830 if (legitimate_indirect_address_p (newaddr, 0))
1835 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1837 addr_reg = XEXP (newaddr, 0);
1838 newoffset = INTVAL (XEXP (newaddr, 1));
1842 if (REGNO (addr_reg) != base_regno
1843 || newoffset != offset + 4 * i)
1850 ;; Return 1 if OP is a stack tie operand.
1851 (define_predicate "tie_operand"
1852 (match_code "parallel")
1854 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1855 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0))
1856 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1857 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1860 ;; Match a small code model toc reference (or medium and large
1861 ;; model toc references before reload).
1862 (define_predicate "small_toc_ref"
1863 (match_code "unspec,plus")
1865 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1868 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1872 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1873 ;; GPR registers on power8.
1874 (define_predicate "fusion_gpr_addis"
1875 (match_code "const_int,high,plus")
1877 HOST_WIDE_INT value;
1880 if (GET_CODE (op) == HIGH)
1883 if (CONST_INT_P (op))
1886 else if (GET_CODE (op) == PLUS
1887 && base_reg_operand (XEXP (op, 0), Pmode)
1888 && CONST_INT_P (XEXP (op, 1)))
1889 int_const = XEXP (op, 1);
1894 value = INTVAL (int_const);
1895 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1898 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1901 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1903 return (IN_RANGE (value >> 16, -16, 15));
1906 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1907 ;; and loads to GPR registers on power8.
1908 (define_predicate "fusion_gpr_mem_load"
1909 (match_code "mem,sign_extend,zero_extend")
1911 rtx addr, base, offset;
1913 /* Handle sign/zero extend. */
1914 if (GET_CODE (op) == ZERO_EXTEND
1915 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1918 mode = GET_MODE (op);
1932 if (!TARGET_POWERPC64)
1936 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1942 addr = XEXP (op, 0);
1943 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1946 base = XEXP (addr, 0);
1947 if (!base_reg_operand (base, GET_MODE (base)))
1950 offset = XEXP (addr, 1);
1952 if (GET_CODE (addr) == PLUS)
1953 return satisfies_constraint_I (offset);
1955 else if (GET_CODE (addr) == LO_SUM)
1957 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1958 return small_toc_ref (offset, GET_MODE (offset));
1960 else if (TARGET_ELF && !TARGET_POWERPC64)
1961 return CONSTANT_P (offset);
1967 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1968 ;; memory field with both the addis and the memory offset. Sign extension
1969 ;; is not handled here, since lha and lwa are not fused.
1970 (define_predicate "fusion_addis_mem_combo_load"
1971 (match_code "mem,zero_extend")
1973 rtx addr, base, offset;
1975 /* Handle zero extend. */
1976 if (GET_CODE (op) == ZERO_EXTEND)
1979 mode = GET_MODE (op);
1992 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1993 separate instructions. */
1995 if (!TARGET_POWERPC64)
1999 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
2005 addr = XEXP (op, 0);
2006 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
2009 base = XEXP (addr, 0);
2010 if (!fusion_gpr_addis (base, GET_MODE (base)))
2013 offset = XEXP (addr, 1);
2014 if (GET_CODE (addr) == PLUS)
2015 return satisfies_constraint_I (offset);
2017 else if (GET_CODE (addr) == LO_SUM)
2019 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
2020 return small_toc_ref (offset, GET_MODE (offset));
2022 else if (TARGET_ELF && !TARGET_POWERPC64)
2023 return CONSTANT_P (offset);
2030 ;; Return true if the operand is a PC-relative address of a local symbol or a
2031 ;; label that can be used directly in a memory operation.
2032 (define_predicate "pcrel_local_address"
2033 (match_code "label_ref,symbol_ref,const")
2035 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
2036 return iform == INSN_FORM_PCREL_LOCAL;
2039 ;; Return true if the operand is a PC-relative external symbol whose address
2040 ;; can be loaded into a register.
2041 (define_predicate "pcrel_external_address"
2042 (match_code "symbol_ref,const")
2044 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
2045 return iform == INSN_FORM_PCREL_EXTERNAL;
2048 ;; Return true if the address is PC-relative and the symbol is either local or
2050 (define_predicate "pcrel_local_or_external_address"
2051 (ior (match_operand 0 "pcrel_local_address")
2052 (match_operand 0 "pcrel_external_address")))
2054 ;; Return true if the operand is a memory address that uses a prefixed address.
2055 (define_predicate "prefixed_memory"
2058 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT);
2061 ;; Return true if the operand is a valid memory operand with a D-form
2062 ;; address that could be merged with the load of a PC-relative external address
2063 ;; with the PCREL_OPT optimization. We don't check here whether or not the
2064 ;; offset needs to be used in a DS-FORM (bottom 2 bits 0) or DQ-FORM (bottom 4
2065 ;; bits 0) instruction.
2066 (define_predicate "d_form_memory"
2069 if (!memory_operand (op, mode))
2072 rtx addr = XEXP (op, 0);
2076 if (SUBREG_P (addr) && REG_P (SUBREG_REG (addr)))
2079 return !indexed_address (addr, mode);
2082 ;; Return 1 if this operand is valid as the index for vec_set.
2083 (define_predicate "vec_set_index_operand"
2084 (if_then_else (match_test "TARGET_VSX")
2085 (match_operand 0 "reg_or_cint_operand")
2086 (match_operand 0 "const_int_operand")))
2088 ;; Return true if the operand is a valid Mach-O pic address.
2090 (define_predicate "macho_pic_address"
2091 (match_code "const,unspec")
2093 if (GET_CODE (op) == CONST)
2096 if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_MACHOPIC_OFFSET)
2097 return CONSTANT_P (XVECEXP (op, 0, 0));
2102 (define_predicate "lowpart_subreg_operator"
2103 (and (match_code "subreg")
2104 (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op)))
2105 == SUBREG_BYTE (op)")))