gcc/config/rs6000/rs6000-cpus.def

   1 /* IBM RS/6000 CPU names..
   2    Copyright (C) 1991-2014 Free Software Foundation, Inc.
   3    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* ISA masks.  */
  22 #ifndef ISA_2_1_MASKS
  23 #define ISA_2_1_MASKS           OPTION_MASK_MFCRF
  24 #define ISA_2_2_MASKS           (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
  25 #define ISA_2_4_MASKS           (ISA_2_2_MASKS | OPTION_MASK_FPRND)
  26
  27   /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
  28      ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
  29      fre, fsqrt, etc. were no longer documented as optional.  Group masks by
  30      server and embedded. */
  31 #define ISA_2_5_MASKS_EMBEDDED  (ISA_2_4_MASKS                          \
  32                                  | OPTION_MASK_CMPB                     \
  33                                  | OPTION_MASK_RECIP_PRECISION          \
  34                                  | OPTION_MASK_PPC_GFXOPT               \
  35                                  | OPTION_MASK_PPC_GPOPT)
  36
  37 #define ISA_2_5_MASKS_SERVER    (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
  38
  39   /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
  40      altivec is a win so enable it.  */
  41   /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
  42      PR 58587 is fixed.  */
  43 #define ISA_2_6_MASKS_EMBEDDED  (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
  44 #define ISA_2_6_MASKS_SERVER    (ISA_2_5_MASKS_SERVER                   \
  45                                  | OPTION_MASK_POPCNTD                  \
  46                                  | OPTION_MASK_ALTIVEC                  \
  47                                  | OPTION_MASK_VSX                      \
  48                                  | OPTION_MASK_UPPER_REGS_DF)
  49
  50 /* For now, don't provide an embedded version of ISA 2.07.  */
  51 #define ISA_2_7_MASKS_SERVER    (ISA_2_6_MASKS_SERVER                   \
  52                                  | OPTION_MASK_P8_FUSION                \
  53                                  | OPTION_MASK_P8_VECTOR                \
  54                                  | OPTION_MASK_CRYPTO                   \
  55                                  | OPTION_MASK_DIRECT_MOVE              \
  56                                  | OPTION_MASK_HTM                      \
  57                                  | OPTION_MASK_QUAD_MEMORY              \
  58                                  | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
  59                                  | OPTION_MASK_UPPER_REGS_SF)
  60
  61 #define POWERPC_7400_MASK       (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
  62
  63 /* Deal with ports that do not have -mstrict-align.  */
  64 #ifdef OPTION_MASK_STRICT_ALIGN
  65 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
  66 #else
  67 #define OPTION_MASK_STRICT_ALIGN 0
  68 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
  69 #ifndef MASK_STRICT_ALIGN
  70 #define MASK_STRICT_ALIGN 0
  71 #endif
  72 #endif
  73
  74 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
  75 #define POWERPC_MASKS           (OPTION_MASK_ALTIVEC                    \
  76                                  | OPTION_MASK_CMPB                     \
  77                                  | OPTION_MASK_CRYPTO                   \
  78                                  | OPTION_MASK_DFP                      \
  79                                  | OPTION_MASK_DIRECT_MOVE              \
  80                                  | OPTION_MASK_DLMZB                    \
  81                                  | OPTION_MASK_FPRND                    \
  82                                  | OPTION_MASK_HTM                      \
  83                                  | OPTION_MASK_ISEL                     \
  84                                  | OPTION_MASK_MFCRF                    \
  85                                  | OPTION_MASK_MFPGPR                   \
  86                                  | OPTION_MASK_MULHW                    \
  87                                  | OPTION_MASK_NO_UPDATE                \
  88                                  | OPTION_MASK_P8_FUSION                \
  89                                  | OPTION_MASK_P8_VECTOR                \
  90                                  | OPTION_MASK_POPCNTB                  \
  91                                  | OPTION_MASK_POPCNTD                  \
  92                                  | OPTION_MASK_POWERPC64                \
  93                                  | OPTION_MASK_PPC_GFXOPT               \
  94                                  | OPTION_MASK_PPC_GPOPT                \
  95                                  | OPTION_MASK_QUAD_MEMORY              \
  96                                  | OPTION_MASK_RECIP_PRECISION          \
  97                                  | OPTION_MASK_SOFT_FLOAT               \
  98                                  | OPTION_MASK_STRICT_ALIGN_OPTIONAL    \
  99                                  | OPTION_MASK_UPPER_REGS_DF            \
 100                                  | OPTION_MASK_UPPER_REGS_SF            \
 101                                  | OPTION_MASK_VSX                      \
 102                                  | OPTION_MASK_VSX_TIMODE)
 103
 104 #endif
 105
 106 /* This table occasionally claims that a processor does not support a
 107    particular feature even though it does, but the feature is slower than the
 108    alternative.  Thus, it shouldn't be relied on as a complete description of
 109    the processor's support.
 110
 111    Please keep this list in order, and don't forget to update the documentation
 112    in invoke.texi when adding a new processor or flag.
 113
 114    Before including this file, define a macro:
 115
 116    RS6000_CPU (NAME, CPU, FLAGS)
 117
 118    where the arguments are the fields of struct rs6000_ptt.  */
 119
 120 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
 121 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
 122 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 123 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
 124 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 125 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 126 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 127 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 128 RS6000_CPU ("476", PROCESSOR_PPC476,
 129             MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
 130             | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 131 RS6000_CPU ("476fp", PROCESSOR_PPC476,
 132             MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 133             | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 134 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 135 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
 136 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 137 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 138 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 139 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
 140 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
 141 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
 142 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 143 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 144 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
 145 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
 146 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 147 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 148 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 149 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 150 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
 151 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
 152 RS6000_CPU ("a2", PROCESSOR_PPCA2,
 153             MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
 154             | MASK_NO_UPDATE)
 155 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
 156 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
 157 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
 158 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
 159             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 160 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
 161             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 162 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
 163             | MASK_MFCRF | MASK_ISEL)
 164 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 165 RS6000_CPU ("970", PROCESSOR_POWER4,
 166             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 167 RS6000_CPU ("cell", PROCESSOR_CELL,
 168             POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 169 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
 170 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 171 RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
 172 RS6000_CPU ("G5", PROCESSOR_POWER4,
 173             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 174 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
 175 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 176 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
 177             | MASK_PPC_GFXOPT | MASK_MFCRF)
 178 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 179             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
 180 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 181             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
 182 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 183             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 184             | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
 185 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 186             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 187             | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
 188 RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
 189             POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
 190             | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
 191             | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF)
 192 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 193 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 194 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
 195 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)