gcc/config/rs6000/rs6000-cpus.def

   1 /* IBM RS/6000 CPU names..
   2    Copyright (C) 1991-2017 Free Software Foundation, Inc.
   3    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* ISA masks.  */
  22 #ifndef ISA_2_1_MASKS
  23 #define ISA_2_1_MASKS           OPTION_MASK_MFCRF
  24 #define ISA_2_2_MASKS           (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
  25 #define ISA_2_4_MASKS           (ISA_2_2_MASKS | OPTION_MASK_FPRND)
  26
  27   /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
  28      ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
  29      fre, fsqrt, etc. were no longer documented as optional.  Group masks by
  30      server and embedded. */
  31 #define ISA_2_5_MASKS_EMBEDDED  (ISA_2_4_MASKS                          \
  32                                  | OPTION_MASK_CMPB                     \
  33                                  | OPTION_MASK_RECIP_PRECISION          \
  34                                  | OPTION_MASK_PPC_GFXOPT               \
  35                                  | OPTION_MASK_PPC_GPOPT)
  36
  37 #define ISA_2_5_MASKS_SERVER    (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
  38
  39   /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
  40      altivec is a win so enable it.  */
  41   /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
  42      PR 58587 is fixed.  */
  43 #define ISA_2_6_MASKS_EMBEDDED  (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
  44 #define ISA_2_6_MASKS_SERVER    (ISA_2_5_MASKS_SERVER                   \
  45                                  | OPTION_MASK_POPCNTD                  \
  46                                  | OPTION_MASK_ALTIVEC                  \
  47                                  | OPTION_MASK_VSX)
  48
  49 /* For now, don't provide an embedded version of ISA 2.07.  */
  50 #define ISA_2_7_MASKS_SERVER    (ISA_2_6_MASKS_SERVER                   \
  51                                  | OPTION_MASK_P8_FUSION                \
  52                                  | OPTION_MASK_P8_VECTOR                \
  53                                  | OPTION_MASK_CRYPTO                   \
  54                                  | OPTION_MASK_DIRECT_MOVE              \
  55                                  | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
  56                                  | OPTION_MASK_HTM                      \
  57                                  | OPTION_MASK_QUAD_MEMORY              \
  58                                  | OPTION_MASK_QUAD_MEMORY_ATOMIC)
  59
  60 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
  61    FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
  62 #define ISA_3_0_MASKS_SERVER    (ISA_2_7_MASKS_SERVER                   \
  63                                  | OPTION_MASK_ISEL                     \
  64                                  | OPTION_MASK_MODULO                   \
  65                                  | OPTION_MASK_P9_FUSION                \
  66                                  | OPTION_MASK_P9_DFORM_SCALAR          \
  67                                  | OPTION_MASK_P9_DFORM_VECTOR          \
  68                                  | OPTION_MASK_P9_MINMAX                \
  69                                  | OPTION_MASK_P9_MISC                  \
  70                                  | OPTION_MASK_P9_VECTOR)
  71
  72 /* Support for the IEEE 128-bit floating point hardware requires a lot of the
  73    VSX instructions that are part of ISA 3.0.  */
  74 #define ISA_3_0_MASKS_IEEE      (OPTION_MASK_VSX                        \
  75                                  | OPTION_MASK_P8_VECTOR                \
  76                                  | OPTION_MASK_P9_VECTOR                \
  77                                  | OPTION_MASK_DIRECT_MOVE)
  78
  79 /* Flags that need to be turned off if -mno-power9-vector.  */
  80 #define OTHER_P9_VECTOR_MASKS   (OPTION_MASK_FLOAT128_HW                \
  81                                  | OPTION_MASK_P9_DFORM_SCALAR          \
  82                                  | OPTION_MASK_P9_DFORM_VECTOR          \
  83                                  | OPTION_MASK_P9_MINMAX)
  84
  85 /* Flags that need to be turned off if -mno-power8-vector.  */
  86 #define OTHER_P8_VECTOR_MASKS   (OTHER_P9_VECTOR_MASKS                  \
  87                                  | OPTION_MASK_P9_VECTOR                \
  88                                  | OPTION_MASK_DIRECT_MOVE              \
  89                                  | OPTION_MASK_CRYPTO)
  90
  91 /* Flags that need to be turned off if -mno-vsx.  */
  92 #define OTHER_VSX_VECTOR_MASKS  (OTHER_P8_VECTOR_MASKS                  \
  93                                  | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
  94                                  | OPTION_MASK_FLOAT128_KEYWORD         \
  95                                  | OPTION_MASK_FLOAT128_TYPE            \
  96                                  | OPTION_MASK_P8_VECTOR                \
  97                                  | OPTION_MASK_VSX_TIMODE)
  98
  99 #define POWERPC_7400_MASK       (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
 100
 101 /* Deal with ports that do not have -mstrict-align.  */
 102 #ifdef OPTION_MASK_STRICT_ALIGN
 103 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
 104 #else
 105 #define OPTION_MASK_STRICT_ALIGN 0
 106 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
 107 #ifndef MASK_STRICT_ALIGN
 108 #define MASK_STRICT_ALIGN 0
 109 #endif
 110 #endif
 111
 112 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 113 #define POWERPC_MASKS           (OPTION_MASK_ALTIVEC                    \
 114                                  | OPTION_MASK_CMPB                     \
 115                                  | OPTION_MASK_CRYPTO                   \
 116                                  | OPTION_MASK_DFP                      \
 117                                  | OPTION_MASK_DIRECT_MOVE              \
 118                                  | OPTION_MASK_DLMZB                    \
 119                                  | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 120                                  | OPTION_MASK_FLOAT128_HW              \
 121                                  | OPTION_MASK_FLOAT128_KEYWORD         \
 122                                  | OPTION_MASK_FLOAT128_TYPE            \
 123                                  | OPTION_MASK_FPRND                    \
 124                                  | OPTION_MASK_HTM                      \
 125                                  | OPTION_MASK_ISEL                     \
 126                                  | OPTION_MASK_LRA                      \
 127                                  | OPTION_MASK_MFCRF                    \
 128                                  | OPTION_MASK_MFPGPR                   \
 129                                  | OPTION_MASK_MODULO                   \
 130                                  | OPTION_MASK_MULHW                    \
 131                                  | OPTION_MASK_NO_UPDATE                \
 132                                  | OPTION_MASK_P8_FUSION                \
 133                                  | OPTION_MASK_P8_VECTOR                \
 134                                  | OPTION_MASK_P9_DFORM_SCALAR          \
 135                                  | OPTION_MASK_P9_DFORM_VECTOR          \
 136                                  | OPTION_MASK_P9_FUSION                \
 137                                  | OPTION_MASK_P9_MINMAX                \
 138                                  | OPTION_MASK_P9_MISC                  \
 139                                  | OPTION_MASK_P9_VECTOR                \
 140                                  | OPTION_MASK_POPCNTB                  \
 141                                  | OPTION_MASK_POPCNTD                  \
 142                                  | OPTION_MASK_POWERPC64                \
 143                                  | OPTION_MASK_PPC_GFXOPT               \
 144                                  | OPTION_MASK_PPC_GPOPT                \
 145                                  | OPTION_MASK_QUAD_MEMORY              \
 146                                  | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
 147                                  | OPTION_MASK_RECIP_PRECISION          \
 148                                  | OPTION_MASK_SOFT_FLOAT               \
 149                                  | OPTION_MASK_STRICT_ALIGN_OPTIONAL    \
 150                                  | OPTION_MASK_TOC_FUSION               \
 151                                  | OPTION_MASK_VSX                      \
 152                                  | OPTION_MASK_VSX_TIMODE)
 153
 154 #endif
 155
 156 /* This table occasionally claims that a processor does not support a
 157    particular feature even though it does, but the feature is slower than the
 158    alternative.  Thus, it shouldn't be relied on as a complete description of
 159    the processor's support.
 160
 161    Please keep this list in order, and don't forget to update the documentation
 162    in invoke.texi when adding a new processor or flag.
 163
 164    Before including this file, define a macro:
 165
 166    RS6000_CPU (NAME, CPU, FLAGS)
 167
 168    where the arguments are the fields of struct rs6000_ptt.  */
 169
 170 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
 171 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
 172 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 173 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
 174 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 175 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 176 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 177 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 178 RS6000_CPU ("476", PROCESSOR_PPC476,
 179             MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
 180             | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 181 RS6000_CPU ("476fp", PROCESSOR_PPC476,
 182             MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 183             | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 184 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 185 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
 186 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 187 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 188 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 189 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
 190 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
 191 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
 192 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 193 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 194 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
 195 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
 196 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 197 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 198 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 199 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 200 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
 201 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
 202 RS6000_CPU ("a2", PROCESSOR_PPCA2,
 203             MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
 204             | MASK_NO_UPDATE)
 205 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
 206 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
 207 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
 208 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
 209             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 210 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
 211             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 212 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
 213             | MASK_MFCRF | MASK_ISEL)
 214 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 215 RS6000_CPU ("970", PROCESSOR_POWER4,
 216             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 217 RS6000_CPU ("cell", PROCESSOR_CELL,
 218             POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 219 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
 220 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 221 RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
 222 RS6000_CPU ("G5", PROCESSOR_POWER4,
 223             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 224 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
 225 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 226 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
 227             | MASK_PPC_GFXOPT | MASK_MFCRF)
 228 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 229             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
 230 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 231             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
 232 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 233             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 234             | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
 235 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 236             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 237             | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
 238 RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
 239 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 240 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
 241 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 242 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
 243 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 244 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)