gcc/config/rs6000/rs64.md

   1 ;; Scheduling description for IBM RS64 processors.
   2 ;;   Copyright (C) 2003-2024 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 3, or (at your
   9 ;; option) any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_automaton "rs64,rs64fp")
  21 (define_cpu_unit "iu_rs64" "rs64")
  22 (define_cpu_unit "mciu_rs64" "rs64")
  23 (define_cpu_unit "fpu_rs64" "rs64fp")
  24 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
  25
  26 ;; RS64a 64-bit IU, LSU, FPU, BPU
  27
  28 (define_insn_reservation "rs64a-load" 2
  29   (and (eq_attr "type" "load")
  30        (eq_attr "cpu" "rs64a"))
  31   "lsu_rs64")
  32
  33 (define_insn_reservation "rs64a-store" 2
  34   (and (eq_attr "type" "store,fpstore")
  35        (eq_attr "cpu" "rs64a"))
  36   "lsu_rs64")
  37
  38 (define_insn_reservation "rs64a-fpload" 3
  39   (and (eq_attr "type" "fpload")
  40        (eq_attr "cpu" "rs64a"))
  41   "lsu_rs64")
  42
  43 (define_insn_reservation "rs64a-llsc" 2
  44   (and (eq_attr "type" "load_l,store_c")
  45        (eq_attr "cpu" "rs64a"))
  46   "lsu_rs64")
  47
  48 (define_insn_reservation "rs64a-integer" 1
  49   (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
  50             (and (eq_attr "type" "add,logical,shift,exts")
  51                  (eq_attr "dot" "no")))
  52        (eq_attr "cpu" "rs64a"))
  53   "iu_rs64")
  54
  55 (define_insn_reservation "rs64a-two" 1
  56   (and (eq_attr "type" "two")
  57        (eq_attr "cpu" "rs64a"))
  58   "iu_rs64,iu_rs64")
  59
  60 (define_insn_reservation "rs64a-three" 1
  61   (and (eq_attr "type" "three")
  62        (eq_attr "cpu" "rs64a"))
  63   "iu_rs64,iu_rs64,iu_rs64")
  64
  65 (define_insn_reservation "rs64a-imul" 20
  66   (and (eq_attr "type" "mul")
  67        (eq_attr "size" "32")
  68        (eq_attr "cpu" "rs64a"))
  69   "mciu_rs64*13")
  70
  71 (define_insn_reservation "rs64a-imul2" 12
  72   (and (eq_attr "type" "mul")
  73        (eq_attr "size" "16")
  74        (eq_attr "cpu" "rs64a"))
  75   "mciu_rs64*5")
  76
  77 (define_insn_reservation "rs64a-imul3" 8
  78   (and (eq_attr "type" "mul")
  79        (eq_attr "size" "8")
  80        (eq_attr "cpu" "rs64a"))
  81   "mciu_rs64*2")
  82
  83 (define_insn_reservation "rs64a-lmul" 34
  84   (and (eq_attr "type" "mul")
  85        (eq_attr "size" "64")
  86        (eq_attr "cpu" "rs64a"))
  87   "mciu_rs64*34")
  88
  89 (define_insn_reservation "rs64a-idiv" 66
  90   (and (eq_attr "type" "div")
  91        (eq_attr "size" "32")
  92        (eq_attr "cpu" "rs64a"))
  93   "mciu_rs64*66")
  94
  95 (define_insn_reservation "rs64a-ldiv" 66
  96   (and (eq_attr "type" "div")
  97        (eq_attr "size" "64")
  98        (eq_attr "cpu" "rs64a"))
  99   "mciu_rs64*66")
 100
 101 (define_insn_reservation "rs64a-compare" 3
 102   (and (ior (eq_attr "type" "cmp")
 103             (and (eq_attr "type" "add,logical,shift,exts")
 104                  (eq_attr "dot" "yes")))
 105        (eq_attr "cpu" "rs64a"))
 106   "iu_rs64,nothing,bpu_rs64")
 107
 108 (define_insn_reservation "rs64a-fpcompare" 5
 109   (and (eq_attr "type" "fpcompare")
 110        (eq_attr "cpu" "rs64a"))
 111   "mciu_rs64,fpu_rs64,bpu_rs64")
 112
 113 (define_insn_reservation "rs64a-fp" 4
 114   (and (eq_attr "type" "fp,fpsimple,dmul")
 115        (eq_attr "cpu" "rs64a"))
 116   "mciu_rs64,fpu_rs64")
 117
 118 (define_insn_reservation "rs64a-sdiv" 31
 119   (and (eq_attr "type" "sdiv,ddiv")
 120        (eq_attr "cpu" "rs64a"))
 121   "mciu_rs64,fpu_rs64*31")
 122
 123 (define_insn_reservation "rs64a-sqrt" 49
 124   (and (eq_attr "type" "ssqrt,dsqrt")
 125        (eq_attr "cpu" "rs64a"))
 126   "mciu_rs64,fpu_rs64*49")
 127
 128 (define_insn_reservation "rs64a-mfcr" 2
 129   (and (eq_attr "type" "mfcr")
 130        (eq_attr "cpu" "rs64a"))
 131   "lsu_rs64")
 132
 133 (define_insn_reservation "rs64a-mtcr" 3
 134   (and (eq_attr "type" "mtcr")
 135        (eq_attr "cpu" "rs64a"))
 136   "lsu_rs64")
 137
 138 (define_insn_reservation "rs64a-mtjmpr" 3
 139   (and (eq_attr "type" "mtjmpr")
 140        (eq_attr "cpu" "rs64a"))
 141   "lsu_rs64")
 142
 143 (define_insn_reservation "rs64a-mfjmpr" 2
 144   (and (eq_attr "type" "mfjmpr")
 145        (eq_attr "cpu" "rs64a"))
 146   "lsu_rs64")
 147
 148 (define_insn_reservation "rs64a-jmpreg" 1
 149   (and (eq_attr "type" "jmpreg,branch,cr_logical")
 150        (eq_attr "cpu" "rs64a"))
 151   "bpu_rs64")
 152
 153 (define_insn_reservation "rs64a-isync" 6
 154   (and (eq_attr "type" "isync")
 155        (eq_attr "cpu" "rs64a"))
 156   "bpu_rs64")
 157
 158 (define_insn_reservation "rs64a-sync" 1
 159   (and (eq_attr "type" "sync")
 160        (eq_attr "cpu" "rs64a"))
 161   "lsu_rs64")
 162