gcc/config/s390/s390-modes.def

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 2002-2020 Free Software Foundation, Inc.
   3    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4                   Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
  23 INT_MODE (OI, 32);
  24
  25 /* Define TFmode to work around reload problem PR 20927.  */
  26 FLOAT_MODE (TF, 16, ieee_quad_format);
  27
  28 /* Add any extra modes needed to represent the condition code.  */
  29
  30 /*
  31
  32 Condition Codes
  33
  34       CC0         CC1          CC2         CC3
  35
  36 Check for zero
  37
  38 CCZ:  EQ          NE           NE          NE
  39 CCZ1: EQ          NE                                  (CS)
  40
  41 Unsigned compares
  42
  43 CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
  44 CCUR: EQ          GTU          LTU         NE         (CLGF/R)
  45
  46 Signed compares
  47
  48 CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
  49                                                        LTDBR, LTDR, LTEBR, LTER,
  50                                                        CG/R, C/R/Y, CGHI, CHI,
  51                                                        CDB/R, CD/R, CEB/R, CE/R,
  52                                                        ADB/R, AEB/R, SDB/R, SEB/R,
  53                                                        SRAG, SRA, SRDA)
  54 CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
  55 CCSFPS: EQ        LT           GT          UNORDERED  (KEB/R, KDB/R, KXBR, KDTR,
  56                                                        KXTR, WFK)
  57
  58 Condition codes resulting from add with overflow
  59
  60 CCA:  EQ          LT           GT          Overflow
  61 CCAP: EQ          LT           GT          LT         (AGHI, AHI)
  62 CCAN: EQ          LT           GT          GT         (AGHI, AHI)
  63
  64 Condition codes for overflow checking resulting from signed adds/subs/mults
  65
  66 CCO:  EQ          EQ           EQ          NE         (AGR, AGHI, SGR, MSC, ...)
  67
  68 Condition codes of unsigned adds and subs
  69
  70 CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
  71                                                        ALCG/R, ALC/R,
  72                                                        SLGF/R, SLG/R, SL/R/Y,
  73                                                        SLBG/R, SLB/R)
  74 CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
  75 CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
  76 CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
  77
  78 Test under mask checks
  79
  80 CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
  81                                                        C/R/Y, CHI, NG/R, N/R/Y,
  82                                                        OG/R, O/R/Y, XG/R, X/R/Y)
  83 CCT1: NE          EQ           NE          NE         (TMH, TML)
  84 CCT2: NE          NE           EQ          NE         (TMH, TML)
  85 CCT3: NE          NE           NE          EQ         (TMH, TML)
  86
  87 CCA and CCT modes are request only modes. These modes are never returned by
  88 s390_select_cc_mode. They are only intended to match other modes.
  89
  90 Requested mode            -> Destination CC register mode
  91
  92 CCS, CCU, CCT, CCSR, CCUR -> CCZ
  93 CCA                       -> CCAP, CCAN
  94
  95
  96
  97 *** Comments ***
  98
  99 CCAP, CCAN
 100
 101 The CC obtained from add instruction usually can't be used for comparisons
 102 because its coupling with overflow flag. In case of an overflow the
 103 less than/greater than data are lost. Nevertheless a comparison can be done
 104 whenever immediate values are involved because they are known at compile time.
 105 If you know whether the used constant is positive or negative you can predict
 106 the sign of the result even in case of an overflow.
 107
 108
 109 CCO
 110
 111 This mode is used to check whether there was an overflow condition in
 112 a signed add, sub, or mul operation.  See (addv<mode>4, subv<mode>4,
 113 mulv<mode>4 patterns).
 114
 115
 116 CCT, CCT1, CCT2, CCT3
 117
 118 If bits of an integer masked with an AND instruction are checked, the test under
 119 mask instructions turn out to be very handy for a set of special cases.
 120 The simple cases are checks whether all masked bits are zero or ones:
 121
 122   int a;
 123   if ((a & (16 + 128)) == 0)          -> CCT/CCZ
 124   if ((a & (16 + 128)) == 16 + 128)   -> CCT3
 125
 126 Using two extra modes makes it possible to do complete checks on two bits of an
 127 integer (This is possible on register operands only. TM does not provide the
 128 information necessary for CCT1 and CCT2 modes.):
 129
 130   int a;
 131   if ((a & (16 + 128)) == 16)         -> CCT1
 132   if ((a & (16 + 128)) == 128)        -> CCT2
 133
 134
 135 CCSR, CCUR
 136
 137 There are several instructions comparing 32 bit with 64-bit unsigned/signed
 138 values. Such instructions can be considered to have a builtin zero/sign_extend.
 139 The problem is that in the RTL (to be canonical) the zero/sign extended operand
 140 has to be the first one but the machine instructions like it the other way
 141 around. The following both modes can be considered as CCS and CCU modes with
 142 exchanged operands.
 143
 144
 145 CCSFPS
 146
 147 This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT.
 148
 149
 150 CCL1, CCL2
 151
 152 These modes represent the result of overflow checks.
 153
 154 if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
 155 if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
 156
 157 They are used when multi word numbers are computed dealing one SImode part after
 158 another or whenever manual overflow checks like the examples above are
 159 compiled.
 160
 161
 162 CCL3
 163
 164 A logical subtract instruction sets the borrow bit in case of an overflow.
 165 The resulting condition code of those instructions is represented by the
 166 CCL3 mode. Together with the CCU mode this mode is used for jumpless
 167 implementations of several if-constructs - see s390_expand_addcc for more
 168 details.
 169
 170 CCZ1
 171
 172 The compare and swap instructions sets the condition code to 0/1 if the
 173 operands were equal/unequal. The CCZ1 mode ensures the result can be
 174 effectively placed into a register.
 175
 176 CCVIH, CCVIHU, CCVFH, CCVFHE
 177
 178 These are condition code modes used in instructions setting the
 179 condition code.  The mode determines which comparison to perform (H -
 180 high, HU - high unsigned, HE - high or equal) and whether it is a
 181 floating point comparison or not (I - int, F - float).
 182
 183 The comparison operation to be performed needs to be encoded into the
 184 condition code mode since the comparison operator is not available in
 185 compare style patterns (set cc (compare (op0) (op1))).  So the
 186 condition code mode is the only information to determine the
 187 instruction to be used.
 188
 189 CCVIALL, CCVIANY, CCVFALL, CCVFANY
 190
 191 These modes are used in instructions reading the condition code.
 192 Opposed to the CC producer patterns the comparison operator is
 193 available.  Hence the comparison operation does not need to be part of
 194 the CC mode.  However, we still need to know whether CC has been
 195 generated by a float or an integer comparison in order to be able to
 196 invert the condition correctly (int: GT -> LE, float: GT -> UNLE).
 197
 198 The ALL and ANY variants differ only in the usage of CC1 which
 199 indicates a mixed result across the vector elements.  Be aware that
 200 depending on the comparison code the ALL and ANY variants might
 201 actually refer to their opposite meaning.  I.e. while inverting the
 202 comparison in (EQ (reg:CCVIALL 33) (const_int 0)) results in (NE
 203 (reg:CCVIALL 33) (const_int 0)) it in fact describes an ANY comparison
 204 (inverting "all equal" should be "any not equal") However, the
 205 middle-end does invert only the comparison operator without touching
 206 the mode.
 207 Hence, the ALL/ANY in the mode names refer to the meaning in the
 208 context of EQ, GT, GE while for the inverted codes it actually means
 209 ANY/ALL.
 210
 211 CCRAW
 212
 213 The cc mode generated by a non-compare instruction.  The condition
 214 code mask for the CC consumer is determined by the comparison operator
 215 (only EQ and NE allowed) and the immediate value given as second
 216 operand to the operator.  For the other CC modes this value used to be
 217 0.
 218
 219 */
 220
 221
 222 CC_MODE (CCZ);
 223 CC_MODE (CCZ1);
 224 CC_MODE (CCA);
 225 CC_MODE (CCAP);
 226 CC_MODE (CCAN);
 227 CC_MODE (CCO);
 228 CC_MODE (CCL);
 229 CC_MODE (CCL1);
 230 CC_MODE (CCL2);
 231 CC_MODE (CCL3);
 232 CC_MODE (CCU);
 233 CC_MODE (CCUR);
 234 CC_MODE (CCS);
 235 CC_MODE (CCSR);
 236 CC_MODE (CCSFPS);
 237 CC_MODE (CCT);
 238 CC_MODE (CCT1);
 239 CC_MODE (CCT2);
 240 CC_MODE (CCT3);
 241 CC_MODE (CCRAW);
 242
 243 CC_MODE (CCVEQ);
 244
 245 CC_MODE (CCVIH);
 246 CC_MODE (CCVIHU);
 247
 248 CC_MODE (CCVFH);
 249 CC_MODE (CCVFHE);
 250
 251 CC_MODE (CCVIALL);
 252 CC_MODE (CCVIANY);
 253
 254 CC_MODE (CCVFALL);
 255 CC_MODE (CCVFANY);
 256
 257 /* Vector modes.  */
 258
 259 VECTOR_MODES (INT, 2);        /*                 V2QI */
 260 VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
 261 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI */
 262 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */
 263
 264 VECTOR_MODE (FLOAT, SF, 2);   /* V2SF */
 265 VECTOR_MODE (FLOAT, SF, 4);   /* V4SF */
 266 VECTOR_MODE (FLOAT, DF, 2);   /* V2DF */
 267
 268 VECTOR_MODE (INT, QI, 1);     /* V1QI */
 269 VECTOR_MODE (INT, HI, 1);     /* V1HI */
 270 VECTOR_MODE (INT, SI, 1);     /* V1SI */
 271 VECTOR_MODE (INT, DI, 1);     /* V1DI */
 272 VECTOR_MODE (INT, TI, 1);     /* V1TI */
 273
 274 VECTOR_MODE (FLOAT, SF, 1);   /* V1SF */
 275 VECTOR_MODE (FLOAT, DF, 1);   /* V1DF */
 276 VECTOR_MODE (FLOAT, TF, 1);   /* V1TF */