1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #define IN_TARGET_CODE 1
27 #define INCLUDE_VECTOR
29 #include "coretypes.h"
39 #include "stringpool.h"
44 #include "diagnostic-core.h"
46 #include "fold-const.h"
47 #include "stor-layout.h"
55 #include "insn-attr.h"
57 #include "langhooks.h"
60 #include "sched-int.h"
62 #include "tm-constrs.h"
64 #include "tree-pass.h"
71 /* This file should be included last. */
72 #include "target-def.h"
74 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
76 #define CONST_OK_FOR_ADD(size) CONST_OK_FOR_I08 (size)
77 #define GEN_MOV (*(gen_movsi))
78 #define GEN_ADD3 (*(gen_addsi3))
79 #define GEN_SUB3 (*(gen_subsi3))
81 /* Used to simplify the logic below. Find the attributes wherever
83 #define SH_ATTRIBUTES(decl) \
84 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
85 : DECL_ATTRIBUTES (decl) \
86 ? (DECL_ATTRIBUTES (decl)) \
87 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
89 /* Set to true by expand_prologue() when the function is an
91 bool current_function_interrupt
;
93 tree sh_deferred_function_attributes
;
94 tree
*sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
96 /* Global variables for machine-dependent things. */
98 /* Which cpu are we scheduling for. */
99 enum processor_type sh_cpu
;
101 /* Definitions used in ready queue reordering for first scheduling pass. */
103 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
104 static short *regmode_weight
[2];
106 /* Total SFmode and SImode weights of scheduled insns. */
107 static int curr_regmode_pressure
[2];
109 /* Number of r0 life regions. */
110 static int r0_life_regions
;
112 /* If true, skip cycles for Q -> R movement. */
113 static int skip_cycles
= 0;
115 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
116 and returned from sh_reorder2. */
117 static short cached_can_issue_more
;
119 /* Unique number for UNSPEC_BBR pattern. */
120 static unsigned int unspec_bbr_uid
= 1;
122 /* Provides the class number of the smallest class containing
124 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
126 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
127 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
128 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
129 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
130 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
131 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
132 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
133 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
134 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
135 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
136 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
137 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
138 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
139 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
140 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
141 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
142 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
143 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
144 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
145 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
146 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
147 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
148 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
149 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
150 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
151 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
152 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
153 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
154 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
155 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
156 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
157 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
158 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
159 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
160 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
161 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
162 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
163 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
164 GENERAL_REGS
, GENERAL_REGS
,
167 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
168 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
170 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
171 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
172 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
174 int assembler_dialect
;
176 static void split_branches (rtx_insn
*);
177 static int branch_dest (rtx
);
178 static void print_slot (rtx_sequence
*);
179 static rtx_code_label
*add_constant (rtx
, machine_mode
, rtx
);
180 static void dump_table (rtx_insn
*, rtx_insn
*);
181 static bool broken_move (rtx_insn
*);
182 static bool mova_p (rtx_insn
*);
183 static rtx_insn
*find_barrier (int, rtx_insn
*, rtx_insn
*);
184 static bool noncall_uses_reg (rtx
, rtx_insn
*, rtx
*);
185 static rtx_insn
*gen_block_redirect (rtx_insn
*, int, int);
186 static void sh_reorg (void);
187 static void sh_option_override (void);
188 static void sh_override_options_after_change (void);
189 static void output_stack_adjust (int, rtx
, int, HARD_REG_SET
*, bool);
190 static rtx_insn
* emit_frame_insn (rtx
);
191 static rtx
push (int);
192 static void pop (int);
193 static void push_regs (HARD_REG_SET
* mask
, bool interrupt_handler
);
194 static int calc_live_regs (HARD_REG_SET
*);
195 static HOST_WIDE_INT
rounded_frame_size (int);
196 static bool sh_frame_pointer_required (void);
197 static void sh_emit_mode_set (int, int, int, HARD_REG_SET
);
198 static int sh_mode_needed (int, rtx_insn
*);
199 static int sh_mode_after (int, int, rtx_insn
*);
200 static int sh_mode_entry (int);
201 static int sh_mode_exit (int);
202 static int sh_mode_priority (int entity
, int n
);
204 static rtx
mark_constant_pool_use (rtx
);
205 static tree
sh_handle_interrupt_handler_attribute (tree
*, tree
, tree
,
207 static tree
sh_handle_resbank_handler_attribute (tree
*, tree
,
209 static tree
sh2a_handle_function_vector_handler_attribute (tree
*, tree
,
211 static tree
sh_handle_sp_switch_attribute (tree
*, tree
, tree
, int, bool *);
212 static tree
sh_handle_trap_exit_attribute (tree
*, tree
, tree
, int, bool *);
213 static tree
sh_handle_renesas_attribute (tree
*, tree
, tree
, int, bool *);
214 static void sh_print_operand (FILE *, rtx
, int);
215 static void sh_print_operand_address (FILE *, machine_mode
, rtx
);
216 static bool sh_print_operand_punct_valid_p (unsigned char code
);
217 static bool sh_asm_output_addr_const_extra (FILE *file
, rtx x
);
218 static void sh_output_function_epilogue (FILE *);
219 static void sh_insert_attributes (tree
, tree
*);
220 static const char *sh_check_pch_target_flags (int);
221 static int sh_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
222 static int sh_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
223 static int sh_issue_rate (void);
224 static int sh_dfa_new_cycle (FILE *, int, rtx_insn
*, int, int, int *sort_p
);
225 static short find_set_regmode_weight (rtx
, machine_mode
);
226 static short find_insn_regmode_weight (rtx
, machine_mode
);
227 static void find_regmode_weight (basic_block
, machine_mode
);
228 static int find_r0_life_regions (basic_block
);
229 static void sh_md_init_global (FILE *, int, int);
230 static void sh_md_finish_global (FILE *, int);
231 static int rank_for_reorder (const void *, const void *);
232 static void swap_reorder (rtx_insn
**, int);
233 static void ready_reorder (rtx_insn
**, int);
234 static bool high_pressure (machine_mode
);
235 static int sh_reorder (FILE *, int, rtx_insn
**, int *, int);
236 static int sh_reorder2 (FILE *, int, rtx_insn
**, int *, int);
237 static void sh_md_init (FILE *, int, int);
238 static int sh_variable_issue (FILE *, int, rtx_insn
*, int);
240 static bool sh_function_ok_for_sibcall (tree
, tree
);
242 static bool sh_can_follow_jump (const rtx_insn
*, const rtx_insn
*);
243 static bool sh_ms_bitfield_layout_p (const_tree
);
245 static void sh_init_builtins (void);
246 static tree
sh_builtin_decl (unsigned, bool);
247 static rtx
sh_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
248 static void sh_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
249 HOST_WIDE_INT
, tree
);
250 static void sh_file_start (void);
251 static bool sh_assemble_integer (rtx
, unsigned int, int);
252 static bool flow_dependent_p (rtx_insn
*, rtx_insn
*);
253 static void flow_dependent_p_1 (rtx
, const_rtx
, void *);
254 static int shiftcosts (rtx
);
255 static int and_xor_ior_costs (rtx
, int);
256 static int addsubcosts (rtx
);
257 static int multcosts (rtx
);
258 static bool unspec_caller_rtx_p (rtx
);
259 static bool sh_cannot_copy_insn_p (rtx_insn
*);
260 static bool sh_cannot_force_const_mem_p (machine_mode
, rtx
);
261 static bool sh_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
262 static int sh_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
263 static int sh_pr_n_sets (void);
264 static rtx
sh_allocate_initial_value (rtx
);
265 static reg_class_t
sh_preferred_reload_class (rtx
, reg_class_t
);
266 static reg_class_t
sh_secondary_reload (bool, rtx
, reg_class_t
,
268 struct secondary_reload_info
*);
269 static bool sh_legitimate_address_p (machine_mode
, rtx
, bool);
270 static rtx
sh_legitimize_address (rtx
, rtx
, machine_mode
);
271 static rtx
sh_delegitimize_address (rtx
);
272 static bool sh_cannot_substitute_mem_equiv_p (rtx
);
273 static bool sh_legitimize_address_displacement (rtx
*, rtx
*,
274 poly_int64
, machine_mode
);
275 static int scavenge_reg (HARD_REG_SET
*s
);
277 static rtx
sh_struct_value_rtx (tree
, int);
278 static rtx
sh_function_value (const_tree
, const_tree
, bool);
279 static bool sh_function_value_regno_p (const unsigned int);
280 static rtx
sh_libcall_value (machine_mode
, const_rtx
);
281 static bool sh_return_in_memory (const_tree
, const_tree
);
282 static rtx
sh_builtin_saveregs (void);
283 static void sh_setup_incoming_varargs (cumulative_args_t
,
284 const function_arg_info
&, int *, int);
285 static bool sh_strict_argument_naming (cumulative_args_t
);
286 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t
);
287 static void sh_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
288 static tree
sh_build_builtin_va_list (void);
289 static void sh_va_start (tree
, rtx
);
290 static tree
sh_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
291 static bool sh_promote_prototypes (const_tree
);
292 static machine_mode
sh_promote_function_mode (const_tree type
,
297 static bool sh_pass_by_reference (cumulative_args_t
,
298 const function_arg_info
&);
299 static bool sh_callee_copies (cumulative_args_t
, const function_arg_info
&);
300 static int sh_arg_partial_bytes (cumulative_args_t
, const function_arg_info
&);
301 static void sh_function_arg_advance (cumulative_args_t
,
302 const function_arg_info
&);
303 static rtx
sh_function_arg (cumulative_args_t
, const function_arg_info
&);
304 static int sh_dwarf_calling_convention (const_tree
);
305 static void sh_encode_section_info (tree
, rtx
, int);
306 static bool sh2a_function_vector_p (tree
);
307 static void sh_trampoline_init (rtx
, tree
, rtx
);
308 static rtx
sh_trampoline_adjust_address (rtx
);
309 static void sh_conditional_register_usage (void);
310 static bool sh_legitimate_constant_p (machine_mode
, rtx
);
311 static int mov_insn_size (machine_mode
, bool);
312 static int mov_insn_alignment_mask (machine_mode
, bool);
313 static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT
,
315 enum by_pieces_operation
,
317 static bool sequence_insn_p (rtx_insn
*);
318 static void sh_canonicalize_comparison (int *, rtx
*, rtx
*, bool);
319 static void sh_canonicalize_comparison (enum rtx_code
&, rtx
&, rtx
&,
321 static bool sh_legitimate_combined_insn (rtx_insn
* insn
);
323 static bool sh_fixed_condition_code_regs (unsigned int* p1
, unsigned int* p2
);
325 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
326 static unsigned int sh_hard_regno_nregs (unsigned int, machine_mode
);
327 static bool sh_hard_regno_mode_ok (unsigned int, machine_mode
);
328 static bool sh_modes_tieable_p (machine_mode
, machine_mode
);
329 static bool sh_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t
);
331 static const struct attribute_spec sh_attribute_table
[] =
333 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
334 affects_type_identity, handler, exclude } */
335 { "interrupt_handler", 0, 0, true, false, false, false,
336 sh_handle_interrupt_handler_attribute
, NULL
},
337 { "sp_switch", 1, 1, true, false, false, false,
338 sh_handle_sp_switch_attribute
, NULL
},
339 { "trap_exit", 1, 1, true, false, false, false,
340 sh_handle_trap_exit_attribute
, NULL
},
341 { "renesas", 0, 0, false, true, false, false,
342 sh_handle_renesas_attribute
, NULL
},
343 { "trapa_handler", 0, 0, true, false, false, false,
344 sh_handle_interrupt_handler_attribute
, NULL
},
345 { "nosave_low_regs", 0, 0, true, false, false, false,
346 sh_handle_interrupt_handler_attribute
, NULL
},
347 { "resbank", 0, 0, true, false, false, false,
348 sh_handle_resbank_handler_attribute
, NULL
},
349 { "function_vector", 1, 1, true, false, false, false,
350 sh2a_handle_function_vector_handler_attribute
, NULL
},
351 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
354 /* Initialize the GCC target structure. */
355 #undef TARGET_ATTRIBUTE_TABLE
356 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
358 /* The next two are used for debug info when compiling with -gdwarf. */
359 #undef TARGET_ASM_UNALIGNED_HI_OP
360 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
361 #undef TARGET_ASM_UNALIGNED_SI_OP
362 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
364 #undef TARGET_OPTION_OVERRIDE
365 #define TARGET_OPTION_OVERRIDE sh_option_override
367 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
368 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
369 sh_override_options_after_change
371 #undef TARGET_PRINT_OPERAND
372 #define TARGET_PRINT_OPERAND sh_print_operand
373 #undef TARGET_PRINT_OPERAND_ADDRESS
374 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
375 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
376 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
377 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
378 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
380 #undef TARGET_ASM_FUNCTION_EPILOGUE
381 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
383 #undef TARGET_ASM_OUTPUT_MI_THUNK
384 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
386 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
387 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
388 hook_bool_const_tree_hwi_hwi_const_tree_true
390 #undef TARGET_ASM_FILE_START
391 #define TARGET_ASM_FILE_START sh_file_start
392 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
393 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
395 #undef TARGET_ASM_INTEGER
396 #define TARGET_ASM_INTEGER sh_assemble_integer
398 #undef TARGET_REGISTER_MOVE_COST
399 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
401 #undef TARGET_INSERT_ATTRIBUTES
402 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
404 #undef TARGET_SCHED_ADJUST_COST
405 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
407 #undef TARGET_SCHED_ISSUE_RATE
408 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
410 /* The next 5 hooks have been implemented for reenabling sched1. With the
411 help of these macros we are limiting the movement of insns in sched1 to
412 reduce the register pressure. The overall idea is to keep count of SImode
413 and SFmode regs required by already scheduled insns. When these counts
414 cross some threshold values; give priority to insns that free registers.
415 The insn that frees registers is most likely to be the insn with lowest
416 LUID (original insn order); but such an insn might be there in the stalled
417 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
418 up to a max of 8 cycles so that such insns may move from Q -> R.
420 The description of the hooks are as below:
422 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
423 scheduler; it is called inside the sched_init function just after
424 find_insn_reg_weights function call. It is used to calculate the SImode
425 and SFmode weights of insns of basic blocks; much similar to what
426 find_insn_reg_weights does.
427 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
429 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
430 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
433 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
434 high; reorder the ready queue so that the insn with lowest LUID will be
437 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
438 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
440 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
441 can be returned from TARGET_SCHED_REORDER2.
443 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
445 #undef TARGET_SCHED_DFA_NEW_CYCLE
446 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
448 #undef TARGET_SCHED_INIT_GLOBAL
449 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
451 #undef TARGET_SCHED_FINISH_GLOBAL
452 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
454 #undef TARGET_SCHED_VARIABLE_ISSUE
455 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
457 #undef TARGET_SCHED_REORDER
458 #define TARGET_SCHED_REORDER sh_reorder
460 #undef TARGET_SCHED_REORDER2
461 #define TARGET_SCHED_REORDER2 sh_reorder2
463 #undef TARGET_SCHED_INIT
464 #define TARGET_SCHED_INIT sh_md_init
466 #undef TARGET_DELEGITIMIZE_ADDRESS
467 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
469 #undef TARGET_LEGITIMIZE_ADDRESS
470 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
472 #undef TARGET_CAN_FOLLOW_JUMP
473 #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump
475 #undef TARGET_MS_BITFIELD_LAYOUT_P
476 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
478 #undef TARGET_INIT_BUILTINS
479 #define TARGET_INIT_BUILTINS sh_init_builtins
480 #undef TARGET_BUILTIN_DECL
481 #define TARGET_BUILTIN_DECL sh_builtin_decl
482 #undef TARGET_EXPAND_BUILTIN
483 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
485 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
486 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
488 #undef TARGET_CANNOT_COPY_INSN_P
489 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
490 #undef TARGET_RTX_COSTS
491 #define TARGET_RTX_COSTS sh_rtx_costs
492 #undef TARGET_ADDRESS_COST
493 #define TARGET_ADDRESS_COST sh_address_cost
494 #undef TARGET_ALLOCATE_INITIAL_VALUE
495 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
497 #undef TARGET_MACHINE_DEPENDENT_REORG
498 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
500 #undef TARGET_DWARF_REGISTER_SPAN
501 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
504 #undef TARGET_HAVE_TLS
505 #define TARGET_HAVE_TLS true
508 #undef TARGET_PROMOTE_PROTOTYPES
509 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
510 #undef TARGET_PROMOTE_FUNCTION_MODE
511 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
513 #undef TARGET_FUNCTION_VALUE
514 #define TARGET_FUNCTION_VALUE sh_function_value
515 #undef TARGET_FUNCTION_VALUE_REGNO_P
516 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
517 #undef TARGET_LIBCALL_VALUE
518 #define TARGET_LIBCALL_VALUE sh_libcall_value
519 #undef TARGET_STRUCT_VALUE_RTX
520 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
521 #undef TARGET_RETURN_IN_MEMORY
522 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
524 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
525 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
526 #undef TARGET_SETUP_INCOMING_VARARGS
527 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
528 #undef TARGET_STRICT_ARGUMENT_NAMING
529 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
530 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
531 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
532 #undef TARGET_MUST_PASS_IN_STACK
533 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
534 #undef TARGET_PASS_BY_REFERENCE
535 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
536 #undef TARGET_CALLEE_COPIES
537 #define TARGET_CALLEE_COPIES sh_callee_copies
538 #undef TARGET_ARG_PARTIAL_BYTES
539 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
540 #undef TARGET_FUNCTION_ARG
541 #define TARGET_FUNCTION_ARG sh_function_arg
542 #undef TARGET_FUNCTION_ARG_ADVANCE
543 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
545 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
546 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sh_atomic_assign_expand_fenv
548 #undef TARGET_BUILD_BUILTIN_VA_LIST
549 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
550 #undef TARGET_EXPAND_BUILTIN_VA_START
551 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
552 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
553 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
555 #undef TARGET_VECTOR_MODE_SUPPORTED_P
556 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
558 #undef TARGET_CHECK_PCH_TARGET_FLAGS
559 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
561 #undef TARGET_DWARF_CALLING_CONVENTION
562 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
564 #undef TARGET_FRAME_POINTER_REQUIRED
565 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
567 #undef TARGET_MODE_EMIT
568 #define TARGET_MODE_EMIT sh_emit_mode_set
570 #undef TARGET_MODE_NEEDED
571 #define TARGET_MODE_NEEDED sh_mode_needed
573 #undef TARGET_MODE_AFTER
574 #define TARGET_MODE_AFTER sh_mode_after
576 #undef TARGET_MODE_ENTRY
577 #define TARGET_MODE_ENTRY sh_mode_entry
579 #undef TARGET_MODE_EXIT
580 #define TARGET_MODE_EXIT sh_mode_exit
582 #undef TARGET_MODE_PRIORITY
583 #define TARGET_MODE_PRIORITY sh_mode_priority
585 /* Return regmode weight for insn. */
586 #define INSN_REGMODE_WEIGHT(INSN, MODE)\
587 regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
589 /* Return current register pressure for regmode. */
590 #define CURR_REGMODE_PRESSURE(MODE)\
591 curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
593 #undef TARGET_ENCODE_SECTION_INFO
594 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
597 #define TARGET_LRA_P sh_lra_p
599 #undef TARGET_SECONDARY_RELOAD
600 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
602 #undef TARGET_PREFERRED_RELOAD_CLASS
603 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
605 #undef TARGET_CONDITIONAL_REGISTER_USAGE
606 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
608 #undef TARGET_LEGITIMATE_ADDRESS_P
609 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
611 #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P
612 #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P sh_cannot_substitute_mem_equiv_p
614 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
615 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
616 sh_legitimize_address_displacement
618 #undef TARGET_TRAMPOLINE_INIT
619 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
620 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
621 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
623 #undef TARGET_LEGITIMATE_CONSTANT_P
624 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
626 #undef TARGET_CANONICALIZE_COMPARISON
627 #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
629 #undef TARGET_LEGITIMATE_COMBINED_INSN
630 #define TARGET_LEGITIMATE_COMBINED_INSN sh_legitimate_combined_insn
632 #undef TARGET_FIXED_CONDITION_CODE_REGS
633 #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
635 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
636 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
637 sh_use_by_pieces_infrastructure_p
639 /* Machine-specific symbol_ref flags. */
640 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
642 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
643 is used by optabs.c atomic op expansion code as well as in sync.md. */
644 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
645 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
647 #undef TARGET_CANNOT_FORCE_CONST_MEM
648 #define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p
650 #undef TARGET_HARD_REGNO_NREGS
651 #define TARGET_HARD_REGNO_NREGS sh_hard_regno_nregs
652 #undef TARGET_HARD_REGNO_MODE_OK
653 #define TARGET_HARD_REGNO_MODE_OK sh_hard_regno_mode_ok
655 #undef TARGET_MODES_TIEABLE_P
656 #define TARGET_MODES_TIEABLE_P sh_modes_tieable_p
658 #undef TARGET_CAN_CHANGE_MODE_CLASS
659 #define TARGET_CAN_CHANGE_MODE_CLASS sh_can_change_mode_class
661 #undef TARGET_CONSTANT_ALIGNMENT
662 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
664 struct gcc_target targetm
= TARGET_INITIALIZER
;
667 /* Information on the currently selected atomic model.
668 This is initialized in sh_option_override. */
669 static sh_atomic_model selected_atomic_model_
;
671 const sh_atomic_model
&
672 selected_atomic_model (void)
674 return selected_atomic_model_
;
677 static sh_atomic_model
678 parse_validate_atomic_model_option (const char* str
)
680 const char* model_names
[sh_atomic_model::num_models
];
681 model_names
[sh_atomic_model::none
] = "none";
682 model_names
[sh_atomic_model::soft_gusa
] = "soft-gusa";
683 model_names
[sh_atomic_model::hard_llcs
] = "hard-llcs";
684 model_names
[sh_atomic_model::soft_tcb
] = "soft-tcb";
685 model_names
[sh_atomic_model::soft_imask
] = "soft-imask";
687 const char* model_cdef_names
[sh_atomic_model::num_models
];
688 model_cdef_names
[sh_atomic_model::none
] = "NONE";
689 model_cdef_names
[sh_atomic_model::soft_gusa
] = "SOFT_GUSA";
690 model_cdef_names
[sh_atomic_model::hard_llcs
] = "HARD_LLCS";
691 model_cdef_names
[sh_atomic_model::soft_tcb
] = "SOFT_TCB";
692 model_cdef_names
[sh_atomic_model::soft_imask
] = "SOFT_IMASK";
695 ret
.type
= sh_atomic_model::none
;
696 ret
.name
= model_names
[sh_atomic_model::none
];
697 ret
.cdef_name
= model_cdef_names
[sh_atomic_model::none
];
699 ret
.tcb_gbr_offset
= -1;
701 /* Handle empty string as 'none'. */
702 if (str
== NULL
|| *str
== '\0')
705 #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0)
707 std::vector
<std::string
> tokens
;
708 for (std::stringstream
ss (str
); ss
.good (); )
710 tokens
.push_back (std::string ());
711 std::getline (ss
, tokens
.back (), ',');
715 err_ret ("invalid atomic model option");
717 /* The first token must be the atomic model name. */
719 for (size_t i
= 0; i
< sh_atomic_model::num_models
; ++i
)
720 if (tokens
.front () == model_names
[i
])
722 ret
.type
= (sh_atomic_model::enum_type
)i
;
723 ret
.name
= model_names
[i
];
724 ret
.cdef_name
= model_cdef_names
[i
];
728 err_ret ("invalid atomic model name \"%s\"", tokens
.front ().c_str ());
732 /* Go through the remaining tokens. */
733 for (size_t i
= 1; i
< tokens
.size (); ++i
)
735 if (tokens
[i
] == "strict")
737 else if (tokens
[i
].find ("gbr-offset=") == 0)
739 std::string offset_str
= tokens
[i
].substr (strlen ("gbr-offset="));
740 ret
.tcb_gbr_offset
= integral_argument (offset_str
.c_str ());
741 if (offset_str
.empty () || ret
.tcb_gbr_offset
== -1)
742 err_ret ("could not parse gbr-offset value \"%s\" in atomic model "
743 "option", offset_str
.c_str ());
746 err_ret ("unknown parameter \"%s\" in atomic model option",
750 /* Check that the selection makes sense. */
751 if (ret
.type
== sh_atomic_model::soft_gusa
&& !TARGET_SH3
)
752 err_ret ("atomic model %s is only available on SH3 and SH4 targets",
755 if (ret
.type
== sh_atomic_model::hard_llcs
&& !TARGET_SH4A
)
756 err_ret ("atomic model %s is only available on SH4A targets", ret
.name
);
758 if (ret
.type
== sh_atomic_model::soft_tcb
&& ret
.tcb_gbr_offset
== -1)
759 err_ret ("atomic model %s requires gbr-offset parameter", ret
.name
);
761 if (ret
.type
== sh_atomic_model::soft_tcb
762 && (ret
.tcb_gbr_offset
< 0 || ret
.tcb_gbr_offset
> 1020
763 || (ret
.tcb_gbr_offset
& 3) != 0))
764 err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be "
765 "a multiple of 4 in the range 0-1020", ret
.tcb_gbr_offset
,
768 if (ret
.type
== sh_atomic_model::soft_imask
&& TARGET_USERMODE
)
769 err_ret ("cannot use atomic model %s in user mode", ret
.name
);
776 /* Register SH specific RTL passes. */
777 extern opt_pass
* make_pass_sh_treg_combine (gcc::context
* ctx
, bool split_insns
,
779 extern opt_pass
* make_pass_sh_optimize_sett_clrt (gcc::context
* ctx
,
782 register_sh_passes (void)
784 /* Running the sh_treg_combine pass after ce1 generates better code when
785 comparisons are combined and reg-reg moves are introduced, because
786 reg-reg moves will be eliminated afterwards. However, there are quite
787 some cases where combine will be unable to fold comparison related insns,
788 thus for now don't do it.
789 register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"),
790 PASS_POS_INSERT_AFTER, "ce1", 1);
793 /* Run sh_treg_combine pass after combine but before register allocation. */
794 register_pass (make_pass_sh_treg_combine (g
, true, "sh_treg_combine2"),
795 PASS_POS_INSERT_AFTER
, "split1", 1);
797 /* Run sh_treg_combine pass after register allocation and basic block
798 reordering as this sometimes creates new opportunities. */
799 register_pass (make_pass_sh_treg_combine (g
, true, "sh_treg_combine3"),
800 PASS_POS_INSERT_AFTER
, "split4", 1);
802 /* Optimize sett and clrt insns, by e.g. removing them if the T bit value
803 is known after a conditional branch.
804 This must be done after basic blocks and branch conditions have
805 stabilized and won't be changed by further passes. */
806 register_pass (make_pass_sh_optimize_sett_clrt (g
, "sh_optimize_sett_clrt"),
807 PASS_POS_INSERT_BEFORE
, "sched2", 1);
810 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
811 various options, and do some machine dependent initialization. */
813 sh_option_override (void)
817 SUBTARGET_OVERRIDE_OPTIONS
;
819 sh_cpu
= PROCESSOR_SH1
;
820 assembler_dialect
= 0;
822 sh_cpu
= PROCESSOR_SH2
;
824 sh_cpu
= PROCESSOR_SH2E
;
826 sh_cpu
= PROCESSOR_SH2A
;
828 sh_cpu
= PROCESSOR_SH3
;
830 sh_cpu
= PROCESSOR_SH3E
;
833 assembler_dialect
= 1;
834 sh_cpu
= PROCESSOR_SH4
;
838 assembler_dialect
= 1;
839 sh_cpu
= PROCESSOR_SH4A
;
842 /* User/priviledged mode is supported only on SH3* and SH4*.
843 Disable it for everything else. */
844 if (!TARGET_SH3
&& TARGET_USERMODE
)
845 TARGET_USERMODE
= false;
847 if (! strcmp (sh_div_str
, "call-div1"))
848 sh_div_strategy
= SH_DIV_CALL_DIV1
;
849 else if (! strcmp (sh_div_str
, "call-fp") && TARGET_FPU_ANY
)
850 sh_div_strategy
= SH_DIV_CALL_FP
;
851 else if (! strcmp (sh_div_str
, "call-table") && TARGET_DYNSHIFT
)
852 sh_div_strategy
= SH_DIV_CALL_TABLE
;
855 /* Pick one that makes most sense for the target in general.
856 It is not much good to use different functions depending on -Os,
857 since then we'll end up with two different functions when some of
858 the code is compiled for size, and some for speed. */
860 /* SH4 tends to emphasize speed. */
862 sh_div_strategy
= SH_DIV_CALL_TABLE
;
863 /* These have their own way of doing things. */
864 else if (TARGET_SH2A
)
865 sh_div_strategy
= SH_DIV_INTRINSIC
;
866 /* SH1 .. SH3 cores often go into small-footprint systems, so
867 default to the smallest implementation available. */
869 sh_div_strategy
= SH_DIV_CALL_DIV1
;
872 if (sh_divsi3_libfunc
[0])
873 ; /* User supplied - leave it alone. */
874 else if (TARGET_DIVIDE_CALL_FP
)
875 sh_divsi3_libfunc
= "__sdivsi3_i4";
876 else if (TARGET_DIVIDE_CALL_TABLE
)
877 sh_divsi3_libfunc
= "__sdivsi3_i4i";
879 sh_divsi3_libfunc
= "__sdivsi3";
881 if (sh_branch_cost
== -1)
883 /* The SH1 does not have delay slots, hence we get a pipeline stall
884 at every branch. The SH4 is superscalar, so the single delay slot
885 is not sufficient to keep both pipelines filled.
886 In any case, set the default branch cost to '2', as it results in
887 slightly overall smaller code and also enables some if conversions
888 that are required for matching special T bit related insns. */
892 /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */
893 if (! global_options_set
.x_TARGET_ZDCBRANCH
&& TARGET_HARD_SH4
)
894 TARGET_ZDCBRANCH
= 1;
896 /* FDPIC code is a special form of PIC, and the vast majority of code
897 generation constraints that apply to PIC also apply to FDPIC, so we
898 set flag_pic to avoid the need to check TARGET_FDPIC everywhere
899 flag_pic is checked. */
900 if (TARGET_FDPIC
&& !flag_pic
)
903 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
904 if (! VALID_REGISTER_P (regno
))
905 sh_register_names
[regno
][0] = '\0';
907 for (regno
= 0; regno
< ADDREGNAMES_SIZE
; regno
++)
908 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno
)))
909 sh_additional_register_names
[regno
][0] = '\0';
911 if (flag_pic
&& ! TARGET_PREFERGOT
)
912 flag_no_function_cse
= 1;
914 if (targetm
.small_register_classes_for_mode_p (VOIDmode
))
916 /* Never run scheduling before reload, since that can
917 break global alloc, and generates slower code anyway due
918 to the pressure on R0. */
919 /* Enable sched1 for SH4 if the user explicitly requests.
920 When sched1 is enabled, the ready queue will be reordered by
921 the target hooks if pressure is high. We cannot do this for
922 PIC, SH3 and lower as they give spill failures for R0. */
923 if (!TARGET_HARD_SH4
|| flag_pic
)
924 flag_schedule_insns
= 0;
925 /* ??? Current exception handling places basic block boundaries
926 after call_insns. It causes the high pressure on R0 and gives
927 spill failures for R0 in reload. See PR 22553 and the thread
929 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
930 else if (flag_exceptions
)
932 if (flag_schedule_insns
&& global_options_set
.x_flag_schedule_insns
)
933 warning (0, "ignoring %<-fschedule-insns%> because of exception "
935 flag_schedule_insns
= 0;
937 else if (flag_schedule_insns
938 && !global_options_set
.x_flag_schedule_insns
)
939 flag_schedule_insns
= 0;
942 /* Unwind info is not correct around the CFG unless either a frame
943 pointer is present or M_A_O_A is set. Fixing this requires rewriting
944 unwind info generation to be aware of the CFG and propagating states
946 if ((flag_unwind_tables
|| flag_asynchronous_unwind_tables
947 || flag_exceptions
|| flag_non_call_exceptions
)
948 && flag_omit_frame_pointer
&& !TARGET_ACCUMULATE_OUTGOING_ARGS
)
950 warning (0, "unwind tables currently require either a frame pointer "
951 "or %<-maccumulate-outgoing-args%> for correctness");
952 TARGET_ACCUMULATE_OUTGOING_ARGS
= 1;
955 if (flag_unsafe_math_optimizations
)
957 /* Enable fsca insn for SH4A if not otherwise specified by the user. */
958 if (global_options_set
.x_TARGET_FSCA
== 0 && TARGET_SH4A_FP
)
961 /* Enable fsrra insn for SH4A if not otherwise specified by the user. */
962 if (global_options_set
.x_TARGET_FSRRA
== 0 && TARGET_SH4A_FP
)
966 /* Allow fsrra insn only if -funsafe-math-optimizations and
967 -ffinite-math-only is enabled. */
968 TARGET_FSRRA
= TARGET_FSRRA
969 && flag_unsafe_math_optimizations
970 && flag_finite_math_only
;
972 /* If the -mieee option was not explicitly set by the user, turn it on
973 unless -ffinite-math-only was specified. See also PR 33135. */
974 if (! global_options_set
.x_TARGET_IEEE
)
975 TARGET_IEEE
= ! flag_finite_math_only
;
977 if (sh_fixed_range_str
)
978 sh_fix_range (sh_fixed_range_str
);
980 /* This target defaults to strict volatile bitfields. */
981 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
982 flag_strict_volatile_bitfields
= 1;
984 sh_override_options_after_change ();
986 /* Parse atomic model option and make sure it is valid for the current
988 selected_atomic_model_
989 = parse_validate_atomic_model_option (sh_atomic_model_str
);
991 register_sh_passes ();
994 /* Implement targetm.override_options_after_change. */
997 sh_override_options_after_change (void)
999 /* Adjust loop, jump and function alignment values (in bytes), if those
1000 were not specified by the user using -falign-loops, -falign-jumps
1001 and -falign-functions options.
1002 32 bit alignment is better for speed, because instructions can be
1003 fetched as a pair from a longword boundary. For size use 16 bit
1004 alignment to get more compact code.
1005 Aligning all jumps increases the code size, even if it might
1006 result in slightly faster code. Thus, it is set to the smallest
1007 alignment possible if not specified by the user. */
1008 if (flag_align_loops
&& !str_align_loops
)
1009 str_align_loops
= optimize_size
? "2" : "4";
1011 /* Parse values so that we can compare for current value. */
1012 parse_alignment_opts ();
1013 if (flag_align_jumps
&& !str_align_jumps
)
1014 str_align_jumps
= "2";
1015 else if (align_jumps
.levels
[0].get_value () < 2)
1016 str_align_jumps
= "2";
1018 if (flag_align_functions
&& !str_align_functions
)
1019 str_align_functions
= optimize_size
? "2" : "4";
1021 /* The linker relaxation code breaks when a function contains
1022 alignments that are larger than that at the start of a
1023 compilation unit. */
1026 /* Parse values so that we can compare for current value. */
1027 parse_alignment_opts ();
1028 int min_align
= MAX (align_loops
.levels
[0].get_value (),
1029 align_jumps
.levels
[0].get_value ());
1031 /* Also take possible .long constants / mova tables into account. */
1034 if (align_functions
.levels
[0].get_value () < min_align
)
1036 char *r
= XNEWVEC (char, 16);
1037 sprintf (r
, "%d", min_align
);
1038 str_align_functions
= r
;
1043 /* Print the operand address in x to the stream. */
1045 sh_print_operand_address (FILE *stream
, machine_mode
/*mode*/, rtx x
)
1047 switch (GET_CODE (x
))
1051 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
1056 rtx base
= XEXP (x
, 0);
1057 rtx index
= XEXP (x
, 1);
1059 switch (GET_CODE (index
))
1062 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
1063 reg_names
[true_regnum (base
)]);
1069 int base_num
= true_regnum (base
);
1070 int index_num
= true_regnum (index
);
1072 /* If base or index is R0, make sure that it comes first.
1073 Usually one of them will be R0, but the order might be wrong.
1074 If neither base nor index are R0 it's an error and we just
1075 pass it on to the assembler. This avoids silent wrong code
1077 if (base_num
== 0 && index_num
!= 0)
1078 std::swap (base_num
, index_num
);
1080 fprintf (stream
, "@(%s,%s)", reg_names
[index_num
],
1081 reg_names
[base_num
]);
1092 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
1096 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
1100 x
= mark_constant_pool_use (x
);
1101 output_addr_const (stream
, x
);
1106 /* Print operand x (an rtx) in assembler syntax to file stream
1107 according to modifier code.
1109 '.' print a .s if insn needs delay slot
1110 ',' print LOCAL_LABEL_PREFIX
1111 '@' print trap, rte or rts depending upon pragma interruptness
1112 '#' output a nop if there is nothing to put in the delay slot
1113 ''' print likelihood suffix (/u for unlikely).
1114 '>' print branch target if -fverbose-asm
1115 'O' print a constant without the #
1116 'R' print the LSW of a dp value - changes if in little endian
1117 'S' print the MSW of a dp value - changes if in little endian
1118 'T' print the next word of a dp value - same as 'R' in big endian mode.
1119 'M' print .b / .w / .l / .s / .d suffix if operand is a MEM.
1120 'N' print 'r63' if the operand is (const_int 0).
1121 'd' print a V2SF reg as dN instead of fpN.
1122 'm' print a pair `base,offset' or `base,index', for LD and ST.
1123 'U' Likewise for {LD,ST}{HI,LO}.
1124 'V' print the position of a single bit set.
1125 'W' print the position of a single bit cleared.
1126 't' print a memory address which is a register.
1127 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1128 'o' output an operator. */
1130 sh_print_operand (FILE *stream
, rtx x
, int code
)
1141 && ! INSN_ANNULLED_BRANCH_P (final_sequence
->insn (0))
1142 && get_attr_length (final_sequence
->insn (1)))
1143 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
1146 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
1149 trapa_attr
= lookup_attribute ("trap_exit",
1150 DECL_ATTRIBUTES (current_function_decl
));
1152 fprintf (stream
, "trapa #%ld",
1153 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr
))));
1154 else if (sh_cfun_interrupt_handler_p ())
1156 if (sh_cfun_resbank_handler_p ())
1157 fprintf (stream
, "resbank\n");
1158 fprintf (stream
, "rte");
1161 fprintf (stream
, "rts");
1164 /* Output a nop if there's nothing in the delay slot. */
1165 if (dbr_sequence_length () == 0)
1166 fprintf (stream
, "\n\tnop");
1170 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1173 && profile_probability::from_reg_br_prob_note (XINT (note
, 0))
1174 < profile_probability::even ())
1175 fputs ("/u", stream
);
1179 if (flag_verbose_asm
&& JUMP_LABEL (current_output_insn
))
1181 fputs ("\t! target: ", stream
);
1182 output_addr_const (stream
, JUMP_LABEL (current_output_insn
));
1186 x
= mark_constant_pool_use (x
);
1187 output_addr_const (stream
, x
);
1189 /* N.B.: %R / %S / %T adjust memory addresses by four.
1190 While they can be used to access 64 bit parts of a larger value
1191 held in general purpose registers, that won't work with memory -
1192 neither for fp registers, since the frxx names are used. */
1194 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1196 regno
= true_regnum (x
);
1197 regno
+= FP_REGISTER_P (regno
) ? 1 : SH_REG_LSW_OFFSET
;
1198 fputs (reg_names
[regno
], (stream
));
1202 x
= adjust_address (x
, SImode
, 4 * SH_REG_LSW_OFFSET
);
1203 sh_print_operand_address (stream
, GET_MODE (x
), XEXP (x
, 0));
1209 mode
= GET_MODE (x
);
1210 if (mode
== VOIDmode
)
1212 if (GET_MODE_SIZE (mode
) >= 8)
1213 sub
= simplify_subreg (SImode
, x
, mode
, 4 * SH_REG_LSW_OFFSET
);
1215 sh_print_operand (stream
, sub
, 0);
1217 output_operand_lossage ("invalid operand to %%R");
1221 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1223 regno
= true_regnum (x
);
1224 regno
+= FP_REGISTER_P (regno
) ? 0 : SH_REG_MSW_OFFSET
;
1225 fputs (reg_names
[regno
], (stream
));
1229 x
= adjust_address (x
, SImode
, 4 * SH_REG_MSW_OFFSET
);
1230 sh_print_operand_address (stream
, GET_MODE (x
), XEXP (x
, 0));
1236 mode
= GET_MODE (x
);
1237 if (mode
== VOIDmode
)
1239 if (GET_MODE_SIZE (mode
) >= 8)
1240 sub
= simplify_subreg (SImode
, x
, mode
, 4 * SH_REG_MSW_OFFSET
);
1242 sh_print_operand (stream
, sub
, 0);
1244 output_operand_lossage ("invalid operand to %%S");
1248 /* Next word of a double. */
1249 switch (GET_CODE (x
))
1252 fputs (reg_names
[REGNO (x
) + 1], (stream
));
1256 machine_mode mode
= GET_MODE (x
);
1257 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
1258 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
1259 x
= adjust_address (x
, SImode
, 4);
1260 sh_print_operand_address (stream
, mode
, XEXP (x
, 0));
1269 gcc_assert (MEM_P (x
));
1271 switch (GET_CODE (x
))
1275 sh_print_operand (stream
, x
, 0);
1283 switch (GET_CODE (x
))
1285 case PLUS
: fputs ("add", stream
); break;
1286 case MINUS
: fputs ("sub", stream
); break;
1287 case MULT
: fputs ("mul", stream
); break;
1288 case DIV
: fputs ("div", stream
); break;
1289 case EQ
: fputs ("eq", stream
); break;
1290 case NE
: fputs ("ne", stream
); break;
1291 case GT
: case LT
: fputs ("gt", stream
); break;
1292 case GE
: case LE
: fputs ("ge", stream
); break;
1293 case GTU
: case LTU
: fputs ("gtu", stream
); break;
1294 case GEU
: case LEU
: fputs ("geu", stream
); break;
1302 switch (GET_MODE (x
))
1304 case E_QImode
: fputs (".b", stream
); break;
1305 case E_HImode
: fputs (".w", stream
); break;
1306 case E_SImode
: fputs (".l", stream
); break;
1307 case E_SFmode
: fputs (".s", stream
); break;
1308 case E_DFmode
: fputs (".d", stream
); break;
1309 default: gcc_unreachable ();
1315 gcc_assert (MEM_P (x
));
1319 switch (GET_CODE (x
))
1323 sh_print_operand (stream
, x
, 0);
1324 fputs (", 0", stream
);
1328 sh_print_operand (stream
, XEXP (x
, 0), 0);
1329 fputs (", ", stream
);
1330 sh_print_operand (stream
, XEXP (x
, 1), 0);
1340 int num
= exact_log2 (INTVAL (x
));
1341 gcc_assert (num
>= 0);
1342 fprintf (stream
, "#%d", num
);
1348 int num
= exact_log2 (~INTVAL (x
));
1349 gcc_assert (num
>= 0);
1350 fprintf (stream
, "#%d", num
);
1355 gcc_assert (REG_P (x
) && GET_MODE (x
) == V2SFmode
);
1357 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
1361 if (x
== CONST0_RTX (GET_MODE (x
)))
1363 fprintf ((stream
), "r63");
1366 goto default_output
;
1368 if (CONST_INT_P (x
))
1370 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
1378 mode
= GET_MODE (x
);
1380 switch (GET_CODE (x
))
1384 rtx inner
= XEXP (x
, 0);
1386 machine_mode inner_mode
;
1388 /* We might see SUBREGs with vector mode registers inside. */
1389 if (GET_CODE (inner
) == SUBREG
1390 && (GET_MODE_SIZE (GET_MODE (inner
))
1391 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1392 && subreg_lowpart_p (inner
))
1393 inner
= SUBREG_REG (inner
);
1394 if (CONST_INT_P (inner
))
1396 x
= GEN_INT (trunc_int_for_mode (INTVAL (inner
), GET_MODE (x
)));
1397 goto default_output
;
1399 inner_mode
= GET_MODE (inner
);
1400 if (GET_CODE (inner
) == SUBREG
1401 && (GET_MODE_SIZE (GET_MODE (inner
))
1402 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1403 && REG_P (SUBREG_REG (inner
)))
1405 offset
= subreg_regno_offset (REGNO (SUBREG_REG (inner
)),
1406 GET_MODE (SUBREG_REG (inner
)),
1407 SUBREG_BYTE (inner
),
1409 inner
= SUBREG_REG (inner
);
1411 if (!REG_P (inner
) || GET_MODE_SIZE (inner_mode
) > 8)
1413 /* Floating point register pairs are always big endian;
1414 general purpose registers are 64 bit wide. */
1415 regno
= REGNO (inner
);
1416 regno
= (hard_regno_nregs (regno
, inner_mode
)
1417 - hard_regno_nregs (regno
, mode
))
1426 gcc_assert (SUBREG_BYTE (x
) == 0
1427 && REG_P (SUBREG_REG (x
)));
1435 if (FP_REGISTER_P (regno
)
1436 && mode
== V16SFmode
)
1437 fprintf ((stream
), "mtrx%s", reg_names
[regno
] + 2);
1438 else if (FP_REGISTER_P (REGNO (x
))
1439 && mode
== V4SFmode
)
1440 fprintf ((stream
), "fv%s", reg_names
[regno
] + 2);
1442 && mode
== V2SFmode
)
1443 fprintf ((stream
), "fp%s", reg_names
[regno
] + 2);
1444 else if (FP_REGISTER_P (REGNO (x
))
1445 && GET_MODE_SIZE (mode
) > 4)
1446 fprintf ((stream
), "d%s", reg_names
[regno
] + 1);
1448 fputs (reg_names
[regno
], (stream
));
1452 output_address (GET_MODE (x
), XEXP (x
, 0));
1456 fputc ('#', stream
);
1457 output_addr_const (stream
, x
);
1465 sh_print_operand_punct_valid_p (unsigned char code
)
1467 return (code
== '.' || code
== '#' || code
== '@' || code
== ','
1468 || code
== '$' || code
== '\'' || code
== '>');
1471 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1473 sh_asm_output_addr_const_extra (FILE *file
, rtx x
)
1475 if (GET_CODE (x
) == UNSPEC
)
1477 switch (XINT (x
, 1))
1480 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1481 output_addr_const (file
, XVECEXP (x
, 0, 0));
1484 output_addr_const (file
, XVECEXP (x
, 0, 0));
1485 fputs ("@GOT", file
);
1488 output_addr_const (file
, XVECEXP (x
, 0, 0));
1489 fputs ("@GOTOFF", file
);
1492 output_addr_const (file
, XVECEXP (x
, 0, 0));
1493 fputs ("@PLT", file
);
1496 output_addr_const (file
, XVECEXP (x
, 0, 0));
1497 fputs ("@GOTPLT", file
);
1500 output_addr_const (file
, XVECEXP (x
, 0, 0));
1501 fputs ("@PCREL", file
);
1504 output_addr_const (file
, XVECEXP (x
, 0, 0));
1505 fputs ("@DTPOFF", file
);
1507 case UNSPEC_GOTTPOFF
:
1508 output_addr_const (file
, XVECEXP (x
, 0, 0));
1509 fputs ("@GOTTPOFF", file
);
1512 output_addr_const (file
, XVECEXP (x
, 0, 0));
1513 fputs ("@TPOFF", file
);
1518 /* LPCS stands for Label for PIC Call Site. */
1519 targetm
.asm_out
.generate_internal_label (name
, "LPCS",
1520 INTVAL (XVECEXP (x
, 0, 0)));
1521 assemble_name (file
, name
);
1525 output_addr_const (file
, XVECEXP (x
, 0, 0));
1527 if (GET_CODE (XVECEXP (x
, 0, 1)) == CONST
)
1530 output_addr_const (file
, XVECEXP (x
, 0, 1));
1534 output_addr_const (file
, XVECEXP (x
, 0, 1));
1536 case UNSPEC_PCREL_SYMOFF
:
1537 output_addr_const (file
, XVECEXP (x
, 0, 0));
1539 output_addr_const (file
, XVECEXP (x
, 0, 1));
1540 fputs ("-.)", file
);
1542 case UNSPEC_GOTFUNCDESC
:
1543 output_addr_const (file
, XVECEXP (x
, 0, 0));
1544 fputs ("@GOTFUNCDESC", file
);
1546 case UNSPEC_GOTOFFFUNCDESC
:
1547 output_addr_const (file
, XVECEXP (x
, 0, 0));
1548 fputs ("@GOTOFFFUNCDESC", file
);
1559 /* Encode symbol attributes of a SYMBOL_REF into its
1560 SYMBOL_REF_FLAGS. */
1562 sh_encode_section_info (tree decl
, rtx rtl
, int first
)
1564 default_encode_section_info (decl
, rtl
, first
);
1566 if (TREE_CODE (decl
) == FUNCTION_DECL
1567 && sh2a_function_vector_p (decl
) && TARGET_SH2A
)
1568 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
1571 /* Prepare operands for a move define_expand; specifically, one of the
1572 operands must be in a register. */
1574 prepare_move_operands (rtx operands
[], machine_mode mode
)
1576 if ((mode
== SImode
|| mode
== DImode
)
1578 && ! ((mode
== Pmode
|| mode
== ptr_mode
)
1579 && tls_symbolic_operand (operands
[1], Pmode
) != TLS_MODEL_NONE
))
1582 if (SYMBOLIC_CONST_P (operands
[1]))
1584 if (MEM_P (operands
[0]))
1585 operands
[1] = force_reg (Pmode
, operands
[1]);
1588 temp
= (!can_create_pseudo_p ()
1590 : gen_reg_rtx (Pmode
));
1591 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
1594 else if (GET_CODE (operands
[1]) == CONST
1595 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1596 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
1598 temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
1599 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
1601 operands
[1] = expand_binop (mode
, add_optab
, temp
,
1602 XEXP (XEXP (operands
[1], 0), 1),
1603 (!can_create_pseudo_p ()
1605 : gen_reg_rtx (Pmode
)),
1606 0, OPTAB_LIB_WIDEN
);
1610 if (! reload_in_progress
&& ! reload_completed
)
1612 /* Copy the source to a register if both operands aren't registers. */
1613 if (! register_operand (operands
[0], mode
)
1614 && ! register_operand (operands
[1], mode
))
1615 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1617 if (MEM_P (operands
[0]) && ! memory_operand (operands
[0], mode
))
1619 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1620 except that we can't use that function because it is static. */
1621 rtx new_rtx
= change_address (operands
[0], mode
, 0);
1622 MEM_COPY_ATTRIBUTES (new_rtx
, operands
[0]);
1623 operands
[0] = new_rtx
;
1626 /* This case can happen while generating code to move the result
1627 of a library call to the target. Reject `st r0,@(rX,rY)' because
1628 reload will fail to find a spill register for rX, since r0 is already
1629 being used for the source. */
1630 else if (refers_to_regno_p (R0_REG
, operands
[1])
1631 && MEM_P (operands
[0])
1632 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
1633 && REG_P (XEXP (XEXP (operands
[0], 0), 1)))
1634 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1636 /* When the displacement addressing is used, RA will assign r0 to
1637 the pseudo register operand for the QI/HImode load/store.
1638 This tends to make a long live range for R0 and might cause
1639 anomalous register spills in some case with LRA. See PR
1641 We split possible load/store to two move insns via r0 so as to
1642 shorten R0 live range. It will make some codes worse but will
1643 win on average for LRA.
1644 Also when base+index addressing is used and the index term is
1645 a subreg, LRA assumes that more hard registers can be available
1646 in some situation. It isn't the case for SH in the problematic
1647 case. We can pre-allocate R0 for that index term to avoid
1648 the issue. See PR target/66591. */
1649 else if (sh_lra_p ()
1651 && ((REG_P (operands
[0]) && MEM_P (operands
[1]))
1652 || (REG_P (operands
[1]) && MEM_P (operands
[0]))))
1654 bool load_p
= REG_P (operands
[0]);
1655 rtx reg
= operands
[load_p
? 0 : 1];
1656 rtx adr
= XEXP (operands
[load_p
? 1 : 0], 0);
1658 if ((mode
== QImode
|| mode
== HImode
)
1659 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1660 && GET_CODE (adr
) == PLUS
1661 && REG_P (XEXP (adr
, 0))
1662 && (REGNO (XEXP (adr
, 0)) >= FIRST_PSEUDO_REGISTER
)
1663 && CONST_INT_P (XEXP (adr
, 1))
1664 && INTVAL (XEXP (adr
, 1)) != 0
1665 && sh_legitimate_index_p (mode
, XEXP (adr
, 1), false, true))
1667 rtx r0_rtx
= gen_rtx_REG (mode
, R0_REG
);
1668 emit_move_insn (r0_rtx
, operands
[1]);
1669 operands
[1] = r0_rtx
;
1671 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1672 && GET_CODE (adr
) == PLUS
1673 && REG_P (XEXP (adr
, 0))
1674 && (REGNO (XEXP (adr
, 0)) >= FIRST_PSEUDO_REGISTER
)
1675 && SUBREG_P (XEXP (adr
, 1))
1676 && REG_P (SUBREG_REG (XEXP (adr
, 1))))
1678 rtx r0_rtx
= gen_rtx_REG (GET_MODE (XEXP (adr
, 1)), R0_REG
);
1679 emit_move_insn (r0_rtx
, XEXP (adr
, 1));
1680 XEXP (adr
, 1) = r0_rtx
;
1685 if (mode
== Pmode
|| mode
== ptr_mode
)
1687 rtx op0
= operands
[0];
1688 rtx op1
= operands
[1];
1690 if (GET_CODE (op1
) == CONST
1691 && GET_CODE (XEXP (op1
, 0)) == PLUS
1692 && (tls_symbolic_operand (XEXP (XEXP (op1
, 0), 0), Pmode
)
1695 opc
= XEXP (XEXP (op1
, 0), 1);
1696 op1
= XEXP (XEXP (op1
, 0), 0);
1701 enum tls_model tls_kind
;
1703 if (! reload_in_progress
&& ! reload_completed
1704 && (tls_kind
= tls_symbolic_operand (op1
, Pmode
)) != TLS_MODEL_NONE
)
1706 rtx tga_op1
, tga_ret
, tmp
, tmp2
;
1709 && (tls_kind
== TLS_MODEL_GLOBAL_DYNAMIC
1710 || tls_kind
== TLS_MODEL_LOCAL_DYNAMIC
1711 || tls_kind
== TLS_MODEL_INITIAL_EXEC
))
1713 static int got_labelno
;
1714 /* Don't schedule insns for getting GOT address when
1715 the first scheduling is enabled, to avoid spill
1717 if (flag_schedule_insns
)
1718 emit_insn (gen_blockage ());
1719 emit_insn (gen_GOTaddr2picreg (GEN_INT (++got_labelno
)));
1720 emit_use (gen_rtx_REG (SImode
, PIC_REG
));
1721 if (flag_schedule_insns
)
1722 emit_insn (gen_blockage ());
1727 case TLS_MODEL_GLOBAL_DYNAMIC
:
1728 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1730 emit_move_insn (gen_rtx_REG (Pmode
, PIC_REG
),
1731 sh_get_fdpic_reg_initial_val ());
1732 emit_call_insn (gen_tls_global_dynamic (tga_ret
, op1
));
1733 tmp
= gen_reg_rtx (Pmode
);
1734 emit_move_insn (tmp
, tga_ret
);
1738 case TLS_MODEL_LOCAL_DYNAMIC
:
1739 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1741 emit_move_insn (gen_rtx_REG (Pmode
, PIC_REG
),
1742 sh_get_fdpic_reg_initial_val ());
1743 emit_call_insn (gen_tls_local_dynamic (tga_ret
, op1
));
1745 tmp
= gen_reg_rtx (Pmode
);
1746 emit_move_insn (tmp
, tga_ret
);
1748 if (register_operand (op0
, Pmode
))
1751 tmp2
= gen_reg_rtx (Pmode
);
1753 emit_insn (gen_symDTPOFF2reg (tmp2
, op1
, tmp
));
1757 case TLS_MODEL_INITIAL_EXEC
:
1758 tga_op1
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (Pmode
);
1759 tmp
= gen_sym2GOTTPOFF (op1
);
1761 emit_move_insn (gen_rtx_REG (Pmode
, PIC_REG
),
1762 sh_get_fdpic_reg_initial_val ());
1763 emit_insn (gen_tls_initial_exec (tga_op1
, tmp
));
1767 case TLS_MODEL_LOCAL_EXEC
:
1768 tmp2
= gen_reg_rtx (Pmode
);
1769 emit_insn (gen_store_gbr (tmp2
));
1770 tmp
= gen_reg_rtx (Pmode
);
1771 emit_insn (gen_symTPOFF2reg (tmp
, op1
));
1773 if (register_operand (op0
, Pmode
))
1776 op1
= gen_reg_rtx (Pmode
);
1778 emit_insn (gen_addsi3 (op1
, tmp
, tmp2
));
1785 emit_insn (gen_addsi3 (op1
, op1
, force_reg (SImode
, opc
)));
1790 if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1793 split_const (operands
[1], &base
, &offset
);
1795 if (GET_CODE (base
) == SYMBOL_REF
1796 && !offset_within_block_p (base
, INTVAL (offset
)))
1798 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx (mode
) : operands
[0];
1799 emit_move_insn (tmp
, base
);
1800 if (!arith_operand (offset
, mode
))
1801 offset
= force_reg (mode
, offset
);
1802 emit_insn (gen_add3_insn (operands
[0], tmp
, offset
));
1807 /* Implement the canonicalize_comparison target hook for the combine
1808 pass. For the target hook this function is invoked via
1809 sh_canonicalize_comparison. This function is also re-used to
1810 canonicalize comparisons in cbranch pattern expanders. */
1812 sh_canonicalize_comparison (enum rtx_code
& cmp
, rtx
& op0
, rtx
& op1
,
1814 bool op0_preserve_value
)
1816 /* When invoked from within the combine pass the mode is not specified,
1817 so try to get it from one of the operands. */
1818 if (mode
== VOIDmode
)
1819 mode
= GET_MODE (op0
);
1820 if (mode
== VOIDmode
)
1821 mode
= GET_MODE (op1
);
1823 // We need to have a mode to do something useful here.
1824 if (mode
== VOIDmode
)
1827 // Currently, we don't deal with floats here.
1828 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1831 // Make sure that the constant operand is the second operand.
1832 if (CONST_INT_P (op0
) && !CONST_INT_P (op1
))
1834 if (op0_preserve_value
)
1837 std::swap (op0
, op1
);
1838 cmp
= swap_condition (cmp
);
1841 if (CONST_INT_P (op1
))
1843 /* Try to adjust the constant operand in such a way that available
1844 comparison insns can be utilized better and the constant can be
1845 loaded with a 'mov #imm,Rm' insn. This avoids a load from the
1847 const HOST_WIDE_INT val
= INTVAL (op1
);
1849 /* x > -1 --> x >= 0
1850 x > 0xFFFFFF7F --> x >= 0xFFFFFF80
1852 x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */
1853 if ((val
== -1 || val
== -0x81) && (cmp
== GT
|| cmp
== LE
))
1855 cmp
= cmp
== GT
? GE
: LT
;
1856 op1
= gen_int_mode (val
+ 1, mode
);
1860 x >= 0x80 --> x > 0x7F
1862 x < 0x80 --> x <= 0x7F */
1863 else if ((val
== 1 || val
== 0x80) && (cmp
== GE
|| cmp
== LT
))
1865 cmp
= cmp
== GE
? GT
: LE
;
1866 op1
= gen_int_mode (val
- 1, mode
);
1869 /* unsigned x >= 1 --> x != 0
1870 unsigned x < 1 --> x == 0 */
1871 else if (val
== 1 && (cmp
== GEU
|| cmp
== LTU
))
1873 cmp
= cmp
== GEU
? NE
: EQ
;
1874 op1
= CONST0_RTX (mode
);
1877 /* unsigned x >= 0x80 --> unsigned x > 0x7F
1878 unsigned x < 0x80 --> unsigned x < 0x7F */
1879 else if (val
== 0x80 && (cmp
== GEU
|| cmp
== LTU
))
1881 cmp
= cmp
== GEU
? GTU
: LEU
;
1882 op1
= gen_int_mode (val
- 1, mode
);
1885 /* unsigned x > 0 --> x != 0
1886 unsigned x <= 0 --> x == 0 */
1887 else if (val
== 0 && (cmp
== GTU
|| cmp
== LEU
))
1888 cmp
= cmp
== GTU
? NE
: EQ
;
1890 /* unsigned x > 0x7FFFFFFF --> signed x < 0
1891 unsigned x <= 0x7FFFFFFF --> signed x >= 0 */
1892 else if (mode
== SImode
&& (cmp
== GTU
|| cmp
== LEU
)
1893 && val
== 0x7FFFFFFF)
1895 cmp
= cmp
== GTU
? LT
: GE
;
1899 /* unsigned x >= 0x80000000 --> signed x < 0
1900 unsigned x < 0x80000000 --> signed x >= 0 */
1901 else if (mode
== SImode
&& (cmp
== GEU
|| cmp
== LTU
)
1902 && (unsigned HOST_WIDE_INT
)val
1903 == ((unsigned HOST_WIDE_INT
)0x7FFFFFFF + 1))
1905 cmp
= cmp
== GEU
? LT
: GE
;
1911 /* This function implements the canonicalize_comparison target hook.
1912 This wrapper around the internally used sh_canonicalize_comparison
1913 function is needed to do the enum rtx_code <-> int conversion.
1914 Target hooks cannot use enum rtx_code in its definition. */
1916 sh_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
1917 bool op0_preserve_value
)
1919 enum rtx_code tmp_code
= (enum rtx_code
)*code
;
1920 sh_canonicalize_comparison (tmp_code
, *op0
, *op1
,
1921 VOIDmode
, op0_preserve_value
);
1922 *code
= (int)tmp_code
;
1925 /* This function implements the legitimate_combined_insn target hook,
1926 which the combine pass uses to early reject combined insns, before
1927 it tries to recog the insn and determine its cost. */
1929 sh_legitimate_combined_insn (rtx_insn
* insn
)
1931 /* Reject combinations of memory loads and zero extensions, as these
1932 interfere with other combine patterns such as zero extracts and bit
1933 tests. The SH2A movu.{b|w} insns are formed later in the
1934 'sh_optimize_extu_exts' pass after combine/split1. */
1935 rtx p
= PATTERN (insn
);
1936 if (GET_CODE (p
) == SET
1937 && REG_P (XEXP (p
, 0)) && GET_MODE (XEXP (p
, 0)) == SImode
1938 && GET_CODE (XEXP (p
, 1)) == ZERO_EXTEND
1939 && MEM_P (XEXP (XEXP (p
, 1), 0)))
1946 sh_fixed_condition_code_regs (unsigned int* p1
, unsigned int* p2
)
1949 *p2
= INVALID_REGNUM
;
1953 /* Try to calculate the branch distance of a conditional branch in bytes.
1955 FIXME: Because of PR 59189 we can't use the CFG here. Instead just
1956 walk from this insn into the next (fall-through) basic block and see if
1957 we hit the label. */
1959 sh_cbranch_distance (rtx_insn
* _cbranch_insn
, unsigned int max_dist
)
1961 rtx_jump_insn
* cbranch_insn
= safe_as_a
<rtx_jump_insn
*> (_cbranch_insn
);
1965 fprintf (dump_file
, "sh_cbranch_distance insn = \n");
1966 print_rtl_single (dump_file
, cbranch_insn
);
1969 unsigned int dist
= 0;
1971 for (rtx_insn
* i
= next_nonnote_insn (cbranch_insn
);
1972 i
!= NULL
&& dist
< max_dist
; i
= next_nonnote_insn (i
))
1974 const unsigned int i_len
= get_attr_length (i
);
1978 fprintf (dump_file
, " insn %d length = %u dist = %u\n",
1979 INSN_UID (i
), i_len
, dist
);
1981 if (rtx_code_label
* l
= dyn_cast
<rtx_code_label
*> (i
))
1983 if (l
== cbranch_insn
->jump_target ())
1986 fprintf (dump_file
, " cbranch dist = %u\n", dist
);
1994 fprintf (dump_file
, " cbranch dist = unknown\n");
1996 return unknown_cbranch_distance
;
2000 prepare_cbranch_operands (rtx
*operands
, machine_mode mode
,
2001 enum rtx_code comparison
)
2003 gcc_assert (can_create_pseudo_p ());
2005 if (comparison
== LAST_AND_UNUSED_RTX_CODE
)
2006 comparison
= GET_CODE (operands
[0]);
2008 sh_canonicalize_comparison (comparison
, operands
[1], operands
[2],
2011 rtx op1
= operands
[1];
2012 operands
[1] = force_reg (mode
, op1
);
2014 /* When we are handling DImode comparisons, we want to keep constants so
2015 that we can optimize the component comparisons; however, memory loads
2016 are better issued as a whole so that they can be scheduled well.
2017 SImode equality comparisons allow I08 constants, but only when they
2018 compare r0. Hence, if operands[1] has to be loaded from somewhere else
2019 into a register, that register might as well be r0, and we allow the
2020 constant. If it is already in a register, this is likely to be
2021 allocated to a different hard register, thus we load the constant into
2022 a register unless it is zero. */
2023 if (!REG_P (operands
[2])
2024 && (!CONST_INT_P (operands
[2])
2025 || (mode
== SImode
&& operands
[2] != CONST0_RTX (SImode
)
2026 && ((comparison
!= EQ
&& comparison
!= NE
)
2027 || (REG_P (op1
) && REGNO (op1
) != R0_REG
)
2028 || !satisfies_constraint_I08 (operands
[2])))))
2029 operands
[2] = force_reg (mode
, operands
[2]);
2035 expand_cbranchsi4 (rtx
*operands
, enum rtx_code comparison
,
2036 profile_probability probability
)
2038 rtx (*branch_expander
) (rtx
) = gen_branch_true
;
2039 comparison
= prepare_cbranch_operands (operands
, SImode
, comparison
);
2042 case NE
: case LT
: case LE
: case LTU
: case LEU
:
2043 comparison
= reverse_condition (comparison
);
2044 branch_expander
= gen_branch_false
;
2047 emit_insn (gen_rtx_SET (get_t_reg_rtx (),
2048 gen_rtx_fmt_ee (comparison
, SImode
,
2049 operands
[1], operands
[2])));
2050 rtx_insn
*jump
= emit_jump_insn (branch_expander (operands
[3]));
2051 if (probability
.initialized_p ())
2052 add_reg_br_prob_note (jump
, probability
);
2056 expand_cbranchsi4 (rtx
*operands
, enum rtx_code comparison
)
2058 expand_cbranchsi4 (operands
, comparison
,
2059 profile_probability::uninitialized ());
2062 /* ??? How should we distribute probabilities when more than one branch
2063 is generated. So far we only have some ad-hoc observations:
2064 - If the operands are random, they are likely to differ in both parts.
2065 - If comparing items in a hash chain, the operands are random or equal;
2066 operation should be EQ or NE.
2067 - If items are searched in an ordered tree from the root, we can expect
2068 the highpart to be unequal about half of the time; operation should be
2069 an inequality comparison, operands non-constant, and overall probability
2070 about 50%. Likewise for quicksort.
2071 - Range checks will be often made against constants. Even if we assume for
2072 simplicity an even distribution of the non-constant operand over a
2073 sub-range here, the same probability could be generated with differently
2074 wide sub-ranges - as long as the ratio of the part of the subrange that
2075 is before the threshold to the part that comes after the threshold stays
2076 the same. Thus, we can't really tell anything here;
2077 assuming random distribution is at least simple.
2080 expand_cbranchdi4 (rtx
*operands
, enum rtx_code comparison
)
2082 enum rtx_code msw_taken
, msw_skip
, lsw_taken
;
2083 rtx_code_label
*skip_label
= NULL
;
2084 rtx op1h
, op1l
, op2h
, op2l
;
2086 profile_probability prob
, rev_prob
;
2087 profile_probability msw_taken_prob
= profile_probability::uninitialized (),
2088 msw_skip_prob
= profile_probability::uninitialized (),
2089 lsw_taken_prob
= profile_probability::uninitialized ();
2091 comparison
= prepare_cbranch_operands (operands
, DImode
, comparison
);
2092 op1h
= gen_highpart_mode (SImode
, DImode
, operands
[1]);
2093 op2h
= gen_highpart_mode (SImode
, DImode
, operands
[2]);
2094 op1l
= gen_lowpart (SImode
, operands
[1]);
2095 op2l
= gen_lowpart (SImode
, operands
[2]);
2096 msw_taken
= msw_skip
= lsw_taken
= LAST_AND_UNUSED_RTX_CODE
;
2097 prob
= split_branch_probability
;
2098 rev_prob
= prob
.invert ();
2104 if (prob
.initialized_p ())
2106 /* FIXME: This is not optimal. We do not really know the probablity
2107 that values differ by MCW only, but we should probably distribute
2108 probabilities more evenly. */
2109 msw_skip_prob
= rev_prob
;
2110 lsw_taken_prob
= prob
> profile_probability::never ()
2111 ? profile_probability::guessed_always ()
2112 : profile_probability::guessed_never ();
2117 msw_taken_prob
= prob
;
2119 lsw_taken_prob
= profile_probability::guessed_never ();
2122 msw_taken
= comparison
;
2123 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
2125 if (comparison
!= GTU
|| op2h
!= CONST0_RTX (SImode
))
2126 msw_skip
= swap_condition (msw_taken
);
2130 if (op2l
== CONST0_RTX (SImode
))
2131 msw_taken
= comparison
;
2134 msw_taken
= comparison
== GE
? GT
: GTU
;
2135 msw_skip
= swap_condition (msw_taken
);
2140 msw_taken
= comparison
;
2141 if (op2l
== CONST0_RTX (SImode
))
2143 msw_skip
= swap_condition (msw_taken
);
2147 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
2148 msw_taken
= comparison
;
2152 if (comparison
== LE
)
2154 else if (op2h
!= CONST0_RTX (SImode
))
2158 msw_skip
= swap_condition (LTU
);
2161 msw_skip
= swap_condition (msw_taken
);
2164 default: return false;
2166 num_branches
= ((msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2167 + (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2168 + (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
));
2169 if (comparison
!= EQ
&& comparison
!= NE
&& num_branches
> 1)
2171 if (!CONSTANT_P (operands
[2])
2172 && prob
.initialized_p ()
2173 && prob
.to_reg_br_prob_base () >= (int) (REG_BR_PROB_BASE
* 3 / 8U)
2174 && prob
.to_reg_br_prob_base () <= (int) (REG_BR_PROB_BASE
* 5 / 8U))
2176 msw_taken_prob
= prob
.apply_scale (1, 2);
2177 msw_skip_prob
= rev_prob
.apply_scale (REG_BR_PROB_BASE
,
2178 rev_prob
.to_reg_br_prob_base ()
2179 + REG_BR_PROB_BASE
);
2180 lsw_taken_prob
= prob
;
2184 msw_taken_prob
= prob
;
2185 msw_skip_prob
= profile_probability::guessed_always ();
2186 /* ??? If we have a constant op2h, should we use that when
2187 calculating lsw_taken_prob? */
2188 lsw_taken_prob
= prob
;
2194 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2195 expand_cbranchsi4 (operands
, msw_taken
, msw_taken_prob
);
2196 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2198 rtx taken_label
= operands
[3];
2200 /* Operands were possibly modified, but msw_skip doesn't expect this.
2201 Always use the original ones. */
2202 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2208 operands
[3] = skip_label
= gen_label_rtx ();
2209 expand_cbranchsi4 (operands
, msw_skip
, msw_skip_prob
);
2210 operands
[3] = taken_label
;
2214 if (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2215 expand_cbranchsi4 (operands
, lsw_taken
, lsw_taken_prob
);
2216 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2217 emit_label (skip_label
);
2221 /* Given an operand, return 1 if the evaluated operand plugged into an
2222 if_then_else will result in a branch_true, 0 if branch_false, or
2223 -1 if neither nor applies. The truth table goes like this:
2225 op | cmpval | code | result
2226 ---------+--------+---------+--------------------
2227 T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1)
2228 T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1)
2229 T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0)
2230 T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0)
2231 !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1)
2232 !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1)
2233 !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0)
2234 !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */
2236 sh_eval_treg_value (rtx op
)
2238 if (t_reg_operand (op
, GET_MODE (op
)))
2240 if (negt_reg_operand (op
, GET_MODE (op
)))
2243 rtx_code code
= GET_CODE (op
);
2244 if ((code
!= EQ
&& code
!= NE
) || !CONST_INT_P (XEXP (op
, 1)))
2247 int cmpop
= code
== EQ
? 1 : 0;
2248 int cmpval
= INTVAL (XEXP (op
, 1));
2249 if (cmpval
!= 0 && cmpval
!= 1)
2253 if (t_reg_operand (XEXP (op
, 0), GET_MODE (XEXP (op
, 0))))
2255 else if (negt_reg_operand (XEXP (op
, 0), GET_MODE (XEXP (op
, 0))))
2260 return t
^ (cmpval
== cmpop
);
2263 /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case
2264 of floating-point comparisons. */
2266 sh_emit_set_t_insn (rtx insn
, machine_mode mode
)
2268 if (TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
2269 && GET_CODE (insn
) != PARALLEL
)
2271 insn
= gen_rtx_PARALLEL (VOIDmode
,
2273 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, FPSCR_STAT_REG
)),
2274 gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, FPSCR_MODES_REG
))));
2279 /* Prepare the operands for an scc instruction; make sure that the
2280 compare has been done and the result is in T_REG. */
2282 sh_emit_scc_to_t (enum rtx_code code
, rtx op0
, rtx op1
)
2284 rtx t_reg
= get_t_reg_rtx ();
2285 enum rtx_code oldcode
= code
;
2287 /* First need a compare insn. */
2291 /* It isn't possible to handle this case. */
2308 if (code
!= oldcode
)
2309 std::swap (op0
, op1
);
2311 machine_mode mode
= GET_MODE (op0
);
2312 if (mode
== VOIDmode
)
2313 mode
= GET_MODE (op1
);
2315 op0
= force_reg (mode
, op0
);
2316 if ((code
!= EQ
&& code
!= NE
2317 && (op1
!= const0_rtx
2318 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2319 || (mode
== DImode
&& op1
!= const0_rtx
)
2320 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2321 op1
= force_reg (mode
, op1
);
2323 sh_emit_set_t_insn (gen_rtx_SET (t_reg
,
2324 gen_rtx_fmt_ee (code
, SImode
, op0
, op1
)),
2328 /* Called from the md file, set up the operands of a compare instruction. */
2330 sh_emit_compare_and_branch (rtx
*operands
, machine_mode mode
)
2332 enum rtx_code code
= GET_CODE (operands
[0]);
2333 enum rtx_code branch_code
;
2334 rtx op0
= operands
[1];
2335 rtx op1
= operands
[2];
2337 bool need_ccmpeq
= false;
2339 if (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2341 op0
= force_reg (mode
, op0
);
2342 op1
= force_reg (mode
, op1
);
2346 if (code
!= EQ
|| mode
== DImode
)
2348 /* Force args into regs, since we can't use constants here. */
2349 op0
= force_reg (mode
, op0
);
2350 if (op1
!= const0_rtx
|| code
== GTU
|| code
== GEU
)
2351 op1
= force_reg (mode
, op1
);
2355 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2358 || (code
== LE
&& TARGET_IEEE
&& TARGET_SH2E
)
2359 || (code
== GE
&& !(TARGET_IEEE
&& TARGET_SH2E
)))
2361 std::swap (op0
, op1
);
2362 code
= swap_condition (code
);
2365 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2368 gcc_assert (TARGET_IEEE
&& TARGET_SH2E
);
2373 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2374 to EQ/GT respectively. */
2375 gcc_assert (code
== EQ
|| code
== GT
|| code
== NE
|| code
== LE
);
2392 branch_code
= reverse_condition (code
);
2398 insn
= gen_rtx_SET (get_t_reg_rtx (),
2399 gen_rtx_fmt_ee (branch_code
, SImode
, op0
, op1
));
2401 sh_emit_set_t_insn (insn
, mode
);
2403 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0
, op1
), mode
);
2405 if (branch_code
== code
)
2406 emit_jump_insn (gen_branch_true (operands
[3]));
2408 emit_jump_insn (gen_branch_false (operands
[3]));
2412 sh_emit_compare_and_set (rtx
*operands
, machine_mode mode
)
2414 enum rtx_code code
= GET_CODE (operands
[1]);
2415 rtx op0
= operands
[2];
2416 rtx op1
= operands
[3];
2417 rtx_code_label
*lab
= NULL
;
2418 bool invert
= false;
2420 op0
= force_reg (mode
, op0
);
2421 if ((code
!= EQ
&& code
!= NE
2422 && (op1
!= const0_rtx
2423 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2424 || (mode
== DImode
&& op1
!= const0_rtx
)
2425 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2426 op1
= force_reg (mode
, op1
);
2428 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2430 if (code
== LT
|| code
== LE
)
2432 std::swap (op0
, op1
);
2433 code
= swap_condition (code
);
2439 lab
= gen_label_rtx ();
2440 sh_emit_scc_to_t (EQ
, op0
, op1
);
2441 emit_jump_insn (gen_branch_true (lab
));
2458 sh_emit_scc_to_t (code
, op0
, op1
);
2462 emit_insn (gen_movnegt (operands
[0], get_t_reg_rtx ()));
2464 emit_move_insn (operands
[0], get_t_reg_rtx ());
2467 /* Functions to output assembly code. */
2469 /* Return a sequence of instructions to perform DI or DF move.
2471 Since the SH cannot move a DI or DF in one instruction, we have
2472 to take care when we see overlapping source and dest registers. */
2474 output_movedouble (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
2477 rtx dst
= operands
[0];
2478 rtx src
= operands
[1];
2481 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
2482 return "mov.l %T1,%0" "\n"
2485 if (register_operand (dst
, mode
)
2486 && register_operand (src
, mode
))
2488 if (REGNO (src
) == MACH_REG
)
2489 return "sts mach,%S0" "\n"
2492 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2493 when mov.d r1,r0 do r1->r0 then r2->r1. */
2494 if (REGNO (src
) + 1 == REGNO (dst
))
2495 return "mov %T1,%T0" "\n"
2498 return "mov %1,%0" "\n"
2501 else if (CONST_INT_P (src
))
2503 if (INTVAL (src
) < 0)
2504 output_asm_insn ("mov #-1,%S0", operands
);
2506 output_asm_insn ("mov #0,%S0", operands
);
2508 return "mov %1,%R0";
2510 else if (MEM_P (src
))
2513 int dreg
= REGNO (dst
);
2514 rtx inside
= XEXP (src
, 0);
2516 switch (GET_CODE (inside
))
2519 ptrreg
= REGNO (inside
);
2523 ptrreg
= subreg_regno (inside
);
2527 ptrreg
= REGNO (XEXP (inside
, 0));
2528 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2529 an offsettable address. Unfortunately, offsettable addresses use
2530 QImode to check the offset, and a QImode offsettable address
2531 requires r0 for the other operand, which is not currently
2532 supported, so we can't use the 'o' constraint.
2533 Thus we must check for and handle r0+REG addresses here.
2534 We punt for now, since this is likely very rare. */
2535 gcc_assert (!REG_P (XEXP (inside
, 1)));
2539 return "mov.l %1,%0" "\n"
2542 return "mov.l %1,%0" "\n"
2548 /* Work out the safe way to copy. Copy into the second half first. */
2550 return "mov.l %T1,%T0" "\n"
2554 return "mov.l %1,%0" "\n"
2558 /* Print an instruction which would have gone into a delay slot after
2559 another instruction, but couldn't because the other instruction expanded
2560 into a sequence where putting the slot insn at the end wouldn't work. */
2562 print_slot (rtx_sequence
*seq
)
2564 final_scan_insn (seq
->insn (1), asm_out_file
, optimize
, 1, NULL
);
2566 seq
->insn (1)->set_deleted ();
2570 output_far_jump (rtx_insn
*insn
, rtx op
)
2572 struct { rtx lab
, reg
, op
; } this_jmp
;
2573 rtx_code_label
*braf_base_lab
= NULL
;
2576 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2579 this_jmp
.lab
= gen_label_rtx ();
2583 && offset
- get_attr_length (insn
) <= 32766
2584 && ! CROSSING_JUMP_P (insn
))
2587 jump
= "mov.w %O0,%1" "\n"
2596 jump
= "mov.l %O0,%1" "\n"
2599 jump
= "mov.l r0,@-r15" "\n"
2601 " mov.l @r0,%1" "\n"
2603 " mov.l @r15+,r0" "\n"
2607 jump
= "mov.l %O0,%1" "\n"
2610 /* If we have a scratch register available, use it. */
2611 if (NONJUMP_INSN_P ((prev
= prev_nonnote_insn (insn
)))
2612 && INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
2614 this_jmp
.reg
= SET_DEST (XVECEXP (PATTERN (prev
), 0, 0));
2615 if (REGNO (this_jmp
.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
2616 jump
= "mov.l r1,@-r15" "\n"
2618 " mov.l @r0,r1" "\n"
2620 " mov.l @r15+,r1" "\n"
2622 output_asm_insn (jump
, &this_jmp
.lab
);
2623 if (dbr_sequence_length ())
2624 print_slot (final_sequence
);
2626 output_asm_insn ("nop", 0);
2630 /* Output the delay slot insn first if any. */
2631 if (dbr_sequence_length ())
2632 print_slot (final_sequence
);
2634 this_jmp
.reg
= gen_rtx_REG (SImode
, 13);
2635 output_asm_insn ("mov.l r13,@-r15", 0);
2636 output_asm_insn (jump
, &this_jmp
.lab
);
2637 output_asm_insn ("mov.l @r15+,r13", 0);
2639 if (far
&& flag_pic
&& TARGET_SH2
)
2641 braf_base_lab
= gen_label_rtx ();
2642 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
2643 CODE_LABEL_NUMBER (braf_base_lab
));
2646 output_asm_insn (".align 2", 0);
2647 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (this_jmp
.lab
));
2649 if (far
&& flag_pic
)
2652 this_jmp
.lab
= braf_base_lab
;
2653 output_asm_insn (".long %O2-%O0", &this_jmp
.lab
);
2656 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this_jmp
.lab
);
2660 /* Local label counter, used for constants in the pool and inside
2661 pattern branches. */
2662 static int lf
= 100;
2664 /* Output code for ordinary branches. */
2666 output_branch (int logic
, rtx_insn
*insn
, rtx
*operands
)
2668 switch (get_attr_length (insn
))
2671 /* This can happen if filling the delay slot has caused a forward
2672 branch to exceed its range (we could reverse it, but only
2673 when we know we won't overextend other branches; this should
2674 best be handled by relaxation).
2675 It can also happen when other condbranches hoist delay slot insn
2676 from their destination, thus leading to code size increase.
2677 But the branch will still be in the range -4092..+4098 bytes. */
2681 /* The call to print_slot will clobber the operands. */
2682 rtx op0
= operands
[0];
2684 /* If the instruction in the delay slot is annulled (true), then
2685 there is no delay slot where we can put it now. The only safe
2686 place for it is after the label. final will do that by default. */
2689 && ! INSN_ANNULLED_BRANCH_P (final_sequence
->insn (0))
2690 && get_attr_length (final_sequence
->insn (1)))
2692 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
2693 ASSEMBLER_DIALECT
? "/" : ".", label
);
2694 print_slot (final_sequence
);
2697 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
2699 output_asm_insn ("bra\t%l0", &op0
);
2700 fprintf (asm_out_file
, "\tnop\n");
2701 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2706 /* When relaxing, handle this like a short branch. The linker
2707 will fix it up if it still doesn't fit after relaxation. */
2709 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
2711 /* These are for SH2e, in which we have to account for the
2712 extra nop because of the hardware bug in annulled branches. */
2718 gcc_assert (!final_sequence
2719 || !(INSN_ANNULLED_BRANCH_P
2720 (XVECEXP (final_sequence
, 0, 0))));
2721 asm_fprintf (asm_out_file
, "b%s%ss\t%LLF%d\n",
2723 ASSEMBLER_DIALECT
? "/" : ".", label
);
2724 fprintf (asm_out_file
, "\tnop\n");
2725 output_asm_insn ("bra\t%l0", operands
);
2726 fprintf (asm_out_file
, "\tnop\n");
2727 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2736 sprintf (buffer
, "b%s%ss\t%%l0",
2738 ASSEMBLER_DIALECT
? "/" : ".");
2739 output_asm_insn (buffer
, &operands
[0]);
2744 /* There should be no longer branches now - that would
2745 indicate that something has destroyed the branches set
2746 up in machine_dependent_reorg. */
2751 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2752 fill in operands 9 as a label to the successor insn.
2753 We try to use jump threading where possible.
2754 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2755 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2756 follow jmp and bt, if the address is in range. */
2758 output_branchy_insn (enum rtx_code code
, const char *templ
,
2759 rtx_insn
*insn
, rtx
*operands
)
2761 rtx_insn
*next_insn
= NEXT_INSN (insn
);
2763 if (next_insn
&& JUMP_P (next_insn
) && condjump_p (next_insn
))
2765 rtx src
= SET_SRC (PATTERN (next_insn
));
2766 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
2768 /* Following branch not taken */
2769 rtx_code_label
*lab
= gen_label_rtx ();
2770 emit_label_after (lab
, next_insn
);
2771 INSN_ADDRESSES_NEW (lab
,
2772 INSN_ADDRESSES (INSN_UID (next_insn
))
2773 + get_attr_length (next_insn
));
2779 int offset
= (branch_dest (next_insn
)
2780 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
2781 if (offset
>= -252 && offset
<= 258)
2783 if (GET_CODE (src
) == IF_THEN_ELSE
)
2785 src
= XEXP (src
, 1);
2791 rtx_code_label
*lab
= gen_label_rtx ();
2792 emit_label_after (lab
, insn
);
2793 INSN_ADDRESSES_NEW (lab
,
2794 INSN_ADDRESSES (INSN_UID (insn
))
2795 + get_attr_length (insn
));
2801 output_ieee_ccmpeq (rtx_insn
*insn
, rtx
*operands
)
2803 return output_branchy_insn (NE
, "bt %l9" "\n"
2808 /* Output the start of the assembler file. */
2810 sh_file_start (void)
2812 default_file_start ();
2815 /* We need to show the text section with the proper
2816 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2817 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2818 will complain. We can teach GAS specifically about the
2819 default attributes for our choice of text section, but
2820 then we would have to change GAS again if/when we change
2821 the text section name. */
2822 fprintf (asm_out_file
, "%s\n", TEXT_SECTION_ASM_OP
);
2824 /* Switch to the data section so that the coffsem symbol
2825 isn't in the text section. */
2826 switch_to_section (data_section
);
2828 if (TARGET_LITTLE_ENDIAN
)
2829 fputs ("\t.little\n", asm_out_file
);
2832 /* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions
2833 need to be output as pointers to function descriptors for
2837 sh_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
2839 if (TARGET_FDPIC
&& size
== UNITS_PER_WORD
2840 && GET_CODE (value
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (value
))
2842 fputs ("\t.long\t", asm_out_file
);
2843 output_addr_const (asm_out_file
, value
);
2844 fputs ("@FUNCDESC\n", asm_out_file
);
2847 return default_assemble_integer (value
, size
, aligned_p
);
2850 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2852 unspec_caller_rtx_p (rtx pat
)
2855 split_const (pat
, &base
, &offset
);
2857 if (GET_CODE (base
) == UNSPEC
)
2859 if (XINT (base
, 1) == UNSPEC_CALLER
)
2861 for (int i
= 0; i
< XVECLEN (base
, 0); i
++)
2862 if (unspec_caller_rtx_p (XVECEXP (base
, 0, i
)))
2868 /* Indicate that INSN cannot be duplicated. This is true for insn
2869 that generates a unique label. */
2871 sh_cannot_copy_insn_p (rtx_insn
*insn
)
2873 if (!reload_completed
|| !flag_pic
)
2876 if (!NONJUMP_INSN_P (insn
))
2878 if (asm_noperands (insn
) >= 0)
2881 rtx pat
= PATTERN (insn
);
2883 if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == USE
)
2886 if (TARGET_FDPIC
&& GET_CODE (pat
) == PARALLEL
)
2888 rtx t
= XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1);
2889 if (GET_CODE (t
) == USE
&& unspec_caller_rtx_p (XEXP (t
, 0)))
2893 if (GET_CODE (pat
) != SET
)
2895 pat
= SET_SRC (pat
);
2897 if (unspec_caller_rtx_p (pat
))
2903 /* Number of instructions used to make an arithmetic right shift by N. */
2904 static const char ashiftrt_insns
[] =
2905 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2907 /* Description of a logical left or right shift, when expanded to a sequence
2909 Notice that one bit right shifts clobber the T bit. One bit left shifts
2910 are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */
2913 ASHL_CLOBBERS_T
= 1 << 0,
2914 LSHR_CLOBBERS_T
= 1 << 1
2917 struct ashl_lshr_sequence
2920 signed char amount
[6];
2924 static const struct ashl_lshr_sequence ashl_lshr_seq
[32] =
2926 { 0, { 0 }, 0 }, // 0
2927 { 1, { 1 }, LSHR_CLOBBERS_T
},
2929 { 2, { 2, 1 }, LSHR_CLOBBERS_T
},
2930 { 2, { 2, 2 }, 0 }, // 4
2931 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T
},
2932 { 3, { 2, 2, 2 }, 0 },
2933 { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T
},
2934 { 1, { 8 }, 0 }, // 8
2935 { 2, { 8, 1 }, LSHR_CLOBBERS_T
},
2937 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T
},
2938 { 3, { 8, 2, 2 }, 0 }, // 12
2939 { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T
},
2940 { 3, { 8, -2, 8 }, 0 },
2941 { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T
},
2942 { 1, { 16 }, 0 }, // 16
2943 { 2, { 16, 1 }, LSHR_CLOBBERS_T
},
2944 { 2, { 16, 2 }, 0 },
2945 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T
},
2946 { 3, { 16, 2, 2 }, 0 }, // 20
2947 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T
},
2948 { 3, { 16, -2, 8 }, 0 },
2949 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T
},
2950 { 2, { 16, 8 }, 0 }, // 24
2951 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T
},
2952 { 3, { 16, 8, 2 }, 0 },
2953 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T
},
2954 { 4, { 16, 8, 2, 2 }, 0 }, // 28
2955 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T
},
2956 { 3, { 16, -2, 16 }, 0 },
2958 /* For a right shift by 31 a 2 insn shll-movt sequence can be used.
2959 For a left shift by 31 a 2 insn and-rotl sequences can be used.
2960 However, the shift-and combiner code needs this entry here to be in
2961 terms of real shift insns. */
2962 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T
}
2965 /* Individual shift amounts for shift amounts < 16, up to three highmost
2966 bits might be clobbered. This is typically used when combined with some
2967 kind of sign or zero extension. */
2968 static const struct ashl_lshr_sequence ext_ashl_lshr_seq
[32] =
2970 { 0, { 0 }, 0 }, // 0
2971 { 1, { 1 }, LSHR_CLOBBERS_T
},
2973 { 2, { 2, 1 }, LSHR_CLOBBERS_T
},
2974 { 2, { 2, 2 }, 0 }, // 4
2975 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T
},
2976 { 2, { 8, -2 }, 0 },
2977 { 2, { 8, -1 }, ASHL_CLOBBERS_T
},
2978 { 1, { 8 }, 0 }, // 8
2979 { 2, { 8, 1 }, LSHR_CLOBBERS_T
},
2981 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T
},
2982 { 3, { 8, 2, 2 }, 0 }, // 12
2983 { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T
},
2984 { 2, { 16, -2 }, 0 },
2985 { 2, { 16, -1 }, ASHL_CLOBBERS_T
},
2986 { 1, { 16 }, 0 }, // 16
2987 { 2, { 16, 1 }, LSHR_CLOBBERS_T
},
2988 { 2, { 16, 2 }, 0 },
2989 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T
},
2990 { 3, { 16, 2, 2 }, 0 }, // 20
2991 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T
},
2992 { 3, { 16, -2, 8 }, 0 },
2993 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T
},
2994 { 2, { 16, 8 }, 0 }, // 24
2995 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T
},
2996 { 3, { 16, 8, 2 }, 0 },
2997 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T
},
2998 { 4, { 16, 8, 2, 2 }, 0 }, // 28
2999 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T
},
3000 { 3, { 16, -2, 16 }, 0 },
3001 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T
}
3004 /* Return true if a shift left consisting of 1/2/8/16 shift instructions
3005 will clobber the T bit. */
3007 sh_ashlsi_clobbers_t_reg_p (rtx shift_amount
)
3009 gcc_assert (CONST_INT_P (shift_amount
));
3011 const int shift_amount_i
= INTVAL (shift_amount
) & 31;
3013 /* Special case for shift count of 31: use and-rotl sequence. */
3014 if (shift_amount_i
== 31)
3017 return (ashl_lshr_seq
[shift_amount_i
].clobbers_t
3018 & ASHL_CLOBBERS_T
) != 0;
3021 /* Return true if a logical right shift consisting of 1/2/8/16 shift
3022 instructions will clobber the T bit. */
3024 sh_lshrsi_clobbers_t_reg_p (rtx shift_amount
)
3026 gcc_assert (CONST_INT_P (shift_amount
));
3028 /* For right shifts the constant might be negative. */
3029 const int shift_amount_i
= std::abs (INTVAL (shift_amount
)) & 31;
3031 /* Special case for shift count of 31: use shll-movt sequence. */
3032 if (shift_amount_i
== 31)
3035 return (ashl_lshr_seq
[shift_amount_i
].clobbers_t
3036 & LSHR_CLOBBERS_T
) != 0;
3039 /* Return true if it is potentially beneficial to use a dynamic shift
3040 instruction (shad / shar) instead of a combination of 1/2/8/16
3041 shift instructions for the specified shift count.
3042 If dynamic shifts are not available, always return false. */
3044 sh_dynamicalize_shift_p (rtx count
)
3046 gcc_assert (CONST_INT_P (count
));
3048 /* For right shifts the constant might be negative. */
3049 const int shift_amount_i
= std::abs (INTVAL (count
)) & 31;
3052 /* For left and right shifts, there are shorter 2 insn sequences for
3053 shift amounts of 31. */
3054 if (shift_amount_i
== 31)
3057 insn_count
= ashl_lshr_seq
[shift_amount_i
].insn_count
;
3059 return TARGET_DYNSHIFT
&& (insn_count
> 1 + SH_DYNAMIC_SHIFT_COST
);
3062 /* Assuming we have a value that has been sign-extended by at least one bit,
3063 can we use the ext_shift_amounts with the last shift turned to an
3064 arithmetic shift to shift it by N without data loss, and quicker than by
3066 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
3068 /* Return the cost of a shift. */
3072 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
3074 if (GET_MODE (x
) == DImode
3075 && CONST_INT_P (XEXP (x
, 1))
3076 && INTVAL (XEXP (x
, 1)) == 1)
3079 /* Everything else is invalid, because there is no pattern for it. */
3082 /* If shift by a non constant, then this will be expensive. */
3083 if (!CONST_INT_P (XEXP (x
, 1)))
3084 return SH_DYNAMIC_SHIFT_COST
;
3086 /* Otherwise, return the true cost in instructions. Cope with out of range
3087 shift counts more or less arbitrarily. */
3088 int value
= INTVAL (XEXP (x
, 1)) & 31;
3090 if (GET_CODE (x
) == ASHIFTRT
)
3092 int cost
= ashiftrt_insns
[value
];
3093 /* If dynamic shifts are available and profitable in this case, then we
3094 put the constant in a reg and use shad. */
3095 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
3096 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
3100 return ashl_lshr_seq
[value
].insn_count
;
3103 /* Return the cost of an AND/XOR/IOR operation. */
3105 and_xor_ior_costs (rtx x
, int code
)
3107 /* On SH1-4 we have only max. SImode operations.
3108 Double the cost for modes > SImode. */
3109 const int cost_scale
= GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
? 2 : 1;
3111 /* A logical operation with two registers is a single cycle
3113 if (!CONST_INT_P (XEXP (x
, 1)))
3114 return 1 * cost_scale
;
3116 int i
= INTVAL (XEXP (x
, 1));
3118 /* These constants are single cycle extu.[bw] instructions. */
3119 if ((i
== 0xff || i
== 0xffff) && code
== AND
)
3120 return 1 * cost_scale
;
3121 /* Constants that can be used in an instruction as an immediate are
3122 a single cycle, but this requires r0, so make it a little more
3124 if (CONST_OK_FOR_K08 (i
))
3125 return 2 * cost_scale
;
3126 /* Constants that can be loaded with a mov immediate need one more cycle.
3127 This case is probably unnecessary. */
3128 if (CONST_OK_FOR_I08 (i
))
3129 return 2 * cost_scale
;
3130 /* Any other constant requires an additional 2 cycle pc-relative load.
3131 This case is probably unnecessary. */
3132 return 3 * cost_scale
;
3135 /* Return the cost of an addition or a subtraction. */
3139 if (GET_MODE (x
) == SImode
)
3141 /* The addc or subc patterns will eventually become one or two
3142 instructions. Below are some costs for some of the patterns
3143 which combine would reject because the costs of the individual
3144 insns in the patterns are lower.
3146 FIXME: It would be much easier if we had something like insn cost
3147 attributes and the cost calculation machinery used those attributes
3148 in the first place. This would eliminate redundant recog-like C
3149 code to calculate costs of complex patterns. */
3150 rtx op0
= XEXP (x
, 0);
3151 rtx op1
= XEXP (x
, 1);
3153 if (GET_CODE (x
) == PLUS
)
3155 if (GET_CODE (op0
) == AND
3156 && XEXP (op0
, 1) == const1_rtx
3157 && (GET_CODE (op1
) == PLUS
3158 || (GET_CODE (op1
) == MULT
&& XEXP (op1
, 1) == const2_rtx
)))
3161 if (GET_CODE (op0
) == MULT
&& XEXP (op0
, 1) == const2_rtx
3162 && GET_CODE (op1
) == LSHIFTRT
3163 && CONST_INT_P (XEXP (op1
, 1)) && INTVAL (XEXP (op1
, 1)) == 31)
3166 /* Let's assume that adding the result of an insns that stores into
3167 the T bit is cheap. */
3168 if (treg_set_expr (op1
, SImode
))
3170 if (treg_set_expr (op0
, SImode
))
3174 /* On SH1-4 we have only max. SImode operations.
3175 Double the cost for modes > SImode. */
3176 const int cost_scale
= GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
? 2 : 1;
3178 /* Adding a register is a single cycle insn. */
3179 if (REG_P (XEXP (x
, 1))
3180 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
3181 return 1 * cost_scale
;
3183 /* Likewise for small constants. */
3184 if (CONST_INT_P (XEXP (x
, 1))
3185 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
3186 return 1 * cost_scale
;
3188 /* Any other constant requires a 2 cycle pc-relative load plus an
3190 return 3 * cost_scale
;
3193 /* Return the cost of a multiply. */
3195 multcosts (rtx x ATTRIBUTE_UNUSED
)
3197 if (sh_multcost
>= 0)
3202 /* We have a mul insn, so we can never take more than the mul and the
3203 read of the mac reg, but count more because of the latency and extra
3210 /* If we're aiming at small code, then just count the number of
3211 insns in a multiply call sequence. */
3215 /* Otherwise count all the insns in the routine we'd be calling too. */
3219 /* Compute a (partial) cost for rtx X. Return true if the complete
3220 cost has been computed, and false if subexpressions should be
3221 scanned. In either case, *TOTAL contains the cost result. */
3223 sh_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
3224 int opno ATTRIBUTE_UNUSED
,
3225 int *total
, bool speed ATTRIBUTE_UNUSED
)
3227 int code
= GET_CODE (x
);
3231 /* The lower-subreg pass decides whether to split multi-word regs
3232 into individual regs by looking at the cost for a SET of certain
3233 modes with the following patterns:
3235 (set (reg) (const_int 0))
3236 On machines that support vector-move operations a multi-word move
3237 is the same cost as individual reg move. On SH there is no
3238 vector-move, so we have to provide the correct cost in the number
3239 of move insns to load/store the reg of the mode in question. */
3241 if (sh_movt_set_dest (x
) != NULL
|| sh_movrt_set_dest (x
) != NULL
)
3243 *total
= COSTS_N_INSNS (1);
3247 if (register_operand (SET_DEST (x
), VOIDmode
)
3248 && (register_operand (SET_SRC (x
), VOIDmode
)
3249 || satisfies_constraint_Z (SET_SRC (x
))))
3251 const machine_mode mode
= GET_MODE (SET_DEST (x
));
3252 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
)
3253 / mov_insn_size (mode
, TARGET_SH2A
));
3258 /* The cost of a mem access is mainly the cost of the address mode. */
3260 *total
= sh_address_cost (XEXP (x
, 0), GET_MODE (x
), MEM_ADDR_SPACE (x
),
3265 /* This case is required for the if_then_else negc pattern. */
3266 if (treg_set_expr (XEXP (x
, 0), SImode
))
3268 *total
= COSTS_N_INSNS (1);
3274 /* Zero extracts of single bits are usually combine patterns for the
3277 if (GET_CODE (XEXP (x
, 0)) == XOR
3278 && arith_reg_operand (XEXP (XEXP (x
, 0), 0), VOIDmode
)
3279 && XEXP (x
, 1) == const1_rtx
3280 && CONST_INT_P (XEXP (x
, 2))
3281 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3282 /* Check that the xor constaint overlaps with the extracted bit. */
3283 && (INTVAL (XEXP (XEXP (x
, 0), 1)) & (1LL << INTVAL (XEXP (x
, 2)))))
3285 *total
= 1; //COSTS_N_INSNS (1);
3289 /* div0s variant. */
3290 if (GET_CODE (XEXP (x
, 0)) == XOR
3291 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == XOR
3292 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
3299 /* The cost of a sign or zero extend depends on whether the source is a
3300 reg or a mem. In case of a mem take the address into account. */
3302 if (arith_reg_operand (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
3304 *total
= COSTS_N_INSNS (1);
3307 if (MEM_P (XEXP (x
, 0)))
3309 *total
= sh_address_cost (XEXP (XEXP (x
, 0), 0),
3310 GET_MODE (XEXP (x
, 0)),
3311 MEM_ADDR_SPACE (XEXP (x
, 0)), true);
3317 if (arith_reg_operand (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
3319 *total
= COSTS_N_INSNS (1);
3322 else if (TARGET_SH2A
&& MEM_P (XEXP (x
, 0))
3323 && (GET_MODE (XEXP (x
, 0)) == QImode
3324 || GET_MODE (XEXP (x
, 0)) == HImode
))
3326 /* Handle SH2A's movu.b and movu.w insn. */
3327 *total
= sh_address_cost (XEXP (XEXP (x
, 0), 0),
3328 GET_MODE (XEXP (x
, 0)),
3329 MEM_ADDR_SPACE (XEXP (x
, 0)), true);
3334 /* mems for SFmode and DFmode can be inside a parallel due to
3335 the way the fpscr is handled. */
3337 for (int i
= 0; i
< XVECLEN (x
, 0); i
++)
3339 rtx xx
= XVECEXP (x
, 0, i
);
3340 if (GET_CODE (xx
) == SET
&& MEM_P (XEXP (xx
, 0)))
3342 *total
= sh_address_cost (XEXP (XEXP (xx
, 0), 0),
3343 GET_MODE (XEXP (xx
, 0)),
3344 MEM_ADDR_SPACE (XEXP (xx
, 0)), true);
3347 if (GET_CODE (xx
) == SET
&& MEM_P (XEXP (xx
, 1)))
3349 *total
= sh_address_cost (XEXP (XEXP (xx
, 1), 0),
3350 GET_MODE (XEXP (xx
, 1)),
3351 MEM_ADDR_SPACE (XEXP (xx
, 1)), true);
3356 if (sh_1el_vec (x
, VOIDmode
))
3357 *total
= outer_code
!= SET
;
3358 else if (sh_rep_vec (x
, VOIDmode
))
3359 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3360 + (outer_code
!= SET
));
3362 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3366 if (CONST_OK_FOR_I08 (INTVAL (x
)))
3368 else if ((outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
3369 && CONST_OK_FOR_K08 (INTVAL (x
)))
3371 /* prepare_cmp_insn will force costly constants int registers before
3372 the cbranch[sd]i4 patterns can see them, so preserve potentially
3373 interesting ones not covered by I08 above. */
3374 else if (outer_code
== COMPARE
3375 && ((unsigned HOST_WIDE_INT
) INTVAL (x
)
3376 == (unsigned HOST_WIDE_INT
) 0x7fffffff + 1
3377 || INTVAL (x
) == 0x7fffffff
3378 || INTVAL (x
) == 0x80 || INTVAL (x
) == -0x81))
3385 /* An and with a constant compared against zero is
3386 most likely going to be a TST #imm, R0 instruction. */
3387 if (XEXP (x
, 1) == const0_rtx
3388 && ((GET_CODE (XEXP (x
, 0)) == AND
3389 || (SUBREG_P (XEXP (x
, 0))
3390 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == AND
))
3391 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
))
3397 else if (XEXP (x
, 1) == const0_rtx
3398 && GET_CODE (XEXP (x
, 0)) == AND
3399 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3400 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == ASHIFT
3401 && arith_reg_operand (XEXP (XEXP (XEXP (x
, 0), 0), 0), SImode
)
3402 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3412 /* This is most likely a clips.b or clips.w insn that is being made up
3415 && (GET_CODE (XEXP (x
, 0)) == SMAX
|| GET_CODE (XEXP (x
, 0)) == SMIN
)
3416 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3417 && REG_P (XEXP (XEXP (x
, 0), 0))
3418 && CONST_INT_P (XEXP (x
, 1)))
3420 *total
= COSTS_N_INSNS (1);
3433 /* prepare_cmp_insn will force costly constants int registers before
3434 the cbranchdi4 pattern can see them, so preserve potentially
3435 interesting ones. */
3436 if (outer_code
== COMPARE
&& GET_MODE (x
) == DImode
)
3443 /* FIXME: This looks broken. Only the last statement has any effect.
3444 Probably this could be folded with the PARALLEL case? */
3445 if (x
== CONST0_RTX (GET_MODE (x
)))
3447 else if (sh_1el_vec (x
, VOIDmode
))
3448 *total
= outer_code
!= SET
;
3449 if (sh_rep_vec (x
, VOIDmode
))
3450 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3451 + (outer_code
!= SET
));
3452 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3457 *total
= COSTS_N_INSNS (addsubcosts (x
));
3461 /* Check for (and (not (reg)) (const_int 1)) which is a tst insn. */
3462 if (GET_CODE (XEXP (x
, 0)) == NOT
&& XEXP (x
, 1) == const1_rtx
)
3464 *total
= COSTS_N_INSNS (1);
3471 *total
= COSTS_N_INSNS (and_xor_ior_costs (x
, code
));
3475 *total
= COSTS_N_INSNS (multcosts (x
));
3480 /* div0s sign comparison. */
3481 if (GET_CODE (XEXP (x
, 0)) == XOR
3482 && REG_P ((XEXP (XEXP (x
, 0), 0)))
3483 && REG_P ((XEXP (XEXP (x
, 0), 1)))
3484 && satisfies_constraint_Z (XEXP (x
, 1)))
3486 *total
= COSTS_N_INSNS (1);
3493 /* div0s sign comparison. */
3494 if (GET_CODE (XEXP (x
, 0)) == XOR
3495 && REG_P ((XEXP (XEXP (x
, 0), 0)))
3496 && REG_P ((XEXP (XEXP (x
, 0), 1)))
3497 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 31)
3499 *total
= COSTS_N_INSNS (1);
3506 int cost
= shiftcosts (x
);
3509 *total
= COSTS_N_INSNS (cost
);
3517 *total
= COSTS_N_INSNS (20);
3530 /* Determine the size of the fundamental move insn that will be used
3531 for the specified mode. */
3533 mov_insn_size (machine_mode mode
, bool consider_sh2a
)
3535 const int mode_sz
= GET_MODE_SIZE (mode
);
3537 if ((consider_sh2a
&& TARGET_SH2A_DOUBLE
&& mode
== DFmode
)
3538 || (TARGET_FMOVD
&& mode
== DFmode
))
3542 /* The max. available mode for actual move insns is SImode.
3543 Larger accesses will be split into multiple loads/stores. */
3544 const int max_mov_sz
= GET_MODE_SIZE (SImode
);
3545 return mode_sz
>= max_mov_sz
? max_mov_sz
: mode_sz
;
3549 /* Determine the maximum possible displacement for a move insn for the
3552 sh_max_mov_insn_displacement (machine_mode mode
, bool consider_sh2a
)
3554 /* The 4 byte displacement move insns are the same as the 2 byte
3555 versions but take a 12 bit displacement. All we need to do is to
3556 scale the max. displacement value accordingly. */
3557 const int disp_scale
= consider_sh2a
? (4095 / 15) : 1;
3559 /* SH2A supports FPU move insns with 12 bit displacements.
3560 Other variants to do not support any kind of displacements for
3562 if (! consider_sh2a
&& TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3566 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3567 const int mode_sz
= GET_MODE_SIZE (mode
);
3568 int r
= 15 * mov_insn_sz
* disp_scale
;
3570 /* If the mov insn will be split into multiple loads/stores, the
3571 maximum possible displacement is a bit smaller. */
3572 if (mode_sz
> mov_insn_sz
)
3573 r
-= mode_sz
- mov_insn_sz
;
3578 /* Determine the alignment mask for a move insn of the
3581 mov_insn_alignment_mask (machine_mode mode
, bool consider_sh2a
)
3583 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3584 return mov_insn_sz
> 0 ? (mov_insn_sz
- 1) : 0;
3587 /* Return the displacement value of a displacement address. */
3589 sh_disp_addr_displacement (rtx x
)
3591 gcc_assert (satisfies_constraint_Sdd (x
));
3592 return INTVAL (XEXP (XEXP (x
, 0), 1));
3595 /* Compute the cost of an address. */
3597 sh_address_cost (rtx x
, machine_mode mode
,
3598 addr_space_t as ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
3600 /* 'GBR + 0'. Account one more because of R0 restriction. */
3601 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
3604 /* Simple reg, post-inc, pre-dec addressing. */
3605 if (REG_P (x
) || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
3608 /* 'reg + disp' addressing. */
3609 if (GET_CODE (x
) == PLUS
3610 && REG_P (XEXP (x
, 0)) && CONST_INT_P (XEXP (x
, 1)))
3612 /* 'GBR + disp'. Account one more because of R0 restriction. */
3613 if (REGNO (XEXP (x
, 0)) == GBR_REG
3614 && gbr_displacement (XEXP (x
, 1), mode
))
3617 const HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
3622 /* The displacement would fit into a 2 byte move insn.
3623 HImode and QImode loads/stores with displacement put pressure on
3624 R0 which will most likely require another reg copy. Thus account
3625 a higher cost for that. */
3626 if (offset
> 0 && offset
<= sh_max_mov_insn_displacement (mode
, false))
3627 return (mode
== HImode
|| mode
== QImode
) ? 2 : 1;
3629 /* The displacement would fit into a 4 byte move insn (SH2A). */
3631 && offset
> 0 && offset
<= sh_max_mov_insn_displacement (mode
, true))
3634 /* The displacement is probably out of range and will require extra
3639 /* 'reg + reg' addressing. Account a slightly higher cost because of
3640 increased pressure on R0. */
3641 if (GET_CODE (x
) == PLUS
&& ! CONSTANT_P (XEXP (x
, 1)))
3644 /* Not sure what it is - probably expensive. */
3648 /* Code to expand a shift. */
3650 gen_ashift (int type
, int n
, rtx reg
)
3654 /* Negative values here come from the shift_amounts array. */
3664 n_rtx
= GEN_INT (n
);
3665 gcc_assert (satisfies_constraint_P27 (n_rtx
));
3670 emit_insn (gen_ashrsi3_k (reg
, reg
, n_rtx
));
3674 emit_insn (gen_shlr (reg
, reg
));
3676 emit_insn (gen_lshrsi3_k (reg
, reg
, n_rtx
));
3679 emit_insn (gen_ashlsi3_k (reg
, reg
, n_rtx
));
3686 /* Code to expand a HImode shift. */
3688 gen_ashift_hi (int type
, int n
, rtx reg
)
3690 /* Negative values here come from the shift_amounts array. */
3704 /* We don't have HImode right shift operations because using the
3705 ordinary 32 bit shift instructions for that doesn't generate proper
3706 zero/sign extension.
3707 gen_ashift_hi is only called in contexts where we know that the
3708 sign extension works out correctly. */
3711 if (GET_CODE (reg
) == SUBREG
)
3713 offset
= SUBREG_BYTE (reg
);
3714 reg
= SUBREG_REG (reg
);
3716 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
3720 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
3725 /* Output RTL to split a constant shift into its component SH constant
3726 shift instructions. */
3728 gen_shifty_op (int code
, rtx
*operands
)
3730 int value
= INTVAL (operands
[2]);
3733 /* Truncate the shift count in case it is out of bounds. */
3738 if (code
== LSHIFTRT
)
3740 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
3741 emit_insn (gen_movt (operands
[0], get_t_reg_rtx ()));
3744 else if (code
== ASHIFT
)
3746 /* There is a two instruction sequence for 31 bit left shifts,
3747 but it requires r0. */
3748 if (REG_P (operands
[0]) && REGNO (operands
[0]) == 0)
3750 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
3751 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
3756 else if (value
== 0)
3758 /* This can happen even when optimizing, if there were subregs before
3759 reload. Don't output a nop here, as this is never optimized away;
3760 use a no-op move instead. */
3761 emit_insn (gen_rtx_SET (operands
[0], operands
[0]));
3765 max
= ashl_lshr_seq
[value
].insn_count
;
3766 for (i
= 0; i
< max
; i
++)
3767 gen_ashift (code
, ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3770 /* Same as gen_shifty_op, but optimized for values where the topmost bits
3773 gen_shifty_hi_op (int code
, rtx
*operands
)
3775 int value
= INTVAL (operands
[2]);
3777 void (*gen_fun
) (int, int, rtx
);
3779 /* This operation is used by and_shl for SImode values with a few
3780 high bits known to be cleared. */
3784 emit_insn (gen_nop ());
3788 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
3791 max
= ext_ashl_lshr_seq
[value
].insn_count
;
3792 for (i
= 0; i
< max
; i
++)
3793 gen_fun (code
, ext_ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3796 /* When shifting right, emit the shifts in reverse order, so that
3797 solitary negative values come first. */
3798 for (i
= ext_ashl_lshr_seq
[value
].insn_count
- 1; i
>= 0; i
--)
3799 gen_fun (code
, ext_ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3802 /* Output RTL for an arithmetic right shift.
3803 ??? Rewrite to use super-optimizer sequences. */
3805 expand_ashiftrt (rtx
*operands
)
3811 if (TARGET_DYNSHIFT
)
3813 if (!CONST_INT_P (operands
[2]))
3815 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
3816 emit_insn (gen_negsi2 (count
, count
));
3817 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
3820 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
3821 > 1 + SH_DYNAMIC_SHIFT_COST
)
3824 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
3825 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
3829 if (!CONST_INT_P (operands
[2]))
3832 value
= INTVAL (operands
[2]) & 31;
3836 /* If we are called from abs expansion, arrange things so that we
3837 we can use a single MT instruction that doesn't clobber the source,
3838 if LICM can hoist out the load of the constant zero. */
3839 if (currently_expanding_to_rtl
)
3841 emit_insn (gen_cmpgtsi_t (force_reg (SImode
, CONST0_RTX (SImode
)),
3843 emit_insn (gen_mov_neg_si_t (operands
[0], get_t_reg_rtx ()));
3846 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
3849 else if (value
>= 16 && value
<= 19)
3851 wrk
= gen_reg_rtx (SImode
);
3852 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
3855 gen_ashift (ASHIFTRT
, 1, wrk
);
3856 emit_move_insn (operands
[0], wrk
);
3859 /* Expand a short sequence inline, longer call a magic routine. */
3860 else if (value
<= 5)
3862 wrk
= gen_reg_rtx (SImode
);
3863 emit_move_insn (wrk
, operands
[1]);
3865 gen_ashift (ASHIFTRT
, 1, wrk
);
3866 emit_move_insn (operands
[0], wrk
);
3870 wrk
= gen_reg_rtx (Pmode
);
3872 /* Load the value into an arg reg and call a helper. */
3873 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
3874 sprintf (func
, "__ashiftrt_r4_%d", value
);
3875 rtx lab
= function_symbol (wrk
, func
, SFUNC_STATIC
).lab
;
3876 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
, lab
));
3877 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
3881 /* Try to find a good way to implement the combiner pattern
3882 [(set (match_operand:SI 0 "register_operand" "r")
3883 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3884 (match_operand:SI 2 "const_int_operand" "n"))
3885 (match_operand:SI 3 "const_int_operand" "n"))) .
3886 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3887 return 0 for simple right / left or left/right shift combination.
3888 return 1 for a combination of shifts with zero_extend.
3889 return 2 for a combination of shifts with an AND that needs r0.
3890 return 3 for a combination of shifts with an AND that needs an extra
3891 scratch register, when the three highmost bits of the AND mask are clear.
3892 return 4 for a combination of shifts with an AND that needs an extra
3893 scratch register, when any of the three highmost bits of the AND mask
3895 If ATTRP is set, store an initial right shift width in ATTRP[0],
3896 and the instruction length in ATTRP[1] . These values are not valid
3898 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3899 shift_amounts for the last shift value that is to be used before the
3902 shl_and_kind (rtx left_rtx
, rtx mask_rtx
, int *attrp
)
3904 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
3905 int left
= INTVAL (left_rtx
), right
;
3907 int cost
, best_cost
= 10000;
3908 int best_right
= 0, best_len
= 0;
3912 if (left
< 0 || left
> 31)
3914 if (CONST_INT_P (mask_rtx
))
3915 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
3917 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
3918 /* Can this be expressed as a right shift / left shift pair? */
3919 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
3920 right
= exact_log2 (lsb
);
3921 mask2
= ~(mask
+ lsb
- 1);
3922 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
3923 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3925 best_cost
= ashl_lshr_seq
[right
].insn_count
3926 + ashl_lshr_seq
[right
+ left
].insn_count
;
3927 /* mask has no trailing zeroes <==> ! right */
3928 else if (! right
&& mask2
== ~(lsb2
- 1))
3930 int late_right
= exact_log2 (lsb2
);
3931 best_cost
= ashl_lshr_seq
[left
+ late_right
].insn_count
3932 + ashl_lshr_seq
[late_right
].insn_count
;
3934 /* Try to use zero extend. */
3935 if (mask2
== ~(lsb2
- 1))
3939 for (width
= 8; width
<= 16; width
+= 8)
3941 /* Can we zero-extend right away? */
3942 if (lsb2
== (unsigned HOST_WIDE_INT
) 1 << width
)
3944 cost
= 1 + ext_ashl_lshr_seq
[right
].insn_count
3945 + ext_ashl_lshr_seq
[left
+ right
].insn_count
;
3946 if (cost
< best_cost
)
3957 /* ??? Could try to put zero extend into initial right shift,
3958 or even shift a bit left before the right shift. */
3959 /* Determine value of first part of left shift, to get to the
3960 zero extend cut-off point. */
3961 first
= width
- exact_log2 (lsb2
) + right
;
3962 if (first
>= 0 && right
+ left
- first
>= 0)
3964 cost
= ext_ashl_lshr_seq
[right
].insn_count
3965 + ext_ashl_lshr_seq
[first
].insn_count
+ 1
3966 + ext_ashl_lshr_seq
[right
+ left
- first
].insn_count
;
3968 if (cost
< best_cost
)
3980 /* Try to use r0 AND pattern */
3981 for (i
= 0; i
<= 2; i
++)
3985 if (! CONST_OK_FOR_K08 (mask
>> i
))
3987 cost
= (i
!= 0) + 2 + ext_ashl_lshr_seq
[left
+ i
].insn_count
;
3988 if (cost
< best_cost
)
3993 best_len
= cost
- 1;
3996 /* Try to use a scratch register to hold the AND operand. */
3997 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
) 3 << 30)) == 0;
3998 for (i
= 0; i
<= 2; i
++)
4002 cost
= (i
!= 0) + (CONST_OK_FOR_I08 (mask
>> i
) ? 2 : 3)
4005 : ashl_lshr_seq
)[left
+ i
].insn_count
;
4006 if (cost
< best_cost
)
4011 best_len
= cost
- 1 - ! CONST_OK_FOR_I08 (mask
>> i
);
4017 attrp
[0] = best_right
;
4018 attrp
[1] = best_len
;
4023 /* This is used in length attributes of the unnamed instructions
4024 corresponding to shl_and_kind return values of 1 and 2. */
4026 shl_and_length (rtx insn
)
4028 rtx set_src
, left_rtx
, mask_rtx
;
4031 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4032 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
4033 mask_rtx
= XEXP (set_src
, 1);
4034 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
4035 return attributes
[1];
4038 /* This is used in length attribute of the and_shl_scratch instruction. */
4040 shl_and_scr_length (rtx insn
)
4042 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4043 int len
= ashl_lshr_seq
[INTVAL (XEXP (set_src
, 1)) & 31].insn_count
;
4044 rtx op
= XEXP (set_src
, 0);
4045 len
+= ashl_lshr_seq
[INTVAL (XEXP (op
, 1)) & 31].insn_count
+ 1;
4046 op
= XEXP (XEXP (op
, 0), 0);
4047 return len
+ ashl_lshr_seq
[INTVAL (XEXP (op
, 1)) & 31].insn_count
;
4050 /* Generate rtl for instructions for which shl_and_kind advised a particular
4051 method of generating them, i.e. returned zero. */
4053 gen_shl_and (rtx dest
, rtx left_rtx
, rtx mask_rtx
, rtx source
)
4056 unsigned HOST_WIDE_INT mask
;
4057 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
4058 int right
, total_shift
;
4059 void (*shift_gen_fun
) (int, rtx
*) = gen_shifty_hi_op
;
4061 right
= attributes
[0];
4062 total_shift
= INTVAL (left_rtx
) + right
;
4063 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
4070 int first
= attributes
[2];
4075 emit_insn ((mask
<< right
) <= 0xff
4076 ? gen_zero_extendqisi2 (dest
,
4077 gen_lowpart (QImode
, source
))
4078 : gen_zero_extendhisi2 (dest
,
4079 gen_lowpart (HImode
, source
)));
4083 emit_insn (gen_movsi (dest
, source
));
4087 operands
[2] = GEN_INT (right
);
4088 gen_shifty_hi_op (LSHIFTRT
, operands
);
4092 operands
[2] = GEN_INT (first
);
4093 gen_shifty_hi_op (ASHIFT
, operands
);
4094 total_shift
-= first
;
4098 emit_insn (mask
<= 0xff
4099 ? gen_zero_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4100 : gen_zero_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4101 if (total_shift
> 0)
4103 operands
[2] = GEN_INT (total_shift
);
4104 gen_shifty_hi_op (ASHIFT
, operands
);
4109 shift_gen_fun
= gen_shifty_op
;
4112 /* If the topmost bit that matters is set, set the topmost bits
4113 that don't matter. This way, we might be able to get a shorter
4115 if (mask
& ((HOST_WIDE_INT
) 1 << (31 - total_shift
)))
4116 mask
|= (HOST_WIDE_INT
) ((HOST_WIDE_INT_M1U
) << (31 - total_shift
));
4119 /* Don't expand fine-grained when combining, because that will
4120 make the pattern fail. */
4121 if (currently_expanding_to_rtl
4122 || reload_in_progress
|| reload_completed
)
4126 /* Cases 3 and 4 should be handled by this split
4127 only while combining */
4128 gcc_assert (kind
<= 2);
4131 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
4134 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
4139 operands
[2] = GEN_INT (total_shift
);
4140 shift_gen_fun (ASHIFT
, operands
);
4147 if (kind
!= 4 && total_shift
< 16)
4149 neg
= -ext_ashl_lshr_seq
[total_shift
].amount
[1];
4151 neg
-= ext_ashl_lshr_seq
[total_shift
].amount
[2];
4155 emit_insn (gen_and_shl_scratch (dest
, source
,
4158 GEN_INT (total_shift
+ neg
),
4160 emit_insn (gen_movsi (dest
, dest
));
4167 /* Try to find a good way to implement the combiner pattern
4168 [(set (match_operand:SI 0 "register_operand" "=r")
4169 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4170 (match_operand:SI 2 "const_int_operand" "n")
4171 (match_operand:SI 3 "const_int_operand" "n")
4173 (clobber (reg:SI T_REG))]
4174 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
4175 return 0 for simple left / right shift combination.
4176 return 1 for left shift / 8 bit sign extend / left shift.
4177 return 2 for left shift / 16 bit sign extend / left shift.
4178 return 3 for left shift / 8 bit sign extend / shift / sign extend.
4179 return 4 for left shift / 16 bit sign extend / shift / sign extend.
4180 return 5 for left shift / 16 bit sign extend / right shift
4181 return 6 for < 8 bit sign extend / left shift.
4182 return 7 for < 8 bit sign extend / left shift / single right shift.
4183 If COSTP is nonzero, assign the calculated cost to *COSTP. */
4185 shl_sext_kind (rtx left_rtx
, rtx size_rtx
, int *costp
)
4187 int left
, size
, insize
, ext
;
4188 int cost
= 0, best_cost
;
4191 left
= INTVAL (left_rtx
);
4192 size
= INTVAL (size_rtx
);
4193 insize
= size
- left
;
4194 gcc_assert (insize
> 0);
4195 /* Default to left / right shift. */
4197 best_cost
= ashl_lshr_seq
[32 - insize
].insn_count
4198 + ashl_lshr_seq
[32 - size
].insn_count
;
4201 /* 16 bit shift / sign extend / 16 bit shift */
4202 cost
= ashl_lshr_seq
[16 - insize
].insn_count
+ 1
4203 + ashl_lshr_seq
[16 - size
].insn_count
;
4204 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
4205 below, by alternative 3 or something even better. */
4206 if (cost
< best_cost
)
4212 /* Try a plain sign extend between two shifts. */
4213 for (ext
= 16; ext
>= insize
; ext
-= 8)
4217 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
+ 1
4218 + ashl_lshr_seq
[size
- ext
].insn_count
;
4219 if (cost
< best_cost
)
4221 kind
= ext
/ (unsigned) 8;
4225 /* Check if we can do a sloppy shift with a final signed shift
4226 restoring the sign. */
4227 if (EXT_SHIFT_SIGNED (size
- ext
))
4228 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
4229 + ext_ashl_lshr_seq
[size
- ext
].insn_count
+ 1;
4230 /* If not, maybe it's still cheaper to do the second shift sloppy,
4231 and do a final sign extend? */
4232 else if (size
<= 16)
4233 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
+ 1
4234 + ext_ashl_lshr_seq
[size
> ext
? size
- ext
: ext
- size
].insn_count
4238 if (cost
< best_cost
)
4240 kind
= ext
/ (unsigned) 8 + 2;
4244 /* Check if we can sign extend in r0 */
4247 cost
= 3 + ashl_lshr_seq
[left
].insn_count
;
4248 if (cost
< best_cost
)
4253 /* Try the same with a final signed shift. */
4256 cost
= 3 + ext_ashl_lshr_seq
[left
+ 1].insn_count
+ 1;
4257 if (cost
< best_cost
)
4264 if (TARGET_DYNSHIFT
)
4266 /* Try to use a dynamic shift. */
4267 cost
= ashl_lshr_seq
[32 - insize
].insn_count
+ 1 + SH_DYNAMIC_SHIFT_COST
;
4268 if (cost
< best_cost
)
4279 /* Function to be used in the length attribute of the instructions
4280 implementing this pattern. */
4282 shl_sext_length (rtx insn
)
4284 rtx set_src
, left_rtx
, size_rtx
;
4287 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4288 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
4289 size_rtx
= XEXP (set_src
, 1);
4290 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
4294 /* Generate rtl for this pattern */
4296 gen_shl_sext (rtx dest
, rtx left_rtx
, rtx size_rtx
, rtx source
)
4299 int left
, size
, insize
, cost
;
4302 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
4303 left
= INTVAL (left_rtx
);
4304 size
= INTVAL (size_rtx
);
4305 insize
= size
- left
;
4313 int ext
= kind
& 1 ? 8 : 16;
4314 int shift2
= size
- ext
;
4316 /* Don't expand fine-grained when combining, because that will
4317 make the pattern fail. */
4318 if (! currently_expanding_to_rtl
4319 && ! reload_in_progress
&& ! reload_completed
)
4321 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4322 emit_insn (gen_movsi (dest
, source
));
4326 emit_insn (gen_movsi (dest
, source
));
4330 operands
[2] = GEN_INT (ext
- insize
);
4331 gen_shifty_hi_op (ASHIFT
, operands
);
4334 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4335 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4340 operands
[2] = GEN_INT (shift2
);
4341 gen_shifty_op (ASHIFT
, operands
);
4348 if (EXT_SHIFT_SIGNED (shift2
))
4350 operands
[2] = GEN_INT (shift2
+ 1);
4351 gen_shifty_op (ASHIFT
, operands
);
4352 operands
[2] = const1_rtx
;
4353 gen_shifty_op (ASHIFTRT
, operands
);
4356 operands
[2] = GEN_INT (shift2
);
4357 gen_shifty_hi_op (ASHIFT
, operands
);
4361 operands
[2] = GEN_INT (-shift2
);
4362 gen_shifty_hi_op (LSHIFTRT
, operands
);
4364 emit_insn (size
<= 8
4365 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4366 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4373 if (! currently_expanding_to_rtl
4374 && ! reload_in_progress
&& ! reload_completed
)
4375 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4379 operands
[2] = GEN_INT (16 - insize
);
4380 gen_shifty_hi_op (ASHIFT
, operands
);
4381 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4383 /* Don't use gen_ashrsi3 because it generates new pseudos. */
4385 gen_ashift (ASHIFTRT
, 1, dest
);
4390 /* Don't expand fine-grained when combining, because that will
4391 make the pattern fail. */
4392 if (! currently_expanding_to_rtl
4393 && ! reload_in_progress
&& ! reload_completed
)
4395 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4396 emit_insn (gen_movsi (dest
, source
));
4399 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
4400 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
4401 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (HOST_WIDE_INT_M1U
<< (insize
- 1))));
4403 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
4404 gen_shifty_op (ASHIFT
, operands
);
4406 emit_insn (gen_ashrsi3_k (dest
, dest
, const1_rtx
));
4414 typedef struct label_ref_list_d
4416 rtx_code_label
*label
;
4417 struct label_ref_list_d
*next
;
4418 } *label_ref_list_t
;
4420 static object_allocator
<label_ref_list_d
> label_ref_list_d_pool
4421 ("label references list");
4423 /* The SH cannot load a large constant into a register, constants have to
4424 come from a pc relative load. The reference of a pc relative load
4425 instruction must be less than 1k in front of the instruction. This
4426 means that we often have to dump a constant inside a function, and
4427 generate code to branch around it.
4429 It is important to minimize this, since the branches will slow things
4430 down and make things bigger.
4432 Worst case code looks like:
4450 We fix this by performing a scan before scheduling, which notices which
4451 instructions need to have their operands fetched from the constant table
4452 and builds the table.
4456 scan, find an instruction which needs a pcrel move. Look forward, find the
4457 last barrier which is within MAX_COUNT bytes of the requirement.
4458 If there isn't one, make one. Process all the instructions between
4459 the find and the barrier.
4461 In the above example, we can tell that L3 is within 1k of L1, so
4462 the first move can be shrunk from the 3 insn+constant sequence into
4463 just 1 insn, and the constant moved to L3 to make:
4474 Then the second move becomes the target for the shortening process. */
4478 rtx value
; /* Value in table. */
4479 rtx_code_label
*label
; /* Label of value. */
4480 label_ref_list_t wend
; /* End of window. */
4481 machine_mode mode
; /* Mode of value. */
4483 /* True if this constant is accessed as part of a post-increment
4484 sequence. Note that HImode constants are never accessed in this way. */
4485 bool part_of_sequence_p
;
4488 /* The maximum number of constants that can fit into one pool, since
4489 constants in the range 0..510 are at least 2 bytes long, and in the
4490 range from there to 1018 at least 4 bytes. */
4492 #define MAX_POOL_SIZE 372
4493 static pool_node pool_vector
[MAX_POOL_SIZE
];
4494 static int pool_size
;
4495 static rtx_code_label
*pool_window_label
;
4496 static int pool_window_last
;
4498 static int max_labelno_before_reorg
;
4500 /* ??? If we need a constant in HImode which is the truncated value of a
4501 constant we need in SImode, we could combine the two entries thus saving
4502 two bytes. Is this common enough to be worth the effort of implementing
4505 /* ??? This stuff should be done at the same time that we shorten branches.
4506 As it is now, we must assume that all branches are the maximum size, and
4507 this causes us to almost always output constant pools sooner than
4510 /* Add a constant to the pool and return its label. */
4511 static rtx_code_label
*
4512 add_constant (rtx x
, machine_mode mode
, rtx last_value
)
4514 rtx_code_label
*lab
, *new_rtx
;
4515 label_ref_list_t ref
, newref
;
4517 /* First see if we've already got it. */
4518 for (int i
= 0; i
< pool_size
; i
++)
4520 if (x
->code
== pool_vector
[i
].value
->code
4521 && mode
== pool_vector
[i
].mode
)
4523 if (x
->code
== CODE_LABEL
)
4525 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
4528 if (rtx_equal_p (x
, pool_vector
[i
].value
))
4533 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
4535 new_rtx
= gen_label_rtx ();
4536 LABEL_REFS (new_rtx
) = pool_vector
[i
].label
;
4537 pool_vector
[i
].label
= lab
= new_rtx
;
4539 if (lab
&& pool_window_label
)
4541 newref
= label_ref_list_d_pool
.allocate ();
4542 newref
->label
= pool_window_label
;
4543 ref
= pool_vector
[pool_window_last
].wend
;
4545 pool_vector
[pool_window_last
].wend
= newref
;
4548 pool_window_label
= new_rtx
;
4549 pool_window_last
= i
;
4555 /* Need a new one. */
4556 pool_vector
[pool_size
].value
= x
;
4557 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
4560 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
4563 lab
= gen_label_rtx ();
4564 pool_vector
[pool_size
].mode
= mode
;
4565 pool_vector
[pool_size
].label
= lab
;
4566 pool_vector
[pool_size
].wend
= NULL
;
4567 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
4568 if (lab
&& pool_window_label
)
4570 newref
= label_ref_list_d_pool
.allocate ();
4571 newref
->label
= pool_window_label
;
4572 ref
= pool_vector
[pool_window_last
].wend
;
4574 pool_vector
[pool_window_last
].wend
= newref
;
4577 pool_window_label
= lab
;
4578 pool_window_last
= pool_size
;
4583 /* Output the literal table. START, if nonzero, is the first instruction
4584 this table is needed for, and also indicates that there is at least one
4585 casesi_worker_2 instruction; We have to emit the operand3 labels from
4586 these insns at a 4-byte aligned position. BARRIER is the barrier
4587 after which we are to place the table. */
4589 dump_table (rtx_insn
*start
, rtx_insn
*barrier
)
4591 rtx_insn
*scan
= barrier
;
4592 bool need_align
= true;
4593 rtx_code_label
*lab
;
4594 label_ref_list_t ref
;
4595 bool have_df
= false;
4597 /* Do two passes, first time dump out the HI sized constants. */
4599 for (int i
= 0; i
< pool_size
; i
++)
4601 pool_node
*p
= &pool_vector
[i
];
4603 if (p
->mode
== HImode
)
4607 scan
= emit_insn_after (gen_align_2 (), scan
);
4610 for (lab
= p
->label
; lab
;
4611 lab
= safe_as_a
<rtx_code_label
*> (LABEL_REFS (lab
)))
4612 scan
= emit_label_after (lab
, scan
);
4613 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
4615 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4618 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4621 else if (p
->mode
== DFmode
)
4629 scan
= emit_insn_after (gen_align_4 (), scan
);
4631 for (; start
!= barrier
; start
= NEXT_INSN (start
))
4632 if (NONJUMP_INSN_P (start
)
4633 && recog_memoized (start
) == CODE_FOR_casesi_worker_2
)
4635 rtx src
= SET_SRC (XVECEXP (PATTERN (start
), 0, 0));
4636 rtx lab
= XEXP (XVECEXP (src
, 0, 3), 0);
4638 scan
= emit_label_after (as_a
<rtx_insn
*> (lab
), scan
);
4641 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
4643 rtx_insn
*align_insn
= NULL
;
4645 scan
= emit_label_after (gen_label_rtx (), scan
);
4646 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4649 for (int i
= 0; i
< pool_size
; i
++)
4651 pool_node
*p
= &pool_vector
[i
];
4659 if (align_insn
&& !p
->part_of_sequence_p
)
4661 for (lab
= p
->label
; lab
;
4662 lab
= safe_as_a
<rtx_code_label
*> (LABEL_REFS (lab
)))
4663 emit_label_before (lab
, align_insn
);
4664 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
4666 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4669 emit_insn_before (gen_consttable_window_end (lab
),
4672 delete_insn (align_insn
);
4678 for (lab
= p
->label
; lab
;
4679 lab
= safe_as_a
<rtx_code_label
*> (LABEL_REFS (lab
)))
4680 scan
= emit_label_after (lab
, scan
);
4681 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
4683 need_align
= ! need_align
;
4689 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4695 for (lab
= p
->label
; lab
;
4696 lab
= safe_as_a
<rtx_code_label
*> (LABEL_REFS (lab
)))
4697 scan
= emit_label_after (lab
, scan
);
4698 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4705 if (p
->mode
!= HImode
)
4707 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4710 scan
= emit_insn_after (gen_consttable_window_end (lab
),
4719 for (int i
= 0; i
< pool_size
; i
++)
4721 pool_node
*p
= &pool_vector
[i
];
4732 scan
= emit_label_after (gen_label_rtx (), scan
);
4733 scan
= emit_insn_after (gen_align_4 (), scan
);
4735 for (lab
= p
->label
; lab
;
4736 lab
= safe_as_a
<rtx_code_label
*> (LABEL_REFS (lab
)))
4737 scan
= emit_label_after (lab
, scan
);
4738 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
4746 scan
= emit_label_after (gen_label_rtx (), scan
);
4747 scan
= emit_insn_after (gen_align_4 (), scan
);
4749 for (lab
= p
->label
; lab
;
4750 lab
= safe_as_a
<rtx_code_label
*> (LABEL_REFS (lab
)))
4751 scan
= emit_label_after (lab
, scan
);
4752 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4759 if (p
->mode
!= HImode
)
4761 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4764 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4769 scan
= emit_insn_after (gen_consttable_end (), scan
);
4770 scan
= emit_barrier_after (scan
);
4772 pool_window_label
= NULL
;
4773 pool_window_last
= 0;
4776 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4778 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4780 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4781 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4782 need to fix it if the input value is CONST_OK_FOR_I08. */
4784 broken_move (rtx_insn
*insn
)
4786 if (NONJUMP_INSN_P (insn
))
4788 rtx pat
= PATTERN (insn
);
4789 if (GET_CODE (pat
) == PARALLEL
)
4790 pat
= XVECEXP (pat
, 0, 0);
4791 if (GET_CODE (pat
) == SET
4792 /* We can load any 8-bit value if we don't care what the high
4793 order bits end up as. */
4794 && GET_MODE (SET_DEST (pat
)) != QImode
4795 && (CONSTANT_P (SET_SRC (pat
))
4796 || (GET_CODE (SET_SRC (pat
)) == UNSPEC_VOLATILE
4797 && XINT (SET_SRC (pat
), 1) == UNSPECV_SP_SWITCH_B
)
4798 /* Match mova_const. */
4799 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
4800 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
4801 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
4803 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
4804 && (fp_zero_operand (SET_SRC (pat
))
4805 || fp_one_operand (SET_SRC (pat
)))
4806 /* In general we don't know the current setting of fpscr, so
4808 There is an exception if this was a register-register move
4809 before reload - and hence it was ascertained that we have
4810 single precision setting - and in a post-reload optimization
4811 we changed this to do a constant load. In that case
4812 we don't have an r0 clobber, hence we must use fldi. */
4814 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
4816 && REG_P (SET_DEST (pat
))
4817 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
4819 && GET_MODE (SET_DEST (pat
)) == SImode
4820 && (satisfies_constraint_I20 (SET_SRC (pat
))
4821 || satisfies_constraint_I28 (SET_SRC (pat
))))
4822 && ! satisfies_constraint_I08 (SET_SRC (pat
)))
4829 /* Return true if the specified insn is a mova insn. */
4831 mova_p (rtx_insn
*insn
)
4833 return (NONJUMP_INSN_P (insn
)
4834 && GET_CODE (PATTERN (insn
)) == SET
4835 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
4836 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
4837 /* Don't match mova_const. */
4838 && GET_CODE (MOVA_LABELREF (insn
)) == LABEL_REF
);
4841 /* Fix up a mova from a switch that went out of range. */
4843 fixup_mova (rtx_insn
*mova
)
4845 PUT_MODE (XEXP (MOVA_LABELREF (mova
), 0), QImode
);
4848 SET_SRC (PATTERN (mova
)) = MOVA_LABELREF (mova
);
4849 INSN_CODE (mova
) = -1;
4853 rtx_insn
*worker
= mova
;
4854 rtx_code_label
*lab
= gen_label_rtx ();
4855 rtx wpat
, wpat0
, wpat1
, wsrc
, target
, base
, diff
;
4859 worker
= NEXT_INSN (worker
);
4861 && !LABEL_P (worker
)
4862 && !JUMP_P (worker
));
4863 } while (NOTE_P (worker
)
4864 || recog_memoized (worker
) != CODE_FOR_casesi_worker_1
);
4865 wpat
= PATTERN (worker
);
4866 wpat0
= XVECEXP (wpat
, 0, 0);
4867 wpat1
= XVECEXP (wpat
, 0, 1);
4868 wsrc
= SET_SRC (wpat0
);
4869 PATTERN (worker
) = (gen_casesi_worker_2
4870 (SET_DEST (wpat0
), XVECEXP (wsrc
, 0, 1),
4871 XEXP (XVECEXP (wsrc
, 0, 2), 0), lab
,
4873 INSN_CODE (worker
) = -1;
4874 target
= XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
4875 base
= gen_rtx_LABEL_REF (Pmode
, lab
);
4876 diff
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, target
, base
), UNSPEC_SYMOFF
);
4877 SET_SRC (PATTERN (mova
)) = gen_rtx_CONST (Pmode
, diff
);
4878 INSN_CODE (mova
) = -1;
4882 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4883 *num_mova, and check if the new mova is not nested within the first one.
4884 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4885 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4887 untangle_mova (int *num_mova
, rtx_insn
**first_mova
, rtx_insn
*new_mova
)
4889 int n_addr
= 0; /* Initialization to shut up spurious warning. */
4890 int f_target
, n_target
= 0; /* Likewise. */
4894 /* If NEW_MOVA has no address yet, it will be handled later. */
4895 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova
))
4898 n_addr
= INSN_ADDRESSES (INSN_UID (new_mova
));
4899 n_target
= INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova
), 0)));
4900 if (n_addr
> n_target
|| n_addr
+ 1022 < n_target
)
4902 /* Change the mova into a load.
4903 broken_move will then return true for it. */
4904 fixup_mova (new_mova
);
4910 *first_mova
= new_mova
;
4915 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova
), 0))))
4920 if (f_target
- INSN_ADDRESSES (INSN_UID (*first_mova
))
4921 > n_target
- n_addr
)
4923 fixup_mova (*first_mova
);
4928 fixup_mova (new_mova
);
4933 /* Find the last barrier from insn FROM which is close enough to hold the
4934 constant pool. If we can't find one, then create one near the end of
4937 find_barrier (int num_mova
, rtx_insn
*mova
, rtx_insn
*from
)
4945 int leading_mova
= num_mova
;
4946 rtx_insn
*barrier_before_mova
= NULL
;
4947 rtx_insn
*found_barrier
= NULL
;
4948 rtx_insn
*good_barrier
= NULL
;
4951 rtx_insn
*orig
= from
;
4952 rtx_insn
*last_got
= NULL
;
4953 rtx_insn
*last_symoff
= NULL
;
4955 /* For HImode: range is 510, add 4 because pc counts from address of
4956 second instruction after this one, subtract 2 for the jump instruction
4957 that we may need to emit before the table, subtract 2 for the instruction
4958 that fills the jump delay slot (in very rare cases, reorg will take an
4959 instruction from after the constant pool or will leave the delay slot
4960 empty). This gives 510.
4961 For SImode: range is 1020, add 4 because pc counts from address of
4962 second instruction after this one, subtract 2 in case pc is 2 byte
4963 aligned, subtract 2 for the jump instruction that we may need to emit
4964 before the table, subtract 2 for the instruction that fills the jump
4965 delay slot. This gives 1018. */
4967 /* The branch will always be shortened now that the reference address for
4968 forward branches is the successor address, thus we need no longer make
4969 adjustments to the [sh]i_limit for -O0. */
4974 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
4976 int inc
= get_attr_length (from
);
4979 /* If this is a label that existed at the time of the compute_alignments
4980 call, determine the alignment. N.B. When find_barrier recurses for
4981 an out-of-reach mova, we might see labels at the start of previously
4982 inserted constant tables. */
4984 && CODE_LABEL_NUMBER (from
) <= max_labelno_before_reorg
)
4987 new_align
= 1 << label_to_alignment (from
).levels
[0].log
;
4988 else if (BARRIER_P (prev_nonnote_insn (from
)))
4989 new_align
= 1 << barrier_align (from
);
4994 /* In case we are scanning a constant table because of recursion, check
4995 for explicit alignments. If the table is long, we might be forced
4996 to emit the new table in front of it; the length of the alignment
4997 might be the last straw. */
4998 else if (NONJUMP_INSN_P (from
)
4999 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
5000 && XINT (PATTERN (from
), 1) == UNSPECV_ALIGN
)
5001 new_align
= INTVAL (XVECEXP (PATTERN (from
), 0, 0));
5002 /* When we find the end of a constant table, paste the new constant
5003 at the end. That is better than putting it in front because
5004 this way, we don't need extra alignment for adding a 4-byte-aligned
5005 mov(a) label to a 2/4 or 8/4 byte aligned table. */
5006 else if (NONJUMP_INSN_P (from
)
5007 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
5008 && XINT (PATTERN (from
), 1) == UNSPECV_CONST_END
)
5011 if (BARRIER_P (from
))
5015 found_barrier
= from
;
5017 /* If we are at the end of the function, or in front of an alignment
5018 instruction, we need not insert an extra alignment. We prefer
5019 this kind of barrier. */
5020 if (barrier_align (from
) > 2)
5021 good_barrier
= from
;
5023 /* If we are at the end of a hot/cold block, dump the constants
5025 next
= NEXT_INSN (from
);
5028 && NOTE_KIND (next
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
5032 if (broken_move (from
))
5037 pat
= PATTERN (from
);
5038 if (GET_CODE (pat
) == PARALLEL
)
5039 pat
= XVECEXP (pat
, 0, 0);
5040 src
= SET_SRC (pat
);
5041 dst
= SET_DEST (pat
);
5042 mode
= GET_MODE (dst
);
5044 /* GOT pcrelat setting comes in pair of
5047 instructions. (plus add r0,r12).
5048 Remember if we see one without the other. */
5049 if (GET_CODE (src
) == UNSPEC
&& PIC_ADDR_P (XVECEXP (src
, 0, 0)))
5050 last_got
= last_got
? NULL
: from
;
5051 else if (PIC_ADDR_P (src
))
5052 last_got
= last_got
? NULL
: from
;
5054 /* We must explicitly check the mode, because sometimes the
5055 front end will generate code to load unsigned constants into
5056 HImode targets without properly sign extending them. */
5058 || (mode
== SImode
&& satisfies_constraint_I16 (src
)
5059 && REGNO (dst
) != FPUL_REG
))
5062 /* We put the short constants before the long constants, so
5063 we must count the length of short constants in the range
5064 for the long constants. */
5065 /* ??? This isn't optimal, but is easy to do. */
5070 /* We dump DF/DI constants before SF/SI ones, because
5071 the limit is the same, but the alignment requirements
5072 are higher. We may waste up to 4 additional bytes
5073 for alignment, and the DF/DI constant may have
5074 another SF/SI constant placed before it. */
5075 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
5077 if (found_si
> count_si
)
5078 count_si
= found_si
;
5079 found_si
+= GET_MODE_SIZE (mode
);
5081 si_limit
-= GET_MODE_SIZE (mode
);
5087 switch (untangle_mova (&num_mova
, &mova
, from
))
5092 rtx src
= SET_SRC (PATTERN (from
));
5093 if (GET_CODE (src
) == CONST
5094 && GET_CODE (XEXP (src
, 0)) == UNSPEC
5095 && XINT (XEXP (src
, 0), 1) == UNSPEC_SYMOFF
)
5099 case 0: return find_barrier (0, 0, mova
);
5104 = good_barrier
? good_barrier
: found_barrier
;
5108 if (found_si
> count_si
)
5109 count_si
= found_si
;
5111 else if (JUMP_TABLE_DATA_P (from
)
5112 && GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
)
5114 if ((num_mova
> 1 && GET_MODE (prev_nonnote_insn (from
)) == VOIDmode
)
5116 && (prev_nonnote_insn (from
)
5117 == XEXP (MOVA_LABELREF (mova
), 0))))
5119 if (barrier_align (next_real_insn (from
)) == align_jumps
.levels
[0].log
)
5121 /* We have just passed the barrier in front of the
5122 ADDR_DIFF_VEC, which is stored in found_barrier. Since
5123 the ADDR_DIFF_VEC is accessed as data, just like our pool
5124 constants, this is a good opportunity to accommodate what
5125 we have gathered so far.
5126 If we waited any longer, we could end up at a barrier in
5127 front of code, which gives worse cache usage for separated
5128 instruction / data caches. */
5129 good_barrier
= found_barrier
;
5134 rtx body
= PATTERN (from
);
5135 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
5138 /* For the SH1, we generate alignments even after jumps-around-jumps. */
5139 else if (JUMP_P (from
)
5144 /* There is a possibility that a bf is transformed into a bf/s by the
5145 delay slot scheduler. */
5147 && get_attr_type (from
) == TYPE_CBRANCH
5148 && ! sequence_insn_p (from
))
5154 if (new_align
> si_align
)
5156 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
5157 si_align
= new_align
;
5159 count_si
= (count_si
+ new_align
- 1) & -new_align
;
5164 if (new_align
> hi_align
)
5166 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
5167 hi_align
= new_align
;
5169 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
5171 from
= NEXT_INSN (from
);
5178 /* Try as we might, the leading mova is out of range. Change
5179 it into a load (which will become a pcload) and retry. */
5181 return find_barrier (0, 0, mova
);
5185 /* Insert the constant pool table before the mova instruction,
5186 to prevent the mova label reference from going out of range. */
5188 good_barrier
= found_barrier
= barrier_before_mova
;
5194 if (good_barrier
&& next_real_insn (found_barrier
))
5195 found_barrier
= good_barrier
;
5199 /* We didn't find a barrier in time to dump our stuff,
5200 so we'll make one. */
5201 rtx_code_label
*label
= gen_label_rtx ();
5203 /* Don't emit a constant table in the middle of insns for
5204 casesi_worker_2. This is a bit overkill but is enough
5205 because casesi_worker_2 wouldn't appear so frequently. */
5209 /* If we exceeded the range, then we must back up over the last
5210 instruction we looked at. Otherwise, we just need to undo the
5211 NEXT_INSN at the end of the loop. */
5212 if (PREV_INSN (from
) != orig
5213 && (count_hi
> hi_limit
|| count_si
> si_limit
))
5214 from
= PREV_INSN (PREV_INSN (from
));
5216 from
= PREV_INSN (from
);
5218 /* Don't emit a constant table int the middle of global pointer setting,
5219 since that that would move the addressing base GOT into another table.
5220 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
5221 in the pool anyway, so just move up the whole constant pool.
5223 However, avoid doing so when the last single GOT mov is the starting
5224 insn itself. Going past above the start insn would create a negative
5225 offset, causing errors. */
5226 if (last_got
&& last_got
!= orig
)
5227 from
= PREV_INSN (last_got
);
5229 /* Don't insert the constant pool table at the position which
5230 may be the landing pad. */
5233 && find_reg_note (from
, REG_EH_REGION
, NULL_RTX
))
5234 from
= PREV_INSN (from
);
5236 /* Walk back to be just before any jump or label.
5237 Putting it before a label reduces the number of times the branch
5238 around the constant pool table will be hit. Putting it before
5239 a jump makes it more likely that the bra delay slot will be
5241 while (NOTE_P (from
) || JUMP_P (from
) || LABEL_P (from
))
5242 from
= PREV_INSN (from
);
5246 bool sibcall_p
= SIBLING_CALL_P (from
);
5248 /* If FROM was a sibling call, then we know that control
5249 will not return. In fact, we were guaranteed to hit
5250 a barrier before another real insn.
5252 The jump around the constant pool is unnecessary. It
5253 costs space, but more importantly it confuses dwarf2cfi
5256 return emit_barrier_after (from
);
5259 from
= emit_jump_insn_after (gen_jump (label
), from
);
5260 JUMP_LABEL (from
) = label
;
5261 LABEL_NUSES (label
) = 1;
5262 found_barrier
= emit_barrier_after (from
);
5263 emit_label_after (label
, found_barrier
);
5266 return found_barrier
;
5269 /* If the instruction INSN is implemented by a special function, and we can
5270 positively find the register that is used to call the sfunc, and this
5271 register is not used anywhere else in this instruction - except as the
5272 destination of a set, return this register; else, return 0. */
5274 sfunc_uses_reg (rtx_insn
*insn
)
5277 rtx pattern
, part
, reg_part
, reg
;
5279 if (!NONJUMP_INSN_P (insn
))
5281 pattern
= PATTERN (insn
);
5282 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
5285 for (reg_part
= NULL_RTX
, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
5287 part
= XVECEXP (pattern
, 0, i
);
5288 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
5293 reg
= XEXP (reg_part
, 0);
5294 for (int i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
5296 part
= XVECEXP (pattern
, 0, i
);
5297 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
5299 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
5300 && REG_P (SET_DEST (part
)))
5301 ? SET_SRC (part
) : part
)))
5307 /* See if the only way in which INSN uses REG is by calling it, or by
5308 setting it while calling it. Set *SET to a SET rtx if the register
5311 noncall_uses_reg (rtx reg
, rtx_insn
*insn
, rtx
*set
)
5315 rtx reg2
= sfunc_uses_reg (insn
);
5316 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
5318 rtx pattern
= single_set (insn
);
5320 && REG_P (SET_DEST (pattern
))
5321 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
5327 /* We don't use rtx_equal_p because we don't care if the mode is
5329 rtx pattern
= single_set (insn
);
5331 && REG_P (SET_DEST (pattern
))
5332 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
5338 par
= PATTERN (insn
);
5339 if (GET_CODE (par
) == PARALLEL
)
5340 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
5342 part
= XVECEXP (par
, 0, i
);
5343 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
5346 return reg_mentioned_p (reg
, SET_SRC (pattern
));
5352 rtx pattern
= PATTERN (insn
);
5354 if (GET_CODE (pattern
) == PARALLEL
)
5356 for (int i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
5357 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
5359 pattern
= XVECEXP (pattern
, 0, 0);
5362 if (GET_CODE (pattern
) == SET
)
5364 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
5366 /* We don't use rtx_equal_p, because we don't care if the
5367 mode is different. */
5368 if (!REG_P (SET_DEST (pattern
))
5369 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
5375 pattern
= SET_SRC (pattern
);
5378 if (GET_CODE (pattern
) != CALL
5379 || !MEM_P (XEXP (pattern
, 0))
5380 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
5386 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5387 general registers. Bits 0..15 mean that the respective registers
5388 are used as inputs in the instruction. Bits 16..31 mean that the
5389 registers 0..15, respectively, are used as outputs, or are clobbered.
5390 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5392 regs_used (rtx x
, int is_dest
)
5400 code
= GET_CODE (x
);
5405 return (((1 << hard_regno_nregs (0, GET_MODE (x
))) - 1)
5406 << (REGNO (x
) + is_dest
));
5410 rtx y
= SUBREG_REG (x
);
5415 return (((1 << hard_regno_nregs (0, GET_MODE (x
))) - 1)
5417 subreg_regno_offset (REGNO (y
),
5420 GET_MODE (x
)) + is_dest
));
5424 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
5426 /* If there was a return value, it must have been indicated with USE. */
5441 fmt
= GET_RTX_FORMAT (code
);
5443 for (int i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5447 for (int j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5448 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
5450 else if (fmt
[i
] == 'e')
5451 used
|= regs_used (XEXP (x
, i
), is_dest
);
5456 /* Create an instruction that prevents redirection of a conditional branch
5457 to the destination of the JUMP with address ADDR.
5458 If the branch needs to be implemented as an indirect jump, try to find
5459 a scratch register for it.
5460 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5461 If any preceding insn that doesn't fit into a delay slot is good enough,
5462 pass 1. Pass 2 if a definite blocking insn is needed.
5463 -1 is used internally to avoid deep recursion.
5464 If a blocking instruction is made or recognized, return it. */
5466 gen_block_redirect (rtx_insn
*jump
, int addr
, int need_block
)
5469 rtx_insn
*prev
= prev_nonnote_insn (jump
);
5471 /* First, check if we already have an instruction that satisfies our need. */
5472 if (prev
&& NONJUMP_INSN_P (prev
) && ! prev
->deleted ())
5474 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
5476 if (GET_CODE (PATTERN (prev
)) == USE
5477 || GET_CODE (PATTERN (prev
)) == CLOBBER
5478 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5480 else if ((need_block
&= ~1) < 0)
5482 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
5485 if (GET_CODE (PATTERN (jump
)) == RETURN
)
5489 /* Reorg even does nasty things with return insns that cause branches
5490 to go out of range - see find_end_label and callers. */
5491 return emit_insn_before (gen_block_branch_redirect (const0_rtx
) , jump
);
5493 /* We can't use JUMP_LABEL here because it might be undefined
5494 when not optimizing. */
5495 rtx dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
5496 /* If the branch is out of range, try to find a scratch register for it. */
5498 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5502 /* Don't look for the stack pointer as a scratch register,
5503 it would cause trouble if an interrupt occurred. */
5504 unsigned attempt
= 0x7fff, used
;
5505 int jump_left
= flag_expensive_optimizations
+ 1;
5507 /* It is likely that the most recent eligible instruction is wanted for
5508 the delay slot. Therefore, find out which registers it uses, and
5509 try to avoid using them. */
5511 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
5513 if (scan
->deleted ())
5515 rtx_code code
= GET_CODE (scan
);
5516 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
5519 && GET_CODE (PATTERN (scan
)) != USE
5520 && GET_CODE (PATTERN (scan
)) != CLOBBER
5521 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
5523 attempt
&= ~regs_used (PATTERN (scan
), 0);
5527 for (used
= dead
= 0, scan
= JUMP_LABEL_AS_INSN (jump
);
5528 (scan
= NEXT_INSN (scan
)); )
5530 if (scan
->deleted ())
5532 rtx_code code
= GET_CODE (scan
);
5535 used
|= regs_used (PATTERN (scan
), 0);
5536 if (code
== CALL_INSN
)
5537 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
5538 dead
|= (used
>> 16) & ~used
;
5544 if (code
== JUMP_INSN
)
5546 if (jump_left
-- && simplejump_p (scan
))
5547 scan
= JUMP_LABEL_AS_INSN (scan
);
5553 /* Mask out the stack pointer again, in case it was
5554 the only 'free' register we have found. */
5557 /* If the immediate destination is still in range, check for possible
5558 threading with a jump beyond the delay slot insn.
5559 Don't check if we are called recursively; the jump has been or will be
5560 checked in a different invocation then. */
5562 else if (optimize
&& need_block
>= 0)
5564 rtx_insn
*next
= next_active_insn (as_a
<rtx_insn
*> (dest
));
5565 next
= next_active_insn (next
);
5566 if (next
&& JUMP_P (next
)
5567 && GET_CODE (PATTERN (next
)) == SET
5568 && recog_memoized (next
) == CODE_FOR_jump_compact
)
5570 dest
= JUMP_LABEL (next
);
5572 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5574 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
5580 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
5582 /* It would be nice if we could convert the jump into an indirect
5583 jump / far branch right now, and thus exposing all constituent
5584 instructions to further optimization. However, reorg uses
5585 simplejump_p to determine if there is an unconditional jump where
5586 it should try to schedule instructions from the target of the
5587 branch; simplejump_p fails for indirect jumps even if they have
5589 rtx_insn
*insn
= emit_insn_before (gen_indirect_jump_scratch
5590 (reg
, GEN_INT (unspec_bbr_uid
++)),
5592 /* ??? We would like this to have the scope of the jump, but that
5593 scope will change when a delay slot insn of an inner scope is added.
5594 Hence, after delay slot scheduling, we'll have to expect
5595 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5598 INSN_LOCATION (insn
) = INSN_LOCATION (jump
);
5599 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
5602 else if (need_block
)
5603 /* We can't use JUMP_LABEL here because it might be undefined
5604 when not optimizing. */
5605 return emit_insn_before (gen_block_branch_redirect
5606 (GEN_INT (unspec_bbr_uid
++)),
5611 #define CONDJUMP_MIN -252
5612 #define CONDJUMP_MAX 262
5615 /* A label (to be placed) in front of the jump
5616 that jumps to our ultimate destination. */
5617 rtx_insn
*near_label
;
5618 /* Where we are going to insert it if we cannot move the jump any farther,
5619 or the jump itself if we have picked up an existing jump. */
5620 rtx_insn
*insert_place
;
5621 /* The ultimate destination. */
5622 rtx_insn
*far_label
;
5623 struct far_branch
*prev
;
5624 /* If the branch has already been created, its address;
5625 else the address of its first prospective user. */
5629 enum mdep_reorg_phase_e mdep_reorg_phase
;
5632 gen_far_branch (struct far_branch
*bp
)
5634 rtx_insn
*insn
= bp
->insert_place
;
5635 rtx_jump_insn
*jump
;
5636 rtx_code_label
*label
= gen_label_rtx ();
5638 emit_label_after (label
, insn
);
5641 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
5642 LABEL_NUSES (bp
->far_label
)++;
5645 jump
= emit_jump_insn_after (gen_return (), insn
);
5647 /* Emit a barrier so that reorg knows that any following instructions
5648 are not reachable via a fall-through path.
5649 But don't do this when not optimizing, since we wouldn't suppress the
5650 alignment for the barrier then, and could end up with out-of-range
5651 pc-relative loads. */
5653 emit_barrier_after (jump
);
5654 emit_label_after (bp
->near_label
, insn
);
5657 JUMP_LABEL (jump
) = bp
->far_label
;
5660 rtx pat
= PATTERN (jump
);
5661 gcc_assert (ANY_RETURN_P (pat
));
5662 JUMP_LABEL (jump
) = pat
;
5665 bool ok
= invert_jump (as_a
<rtx_jump_insn
*> (insn
), label
, 1);
5668 /* If we are branching around a jump (rather than a return), prevent
5669 reorg from using an insn from the jump target as the delay slot insn -
5670 when reorg did this, it pessimized code (we rather hide the delay slot)
5671 and it could cause branches to go out of range. */
5674 (gen_stuff_delay_slot
5675 (GEN_INT (unspec_bbr_uid
++),
5676 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
5678 /* Prevent reorg from undoing our splits. */
5679 gen_block_redirect (jump
, bp
->address
+= 2, 2);
5682 /* Fix up ADDR_DIFF_VECs. */
5684 fixup_addr_diff_vecs (rtx_insn
*first
)
5688 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5690 rtx vec_lab
, pat
, prevpat
, x
, braf_label
;
5693 if (! JUMP_TABLE_DATA_P (insn
)
5694 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
5696 pat
= PATTERN (insn
);
5697 vec_lab
= XEXP (XEXP (pat
, 0), 0);
5699 /* Search the matching casesi_jump_2. */
5700 for (prev
= as_a
<rtx_insn
*> (vec_lab
); ; prev
= PREV_INSN (prev
))
5704 prevpat
= PATTERN (prev
);
5705 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
5707 x
= XVECEXP (prevpat
, 0, 1);
5708 if (GET_CODE (x
) != USE
)
5711 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
5714 /* FIXME: This is a bug in the optimizer, but it seems harmless
5715 to just avoid panicing. */
5719 /* Emit the reference label of the braf where it belongs, right after
5720 the casesi_jump_2 (i.e. braf). */
5721 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
5722 emit_label_after (as_a
<rtx_insn
*> (braf_label
), prev
);
5724 /* Fix up the ADDR_DIF_VEC to be relative
5725 to the reference address of the braf. */
5726 XEXP (XEXP (pat
, 0), 0) = braf_label
;
5730 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5731 a barrier. Return the base 2 logarithm of the desired alignment. */
5733 barrier_align (rtx_insn
*barrier_or_label
)
5735 if (! barrier_or_label
)
5738 if (LABEL_P (barrier_or_label
)
5739 && NEXT_INSN (barrier_or_label
)
5740 && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label
)))
5743 if (BARRIER_P (barrier_or_label
)
5744 && PREV_INSN (barrier_or_label
)
5745 && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label
)))
5747 rtx pat
= PATTERN (PREV_INSN (barrier_or_label
));
5748 /* If this is a very small table, we want to keep the alignment after
5749 the table to the minimum for proper code alignment. */
5750 return ((optimize_size
5751 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
5752 <= (unsigned) 1 << (CACHE_LOG
- 2)))
5753 ? 1 : align_jumps
.levels
[0].log
);
5756 rtx_insn
*next
= next_active_insn (barrier_or_label
);
5761 rtx pat
= PATTERN (next
);
5763 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
5764 /* This is a barrier in front of a constant table. */
5770 if (! TARGET_SH2
|| ! optimize
)
5771 return align_jumps
.levels
[0].log
;
5773 /* When fixing up pcloads, a constant table might be inserted just before
5774 the basic block that ends with the barrier. Thus, we can't trust the
5775 instruction lengths before that. */
5776 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
5778 /* Check if there is an immediately preceding branch to the insn beyond
5779 the barrier. We must weight the cost of discarding useful information
5780 from the current cache line when executing this branch and there is
5781 an alignment, against that of fetching unneeded insn in front of the
5782 branch target when there is no alignment. */
5784 /* There are two delay_slot cases to consider. One is the simple case
5785 where the preceding branch is to the insn beyond the barrier (simple
5786 delay slot filling), and the other is where the preceding branch has
5787 a delay slot that is a duplicate of the insn after the barrier
5788 (fill_eager_delay_slots) and the branch is to the insn after the insn
5789 after the barrier. */
5792 bool jump_to_next
= false;
5794 /* Skip to the insn before the JUMP_INSN before the barrier under
5796 rtx_insn
*prev
= prev_real_insn (prev_active_insn (barrier_or_label
));
5798 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
5799 credit
>= 0 && prev
&& NONJUMP_INSN_P (prev
);
5800 prev
= prev_real_insn (prev
))
5802 jump_to_next
= false;
5803 if (GET_CODE (PATTERN (prev
)) == USE
5804 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
5806 if (rtx_sequence
*prev_seq
= dyn_cast
<rtx_sequence
*> (PATTERN (prev
)))
5808 prev
= prev_seq
->insn (1);
5809 if (INSN_UID (prev
) == INSN_UID (next
))
5811 /* Delay slot was filled with insn at jump target. */
5812 jump_to_next
= true;
5818 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5820 credit
-= get_attr_length (prev
);
5822 if (prev
&& jump_to_label_p (prev
))
5826 || next_real_insn (JUMP_LABEL_AS_INSN (prev
)) == next
5827 /* If relax_delay_slots() decides NEXT was redundant
5828 with some previous instruction, it will have
5829 redirected PREV's jump to the following insn. */
5830 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
5831 /* There is no upper bound on redundant instructions
5832 that might have been skipped, but we must not put an
5833 alignment where none had been before. */
5834 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
5836 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
5837 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
5838 || INSN_CODE (x
) == CODE_FOR_stuff_delay_slot
))))
5840 rtx pat
= PATTERN (prev
);
5841 if (GET_CODE (pat
) == PARALLEL
)
5842 pat
= XVECEXP (pat
, 0, 0);
5843 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
5849 return align_jumps
.levels
[0].log
;
5852 /* If we are inside a phony loop, almost any kind of label can turn up as the
5853 first one in the loop. Aligning a braf label causes incorrect switch
5854 destination addresses; we can detect braf labels because they are
5855 followed by a BARRIER.
5856 Applying loop alignment to small constant or switch tables is a waste
5857 of space, so we suppress this too. */
5859 sh_loop_align (rtx_insn
*label
)
5861 rtx_insn
*next
= label
;
5863 if (! optimize
|| optimize_size
)
5867 next
= next_nonnote_insn (next
);
5868 while (next
&& LABEL_P (next
));
5872 || recog_memoized (next
) == CODE_FOR_consttable_2
)
5875 return align_loops
.levels
[0].log
;
5878 /* Do a final pass over the function, just before delayed branch
5883 rtx_insn
*first
, *insn
, *mova
= NULL
;
5885 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
5886 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
5888 first
= get_insns ();
5889 max_labelno_before_reorg
= max_label_num ();
5891 /* We must split call insns before introducing `mova's. If we're
5892 optimizing, they'll have already been split. Otherwise, make
5893 sure we don't split them too late. */
5895 split_all_insns_noflow ();
5897 /* If relaxing, generate pseudo-ops to associate function calls with
5898 the symbols they call. It does no harm to not generate these
5899 pseudo-ops. However, when we can generate them, it enables the
5900 linker to potentially relax the jsr to a bsr, and eliminate the
5901 register load and, possibly, the constant pool entry. */
5903 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
5906 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5907 own purposes. This works because none of the remaining passes
5908 need to look at them.
5910 ??? But it may break in the future. We should use a machine
5911 dependent REG_NOTE, or some other approach entirely. */
5912 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5918 while ((note
= find_reg_note (insn
, REG_LABEL_OPERAND
,
5920 remove_note (insn
, note
);
5924 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5926 rtx pattern
, reg
, set
, dies
;
5927 rtx_code_label
*label
;
5928 rtx_insn
*link
, *scan
;
5929 int rescan
= 0, foundinsn
= 0;
5933 pattern
= PATTERN (insn
);
5935 if (GET_CODE (pattern
) == PARALLEL
)
5936 pattern
= XVECEXP (pattern
, 0, 0);
5937 if (GET_CODE (pattern
) == SET
)
5938 pattern
= SET_SRC (pattern
);
5940 if (GET_CODE (pattern
) != CALL
5941 || !MEM_P (XEXP (pattern
, 0)))
5944 reg
= XEXP (XEXP (pattern
, 0), 0);
5948 reg
= sfunc_uses_reg (insn
);
5956 /* Try scanning backward to find where the register is set. */
5958 for (scan
= PREV_INSN (insn
);
5959 scan
&& !LABEL_P (scan
);
5960 scan
= PREV_INSN (scan
))
5962 if (! INSN_P (scan
))
5965 if (! reg_mentioned_p (reg
, scan
))
5968 if (noncall_uses_reg (reg
, scan
, &set
))
5981 /* The register is set at LINK. */
5983 /* We can only optimize the function call if the register is
5984 being set to a symbol. In theory, we could sometimes
5985 optimize calls to a constant location, but the assembler
5986 and linker do not support that at present. */
5987 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
5988 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
5991 /* Scan forward from LINK to the place where REG dies, and
5992 make sure that the only insns which use REG are
5993 themselves function calls. */
5995 /* ??? This doesn't work for call targets that were allocated
5996 by reload, since there may not be a REG_DEAD note for the
6000 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
6004 /* Don't try to trace forward past a CODE_LABEL if we haven't
6005 seen INSN yet. Ordinarily, we will only find the setting insn
6006 if it is in the same basic block. However,
6007 cross-jumping can insert code labels in between the load and
6008 the call, and can result in situations where a single call
6009 insn may have two targets depending on where we came from. */
6011 if (LABEL_P (scan
) && ! foundinsn
)
6014 if (! INSN_P (scan
))
6017 /* Don't try to trace forward past a JUMP. To optimize
6018 safely, we would have to check that all the
6019 instructions at the jump destination did not use REG. */
6024 if (! reg_mentioned_p (reg
, scan
))
6027 if (noncall_uses_reg (reg
, scan
, &scanset
))
6034 && (CALL_P (scan
) || sfunc_uses_reg (scan
)))
6036 /* There is a function call to this register other
6037 than the one we are checking. If we optimize
6038 this call, we need to rescan again below. */
6042 /* ??? We shouldn't have to worry about SCANSET here.
6043 We should just be able to check for a REG_DEAD note
6044 on a function call. However, the REG_DEAD notes are
6045 apparently not dependable around libcalls; c-torture
6046 execute/920501-2 is a test case. If SCANSET is set,
6047 then this insn sets the register, so it must have
6048 died earlier. Unfortunately, this will only handle
6049 the cases in which the register is, in fact, set in a
6052 /* ??? We shouldn't have to use FOUNDINSN here.
6053 This dates back to when we used LOG_LINKS to find
6054 the most recent insn which sets the register. */
6058 || find_reg_note (scan
, REG_DEAD
, reg
)))
6067 /* Either there was a branch, or some insn used REG
6068 other than as a function call address. */
6072 /* Create a code label, and put it in a REG_LABEL_OPERAND note
6073 on the insn which sets the register, and on each call insn
6074 which uses the register. In final_prescan_insn we look for
6075 the REG_LABEL_OPERAND notes, and output the appropriate label
6078 label
= gen_label_rtx ();
6079 add_reg_note (link
, REG_LABEL_OPERAND
, label
);
6080 add_reg_note (insn
, REG_LABEL_OPERAND
, label
);
6088 scan
= NEXT_INSN (scan
);
6091 && reg_mentioned_p (reg
, scan
))
6092 || ((reg2
= sfunc_uses_reg (scan
))
6093 && REGNO (reg2
) == REGNO (reg
))))
6094 add_reg_note (scan
, REG_LABEL_OPERAND
, label
);
6096 while (scan
!= dies
);
6102 fixup_addr_diff_vecs (first
);
6106 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
6107 shorten_branches (first
);
6110 /* Scan the function looking for move instructions which have to be
6111 changed to pc-relative loads and insert the literal tables. */
6112 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
6113 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
6117 /* ??? basic block reordering can move a switch table dispatch
6118 below the switch table. Check if that has happened.
6119 We only have the addresses available when optimizing; but then,
6120 this check shouldn't be needed when not optimizing. */
6121 if (!untangle_mova (&num_mova
, &mova
, insn
))
6127 else if (JUMP_TABLE_DATA_P (insn
)
6128 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
6130 /* ??? loop invariant motion can also move a mova out of a
6131 loop. Since loop does this code motion anyway, maybe we
6132 should wrap UNSPEC_MOVA into a CONST, so that reload can
6135 && GET_MODE (prev_nonnote_insn (insn
)) == VOIDmode
)
6136 || (prev_nonnote_insn (insn
)
6137 == XEXP (MOVA_LABELREF (mova
), 0))))
6144 /* Some code might have been inserted between the mova and
6145 its ADDR_DIFF_VEC. Check if the mova is still in range. */
6146 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
6147 total
+= get_attr_length (scan
);
6149 /* range of mova is 1020, add 4 because pc counts from address of
6150 second instruction after this one, subtract 2 in case pc is 2
6151 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
6152 cancels out with alignment effects of the mova itself. */
6155 /* Change the mova into a load, and restart scanning
6156 there. broken_move will then return true for mova. */
6161 if (broken_move (insn
)
6162 || (NONJUMP_INSN_P (insn
)
6163 && recog_memoized (insn
) == CODE_FOR_casesi_worker_2
))
6166 /* Scan ahead looking for a barrier to stick the constant table
6168 rtx_insn
*barrier
= find_barrier (num_mova
, mova
, insn
);
6169 rtx_insn
*last_float_move
= NULL
;
6170 rtx last_float
= 0, *last_float_addr
= NULL
;
6171 int need_aligned_label
= 0;
6173 if (num_mova
&& ! mova_p (mova
))
6175 /* find_barrier had to change the first mova into a
6176 pcload; thus, we have to start with this new pcload. */
6180 /* Now find all the moves between the points and modify them. */
6181 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
6185 if (NONJUMP_INSN_P (scan
)
6186 && recog_memoized (scan
) == CODE_FOR_casesi_worker_2
)
6187 need_aligned_label
= 1;
6188 if (broken_move (scan
))
6190 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
6196 if (GET_CODE (pat
) == PARALLEL
)
6197 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
6198 src
= SET_SRC (pat
);
6199 dst
= SET_DEST (pat
);
6200 mode
= GET_MODE (dst
);
6202 if (mode
== SImode
&& satisfies_constraint_I16 (src
)
6203 && REGNO (dst
) != FPUL_REG
)
6208 while (GET_CODE (dst
) == SUBREG
)
6210 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
6211 GET_MODE (SUBREG_REG (dst
)),
6214 dst
= SUBREG_REG (dst
);
6216 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
6218 if (REG_P (dst
) && FP_ANY_REGISTER_P (REGNO (dst
)))
6220 /* This must be an insn that clobbers r0. */
6221 rtx
*clobberp
= &XVECEXP (PATTERN (scan
), 0,
6222 XVECLEN (PATTERN (scan
), 0)
6224 rtx clobber
= *clobberp
;
6226 gcc_assert (GET_CODE (clobber
) == CLOBBER
6227 && rtx_equal_p (XEXP (clobber
, 0), r0_rtx
));
6230 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
6232 lab
= add_constant (src
, mode
, last_float
);
6234 emit_insn_before (gen_mova (lab
), scan
);
6237 /* There will be a REG_UNUSED note for r0 on
6238 LAST_FLOAT_MOVE; we have to change it to REG_INC,
6239 lest reorg:mark_target_live_regs will not
6240 consider r0 to be used, and we end up with delay
6241 slot insn in front of SCAN that clobbers r0. */
6243 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
6245 /* If we are not optimizing, then there may not be
6248 PUT_REG_NOTE_KIND (note
, REG_INC
);
6250 *last_float_addr
= r0_inc_rtx
;
6252 last_float_move
= scan
;
6254 newsrc
= gen_const_mem (mode
,
6255 (((TARGET_SH4
&& ! TARGET_FMOVD
)
6256 || REGNO (dst
) == FPUL_REG
)
6259 last_float_addr
= &XEXP (newsrc
, 0);
6261 /* Remove the clobber of r0. */
6262 *clobberp
= gen_rtx_CLOBBER (GET_MODE (clobber
),
6263 gen_rtx_SCRATCH (Pmode
));
6265 /* This is a mova needing a label. Create it. */
6266 else if (GET_CODE (src
) == UNSPEC
6267 && XINT (src
, 1) == UNSPEC_MOVA
6268 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
6270 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
6271 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
6272 newsrc
= gen_rtx_UNSPEC (SImode
,
6273 gen_rtvec (1, newsrc
),
6276 else if (GET_CODE (src
) == UNSPEC_VOLATILE
6277 && XINT (src
, 1) == UNSPECV_SP_SWITCH_B
)
6279 newsrc
= XVECEXP (src
, 0, 0);
6280 XVECEXP (src
, 0, 0) = gen_const_mem (mode
, newsrc
);
6281 INSN_CODE (scan
) = -1;
6286 lab
= add_constant (src
, mode
, 0);
6287 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
6288 newsrc
= gen_const_mem (mode
, newsrc
);
6290 *patp
= gen_rtx_SET (dst
, newsrc
);
6291 INSN_CODE (scan
) = -1;
6294 dump_table (need_aligned_label
? insn
: 0, barrier
);
6298 label_ref_list_d_pool
.release ();
6299 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6300 PUT_MODE (insn
, VOIDmode
);
6302 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
6303 INSN_ADDRESSES_FREE ();
6304 split_branches (first
);
6306 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
6307 also has an effect on the register that holds the address of the sfunc.
6308 Insert an extra dummy insn in front of each sfunc that pretends to
6309 use this register. */
6310 if (flag_delayed_branch
)
6312 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6314 rtx reg
= sfunc_uses_reg (insn
);
6318 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
6321 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
6324 /* Return the UID of the insn that follows the specified label. */
6326 get_dest_uid (rtx_insn
*label
, int max_uid
)
6328 rtx_insn
*dest
= next_real_insn (label
);
6331 /* This can happen for an undefined label. */
6333 int dest_uid
= INSN_UID (dest
);
6334 /* If this is a newly created branch redirection blocking instruction,
6335 we cannot index the branch_uid or insn_addresses arrays with its
6336 uid. But then, we won't need to, because the actual destination is
6337 the following branch. */
6338 while (dest_uid
>= max_uid
)
6340 dest
= NEXT_INSN (dest
);
6341 dest_uid
= INSN_UID (dest
);
6343 if (JUMP_P (dest
) && GET_CODE (PATTERN (dest
)) == RETURN
)
6348 /* Split condbranches that are out of range. Also add clobbers for
6349 scratch registers that are needed in far jumps.
6350 We do this before delay slot scheduling, so that it can take our
6351 newly created instructions into account. It also allows us to
6352 find branches with common targets more easily. */
6354 split_branches (rtx_insn
*first
)
6357 struct far_branch
**uid_branch
, *far_branch_list
= 0;
6358 int max_uid
= get_max_uid ();
6361 /* Find out which branches are out of range. */
6362 shorten_branches (first
);
6364 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
6365 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
6367 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6368 if (! INSN_P (insn
))
6370 else if (insn
->deleted ())
6372 /* Shorten_branches would split this instruction again,
6373 so transform it into a note. */
6374 SET_INSN_DELETED (insn
);
6376 else if (JUMP_P (insn
))
6378 enum attr_type type
= get_attr_type (insn
);
6379 if (type
== TYPE_CBRANCH
)
6381 rtx_insn
*next
, *beyond
;
6383 if (get_attr_length (insn
) > 4)
6385 rtx src
= SET_SRC (PATTERN (insn
));
6386 rtx_insn
*olabel
= safe_as_a
<rtx_insn
*> (XEXP (XEXP (src
, 1), 0));
6387 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6388 rtx_insn
*label
= 0;
6389 int dest_uid
= get_dest_uid (olabel
, max_uid
);
6390 struct far_branch
*bp
= uid_branch
[dest_uid
];
6392 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6393 the label if the LABEL_NUSES count drops to zero. There is
6394 always a jump_optimize pass that sets these values, but it
6395 proceeds to delete unreferenced code, and then if not
6396 optimizing, to un-delete the deleted instructions, thus
6397 leaving labels with too low uses counts. */
6400 JUMP_LABEL (insn
) = olabel
;
6401 LABEL_NUSES (olabel
)++;
6405 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6406 uid_branch
[dest_uid
] = bp
;
6407 bp
->prev
= far_branch_list
;
6408 far_branch_list
= bp
;
6409 bp
->far_label
= as_a
<rtx_insn
*> (
6410 XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
6412 LABEL_NUSES (bp
->far_label
)++;
6416 label
= bp
->near_label
;
6417 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
6419 rtx_insn
*block
= bp
->insert_place
;
6421 if (GET_CODE (PATTERN (block
)) == RETURN
)
6422 block
= PREV_INSN (block
);
6424 block
= gen_block_redirect (block
,
6426 label
= emit_label_after (gen_label_rtx (),
6428 bp
->near_label
= label
;
6430 else if (label
&& ! NEXT_INSN (label
))
6432 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
6433 bp
->insert_place
= insn
;
6435 gen_far_branch (bp
);
6439 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
6441 bp
->near_label
= label
= gen_label_rtx ();
6442 bp
->insert_place
= insn
;
6445 ok
= redirect_jump (as_a
<rtx_jump_insn
*> (insn
), label
, 0);
6450 /* get_attr_length (insn) == 2 */
6451 /* Check if we have a pattern where reorg wants to redirect
6452 the branch to a label from an unconditional branch that
6454 /* We can't use JUMP_LABEL here because it might be undefined
6455 when not optimizing. */
6456 /* A syntax error might cause beyond to be NULL_RTX. */
6457 rtx temp
= XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
6458 beyond
= next_active_insn (as_a
<rtx_insn
*> (temp
));
6462 || ((beyond
= next_active_insn (beyond
))
6463 && JUMP_P (beyond
)))
6464 && GET_CODE (PATTERN (beyond
)) == SET
6465 && recog_memoized (beyond
) == CODE_FOR_jump_compact
6467 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
6468 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6470 gen_block_redirect (beyond
,
6471 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
6474 next
= next_active_insn (insn
);
6478 || ((next
= next_active_insn (next
))
6480 && GET_CODE (PATTERN (next
)) == SET
6481 && recog_memoized (next
) == CODE_FOR_jump_compact
6483 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
6484 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6486 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
6488 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
6490 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6491 rtx_insn
*far_label
= 0;
6493 struct far_branch
*bp
;
6495 if (type
== TYPE_JUMP
)
6497 if (CROSSING_JUMP_P (insn
))
6499 emit_insn_before (gen_block_branch_redirect (const0_rtx
),
6504 far_label
= as_a
<rtx_insn
*> (
6505 XEXP (SET_SRC (PATTERN (insn
)), 0));
6506 dest_uid
= get_dest_uid (far_label
, max_uid
);
6509 /* Parse errors can lead to labels outside
6511 if (! NEXT_INSN (far_label
))
6516 JUMP_LABEL (insn
) = far_label
;
6517 LABEL_NUSES (far_label
)++;
6519 redirect_jump (as_a
<rtx_jump_insn
*> (insn
), ret_rtx
, 1);
6523 bp
= uid_branch
[dest_uid
];
6526 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6527 uid_branch
[dest_uid
] = bp
;
6528 bp
->prev
= far_branch_list
;
6529 far_branch_list
= bp
;
6531 bp
->far_label
= far_label
;
6533 LABEL_NUSES (far_label
)++;
6535 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
6536 if (addr
- bp
->address
<= CONDJUMP_MAX
)
6537 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
6540 gen_far_branch (bp
);
6546 bp
->insert_place
= insn
;
6548 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
6550 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
6553 /* Generate all pending far branches,
6554 and free our references to the far labels. */
6555 while (far_branch_list
)
6557 if (far_branch_list
->near_label
6558 && ! NEXT_INSN (far_branch_list
->near_label
))
6559 gen_far_branch (far_branch_list
);
6561 && far_branch_list
->far_label
6562 && ! --LABEL_NUSES (far_branch_list
->far_label
))
6563 delete_insn (far_branch_list
->far_label
);
6564 far_branch_list
= far_branch_list
->prev
;
6567 /* Instruction length information is no longer valid due to the new
6568 instructions that have been generated. */
6569 init_insn_lengths ();
6572 /* Dump out instruction addresses, which is useful for debugging the
6573 constant pool table stuff.
6575 If relaxing, output the label and pseudo-ops used to link together
6576 calls and the instruction which set the registers.
6578 ??? The addresses printed by this routine for insns are nonsense for
6579 insns which are inside of a sequence where none of the inner insns have
6580 variable length. This is because the second pass of shorten_branches
6581 does not bother to update them. */
6583 final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
6584 int noperands ATTRIBUTE_UNUSED
)
6586 if (TARGET_DUMPISIZE
)
6587 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
6591 if (rtx note
= find_reg_note (insn
, REG_LABEL_OPERAND
, NULL_RTX
))
6593 rtx pattern
= PATTERN (insn
);
6594 if (GET_CODE (pattern
) == PARALLEL
)
6595 pattern
= XVECEXP (pattern
, 0, 0);
6596 switch (GET_CODE (pattern
))
6599 if (GET_CODE (SET_SRC (pattern
)) != CALL
6600 && get_attr_type (insn
) != TYPE_SFUNC
)
6602 targetm
.asm_out
.internal_label
6603 (asm_out_file
, "L", CODE_LABEL_NUMBER (XEXP (note
, 0)));
6608 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
6609 CODE_LABEL_NUMBER (XEXP (note
, 0)));
6619 /* Dump out any constants accumulated in the final pass. These will
6622 output_jump_label_table (void)
6626 fprintf (asm_out_file
, "\t.align 2\n");
6627 for (int i
= 0; i
< pool_size
; i
++)
6629 pool_node
*p
= &pool_vector
[i
];
6631 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
6632 CODE_LABEL_NUMBER (p
->label
));
6633 output_asm_insn (".long %O0", &p
->value
);
6641 /* A full frame looks like:
6645 [ if current_function_anonymous_args
6658 local-0 <- fp points here.
6660 Number of bytes pushed for anonymous args, used to pass information
6661 between expand_prologue and expand_epilogue.
6663 Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6664 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6665 for an epilogue and a negative value means that it's for a sibcall
6666 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6667 all the registers that are about to be restored, and hence dead. */
6669 output_stack_adjust (int size
, rtx reg
, int epilogue_p
,
6670 HARD_REG_SET
*live_regs_mask
, bool frame_p
)
6672 rtx_insn
*(*emit_fn
) (rtx
) = frame_p
? &emit_frame_insn
: &emit_insn
;
6675 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6677 /* This test is bogus, as output_stack_adjust is used to re-align the
6680 gcc_assert (!(size
% align
));
6683 if (CONST_OK_FOR_ADD (size
))
6684 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
6685 /* Try to do it with two partial adjustments; however, we must make
6686 sure that the stack is properly aligned at all times, in case
6687 an interrupt occurs between the two partial adjustments. */
6688 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
6689 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
6691 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
6692 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
6698 int temp
= epilogue_p
? 7 : 1;
6701 /* If TEMP is invalid, we could temporarily save a general
6702 register to MACL. However, there is currently no need
6703 to handle this case, so just die when we see it. */
6705 || current_function_interrupt
6706 || ! call_really_used_regs
[temp
] || fixed_regs
[temp
])
6708 if (temp
< 0 && ! current_function_interrupt
&& epilogue_p
>= 0)
6710 HARD_REG_SET temps
= call_used_reg_set
& ~call_fixed_reg_set
;
6714 if (crtl
->return_rtx
)
6717 mode
= GET_MODE (crtl
->return_rtx
);
6718 if (BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
)
6719 nreg
= hard_regno_nregs (FIRST_RET_REG
, mode
);
6721 for (i
= 0; i
< nreg
; i
++)
6722 CLEAR_HARD_REG_BIT (temps
, FIRST_RET_REG
+ i
);
6723 if (crtl
->calls_eh_return
)
6725 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_STACKADJ_REGNO
);
6726 for (i
= 0; i
<= 3; i
++)
6727 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_DATA_REGNO (i
));
6730 if (epilogue_p
<= 0)
6732 for (i
= FIRST_PARM_REG
;
6733 i
< FIRST_PARM_REG
+ NPARM_REGS (SImode
); i
++)
6734 CLEAR_HARD_REG_BIT (temps
, i
);
6735 if (cfun
->static_chain_decl
!= NULL
)
6736 CLEAR_HARD_REG_BIT (temps
, STATIC_CHAIN_REGNUM
);
6738 temp
= scavenge_reg (&temps
);
6740 if (temp
< 0 && live_regs_mask
)
6744 temps
= *live_regs_mask
;
6745 CLEAR_HARD_REG_BIT (temps
, REGNO (reg
));
6746 temp
= scavenge_reg (&temps
);
6750 rtx adj_reg
, tmp_reg
, mem
;
6752 /* If we reached here, the most likely case is the (sibcall)
6753 epilogue. Put a special push/pop sequence for such case as
6754 the last resort. This looks lengthy but would not be problem
6755 because it seems to be very rare. */
6756 gcc_assert (epilogue_p
);
6758 /* ??? There is still the slight possibility that r4 or
6759 r5 have been reserved as fixed registers or assigned
6760 as global registers, and they change during an
6761 interrupt. There are possible ways to handle this:
6763 - If we are adjusting the frame pointer (r14), we can do
6764 with a single temp register and an ordinary push / pop
6766 - Grab any call-used or call-saved registers (i.e. not
6767 fixed or globals) for the temps we need. We might
6768 also grab r14 if we are adjusting the stack pointer.
6769 If we can't find enough available registers, issue
6770 a diagnostic and die - the user must have reserved
6771 way too many registers.
6772 But since all this is rather unlikely to happen and
6773 would require extra testing, we just die if r4 / r5
6774 are not available. */
6775 gcc_assert (!fixed_regs
[4] && !fixed_regs
[5]
6776 && !global_regs
[4] && !global_regs
[5]);
6778 adj_reg
= gen_rtx_REG (GET_MODE (reg
), 4);
6779 tmp_reg
= gen_rtx_REG (GET_MODE (reg
), 5);
6780 emit_move_insn (gen_tmp_stack_mem (Pmode
, reg
), adj_reg
);
6781 emit_insn (GEN_MOV (adj_reg
, GEN_INT (size
)));
6782 emit_insn (GEN_ADD3 (adj_reg
, adj_reg
, reg
));
6783 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
6784 emit_move_insn (mem
, tmp_reg
);
6785 emit_move_insn (tmp_reg
, gen_tmp_stack_mem (Pmode
, reg
));
6786 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
6787 emit_move_insn (mem
, tmp_reg
);
6788 emit_move_insn (reg
, adj_reg
);
6789 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
6790 emit_move_insn (adj_reg
, mem
);
6791 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
6792 emit_move_insn (tmp_reg
, mem
);
6793 /* Tell flow the insns that pop r4/r5 aren't dead. */
6798 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
6800 /* If SIZE is negative, subtract the positive value.
6801 This sometimes allows a constant pool entry to be shared
6802 between prologue and epilogue code. */
6805 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
6806 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
6810 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
6811 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
6813 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
6814 gen_rtx_SET (reg
, gen_rtx_PLUS (SImode
, reg
,
6820 /* Emit the specified insn and mark it as frame related. */
6822 emit_frame_insn (rtx x
)
6824 rtx_insn
*insn
= emit_insn (x
);
6825 RTX_FRAME_RELATED_P (insn
) = 1;
6829 /* Output RTL to push register RN onto the stack. */
6835 x
= gen_push_fpul ();
6836 else if (rn
== FPSCR_REG
)
6837 x
= gen_push_fpscr ();
6838 else if (TARGET_FPU_DOUBLE
&& TARGET_FMOVD
6839 && ! TARGET_FPU_SINGLE
&& FP_OR_XD_REGISTER_P (rn
))
6841 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
6843 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
6845 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
6846 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
6848 x
= gen_push (gen_rtx_REG (SImode
, rn
));
6850 x
= emit_frame_insn (x
);
6851 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
6855 /* Output RTL to pop register RN from the stack. */
6861 x
= gen_pop_fpul ();
6862 else if (rn
== FPSCR_REG
)
6863 x
= gen_pop_fpscr ();
6864 else if (TARGET_FPU_DOUBLE
&& TARGET_FMOVD
6865 && ! TARGET_FPU_SINGLE
&& FP_OR_XD_REGISTER_P (rn
))
6867 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
6869 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
6871 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
6872 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
6874 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
6878 sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
6879 reg
= copy_rtx (GET_CODE (PATTERN (x
)) == PARALLEL
6880 ? SET_DEST (XVECEXP (PATTERN (x
), 0, 0))
6881 : SET_DEST (PATTERN (x
)));
6882 add_reg_note (x
, REG_CFA_RESTORE
, reg
);
6883 add_reg_note (x
, REG_CFA_ADJUST_CFA
,
6884 gen_rtx_SET (sp_reg
,
6885 plus_constant (SImode
, sp_reg
,
6886 GET_MODE_SIZE (GET_MODE (reg
)))));
6887 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
6888 RTX_FRAME_RELATED_P (x
) = 1;
6891 /* Generate code to push the regs specified in the mask. */
6893 push_regs (HARD_REG_SET
*mask
, bool interrupt_handler
)
6895 bool skip_fpscr
= false;
6897 /* Push PR last; this gives better latencies after the prologue, and
6898 candidates for the return delay slot when there are no general
6899 registers pushed. */
6900 for (int i
= interrupt_handler
? LAST_BANKED_REG
+ 1 : 0;
6901 i
< FIRST_PSEUDO_REGISTER
; i
++)
6903 /* If this is an interrupt handler, and the SZ bit varies,
6904 and we have to push any floating point register, we need
6905 to switch to the correct precision first. */
6906 if (i
== FIRST_FP_REG
&& interrupt_handler
&& TARGET_FMOVD
6907 && hard_reg_set_intersect_p (*mask
, reg_class_contents
[DF_REGS
]))
6910 fpscr_set_from_mem (NORMAL_MODE (FP_MODE
), ~*mask
);
6914 && (i
!= FPSCR_REG
|| ! skip_fpscr
)
6915 && TEST_HARD_REG_BIT (*mask
, i
))
6917 /* If the ISR has RESBANK attribute assigned, don't push any of
6918 the following registers - R0-R14, MACH, MACL and GBR. */
6919 if (! (sh_cfun_resbank_handler_p ()
6920 && ((i
>= FIRST_GENERAL_REG
&& i
< LAST_GENERAL_REG
)
6928 /* Push banked registers last to improve delay slot opportunities. */
6929 if (interrupt_handler
)
6931 bool use_movml
= false;
6935 unsigned int count
= 0;
6937 for (int i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
6938 if (TEST_HARD_REG_BIT (*mask
, i
))
6943 /* Use movml when all banked registers are pushed. */
6944 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
6948 if (sh_cfun_resbank_handler_p ())
6952 rtx x
, mem
, reg
, set
;
6953 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
6955 /* We must avoid scheduling multiple store insn with another
6957 emit_insn (gen_blockage ());
6958 x
= gen_movml_push_banked (sp_reg
);
6959 x
= emit_frame_insn (x
);
6960 for (int i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
6962 mem
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp_reg
, i
* 4));
6963 reg
= gen_rtx_REG (SImode
, i
);
6964 add_reg_note (x
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, reg
));
6967 set
= gen_rtx_SET (sp_reg
, plus_constant (Pmode
, sp_reg
, - 32));
6968 add_reg_note (x
, REG_CFA_ADJUST_CFA
, set
);
6969 emit_insn (gen_blockage ());
6972 for (int i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
6973 if (TEST_HARD_REG_BIT (*mask
, i
))
6977 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6978 if (TEST_HARD_REG_BIT (*mask
, PR_REG
) && !sh_cfun_resbank_handler_p ())
6982 /* Work out the registers which need to be saved, both as a mask and a
6983 count of saved words. Return the count.
6985 If doing a pragma interrupt function, then push all regs used by the
6986 function, and if we call another function (we can tell by looking at PR),
6987 make sure that all the regs it clobbers are safe too. */
6989 calc_live_regs (HARD_REG_SET
*live_regs_mask
)
6993 bool interrupt_or_trapa_handler
, trapa_handler
, interrupt_handler
;
6994 bool nosave_low_regs
;
6996 attrs
= DECL_ATTRIBUTES (current_function_decl
);
6997 interrupt_or_trapa_handler
= sh_cfun_interrupt_handler_p ();
6998 trapa_handler
= lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
;
6999 interrupt_handler
= interrupt_or_trapa_handler
&& ! trapa_handler
;
7000 nosave_low_regs
= lookup_attribute ("nosave_low_regs", attrs
) != NULL_TREE
;
7002 CLEAR_HARD_REG_SET (*live_regs_mask
);
7003 if (TARGET_FPU_DOUBLE
&& TARGET_FMOVD
&& interrupt_handler
7004 && df_regs_ever_live_p (FPSCR_REG
))
7005 target_flags
&= ~MASK_FPU_SINGLE
;
7006 /* If we can save a lot of saves by switching to double mode, do that. */
7007 else if (TARGET_FPU_DOUBLE
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
7008 for (int count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
7009 if (df_regs_ever_live_p (reg
) && df_regs_ever_live_p (reg
+1)
7010 && (! call_really_used_regs
[reg
]
7011 || interrupt_handler
)
7014 target_flags
&= ~MASK_FPU_SINGLE
;
7019 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
7020 bool pr_live
= (pr_initial
7021 ? (!REG_P (pr_initial
)
7022 || REGNO (pr_initial
) != (PR_REG
))
7023 : df_regs_ever_live_p (PR_REG
));
7024 /* For Shcompact, if not optimizing, we end up with a memory reference
7025 using the return address pointer for __builtin_return_address even
7026 though there is no actual need to put the PR register on the stack. */
7027 pr_live
|= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM
);
7029 /* Force PR to be live if the prologue has to call the SHmedia
7030 argument decoder or register saver. */
7031 bool has_call
= pr_live
;
7034 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
; reg
-- != 0; )
7039 ? (/* Need to save all the regs ever live. */
7040 (df_regs_ever_live_p (reg
)
7041 || (call_really_used_regs
[reg
]
7042 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
7043 || reg
== PIC_OFFSET_TABLE_REGNUM
)
7045 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
7046 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
7047 && reg
!= T_REG
&& reg
!= GBR_REG
7048 && reg
!= FPSCR_MODES_REG
&& reg
!= FPSCR_STAT_REG
7049 /* Push fpscr only on targets which have FPU */
7050 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
7051 : (/* Only push those regs which are used and need to be saved. */
7053 || (df_regs_ever_live_p (reg
)
7054 && ((!call_really_used_regs
[reg
]
7055 && !(reg
!= PIC_OFFSET_TABLE_REGNUM
7056 && fixed_regs
[reg
] && call_used_regs
[reg
]))
7057 || (trapa_handler
&& reg
== FPSCR_REG
&& TARGET_FPU_ANY
)))
7058 || (crtl
->calls_eh_return
7059 && (reg
== EH_RETURN_DATA_REGNO (0)
7060 || reg
== EH_RETURN_DATA_REGNO (1)
7061 || reg
== EH_RETURN_DATA_REGNO (2)
7062 || reg
== EH_RETURN_DATA_REGNO (3)))
7063 || ((reg
== MACL_REG
|| reg
== MACH_REG
)
7064 && df_regs_ever_live_p (reg
)
7065 && sh_cfun_attr_renesas_p ())
7068 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
7069 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7071 if (TARGET_FPU_DOUBLE
&& TARGET_FMOVD
7072 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
7074 if (FP_REGISTER_P (reg
))
7076 if (! TARGET_FPU_SINGLE
&& ! df_regs_ever_live_p (reg
^ 1))
7078 SET_HARD_REG_BIT (*live_regs_mask
, (reg
^ 1));
7079 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
7082 else if (XD_REGISTER_P (reg
))
7084 /* Must switch to double mode to access these registers. */
7085 target_flags
&= ~MASK_FPU_SINGLE
;
7089 if (nosave_low_regs
&& reg
== R8_REG
)
7096 /* Code to generate prologue and epilogue sequences */
7098 /* PUSHED is the number of bytes that are being pushed on the
7099 stack for register saves. Return the frame size, padded
7100 appropriately so that the stack stays properly aligned. */
7101 static HOST_WIDE_INT
7102 rounded_frame_size (int pushed
)
7104 HOST_WIDE_INT size
= get_frame_size ();
7105 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7107 if (ACCUMULATE_OUTGOING_ARGS
)
7108 size
+= crtl
->outgoing_args_size
;
7110 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
7113 /* Expand code for the function prologue. */
7115 sh_expand_prologue (void)
7117 int save_flags
= target_flags
;
7119 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
));
7121 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
7123 /* We have pretend args if we had an object sent partially in registers
7124 and partially on the stack, e.g. a large structure. */
7125 int pretend_args
= crtl
->args
.pretend_args_size
;
7126 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
)
7127 && (NPARM_REGS(SImode
)
7128 > crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]))
7131 output_stack_adjust (-pretend_args
, stack_pointer_rtx
, 0, NULL
, true);
7132 int stack_usage
= pretend_args
;
7134 /* Emit the code for SETUP_VARARGS. */
7137 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
7139 /* Push arg regs as if they'd been provided by caller in stack. */
7140 for (int i
= 0; i
< NPARM_REGS(SImode
); i
++)
7142 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
7144 if (i
>= (NPARM_REGS(SImode
)
7145 - crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]
7149 stack_usage
+= GET_MODE_SIZE (SImode
);
7154 /* If we're supposed to switch stacks at function entry, do so now. */
7158 /* The argument specifies a variable holding the address of the
7159 stack the interrupt function should switch to/from at entry/exit. */
7160 tree arg
= TREE_VALUE ( TREE_VALUE (sp_switch_attr
));
7161 const char* s
= ggc_strdup (TREE_STRING_POINTER (arg
));
7162 rtx sp_switch
= gen_rtx_SYMBOL_REF (Pmode
, s
);
7164 lab
= add_constant (sp_switch
, SImode
, 0);
7165 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
7167 emit_insn (gen_sp_switch_1 (newsrc
));
7170 HARD_REG_SET live_regs_mask
;
7171 int d
= calc_live_regs (&live_regs_mask
);
7172 /* ??? Maybe we could save some switching if we can move a mode switch
7173 that already happens to be at the function start into the prologue. */
7174 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7175 emit_insn (gen_toggle_sz ());
7177 push_regs (&live_regs_mask
, current_function_interrupt
);
7180 if (flag_pic
&& !TARGET_FDPIC
7181 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7182 emit_insn (gen_GOTaddr2picreg (const0_rtx
));
7184 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7185 emit_insn (gen_toggle_sz ());
7187 target_flags
= save_flags
;
7189 output_stack_adjust (-rounded_frame_size (d
),
7190 stack_pointer_rtx
, 0, NULL
, true);
7191 stack_usage
+= rounded_frame_size (d
);
7193 if (frame_pointer_needed
)
7194 emit_frame_insn (GEN_MOV (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7196 /* If we are profiling, make sure no instructions are scheduled before
7197 the call to mcount. Similarly if some call instructions are swapped
7198 before frame related insns, it'll confuse the unwinder because
7199 currently SH has no unwind info for function epilogues. */
7200 if (crtl
->profile
|| flag_exceptions
|| flag_unwind_tables
)
7201 emit_insn (gen_blockage ());
7203 if (flag_stack_usage_info
)
7204 current_function_static_stack_size
= stack_usage
;
7207 /* Expand code for the function epilogue. */
7209 sh_expand_epilogue (bool sibcall_p
)
7211 int save_flags
= target_flags
;
7212 bool fpscr_deferred
= false;
7213 int e
= sibcall_p
? -1 : 1;
7215 HARD_REG_SET live_regs_mask
;
7216 int d
= calc_live_regs (&live_regs_mask
);
7219 int frame_size
= rounded_frame_size (d
);
7221 if (frame_pointer_needed
)
7223 /* We must avoid scheduling the epilogue with previous basic blocks.
7224 See PR/18032 and PR/40313. */
7225 emit_insn (gen_blockage ());
7226 output_stack_adjust (frame_size
, hard_frame_pointer_rtx
, e
,
7227 &live_regs_mask
, true);
7229 /* We must avoid moving the stack pointer adjustment past code
7230 which reads from the local frame, else an interrupt could
7231 occur after the SP adjustment and clobber data in the local
7233 emit_insn (gen_blockage ());
7234 emit_frame_insn (GEN_MOV (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7236 else if (frame_size
)
7238 /* We must avoid moving the stack pointer adjustment past code
7239 which reads from the local frame, else an interrupt could
7240 occur after the SP adjustment and clobber data in the local
7242 emit_insn (gen_blockage ());
7243 output_stack_adjust (frame_size
, stack_pointer_rtx
, e
,
7244 &live_regs_mask
, true);
7247 /* Pop all the registers. */
7249 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7250 emit_insn (gen_toggle_sz ());
7256 /* For an ISR with RESBANK attribute assigned, don't pop PR
7258 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
)
7259 && !sh_cfun_resbank_handler_p ())
7261 if (!frame_pointer_needed
)
7262 emit_insn (gen_blockage ());
7266 /* Banked registers are popped first to avoid being scheduled in the
7267 delay slot. RTE switches banks before the ds instruction. */
7268 if (current_function_interrupt
)
7270 bool use_movml
= false;
7274 unsigned int count
= 0;
7276 for (int i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7277 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
7282 /* Use movml when all banked register are poped. */
7283 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
7287 if (sh_cfun_resbank_handler_p ())
7291 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
7293 /* We must avoid scheduling multiple load insn with another
7295 emit_insn (gen_blockage ());
7296 emit_insn (gen_movml_pop_banked (sp_reg
));
7297 emit_insn (gen_blockage ());
7300 for (int i
= LAST_BANKED_REG
; i
>= FIRST_BANKED_REG
; i
--)
7301 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
7304 last_reg
= FIRST_PSEUDO_REGISTER
- LAST_BANKED_REG
- 1;
7307 last_reg
= FIRST_PSEUDO_REGISTER
;
7309 for (int i
= 0; i
< last_reg
; i
++)
7311 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
7313 if (j
== FPSCR_REG
&& current_function_interrupt
&& TARGET_FMOVD
7314 && hard_reg_set_intersect_p (live_regs_mask
,
7315 reg_class_contents
[DF_REGS
]))
7316 fpscr_deferred
= true;
7317 /* For an ISR with RESBANK attribute assigned, don't pop
7318 following registers, R0-R14, MACH, MACL and GBR. */
7319 else if (j
!= PR_REG
&& TEST_HARD_REG_BIT (live_regs_mask
, j
)
7320 && ! (sh_cfun_resbank_handler_p ()
7321 && ((j
>= FIRST_GENERAL_REG
7322 && j
< LAST_GENERAL_REG
)
7328 if (j
== FIRST_FP_REG
&& fpscr_deferred
)
7332 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7333 emit_insn (gen_toggle_sz ());
7334 target_flags
= save_flags
;
7336 output_stack_adjust (crtl
->args
.pretend_args_size
+ save_size
,
7337 stack_pointer_rtx
, e
, NULL
, true);
7339 if (crtl
->calls_eh_return
)
7340 emit_insn (GEN_ADD3 (stack_pointer_rtx
, stack_pointer_rtx
,
7341 EH_RETURN_STACKADJ_RTX
));
7343 /* Switch back to the normal stack if necessary. */
7344 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
)))
7345 emit_insn (gen_sp_switch_2 ());
7347 /* Tell flow the insn that pops PR isn't dead. */
7348 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
7349 emit_use (gen_rtx_REG (SImode
, PR_REG
));
7352 /* Emit code to change the current function's return address to RA.
7353 TEMP is available as a scratch register, if needed. */
7355 sh_set_return_address (rtx ra
, rtx tmp
)
7357 HARD_REG_SET live_regs_mask
;
7358 int d
= calc_live_regs (&live_regs_mask
);
7360 /* If pr_reg isn't life, we can set it directly. */
7361 if (! TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
7363 rtx rr
= gen_rtx_REG (SImode
, PR_REG
);
7364 emit_insn (GEN_MOV (rr
, ra
));
7365 /* Tell flow the register for return isn't dead. */
7370 int pr_offset
= rounded_frame_size (d
);
7372 emit_insn (GEN_MOV (tmp
, GEN_INT (pr_offset
)));
7374 if (frame_pointer_needed
)
7375 emit_insn (GEN_ADD3 (tmp
, tmp
, hard_frame_pointer_rtx
));
7377 emit_insn (GEN_ADD3 (tmp
, tmp
, stack_pointer_rtx
));
7379 tmp
= gen_frame_mem (Pmode
, tmp
);
7380 emit_insn (GEN_MOV (tmp
, ra
));
7381 /* Tell this store isn't dead. */
7385 /* Clear variables at function end. */
7387 sh_output_function_epilogue (FILE *)
7392 sh_builtin_saveregs (void)
7394 /* First unnamed integer register. */
7395 int first_intreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
];
7396 /* Number of integer registers we need to save. */
7397 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
7398 /* First unnamed SFmode float reg */
7399 int first_floatreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_FLOAT
];
7400 /* Number of SFmode float regs to save. */
7401 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
7404 alias_set_type alias_set
;
7406 if (!TARGET_FPU_ANY
)
7408 error ("%<__builtin_saveregs%> not supported by this subtarget");
7412 /* Allocate block of memory for the regs. */
7413 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7414 Or can assign_stack_local accept a 0 SIZE argument? */
7415 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
7417 if (n_floatregs
& 1)
7421 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
7422 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
7423 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
7424 regbuf
= change_address (regbuf
, BLKmode
, addr
);
7426 else if (STACK_BOUNDARY
< 64 && TARGET_FPU_DOUBLE
&& n_floatregs
)
7430 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
7431 addr
= copy_to_mode_reg (Pmode
, plus_constant (Pmode
,
7432 XEXP (regbuf
, 0), 4));
7433 mask
= copy_to_mode_reg (Pmode
, GEN_INT (-8));
7434 emit_insn (gen_andsi3 (addr
, addr
, mask
));
7435 regbuf
= change_address (regbuf
, BLKmode
, addr
);
7438 regbuf
= assign_stack_local (BLKmode
, bufsize
, TARGET_FPU_DOUBLE
? 64 : 0);
7439 alias_set
= get_varargs_alias_set ();
7440 set_mem_alias_set (regbuf
, alias_set
);
7443 This is optimized to only save the regs that are necessary. Explicitly
7444 named args need not be saved. */
7446 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
7447 adjust_address (regbuf
, BLKmode
,
7448 n_floatregs
* UNITS_PER_WORD
),
7452 This is optimized to only save the regs that are necessary. Explicitly
7453 named args need not be saved.
7454 We explicitly build a pointer to the buffer because it halves the insn
7455 count when not optimizing (otherwise the pointer is built for each reg
7457 We emit the moves in reverse order so that we can use predecrement. */
7459 fpregs
= copy_to_mode_reg (Pmode
,
7460 plus_constant (Pmode
, XEXP (regbuf
, 0),
7461 n_floatregs
* UNITS_PER_WORD
));
7462 if (TARGET_FPU_DOUBLE
)
7465 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
7467 emit_insn (gen_addsi3 (fpregs
, fpregs
,
7468 GEN_INT (-2 * UNITS_PER_WORD
)));
7469 mem
= change_address (regbuf
, DFmode
, fpregs
);
7470 emit_move_insn (mem
,
7471 gen_rtx_REG (DFmode
, BASE_ARG_REG (DFmode
) + regno
));
7473 regno
= first_floatreg
;
7476 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
7477 mem
= change_address (regbuf
, SFmode
, fpregs
);
7478 emit_move_insn (mem
,
7479 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
)
7480 + regno
- SH_REG_MSW_OFFSET
));
7484 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
7488 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
7489 mem
= change_address (regbuf
, SFmode
, fpregs
);
7490 emit_move_insn (mem
,
7491 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
7494 /* Return the address of the regbuf. */
7495 return XEXP (regbuf
, 0);
7498 /* Define the `__builtin_va_list' type for the ABI. */
7500 sh_build_builtin_va_list (void)
7502 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
7503 tree record
, type_decl
;
7505 if ((! TARGET_SH2E
&& ! TARGET_SH4
)
7506 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
7507 return ptr_type_node
;
7509 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
7510 type_decl
= build_decl (BUILTINS_LOCATION
,
7511 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
7513 f_next_o
= build_decl (BUILTINS_LOCATION
,
7514 FIELD_DECL
, get_identifier ("__va_next_o"),
7516 f_next_o_limit
= build_decl (BUILTINS_LOCATION
,
7518 get_identifier ("__va_next_o_limit"),
7520 f_next_fp
= build_decl (BUILTINS_LOCATION
,
7521 FIELD_DECL
, get_identifier ("__va_next_fp"),
7523 f_next_fp_limit
= build_decl (BUILTINS_LOCATION
,
7525 get_identifier ("__va_next_fp_limit"),
7527 f_next_stack
= build_decl (BUILTINS_LOCATION
,
7528 FIELD_DECL
, get_identifier ("__va_next_stack"),
7531 DECL_FIELD_CONTEXT (f_next_o
) = record
;
7532 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
7533 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
7534 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
7535 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
7537 TYPE_STUB_DECL (record
) = type_decl
;
7538 TYPE_NAME (record
) = type_decl
;
7539 TYPE_FIELDS (record
) = f_next_o
;
7540 DECL_CHAIN (f_next_o
) = f_next_o_limit
;
7541 DECL_CHAIN (f_next_o_limit
) = f_next_fp
;
7542 DECL_CHAIN (f_next_fp
) = f_next_fp_limit
;
7543 DECL_CHAIN (f_next_fp_limit
) = f_next_stack
;
7545 layout_type (record
);
7550 /* Implement `va_start' for varargs and stdarg. */
7552 sh_va_start (tree valist
, rtx nextarg
)
7554 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
7555 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
7559 if ((! TARGET_SH2E
&& ! TARGET_SH4
)
7560 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
7562 std_expand_builtin_va_start (valist
, nextarg
);
7566 f_next_o
= TYPE_FIELDS (va_list_type_node
);
7567 f_next_o_limit
= DECL_CHAIN (f_next_o
);
7568 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
7569 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
7570 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
7572 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
7574 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
7575 valist
, f_next_o_limit
, NULL_TREE
);
7576 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
,
7578 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
7579 valist
, f_next_fp_limit
, NULL_TREE
);
7580 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
7581 valist
, f_next_stack
, NULL_TREE
);
7583 /* Call __builtin_saveregs. */
7584 u
= make_tree (sizetype
, expand_builtin_saveregs ());
7585 u
= fold_convert (ptr_type_node
, u
);
7586 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
7587 TREE_SIDE_EFFECTS (t
) = 1;
7588 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7590 nfp
= crtl
->args
.info
.arg_count
[SH_ARG_FLOAT
];
7595 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nfp
);
7596 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
7597 TREE_SIDE_EFFECTS (t
) = 1;
7598 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7600 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
7601 TREE_SIDE_EFFECTS (t
) = 1;
7602 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7604 nint
= crtl
->args
.info
.arg_count
[SH_ARG_INT
];
7609 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nint
);
7610 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
7611 TREE_SIDE_EFFECTS (t
) = 1;
7612 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7614 u
= make_tree (ptr_type_node
, nextarg
);
7615 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
7616 TREE_SIDE_EFFECTS (t
) = 1;
7617 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7620 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7621 member, return it. */
7623 find_sole_member (tree type
)
7625 tree field
, member
= NULL_TREE
;
7627 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
7629 if (TREE_CODE (field
) != FIELD_DECL
)
7631 if (!DECL_SIZE (field
))
7633 if (integer_zerop (DECL_SIZE (field
)))
7642 /* Implement `va_arg'. */
7644 sh_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
7645 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
7648 tree addr
, lab_over
= NULL
, result
= NULL
;
7651 const bool pass_by_ref
7652 = !VOID_TYPE_P (type
) && must_pass_va_arg_in_stack (type
);
7655 type
= build_pointer_type (type
);
7657 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7658 HOST_WIDE_INT rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
7659 tree pptr_type_node
= build_pointer_type (ptr_type_node
);
7661 if ((TARGET_SH2E
|| TARGET_SH4
)
7662 && ! (TARGET_HITACHI
|| sh_cfun_attr_renesas_p ()))
7664 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
7665 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
7669 f_next_o
= TYPE_FIELDS (va_list_type_node
);
7670 f_next_o_limit
= DECL_CHAIN (f_next_o
);
7671 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
7672 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
7673 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
7675 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
7677 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
7678 valist
, f_next_o_limit
, NULL_TREE
);
7679 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
7680 valist
, f_next_fp
, NULL_TREE
);
7681 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
7682 valist
, f_next_fp_limit
, NULL_TREE
);
7683 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
7684 valist
, f_next_stack
, NULL_TREE
);
7686 /* Structures with a single member with a distinct mode are passed
7687 like their member. This is relevant if the latter has a REAL_TYPE
7688 or COMPLEX_TYPE type. */
7690 while (TREE_CODE (eff_type
) == RECORD_TYPE
7691 && (member
= find_sole_member (eff_type
))
7692 && (TREE_CODE (TREE_TYPE (member
)) == REAL_TYPE
7693 || TREE_CODE (TREE_TYPE (member
)) == COMPLEX_TYPE
7694 || TREE_CODE (TREE_TYPE (member
)) == RECORD_TYPE
))
7696 tree field_type
= TREE_TYPE (member
);
7698 if (TYPE_MODE (eff_type
) == TYPE_MODE (field_type
))
7699 eff_type
= field_type
;
7702 gcc_assert ((TYPE_ALIGN (eff_type
)
7703 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type
)))
7704 || (TYPE_ALIGN (eff_type
)
7705 > GET_MODE_BITSIZE (TYPE_MODE (field_type
))));
7711 if (TARGET_FPU_DOUBLE
)
7713 pass_as_float
= ((TREE_CODE (eff_type
) == REAL_TYPE
&& size
<= 8)
7714 || (TREE_CODE (eff_type
) == COMPLEX_TYPE
7715 && TREE_CODE (TREE_TYPE (eff_type
)) == REAL_TYPE
7720 pass_as_float
= (TREE_CODE (eff_type
) == REAL_TYPE
&& size
== 4);
7723 addr
= create_tmp_var (pptr_type_node
);
7724 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
7725 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
7727 valist
= build_simple_mem_ref (addr
);
7731 tree next_fp_tmp
= create_tmp_var (TREE_TYPE (f_next_fp
));
7733 bool is_double
= size
== 8 && TREE_CODE (eff_type
) == REAL_TYPE
;
7735 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_fp
));
7736 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
7738 gimplify_assign (unshare_expr (next_fp_tmp
), valist
, pre_p
);
7739 tmp
= next_fp_limit
;
7740 if (size
> 4 && !is_double
)
7741 tmp
= fold_build_pointer_plus_hwi (unshare_expr (tmp
), 4 - size
);
7742 tmp
= build2 (GE_EXPR
, boolean_type_node
,
7743 unshare_expr (next_fp_tmp
), unshare_expr (tmp
));
7744 cmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
7745 build1 (GOTO_EXPR
, void_type_node
,
7746 unshare_expr (lab_false
)), NULL_TREE
);
7748 gimplify_and_add (cmp
, pre_p
);
7750 if (TYPE_ALIGN (eff_type
) > BITS_PER_WORD
7751 || (is_double
|| size
== 16))
7753 tmp
= fold_convert (sizetype
, next_fp_tmp
);
7754 tmp
= build2 (BIT_AND_EXPR
, sizetype
, tmp
,
7755 size_int (UNITS_PER_WORD
));
7756 tmp
= fold_build_pointer_plus (unshare_expr (next_fp_tmp
), tmp
);
7757 gimplify_assign (unshare_expr (next_fp_tmp
), tmp
, pre_p
);
7760 gimplify_and_add (cmp
, pre_p
);
7762 #ifdef FUNCTION_ARG_SCmode_WART
7763 if (TYPE_MODE (eff_type
) == SCmode
7764 && TARGET_SH4
&& TARGET_LITTLE_ENDIAN
)
7766 tree subtype
= TREE_TYPE (eff_type
);
7770 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
7771 imag
= get_initialized_tmp_var (imag
, pre_p
, NULL
);
7774 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
7775 real
= get_initialized_tmp_var (real
, pre_p
, NULL
);
7777 result
= build2 (COMPLEX_EXPR
, eff_type
, real
, imag
);
7778 if (type
!= eff_type
)
7779 result
= build1 (VIEW_CONVERT_EXPR
, type
, result
);
7780 result
= get_initialized_tmp_var (result
, pre_p
, NULL
);
7782 #endif /* FUNCTION_ARG_SCmode_WART */
7784 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
7785 gimplify_and_add (tmp
, pre_p
);
7787 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
7788 gimplify_and_add (tmp
, pre_p
);
7790 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
7791 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
7792 gimplify_assign (unshare_expr (next_fp_tmp
),
7793 unshare_expr (valist
), pre_p
);
7795 gimplify_assign (unshare_expr (valist
),
7796 unshare_expr (next_fp_tmp
), post_p
);
7797 valist
= next_fp_tmp
;
7801 tmp
= fold_build_pointer_plus_hwi (unshare_expr (next_o
), rsize
);
7802 tmp
= build2 (GT_EXPR
, boolean_type_node
, tmp
,
7803 unshare_expr (next_o_limit
));
7804 tmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
7805 build1 (GOTO_EXPR
, void_type_node
,
7806 unshare_expr (lab_false
)),
7808 gimplify_and_add (tmp
, pre_p
);
7810 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_o
));
7811 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
7813 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
7814 gimplify_and_add (tmp
, pre_p
);
7816 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
7817 gimplify_and_add (tmp
, pre_p
);
7819 if (size
> 4 && ! (TARGET_SH4
|| TARGET_SH2A
))
7820 gimplify_assign (unshare_expr (next_o
),
7821 unshare_expr (next_o_limit
), pre_p
);
7823 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
7824 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
7829 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
7830 gimplify_and_add (tmp
, pre_p
);
7834 /* ??? In va-sh.h, there had been code to make values larger than
7835 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7837 tmp
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, NULL
);
7840 gimplify_assign (result
, tmp
, pre_p
);
7841 result
= build1 (NOP_EXPR
, TREE_TYPE (result
), result
);
7842 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
7843 gimplify_and_add (tmp
, pre_p
);
7849 result
= build_va_arg_indirect_ref (result
);
7854 /* 64 bit floating points memory transfers are paired single precision loads
7855 or store. So DWARF information needs fixing in little endian (unless
7856 PR=SZ=1 in FPSCR). */
7858 sh_dwarf_register_span (rtx reg
)
7860 unsigned regno
= REGNO (reg
);
7862 if (WORDS_BIG_ENDIAN
|| GET_MODE (reg
) != DFmode
)
7866 gen_rtx_PARALLEL (VOIDmode
,
7868 gen_rtx_REG (SFmode
, regno
+ 1),
7869 gen_rtx_REG (SFmode
, regno
)));
7873 sh_promote_function_mode (const_tree type
, machine_mode mode
,
7874 int *punsignedp
, const_tree funtype
,
7877 if (sh_promote_prototypes (funtype
))
7878 return promote_mode (type
, mode
, punsignedp
);
7880 return default_promote_function_mode (type
, mode
, punsignedp
, funtype
,
7885 sh_promote_prototypes (const_tree type
)
7891 return ! sh_attr_renesas_p (type
);
7895 sh_pass_by_reference (cumulative_args_t cum_v
, const function_arg_info
&arg
)
7897 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7899 if (targetm
.calls
.must_pass_in_stack (arg
))
7902 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7903 wants to know about pass-by-reference semantics for incoming
7912 sh_callee_copies (cumulative_args_t cum
, const function_arg_info
&arg
)
7914 /* ??? How can it possibly be correct to return true only on the
7915 caller side of the equation? Is there someplace else in the
7916 sh backend that's magically producing the copies? */
7917 return (get_cumulative_args (cum
)->outgoing
7918 && ((arg
.mode
== BLKmode
7919 ? TYPE_ALIGN (arg
.type
)
7920 : GET_MODE_ALIGNMENT (arg
.mode
))
7921 % SH_MIN_ALIGN_FOR_CALLEE_COPY
== 0));
7925 get_sh_arg_class (machine_mode mode
)
7927 if (TARGET_FPU_ANY
&& mode
== SFmode
)
7928 return SH_ARG_FLOAT
;
7930 if (TARGET_FPU_DOUBLE
7931 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
7932 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
))
7933 return SH_ARG_FLOAT
;
7938 /* Round a register number up to a proper boundary for an arg of mode
7940 The SH doesn't care about double alignment, so we only
7941 round doubles to even regs when asked to explicitly. */
7943 sh_round_reg (const CUMULATIVE_ARGS
& cum
, machine_mode mode
)
7945 /* FIXME: This used to be a macro and has been copy pasted into this
7946 function as is. Make this more readable. */
7948 (((TARGET_ALIGN_DOUBLE
7949 || (TARGET_FPU_DOUBLE
7950 && (mode
== DFmode
|| mode
== DCmode
)
7951 && cum
.arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (mode
)))
7952 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_WORD
)
7953 ? (cum
.arg_count
[(int) get_sh_arg_class (mode
)]
7954 + (cum
.arg_count
[(int) get_sh_arg_class (mode
)] & 1))
7955 : cum
.arg_count
[(int) get_sh_arg_class (mode
)]);
7958 /* Return true if arg of the specified mode should be passed in a register
7959 or false otherwise. */
7961 sh_pass_in_reg_p (const CUMULATIVE_ARGS
& cum
, machine_mode mode
,
7964 /* FIXME: This used to be a macro and has been copy pasted into this
7965 function as is. Make this more readable. */
7968 || (! TREE_ADDRESSABLE (type
)
7969 && (! (TARGET_HITACHI
|| cum
.renesas_abi
)
7970 || ! (AGGREGATE_TYPE_P (type
)
7972 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
7973 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (SFmode
)))))))
7976 ? ((mode
) == BLKmode
7977 ? ((cum
.arg_count
[(int) SH_ARG_INT
] * UNITS_PER_WORD
7978 + int_size_in_bytes (type
))
7979 <= NPARM_REGS (SImode
) * UNITS_PER_WORD
)
7980 : ((sh_round_reg (cum
, mode
)
7981 + sh_hard_regno_nregs (BASE_ARG_REG (mode
), mode
))
7982 <= NPARM_REGS (mode
)))
7983 : sh_round_reg (cum
, mode
) < NPARM_REGS (mode
)));
7987 sh_arg_partial_bytes (cumulative_args_t cum_v
, const function_arg_info
&arg
)
7989 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7992 if (sh_pass_in_reg_p (*cum
, arg
.mode
, arg
.type
)
7993 && !TARGET_FPU_DOUBLE
7994 && (sh_round_reg (*cum
, arg
.mode
)
7995 + CEIL (arg
.promoted_size_in_bytes (), UNITS_PER_WORD
)
7996 > NPARM_REGS (arg
.mode
)))
7997 words
= NPARM_REGS (arg
.mode
) - sh_round_reg (*cum
, arg
.mode
);
7999 return words
* UNITS_PER_WORD
;
8003 /* Define where to put the arguments to a function.
8004 Value is zero to push the argument on the stack,
8005 or a hard register in which to store the argument.
8007 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8008 the preceding args and about the function being called.
8009 ARG is a description of the argument.
8011 On SH the first args are normally in registers
8012 and the rest are pushed. Any arg that starts within the first
8013 NPARM_REGS words is at least partially passed in a register unless
8014 its data type forbids. */
8016 sh_function_arg (cumulative_args_t ca_v
, const function_arg_info
&arg
)
8018 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8019 machine_mode mode
= arg
.mode
;
8021 if (arg
.end_marker_p ())
8022 return ca
->renesas_abi
? const1_rtx
: const0_rtx
;
8024 if (sh_pass_in_reg_p (*ca
, mode
, arg
.type
)
8025 && (arg
.named
|| ! (TARGET_HITACHI
|| ca
->renesas_abi
)))
8029 if (mode
== SCmode
&& TARGET_SH4
&& TARGET_LITTLE_ENDIAN
8030 && (! FUNCTION_ARG_SCmode_WART
|| (sh_round_reg (*ca
, mode
) & 1)))
8032 rtx r1
= gen_rtx_EXPR_LIST (VOIDmode
,
8033 gen_rtx_REG (SFmode
,
8035 + (sh_round_reg (*ca
, mode
) ^ 1)),
8037 rtx r2
= gen_rtx_EXPR_LIST (VOIDmode
,
8038 gen_rtx_REG (SFmode
,
8040 + ((sh_round_reg (*ca
, mode
) + 1) ^ 1)),
8042 return gen_rtx_PARALLEL(SCmode
, gen_rtvec(2, r1
, r2
));
8045 /* If the alignment of a DF value causes an SF register to be
8046 skipped, we will use that skipped register for the next SF
8048 if ((TARGET_HITACHI
|| ca
->renesas_abi
)
8049 && ca
->free_single_fp_reg
8051 return gen_rtx_REG (mode
, ca
->free_single_fp_reg
);
8053 regno
= (BASE_ARG_REG (mode
) + sh_round_reg (*ca
, mode
))
8054 ^ (mode
== SFmode
&& TARGET_SH4
8055 && TARGET_LITTLE_ENDIAN
8056 && ! TARGET_HITACHI
&& ! ca
->renesas_abi
);
8057 return gen_rtx_REG (mode
, regno
);
8064 /* Update the data in CUM to advance over argument ARG. */
8066 sh_function_arg_advance (cumulative_args_t ca_v
,
8067 const function_arg_info
&arg
)
8069 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8072 ca
->force_mem
= false;
8074 if ((TARGET_HITACHI
|| ca
->renesas_abi
) && TARGET_FPU_DOUBLE
)
8076 /* Note that we've used the skipped register. */
8077 if (arg
.mode
== SFmode
&& ca
->free_single_fp_reg
)
8079 ca
->free_single_fp_reg
= 0;
8082 /* When we have a DF after an SF, there's an SF register that get
8083 skipped in order to align the DF value. We note this skipped
8084 register, because the next SF value will use it, and not the
8085 SF that follows the DF. */
8086 if (arg
.mode
== DFmode
8087 && sh_round_reg (*ca
, DFmode
) != sh_round_reg (*ca
, SFmode
))
8089 ca
->free_single_fp_reg
= (sh_round_reg (*ca
, SFmode
)
8090 + BASE_ARG_REG (arg
.mode
));
8094 if (! ((TARGET_SH4
|| TARGET_SH2A
) || ca
->renesas_abi
)
8095 || sh_pass_in_reg_p (*ca
, arg
.mode
, arg
.type
))
8096 (ca
->arg_count
[(int) get_sh_arg_class (arg
.mode
)]
8097 = (sh_round_reg (*ca
, arg
.mode
)
8098 + CEIL (arg
.promoted_size_in_bytes (), UNITS_PER_WORD
)));
8101 /* The Renesas calling convention doesn't quite fit into this scheme since
8102 the address is passed like an invisible argument, but one that is always
8103 passed in memory. */
8105 sh_struct_value_rtx (tree fndecl
, int incoming ATTRIBUTE_UNUSED
)
8107 if (TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
8109 return gen_rtx_REG (Pmode
, 2);
8112 /* Worker function for TARGET_FUNCTION_VALUE.
8114 For the SH, this is like LIBCALL_VALUE, except that we must change the
8115 mode like PROMOTE_MODE does.
8116 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8117 tested here has to be kept in sync with the one in
8118 explow.c:promote_mode. */
8120 sh_function_value (const_tree valtype
,
8121 const_tree fn_decl_or_type
,
8122 bool outgoing ATTRIBUTE_UNUSED
)
8125 && !DECL_P (fn_decl_or_type
))
8126 fn_decl_or_type
= NULL
;
8128 return gen_rtx_REG (
8129 ((GET_MODE_CLASS (TYPE_MODE (valtype
)) == MODE_INT
8130 && GET_MODE_SIZE (TYPE_MODE (valtype
)) < 4
8131 && (TREE_CODE (valtype
) == INTEGER_TYPE
8132 || TREE_CODE (valtype
) == ENUMERAL_TYPE
8133 || TREE_CODE (valtype
) == BOOLEAN_TYPE
8134 || TREE_CODE (valtype
) == REAL_TYPE
8135 || TREE_CODE (valtype
) == OFFSET_TYPE
))
8136 && sh_promote_prototypes (fn_decl_or_type
)
8137 ? SImode
: TYPE_MODE (valtype
)),
8138 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype
)));
8141 /* Worker function for TARGET_LIBCALL_VALUE. */
8143 sh_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8145 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG (mode
));
8148 /* Return true if N is a possible register number of function value. */
8150 sh_function_value_regno_p (const unsigned int regno
)
8152 return regno
== FIRST_RET_REG
|| (TARGET_SH2E
&& regno
== FIRST_FP_RET_REG
);
8155 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8157 sh_return_in_memory (const_tree type
, const_tree fndecl
)
8159 return TYPE_MODE (type
) == BLKmode
8160 || ((TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
8161 && TREE_CODE (type
) == RECORD_TYPE
);
8164 /* We actually emit the code in sh_expand_prologue. We used to use
8165 a static variable to flag that we need to emit this code, but that
8166 doesn't when inlining, when functions are deferred and then emitted
8167 later. Fortunately, we already have two flags that are part of struct
8168 function that tell if a function uses varargs or stdarg. */
8170 sh_setup_incoming_varargs (cumulative_args_t ca
,
8171 const function_arg_info
&arg
,
8172 int *pretend_arg_size
,
8173 int second_time ATTRIBUTE_UNUSED
)
8175 gcc_assert (cfun
->stdarg
);
8176 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
8178 int named_parm_regs
, anon_parm_regs
;
8180 named_parm_regs
= (sh_round_reg (*get_cumulative_args (ca
), arg
.mode
)
8181 + CEIL (arg
.promoted_size_in_bytes (),
8183 anon_parm_regs
= NPARM_REGS (SImode
) - named_parm_regs
;
8184 if (anon_parm_regs
> 0)
8185 *pretend_arg_size
= anon_parm_regs
* 4;
8190 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
8196 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v
)
8198 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8200 return ! (TARGET_HITACHI
|| ca
->renesas_abi
);
8204 /* Define the offset between two registers, one to be eliminated, and
8205 the other its replacement, at the start of a routine. */
8207 initial_elimination_offset (int from
, int to
)
8209 const int regs_saved_rounding
= 0;
8210 int save_flags
= target_flags
;
8211 HARD_REG_SET live_regs_mask
;
8213 int regs_saved
= calc_live_regs (&live_regs_mask
);
8215 int total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
8216 target_flags
= save_flags
;
8218 int total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
8220 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8221 return total_saved_regs_space
+ total_auto_space
;
8223 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8224 return total_saved_regs_space
+ total_auto_space
;
8226 /* Initial gap between fp and sp is 0. */
8227 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8230 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8231 return rounded_frame_size (0);
8233 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8234 return rounded_frame_size (0);
8236 gcc_assert (from
== RETURN_ADDRESS_POINTER_REGNUM
8237 && (to
== HARD_FRAME_POINTER_REGNUM
8238 || to
== STACK_POINTER_REGNUM
));
8239 return total_auto_space
;
8242 /* Parse the -mfixed-range= option string. */
8244 sh_fix_range (const char *const_str
)
8246 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8247 REG2 are either register names or register numbers. The effect
8248 of this option is to mark the registers in the range from REG1 to
8249 REG2 as ``fixed'' so they won't be used by the compiler. */
8251 char* str
= strcpy ((char*)alloca (strlen (const_str
) + 1), const_str
);
8255 char* dash
= strchr (str
, '-');
8258 warning (0, "value of %<-mfixed-range%> must have form REG1-REG2");
8262 char* comma
= strchr (dash
+ 1, ',');
8266 int first
= decode_reg_name (str
);
8269 warning (0, "unknown register name: %s", str
);
8273 int last
= decode_reg_name (dash
+ 1);
8276 warning (0, "unknown register name: %s", dash
+ 1);
8284 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
8288 for (int i
= first
; i
<= last
; ++i
)
8289 fixed_regs
[i
] = call_used_regs
[i
] = 1;
8299 /* Insert any deferred function attributes from earlier pragmas. */
8301 sh_insert_attributes (tree node
, tree
*attributes
)
8303 if (TREE_CODE (node
) != FUNCTION_DECL
)
8306 /* We are only interested in fields. */
8310 /* Append the attributes to the deferred attributes. */
8311 *sh_deferred_function_attributes_tail
= *attributes
;
8312 tree attrs
= sh_deferred_function_attributes
;
8316 /* Some attributes imply or require the interrupt attribute. */
8317 if (!lookup_attribute ("interrupt_handler", attrs
)
8318 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node
)))
8320 /* If we have a trapa_handler, but no interrupt_handler attribute,
8321 insert an interrupt_handler attribute. */
8322 if (lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
)
8323 /* We can't use sh_pr_interrupt here because that's not in the
8326 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE
, attrs
);
8327 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8328 if the interrupt attribute is missing, we ignore the attribute
8330 else if (lookup_attribute ("sp_switch", attrs
)
8331 || lookup_attribute ("trap_exit", attrs
)
8332 || lookup_attribute ("nosave_low_regs", attrs
)
8333 || lookup_attribute ("resbank", attrs
))
8337 for (tail
= attributes
; attrs
; attrs
= TREE_CHAIN (attrs
))
8339 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs
))
8340 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs
))
8341 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs
))
8342 || is_attribute_p ("resbank", TREE_PURPOSE (attrs
)))
8343 warning (OPT_Wattributes
,
8344 "%qE attribute only applies to interrupt functions",
8345 TREE_PURPOSE (attrs
));
8348 *tail
= tree_cons (TREE_PURPOSE (attrs
), NULL_TREE
,
8350 tail
= &TREE_CHAIN (*tail
);
8353 attrs
= *attributes
;
8357 /* Install the processed list. */
8358 *attributes
= attrs
;
8360 /* Clear deferred attributes. */
8361 sh_deferred_function_attributes
= NULL_TREE
;
8362 sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
8367 /*------------------------------------------------------------------------------
8368 Target specific attributes
8369 Supported attributes are:
8372 Specifies this function is an interrupt handler.
8375 Like interrupt_handler, but don't save all registers.
8378 Specifies an alternate stack for an interrupt handler to run on.
8381 Use a trapa to exit an interrupt function instead of rte.
8384 Don't save r0..r7 in an interrupt handler function.
8385 This is useful on SH3* and SH4*, which have a separate set of low
8386 regs for user and privileged modes.
8387 This is mainly to be used for non-reentrant interrupt handlers (i.e.
8388 those that run with interrupts disabled and thus can't be
8389 interrupted thenselves).
8392 Use Renesas calling/layout conventions (functions and structures).
8395 In case of an interrupt handler function, use a register bank to
8396 save registers R0-R14, MACH, MACL, GBR and PR.
8397 This is available only on SH2A targets.
8400 Declares a function to be called using the TBR relative addressing
8401 mode. Takes an argument that specifies the slot number in the table
8402 where this function can be looked up by the JSR/N @@(disp8,TBR) insn.
8405 /* Handle a 'resbank' attribute. */
8407 sh_handle_resbank_handler_attribute (tree
* node
, tree name
,
8408 tree args ATTRIBUTE_UNUSED
,
8409 int flags ATTRIBUTE_UNUSED
,
8410 bool * no_add_attrs
)
8414 warning (OPT_Wattributes
, "%qE attribute is supported only for SH2A",
8416 *no_add_attrs
= true;
8418 if (TREE_CODE (*node
) != FUNCTION_DECL
)
8420 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8422 *no_add_attrs
= true;
8428 /* Handle an "interrupt_handler" attribute; arguments as in
8429 struct attribute_spec.handler. */
8431 sh_handle_interrupt_handler_attribute (tree
*node
, tree name
,
8432 tree args ATTRIBUTE_UNUSED
,
8433 int flags ATTRIBUTE_UNUSED
,
8436 if (TREE_CODE (*node
) != FUNCTION_DECL
)
8438 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8440 *no_add_attrs
= true;
8446 /* Handle an 'function_vector' attribute; arguments as in
8447 struct attribute_spec.handler. */
8449 sh2a_handle_function_vector_handler_attribute (tree
* node
, tree name
,
8450 tree args ATTRIBUTE_UNUSED
,
8451 int flags ATTRIBUTE_UNUSED
,
8452 bool * no_add_attrs
)
8456 warning (OPT_Wattributes
, "%qE attribute only applies to SH2A",
8458 *no_add_attrs
= true;
8460 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
8462 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8464 *no_add_attrs
= true;
8466 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
8468 /* The argument must be a constant integer. */
8469 warning (OPT_Wattributes
,
8470 "%qE attribute argument not an integer constant",
8472 *no_add_attrs
= true;
8474 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
8476 /* The argument value must be between 0 to 255. */
8477 warning (OPT_Wattributes
,
8478 "%qE attribute argument should be between 0 to 255",
8480 *no_add_attrs
= true;
8485 /* Returns true if current function has been assigned the attribute
8486 'function_vector'. */
8488 sh2a_is_function_vector_call (rtx x
)
8490 if (GET_CODE (x
) == SYMBOL_REF
8491 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
8493 tree tr
= SYMBOL_REF_DECL (x
);
8495 if (sh2a_function_vector_p (tr
))
8502 /* Returns the function vector number, if the attribute
8503 'function_vector' is assigned, otherwise returns zero. */
8505 sh2a_get_function_vector_number (rtx x
)
8507 if ((GET_CODE (x
) == SYMBOL_REF
)
8508 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
8510 tree t
= SYMBOL_REF_DECL (x
);
8512 if (TREE_CODE (t
) != FUNCTION_DECL
)
8515 for (tree list
= SH_ATTRIBUTES (t
); list
; list
= TREE_CHAIN (list
))
8516 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
8517 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
8525 /* Handle an "sp_switch" attribute; arguments as in
8526 struct attribute_spec.handler. */
8528 sh_handle_sp_switch_attribute (tree
*node
, tree name
, tree args
,
8529 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
8531 if (TREE_CODE (*node
) != FUNCTION_DECL
)
8533 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8535 *no_add_attrs
= true;
8537 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
8539 /* The argument must be a constant string. */
8540 warning (OPT_Wattributes
, "%qE attribute argument not a string constant",
8542 *no_add_attrs
= true;
8548 /* Handle an "trap_exit" attribute; arguments as in
8549 struct attribute_spec.handler. */
8551 sh_handle_trap_exit_attribute (tree
*node
, tree name
, tree args
,
8552 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
8554 if (TREE_CODE (*node
) != FUNCTION_DECL
)
8556 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8558 *no_add_attrs
= true;
8560 /* The argument specifies a trap number to be used in a trapa instruction
8561 at function exit (instead of an rte instruction). */
8562 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
8564 /* The argument must be a constant integer. */
8565 warning (OPT_Wattributes
, "%qE attribute argument not an "
8566 "integer constant", name
);
8567 *no_add_attrs
= true;
8574 sh_handle_renesas_attribute (tree
*node ATTRIBUTE_UNUSED
,
8575 tree name ATTRIBUTE_UNUSED
,
8576 tree args ATTRIBUTE_UNUSED
,
8577 int flags ATTRIBUTE_UNUSED
,
8578 bool *no_add_attrs ATTRIBUTE_UNUSED
)
8583 /* True if __attribute__((renesas)) or -mrenesas. */
8585 sh_attr_renesas_p (const_tree td
)
8589 if (td
== NULL_TREE
)
8592 td
= TREE_TYPE (td
);
8593 if (td
== error_mark_node
)
8595 return lookup_attribute ("renesas", TYPE_ATTRIBUTES (td
)) != NULL_TREE
;
8598 /* True if __attribute__((renesas)) or -mrenesas, for the current
8601 sh_cfun_attr_renesas_p (void)
8603 return sh_attr_renesas_p (current_function_decl
);
8606 /* Returns true if the current function has the "interrupt_handler"
8609 sh_cfun_interrupt_handler_p (void)
8611 return (lookup_attribute ("interrupt_handler",
8612 DECL_ATTRIBUTES (current_function_decl
))
8616 /* Returns true if FUNC has been assigned the attribute
8617 "function_vector". */
8619 sh2a_function_vector_p (tree func
)
8621 if (TREE_CODE (func
) != FUNCTION_DECL
)
8624 for (tree list
= SH_ATTRIBUTES (func
); list
; list
= TREE_CHAIN (list
))
8625 if (is_attribute_p ("function_vector", get_attribute_name (list
)))
8631 /* Returns true if given tree has the "resbank" attribute set. */
8633 sh_cfun_resbank_handler_p (void)
8635 return ((lookup_attribute ("resbank",
8636 DECL_ATTRIBUTES (current_function_decl
))
8638 && (lookup_attribute ("interrupt_handler",
8639 DECL_ATTRIBUTES (current_function_decl
))
8640 != NULL_TREE
) && TARGET_SH2A
);
8643 /* Returns true if the current function has a "trap_exit" attribute set. */
8645 sh_cfun_trap_exit_p (void)
8647 return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl
))
8651 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8653 sh_check_pch_target_flags (int old_flags
)
8655 if ((old_flags
^ target_flags
) & (MASK_SH1
| MASK_SH2
| MASK_SH3
8656 | MASK_SH_E
| MASK_HARD_SH4
8657 | MASK_FPU_SINGLE
| MASK_SH4
))
8658 return _("created and used with different architectures / ABIs");
8659 if ((old_flags
^ target_flags
) & MASK_HITACHI
)
8660 return _("created and used with different ABIs");
8661 if ((old_flags
^ target_flags
) & MASK_LITTLE_ENDIAN
)
8662 return _("created and used with different endianness");
8666 /* Predicates used by the templates. */
8668 /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
8669 Used only in general_movsrc_operand. */
8671 system_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
8683 /* Returns true if OP is a floating point value with value 0.0. */
8685 fp_zero_operand (rtx op
)
8687 if (GET_MODE (op
) != SFmode
)
8690 const REAL_VALUE_TYPE
* r
= CONST_DOUBLE_REAL_VALUE (op
);
8691 return real_equal (r
, &dconst0
) && ! REAL_VALUE_MINUS_ZERO (*r
);
8694 /* Returns true if OP is a floating point value with value 1.0. */
8696 fp_one_operand (rtx op
)
8698 if (GET_MODE (op
) != SFmode
)
8701 return real_equal (CONST_DOUBLE_REAL_VALUE (op
), &dconst1
);
8704 /* Return the TLS type for TLS symbols. */
8706 tls_symbolic_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
8708 if (GET_CODE (op
) != SYMBOL_REF
)
8709 return TLS_MODEL_NONE
;
8710 return SYMBOL_REF_TLS_MODEL (op
);
8713 /* Return the destination address of a branch. */
8715 branch_dest (rtx branch
)
8717 rtx dest
= SET_SRC (PATTERN (branch
));
8719 if (GET_CODE (dest
) == IF_THEN_ELSE
)
8720 dest
= XEXP (dest
, 1);
8722 return INSN_ADDRESSES (INSN_UID (XEXP (dest
, 0)));
8725 /* Return nonzero if REG is not used after INSN.
8726 We assume REG is a reload reg, and therefore does
8727 not live past labels. It may live past calls or jumps though. */
8729 reg_unused_after (rtx reg
, rtx_insn
*insn
)
8731 /* If the reg is set by this instruction, then it is safe for our
8732 case. Disregard the case where this is a store to memory, since
8733 we are checking a register used in the store address. */
8734 rtx set
= single_set (insn
);
8735 if (set
&& !MEM_P (SET_DEST (set
))
8736 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
8739 while ((insn
= NEXT_INSN (insn
)))
8744 rtx_code code
= GET_CODE (insn
);
8747 /* If this is a label that existed before reload, then the register
8748 is dead here. However, if this is a label added by reorg, then
8749 the register may still be live here. We can't tell the difference,
8750 so we just ignore labels completely. */
8751 if (code
== CODE_LABEL
)
8756 if (code
== JUMP_INSN
)
8759 /* If this is a sequence, we must handle them all at once.
8760 We could have for instance a call that sets the target register,
8761 and an insn in a delay slot that uses the register. In this case,
8762 we must return 0. */
8763 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
8765 rtx_sequence
*seq
= as_a
<rtx_sequence
*> (PATTERN (insn
));
8766 bool retval
= false;
8768 for (int i
= 0; i
< seq
->len (); i
++)
8770 rtx_insn
*this_insn
= seq
->insn (i
);
8771 rtx set
= single_set (this_insn
);
8773 if (CALL_P (this_insn
))
8775 else if (JUMP_P (this_insn
))
8777 if (INSN_ANNULLED_BRANCH_P (this_insn
))
8782 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
8784 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
8786 if (!MEM_P (SET_DEST (set
)))
8792 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
8797 else if (code
== JUMP_INSN
)
8801 rtx set
= single_set (insn
);
8802 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
8804 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
8805 return !MEM_P (SET_DEST (set
));
8806 if (set
== NULL
&& reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
8809 if (code
== CALL_INSN
&& call_really_used_regs
[REGNO (reg
)])
8816 static GTY(()) rtx t_reg_rtx
;
8818 get_t_reg_rtx (void)
8821 t_reg_rtx
= gen_rtx_REG (SImode
, T_REG
);
8825 static GTY(()) tree fpscr_values
;
8828 emit_fpu_switch (rtx scratch
, int index
)
8830 if (fpscr_values
== NULL
)
8832 tree t
= build_index_type (integer_one_node
);
8833 t
= build_array_type (integer_type_node
, t
);
8834 t
= build_decl (BUILTINS_LOCATION
,
8835 VAR_DECL
, get_identifier ("__fpscr_values"), t
);
8836 DECL_ARTIFICIAL (t
) = 1;
8837 DECL_IGNORED_P (t
) = 1;
8838 DECL_EXTERNAL (t
) = 1;
8839 TREE_STATIC (t
) = 1;
8840 TREE_PUBLIC (t
) = 1;
8846 rtx src
= DECL_RTL (fpscr_values
);
8847 if (!can_create_pseudo_p ())
8849 emit_move_insn (scratch
, XEXP (src
, 0));
8851 emit_insn (gen_addsi3 (scratch
, scratch
, GEN_INT (index
* 4)));
8852 src
= adjust_automodify_address (src
, SImode
, scratch
, index
* 4);
8855 src
= adjust_address (src
, SImode
, index
* 4);
8857 emit_insn (gen_lds_fpscr (src
));
8860 static rtx
get_free_reg (HARD_REG_SET
);
8862 /* This function returns a register to use to load the address to load
8863 the fpscr from. Currently it always returns r1 or r7, but when we are
8864 able to use pseudo registers after combine, or have a better mechanism
8865 for choosing a register, it should be done here. */
8866 /* REGS_LIVE is the liveness information for the point for which we
8867 need this allocation. In some bare-bones exit blocks, r1 is live at the
8868 start. We can even have all of r0..r3 being live:
8869 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8870 INSN before which new insns are placed with will clobber the register
8871 we return. If a basic block consists only of setting the return value
8872 register to a pseudo and using that register, the return value is not
8873 live before or after this block, yet we we'll insert our insns right in
8876 get_free_reg (HARD_REG_SET regs_live
)
8878 if (! TEST_HARD_REG_BIT (regs_live
, 1))
8879 return gen_rtx_REG (Pmode
, 1);
8881 /* Hard reg 1 is live; since this is a small register classes target,
8882 there shouldn't be anything but a jump before the function end. */
8883 gcc_assert (!TEST_HARD_REG_BIT (regs_live
, 7));
8884 return gen_rtx_REG (Pmode
, 7);
8887 /* This function will set the fpscr from memory.
8888 MODE is the mode we are setting it to. */
8890 fpscr_set_from_mem (int mode
, HARD_REG_SET regs_live
)
8892 enum attr_fp_mode fp_mode
= (enum attr_fp_mode
) mode
;
8893 enum attr_fp_mode norm_mode
= ACTUAL_NORMAL_MODE (FP_MODE
);
8895 rtx addr_reg
= !can_create_pseudo_p () ? get_free_reg (regs_live
) : NULL_RTX
;
8896 emit_fpu_switch (addr_reg
, fp_mode
== norm_mode
);
8899 /* Is the given character a logical line separator for the assembler? */
8900 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8901 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8905 sequence_insn_p (rtx_insn
*insn
)
8907 rtx_insn
* prev
= PREV_INSN (insn
);
8911 rtx_insn
* next
= NEXT_INSN (prev
);
8915 return INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
;
8919 sh_insn_length_adjustment (rtx_insn
*insn
)
8921 /* Instructions with unfilled delay slots take up an extra two bytes for
8922 the nop in the delay slot. */
8923 if (((NONJUMP_INSN_P (insn
)
8924 && GET_CODE (PATTERN (insn
)) != USE
8925 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
8926 || CALL_P (insn
) || JUMP_P (insn
))
8927 && ! sequence_insn_p (insn
)
8928 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
8931 /* Increase the insn length of a cbranch without a delay slot insn to
8932 force a delay slot which will be stuffed with a nop. */
8933 if (TARGET_CBRANCH_FORCE_DELAY_SLOT
&& TARGET_SH2
8934 && JUMP_P (insn
) && get_attr_type (insn
) == TYPE_CBRANCH
8935 && ! sequence_insn_p (insn
))
8938 /* sh-dsp parallel processing insn take four bytes instead of two. */
8940 if (NONJUMP_INSN_P (insn
))
8943 rtx body
= PATTERN (insn
);
8946 bool maybe_label
= true;
8948 if (GET_CODE (body
) == ASM_INPUT
)
8949 templ
= XSTR (body
, 0);
8950 else if (asm_noperands (body
) >= 0)
8952 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
, NULL
);
8961 while (c
== ' ' || c
== '\t');
8962 /* all sh-dsp parallel-processing insns start with p.
8963 The only non-ppi sh insn starting with p is pref.
8964 The only ppi starting with pr is prnd. */
8965 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", templ
, 2))
8967 /* The repeat pseudo-insn expands two three insns, a total of
8968 six bytes in size. */
8969 else if ((c
== 'r' || c
== 'R')
8970 && ! strncasecmp ("epeat", templ
, 5))
8972 while (c
&& c
!= '\n'
8973 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
, templ
))
8975 /* If this is a label, it is obviously not a ppi insn. */
8976 if (c
== ':' && maybe_label
)
8981 else if (c
== '\'' || c
== '"')
8982 maybe_label
= false;
8986 maybe_label
= c
!= ':';
8994 /* Return TRUE for a valid displacement for the REG+disp addressing
8997 sh_legitimate_index_p (machine_mode mode
, rtx op
, bool consider_sh2a
,
9000 if (! CONST_INT_P (op
))
9004 const HOST_WIDE_INT offset
= INTVAL (op
);
9005 const int max_disp
= sh_max_mov_insn_displacement (mode
, consider_sh2a
);
9006 const int align_mask
= mov_insn_alignment_mask (mode
, consider_sh2a
);
9008 /* If the mode does not support any displacement always return false.
9009 Even though an index of '0' is actually always valid, it will cause
9010 troubles when e.g. a DFmode move is split into two SFmode moves,
9011 where one SFmode move will have index '0' and the other move will
9013 if (!allow_zero
&& max_disp
< 1)
9016 return offset
>= 0 && offset
<= max_disp
&& (offset
& align_mask
) == 0;
9020 /* Recognize an RTL expression that is a valid memory address for
9022 The MODE argument is the machine mode for the MEM expression
9023 that wants to use this address.
9032 sh_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
9034 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
9037 if (MAYBE_BASE_REGISTER_RTX_P (x
, strict
))
9039 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
9040 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x
, 0), strict
))
9042 else if (GET_CODE (x
) == PLUS
)
9044 rtx xop0
= XEXP (x
, 0);
9045 rtx xop1
= XEXP (x
, 1);
9047 if (REG_P (xop0
) && REGNO (xop0
) == GBR_REG
)
9048 return gbr_displacement (xop1
, mode
);
9050 if (GET_MODE_SIZE (mode
) <= 8
9051 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
)
9052 && sh_legitimate_index_p (mode
, xop1
, TARGET_SH2A
, false))
9055 if (GET_MODE_SIZE (mode
) <= 4
9056 || (TARGET_FPU_DOUBLE
&& TARGET_FMOVD
&& mode
== DFmode
))
9058 if (MAYBE_BASE_REGISTER_RTX_P (xop1
, strict
)
9059 && MAYBE_INDEX_REGISTER_RTX_P (xop0
, strict
))
9061 if (MAYBE_INDEX_REGISTER_RTX_P (xop1
, strict
)
9062 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
))
9070 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9071 isn't protected by a PIC unspec. */
9073 nonpic_symbol_mentioned_p (rtx x
)
9075 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
9076 || GET_CODE (x
) == PC
)
9079 /* We don't want to look into the possible MEM location of a
9080 CONST_DOUBLE, since we're not going to use it, in general. */
9081 if (GET_CODE (x
) == CONST_DOUBLE
)
9084 if (GET_CODE (x
) == UNSPEC
9085 && (XINT (x
, 1) == UNSPEC_PIC
9086 || XINT (x
, 1) == UNSPEC_GOT
9087 || XINT (x
, 1) == UNSPEC_GOTOFF
9088 || XINT (x
, 1) == UNSPEC_GOTPLT
9089 || XINT (x
, 1) == UNSPEC_GOTTPOFF
9090 || XINT (x
, 1) == UNSPEC_DTPOFF
9091 || XINT (x
, 1) == UNSPEC_TPOFF
9092 || XINT (x
, 1) == UNSPEC_PLT
9093 || XINT (x
, 1) == UNSPEC_PCREL
9094 || XINT (x
, 1) == UNSPEC_SYMOFF
9095 || XINT (x
, 1) == UNSPEC_PCREL_SYMOFF
9096 || XINT (x
, 1) == UNSPEC_GOTFUNCDESC
9097 || XINT (x
, 1) == UNSPEC_GOTOFFFUNCDESC
))
9100 const char* fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9101 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
9105 for (int j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9106 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
9109 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
9116 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9117 @GOTOFF in `reg'. */
9119 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
, rtx reg
)
9121 if (tls_symbolic_operand (orig
, Pmode
) != TLS_MODEL_NONE
)
9124 if (GET_CODE (orig
) == LABEL_REF
9125 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
9127 if (reg
== NULL_RTX
)
9128 reg
= gen_reg_rtx (Pmode
);
9131 && GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (orig
))
9133 /* Weak functions may be NULL which doesn't work with
9134 GOTOFFFUNCDESC because the runtime offset is not known. */
9135 if (SYMBOL_REF_WEAK (orig
))
9136 emit_insn (gen_symGOTFUNCDESC2reg (reg
, orig
));
9138 emit_insn (gen_symGOTOFFFUNCDESC2reg (reg
, orig
));
9140 else if (TARGET_FDPIC
9141 && (GET_CODE (orig
) == LABEL_REF
9142 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_DECL (orig
)
9143 && (TREE_READONLY (SYMBOL_REF_DECL (orig
))
9144 || SYMBOL_REF_EXTERNAL_P (orig
)
9145 || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig
))))))
9146 /* In FDPIC, GOTOFF can only be used for writable data. */
9147 emit_insn (gen_symGOT2reg (reg
, orig
));
9149 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
9152 else if (GET_CODE (orig
) == SYMBOL_REF
)
9154 if (reg
== NULL_RTX
)
9155 reg
= gen_reg_rtx (Pmode
);
9157 if (TARGET_FDPIC
&& SYMBOL_REF_FUNCTION_P (orig
))
9158 emit_insn (gen_symGOTFUNCDESC2reg (reg
, orig
));
9160 emit_insn (gen_symGOT2reg (reg
, orig
));
9166 /* Given a (logical) mode size and an offset in bytes, try to find a the
9167 appropriate displacement value for a mov insn. On SH the displacements
9168 are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max.
9169 15 bytes in QImode. To compensate this we create a new base address by
9170 adding an adjustment value to it.
9172 If the originally requested offset is greater than 127 we prefer using
9173 values 124..127 over 128..131 to increase opportunities to use the
9176 In some cases it is possible that a requested offset might seem unaligned
9177 or inappropriate for the mode size, like offset = 2 and mode size = 4.
9178 This is compensated by adjusting the base address so that the effective
9179 address of the displacement move insn will be aligned.
9181 This is not the best possible way of rebasing the base address, as it
9182 does not look at other present displacement addressings around it.
9183 In some cases this can create more base address adjustments than would
9184 actually be necessary. */
9191 static struct disp_adjust
9192 sh_find_mov_disp_adjust (machine_mode mode
, HOST_WIDE_INT offset
)
9194 struct disp_adjust res
= { NULL_RTX
, NULL_RTX
};
9196 /* Do not try to use SH2A's large displacements here, because this would
9197 effectively disable the small displacement insns. */
9198 const int mode_sz
= GET_MODE_SIZE (mode
);
9199 const int mov_insn_sz
= mov_insn_size (mode
, false);
9200 const int max_disp
= sh_max_mov_insn_displacement (mode
, false);
9201 const int max_disp_next
= max_disp
+ mov_insn_sz
;
9202 HOST_WIDE_INT align_modifier
= offset
> 127 ? mov_insn_sz
: 0;
9203 HOST_WIDE_INT offset_adjust
;
9205 /* In some cases this actually does happen and we must check for it. */
9206 if (mode_sz
< 1 || mode_sz
> 8 || max_disp
< 1)
9209 /* Keeps the previous behavior for QImode displacement addressing.
9210 This just decides how the offset is re-based. Removing this special
9211 case will result in slightly bigger code on average, but it's not that
9213 if (mov_insn_sz
== 1)
9216 offset_adjust
= ((offset
+ align_modifier
) & ~max_disp
) - align_modifier
;
9218 if (mode_sz
+ offset
- offset_adjust
<= max_disp_next
)
9220 res
.offset_adjust
= GEN_INT (offset_adjust
);
9221 res
.mov_disp
= GEN_INT (offset
- offset_adjust
);
9227 /* Try to modify an illegitimate address and make it legitimate.
9228 If we find one, return the new, valid address.
9229 Otherwise, return the original address. */
9231 sh_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
9234 x
= legitimize_pic_address (oldx
, mode
, NULL_RTX
);
9236 if ((TARGET_FPU_DOUBLE
&& mode
== DFmode
)
9237 || (TARGET_SH2E
&& mode
== SFmode
))
9240 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
9241 && BASE_REGISTER_RTX_P (XEXP (x
, 0)))
9243 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
,
9244 INTVAL (XEXP (x
, 1)));
9246 if (adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
9248 rtx sum
= expand_binop (Pmode
, add_optab
, XEXP (x
, 0),
9249 adj
.offset_adjust
, NULL_RTX
, 0,
9251 return gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
9257 /* Attempt to replace *p, which is an address that needs reloading, with
9258 a valid memory address for an operand of mode MODE.
9259 Like for sh_legitimize_address, for the SH we try to get a normal form
9260 of the address. That will allow inheritance of the address reloads. */
9262 sh_legitimize_reload_address (rtx
*p
, machine_mode mode
, int opnum
,
9265 enum reload_type type
= (enum reload_type
) itype
;
9266 const int mode_sz
= GET_MODE_SIZE (mode
);
9271 if (GET_CODE (*p
) == PLUS
&& CONST_INT_P (XEXP (*p
, 1))
9272 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p
, 0), true))
9274 const HOST_WIDE_INT offset
= INTVAL (XEXP (*p
, 1));
9275 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
, offset
);
9277 if (TARGET_SH2A
&& mode
== DFmode
&& (offset
& 0x7))
9279 push_reload (*p
, NULL_RTX
, p
, NULL
,
9280 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9284 if (TARGET_SH2E
&& mode
== SFmode
)
9287 push_reload (*p
, NULL_RTX
, p
, NULL
,
9288 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9292 /* FIXME: Do not allow to legitimize QImode and HImode displacement
9293 moves because then reload has a problem figuring the constraint
9294 that the move insn target/source reg must be R0.
9295 Or maybe some handling is wrong in sh_secondary_reload for this
9296 to work properly? */
9297 if ((mode_sz
== 4 || mode_sz
== 8)
9298 && ! (TARGET_SH4
&& mode
== DFmode
)
9299 && adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
9301 rtx sum
= gen_rtx_PLUS (Pmode
, XEXP (*p
, 0), adj
.offset_adjust
);
9302 *p
= gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
9303 push_reload (sum
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
9304 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9309 /* We must re-recognize what we created before. */
9310 if (GET_CODE (*p
) == PLUS
9311 && (mode_sz
== 4 || mode_sz
== 8)
9312 && GET_CODE (XEXP (*p
, 0)) == PLUS
9313 && CONST_INT_P (XEXP (XEXP (*p
, 0), 1))
9314 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p
, 0), 0), true)
9315 && CONST_INT_P (XEXP (*p
, 1))
9316 && ! (TARGET_SH2E
&& mode
== SFmode
))
9318 /* Because this address is so complex, we know it must have
9319 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9320 it is already unshared, and needs no further unsharing. */
9321 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
9322 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9329 /* In the name of slightly smaller debug output, and to cater to
9330 general assembler lossage, recognize various UNSPEC sequences
9331 and turn them back into a direct symbol reference. */
9333 sh_delegitimize_address (rtx orig_x
)
9335 orig_x
= delegitimize_mem_from_attrs (orig_x
);
9340 if (GET_CODE (x
) == CONST
)
9342 rtx y
= XEXP (x
, 0);
9343 if (GET_CODE (y
) == UNSPEC
)
9345 if (XINT (y
, 1) == UNSPEC_GOT
9346 || XINT (y
, 1) == UNSPEC_GOTOFF
9347 || XINT (y
, 1) == UNSPEC_SYMOFF
)
9348 return XVECEXP (y
, 0, 0);
9349 else if (XINT (y
, 1) == UNSPEC_PCREL_SYMOFF
)
9351 if (GET_CODE (XVECEXP (y
, 0, 0)) == CONST
)
9353 rtx symplt
= XEXP (XVECEXP (y
, 0, 0), 0);
9355 if (GET_CODE (symplt
) == UNSPEC
9356 && (XINT (symplt
, 1) == UNSPEC_PLT
9357 || XINT (symplt
, 1) == UNSPEC_PCREL
))
9358 return XVECEXP (symplt
, 0, 0);
9367 /* Mark the use of a constant in the literal table. If the constant
9368 has multiple labels, make it unique. */
9370 mark_constant_pool_use (rtx x
)
9375 switch (GET_CODE (x
))
9385 /* Get the first label in the list of labels for the same constant
9386 and delete another labels in the list. */
9387 rtx_insn
* lab
= as_a
<rtx_insn
*> (x
);
9388 for (rtx_insn
* insn
= PREV_INSN (lab
); insn
; insn
= PREV_INSN (insn
))
9391 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
9396 for (rtx insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
9397 as_a
<rtx_insn
*> (insn
)->set_deleted ();
9399 /* Mark constants in a window. */
9400 for (rtx_insn
* insn
= NEXT_INSN (as_a
<rtx_insn
*> (x
)); insn
;
9401 insn
= NEXT_INSN (insn
))
9403 if (!NONJUMP_INSN_P (insn
))
9406 rtx pattern
= PATTERN (insn
);
9407 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
9410 switch (XINT (pattern
, 1))
9412 case UNSPECV_CONST2
:
9413 case UNSPECV_CONST4
:
9414 case UNSPECV_CONST8
:
9415 XVECEXP (pattern
, 0, 1) = const1_rtx
;
9417 case UNSPECV_WINDOW_END
:
9418 if (XVECEXP (pattern
, 0, 0) == x
)
9421 case UNSPECV_CONST_END
:
9431 /* Return true if it's possible to redirect BRANCH1 to the destination
9432 of an unconditional jump BRANCH2. We only want to do this if the
9433 resulting branch will have a short displacement. */
9435 sh_can_follow_jump (const rtx_insn
*branch1
, const rtx_insn
*branch2
)
9437 /* Don't follow if BRANCH2 is possible to be a jump crossing between
9438 hot and cold partitions. */
9439 if (flag_reorder_blocks_and_partition
9440 && simplejump_p (branch2
)
9441 && CROSSING_JUMP_P (branch2
))
9444 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
9446 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
9450 for (distance
= 0, insn
= NEXT_INSN (branch1
);
9451 insn
&& distance
< 256;
9452 insn
= PREV_INSN (insn
))
9457 distance
+= get_attr_length (insn
);
9459 for (distance
= 0, insn
= NEXT_INSN (branch1
);
9460 insn
&& distance
< 256;
9461 insn
= NEXT_INSN (insn
))
9466 distance
+= get_attr_length (insn
);
9472 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9474 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
9475 unsigned int new_reg
)
9477 /* Interrupt functions can only use registers that have already been
9478 saved by the prologue, even if they would normally be
9480 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg
))
9486 /* Function to update the integer COST
9487 based on the relationship between INSN that is dependent on
9488 DEP_INSN through the dependence LINK. The default is to make no
9489 adjustment to COST. This can be used for example to specify to
9490 the scheduler that an output- or anti-dependence does not incur
9491 the same cost as a data-dependence. The return value should be
9492 the new value for COST. */
9494 sh_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
9501 if (recog_memoized (insn
) < 0
9502 || recog_memoized (dep_insn
) < 0)
9505 rtx dep_set
= single_set (dep_insn
);
9507 /* The latency that we specify in the scheduling description refers
9508 to the actual output, not to an auto-increment register; for that,
9509 the latency is one. */
9510 if (dep_set
&& MEM_P (SET_SRC (dep_set
)) && cost
> 1)
9512 rtx set
= single_set (insn
);
9515 && !reg_mentioned_p (SET_DEST (dep_set
), SET_SRC (set
))
9516 && (!MEM_P (SET_DEST (set
))
9517 || !reg_mentioned_p (SET_DEST (dep_set
),
9518 XEXP (SET_DEST (set
), 0))))
9521 /* The only input for a call that is timing-critical is the
9522 function's address. */
9525 rtx call
= get_call_rtx_from (insn
);
9527 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9528 && (GET_CODE (XEXP (XEXP (call
, 0), 0)) == UNSPEC
9529 || ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
)))
9530 cost
-= TARGET_SH4_300
? 3 : 6;
9532 /* Likewise, the most timing critical input for an sfuncs call
9533 is the function address. However, sfuncs typically start
9534 using their arguments pretty quickly.
9535 Assume a four cycle delay for SH4 before they are needed.
9536 Cached ST40-300 calls are quicker, so assume only a one
9538 ??? Maybe we should encode the delays till input registers
9539 are needed by sfuncs into the sfunc call insn. */
9540 /* All sfunc calls are parallels with at least four components.
9541 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9542 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
9543 && XVECLEN (PATTERN (insn
), 0) >= 4
9544 && (reg
= sfunc_uses_reg (insn
)))
9546 if (! reg_set_p (reg
, dep_insn
))
9547 cost
-= TARGET_SH4_300
? 1 : 4;
9549 if (TARGET_HARD_SH4
&& !TARGET_SH4_300
)
9551 attr_type dep_type
= get_attr_type (dep_insn
);
9553 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
9555 else if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
9556 && (type
= get_attr_type (insn
)) != TYPE_CALL
9557 && type
!= TYPE_SFUNC
)
9559 /* When the preceding instruction loads the shift amount of
9560 the following SHAD/SHLD, the latency of the load is increased
9562 if (get_attr_type (insn
) == TYPE_DYN_SHIFT
9563 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
9564 && reg_overlap_mentioned_p (SET_DEST (dep_set
),
9565 XEXP (SET_SRC (single_set (insn
)),
9568 /* When an LS group instruction with a latency of less than
9569 3 cycles is followed by a double-precision floating-point
9570 instruction, FIPR, or FTRV, the latency of the first
9571 instruction is increased to 3 cycles. */
9573 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
9574 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
9576 /* The lsw register of a double-precision computation is ready one
9578 else if (reload_completed
9579 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
9580 && (use_pat
= single_set (insn
))
9581 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
9585 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
9586 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
9589 else if (TARGET_SH4_300
)
9591 /* Stores need their input register two cycles later. */
9593 if (dep_set
&& cost
>= 1
9594 && ((type
= get_attr_type (insn
)) == TYPE_STORE
9595 || type
== TYPE_PSTORE
9596 || type
== TYPE_FSTORE
|| type
== TYPE_MAC_MEM
))
9598 rtx set
= single_set (insn
);
9600 if (!reg_mentioned_p (SET_SRC (set
), XEXP (SET_DEST (set
), 0))
9601 && rtx_equal_p (SET_SRC (set
), SET_DEST (dep_set
)))
9604 /* But don't reduce the cost below 1 if the address depends
9605 on a side effect of dep_insn. */
9607 && modified_in_p (XEXP (SET_DEST (set
), 0), dep_insn
))
9613 /* An anti-dependence penalty of two applies if the first insn is a double
9614 precision fadd / fsub / fmul. */
9615 else if (!TARGET_SH4_300
9616 && dep_type
== REG_DEP_ANTI
9617 && recog_memoized (dep_insn
) >= 0
9618 && (get_attr_type (dep_insn
) == TYPE_DFP_ARITH
9619 || get_attr_type (dep_insn
) == TYPE_DFP_MUL
)
9620 /* A lot of alleged anti-flow dependences are fake,
9621 so check this one is real. */
9622 && flow_dependent_p (dep_insn
, insn
))
9628 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9629 if DEP_INSN is anti-flow dependent on INSN. */
9631 flow_dependent_p (rtx_insn
*insn
, rtx_insn
*dep_insn
)
9633 rtx tmp
= PATTERN (insn
);
9635 note_stores (dep_insn
, flow_dependent_p_1
, &tmp
);
9636 return tmp
== NULL_RTX
;
9639 /* A helper function for flow_dependent_p called through note_stores. */
9641 flow_dependent_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
9643 rtx
* pinsn
= (rtx
*) data
;
9645 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
9649 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9650 'special function' patterns (type sfunc) that clobber pr, but that
9651 do not look like function calls to leaf_function_p. Hence we must
9652 do this extra check. */
9656 return DF_REG_DEF_COUNT (PR_REG
);
9659 /* Return where to allocate pseudo for a given hard register initial
9662 sh_allocate_initial_value (rtx hard_reg
)
9664 if (REGNO (hard_reg
) == PR_REG
)
9666 if (crtl
->is_leaf
&& ! sh_pr_n_sets ())
9669 return gen_frame_mem (Pmode
, return_address_pointer_rtx
);
9675 /* This function returns "2" to indicate dual issue for the SH4
9676 processor. To be used by the DFA pipeline description. */
9678 sh_issue_rate (void)
9680 if (TARGET_SUPERSCALAR
)
9686 /* Functions for ready queue reordering for sched1. */
9688 /* Get weight for mode for a set x. */
9690 find_set_regmode_weight (rtx x
, machine_mode mode
)
9692 if (GET_CODE (x
) == CLOBBER
&& register_operand (SET_DEST (x
), mode
))
9694 if (GET_CODE (x
) == SET
&& register_operand (SET_DEST (x
), mode
))
9696 if (REG_P (SET_DEST (x
)))
9698 if (!reg_mentioned_p (SET_DEST (x
), SET_SRC (x
)))
9708 /* Get regmode weight for insn. */
9710 find_insn_regmode_weight (rtx insn
, machine_mode mode
)
9712 /* Increment weight for each register born here. */
9713 rtx x
= PATTERN (insn
);
9714 short reg_weight
= find_set_regmode_weight (x
, mode
);
9715 if (GET_CODE (x
) == PARALLEL
)
9718 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
9720 x
= XVECEXP (PATTERN (insn
), 0, j
);
9721 reg_weight
+= find_set_regmode_weight (x
, mode
);
9724 /* Decrement weight for each register that dies here. */
9725 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
9727 if (REG_NOTE_KIND (x
) == REG_DEAD
|| REG_NOTE_KIND (x
) == REG_UNUSED
)
9729 rtx note
= XEXP (x
, 0);
9730 if (REG_P (note
) && GET_MODE (note
) == mode
)
9737 /* Calculate regmode weights for all insns of a basic block. */
9739 find_regmode_weight (basic_block b
, machine_mode mode
)
9741 rtx_insn
*insn
, *next_tail
, *head
, *tail
;
9743 get_ebb_head_tail (b
, b
, &head
, &tail
);
9744 next_tail
= NEXT_INSN (tail
);
9746 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
9748 /* Handle register life information. */
9753 INSN_REGMODE_WEIGHT (insn
, mode
) =
9754 find_insn_regmode_weight (insn
, mode
)
9755 + 2 * find_insn_regmode_weight (insn
, DFmode
);
9756 else if (mode
== SImode
)
9757 INSN_REGMODE_WEIGHT (insn
, mode
) =
9758 find_insn_regmode_weight (insn
, mode
)
9759 + 2 * find_insn_regmode_weight (insn
, DImode
);
9763 /* Comparison function for ready queue sorting. */
9765 rank_for_reorder (const void *x
, const void *y
)
9767 rtx_insn
*tmp
= *(rtx_insn
* const *) y
;
9768 rtx_insn
*tmp2
= *(rtx_insn
* const *) x
;
9770 /* The insn in a schedule group should be issued the first. */
9771 if (SCHED_GROUP_P (tmp
) != SCHED_GROUP_P (tmp2
))
9772 return SCHED_GROUP_P (tmp2
) ? 1 : -1;
9774 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9775 minimizes instruction movement, thus minimizing sched's effect on
9776 register pressure. */
9777 return INSN_LUID (tmp
) - INSN_LUID (tmp2
);
9780 /* Resort the array A in which only element at index N may be out of order. */
9782 swap_reorder (rtx_insn
**a
, int n
)
9784 rtx_insn
*insn
= a
[n
- 1];
9787 while (i
>= 0 && rank_for_reorder (a
+ i
, &insn
) >= 0)
9795 /* Sort the ready list by ascending priority. */
9797 ready_reorder (rtx_insn
**ready
, int nready
)
9800 swap_reorder (ready
, nready
);
9801 else if (nready
> 2)
9802 qsort (ready
, nready
, sizeof (rtx_insn
*), rank_for_reorder
);
9805 /* Count life regions of r0 for a block. */
9807 find_r0_life_regions (basic_block b
)
9813 if (REGNO_REG_SET_P (df_get_live_in (b
), R0_REG
))
9824 rtx_insn
* insn
= BB_HEAD (b
);
9825 rtx_insn
* end
= BB_END (b
);
9826 rtx r0_reg
= gen_rtx_REG (SImode
, R0_REG
);
9831 if (find_regno_note (insn
, REG_DEAD
, R0_REG
))
9839 && (pset
= single_set (insn
))
9840 && reg_overlap_mentioned_p (r0_reg
, SET_DEST (pset
))
9841 && !find_regno_note (insn
, REG_UNUSED
, R0_REG
))
9849 insn
= NEXT_INSN (insn
);
9854 /* Calculate regmode weights for all insns of all basic block. */
9856 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED
,
9857 int verbose ATTRIBUTE_UNUSED
,
9862 regmode_weight
[0] = (short *) xcalloc (old_max_uid
, sizeof (short));
9863 regmode_weight
[1] = (short *) xcalloc (old_max_uid
, sizeof (short));
9864 r0_life_regions
= 0;
9866 FOR_EACH_BB_REVERSE_FN (b
, cfun
)
9868 find_regmode_weight (b
, SImode
);
9869 find_regmode_weight (b
, SFmode
);
9870 if (!reload_completed
)
9871 r0_life_regions
+= find_r0_life_regions (b
);
9874 CURR_REGMODE_PRESSURE (SImode
) = 0;
9875 CURR_REGMODE_PRESSURE (SFmode
) = 0;
9880 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
9881 int verbose ATTRIBUTE_UNUSED
)
9883 if (regmode_weight
[0])
9885 free (regmode_weight
[0]);
9886 regmode_weight
[0] = NULL
;
9888 if (regmode_weight
[1])
9890 free (regmode_weight
[1]);
9891 regmode_weight
[1] = NULL
;
9895 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9896 keep count of register pressures on SImode and SFmode. */
9898 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
9899 int sched_verbose ATTRIBUTE_UNUSED
,
9903 if (GET_CODE (PATTERN (insn
)) != USE
9904 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
9905 cached_can_issue_more
= can_issue_more
- 1;
9907 cached_can_issue_more
= can_issue_more
;
9909 if (reload_completed
)
9910 return cached_can_issue_more
;
9912 CURR_REGMODE_PRESSURE (SImode
) += INSN_REGMODE_WEIGHT (insn
, SImode
);
9913 CURR_REGMODE_PRESSURE (SFmode
) += INSN_REGMODE_WEIGHT (insn
, SFmode
);
9915 return cached_can_issue_more
;
9919 sh_md_init (FILE *dump ATTRIBUTE_UNUSED
,
9920 int verbose ATTRIBUTE_UNUSED
,
9921 int veclen ATTRIBUTE_UNUSED
)
9923 CURR_REGMODE_PRESSURE (SImode
) = 0;
9924 CURR_REGMODE_PRESSURE (SFmode
) = 0;
9927 /* Some magic numbers. */
9928 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9929 functions that already have high pressure on r0. */
9930 #define R0_MAX_LIFE_REGIONS 2
9931 /* Register Pressure thresholds for SImode and SFmode registers. */
9932 #define SIMODE_MAX_WEIGHT 5
9933 #define SFMODE_MAX_WEIGHT 10
9935 /* Return true if the pressure is high for MODE. */
9937 high_pressure (machine_mode mode
)
9939 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9940 functions that already have high pressure on r0. */
9941 if (r0_life_regions
>= R0_MAX_LIFE_REGIONS
)
9945 return (CURR_REGMODE_PRESSURE (SFmode
) > SFMODE_MAX_WEIGHT
);
9947 return (CURR_REGMODE_PRESSURE (SImode
) > SIMODE_MAX_WEIGHT
);
9950 /* Reorder ready queue if register pressure is high. */
9952 sh_reorder (FILE *dump ATTRIBUTE_UNUSED
,
9953 int sched_verbose ATTRIBUTE_UNUSED
,
9956 int clock_var ATTRIBUTE_UNUSED
)
9958 if (reload_completed
)
9959 return sh_issue_rate ();
9961 if (high_pressure (SFmode
) || high_pressure (SImode
))
9963 ready_reorder (ready
, *n_readyp
);
9966 return sh_issue_rate ();
9969 /* Skip cycles if the current register pressure is high. */
9971 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
9972 int sched_verbose ATTRIBUTE_UNUSED
,
9973 rtx_insn
**ready ATTRIBUTE_UNUSED
,
9974 int *n_readyp ATTRIBUTE_UNUSED
,
9975 int clock_var ATTRIBUTE_UNUSED
)
9977 if (reload_completed
)
9978 return cached_can_issue_more
;
9980 if (high_pressure(SFmode
) || high_pressure (SImode
))
9983 return cached_can_issue_more
;
9986 /* Skip cycles without sorting the ready queue. This will move insn from
9987 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9988 queue by sh_reorder. */
9990 /* Generally, skipping these many cycles are sufficient for all insns to move
9995 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED
,
9996 int sched_verbose ATTRIBUTE_UNUSED
,
9997 rtx_insn
*insn ATTRIBUTE_UNUSED
,
10002 if (reload_completed
)
10007 if ((clock_var
- last_clock_var
) < MAX_SKIPS
)
10012 /* If this is the last cycle we are skipping, allow reordering of R. */
10013 if ((clock_var
- last_clock_var
) == MAX_SKIPS
)
10026 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED
)
10028 return TARGET_HITACHI
|| sh_attr_renesas_p (record_type
);
10032 On the SH1..SH4, the trampoline looks like
10033 2 0002 D202 mov.l l2,r2
10034 1 0000 D301 mov.l l1,r3
10035 3 0004 422B jmp @r2
10037 5 0008 00000000 l1: .long area
10038 6 000c 00000000 l2: .long function
10040 FDPIC needs a form that includes a function descriptor and
10041 code to load the GOT register:
10042 0 0000 00000000 .long l0
10043 1 0004 00000000 .long gotval
10044 2 0008 D302 l0: mov.l l1,r3
10045 3 000a D203 mov.l l2,r2
10046 4 000c 6122 mov.l @r2,r1
10047 5 000e 5C21 mov.l @(4,r2),r12
10048 6 0010 412B jmp @r1
10050 8 0014 00000000 l1: .long area
10051 9 0018 00000000 l2: .long function
10053 SH5 (compact) uses r1 instead of r3 for the static chain. */
10055 /* Emit insns to store a value at memory address + offset. */
10057 sh_emit_storesi (rtx addr
, HOST_WIDE_INT offset
, rtx value
)
10059 gcc_assert ((offset
& 3) == 0);
10060 emit_move_insn (offset
== 0
10061 ? change_address (addr
, SImode
, NULL_RTX
)
10062 : adjust_address (addr
, SImode
, offset
), value
);
10065 /* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */
10067 sh_emit_storehi (rtx addr
, HOST_WIDE_INT offset
, uint16_t w0
, uint16_t w1
)
10069 sh_emit_storesi (addr
, offset
, gen_int_mode (TARGET_LITTLE_ENDIAN
10070 ? (w0
| (w1
<< 16))
10071 : (w1
| (w0
<< 16)), SImode
));
10074 /* Emit RTL insns to initialize the variable parts of a trampoline.
10075 FNADDR is an RTX for the address of the function's pure code.
10076 CXT is an RTX for the static chain value for the function. */
10078 sh_trampoline_init (rtx tramp_mem
, tree fndecl
, rtx cxt
)
10080 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10081 rtx tramp
= force_reg (Pmode
, XEXP (tramp_mem
, 0));
10085 rtx a
= force_reg (Pmode
, plus_constant (Pmode
, XEXP (tramp_mem
, 0), 8));
10087 sh_emit_storesi (tramp_mem
, 0, a
);
10088 sh_emit_storesi (tramp_mem
, 4, sh_get_fdpic_reg_initial_val ());
10090 sh_emit_storehi (tramp_mem
, 8, 0xd302, 0xd203);
10091 sh_emit_storehi (tramp_mem
, 12, 0x6122, 0x5c21);
10092 sh_emit_storehi (tramp_mem
, 16, 0x412b, 0x0009);
10094 sh_emit_storesi (tramp_mem
, 20, cxt
);
10095 sh_emit_storesi (tramp_mem
, 24, fnaddr
);
10099 sh_emit_storehi (tramp_mem
, 0, 0xd202, 0xd301);
10100 sh_emit_storehi (tramp_mem
, 4, 0x422b, 0x0009);
10102 sh_emit_storesi (tramp_mem
, 8, cxt
);
10103 sh_emit_storesi (tramp_mem
, 12, fnaddr
);
10105 if (TARGET_HARD_SH4
)
10107 if (!TARGET_INLINE_IC_INVALIDATE
10108 || (!(TARGET_SH4A
|| TARGET_SH4_300
) && TARGET_USERMODE
))
10109 emit_library_call (function_symbol (NULL
, "__ic_invalidate",
10110 FUNCTION_ORDINARY
).sym
,
10111 LCT_NORMAL
, VOIDmode
, tramp
, SImode
);
10113 emit_insn (gen_ic_invalidate_line (tramp
));
10117 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10119 sh_trampoline_adjust_address (rtx tramp
)
10124 /* If PIC, we cannot make sibling calls to global functions
10125 because the PLT requires r12 to be live. */
10127 sh_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10130 && ! sh_cfun_interrupt_handler_p ()
10131 && (! flag_pic
|| TARGET_FDPIC
10132 || (decl
&& ! (TREE_PUBLIC (decl
) || DECL_WEAK (decl
)))
10133 || (decl
&& DECL_VISIBILITY (decl
) != VISIBILITY_DEFAULT
)));
10136 /* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
10138 sh_expand_sym_label2reg (rtx reg
, rtx sym
, rtx lab
, bool sibcall_p
)
10140 const_tree decl
= SYMBOL_REF_DECL (sym
);
10141 bool is_weak
= (decl
&& DECL_P (decl
) && DECL_WEAK (decl
));
10143 if (!is_weak
&& SYMBOL_REF_LOCAL_P (sym
))
10144 emit_insn (gen_sym_label2reg (reg
, sym
, lab
));
10145 else if (sibcall_p
&& SYMBOL_REF_LOCAL_P (sym
))
10146 emit_insn (gen_symPCREL_label2reg (reg
, sym
, lab
));
10148 emit_insn (gen_symPLT_label2reg (reg
, sym
, lab
));
10151 /* Machine specific built-in functions. */
10153 struct builtin_description
10155 bool (* const is_enabled
) (void);
10156 const enum insn_code icode
;
10157 const char *const name
;
10162 /* This function can be used if there are any built-ins that are not for
10163 SHmedia. It's commented out to avoid the defined-but-unused warning. */
10165 sh1_builtin_p (void)
10170 /* describe number and signedness of arguments; arg[0] == result
10171 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10172 /* 9: 64-bit pointer, 10: 32-bit pointer */
10173 static const char signature_args
[][4] =
10175 #define SH_BLTIN_V2SI2 0
10177 #define SH_BLTIN_V4HI2 1
10179 #define SH_BLTIN_V2SI3 2
10181 #define SH_BLTIN_V4HI3 3
10183 #define SH_BLTIN_V8QI3 4
10185 #define SH_BLTIN_MAC_HISI 5
10187 #define SH_BLTIN_SH_HI 6
10189 #define SH_BLTIN_SH_SI 7
10191 #define SH_BLTIN_V4HI2V2SI 8
10193 #define SH_BLTIN_V4HI2V8QI 9
10195 #define SH_BLTIN_SISF 10
10197 #define SH_BLTIN_LDUA_L 11
10199 #define SH_BLTIN_LDUA_Q 12
10201 #define SH_BLTIN_STUA_L 13
10203 #define SH_BLTIN_STUA_Q 14
10205 #define SH_BLTIN_LDUA_L64 15
10207 #define SH_BLTIN_LDUA_Q64 16
10209 #define SH_BLTIN_STUA_L64 17
10211 #define SH_BLTIN_STUA_Q64 18
10213 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10214 #define SH_BLTIN_2 19
10215 #define SH_BLTIN_SU 19
10217 #define SH_BLTIN_3 20
10218 #define SH_BLTIN_SUS 20
10220 #define SH_BLTIN_PSSV 21
10222 #define SH_BLTIN_XXUU 22
10223 #define SH_BLTIN_UUUU 22
10225 #define SH_BLTIN_PV 23
10227 #define SH_BLTIN_VP 24
10229 #define SH_BLTIN_UV 25
10231 #define SH_BLTIN_VU 26
10234 /* mcmv: operands considered unsigned. */
10235 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10236 /* mperm: control value considered unsigned int. */
10237 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10238 /* mshards_q: returns signed short. */
10239 /* nsb: takes long long arg, returns unsigned char. */
10240 static struct builtin_description bdesc
[] =
10243 CODE_FOR_sts_fpscr
, "__builtin_sh_get_fpscr", SH_BLTIN_UV
, 0 },
10245 CODE_FOR_set_fpscr
, "__builtin_sh_set_fpscr", SH_BLTIN_VU
, 0 },
10248 static tree sh_builtin_get_fpscr
;
10249 static tree sh_builtin_set_fpscr
;
10252 sh_init_builtins (void)
10254 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
10255 memset (shared
, 0, sizeof shared
);
10257 for (unsigned int di
= 0; di
< ARRAY_SIZE (bdesc
); ++di
)
10259 builtin_description
* d
= &bdesc
[di
];
10261 if (!d
->is_enabled ())
10264 tree type
, arg_type
= NULL_TREE
;
10265 int signature
= d
->signature
;
10267 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
10268 type
= shared
[signature
];
10271 int has_result
= signature_args
[signature
][0] != 0;
10274 if (! TARGET_FPU_ANY
10275 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
10277 for (unsigned int i
= 0; i
< ARRAY_SIZE (args
); i
++)
10278 args
[i
] = NULL_TREE
;
10279 for (int i
= 3; ; i
--)
10281 int arg
= signature_args
[signature
][i
];
10282 int opno
= i
- 1 + has_result
;
10285 arg_type
= ptr_type_node
;
10287 arg_type
= (*lang_hooks
.types
.type_for_mode
)
10288 (insn_data
[d
->icode
].operand
[opno
].mode
, (arg
& 1));
10292 arg_type
= void_type_node
;
10295 args
[i
-1] = arg_type
;
10297 type
= build_function_type_list (arg_type
, args
[0], args
[1],
10298 args
[2], NULL_TREE
);
10299 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
10300 shared
[signature
] = type
;
10303 add_builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
10305 /* Recode {sts,set}_fpscr decls for sh_atomic_assign_expand_fenv. */
10306 if (d
->icode
== CODE_FOR_sts_fpscr
)
10307 sh_builtin_get_fpscr
= d
->fndecl
;
10308 else if (d
->icode
== CODE_FOR_set_fpscr
)
10309 sh_builtin_set_fpscr
= d
->fndecl
;
10313 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
10316 sh_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
10318 const unsigned SH_FE_INVALID
= 64;
10319 const unsigned SH_FE_DIVBYZERO
= 32;
10320 const unsigned SH_FE_OVERFLOW
= 16;
10321 const unsigned SH_FE_UNDERFLOW
= 8;
10322 const unsigned SH_FE_INEXACT
= 4;
10323 const unsigned HOST_WIDE_INT SH_FE_ALL_EXCEPT
= (SH_FE_INVALID
10328 const unsigned HOST_WIDE_INT SH_FE_EXCEPT_SHIFT
= 5;
10329 tree fenv_var
, mask
, ld_fenv
, masked_fenv
;
10330 tree new_fenv_var
, reload_fenv
, restore_fnenv
;
10331 tree update_call
, atomic_feraiseexcept
, hold_fnclex
;
10333 if (! TARGET_FPU_ANY
)
10336 /* Generate the equivalent of :
10337 unsigned int fenv_var;
10338 fenv_var = __builtin_sh_get_fpscr ();
10340 unsigned int masked_fenv;
10341 masked_fenv = fenv_var & mask;
10343 __builtin_sh_set_fpscr (masked_fenv); */
10345 fenv_var
= create_tmp_var_raw (unsigned_type_node
);
10346 mask
= build_int_cst (unsigned_type_node
,
10347 ~((SH_FE_ALL_EXCEPT
<< SH_FE_EXCEPT_SHIFT
)
10348 | SH_FE_ALL_EXCEPT
));
10349 ld_fenv
= build2 (MODIFY_EXPR
, unsigned_type_node
,
10350 fenv_var
, build_call_expr (sh_builtin_get_fpscr
, 0));
10351 masked_fenv
= build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
, mask
);
10352 hold_fnclex
= build_call_expr (sh_builtin_set_fpscr
, 1, masked_fenv
);
10353 fenv_var
= build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
10354 build2 (COMPOUND_EXPR
, void_type_node
, masked_fenv
,
10356 NULL_TREE
, NULL_TREE
);
10357 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, fenv_var
, hold_fnclex
);
10359 /* Store the value of masked_fenv to clear the exceptions:
10360 __builtin_sh_set_fpscr (masked_fenv); */
10362 *clear
= build_call_expr (sh_builtin_set_fpscr
, 1, masked_fenv
);
10364 /* Generate the equivalent of :
10365 unsigned int new_fenv_var;
10366 new_fenv_var = __builtin_sh_get_fpscr ();
10368 __builtin_sh_set_fpscr (fenv_var);
10370 __atomic_feraiseexcept (new_fenv_var); */
10372 new_fenv_var
= create_tmp_var_raw (unsigned_type_node
);
10373 reload_fenv
= build2 (MODIFY_EXPR
, unsigned_type_node
, new_fenv_var
,
10374 build_call_expr (sh_builtin_get_fpscr
, 0));
10375 restore_fnenv
= build_call_expr (sh_builtin_set_fpscr
, 1, fenv_var
);
10376 atomic_feraiseexcept
= builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
10377 update_call
= build_call_expr (atomic_feraiseexcept
, 1,
10378 fold_convert (integer_type_node
,
10380 *update
= build2 (COMPOUND_EXPR
, void_type_node
,
10381 build2 (COMPOUND_EXPR
, void_type_node
,
10382 reload_fenv
, restore_fnenv
), update_call
);
10385 /* Implements target hook vector_mode_supported_p. */
10387 sh_vector_mode_supported_p (machine_mode mode ATTRIBUTE_UNUSED
)
10393 sh_frame_pointer_required (void)
10395 /* If needed override this in other tm.h files to cope with various OS
10396 lossage requiring a frame pointer. */
10397 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
10406 /* Implements target hook dwarf_calling_convention. Return an enum
10407 of dwarf_calling_convention. */
10409 sh_dwarf_calling_convention (const_tree func
)
10411 if (sh_attr_renesas_p (func
))
10412 return DW_CC_GNU_renesas_sh
;
10414 return DW_CC_normal
;
10417 /* Returns the sh builtin decl for CODE. */
10419 sh_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10421 if (code
>= ARRAY_SIZE (bdesc
))
10422 return error_mark_node
;
10424 if (!bdesc
[code
].is_enabled ())
10425 return error_mark_node
;
10427 return bdesc
[code
].fndecl
;
10430 /* Expand an expression EXP that calls a built-in function,
10431 with result going to TARGET if that's convenient
10432 (and in mode MODE if that's convenient).
10433 SUBTARGET may be used as the target for computing one of EXP's operands.
10434 IGNORE is nonzero if the value is to be ignored. */
10436 sh_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10437 machine_mode mode ATTRIBUTE_UNUSED
, int ignore
)
10439 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10440 unsigned int fcode
= DECL_MD_FUNCTION_CODE (fndecl
);
10441 const struct builtin_description
*d
= &bdesc
[fcode
];
10442 enum insn_code icode
= d
->icode
;
10443 int signature
= d
->signature
;
10447 if (signature_args
[signature
][0])
10452 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10453 if (! target
|| GET_MODE (target
) != tmode
10454 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10455 target
= gen_reg_rtx (tmode
);
10456 op
[nop
++] = target
;
10461 for (int i
= 1; i
<= 3; i
++, nop
++)
10463 if (! signature_args
[signature
][i
])
10465 tree arg
= CALL_EXPR_ARG (exp
, i
- 1);
10466 if (arg
== error_mark_node
)
10469 machine_mode opmode
;
10471 if (signature_args
[signature
][i
] & 8)
10474 optype
= ptr_type_node
;
10478 opmode
= insn_data
[icode
].operand
[nop
].mode
;
10479 optype
= (*lang_hooks
.types
.type_for_mode
) (opmode
, 0);
10482 machine_mode argmode
= TYPE_MODE (TREE_TYPE (arg
));
10483 if (argmode
!= opmode
)
10484 arg
= build1 (NOP_EXPR
, optype
, arg
);
10485 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, EXPAND_NORMAL
);
10486 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
10487 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
10490 rtx pat
= NULL_RTX
;
10495 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
10498 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
10501 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
10504 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
10507 gcc_unreachable ();
10515 /* Implement TARGET_HARD_REGNO_NREGS. On the SH all but the XD regs are
10516 UNITS_PER_WORD bits wide. */
10518 static unsigned int
10519 sh_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
10521 if (XD_REGISTER_P (regno
))
10522 return CEIL (GET_MODE_SIZE (mode
), 2 * UNITS_PER_WORD
);
10523 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
10526 /* Implement TARGET_HARD_REGNO_MODE_OK.
10528 We can allow any mode in any general register. The special registers
10529 only allow SImode. Don't allow any mode in the PR.
10531 We cannot hold DCmode values in the XD registers because alter_reg
10532 handles subregs of them incorrectly. We could work around this by
10533 spacing the XD registers like the DR registers, but this would require
10534 additional memory in every compilation to hold larger register vectors.
10535 We could hold SFmode / SCmode values in XD registers, but that
10536 would require a tertiary reload when reloading from / to memory,
10537 and a secondary reload to reload from / to general regs; that
10538 seems to be a losing proposition.
10540 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10541 it won't be ferried through GP registers first. */
10543 sh_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
10545 if (SPECIAL_REGISTER_P (regno
))
10546 return mode
== SImode
;
10548 if (regno
== FPUL_REG
)
10549 return (mode
== SImode
|| mode
== SFmode
);
10551 if (FP_REGISTER_P (regno
) && mode
== SFmode
)
10554 if (mode
== V2SFmode
)
10556 if (((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 2 == 0)
10557 || GENERAL_REGISTER_P (regno
)))
10563 if (mode
== V4SFmode
)
10565 if ((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 4 == 0)
10566 || GENERAL_REGISTER_P (regno
))
10572 if (mode
== V16SFmode
)
10573 return regno
== FIRST_XD_REG
;
10575 if (FP_REGISTER_P (regno
))
10579 || ((TARGET_SH2E
) && mode
== SCmode
)
10580 || (((TARGET_FPU_DOUBLE
&& mode
== DFmode
) || mode
== DCmode
)
10581 && ((regno
- FIRST_FP_REG
) & 1) == 0)
10582 || (TARGET_SH4
&& mode
== TImode
10583 && ((regno
- FIRST_FP_REG
) & 3) == 0))
10589 if (XD_REGISTER_P (regno
))
10590 return mode
== DFmode
;
10592 if (regno
== PR_REG
)
10593 return mode
== SImode
;
10595 if (regno
== FPSCR_REG
)
10596 return mode
== SImode
;
10601 /* Implement TARGET_MODES_TIEABLE_P.
10603 If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
10604 and MODE2, for any hard reg, then this must be false for correct output.
10605 That's the case for xd registers: we don't hold SFmode values in
10606 them, so we can't tie an SFmode pseudos with one in another
10607 floating-point mode. */
10610 sh_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
10612 return (mode1
== mode2
10613 || (GET_MODE_CLASS (mode1
) == GET_MODE_CLASS (mode2
)
10614 && (mode1
!= SFmode
&& mode2
!= SFmode
)));
10617 /* Specify the modes required to caller save a given hard regno.
10618 choose_hard_reg_mode chooses mode based on TARGET_HARD_REGNO_MODE_OK
10619 and returns ?Imode for float regs when sh_hard_regno_mode_ok
10620 permits integer modes on them. That makes LRA's split process
10621 unhappy. See PR55212.
10624 sh_hard_regno_caller_save_mode (unsigned int regno
, unsigned int nregs
,
10627 if (FP_REGISTER_P (regno
)
10630 || ((mode
== DFmode
|| mode
== DCmode
)
10631 && ((regno
- FIRST_FP_REG
) & 1) == 0)))
10634 return choose_hard_reg_mode (regno
, nregs
, false);
10637 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10639 sh_can_change_mode_class (machine_mode from
, machine_mode to
,
10640 reg_class_t rclass
)
10642 /* We want to enable the use of SUBREGs as a means to
10643 VEC_SELECT a single element of a vector. */
10645 /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
10646 This can be problematic when SFmode vector subregs need to be accessed
10647 on the stack with displacement addressing, as it happens with -O0.
10648 Thus we disallow the mode change for -O0. */
10649 if (to
== SFmode
&& VECTOR_MODE_P (from
) && GET_MODE_INNER (from
) == SFmode
)
10650 return optimize
? !reg_classes_intersect_p (GENERAL_REGS
, rclass
) : true;
10652 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
10654 if (TARGET_LITTLE_ENDIAN
)
10656 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
10657 return !reg_classes_intersect_p (DF_REGS
, rclass
);
10661 if (GET_MODE_SIZE (from
) < 8)
10662 return !reg_classes_intersect_p (DF_REGS
, rclass
);
10668 /* Return true if registers in machine mode MODE will likely be
10669 allocated to registers in small register classes. */
10671 sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED
)
10676 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10677 that label is used. */
10679 sh_mark_label (rtx address
, int nuses
)
10681 if (GOTOFF_P (address
))
10683 /* Extract the label or symbol. */
10684 address
= XEXP (address
, 0);
10685 if (GET_CODE (address
) == PLUS
)
10686 address
= XEXP (address
, 0);
10687 address
= XVECEXP (address
, 0, 0);
10689 if (GET_CODE (address
) == LABEL_REF
10690 && LABEL_P (XEXP (address
, 0)))
10691 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
10694 /* Compute extra cost of moving data between one register class
10697 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10698 uses this information. Hence, the general register <-> floating point
10699 register information here is not used for SFmode. */
10701 sh_register_move_cost (machine_mode mode
,
10702 reg_class_t srcclass
, reg_class_t dstclass
)
10704 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
10707 if (dstclass
== MAC_REGS
&& srcclass
== MAC_REGS
)
10710 if (mode
== SImode
&& TARGET_FMOVD
10711 && REGCLASS_HAS_FP_REG (srcclass
)
10712 && REGCLASS_HAS_FP_REG (dstclass
))
10715 if (REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== T_REGS
)
10716 return ((TARGET_HARD_SH4
&& !optimize_size
) ? 10 : 7);
10718 if ((REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== MAC_REGS
)
10719 || (dstclass
== MAC_REGS
&& REGCLASS_HAS_FP_REG (srcclass
)))
10722 if ((REGCLASS_HAS_FP_REG (dstclass
)
10723 && REGCLASS_HAS_GENERAL_REG (srcclass
))
10724 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
10725 && REGCLASS_HAS_FP_REG (srcclass
)))
10727 /* Discourage trying to use fp regs for a pointer. This also
10728 discourages fp regs with SImode because Pmode is an alias
10729 of SImode on this target. See PR target/48596. */
10730 int addend
= (mode
== Pmode
) ? 40 : 0;
10732 return ((TARGET_FMOVD
? 8 : 12) + addend
)
10733 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
10736 if ((dstclass
== FPUL_REGS
10737 && REGCLASS_HAS_GENERAL_REG (srcclass
))
10738 || (srcclass
== FPUL_REGS
10739 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
10742 if ((dstclass
== FPUL_REGS
10743 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
10744 || (srcclass
== FPUL_REGS
10745 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
10748 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
10749 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
10753 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
10754 && ! REGCLASS_HAS_GENERAL_REG (dstclass
))
10755 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
10757 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
10761 emit_load_ptr (rtx reg
, rtx addr
)
10763 rtx mem
= gen_const_mem (ptr_mode
, addr
);
10765 if (Pmode
!= ptr_mode
)
10766 mem
= gen_rtx_SIGN_EXTEND (Pmode
, mem
);
10767 return emit_move_insn (reg
, mem
);
10771 sh_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
10772 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10775 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
10776 CUMULATIVE_ARGS cum
;
10777 int structure_value_byref
= 0;
10778 rtx this_rtx
, this_value
, sibcall
, funexp
;
10780 tree funtype
= TREE_TYPE (function
);
10781 int simple_add
= CONST_OK_FOR_ADD (delta
);
10783 rtx scratch0
, scratch1
, scratch2
;
10785 reload_completed
= 1;
10786 epilogue_completed
= 1;
10787 crtl
->uses_only_leaf_regs
= 1;
10789 emit_note (NOTE_INSN_PROLOGUE_END
);
10791 /* Find the "this" pointer. We have such a wide range of ABIs for the
10792 SH that it's best to do this completely machine independently.
10793 "this" is passed as first argument, unless a structure return pointer
10794 comes first, in which case "this" comes second. */
10795 INIT_CUMULATIVE_ARGS (cum
, funtype
, NULL_RTX
, 0, 1);
10796 #ifndef PCC_STATIC_STRUCT_RETURN
10797 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10798 structure_value_byref
= 1;
10799 #endif /* not PCC_STATIC_STRUCT_RETURN */
10800 if (structure_value_byref
&& sh_struct_value_rtx (function
, 0) == 0)
10802 tree ptype
= build_pointer_type (TREE_TYPE (funtype
));
10804 function_arg_info
ptr_arg (ptype
, Pmode
, /*named=*/true);
10805 sh_function_arg_advance (pack_cumulative_args (&cum
), ptr_arg
);
10807 function_arg_info
ptr_arg (ptr_type_node
, Pmode
, /*named=*/true);
10808 this_rtx
= sh_function_arg (pack_cumulative_args (&cum
), ptr_arg
);
10810 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10811 static chain pointer (even if you can't have nested virtual functions
10812 right now, someone might implement them sometime), and the rest of the
10813 registers are used for argument passing, are callee-saved, or reserved. */
10814 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10815 -ffixed-reg has been used. */
10816 if (! call_used_regs
[0] || fixed_regs
[0])
10817 error ("r0 needs to be available as a call-clobbered register");
10818 scratch0
= scratch1
= scratch2
= gen_rtx_REG (Pmode
, 0);
10821 if (call_used_regs
[1] && ! fixed_regs
[1])
10822 scratch1
= gen_rtx_REG (ptr_mode
, 1);
10823 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10824 pointing where to return struct values. */
10825 if (call_used_regs
[3] && ! fixed_regs
[3])
10826 scratch2
= gen_rtx_REG (Pmode
, 3);
10829 this_value
= plus_constant (Pmode
, this_rtx
, delta
);
10831 && (simple_add
|| scratch0
!= scratch1
)
10832 && strict_memory_address_p (ptr_mode
, this_value
))
10834 emit_load_ptr (scratch0
, this_value
);
10839 ; /* Do nothing. */
10840 else if (simple_add
)
10841 emit_move_insn (this_rtx
, this_value
);
10844 emit_move_insn (scratch1
, GEN_INT (delta
));
10845 emit_insn (gen_add2_insn (this_rtx
, scratch1
));
10853 emit_load_ptr (scratch0
, this_rtx
);
10855 offset_addr
= plus_constant (Pmode
, scratch0
, vcall_offset
);
10856 if (strict_memory_address_p (ptr_mode
, offset_addr
))
10857 ; /* Do nothing. */
10858 else if (scratch0
!= scratch1
)
10860 /* scratch0 != scratch1, and we have indexed loads. Get better
10861 schedule by loading the offset into r1 and using an indexed
10862 load - then the load of r1 can issue before the load from
10863 (this_rtx + delta) finishes. */
10864 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
10865 offset_addr
= gen_rtx_PLUS (Pmode
, scratch0
, scratch1
);
10867 else if (CONST_OK_FOR_ADD (vcall_offset
))
10869 emit_insn (gen_add2_insn (scratch0
, GEN_INT (vcall_offset
)));
10870 offset_addr
= scratch0
;
10873 gcc_unreachable (); /* FIXME */
10874 emit_load_ptr (scratch0
, offset_addr
);
10876 if (Pmode
!= ptr_mode
)
10877 scratch0
= gen_rtx_TRUNCATE (ptr_mode
, scratch0
);
10878 emit_insn (gen_add2_insn (this_rtx
, scratch0
));
10881 /* Generate a tail call to the target function. */
10882 if (! TREE_USED (function
))
10884 assemble_external (function
);
10885 TREE_USED (function
) = 1;
10887 funexp
= XEXP (DECL_RTL (function
), 0);
10888 /* If the function is overridden, so is the thunk, hence we don't
10889 need GOT addressing even if this is a public symbol. */
10891 if (TARGET_SH1
&& ! flag_weak
)
10892 sibcall
= gen_sibcalli_thunk (funexp
, const0_rtx
);
10895 if (TARGET_SH2
&& flag_pic
)
10899 sibcall
= gen_sibcall_pcrel_fdpic (funexp
, const0_rtx
);
10900 XEXP (XVECEXP (sibcall
, 0, 3), 0) = scratch2
;
10904 sibcall
= gen_sibcall_pcrel (funexp
, const0_rtx
);
10905 XEXP (XVECEXP (sibcall
, 0, 2), 0) = scratch2
;
10910 emit_move_insn (scratch2
, funexp
);
10911 funexp
= gen_rtx_MEM (FUNCTION_MODE
, scratch2
);
10912 sibcall
= gen_sibcall (funexp
, const0_rtx
, NULL_RTX
);
10914 sibcall
= emit_call_insn (sibcall
);
10915 SIBLING_CALL_P (sibcall
) = 1;
10916 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall
), this_rtx
);
10919 /* Run just enough of rest_of_compilation to do scheduling and get
10920 the insns emitted. */
10922 insns
= get_insns ();
10928 split_all_insns_noflow ();
10932 shorten_branches (insns
);
10933 assemble_start_function (thunk_fndecl
, fnname
);
10934 final_start_function (insns
, file
, 1);
10935 final (insns
, file
, 1);
10936 final_end_function ();
10937 assemble_end_function (thunk_fndecl
, fnname
);
10939 reload_completed
= 0;
10940 epilogue_completed
= 0;
10943 /* Return an RTX pair for the address and call site label of a function
10944 NAME of kind KIND, placing the result in TARGET if not NULL. For
10945 SFUNC_STATIC, if FDPIC, the LAB member of result will be set to
10946 (const_int 0) if jsr should be used, or a label_ref if bsrf should
10947 be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the
10948 address of the function itself, not a function descriptor, so they
10949 can only be used with functions not using the FDPIC register that
10950 are known to be called directory without a PLT entry. */
10952 function_symbol_result
10953 function_symbol (rtx target
, const char *name
, sh_function_kind kind
)
10955 /* If this is not an ordinary function, the name usually comes from a
10956 string literal or an sprintf buffer. Make sure we use the same
10957 string consistently, so that cse will be able to unify address loads. */
10958 if (kind
!= FUNCTION_ORDINARY
)
10959 name
= IDENTIFIER_POINTER (get_identifier (name
));
10960 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
10961 rtx lab
= const0_rtx
;
10962 SYMBOL_REF_FLAGS (sym
) = SYMBOL_FLAG_FUNCTION
;
10966 case FUNCTION_ORDINARY
:
10970 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
10972 emit_insn (gen_symGOT2reg (reg
, sym
));
10978 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
10982 /* We use PC-relative calls, since GOTOFF can only refer
10983 to writable data. This works along with sh_sfunc_call. */
10984 lab
= PATTERN (gen_call_site ());
10985 emit_insn (gen_sym_label2reg (reg
, sym
, lab
));
10989 /* ??? To allow cse to work, we use GOTOFF relocations.
10990 we could add combiner patterns to transform this into
10991 straight pc-relative calls with sym2PIC / bsrf when
10992 label load and function call are still 1:1 and in the
10993 same basic block during combine. */
10994 emit_insn (gen_symGOTOFF2reg (reg
, sym
));
11001 if (target
&& sym
!= target
)
11003 emit_move_insn (target
, sym
);
11004 return function_symbol_result (target
, lab
);
11006 return function_symbol_result (sym
, lab
);
11009 /* Find the number of the first general purpose register in S that
11012 scavenge_reg (HARD_REG_SET
*s
)
11014 for (int r
= FIRST_GENERAL_REG
; r
<= LAST_GENERAL_REG
; r
++)
11015 if (TEST_HARD_REG_BIT (*s
, r
))
11021 sh_get_pr_initial_val (void)
11023 /* If we haven't finished rtl generation, there might be a nonlocal label
11024 that we haven't seen yet.
11025 ??? get_hard_reg_initial_val fails if it is called after register
11026 allocation has started, unless it has been called before for the
11027 same register. And even then, we end in trouble if we didn't use
11028 the register in the same basic block before. So call
11029 get_hard_reg_initial_val now and wrap it in an unspec if we might
11030 need to replace it. */
11031 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11032 combine can put the pseudo returned by get_hard_reg_initial_val into
11033 instructions that need a general purpose registers, which will fail to
11034 be recognized when the pseudo becomes allocated to PR. */
11035 rtx val
= get_hard_reg_initial_val (Pmode
, PR_REG
);
11036 return gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_RA
);
11040 sh_expand_t_scc (rtx operands
[])
11042 enum rtx_code code
= GET_CODE (operands
[1]);
11043 rtx target
= operands
[0];
11044 rtx op0
= operands
[2];
11045 rtx op1
= operands
[3];
11046 rtx result
= target
;
11048 if (!REG_P (op0
) || REGNO (op0
) != T_REG
11049 || !CONST_INT_P (op1
))
11051 if (!REG_P (result
))
11052 result
= gen_reg_rtx (SImode
);
11053 HOST_WIDE_INT val
= INTVAL (op1
);
11054 if ((code
== EQ
&& val
== 1) || (code
== NE
&& val
== 0))
11055 emit_insn (gen_movt (result
, get_t_reg_rtx ()));
11056 else if ((code
== EQ
&& val
== 0) || (code
== NE
&& val
== 1))
11057 emit_insn (gen_movnegt (result
, get_t_reg_rtx ()));
11058 else if (code
== EQ
|| code
== NE
)
11059 emit_insn (gen_move_insn (result
, GEN_INT (code
== NE
)));
11062 if (result
!= target
)
11063 emit_move_insn (target
, result
);
11067 /* INSN is an sfunc; return the rtx that describes the address used. */
11069 extract_sfunc_addr (rtx insn
)
11071 rtx pattern
= PATTERN (insn
);
11072 const int len
= XVECLEN (pattern
, 0);
11073 for (int i
= 0; i
< len
; i
++)
11075 rtx part
= XVECEXP (pattern
, 0, i
);
11076 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == Pmode
11077 && GENERAL_REGISTER_P (true_regnum (XEXP (part
, 0))))
11078 return XEXP (part
, 0);
11080 gcc_assert (GET_CODE (XVECEXP (pattern
, 0, 0)) == UNSPEC_VOLATILE
);
11081 return XVECEXP (XVECEXP (pattern
, 0, 0), 0, 1);
11084 /* Verify that the register in use_sfunc_addr still agrees with the address
11085 used in the sfunc. This prevents fill_slots_from_thread from changing
11087 INSN is the use_sfunc_addr instruction, and REG is the register it
11090 check_use_sfunc_addr (rtx_insn
*insn
, rtx reg
)
11092 /* Search for the sfunc. It should really come right after INSN. */
11093 while ((insn
= NEXT_INSN (insn
)))
11095 if (LABEL_P (insn
) || JUMP_P (insn
))
11097 if (! INSN_P (insn
))
11100 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
11101 insn
= seq
->insn (0);
11102 if (GET_CODE (PATTERN (insn
)) != PARALLEL
11103 || get_attr_type (insn
) != TYPE_SFUNC
)
11105 return rtx_equal_p (extract_sfunc_addr (insn
), reg
);
11107 gcc_unreachable ();
11110 /* This function returns a constant rtx that represents 2**15 / pi in
11111 SFmode. It's used to scale a fixed-point signed 16.16-bit fraction
11112 of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */
11113 static GTY(()) rtx sh_fsca_sf2int_rtx
;
11116 sh_fsca_sf2int (void)
11118 if (! sh_fsca_sf2int_rtx
)
11120 REAL_VALUE_TYPE rv
;
11122 real_from_string (&rv
, "10430.378350470453");
11123 sh_fsca_sf2int_rtx
= const_double_from_real_value (rv
, SFmode
);
11126 return sh_fsca_sf2int_rtx
;
11129 /* This function returns a constant rtx that represents pi / 2**15 in
11130 SFmode. It's used to scale SFmode angles, in radians, to a
11131 fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi
11132 maps to 0x10000. */
11133 static GTY(()) rtx sh_fsca_int2sf_rtx
;
11136 sh_fsca_int2sf (void)
11138 if (! sh_fsca_int2sf_rtx
)
11140 REAL_VALUE_TYPE rv
;
11142 real_from_string (&rv
, "9.587379924285257e-5");
11143 sh_fsca_int2sf_rtx
= const_double_from_real_value (rv
, SFmode
);
11146 return sh_fsca_int2sf_rtx
;
11149 /* Initialize the CUMULATIVE_ARGS structure. */
11151 sh_init_cumulative_args (CUMULATIVE_ARGS
* pcum
,
11153 rtx libname ATTRIBUTE_UNUSED
,
11155 signed int n_named_args
,
11158 pcum
->arg_count
[(int) SH_ARG_FLOAT
] = 0;
11159 pcum
->free_single_fp_reg
= 0;
11160 pcum
->outgoing
= n_named_args
!= -1;
11162 /* FIXME: Should we check TARGET_HITACHI here ??? */
11163 pcum
->renesas_abi
= sh_attr_renesas_p (fntype
);
11167 pcum
->force_mem
= ((TARGET_HITACHI
|| pcum
->renesas_abi
)
11168 && aggregate_value_p (TREE_TYPE (fntype
), fndecl
));
11169 pcum
->prototype_p
= prototype_p (fntype
);
11170 pcum
->arg_count
[(int) SH_ARG_INT
] = false;
11174 pcum
->arg_count
[(int) SH_ARG_INT
] = 0;
11175 pcum
->prototype_p
= false;
11176 if (mode
!= VOIDmode
)
11178 /* If the default ABI is the Renesas ABI then all library
11179 calls must assume that the library will be using the
11180 Renesas ABI. So if the function would return its result
11181 in memory then we must force the address of this memory
11182 block onto the stack. Ideally we would like to call
11183 targetm.calls.return_in_memory() here but we do not have
11184 the TYPE or the FNDECL available so we synthesize the
11185 contents of that function as best we can. */
11187 (TARGET_DEFAULT
& MASK_HITACHI
)
11188 && (mode
== BLKmode
11189 || (GET_MODE_SIZE (mode
) > 4
11190 && !(mode
== DFmode
11191 && TARGET_FPU_DOUBLE
)));
11194 pcum
->force_mem
= false;
11199 sh_gen_truncate (machine_mode mode
, rtx x
, int need_sign_ext
)
11201 enum rtx_code code
= TRUNCATE
;
11203 if (GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
11205 rtx inner
= XEXP (x
, 0);
11206 machine_mode inner_mode
= GET_MODE (inner
);
11208 if (inner_mode
== mode
)
11210 else if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
11212 else if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
)
11213 && (! need_sign_ext
|| GET_CODE (x
) == SIGN_EXTEND
))
11215 code
= GET_CODE (x
);
11219 return gen_rtx_fmt_e (code
, mode
, x
);
11222 /* Load and store depend on the highpart of the address. However,
11223 set_attr_alternative does not give well-defined results before reload,
11224 so we must look at the rtl ourselves to see if any of the feeding
11225 registers is used in a memref.
11227 Return true iff INSN contains a MEM. */
11229 sh_contains_memref_p (rtx insn
)
11231 subrtx_iterator::array_type array
;
11232 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
11238 /* Return true iff INSN loads a banked register. */
11240 sh_loads_bankedreg_p (rtx insn
)
11242 if (GET_CODE (PATTERN (insn
)) == SET
)
11244 rtx op
= SET_DEST (PATTERN(insn
));
11245 if (REG_P (op
) && BANKED_REGISTER_P (REGNO (op
)))
11252 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11254 sh_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
11259 /* Implement TARGET_SECONDARY_RELOAD. */
11261 sh_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
11262 machine_mode mode
, secondary_reload_info
*sri
)
11264 enum reg_class rclass
= (enum reg_class
) rclass_i
;
11266 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
11267 && REG_P (XEXP (XEXP (x
, 0), 0))
11268 && REGNO (XEXP (XEXP (x
, 0), 0)) == GBR_REG
)
11269 return rclass
== R0_REGS
? NO_REGS
: R0_REGS
;
11271 if (MEM_P (x
) && REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == GBR_REG
)
11272 return rclass
== R0_REGS
? NO_REGS
: R0_REGS
;
11274 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
11279 if (REGCLASS_HAS_FP_REG (rclass
)
11280 && immediate_operand ((x
), mode
)
11281 && ! ((fp_zero_operand (x
) || fp_one_operand (x
)) && mode
== SFmode
))
11285 sri
->icode
= CODE_FOR_reload_insf__frn
;
11288 sri
->icode
= CODE_FOR_reload_indf__frn
;
11291 /* ??? If we knew that we are in the appropriate mode -
11292 single precision - we could use a reload pattern directly. */
11297 if (rclass
== FPUL_REGS
11298 && ((REG_P (x
) && (REGNO (x
) == MACL_REG
|| REGNO (x
) == MACH_REG
11299 || REGNO (x
) == T_REG
))
11300 || GET_CODE (x
) == PLUS
))
11301 return GENERAL_REGS
;
11302 if (rclass
== FPUL_REGS
&& immediate_operand (x
, mode
))
11304 if (satisfies_constraint_I08 (x
) || fp_zero_operand (x
))
11305 return GENERAL_REGS
;
11306 else if (mode
== SFmode
)
11308 sri
->icode
= CODE_FOR_reload_insi__i_fpul
;
11311 if (rclass
== FPSCR_REGS
11312 && ((REG_P (x
) && REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
11313 || (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
)))
11314 return GENERAL_REGS
;
11315 } /* end of input-only processing. */
11317 if (((REGCLASS_HAS_FP_REG (rclass
)
11319 && (GENERAL_OR_AP_REGISTER_P (REGNO (x
))
11320 || (FP_REGISTER_P (REGNO (x
)) && mode
== SImode
11321 && TARGET_FMOVD
))))
11322 || (REGCLASS_HAS_GENERAL_REG (rclass
)
11324 && FP_REGISTER_P (REGNO (x
))))
11325 && (mode
== SFmode
|| mode
== SImode
))
11327 if ((rclass
== FPUL_REGS
11328 || (REGCLASS_HAS_FP_REG (rclass
) && mode
== SImode
))
11331 && (REGNO (x
) >= FIRST_PSEUDO_REGISTER
11332 || REGNO (x
) == T_REG
11333 || system_reg_operand (x
, VOIDmode
)))))
11335 if (rclass
== FPUL_REGS
)
11336 return GENERAL_REGS
;
11337 return NO_REGS
; // LRA wants NO_REGS here, it used to be FPUL_REGS;
11340 if ((rclass
== MAC_REGS
|| rclass
== PR_REGS
)
11341 && REG_P (x
) && ! GENERAL_REGISTER_P (REGNO (x
))
11342 && rclass
!= REGNO_REG_CLASS (REGNO (x
)))
11343 return GENERAL_REGS
;
11345 /* If here fall back to loading FPUL register through general registers.
11346 This case can happen when movsi_ie insn is picked initially to
11347 load/store the FPUL register from/to another register, and then the
11348 other register is allocated on the stack. */
11349 if (rclass
== FPUL_REGS
&& true_regnum (x
) == -1)
11350 return GENERAL_REGS
;
11352 /* Force mov.b / mov.w displacement addressing insn to use R0 as
11354 On SH2A could also just leave it alone here, which would result in a
11355 4 byte move insn being generated instead. However, for this to work
11356 the insns must have the appropriate alternatives. */
11357 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
11358 && satisfies_constraint_Sdd (x
)
11359 && sh_disp_addr_displacement (x
)
11360 <= sh_max_mov_insn_displacement (mode
, false))
11363 /* When reload is trying to address a QImode or HImode subreg on the stack,
11364 force any subreg byte into R0_REGS, as this is going to become a
11365 displacement address.
11366 We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg
11367 is on the stack, the memref to it might already require a displacement
11368 and that has to be added to the final address. At this point we don't
11369 know the cumulative displacement so we assume the worst case. */
11370 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
11371 && GET_CODE (x
) == SUBREG
&& true_regnum (x
) == -1)
11377 /* Return true if SUBST can't safely replace its equivalent during RA. */
11379 sh_cannot_substitute_mem_equiv_p (rtx
)
11381 /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn
11382 uses R0 and may cause spill failure when R0 is already used.
11383 We have to return true for that case at least.
11384 Moreover SH has strong R0 parity and also have not enough numbers of
11385 the hard registers to make the equiv substitution win in the size
11386 and the speed on average working sets. The pseudos produced to
11387 hold the equiv values can't get good hard registers for bad cases
11388 and end up memory save/restore insns which make the code worse. */
11392 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
11394 sh_legitimize_address_displacement (rtx
*offset1
, rtx
*offset2
,
11395 poly_int64 orig_offset
,
11398 if ((TARGET_FPU_DOUBLE
&& mode
== DFmode
)
11399 || (TARGET_SH2E
&& mode
== SFmode
))
11402 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
, orig_offset
);
11403 if (adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
11405 *offset1
= adj
.offset_adjust
;
11406 *offset2
= adj
.mov_disp
;
11413 /* Return true if movsf insn should be splited with an additional
11416 sh_movsf_ie_ra_split_p (rtx op0
, rtx op1
, rtx op2
)
11419 if (rtx_equal_p (op0
, op1
))
11422 if (GET_CODE (op1
) == CONST_DOUBLE
11423 && ! satisfies_constraint_G (op1
)
11424 && ! satisfies_constraint_H (op1
)
11429 if (REG_P (op0
) && FP_REGISTER_P (REGNO (op0
))
11430 && REG_P (op1
) && GENERAL_REGISTER_P (REGNO (op1
))
11431 && REG_P (op2
) && (REGNO (op2
) == FPUL_REG
))
11434 if (REG_P (op1
) && FP_REGISTER_P (REGNO (op1
))
11435 && REG_P (op0
) && GENERAL_REGISTER_P (REGNO (op0
))
11436 && REG_P (op2
) && (REGNO (op2
) == FPUL_REG
))
11443 sh_conditional_register_usage (void)
11445 for (int regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
11446 if (! VALID_REGISTER_P (regno
))
11447 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
11448 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
11451 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
11452 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
11456 fixed_regs
[PIC_REG
] = 1;
11457 call_used_regs
[PIC_REG
] = 1;
11458 call_really_used_regs
[PIC_REG
] = 1;
11460 /* Renesas saves and restores mac registers on call. */
11461 if (TARGET_HITACHI
&& ! TARGET_NOMACSAVE
)
11463 call_really_used_regs
[MACH_REG
] = 0;
11464 call_really_used_regs
[MACL_REG
] = 0;
11467 for (int regno
= FIRST_GENERAL_REG
; regno
<= LAST_GENERAL_REG
; regno
++)
11468 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
11469 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
11471 call_really_used_regs
[FPSCR_MODES_REG
] = 0;
11472 call_really_used_regs
[FPSCR_STAT_REG
] = 0;
11475 /* Implement TARGET_LEGITIMATE_CONSTANT_P
11477 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
11479 sh_legitimate_constant_p (machine_mode mode
, rtx x
)
11481 if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
11484 split_const (x
, &base
, &offset
);
11486 if (GET_CODE (base
) == SYMBOL_REF
11487 && !offset_within_block_p (base
, INTVAL (offset
)))
11492 && (SYMBOLIC_CONST_P (x
)
11493 || (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
11494 && SYMBOLIC_CONST_P (XEXP (XEXP (x
, 0), 0)))))
11497 return GET_CODE (x
) != CONST_DOUBLE
11498 || mode
== DFmode
|| mode
== SFmode
11499 || mode
== DImode
|| GET_MODE (x
) == VOIDmode
;
11502 enum sh_divide_strategy_e sh_div_strategy
= SH_DIV_STRATEGY_DEFAULT
;
11505 sh_init_sync_libfuncs (void)
11507 init_sync_libfuncs (UNITS_PER_WORD
);
11510 /* Return true if it is appropriate to emit `ret' instructions in the
11511 body of a function. */
11513 sh_can_use_simple_return_p (void)
11515 if (! reload_completed
|| frame_pointer_needed
)
11518 /* Moving prologue around does't reduce the size. */
11519 if (optimize_function_for_size_p (cfun
))
11522 /* Finally, allow for pr save. */
11523 HARD_REG_SET live_regs_mask
;
11524 int d
= calc_live_regs (&live_regs_mask
);
11526 if (rounded_frame_size (d
) > 4)
11532 /*------------------------------------------------------------------------------
11533 Address mode optimization support code
11536 typedef HOST_WIDE_INT disp_t
;
11537 static const disp_t MIN_DISP
= HOST_WIDE_INT_MIN
;
11538 static const disp_t MAX_DISP
= HOST_WIDE_INT_MAX
;
11539 static const disp_t INVALID_DISP
= MAX_DISP
;
11541 /* A memory reference which is described by a base register and a
11543 class base_reg_disp
11546 base_reg_disp (rtx br
, disp_t d
);
11548 bool is_reg (void) const;
11549 bool is_disp (void) const;
11550 rtx
reg (void) const;
11551 disp_t
disp (void) const;
11559 base_reg_disp::base_reg_disp (rtx br
, disp_t d
)
11560 : reg_ (br
), disp_ (d
)
11565 base_reg_disp::is_reg (void) const
11567 return reg_
!= NULL_RTX
&& disp_
!= INVALID_DISP
;
11571 base_reg_disp::is_disp (void) const
11573 return reg_
== NULL_RTX
&& disp_
!= INVALID_DISP
;
11577 base_reg_disp::reg (void) const
11583 base_reg_disp::disp (void) const
11588 /* Find the base register and calculate the displacement for a given
11589 address rtx 'x'. */
11590 static base_reg_disp
11591 sh_find_base_reg_disp (rtx_insn
* insn
, rtx x
, disp_t disp
= 0,
11592 rtx base_reg
= NULL
)
11596 if (REGNO (x
) == GBR_REG
)
11597 return base_reg_disp (x
, disp
);
11599 /* We've reached a hard-reg. This is probably the point where
11600 function args are copied to pseudos. Do not go any further and
11601 stick to the pseudo. If the original mem addr was in a hard reg
11602 from the beginning, it will become the base reg. */
11603 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
11604 return base_reg_disp (base_reg
!= NULL
? base_reg
: x
, disp
);
11606 /* Find the def of the reg and trace it. If there are more than one
11607 defs and they are not the same, assume it's not safe to proceed. */
11608 rtx_insn
* last_i
= NULL
;
11609 rtx last_set
= NULL
;
11610 for (df_ref d
= DF_REG_DEF_CHAIN (REGNO (x
)); d
!= NULL
;
11611 d
= DF_REF_NEXT_REG (d
))
11613 rtx set
= const_cast<rtx
> (set_of (x
, DF_REF_INSN (d
)));
11615 /* Accept multiple defs, as long as they are equal. */
11616 if (last_set
== NULL
|| rtx_equal_p (last_set
, set
))
11618 last_i
= DF_REF_INSN (d
);
11629 if (last_set
!= NULL
&& last_i
!= NULL
)
11630 return sh_find_base_reg_disp (last_i
, XEXP (last_set
, 1), disp
,
11631 XEXP (last_set
, 0));
11633 /* When here, no previous insn was found that sets the reg.
11634 The input reg is already the base reg. */
11635 return base_reg_disp (x
, disp
);
11638 else if (GET_CODE (x
) == PLUS
)
11640 base_reg_disp left_val
= sh_find_base_reg_disp (insn
, XEXP (x
, 0));
11641 base_reg_disp right_val
= sh_find_base_reg_disp (insn
, XEXP (x
, 1));
11643 /* Either left or right val must be a reg.
11644 We don't handle the case of 'reg + reg' here. */
11645 if (left_val
.is_reg () && right_val
.is_disp ())
11646 return base_reg_disp (left_val
.reg (), left_val
.disp ()
11647 + right_val
.disp () + disp
);
11648 else if (right_val
.is_reg () && left_val
.is_disp ())
11649 return base_reg_disp (right_val
.reg (), right_val
.disp ()
11650 + left_val
.disp () + disp
);
11652 return base_reg_disp (base_reg
, disp
);
11655 else if (CONST_INT_P (x
))
11656 return base_reg_disp (NULL
, disp
+ INTVAL (x
));
11658 /* Didn't find anything useful. */
11659 return base_reg_disp (base_reg
, disp
);
11662 /* Given an insn and a memory operand, try to find an equivalent GBR
11663 based memory address and return the corresponding new memory address.
11664 Return NULL_RTX if not found. */
11666 sh_find_equiv_gbr_addr (rtx_insn
* insn
, rtx mem
)
11668 if (!MEM_P (mem
) || gbr_address_mem (mem
, GET_MODE (mem
)))
11671 /* Leave post/pre inc/dec or any other side effect addresses alone. */
11672 if (side_effects_p (XEXP (mem
, 0)))
11675 /* When not optimizing there might be no dataflow available. */
11679 base_reg_disp gbr_disp
= sh_find_base_reg_disp (insn
, XEXP (mem
, 0));
11681 if (gbr_disp
.is_reg () && REGNO (gbr_disp
.reg ()) == GBR_REG
)
11683 /* If GBR is marked as call clobbered we bail out if we see a call.
11684 FIXME: Actually should check if this mem refers to the gbr value
11685 before or after the call. If there is a store_gbr preceeding this
11686 mem, it's safe to use GBR for this mem.
11688 If GBR is not marked as call clobbered, but there is some other
11689 def than a call, it's probably a load_gbr upon which we also
11690 bail out to be on the safe side.
11691 FIXME: Should check if we have a use-after-def case, such as
11692 the call case above. */
11693 for (df_ref d
= DF_REG_DEF_CHAIN (GBR_REG
); d
!= NULL
;
11694 d
= DF_REF_NEXT_REG (d
))
11696 if (CALL_P (DF_REF_INSN (d
)))
11698 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, GBR_REG
))
11707 rtx disp
= GEN_INT (gbr_disp
.disp ());
11708 if (gbr_displacement (disp
, GET_MODE (mem
)))
11709 return gen_rtx_PLUS (SImode
, gen_rtx_REG (SImode
, GBR_REG
), disp
);
11715 /*------------------------------------------------------------------------------
11716 Manual insn combine support code.
11719 /* Return true if the specified insn contains any UNSPECs or
11720 UNSPEC_VOLATILEs. */
11722 sh_unspec_insn_p (rtx x
)
11724 subrtx_iterator::array_type array
;
11725 FOR_EACH_SUBRTX (i
, array
, x
, ALL
)
11727 && (GET_CODE (*i
) == UNSPEC
|| GET_CODE (*i
) == UNSPEC_VOLATILE
))
11733 /* Return true if the register operands of the specified insn are modified
11734 between the specified from and to insns (exclusive of those two). */
11736 sh_insn_operands_modified_between_p (rtx_insn
* operands_insn
,
11737 const rtx_insn
* from
,
11738 const rtx_insn
* to
)
11740 /* FIXME: Return true for multiple sets for now. */
11741 rtx s
= single_set (operands_insn
);
11745 subrtx_iterator::array_type array
;
11746 FOR_EACH_SUBRTX (i
, array
, SET_SRC (s
), ALL
)
11748 ((REG_P (*i
) || SUBREG_P (*i
)) && reg_set_between_p (*i
, from
, to
)))
11754 /* Given an insn, determine whether it's a 'nott' insn, i.e. an insn that
11755 negates the T bit and stores the result in the T bit. */
11757 sh_is_nott_insn (const rtx_insn
* i
)
11759 return i
!= NULL
&& GET_CODE (PATTERN (i
)) == SET
11760 && t_reg_operand (XEXP (PATTERN (i
), 0), VOIDmode
)
11761 && negt_reg_operand (XEXP (PATTERN (i
), 1), VOIDmode
);
11765 sh_movt_set_dest (const rtx_insn
* i
)
11767 return i
== NULL
? NULL
: sh_movt_set_dest (PATTERN (i
));
11771 sh_movt_set_dest (const_rtx pat
)
11773 return GET_CODE (pat
) == SET
11774 && arith_reg_dest (XEXP (pat
, 0), SImode
)
11775 && t_reg_operand (XEXP (pat
, 1), VOIDmode
) ? XEXP (pat
, 0) : NULL
;
11778 /* Given an insn, check whether it's a 'movrt' kind of insn, i.e. an insn
11779 that stores the negated T bit in a register, and return the destination
11780 register rtx, or null. */
11782 sh_movrt_set_dest (const rtx_insn
* i
)
11784 return i
== NULL
? NULL
: sh_movrt_set_dest (PATTERN (i
));
11788 sh_movrt_set_dest (const_rtx pat
)
11790 /* The negc movrt replacement is inside a parallel. */
11791 if (GET_CODE (pat
) == PARALLEL
)
11792 pat
= XVECEXP (pat
, 0, 0);
11794 return GET_CODE (pat
) == SET
11795 && arith_reg_dest (XEXP (pat
, 0), SImode
)
11796 && negt_reg_operand (XEXP (pat
, 1), VOIDmode
) ? XEXP (pat
, 0) : NULL
;
11800 /* Given an insn and a reg number, tell whether the reg dies or is unused
11803 sh_reg_dead_or_unused_after_insn (const rtx_insn
* i
, int regno
)
11805 return find_regno_note (i
, REG_DEAD
, regno
) != NULL
11806 || find_regno_note (i
, REG_UNUSED
, regno
) != NULL
;
11809 /* Given an insn and a reg number, remove reg dead or reg unused notes to
11810 mark it as being used after the insn. */
11812 sh_remove_reg_dead_or_unused_notes (rtx_insn
* i
, int regno
)
11814 if (rtx n
= find_regno_note (i
, REG_DEAD
, regno
))
11815 remove_note (i
, n
);
11816 if (rtx n
= find_regno_note (i
, REG_UNUSED
, regno
))
11817 remove_note (i
, n
);
11820 /* Given an insn check if it contains any post/pre inc/dec mem operands and
11821 add the REG_INC notes accordingly.
11822 FIXME: This function is very similar to lra.c (add_auto_inc_notes).
11823 FIXME: This function is currently used by peephole2 patterns because
11824 the peephole2 pass does not preserve REG_INC notes. If the notes
11825 are dropped the following passes will do wrong things. */
11827 sh_check_add_incdec_notes (rtx_insn
* i
)
11829 struct for_each_inc_dec_clb
11831 static int func (rtx mem ATTRIBUTE_UNUSED
, rtx op ATTRIBUTE_UNUSED
,
11832 rtx dest
, rtx src ATTRIBUTE_UNUSED
,
11833 rtx srcoff ATTRIBUTE_UNUSED
, void* arg
)
11835 gcc_assert (REG_P (dest
));
11837 rtx_insn
* i
= (rtx_insn
*)arg
;
11838 if (find_regno_note (i
, REG_INC
, REGNO (dest
)) == NULL
)
11839 add_reg_note (i
, REG_INC
, dest
);
11845 for_each_inc_dec (PATTERN (i
), for_each_inc_dec_clb::func
, i
);
11849 /* Given a move insn destiation and a source, make sure that the move source
11850 operand is not a post-inc mem load with the same address reg as the
11851 destination. Returns the modified source operand with the post-inc removed
11854 sh_remove_overlapping_post_inc (rtx dst
, rtx src
)
11859 rtx addr
= XEXP (src
, 0);
11861 if (GET_CODE (addr
) == POST_INC
11862 && reg_overlap_mentioned_p (XEXP (addr
, 0), dst
))
11863 return replace_equiv_address (src
, XEXP (addr
, 0));
11865 gcc_assert (GET_CODE (addr
) != POST_MODIFY
);
11869 /* Emit a move insn that is safe to be used in peephole patterns. */
11871 sh_peephole_emit_move_insn (rtx dst
, rtx src
)
11873 return sh_check_add_incdec_notes (
11874 emit_move_insn (dst
, sh_remove_overlapping_post_inc (dst
, src
)));
11877 /* Given an op rtx and an insn, try to find out whether the result of the
11878 specified op consists only of logical operations on T bit stores. */
11880 sh_is_logical_t_store_expr (rtx op
, rtx_insn
* insn
)
11882 if (!logical_operator (op
, SImode
))
11885 rtx ops
[2] = { XEXP (op
, 0), XEXP (op
, 1) };
11886 int op_is_t_count
= 0;
11888 for (int i
= 0; i
< 2; ++i
)
11890 if (t_reg_operand (ops
[i
], VOIDmode
)
11891 || negt_reg_operand (ops
[i
], VOIDmode
))
11896 set_of_reg op_set
= sh_find_set_of_reg
11897 (ops
[i
], insn
, prev_nonnote_nondebug_insn_bb
);
11898 if (op_set
.set_src
== NULL_RTX
)
11901 if (t_reg_operand (op_set
.set_src
, VOIDmode
)
11902 || negt_reg_operand (op_set
.set_src
, VOIDmode
)
11903 || sh_is_logical_t_store_expr (op_set
.set_src
, op_set
.insn
))
11908 return op_is_t_count
== 2;
11911 /* Given the operand that is extended in a sign/zero extend insn, and the
11912 insn, try to figure out whether the sign/zero extension can be replaced
11913 by a simple reg-reg copy. If so, the replacement reg rtx is returned,
11914 NULL_RTX otherwise. */
11916 sh_try_omit_signzero_extend (rtx extended_op
, rtx_insn
* insn
)
11918 if (REG_P (extended_op
))
11919 extended_op
= extended_op
;
11920 else if (GET_CODE (extended_op
) == SUBREG
&& REG_P (SUBREG_REG (extended_op
)))
11921 extended_op
= SUBREG_REG (extended_op
);
11925 /* Reg moves must be of the same mode. */
11926 if (GET_MODE (extended_op
) != SImode
)
11929 set_of_reg s
= sh_find_set_of_reg (extended_op
, insn
,
11930 prev_nonnote_nondebug_insn_bb
);
11931 if (s
.set_src
== NULL_RTX
)
11934 if (t_reg_operand (s
.set_src
, VOIDmode
)
11935 || negt_reg_operand (s
.set_src
, VOIDmode
))
11936 return extended_op
;
11938 /* If the zero extended reg was formed by a logical operation, check the
11939 operands of the logical operation. If both originated from T bit
11940 stores the zero extension can be eliminated. */
11941 else if (sh_is_logical_t_store_expr (s
.set_src
, s
.insn
))
11942 return extended_op
;
11947 /* Given the current insn, which is assumed to be a movrt_negc insn, try to
11948 figure out whether it should be converted into a movt-xor sequence in
11949 the movrt_negc splitter.
11950 Returns true if insns have been modified and the splitter has succeeded. */
11952 sh_split_movrt_negc_to_movt_xor (rtx_insn
* curr_insn
, rtx operands
[])
11954 /* In cases such as
11959 we can replace the T bit clobbering negc with a movt-xor sequence and
11960 eliminate the redundant comparison.
11961 Because the xor insn depends on register allocation results, allow this
11962 only before reload. */
11963 if (!can_create_pseudo_p ())
11966 set_of_reg t_before_negc
= sh_find_set_of_reg
11967 (get_t_reg_rtx (), curr_insn
, prev_nonnote_nondebug_insn_bb
);
11968 set_of_reg t_after_negc
= sh_find_set_of_reg
11969 (get_t_reg_rtx (), curr_insn
, next_nonnote_nondebug_insn_bb
);
11971 if (t_before_negc
.set_rtx
!= NULL_RTX
&& t_after_negc
.set_rtx
!= NULL_RTX
11972 && rtx_equal_p (t_before_negc
.set_rtx
, t_after_negc
.set_rtx
)
11973 && !reg_used_between_p (get_t_reg_rtx (), curr_insn
, t_after_negc
.insn
)
11974 && !sh_insn_operands_modified_between_p (t_before_negc
.insn
,
11975 t_before_negc
.insn
,
11977 && !modified_between_p (get_t_reg_rtx (), curr_insn
, t_after_negc
.insn
)
11978 && !sh_unspec_insn_p (t_after_negc
.insn
)
11979 && !volatile_insn_p (PATTERN (t_after_negc
.insn
))
11980 && !side_effects_p (PATTERN (t_after_negc
.insn
))
11981 && !may_trap_or_fault_p (PATTERN (t_after_negc
.insn
)))
11983 emit_insn (gen_movrt_xor (operands
[0], get_t_reg_rtx ()));
11984 set_insn_deleted (t_after_negc
.insn
);
11991 /* Given a reg and the current insn, see if the value of the reg originated
11992 from a sign or zero extension and return the discovered information. */
11993 sh_extending_set_of_reg
11994 sh_find_extending_set_of_reg (rtx reg
, rtx_insn
* curr_insn
)
11997 return sh_extending_set_of_reg (curr_insn
);
11999 if (SUBREG_P (reg
))
12000 reg
= SUBREG_REG (reg
);
12003 return sh_extending_set_of_reg (curr_insn
);
12005 /* FIXME: Also search the predecessor basic blocks. It seems that checking
12006 only the adjacent predecessor blocks would cover most of the cases.
12007 Also try to look through the first extension that we hit. There are some
12008 cases, where a zero_extend is followed an (implicit) sign_extend, and it
12009 fails to see the sign_extend. */
12010 sh_extending_set_of_reg result
= sh_find_set_of_reg
12011 (reg
, curr_insn
, prev_nonnote_nondebug_insn_bb
, true);
12013 if (result
.set_src
!= NULL
)
12015 if (GET_CODE (result
.set_src
) == SIGN_EXTEND
12016 || GET_CODE (result
.set_src
) == ZERO_EXTEND
)
12019 fprintf (dump_file
, "sh_find_extending_set_of_reg: reg %d is "
12020 "explicitly sign/zero extended in insn %d\n",
12021 REGNO (reg
), INSN_UID (result
.insn
));
12022 result
.from_mode
= GET_MODE (XEXP (result
.set_src
, 0));
12023 result
.ext_code
= GET_CODE (result
.set_src
);
12025 else if (MEM_P (result
.set_src
)
12026 && (GET_MODE (result
.set_src
) == QImode
12027 || GET_MODE (result
.set_src
) == HImode
)
12028 && !sh_unspec_insn_p (result
.insn
))
12030 /* On SH QIHImode memory loads always sign extend. However, in
12031 some cases where it seems that the higher bits are not
12032 interesting, the loads will not be expanded as sign extending
12033 insns, but as QIHImode loads into QIHImode regs. We report that
12034 the reg has been sign extended by the mem load. When it is used
12035 as such, we must convert the mem load into a sign extending insn,
12036 see also sh_extending_set_of_reg::use_as_extended_reg. */
12038 fprintf (dump_file
, "sh_find_extending_set_of_reg: reg %d is "
12039 "implicitly sign extended in insn %d\n",
12040 REGNO (reg
), INSN_UID (result
.insn
));
12041 result
.from_mode
= GET_MODE (result
.set_src
);
12042 result
.ext_code
= SIGN_EXTEND
;
12049 /* Given a reg that is known to be sign or zero extended at some insn,
12050 take the appropriate measures so that the extended value can be used as
12051 a reg at the specified insn and return the resulting reg rtx. */
12053 sh_extending_set_of_reg::use_as_extended_reg (rtx_insn
* use_at_insn
) const
12055 gcc_assert (insn
!= NULL
&& set_src
!= NULL
&& set_rtx
!= NULL
);
12056 gcc_assert (ext_code
== SIGN_EXTEND
|| ext_code
== ZERO_EXTEND
);
12057 gcc_assert (from_mode
== QImode
|| from_mode
== HImode
);
12059 if (MEM_P (set_src
) && ext_code
== SIGN_EXTEND
)
12062 fprintf (dump_file
,
12063 "use_as_extended_reg: converting non-extending mem load in "
12064 "insn %d into sign-extending load\n", INSN_UID (insn
));
12066 rtx r
= gen_reg_rtx (SImode
);
12068 if (from_mode
== QImode
)
12069 i0
= emit_insn_after (gen_extendqisi2 (r
, set_src
), insn
);
12070 else if (from_mode
== HImode
)
12071 i0
= emit_insn_after (gen_extendhisi2 (r
, set_src
), insn
);
12073 gcc_unreachable ();
12076 gen_move_insn (XEXP (set_rtx
, 0),
12077 gen_lowpart (GET_MODE (set_src
), r
)), i0
);
12078 set_insn_deleted (insn
);
12083 rtx extension_dst
= XEXP (set_rtx
, 0);
12084 if (GET_MODE (extension_dst
) != SImode
)
12085 extension_dst
= simplify_gen_subreg (SImode
, extension_dst
,
12086 GET_MODE (extension_dst
), 0);
12087 if (modified_between_p (extension_dst
, insn
, use_at_insn
))
12090 fprintf (dump_file
,
12091 "use_as_extended_reg: dest reg %d of extending insn %d is "
12092 "modified, inserting a reg-reg copy\n",
12093 REGNO (extension_dst
), INSN_UID (insn
));
12095 rtx r
= gen_reg_rtx (SImode
);
12096 emit_insn_after (gen_move_insn (r
, extension_dst
), insn
);
12101 sh_remove_reg_dead_or_unused_notes (insn
, REGNO (extension_dst
));
12102 return extension_dst
;
12108 sh_extending_set_of_reg::can_use_as_unextended_reg (void) const
12110 if ((ext_code
== SIGN_EXTEND
|| ext_code
== ZERO_EXTEND
)
12111 && (from_mode
== QImode
|| from_mode
== HImode
)
12112 && set_src
!= NULL
)
12113 return arith_reg_operand (XEXP (set_src
, 0), from_mode
);
12119 sh_extending_set_of_reg::use_as_unextended_reg (rtx_insn
* use_at_insn
) const
12121 gcc_assert (can_use_as_unextended_reg ());
12123 rtx r
= XEXP (set_src
, 0);
12124 rtx r0
= simplify_gen_subreg (SImode
, r
, from_mode
, 0);
12126 if (modified_between_p (r
, insn
, use_at_insn
))
12128 rtx r1
= gen_reg_rtx (SImode
);
12129 emit_insn_after (gen_move_insn (r1
, r0
), insn
);
12134 sh_remove_reg_dead_or_unused_notes (insn
, SUBREG_P (r
)
12135 ? REGNO (SUBREG_REG (r
))
12141 /* Given the current insn, which is assumed to be the *tst<mode>_t_subregs insn,
12142 perform the necessary checks on the operands and split it accordingly. */
12144 sh_split_tst_subregs (rtx_insn
* curr_insn
, machine_mode subreg_mode
,
12145 int subreg_offset
, rtx operands
[])
12147 gcc_assert (subreg_mode
== QImode
|| subreg_mode
== HImode
);
12149 sh_extending_set_of_reg eop0
= sh_find_extending_set_of_reg (operands
[0],
12151 sh_extending_set_of_reg eop1
= sh_find_extending_set_of_reg (operands
[1],
12154 /* If one of the operands is known to be zero extended, that's already
12155 sufficient to mask out the unwanted high bits. */
12156 if (eop0
.ext_code
== ZERO_EXTEND
&& eop0
.from_mode
== subreg_mode
)
12158 emit_insn (gen_tstsi_t (eop0
.use_as_extended_reg (curr_insn
),
12162 if (eop1
.ext_code
== ZERO_EXTEND
&& eop1
.from_mode
== subreg_mode
)
12164 emit_insn (gen_tstsi_t (operands
[0],
12165 eop1
.use_as_extended_reg (curr_insn
)));
12169 /* None of the operands seem to be zero extended.
12170 If both are sign extended it's OK, too. */
12171 if (eop0
.ext_code
== SIGN_EXTEND
&& eop1
.ext_code
== SIGN_EXTEND
12172 && eop0
.from_mode
== subreg_mode
&& eop1
.from_mode
== subreg_mode
)
12174 emit_insn (gen_tstsi_t (eop0
.use_as_extended_reg (curr_insn
),
12175 eop1
.use_as_extended_reg (curr_insn
)));
12179 /* Otherwise we have to insert a zero extension on one of the operands to
12180 mask out the unwanted high bits.
12181 Prefer the operand that has no known extension. */
12182 if (eop0
.ext_code
!= UNKNOWN
&& eop1
.ext_code
== UNKNOWN
)
12183 std::swap (operands
[0], operands
[1]);
12185 rtx tmp0
= gen_reg_rtx (SImode
);
12186 rtx tmp1
= simplify_gen_subreg (subreg_mode
, operands
[0],
12187 GET_MODE (operands
[0]), subreg_offset
);
12188 emit_insn (subreg_mode
== QImode
12189 ? gen_zero_extendqisi2 (tmp0
, tmp1
)
12190 : gen_zero_extendhisi2 (tmp0
, tmp1
));
12191 emit_insn (gen_tstsi_t (tmp0
, operands
[1]));
12194 /* A helper class to increment/decrement a counter variable each time a
12195 function is entered/left. */
12196 class scope_counter
12199 scope_counter (int& counter
) : m_counter (counter
) { ++m_counter
; }
12201 ~scope_counter (void)
12204 gcc_assert (m_counter
>= 0);
12207 int count (void) const { return m_counter
; }
12213 /* Given an rtx x, determine whether the expression can be used to create
12214 an insn that calulates x and stores the result in the T bit.
12215 This is used by the 'treg_set_expr' predicate to construct insns sequences
12216 where T bit results are fed into other insns, such as addc, subc, negc
12219 FIXME: The patterns that expand 'treg_set_expr' operands tend to
12220 distinguish between 'positive' and 'negative' forms. For now this has to
12221 be done in the preparation code. We could also introduce
12222 'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write
12223 two different patterns for the 'postive' and 'negative' forms. However,
12224 the total amount of lines of code seems to be about the same and the
12225 '{pos|neg}_treg_set_expr' predicates would be more expensive, because the
12226 recog function would need to look inside the expression by temporarily
12228 static int sh_recog_treg_set_expr_reent_count
= 0;
12231 sh_recog_treg_set_expr (rtx op
, machine_mode mode
)
12233 scope_counter
recursion (sh_recog_treg_set_expr_reent_count
);
12235 /* Limit the recursion count to avoid nested expressions which we can't
12236 resolve to a single treg set insn. */
12237 if (recursion
.count () > 1)
12240 /* Early accept known possible operands before doing recog. */
12241 if (op
== const0_rtx
|| op
== const1_rtx
|| t_reg_operand (op
, mode
)
12242 || negt_reg_operand (op
, mode
))
12245 /* Early reject impossible operands before doing recog.
12246 There are some (set ((t) (subreg ...))) patterns, but we must be careful
12247 not to allow any invalid reg-reg or mem-reg moves, or else other passes
12248 such as lower-subreg will bail out. Some insns such as SH4A movua are
12249 done with UNSPEC, so must reject those, too, or else it would result
12250 in an invalid reg -> treg move. */
12251 if (CONST_INT_P (op
) || register_operand (op
, mode
)
12252 || memory_operand (op
, mode
) || sh_unspec_insn_p (op
))
12255 if (!can_create_pseudo_p ())
12258 /* expand_debug_locations may call this to compute rtx costs at
12259 very early stage. In that case, don't make new insns here to
12260 avoid codegen differences with -g. */
12261 if (currently_expanding_to_rtl
)
12264 /* We are going to invoke recog in a re-entrant way and thus
12265 have to capture its current state and restore it afterwards. */
12266 recog_data_d prev_recog_data
= recog_data
;
12268 rtx_insn
* i
= make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op
));
12269 SET_PREV_INSN (i
) = NULL
;
12270 SET_NEXT_INSN (i
) = NULL
;
12272 /* If the comparison op doesn't have a result mode, set it to SImode. */
12273 machine_mode prev_op_mode
= GET_MODE (op
);
12274 if (COMPARISON_P (op
) && prev_op_mode
== VOIDmode
)
12275 PUT_MODE (op
, SImode
);
12277 int result
= recog (PATTERN (i
), i
, 0);
12279 /* It seems there is no insn like that. Create a negated version and
12280 try again. If we hit a negated form, we'll allow that and append a
12281 nott sequence when splitting out the insns. Insns that do the split
12282 can then remove the trailing nott if they know how to deal with it. */
12283 if (result
< 0 && COMPARISON_P (op
))
12285 machine_mode cmp_mode
= GET_MODE (XEXP (op
, 0));
12286 if (cmp_mode
== VOIDmode
)
12287 cmp_mode
= GET_MODE (XEXP (op
, 1));
12289 rtx_code prev_code
= GET_CODE (op
);
12290 PUT_CODE (op
, reverse_condition (GET_CODE (op
)));
12291 result
= recog (PATTERN (i
), i
, 0);
12292 PUT_CODE (op
, prev_code
);
12295 PUT_MODE (op
, prev_op_mode
);
12296 recog_data
= prev_recog_data
;
12297 return result
>= 0;
12300 /* Returns true when recog of a 'treg_set_expr' is currently in progress.
12301 This can be used as a condition for insn/split patterns to allow certain
12302 T bit setting patters only to be matched as sub expressions of other
12305 sh_in_recog_treg_set_expr (void)
12307 return sh_recog_treg_set_expr_reent_count
> 0;
12310 /* Given an rtx x, which is assumed to be some expression that has been
12311 matched by the 'treg_set_expr' predicate before, split and emit the
12312 insns that are necessary to calculate the expression and store the result
12314 The splitting is done recursively similar to 'try_split' in emit-rt.c.
12315 Unfortunately we can't use 'try_split' here directly, as it tries to invoke
12316 'delete_insn' which then causes the DF parts to bail out, because we
12317 currently are inside another gen_split* function and would invoke
12318 'try_split' in a reentrant way. */
12319 static std::pair
<rtx_insn
*, rtx_insn
*>
12320 sh_try_split_insn_simple (rtx_insn
* i
, rtx_insn
* curr_insn
, int n
= 0)
12324 fprintf (dump_file
, "sh_try_split_insn_simple n = %d i = \n", n
);
12325 print_rtl_single (dump_file
, i
);
12326 fprintf (dump_file
, "\n");
12329 rtx_insn
* seq
= split_insns (PATTERN (i
), curr_insn
);
12332 return std::make_pair (i
, i
);
12334 /* Avoid infinite splitter loops if any insn of the result matches
12335 the original pattern. */
12336 for (rtx_insn
* s
= seq
; s
!= NULL
; s
= NEXT_INSN (s
))
12337 if (INSN_P (s
) && rtx_equal_p (PATTERN (s
), PATTERN (i
)))
12338 return std::make_pair (i
, i
);
12340 unshare_all_rtl_in_chain (seq
);
12342 /* 'seq' is now a replacement for 'i'. Assuming that 'i' is an insn in
12343 a linked list, replace the single insn with the new insns. */
12344 rtx_insn
* seqlast
= seq
;
12345 while (NEXT_INSN (seqlast
) != NULL
)
12346 seqlast
= NEXT_INSN (seqlast
);
12348 if (rtx_insn
* iprev
= PREV_INSN (i
))
12349 SET_NEXT_INSN (iprev
) = seq
;
12350 if (rtx_insn
* inext
= NEXT_INSN (i
))
12351 SET_PREV_INSN (inext
) = seqlast
;
12353 SET_PREV_INSN (seq
) = PREV_INSN (i
);
12354 SET_NEXT_INSN (seqlast
) = NEXT_INSN (i
);
12356 SET_PREV_INSN (i
) = NULL
;
12357 SET_NEXT_INSN (i
) = NULL
;
12359 /* Recursively split all insns. */
12360 for (i
= seq
; ; i
= NEXT_INSN (i
))
12362 std::pair
<rtx_insn
*, rtx_insn
*> ii
=
12363 sh_try_split_insn_simple (i
, curr_insn
, n
+ 1);
12368 seqlast
= ii
.second
;
12374 return std::make_pair (seq
, seqlast
);
12378 sh_split_treg_set_expr (rtx x
, rtx_insn
* curr_insn
)
12380 if (t_reg_operand (x
, VOIDmode
))
12381 return sh_treg_insns ();
12383 scope_counter
in_treg_set_expr (sh_recog_treg_set_expr_reent_count
);
12385 rtx_insn
* i
= make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), x
));
12386 SET_PREV_INSN (i
) = NULL
;
12387 SET_NEXT_INSN (i
) = NULL
;
12391 fprintf (dump_file
, "split_treg_set_expr insn:\n");
12392 print_rtl (dump_file
, i
);
12393 fprintf (dump_file
, "\n");
12396 /* If the insn is not found, we will try a negated form and append
12398 bool append_nott
= false;
12400 /* We are going to invoke recog/split_insns in a re-entrant way and thus
12401 have to capture its current state and restore it afterwards. */
12402 recog_data_d prev_recog_data
= recog_data
;
12404 if (negt_reg_operand (x
, GET_MODE (x
)))
12406 /* This is a normal movt followed by a nott. It will be converted
12407 into a movrt after initial expansion. */
12408 XEXP (PATTERN (i
), 1) = get_t_reg_rtx ();
12409 append_nott
= true;
12413 /* If the comparison op doesn't have a mode set, set it to SImode. */
12414 if (COMPARISON_P (x
) && GET_MODE (x
) == VOIDmode
)
12415 PUT_MODE (x
, SImode
);
12417 int insn_code
= recog (PATTERN (i
), i
, 0);
12419 if (insn_code
< 0 && COMPARISON_P (x
))
12421 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
12422 if (cmp_mode
== VOIDmode
)
12423 cmp_mode
= GET_MODE (XEXP (x
, 1));
12425 PUT_CODE (x
, reverse_condition (GET_CODE (x
)));
12426 insn_code
= recog (PATTERN (i
), i
, 0);
12427 append_nott
= true;
12430 gcc_assert (insn_code
>= 0);
12433 /* Try to recursively split the insn. Some insns might refuse to split
12434 any further while we are in the treg_set_expr splitting phase. They
12435 will be emitted as part of the outer insn and then split again. */
12436 std::pair
<rtx_insn
*, rtx_insn
*> insnlist
=
12437 sh_try_split_insn_simple (i
, curr_insn
);
12439 /* Restore recog state. */
12440 recog_data
= prev_recog_data
;
12442 rtx_insn
* nott_insn
= sh_is_nott_insn (insnlist
.second
)
12447 fprintf (dump_file
, "split_treg_set_expr insnlist:\n");
12448 print_rtl (dump_file
, insnlist
.first
);
12449 fprintf (dump_file
, "\n");
12451 if (nott_insn
!= NULL
)
12452 fprintf (dump_file
, "trailing nott insn %d\n", INSN_UID (nott_insn
));
12455 emit_insn (insnlist
.first
);
12457 if (nott_insn
!= NULL
&& append_nott
)
12460 fprintf (dump_file
, "removing trailing nott\n");
12461 remove_insn (nott_insn
);
12463 append_nott
= false;
12467 nott_insn
= emit_insn (gen_nott (get_t_reg_rtx ()));
12469 rtx_insn
* first_insn
= get_insns ();
12473 fprintf (dump_file
, "resulting insns:\n");
12474 print_rtl (dump_file
, first_insn
);
12475 fprintf (dump_file
, "\n");
12478 return sh_treg_insns (first_insn
, nott_insn
);
12481 /*------------------------------------------------------------------------------
12482 Mode switching support code.
12486 sh_emit_mode_set (int entity ATTRIBUTE_UNUSED
, int mode
,
12487 int prev_mode
, HARD_REG_SET regs_live ATTRIBUTE_UNUSED
)
12489 if ((TARGET_SH4A_FP
|| TARGET_SH4_300
)
12490 && prev_mode
!= FP_MODE_NONE
&& prev_mode
!= mode
)
12492 emit_insn (gen_toggle_pr ());
12494 emit_insn (gen_toggle_sz ());
12496 else if (mode
!= FP_MODE_NONE
)
12498 rtx tmp
= gen_reg_rtx (SImode
);
12499 emit_insn (gen_sts_fpscr (tmp
));
12502 const unsigned HOST_WIDE_INT fpbits
=
12503 TARGET_FMOVD
? (FPSCR_PR
| FPSCR_SZ
) : FPSCR_PR
;
12505 if (prev_mode
!= FP_MODE_NONE
&& prev_mode
!= mode
)
12506 i
= gen_xorsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (fpbits
)));
12507 else if (mode
== FP_MODE_SINGLE
)
12508 i
= gen_andsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (~fpbits
)));
12509 else if (mode
== FP_MODE_DOUBLE
)
12510 i
= gen_iorsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (fpbits
)));
12512 gcc_unreachable ();
12515 emit_insn (gen_lds_fpscr (tmp
));
12520 sh_mode_needed (int entity ATTRIBUTE_UNUSED
, rtx_insn
*insn
)
12522 return recog_memoized (insn
) >= 0 ? get_attr_fp_mode (insn
) : FP_MODE_NONE
;
12526 sh_mode_after (int entity ATTRIBUTE_UNUSED
, int mode
, rtx_insn
*insn
)
12528 if (TARGET_HITACHI
&& recog_memoized (insn
) >= 0 &&
12529 get_attr_fp_set (insn
) != FP_SET_NONE
)
12530 return (int) get_attr_fp_set (insn
);
12536 sh_mode_entry (int entity ATTRIBUTE_UNUSED
)
12538 return NORMAL_MODE (entity
);
12542 sh_mode_exit (int entity ATTRIBUTE_UNUSED
)
12544 return sh_cfun_attr_renesas_p () ? FP_MODE_NONE
: NORMAL_MODE (entity
);
12548 sh_mode_priority (int entity ATTRIBUTE_UNUSED
, int n
)
12550 return ((TARGET_FPU_SINGLE
!= 0) ^ (n
) ? FP_MODE_SINGLE
: FP_MODE_DOUBLE
);
12553 /*------------------------------------------------------------------------------
12557 /* Return true if we use LRA instead of reload pass. */
12561 return sh_lra_flag
;
12564 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12567 sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
12568 unsigned int align
,
12569 enum by_pieces_operation op
,
12574 case MOVE_BY_PIECES
:
12575 return by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1, op
)
12576 < (!speed_p
? 2 : (align
>= 32) ? 16 : 2);
12577 case STORE_BY_PIECES
:
12578 case SET_BY_PIECES
:
12579 return by_pieces_ninsns (size
, align
, STORE_MAX_PIECES
+ 1, op
)
12580 < (!speed_p
? 2 : (align
>= 32) ? 16 : 2);
12582 return default_use_by_pieces_infrastructure_p (size
, align
,
12588 sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED
,
12589 rtx x ATTRIBUTE_UNUSED
)
12591 return TARGET_FDPIC
;
12594 /* Emit insns to load the function address from FUNCDESC (an FDPIC
12595 function descriptor) into r1 and the GOT address into r12,
12596 returning an rtx for r1. */
12599 sh_load_function_descriptor (rtx funcdesc
)
12601 rtx r1
= gen_rtx_REG (Pmode
, R1_REG
);
12602 rtx pic_reg
= gen_rtx_REG (Pmode
, PIC_REG
);
12603 rtx fnaddr
= gen_rtx_MEM (Pmode
, funcdesc
);
12604 rtx gotaddr
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
, funcdesc
, 4));
12606 emit_move_insn (r1
, fnaddr
);
12607 /* The ABI requires the entry point address to be loaded first, so
12608 prevent the load from being moved after that of the GOT
12610 emit_insn (gen_blockage ());
12611 emit_move_insn (pic_reg
, gotaddr
);
12615 /* Return an rtx holding the initial value of the FDPIC register (the
12616 FDPIC pointer passed in from the caller). */
12619 sh_get_fdpic_reg_initial_val (void)
12621 return get_hard_reg_initial_val (Pmode
, PIC_REG
);