1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993-2015 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
34 #include "insn-config.h"
36 #include "fold-const.h"
37 #include "stringpool.h"
38 #include "stor-layout.h"
48 #include "insn-codes.h"
53 #include "insn-attr.h"
54 #include "diagnostic-core.h"
59 #include "langhooks.h"
64 #include "cfgcleanup.h"
66 #include "sched-int.h"
68 #include "internal-fn.h"
69 #include "gimple-fold.h"
73 #include "alloc-pool.h"
74 #include "tm-constrs.h"
76 #include "tree-pass.h"
77 #include "pass_manager.h"
82 /* This file should be included last. */
83 #include "target-def.h"
85 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
87 /* These are some macros to abstract register modes. */
88 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
89 && ((HOST_WIDE_INT)(VALUE)) <= 511)
91 #define CONST_OK_FOR_ADD(size) \
92 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
93 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
94 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
95 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
97 /* Used to simplify the logic below. Find the attributes wherever
99 #define SH_ATTRIBUTES(decl) \
100 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
101 : DECL_ATTRIBUTES (decl) \
102 ? (DECL_ATTRIBUTES (decl)) \
103 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
105 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
106 int current_function_interrupt
;
108 tree sh_deferred_function_attributes
;
109 tree
*sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
111 /* Global variables for machine-dependent things. */
113 /* Which cpu are we scheduling for. */
114 enum processor_type sh_cpu
;
116 /* Definitions used in ready queue reordering for first scheduling pass. */
118 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
119 static short *regmode_weight
[2];
121 /* Total SFmode and SImode weights of scheduled insns. */
122 static int curr_regmode_pressure
[2];
124 /* Number of r0 life regions. */
125 static int r0_life_regions
;
127 /* If true, skip cycles for Q -> R movement. */
128 static int skip_cycles
= 0;
130 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
131 and returned from sh_reorder2. */
132 static short cached_can_issue_more
;
134 /* Unique number for UNSPEC_BBR pattern. */
135 static unsigned int unspec_bbr_uid
= 1;
137 /* Provides the class number of the smallest class containing
139 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
141 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
142 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
143 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
144 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
145 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
146 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
147 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
148 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
149 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
150 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
151 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
152 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
153 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
154 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
155 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
156 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
157 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
158 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
159 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
160 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
161 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
162 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
163 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
164 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
165 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
166 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
167 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
168 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
169 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
170 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
171 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
172 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
173 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
174 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
175 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
176 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
177 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
178 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
179 GENERAL_REGS
, GENERAL_REGS
,
182 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
183 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
185 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
186 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
187 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
189 int assembler_dialect
;
191 static bool shmedia_space_reserved_for_target_registers
;
193 static void split_branches (rtx_insn
*);
194 static int branch_dest (rtx
);
195 static void print_slot (rtx_sequence
*);
196 static rtx_code_label
*add_constant (rtx
, machine_mode
, rtx
);
197 static void dump_table (rtx_insn
*, rtx_insn
*);
198 static bool broken_move (rtx_insn
*);
199 static bool mova_p (rtx_insn
*);
200 static rtx_insn
*find_barrier (int, rtx_insn
*, rtx_insn
*);
201 static bool noncall_uses_reg (rtx
, rtx_insn
*, rtx
*);
202 static rtx_insn
*gen_block_redirect (rtx_insn
*, int, int);
203 static void sh_reorg (void);
204 static void sh_option_override (void);
205 static void output_stack_adjust (int, rtx
, int, HARD_REG_SET
*, bool);
206 static rtx_insn
*frame_insn (rtx
);
207 static rtx
push (int);
208 static void pop (int);
209 static void push_regs (HARD_REG_SET
*, int);
210 static int calc_live_regs (HARD_REG_SET
*);
211 static HOST_WIDE_INT
rounded_frame_size (int);
212 static bool sh_frame_pointer_required (void);
213 static void sh_emit_mode_set (int, int, int, HARD_REG_SET
);
214 static int sh_mode_needed (int, rtx_insn
*);
215 static int sh_mode_after (int, int, rtx_insn
*);
216 static int sh_mode_entry (int);
217 static int sh_mode_exit (int);
218 static int sh_mode_priority (int entity
, int n
);
219 static bool sh_lra_p (void);
221 static rtx
mark_constant_pool_use (rtx
);
222 static tree
sh_handle_interrupt_handler_attribute (tree
*, tree
, tree
,
224 static tree
sh_handle_resbank_handler_attribute (tree
*, tree
,
226 static tree
sh2a_handle_function_vector_handler_attribute (tree
*, tree
,
228 static tree
sh_handle_sp_switch_attribute (tree
*, tree
, tree
, int, bool *);
229 static tree
sh_handle_trap_exit_attribute (tree
*, tree
, tree
, int, bool *);
230 static tree
sh_handle_renesas_attribute (tree
*, tree
, tree
, int, bool *);
231 static void sh_print_operand (FILE *, rtx
, int);
232 static void sh_print_operand_address (FILE *, rtx
);
233 static bool sh_print_operand_punct_valid_p (unsigned char code
);
234 static bool sh_asm_output_addr_const_extra (FILE *file
, rtx x
);
235 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT
);
236 static void sh_insert_attributes (tree
, tree
*);
237 static const char *sh_check_pch_target_flags (int);
238 static int sh_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
239 static int sh_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
240 static int sh_issue_rate (void);
241 static int sh_dfa_new_cycle (FILE *, int, rtx_insn
*, int, int, int *sort_p
);
242 static short find_set_regmode_weight (rtx
, machine_mode
);
243 static short find_insn_regmode_weight (rtx
, machine_mode
);
244 static void find_regmode_weight (basic_block
, machine_mode
);
245 static int find_r0_life_regions (basic_block
);
246 static void sh_md_init_global (FILE *, int, int);
247 static void sh_md_finish_global (FILE *, int);
248 static int rank_for_reorder (const void *, const void *);
249 static void swap_reorder (rtx_insn
**, int);
250 static void ready_reorder (rtx_insn
**, int);
251 static bool high_pressure (machine_mode
);
252 static int sh_reorder (FILE *, int, rtx_insn
**, int *, int);
253 static int sh_reorder2 (FILE *, int, rtx_insn
**, int *, int);
254 static void sh_md_init (FILE *, int, int);
255 static int sh_variable_issue (FILE *, int, rtx_insn
*, int);
257 static bool sh_function_ok_for_sibcall (tree
, tree
);
259 static bool sh_cannot_modify_jumps_p (void);
260 static bool sh_can_follow_jump (const rtx_insn
*, const rtx_insn
*);
261 static reg_class_t
sh_target_reg_class (void);
262 static bool sh_optimize_target_register_callee_saved (bool);
263 static bool sh_ms_bitfield_layout_p (const_tree
);
265 static void sh_init_builtins (void);
266 static tree
sh_builtin_decl (unsigned, bool);
267 static rtx
sh_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
268 static void sh_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
269 HOST_WIDE_INT
, tree
);
270 static void sh_file_start (void);
271 static bool flow_dependent_p (rtx
, rtx
);
272 static void flow_dependent_p_1 (rtx
, const_rtx
, void *);
273 static int shiftcosts (rtx
);
274 static int and_xor_ior_costs (rtx
, int);
275 static int addsubcosts (rtx
);
276 static int multcosts (rtx
);
277 static bool unspec_caller_rtx_p (rtx
);
278 static bool sh_cannot_copy_insn_p (rtx_insn
*);
279 static bool sh_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
280 static int sh_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
281 static int sh_pr_n_sets (void);
282 static rtx
sh_allocate_initial_value (rtx
);
283 static reg_class_t
sh_preferred_reload_class (rtx
, reg_class_t
);
284 static reg_class_t
sh_secondary_reload (bool, rtx
, reg_class_t
,
286 struct secondary_reload_info
*);
287 static bool sh_legitimate_address_p (machine_mode
, rtx
, bool);
288 static rtx
sh_legitimize_address (rtx
, rtx
, machine_mode
);
289 static rtx
sh_delegitimize_address (rtx
);
290 static bool sh_cannot_substitute_mem_equiv_p (rtx
);
291 static bool sh_legitimize_address_displacement (rtx
*, rtx
*, machine_mode
);
292 static int shmedia_target_regs_stack_space (HARD_REG_SET
*);
293 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET
*);
294 static int shmedia_target_regs_stack_adjust (HARD_REG_SET
*);
295 static int scavenge_reg (HARD_REG_SET
*s
);
296 struct save_schedule_s
;
297 static struct save_entry_s
*sh5_schedule_saves (HARD_REG_SET
*,
298 struct save_schedule_s
*, int);
300 static rtx
sh_struct_value_rtx (tree
, int);
301 static rtx
sh_function_value (const_tree
, const_tree
, bool);
302 static bool sh_function_value_regno_p (const unsigned int);
303 static rtx
sh_libcall_value (machine_mode
, const_rtx
);
304 static bool sh_return_in_memory (const_tree
, const_tree
);
305 static rtx
sh_builtin_saveregs (void);
306 static void sh_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
308 static bool sh_strict_argument_naming (cumulative_args_t
);
309 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t
);
310 static void sh_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
311 static tree
sh_build_builtin_va_list (void);
312 static void sh_va_start (tree
, rtx
);
313 static tree
sh_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
314 static bool sh_promote_prototypes (const_tree
);
315 static machine_mode
sh_promote_function_mode (const_tree type
,
320 static bool sh_pass_by_reference (cumulative_args_t
, machine_mode
,
322 static bool sh_callee_copies (cumulative_args_t
, machine_mode
,
324 static int sh_arg_partial_bytes (cumulative_args_t
, machine_mode
,
326 static void sh_function_arg_advance (cumulative_args_t
, machine_mode
,
328 static rtx
sh_function_arg (cumulative_args_t
, machine_mode
,
330 static bool sh_scalar_mode_supported_p (machine_mode
);
331 static int sh_dwarf_calling_convention (const_tree
);
332 static void sh_encode_section_info (tree
, rtx
, int);
333 static bool sh2a_function_vector_p (tree
);
334 static void sh_trampoline_init (rtx
, tree
, rtx
);
335 static rtx
sh_trampoline_adjust_address (rtx
);
336 static void sh_conditional_register_usage (void);
337 static bool sh_legitimate_constant_p (machine_mode
, rtx
);
338 static int mov_insn_size (machine_mode
, bool);
339 static int mov_insn_alignment_mask (machine_mode
, bool);
340 static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT
,
342 enum by_pieces_operation
,
344 static bool sequence_insn_p (rtx_insn
*);
345 static void sh_canonicalize_comparison (int *, rtx
*, rtx
*, bool);
346 static void sh_canonicalize_comparison (enum rtx_code
&, rtx
&, rtx
&,
348 static bool sh_legitimate_combined_insn (rtx_insn
* insn
);
350 static bool sh_fixed_condition_code_regs (unsigned int* p1
, unsigned int* p2
);
352 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
354 static const struct attribute_spec sh_attribute_table
[] =
356 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
357 affects_type_identity } */
358 { "interrupt_handler", 0, 0, true, false, false,
359 sh_handle_interrupt_handler_attribute
, false },
360 { "sp_switch", 1, 1, true, false, false,
361 sh_handle_sp_switch_attribute
, false },
362 { "trap_exit", 1, 1, true, false, false,
363 sh_handle_trap_exit_attribute
, false },
364 { "renesas", 0, 0, false, true, false,
365 sh_handle_renesas_attribute
, false },
366 { "trapa_handler", 0, 0, true, false, false,
367 sh_handle_interrupt_handler_attribute
, false },
368 { "nosave_low_regs", 0, 0, true, false, false,
369 sh_handle_interrupt_handler_attribute
, false },
370 { "resbank", 0, 0, true, false, false,
371 sh_handle_resbank_handler_attribute
, false },
372 { "function_vector", 1, 1, true, false, false,
373 sh2a_handle_function_vector_handler_attribute
, false },
374 { NULL
, 0, 0, false, false, false, NULL
, false }
377 /* Initialize the GCC target structure. */
378 #undef TARGET_ATTRIBUTE_TABLE
379 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
381 /* The next two are used for debug info when compiling with -gdwarf. */
382 #undef TARGET_ASM_UNALIGNED_HI_OP
383 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
384 #undef TARGET_ASM_UNALIGNED_SI_OP
385 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
387 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
388 #undef TARGET_ASM_UNALIGNED_DI_OP
389 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
390 #undef TARGET_ASM_ALIGNED_DI_OP
391 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
393 #undef TARGET_OPTION_OVERRIDE
394 #define TARGET_OPTION_OVERRIDE sh_option_override
396 #undef TARGET_PRINT_OPERAND
397 #define TARGET_PRINT_OPERAND sh_print_operand
398 #undef TARGET_PRINT_OPERAND_ADDRESS
399 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
400 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
401 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
402 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
403 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
405 #undef TARGET_ASM_FUNCTION_EPILOGUE
406 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
408 #undef TARGET_ASM_OUTPUT_MI_THUNK
409 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
411 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
412 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
413 hook_bool_const_tree_hwi_hwi_const_tree_true
415 #undef TARGET_ASM_FILE_START
416 #define TARGET_ASM_FILE_START sh_file_start
417 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
418 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
420 #undef TARGET_REGISTER_MOVE_COST
421 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
423 #undef TARGET_INSERT_ATTRIBUTES
424 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
426 #undef TARGET_SCHED_ADJUST_COST
427 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
429 #undef TARGET_SCHED_ISSUE_RATE
430 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
432 /* The next 5 hooks have been implemented for reenabling sched1. With the
433 help of these macros we are limiting the movement of insns in sched1 to
434 reduce the register pressure. The overall idea is to keep count of SImode
435 and SFmode regs required by already scheduled insns. When these counts
436 cross some threshold values; give priority to insns that free registers.
437 The insn that frees registers is most likely to be the insn with lowest
438 LUID (original insn order); but such an insn might be there in the stalled
439 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
440 up to a max of 8 cycles so that such insns may move from Q -> R.
442 The description of the hooks are as below:
444 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
445 scheduler; it is called inside the sched_init function just after
446 find_insn_reg_weights function call. It is used to calculate the SImode
447 and SFmode weights of insns of basic blocks; much similar to what
448 find_insn_reg_weights does.
449 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
451 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
452 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
455 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
456 high; reorder the ready queue so that the insn with lowest LUID will be
459 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
460 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
462 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
463 can be returned from TARGET_SCHED_REORDER2.
465 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
467 #undef TARGET_SCHED_DFA_NEW_CYCLE
468 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
470 #undef TARGET_SCHED_INIT_GLOBAL
471 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
473 #undef TARGET_SCHED_FINISH_GLOBAL
474 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
476 #undef TARGET_SCHED_VARIABLE_ISSUE
477 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
479 #undef TARGET_SCHED_REORDER
480 #define TARGET_SCHED_REORDER sh_reorder
482 #undef TARGET_SCHED_REORDER2
483 #define TARGET_SCHED_REORDER2 sh_reorder2
485 #undef TARGET_SCHED_INIT
486 #define TARGET_SCHED_INIT sh_md_init
488 #undef TARGET_DELEGITIMIZE_ADDRESS
489 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
491 #undef TARGET_LEGITIMIZE_ADDRESS
492 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
494 #undef TARGET_CANNOT_MODIFY_JUMPS_P
495 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
496 #undef TARGET_CAN_FOLLOW_JUMP
497 #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump
498 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
499 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
500 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
501 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
502 sh_optimize_target_register_callee_saved
504 #undef TARGET_MS_BITFIELD_LAYOUT_P
505 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
507 #undef TARGET_INIT_BUILTINS
508 #define TARGET_INIT_BUILTINS sh_init_builtins
509 #undef TARGET_BUILTIN_DECL
510 #define TARGET_BUILTIN_DECL sh_builtin_decl
511 #undef TARGET_EXPAND_BUILTIN
512 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
514 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
515 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
517 #undef TARGET_CANNOT_COPY_INSN_P
518 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
519 #undef TARGET_RTX_COSTS
520 #define TARGET_RTX_COSTS sh_rtx_costs
521 #undef TARGET_ADDRESS_COST
522 #define TARGET_ADDRESS_COST sh_address_cost
523 #undef TARGET_ALLOCATE_INITIAL_VALUE
524 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
526 #undef TARGET_MACHINE_DEPENDENT_REORG
527 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
529 #undef TARGET_DWARF_REGISTER_SPAN
530 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
533 #undef TARGET_HAVE_TLS
534 #define TARGET_HAVE_TLS true
537 #undef TARGET_PROMOTE_PROTOTYPES
538 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
539 #undef TARGET_PROMOTE_FUNCTION_MODE
540 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
542 #undef TARGET_FUNCTION_VALUE
543 #define TARGET_FUNCTION_VALUE sh_function_value
544 #undef TARGET_FUNCTION_VALUE_REGNO_P
545 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
546 #undef TARGET_LIBCALL_VALUE
547 #define TARGET_LIBCALL_VALUE sh_libcall_value
548 #undef TARGET_STRUCT_VALUE_RTX
549 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
550 #undef TARGET_RETURN_IN_MEMORY
551 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
553 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
554 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
555 #undef TARGET_SETUP_INCOMING_VARARGS
556 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
557 #undef TARGET_STRICT_ARGUMENT_NAMING
558 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
559 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
560 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
561 #undef TARGET_MUST_PASS_IN_STACK
562 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
563 #undef TARGET_PASS_BY_REFERENCE
564 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
565 #undef TARGET_CALLEE_COPIES
566 #define TARGET_CALLEE_COPIES sh_callee_copies
567 #undef TARGET_ARG_PARTIAL_BYTES
568 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
569 #undef TARGET_FUNCTION_ARG
570 #define TARGET_FUNCTION_ARG sh_function_arg
571 #undef TARGET_FUNCTION_ARG_ADVANCE
572 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
574 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
575 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sh_atomic_assign_expand_fenv
577 #undef TARGET_BUILD_BUILTIN_VA_LIST
578 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
579 #undef TARGET_EXPAND_BUILTIN_VA_START
580 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
581 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
582 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
584 #undef TARGET_SCALAR_MODE_SUPPORTED_P
585 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
586 #undef TARGET_VECTOR_MODE_SUPPORTED_P
587 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
589 #undef TARGET_CHECK_PCH_TARGET_FLAGS
590 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
592 #undef TARGET_DWARF_CALLING_CONVENTION
593 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
595 #undef TARGET_FRAME_POINTER_REQUIRED
596 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
598 #undef TARGET_MODE_EMIT
599 #define TARGET_MODE_EMIT sh_emit_mode_set
601 #undef TARGET_MODE_NEEDED
602 #define TARGET_MODE_NEEDED sh_mode_needed
604 #undef TARGET_MODE_AFTER
605 #define TARGET_MODE_AFTER sh_mode_after
607 #undef TARGET_MODE_ENTRY
608 #define TARGET_MODE_ENTRY sh_mode_entry
610 #undef TARGET_MODE_EXIT
611 #define TARGET_MODE_EXIT sh_mode_exit
613 #undef TARGET_MODE_PRIORITY
614 #define TARGET_MODE_PRIORITY sh_mode_priority
616 /* Return regmode weight for insn. */
617 #define INSN_REGMODE_WEIGHT(INSN, MODE)\
618 regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
620 /* Return current register pressure for regmode. */
621 #define CURR_REGMODE_PRESSURE(MODE)\
622 curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
624 #undef TARGET_ENCODE_SECTION_INFO
625 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
628 #define TARGET_LRA_P sh_lra_p
630 #undef TARGET_SECONDARY_RELOAD
631 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
633 #undef TARGET_PREFERRED_RELOAD_CLASS
634 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
636 #undef TARGET_CONDITIONAL_REGISTER_USAGE
637 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
639 #undef TARGET_LEGITIMATE_ADDRESS_P
640 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
642 #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P
643 #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P sh_cannot_substitute_mem_equiv_p
645 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
646 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
647 sh_legitimize_address_displacement
649 #undef TARGET_TRAMPOLINE_INIT
650 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
651 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
652 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
654 #undef TARGET_LEGITIMATE_CONSTANT_P
655 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
657 #undef TARGET_CANONICALIZE_COMPARISON
658 #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
660 #undef TARGET_LEGITIMATE_COMBINED_INSN
661 #define TARGET_LEGITIMATE_COMBINED_INSN sh_legitimate_combined_insn
663 #undef TARGET_FIXED_CONDITION_CODE_REGS
664 #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
666 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
667 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
668 sh_use_by_pieces_infrastructure_p
670 /* Machine-specific symbol_ref flags. */
671 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
673 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
674 is used by optabs.c atomic op expansion code as well as in sync.md. */
675 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
676 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
678 struct gcc_target targetm
= TARGET_INITIALIZER
;
681 /* Information on the currently selected atomic model.
682 This is initialized in sh_option_override. */
683 static sh_atomic_model selected_atomic_model_
;
685 const sh_atomic_model
&
686 selected_atomic_model (void)
688 return selected_atomic_model_
;
691 static sh_atomic_model
692 parse_validate_atomic_model_option (const char* str
)
694 const char* model_names
[sh_atomic_model::num_models
];
695 model_names
[sh_atomic_model::none
] = "none";
696 model_names
[sh_atomic_model::soft_gusa
] = "soft-gusa";
697 model_names
[sh_atomic_model::hard_llcs
] = "hard-llcs";
698 model_names
[sh_atomic_model::soft_tcb
] = "soft-tcb";
699 model_names
[sh_atomic_model::soft_imask
] = "soft-imask";
701 const char* model_cdef_names
[sh_atomic_model::num_models
];
702 model_cdef_names
[sh_atomic_model::none
] = "NONE";
703 model_cdef_names
[sh_atomic_model::soft_gusa
] = "SOFT_GUSA";
704 model_cdef_names
[sh_atomic_model::hard_llcs
] = "HARD_LLCS";
705 model_cdef_names
[sh_atomic_model::soft_tcb
] = "SOFT_TCB";
706 model_cdef_names
[sh_atomic_model::soft_imask
] = "SOFT_IMASK";
709 ret
.type
= sh_atomic_model::none
;
710 ret
.name
= model_names
[sh_atomic_model::none
];
711 ret
.cdef_name
= model_cdef_names
[sh_atomic_model::none
];
713 ret
.tcb_gbr_offset
= -1;
715 /* Handle empty string as 'none'. */
716 if (str
== NULL
|| *str
== '\0')
719 #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0)
721 std::vector
<std::string
> tokens
;
722 for (std::stringstream
ss (str
); ss
.good (); )
724 tokens
.push_back (std::string ());
725 std::getline (ss
, tokens
.back (), ',');
729 err_ret ("invalid atomic model option");
731 /* The first token must be the atomic model name. */
733 for (size_t i
= 0; i
< sh_atomic_model::num_models
; ++i
)
734 if (tokens
.front () == model_names
[i
])
736 ret
.type
= (sh_atomic_model::enum_type
)i
;
737 ret
.name
= model_names
[i
];
738 ret
.cdef_name
= model_cdef_names
[i
];
742 err_ret ("invalid atomic model name \"%s\"", tokens
.front ().c_str ());
746 /* Go through the remaining tokens. */
747 for (size_t i
= 1; i
< tokens
.size (); ++i
)
749 if (tokens
[i
] == "strict")
751 else if (tokens
[i
].find ("gbr-offset=") == 0)
753 std::string offset_str
= tokens
[i
].substr (strlen ("gbr-offset="));
754 ret
.tcb_gbr_offset
= integral_argument (offset_str
.c_str ());
755 if (offset_str
.empty () || ret
.tcb_gbr_offset
== -1)
756 err_ret ("could not parse gbr-offset value \"%s\" in atomic model "
757 "option", offset_str
.c_str ());
760 err_ret ("unknown parameter \"%s\" in atomic model option",
764 /* Check that the selection makes sense. */
765 if (TARGET_SHMEDIA
&& ret
.type
!= sh_atomic_model::none
)
766 err_ret ("atomic operations are not supported on SHmedia");
768 if (ret
.type
== sh_atomic_model::soft_gusa
&& !TARGET_SH3
)
769 err_ret ("atomic model %s is only available on SH3 and SH4 targets",
772 if (ret
.type
== sh_atomic_model::hard_llcs
&& !TARGET_SH4A
)
773 err_ret ("atomic model %s is only available on SH4A targets", ret
.name
);
775 if (ret
.type
== sh_atomic_model::soft_tcb
&& ret
.tcb_gbr_offset
== -1)
776 err_ret ("atomic model %s requires gbr-offset parameter", ret
.name
);
778 if (ret
.type
== sh_atomic_model::soft_tcb
779 && (ret
.tcb_gbr_offset
< 0 || ret
.tcb_gbr_offset
> 1020
780 || (ret
.tcb_gbr_offset
& 3) != 0))
781 err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be "
782 "a multiple of 4 in the range 0-1020", ret
.tcb_gbr_offset
,
785 if (ret
.type
== sh_atomic_model::soft_imask
&& TARGET_USERMODE
)
786 err_ret ("cannot use atomic model %s in user mode", ret
.name
);
793 /* Register SH specific RTL passes. */
794 extern opt_pass
* make_pass_sh_treg_combine (gcc::context
* ctx
, bool split_insns
,
796 extern opt_pass
* make_pass_sh_optimize_sett_clrt (gcc::context
* ctx
,
799 register_sh_passes (void)
804 /* Running the sh_treg_combine pass after ce1 generates better code when
805 comparisons are combined and reg-reg moves are introduced, because
806 reg-reg moves will be eliminated afterwards. However, there are quite
807 some cases where combine will be unable to fold comparison related insns,
808 thus for now don't do it.
809 register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"),
810 PASS_POS_INSERT_AFTER, "ce1", 1);
813 /* Run sh_treg_combine pass after combine but before register allocation. */
814 register_pass (make_pass_sh_treg_combine (g
, true, "sh_treg_combine2"),
815 PASS_POS_INSERT_AFTER
, "split1", 1);
817 /* Run sh_treg_combine pass after register allocation and basic block
818 reordering as this sometimes creates new opportunities. */
819 register_pass (make_pass_sh_treg_combine (g
, true, "sh_treg_combine3"),
820 PASS_POS_INSERT_AFTER
, "split4", 1);
822 /* Optimize sett and clrt insns, by e.g. removing them if the T bit value
823 is known after a conditional branch.
824 This must be done after basic blocks and branch conditions have
825 stabilized and won't be changed by further passes. */
826 register_pass (make_pass_sh_optimize_sett_clrt (g
, "sh_optimize_sett_clrt"),
827 PASS_POS_INSERT_BEFORE
, "sched2", 1);
830 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
831 various options, and do some machine dependent initialization. */
833 sh_option_override (void)
837 SUBTARGET_OVERRIDE_OPTIONS
;
838 if (optimize
> 1 && !optimize_size
)
839 target_flags
|= MASK_SAVE_ALL_TARGET_REGS
;
841 /* Set default values of TARGET_CBRANCHDI4 and TARGET_CMPEQDI_T. */
842 TARGET_CBRANCHDI4
= 1;
843 TARGET_CMPEQDI_T
= 0;
845 sh_cpu
= PROCESSOR_SH1
;
846 assembler_dialect
= 0;
848 sh_cpu
= PROCESSOR_SH2
;
850 sh_cpu
= PROCESSOR_SH2E
;
852 sh_cpu
= PROCESSOR_SH2A
;
854 sh_cpu
= PROCESSOR_SH3
;
856 sh_cpu
= PROCESSOR_SH3E
;
859 assembler_dialect
= 1;
860 sh_cpu
= PROCESSOR_SH4
;
864 assembler_dialect
= 1;
865 sh_cpu
= PROCESSOR_SH4A
;
869 sh_cpu
= PROCESSOR_SH5
;
870 target_flags
|= MASK_ALIGN_DOUBLE
;
871 if (TARGET_SHMEDIA_FPU
)
872 target_flags
|= MASK_FMOVD
;
875 /* There are no delay slots on SHmedia. */
876 flag_delayed_branch
= 0;
877 /* Relaxation isn't yet supported for SHmedia */
878 target_flags
&= ~MASK_RELAX
;
879 /* After reload, if conversion does little good but can cause
881 - find_if_block doesn't do anything for SH because we don't
882 have conditional execution patterns. (We use conditional
883 move patterns, which are handled differently, and only
885 - find_cond_trap doesn't do anything for the SH because we
886 don't have conditional traps.
887 - find_if_case_1 uses redirect_edge_and_branch_force in
888 the only path that does an optimization, and this causes
889 an ICE when branch targets are in registers.
890 - find_if_case_2 doesn't do anything for the SHmedia after
891 reload except when it can redirect a tablejump - and
892 that's rather rare. */
893 flag_if_conversion2
= 0;
894 if (! strcmp (sh_div_str
, "call"))
895 sh_div_strategy
= SH_DIV_CALL
;
896 else if (! strcmp (sh_div_str
, "call2"))
897 sh_div_strategy
= SH_DIV_CALL2
;
898 if (! strcmp (sh_div_str
, "fp") && TARGET_FPU_ANY
)
899 sh_div_strategy
= SH_DIV_FP
;
900 else if (! strcmp (sh_div_str
, "inv"))
901 sh_div_strategy
= SH_DIV_INV
;
902 else if (! strcmp (sh_div_str
, "inv:minlat"))
903 sh_div_strategy
= SH_DIV_INV_MINLAT
;
904 else if (! strcmp (sh_div_str
, "inv20u"))
905 sh_div_strategy
= SH_DIV_INV20U
;
906 else if (! strcmp (sh_div_str
, "inv20l"))
907 sh_div_strategy
= SH_DIV_INV20L
;
908 else if (! strcmp (sh_div_str
, "inv:call2"))
909 sh_div_strategy
= SH_DIV_INV_CALL2
;
910 else if (! strcmp (sh_div_str
, "inv:call"))
911 sh_div_strategy
= SH_DIV_INV_CALL
;
912 else if (! strcmp (sh_div_str
, "inv:fp"))
915 sh_div_strategy
= SH_DIV_INV_FP
;
917 sh_div_strategy
= SH_DIV_INV
;
919 TARGET_CBRANCHDI4
= 0;
920 /* Assembler CFI isn't yet fully supported for SHmedia. */
921 flag_dwarf2_cfi_asm
= 0;
926 /* Only the sh64-elf assembler fully supports .quad properly. */
927 targetm
.asm_out
.aligned_op
.di
= NULL
;
928 targetm
.asm_out
.unaligned_op
.di
= NULL
;
931 /* User/priviledged mode is supported only on SH3*, SH4* and SH5*.
932 Disable it for everything else. */
933 if (! (TARGET_SH3
|| TARGET_SH5
) && TARGET_USERMODE
)
934 TARGET_USERMODE
= false;
938 if (! strcmp (sh_div_str
, "call-div1"))
939 sh_div_strategy
= SH_DIV_CALL_DIV1
;
940 else if (! strcmp (sh_div_str
, "call-fp")
941 && (TARGET_FPU_DOUBLE
|| TARGET_FPU_SINGLE_ONLY
942 || (TARGET_SHCOMPACT
&& TARGET_FPU_ANY
)))
943 sh_div_strategy
= SH_DIV_CALL_FP
;
944 else if (! strcmp (sh_div_str
, "call-table") && TARGET_DYNSHIFT
)
945 sh_div_strategy
= SH_DIV_CALL_TABLE
;
947 /* Pick one that makes most sense for the target in general.
948 It is not much good to use different functions depending
949 on -Os, since then we'll end up with two different functions
950 when some of the code is compiled for size, and some for
953 /* SH4 tends to emphasize speed. */
955 sh_div_strategy
= SH_DIV_CALL_TABLE
;
956 /* These have their own way of doing things. */
957 else if (TARGET_SH2A
)
958 sh_div_strategy
= SH_DIV_INTRINSIC
;
959 /* ??? Should we use the integer SHmedia function instead? */
960 else if (TARGET_SHCOMPACT
&& TARGET_FPU_ANY
)
961 sh_div_strategy
= SH_DIV_CALL_FP
;
962 /* SH1 .. SH3 cores often go into small-footprint systems, so
963 default to the smallest implementation available. */
965 sh_div_strategy
= SH_DIV_CALL_DIV1
;
968 TARGET_PRETEND_CMOVE
= 0;
969 if (sh_divsi3_libfunc
[0])
970 ; /* User supplied - leave it alone. */
971 else if (TARGET_DIVIDE_CALL_FP
)
972 sh_divsi3_libfunc
= "__sdivsi3_i4";
973 else if (TARGET_DIVIDE_CALL_TABLE
)
974 sh_divsi3_libfunc
= "__sdivsi3_i4i";
976 sh_divsi3_libfunc
= "__sdivsi3_1";
978 sh_divsi3_libfunc
= "__sdivsi3";
980 if (sh_branch_cost
== -1)
982 /* The SH1 does not have delay slots, hence we get a pipeline stall
983 at every branch. The SH4 is superscalar, so the single delay slot
984 is not sufficient to keep both pipelines filled.
985 In any case, set the default branch cost to '2', as it results in
986 slightly overall smaller code and also enables some if conversions
987 that are required for matching special T bit related insns. */
991 /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */
992 if (! global_options_set
.x_TARGET_ZDCBRANCH
&& TARGET_HARD_SH4
)
993 TARGET_ZDCBRANCH
= 1;
995 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
996 if (! VALID_REGISTER_P (regno
))
997 sh_register_names
[regno
][0] = '\0';
999 for (regno
= 0; regno
< ADDREGNAMES_SIZE
; regno
++)
1000 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno
)))
1001 sh_additional_register_names
[regno
][0] = '\0';
1003 if ((flag_pic
&& ! TARGET_PREFERGOT
)
1004 || (TARGET_SHMEDIA
&& !TARGET_PT_FIXED
))
1005 flag_no_function_cse
= 1;
1007 if (targetm
.small_register_classes_for_mode_p (VOIDmode
))
1009 /* Never run scheduling before reload, since that can
1010 break global alloc, and generates slower code anyway due
1011 to the pressure on R0. */
1012 /* Enable sched1 for SH4 if the user explicitly requests.
1013 When sched1 is enabled, the ready queue will be reordered by
1014 the target hooks if pressure is high. We can not do this for
1015 PIC, SH3 and lower as they give spill failures for R0. */
1016 if (!TARGET_HARD_SH4
|| flag_pic
)
1017 flag_schedule_insns
= 0;
1018 /* ??? Current exception handling places basic block boundaries
1019 after call_insns. It causes the high pressure on R0 and gives
1020 spill failures for R0 in reload. See PR 22553 and the thread
1022 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
1023 else if (flag_exceptions
)
1025 if (flag_schedule_insns
&& global_options_set
.x_flag_schedule_insns
)
1026 warning (0, "ignoring -fschedule-insns because of exception "
1028 flag_schedule_insns
= 0;
1030 else if (flag_schedule_insns
1031 && !global_options_set
.x_flag_schedule_insns
)
1032 flag_schedule_insns
= 0;
1035 /* Unwind info is not correct around the CFG unless either a frame
1036 pointer is present or M_A_O_A is set. Fixing this requires rewriting
1037 unwind info generation to be aware of the CFG and propagating states
1039 if ((flag_unwind_tables
|| flag_asynchronous_unwind_tables
1040 || flag_exceptions
|| flag_non_call_exceptions
)
1041 && flag_omit_frame_pointer
&& !TARGET_ACCUMULATE_OUTGOING_ARGS
)
1043 warning (0, "unwind tables currently require either a frame pointer "
1044 "or -maccumulate-outgoing-args for correctness");
1045 TARGET_ACCUMULATE_OUTGOING_ARGS
= 1;
1048 /* Adjust loop, jump and function alignment values (in bytes), if those
1049 were not specified by the user using -falign-loops, -falign-jumps
1050 and -falign-functions options.
1051 32 bit alignment is better for speed, because instructions can be
1052 fetched as a pair from a longword boundary. For size use 16 bit
1053 alignment to get more compact code.
1054 Aligning all jumps increases the code size, even if it might
1055 result in slightly faster code. Thus, it is set to the smallest
1056 alignment possible if not specified by the user. */
1057 if (align_loops
== 0)
1062 align_loops
= optimize_size
? 2 : 4;
1065 if (align_jumps
== 0)
1068 align_jumps
= 1 << CACHE_LOG
;
1072 else if (align_jumps
< (TARGET_SHMEDIA
? 4 : 2))
1073 align_jumps
= TARGET_SHMEDIA
? 4 : 2;
1075 if (align_functions
== 0)
1078 align_functions
= optimize_size
1079 ? FUNCTION_BOUNDARY
/8 : (1 << CACHE_LOG
);
1081 align_functions
= optimize_size
? 2 : 4;
1084 /* The linker relaxation code breaks when a function contains
1085 alignments that are larger than that at the start of a
1086 compilation unit. */
1089 int min_align
= align_loops
> align_jumps
? align_loops
: align_jumps
;
1091 /* Also take possible .long constants / mova tables into account. */
1094 if (align_functions
< min_align
)
1095 align_functions
= min_align
;
1098 if (flag_unsafe_math_optimizations
)
1100 /* Enable fsca insn for SH4A if not otherwise specified by the user. */
1101 if (global_options_set
.x_TARGET_FSCA
== 0 && TARGET_SH4A_FP
)
1104 /* Enable fsrra insn for SH4A if not otherwise specified by the user. */
1105 if (global_options_set
.x_TARGET_FSRRA
== 0 && TARGET_SH4A_FP
)
1109 /* Allow fsrra insn only if -funsafe-math-optimizations and
1110 -ffinite-math-only is enabled. */
1111 TARGET_FSRRA
= TARGET_FSRRA
1112 && flag_unsafe_math_optimizations
1113 && flag_finite_math_only
;
1115 /* If the -mieee option was not explicitly set by the user, turn it on
1116 unless -ffinite-math-only was specified. See also PR 33135. */
1117 if (! global_options_set
.x_TARGET_IEEE
)
1118 TARGET_IEEE
= ! flag_finite_math_only
;
1120 if (sh_fixed_range_str
)
1121 sh_fix_range (sh_fixed_range_str
);
1123 /* This target defaults to strict volatile bitfields. */
1124 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
1125 flag_strict_volatile_bitfields
= 1;
1127 /* Parse atomic model option and make sure it is valid for the current
1129 selected_atomic_model_
1130 = parse_validate_atomic_model_option (sh_atomic_model_str
);
1132 register_sh_passes ();
1135 /* Print the operand address in x to the stream. */
1137 sh_print_operand_address (FILE *stream
, rtx x
)
1139 switch (GET_CODE (x
))
1143 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
1148 rtx base
= XEXP (x
, 0);
1149 rtx index
= XEXP (x
, 1);
1151 switch (GET_CODE (index
))
1154 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
1155 reg_names
[true_regnum (base
)]);
1161 int base_num
= true_regnum (base
);
1162 int index_num
= true_regnum (index
);
1164 fprintf (stream
, "@(r0,%s)",
1165 reg_names
[MAX (base_num
, index_num
)]);
1176 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
1180 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
1184 x
= mark_constant_pool_use (x
);
1185 output_addr_const (stream
, x
);
1190 /* Print operand x (an rtx) in assembler syntax to file stream
1191 according to modifier code.
1193 '.' print a .s if insn needs delay slot
1194 ',' print LOCAL_LABEL_PREFIX
1195 '@' print trap, rte or rts depending upon pragma interruptness
1196 '#' output a nop if there is nothing to put in the delay slot
1197 ''' print likelihood suffix (/u for unlikely).
1198 '>' print branch target if -fverbose-asm
1199 'O' print a constant without the #
1200 'R' print the LSW of a dp value - changes if in little endian
1201 'S' print the MSW of a dp value - changes if in little endian
1202 'T' print the next word of a dp value - same as 'R' in big endian mode.
1203 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1204 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
1205 'N' print 'r63' if the operand is (const_int 0).
1206 'd' print a V2SF reg as dN instead of fpN.
1207 'm' print a pair `base,offset' or `base,index', for LD and ST.
1208 'U' Likewise for {LD,ST}{HI,LO}.
1209 'V' print the position of a single bit set.
1210 'W' print the position of a single bit cleared.
1211 't' print a memory address which is a register.
1212 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1213 'o' output an operator. */
1215 sh_print_operand (FILE *stream
, rtx x
, int code
)
1226 && ! INSN_ANNULLED_BRANCH_P (final_sequence
->insn (0))
1227 && get_attr_length (final_sequence
->insn (1)))
1228 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
1231 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
1234 trapa_attr
= lookup_attribute ("trap_exit",
1235 DECL_ATTRIBUTES (current_function_decl
));
1237 fprintf (stream
, "trapa #%ld",
1238 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr
))));
1239 else if (sh_cfun_interrupt_handler_p ())
1241 if (sh_cfun_resbank_handler_p ())
1242 fprintf (stream
, "resbank\n");
1243 fprintf (stream
, "rte");
1246 fprintf (stream
, "rts");
1249 /* Output a nop if there's nothing in the delay slot. */
1250 if (dbr_sequence_length () == 0)
1251 fprintf (stream
, "\n\tnop");
1255 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1257 if (note
&& XINT (note
, 0) * 2 < REG_BR_PROB_BASE
)
1258 fputs ("/u", stream
);
1262 if (flag_verbose_asm
&& JUMP_LABEL (current_output_insn
))
1264 fputs ("\t! target: ", stream
);
1265 output_addr_const (stream
, JUMP_LABEL (current_output_insn
));
1269 x
= mark_constant_pool_use (x
);
1270 output_addr_const (stream
, x
);
1272 /* N.B.: %R / %S / %T adjust memory addresses by four.
1273 For SHMEDIA, that means they can be used to access the first and
1274 second 32 bit part of a 64 bit (or larger) value that
1275 might be held in floating point registers or memory.
1276 While they can be used to access 64 bit parts of a larger value
1277 held in general purpose registers, that won't work with memory -
1278 neither for fp registers, since the frxx names are used. */
1280 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1282 regno
= true_regnum (x
);
1283 regno
+= FP_REGISTER_P (regno
) ? 1 : SH_REG_LSW_OFFSET
;
1284 fputs (reg_names
[regno
], (stream
));
1288 x
= adjust_address (x
, SImode
, 4 * SH_REG_LSW_OFFSET
);
1289 sh_print_operand_address (stream
, XEXP (x
, 0));
1295 mode
= GET_MODE (x
);
1296 if (mode
== VOIDmode
)
1298 if (GET_MODE_SIZE (mode
) >= 8)
1299 sub
= simplify_subreg (SImode
, x
, mode
, 4 * SH_REG_LSW_OFFSET
);
1301 sh_print_operand (stream
, sub
, 0);
1303 output_operand_lossage ("invalid operand to %%R");
1307 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1309 regno
= true_regnum (x
);
1310 regno
+= FP_REGISTER_P (regno
) ? 0 : SH_REG_MSW_OFFSET
;
1311 fputs (reg_names
[regno
], (stream
));
1315 x
= adjust_address (x
, SImode
, 4 * SH_REG_MSW_OFFSET
);
1316 sh_print_operand_address (stream
, XEXP (x
, 0));
1322 mode
= GET_MODE (x
);
1323 if (mode
== VOIDmode
)
1325 if (GET_MODE_SIZE (mode
) >= 8)
1326 sub
= simplify_subreg (SImode
, x
, mode
, 4 * SH_REG_MSW_OFFSET
);
1328 sh_print_operand (stream
, sub
, 0);
1330 output_operand_lossage ("invalid operand to %%S");
1334 /* Next word of a double. */
1335 switch (GET_CODE (x
))
1338 fputs (reg_names
[REGNO (x
) + 1], (stream
));
1341 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
1342 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
1343 x
= adjust_address (x
, SImode
, 4);
1344 sh_print_operand_address (stream
, XEXP (x
, 0));
1352 gcc_assert (MEM_P (x
));
1354 switch (GET_CODE (x
))
1358 sh_print_operand (stream
, x
, 0);
1366 switch (GET_CODE (x
))
1368 case PLUS
: fputs ("add", stream
); break;
1369 case MINUS
: fputs ("sub", stream
); break;
1370 case MULT
: fputs ("mul", stream
); break;
1371 case DIV
: fputs ("div", stream
); break;
1372 case EQ
: fputs ("eq", stream
); break;
1373 case NE
: fputs ("ne", stream
); break;
1374 case GT
: case LT
: fputs ("gt", stream
); break;
1375 case GE
: case LE
: fputs ("ge", stream
); break;
1376 case GTU
: case LTU
: fputs ("gtu", stream
); break;
1377 case GEU
: case LEU
: fputs ("geu", stream
); break;
1386 && GET_CODE (XEXP (x
, 0)) == PLUS
1387 && (REG_P (XEXP (XEXP (x
, 0), 1))
1388 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
1389 fputc ('x', stream
);
1395 switch (GET_MODE (x
))
1397 case QImode
: fputs (".b", stream
); break;
1398 case HImode
: fputs (".w", stream
); break;
1399 case SImode
: fputs (".l", stream
); break;
1400 case SFmode
: fputs (".s", stream
); break;
1401 case DFmode
: fputs (".d", stream
); break;
1402 default: gcc_unreachable ();
1409 gcc_assert (MEM_P (x
));
1413 switch (GET_CODE (x
))
1417 sh_print_operand (stream
, x
, 0);
1418 fputs (", 0", stream
);
1422 sh_print_operand (stream
, XEXP (x
, 0), 0);
1423 fputs (", ", stream
);
1424 sh_print_operand (stream
, XEXP (x
, 1), 0);
1434 int num
= exact_log2 (INTVAL (x
));
1435 gcc_assert (num
>= 0);
1436 fprintf (stream
, "#%d", num
);
1442 int num
= exact_log2 (~INTVAL (x
));
1443 gcc_assert (num
>= 0);
1444 fprintf (stream
, "#%d", num
);
1449 gcc_assert (REG_P (x
) && GET_MODE (x
) == V2SFmode
);
1451 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
1455 if (x
== CONST0_RTX (GET_MODE (x
)))
1457 fprintf ((stream
), "r63");
1460 goto default_output
;
1462 if (CONST_INT_P (x
))
1464 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
1472 mode
= GET_MODE (x
);
1474 switch (GET_CODE (x
))
1478 rtx inner
= XEXP (x
, 0);
1480 machine_mode inner_mode
;
1482 /* We might see SUBREGs with vector mode registers inside. */
1483 if (GET_CODE (inner
) == SUBREG
1484 && (GET_MODE_SIZE (GET_MODE (inner
))
1485 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1486 && subreg_lowpart_p (inner
))
1487 inner
= SUBREG_REG (inner
);
1488 if (CONST_INT_P (inner
))
1490 x
= GEN_INT (trunc_int_for_mode (INTVAL (inner
), GET_MODE (x
)));
1491 goto default_output
;
1493 inner_mode
= GET_MODE (inner
);
1494 if (GET_CODE (inner
) == SUBREG
1495 && (GET_MODE_SIZE (GET_MODE (inner
))
1496 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1497 && REG_P (SUBREG_REG (inner
)))
1499 offset
= subreg_regno_offset (REGNO (SUBREG_REG (inner
)),
1500 GET_MODE (SUBREG_REG (inner
)),
1501 SUBREG_BYTE (inner
),
1503 inner
= SUBREG_REG (inner
);
1505 if (!REG_P (inner
) || GET_MODE_SIZE (inner_mode
) > 8)
1507 /* Floating point register pairs are always big endian;
1508 general purpose registers are 64 bit wide. */
1509 regno
= REGNO (inner
);
1510 regno
= (HARD_REGNO_NREGS (regno
, inner_mode
)
1511 - HARD_REGNO_NREGS (regno
, mode
))
1519 /* FIXME: We need this on SHmedia32 because reload generates
1520 some sign-extended HI or QI loads into DImode registers
1521 but, because Pmode is SImode, the address ends up with a
1522 subreg:SI of the DImode register. Maybe reload should be
1523 fixed so as to apply alter_subreg to such loads? */
1525 gcc_assert (trapping_target_operand (x
, VOIDmode
));
1526 x
= XEXP (XEXP (x
, 2), 0);
1527 goto default_output
;
1529 gcc_assert (SUBREG_BYTE (x
) == 0
1530 && REG_P (SUBREG_REG (x
)));
1538 if (FP_REGISTER_P (regno
)
1539 && mode
== V16SFmode
)
1540 fprintf ((stream
), "mtrx%s", reg_names
[regno
] + 2);
1541 else if (FP_REGISTER_P (REGNO (x
))
1542 && mode
== V4SFmode
)
1543 fprintf ((stream
), "fv%s", reg_names
[regno
] + 2);
1545 && mode
== V2SFmode
)
1546 fprintf ((stream
), "fp%s", reg_names
[regno
] + 2);
1547 else if (FP_REGISTER_P (REGNO (x
))
1548 && GET_MODE_SIZE (mode
) > 4)
1549 fprintf ((stream
), "d%s", reg_names
[regno
] + 1);
1551 fputs (reg_names
[regno
], (stream
));
1555 output_address (XEXP (x
, 0));
1560 fputc ('#', stream
);
1561 output_addr_const (stream
, x
);
1569 sh_print_operand_punct_valid_p (unsigned char code
)
1571 return (code
== '.' || code
== '#' || code
== '@' || code
== ','
1572 || code
== '$' || code
== '\'' || code
== '>');
1575 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1577 sh_asm_output_addr_const_extra (FILE *file
, rtx x
)
1579 if (GET_CODE (x
) == UNSPEC
)
1581 switch (XINT (x
, 1))
1583 case UNSPEC_DATALABEL
:
1584 fputs ("datalabel ", file
);
1585 output_addr_const (file
, XVECEXP (x
, 0, 0));
1588 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1589 output_addr_const (file
, XVECEXP (x
, 0, 0));
1592 output_addr_const (file
, XVECEXP (x
, 0, 0));
1593 fputs ("@GOT", file
);
1596 output_addr_const (file
, XVECEXP (x
, 0, 0));
1597 fputs ("@GOTOFF", file
);
1600 output_addr_const (file
, XVECEXP (x
, 0, 0));
1601 fputs ("@PLT", file
);
1604 output_addr_const (file
, XVECEXP (x
, 0, 0));
1605 fputs ("@GOTPLT", file
);
1608 output_addr_const (file
, XVECEXP (x
, 0, 0));
1609 fputs ("@PCREL", file
);
1612 output_addr_const (file
, XVECEXP (x
, 0, 0));
1613 fputs ("@DTPOFF", file
);
1615 case UNSPEC_GOTTPOFF
:
1616 output_addr_const (file
, XVECEXP (x
, 0, 0));
1617 fputs ("@GOTTPOFF", file
);
1620 output_addr_const (file
, XVECEXP (x
, 0, 0));
1621 fputs ("@TPOFF", file
);
1626 /* LPCS stands for Label for PIC Call Site. */
1627 targetm
.asm_out
.generate_internal_label (name
, "LPCS",
1628 INTVAL (XVECEXP (x
, 0, 0)));
1629 assemble_name (file
, name
);
1632 case UNSPEC_EXTRACT_S16
:
1633 case UNSPEC_EXTRACT_U16
:
1637 val
= XVECEXP (x
, 0, 0);
1638 shift
= XVECEXP (x
, 0, 1);
1640 if (shift
!= const0_rtx
)
1642 if (GET_CODE (val
) == CONST
1643 || GET_RTX_CLASS (GET_CODE (val
)) != RTX_OBJ
)
1646 output_addr_const (file
, val
);
1650 output_addr_const (file
, val
);
1651 if (shift
!= const0_rtx
)
1653 fputs (" >> ", file
);
1654 output_addr_const (file
, shift
);
1657 fputs (" & 65535)", file
);
1661 output_addr_const (file
, XVECEXP (x
, 0, 0));
1663 if (GET_CODE (XVECEXP (x
, 0, 1)) == CONST
)
1666 output_addr_const (file
, XVECEXP (x
, 0, 1));
1670 output_addr_const (file
, XVECEXP (x
, 0, 1));
1672 case UNSPEC_PCREL_SYMOFF
:
1673 output_addr_const (file
, XVECEXP (x
, 0, 0));
1675 output_addr_const (file
, XVECEXP (x
, 0, 1));
1676 fputs ("-.)", file
);
1687 /* Encode symbol attributes of a SYMBOL_REF into its
1688 SYMBOL_REF_FLAGS. */
1690 sh_encode_section_info (tree decl
, rtx rtl
, int first
)
1692 default_encode_section_info (decl
, rtl
, first
);
1694 if (TREE_CODE (decl
) == FUNCTION_DECL
1695 && sh2a_function_vector_p (decl
) && TARGET_SH2A
)
1696 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
1699 /* Prepare operands for a move define_expand; specifically, one of the
1700 operands must be in a register. */
1702 prepare_move_operands (rtx operands
[], machine_mode mode
)
1704 if ((mode
== SImode
|| mode
== DImode
)
1706 && ! ((mode
== Pmode
|| mode
== ptr_mode
)
1707 && tls_symbolic_operand (operands
[1], Pmode
) != TLS_MODEL_NONE
))
1710 if (SYMBOLIC_CONST_P (operands
[1]))
1712 if (MEM_P (operands
[0]))
1713 operands
[1] = force_reg (Pmode
, operands
[1]);
1714 else if (TARGET_SHMEDIA
1715 && GET_CODE (operands
[1]) == LABEL_REF
1716 && target_reg_operand (operands
[0], mode
))
1720 temp
= (!can_create_pseudo_p ()
1722 : gen_reg_rtx (Pmode
));
1723 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
1726 else if (GET_CODE (operands
[1]) == CONST
1727 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1728 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
1730 temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
1731 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
1733 operands
[1] = expand_binop (mode
, add_optab
, temp
,
1734 XEXP (XEXP (operands
[1], 0), 1),
1735 (!can_create_pseudo_p ()
1737 : gen_reg_rtx (Pmode
)),
1738 0, OPTAB_LIB_WIDEN
);
1742 if (! reload_in_progress
&& ! reload_completed
)
1744 /* Copy the source to a register if both operands aren't registers. */
1745 if (! register_operand (operands
[0], mode
)
1746 && ! sh_register_operand (operands
[1], mode
))
1747 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1749 if (MEM_P (operands
[0]) && ! memory_operand (operands
[0], mode
))
1751 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1752 except that we can't use that function because it is static. */
1753 rtx new_rtx
= change_address (operands
[0], mode
, 0);
1754 MEM_COPY_ATTRIBUTES (new_rtx
, operands
[0]);
1755 operands
[0] = new_rtx
;
1758 /* This case can happen while generating code to move the result
1759 of a library call to the target. Reject `st r0,@(rX,rY)' because
1760 reload will fail to find a spill register for rX, since r0 is already
1761 being used for the source. */
1763 && refers_to_regno_p (R0_REG
, operands
[1])
1764 && MEM_P (operands
[0])
1765 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
1766 && REG_P (XEXP (XEXP (operands
[0], 0), 1)))
1767 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1769 /* When the displacement addressing is used, RA will assign r0 to
1770 the pseudo register operand for the QI/HImode load/store.
1771 This tends to make a long live range for R0 and might cause
1772 anomalous register spills in some case with LRA. See PR
1774 We split possible load/store to two move insns via r0 so as to
1775 shorten R0 live range. It will make some codes worse but will
1776 win on average for LRA.
1777 Also when base+index addressing is used and the index term is
1778 a subreg, LRA assumes that more hard registers can be available
1779 in some situation. It isn't the case for SH in the problematic
1780 case. We can pre-allocate R0 for that index term to avoid
1781 the issue. See PR target/66591. */
1782 else if (sh_lra_p ()
1783 && TARGET_SH1
&& ! TARGET_SH2A
1784 && ((REG_P (operands
[0]) && MEM_P (operands
[1]))
1785 || (REG_P (operands
[1]) && MEM_P (operands
[0]))))
1787 bool load_p
= REG_P (operands
[0]);
1788 rtx reg
= operands
[load_p
? 0 : 1];
1789 rtx adr
= XEXP (operands
[load_p
? 1 : 0], 0);
1791 if ((mode
== QImode
|| mode
== HImode
)
1792 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1793 && GET_CODE (adr
) == PLUS
1794 && REG_P (XEXP (adr
, 0))
1795 && (REGNO (XEXP (adr
, 0)) >= FIRST_PSEUDO_REGISTER
)
1796 && CONST_INT_P (XEXP (adr
, 1))
1797 && INTVAL (XEXP (adr
, 1)) != 0
1798 && sh_legitimate_index_p (mode
, XEXP (adr
, 1), false, true))
1800 rtx r0_rtx
= gen_rtx_REG (mode
, R0_REG
);
1801 emit_move_insn (r0_rtx
, operands
[1]);
1802 operands
[1] = r0_rtx
;
1804 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1805 && GET_CODE (adr
) == PLUS
1806 && REG_P (XEXP (adr
, 0))
1807 && (REGNO (XEXP (adr
, 0)) >= FIRST_PSEUDO_REGISTER
)
1808 && SUBREG_P (XEXP (adr
, 1))
1809 && REG_P (SUBREG_REG (XEXP (adr
, 1))))
1811 rtx r0_rtx
= gen_rtx_REG (GET_MODE (XEXP (adr
, 1)), R0_REG
);
1812 emit_move_insn (r0_rtx
, XEXP (adr
, 1));
1813 XEXP (adr
, 1) = r0_rtx
;
1818 if (mode
== Pmode
|| mode
== ptr_mode
)
1821 enum tls_model tls_kind
;
1825 if (GET_CODE (op1
) == CONST
1826 && GET_CODE (XEXP (op1
, 0)) == PLUS
1827 && (tls_symbolic_operand (XEXP (XEXP (op1
, 0), 0), Pmode
)
1830 opc
= XEXP (XEXP (op1
, 0), 1);
1831 op1
= XEXP (XEXP (op1
, 0), 0);
1836 if (! reload_in_progress
&& ! reload_completed
1837 && (tls_kind
= tls_symbolic_operand (op1
, Pmode
)) != TLS_MODEL_NONE
)
1839 rtx tga_op1
, tga_ret
, tmp
, tmp2
;
1842 && (tls_kind
== TLS_MODEL_GLOBAL_DYNAMIC
1843 || tls_kind
== TLS_MODEL_LOCAL_DYNAMIC
1844 || tls_kind
== TLS_MODEL_INITIAL_EXEC
))
1846 static int got_labelno
;
1847 /* Don't schedule insns for getting GOT address when
1848 the first scheduling is enabled, to avoid spill
1850 if (flag_schedule_insns
)
1851 emit_insn (gen_blockage ());
1852 emit_insn (gen_GOTaddr2picreg (GEN_INT (++got_labelno
)));
1853 emit_use (gen_rtx_REG (SImode
, PIC_REG
));
1854 if (flag_schedule_insns
)
1855 emit_insn (gen_blockage ());
1860 case TLS_MODEL_GLOBAL_DYNAMIC
:
1861 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1862 emit_call_insn (gen_tls_global_dynamic (tga_ret
, op1
));
1863 tmp
= gen_reg_rtx (Pmode
);
1864 emit_move_insn (tmp
, tga_ret
);
1868 case TLS_MODEL_LOCAL_DYNAMIC
:
1869 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1870 emit_call_insn (gen_tls_local_dynamic (tga_ret
, op1
));
1872 tmp
= gen_reg_rtx (Pmode
);
1873 emit_move_insn (tmp
, tga_ret
);
1875 if (register_operand (op0
, Pmode
))
1878 tmp2
= gen_reg_rtx (Pmode
);
1880 emit_insn (gen_symDTPOFF2reg (tmp2
, op1
, tmp
));
1884 case TLS_MODEL_INITIAL_EXEC
:
1885 tga_op1
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (Pmode
);
1886 tmp
= gen_sym2GOTTPOFF (op1
);
1887 emit_insn (gen_tls_initial_exec (tga_op1
, tmp
));
1891 case TLS_MODEL_LOCAL_EXEC
:
1892 tmp2
= gen_reg_rtx (Pmode
);
1893 emit_insn (gen_store_gbr (tmp2
));
1894 tmp
= gen_reg_rtx (Pmode
);
1895 emit_insn (gen_symTPOFF2reg (tmp
, op1
));
1897 if (register_operand (op0
, Pmode
))
1900 op1
= gen_reg_rtx (Pmode
);
1902 emit_insn (gen_addsi3 (op1
, tmp
, tmp2
));
1909 emit_insn (gen_addsi3 (op1
, op1
, force_reg (SImode
, opc
)));
1915 /* Implement the canonicalize_comparison target hook for the combine
1916 pass. For the target hook this function is invoked via
1917 sh_canonicalize_comparison. This function is also re-used to
1918 canonicalize comparisons in cbranch pattern expanders. */
1920 sh_canonicalize_comparison (enum rtx_code
& cmp
, rtx
& op0
, rtx
& op1
,
1922 bool op0_preserve_value
)
1924 /* When invoked from within the combine pass the mode is not specified,
1925 so try to get it from one of the operands. */
1926 if (mode
== VOIDmode
)
1927 mode
= GET_MODE (op0
);
1928 if (mode
== VOIDmode
)
1929 mode
= GET_MODE (op1
);
1931 // We need to have a mode to do something useful here.
1932 if (mode
== VOIDmode
)
1935 // Currently, we don't deal with floats here.
1936 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1939 // Make sure that the constant operand is the second operand.
1940 if (CONST_INT_P (op0
) && !CONST_INT_P (op1
))
1942 if (op0_preserve_value
)
1945 std::swap (op0
, op1
);
1946 cmp
= swap_condition (cmp
);
1949 if (CONST_INT_P (op1
))
1951 /* Try to adjust the constant operand in such a way that available
1952 comparison insns can be utilized better and the constant can be
1953 loaded with a 'mov #imm,Rm' insn. This avoids a load from the
1955 const HOST_WIDE_INT val
= INTVAL (op1
);
1957 /* x > -1 --> x >= 0
1958 x > 0xFFFFFF7F --> x >= 0xFFFFFF80
1960 x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */
1961 if ((val
== -1 || val
== -0x81) && (cmp
== GT
|| cmp
== LE
))
1963 cmp
= cmp
== GT
? GE
: LT
;
1964 op1
= gen_int_mode (val
+ 1, mode
);
1968 x >= 0x80 --> x > 0x7F
1970 x < 0x80 --> x <= 0x7F */
1971 else if ((val
== 1 || val
== 0x80) && (cmp
== GE
|| cmp
== LT
))
1973 cmp
= cmp
== GE
? GT
: LE
;
1974 op1
= gen_int_mode (val
- 1, mode
);
1977 /* unsigned x >= 1 --> x != 0
1978 unsigned x < 1 --> x == 0 */
1979 else if (val
== 1 && (cmp
== GEU
|| cmp
== LTU
))
1981 cmp
= cmp
== GEU
? NE
: EQ
;
1982 op1
= CONST0_RTX (mode
);
1985 /* unsigned x >= 0x80 --> unsigned x > 0x7F
1986 unsigned x < 0x80 --> unsigned x < 0x7F */
1987 else if (val
== 0x80 && (cmp
== GEU
|| cmp
== LTU
))
1989 cmp
= cmp
== GEU
? GTU
: LEU
;
1990 op1
= gen_int_mode (val
- 1, mode
);
1993 /* unsigned x > 0 --> x != 0
1994 unsigned x <= 0 --> x == 0 */
1995 else if (val
== 0 && (cmp
== GTU
|| cmp
== LEU
))
1996 cmp
= cmp
== GTU
? NE
: EQ
;
1998 /* unsigned x > 0x7FFFFFFF --> signed x < 0
1999 unsigned x <= 0x7FFFFFFF --> signed x >= 0 */
2000 else if (mode
== SImode
&& (cmp
== GTU
|| cmp
== LEU
)
2001 && val
== 0x7FFFFFFF)
2003 cmp
= cmp
== GTU
? LT
: GE
;
2007 /* unsigned x >= 0x80000000 --> signed x < 0
2008 unsigned x < 0x80000000 --> signed x >= 0 */
2009 else if (mode
== SImode
&& (cmp
== GEU
|| cmp
== LTU
)
2010 && (unsigned HOST_WIDE_INT
)val
2011 == ((unsigned HOST_WIDE_INT
)0x7FFFFFFF + 1))
2013 cmp
= cmp
== GEU
? LT
: GE
;
2019 /* This function implements the canonicalize_comparison target hook.
2020 This wrapper around the internally used sh_canonicalize_comparison
2021 function is needed to do the enum rtx_code <-> int conversion.
2022 Target hooks cannot use enum rtx_code in its definition. */
2024 sh_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
2025 bool op0_preserve_value
)
2027 enum rtx_code tmp_code
= (enum rtx_code
)*code
;
2028 sh_canonicalize_comparison (tmp_code
, *op0
, *op1
,
2029 VOIDmode
, op0_preserve_value
);
2030 *code
= (int)tmp_code
;
2033 /* This function implements the legitimate_combined_insn target hook,
2034 which the combine pass uses to early reject combined insns, before
2035 it tries to recog the insn and determine its cost. */
2037 sh_legitimate_combined_insn (rtx_insn
* insn
)
2039 /* Reject combinations of memory loads and zero extensions, as these
2040 interfere with other combine patterns such as zero extracts and bit
2041 tests. The SH2A movu.{b|w} insns are formed later in the
2042 'sh_optimize_extu_exts' pass after combine/split1. */
2043 rtx p
= PATTERN (insn
);
2044 if (GET_CODE (p
) == SET
2045 && REG_P (XEXP (p
, 0)) && GET_MODE (XEXP (p
, 0)) == SImode
2046 && GET_CODE (XEXP (p
, 1)) == ZERO_EXTEND
2047 && MEM_P (XEXP (XEXP (p
, 1), 0)))
2054 sh_fixed_condition_code_regs (unsigned int* p1
, unsigned int* p2
)
2057 *p2
= INVALID_REGNUM
;
2062 prepare_cbranch_operands (rtx
*operands
, machine_mode mode
,
2063 enum rtx_code comparison
)
2065 /* The scratch reg is only available when this is invoked from within
2066 the cbranchdi4_i splitter, through expand_cbranchdi4. */
2067 rtx scratch
= NULL_RTX
;
2069 if (comparison
== LAST_AND_UNUSED_RTX_CODE
)
2070 comparison
= GET_CODE (operands
[0]);
2072 scratch
= operands
[4];
2074 sh_canonicalize_comparison (comparison
, operands
[1], operands
[2],
2077 /* Notice that this function is also invoked after reload by
2078 the cbranchdi4_i pattern, through expand_cbranchdi4. */
2079 rtx op1
= operands
[1];
2081 if (can_create_pseudo_p ())
2082 operands
[1] = force_reg (mode
, op1
);
2083 /* When we are handling DImode comparisons, we want to keep constants so
2084 that we can optimize the component comparisons; however, memory loads
2085 are better issued as a whole so that they can be scheduled well.
2086 SImode equality comparisons allow I08 constants, but only when they
2087 compare r0. Hence, if operands[1] has to be loaded from somewhere else
2088 into a register, that register might as well be r0, and we allow the
2089 constant. If it is already in a register, this is likely to be
2090 allocated to a different hard register, thus we load the constant into
2091 a register unless it is zero. */
2092 if (!REG_P (operands
[2])
2093 && (!CONST_INT_P (operands
[2])
2094 || (mode
== SImode
&& operands
[2] != CONST0_RTX (SImode
)
2095 && ((comparison
!= EQ
&& comparison
!= NE
)
2096 || (REG_P (op1
) && REGNO (op1
) != R0_REG
)
2097 || !satisfies_constraint_I08 (operands
[2])))))
2099 if (scratch
&& GET_MODE (scratch
) == mode
)
2101 emit_move_insn (scratch
, operands
[2]);
2102 operands
[2] = scratch
;
2104 else if (can_create_pseudo_p ())
2105 operands
[2] = force_reg (mode
, operands
[2]);
2111 expand_cbranchsi4 (rtx
*operands
, enum rtx_code comparison
, int probability
)
2113 rtx (*branch_expander
) (rtx
) = gen_branch_true
;
2114 comparison
= prepare_cbranch_operands (operands
, SImode
, comparison
);
2117 case NE
: case LT
: case LE
: case LTU
: case LEU
:
2118 comparison
= reverse_condition (comparison
);
2119 branch_expander
= gen_branch_false
;
2122 emit_insn (gen_rtx_SET (get_t_reg_rtx (),
2123 gen_rtx_fmt_ee (comparison
, SImode
,
2124 operands
[1], operands
[2])));
2125 rtx_insn
*jump
= emit_jump_insn (branch_expander (operands
[3]));
2126 if (probability
>= 0)
2127 add_int_reg_note (jump
, REG_BR_PROB
, probability
);
2130 /* ??? How should we distribute probabilities when more than one branch
2131 is generated. So far we only have some ad-hoc observations:
2132 - If the operands are random, they are likely to differ in both parts.
2133 - If comparing items in a hash chain, the operands are random or equal;
2134 operation should be EQ or NE.
2135 - If items are searched in an ordered tree from the root, we can expect
2136 the highpart to be unequal about half of the time; operation should be
2137 an inequality comparison, operands non-constant, and overall probability
2138 about 50%. Likewise for quicksort.
2139 - Range checks will be often made against constants. Even if we assume for
2140 simplicity an even distribution of the non-constant operand over a
2141 sub-range here, the same probability could be generated with differently
2142 wide sub-ranges - as long as the ratio of the part of the subrange that
2143 is before the threshold to the part that comes after the threshold stays
2144 the same. Thus, we can't really tell anything here;
2145 assuming random distribution is at least simple.
2148 expand_cbranchdi4 (rtx
*operands
, enum rtx_code comparison
)
2150 enum rtx_code msw_taken
, msw_skip
, lsw_taken
;
2151 rtx_code_label
*skip_label
= NULL
;
2152 rtx op1h
, op1l
, op2h
, op2l
;
2155 int msw_taken_prob
= -1, msw_skip_prob
= -1, lsw_taken_prob
= -1;
2156 rtx scratch
= operands
[4];
2158 comparison
= prepare_cbranch_operands (operands
, DImode
, comparison
);
2159 op1h
= gen_highpart_mode (SImode
, DImode
, operands
[1]);
2160 op2h
= gen_highpart_mode (SImode
, DImode
, operands
[2]);
2161 op1l
= gen_lowpart (SImode
, operands
[1]);
2162 op2l
= gen_lowpart (SImode
, operands
[2]);
2163 msw_taken
= msw_skip
= lsw_taken
= LAST_AND_UNUSED_RTX_CODE
;
2164 prob
= split_branch_probability
;
2165 rev_prob
= REG_BR_PROB_BASE
- prob
;
2168 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
2169 That costs 1 cycle more when the first branch can be predicted taken,
2170 but saves us mispredicts because only one branch needs prediction.
2171 It also enables generating the cmpeqdi_t-1 pattern. */
2173 if (TARGET_CMPEQDI_T
)
2175 emit_insn (gen_cmpeqdi_t (operands
[1], operands
[2]));
2176 emit_jump_insn (gen_branch_true (operands
[3]));
2183 // If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
2184 msw_skip_prob
= rev_prob
;
2185 if (REG_BR_PROB_BASE
<= 65535)
2186 lsw_taken_prob
= prob
? REG_BR_PROB_BASE
: 0;
2192 - ((gcov_type
) REG_BR_PROB_BASE
* rev_prob
2193 / ((gcov_type
) prob
<< 32)))
2199 if (TARGET_CMPEQDI_T
)
2201 emit_insn (gen_cmpeqdi_t (operands
[1], operands
[2]));
2202 emit_jump_insn (gen_branch_false (operands
[3]));
2206 msw_taken_prob
= prob
;
2211 msw_taken
= comparison
;
2212 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
2214 if (comparison
!= GTU
|| op2h
!= CONST0_RTX (SImode
))
2215 msw_skip
= swap_condition (msw_taken
);
2219 if (op2l
== CONST0_RTX (SImode
))
2220 msw_taken
= comparison
;
2223 msw_taken
= comparison
== GE
? GT
: GTU
;
2224 msw_skip
= swap_condition (msw_taken
);
2229 msw_taken
= comparison
;
2230 if (op2l
== CONST0_RTX (SImode
))
2232 msw_skip
= swap_condition (msw_taken
);
2236 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
2237 msw_taken
= comparison
;
2241 if (comparison
== LE
)
2243 else if (op2h
!= CONST0_RTX (SImode
))
2247 msw_skip
= swap_condition (LTU
);
2250 msw_skip
= swap_condition (msw_taken
);
2253 default: return false;
2255 num_branches
= ((msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2256 + (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2257 + (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
));
2258 if (comparison
!= EQ
&& comparison
!= NE
&& num_branches
> 1)
2260 if (!CONSTANT_P (operands
[2])
2261 && prob
>= (int) (REG_BR_PROB_BASE
* 3 / 8U)
2262 && prob
<= (int) (REG_BR_PROB_BASE
* 5 / 8U))
2264 msw_taken_prob
= prob
/ 2U;
2266 = REG_BR_PROB_BASE
* rev_prob
/ (REG_BR_PROB_BASE
+ rev_prob
);
2267 lsw_taken_prob
= prob
;
2271 msw_taken_prob
= prob
;
2272 msw_skip_prob
= REG_BR_PROB_BASE
;
2273 /* ??? If we have a constant op2h, should we use that when
2274 calculating lsw_taken_prob? */
2275 lsw_taken_prob
= prob
;
2280 operands
[4] = NULL_RTX
;
2281 if (reload_completed
2282 && ! arith_reg_or_0_operand (op2h
, SImode
)
2283 && (true_regnum (op1h
) || (comparison
!= EQ
&& comparison
!= NE
))
2284 && (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
2285 || msw_skip
!= LAST_AND_UNUSED_RTX_CODE
))
2287 emit_move_insn (scratch
, operands
[2]);
2288 operands
[2] = scratch
;
2290 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2291 expand_cbranchsi4 (operands
, msw_taken
, msw_taken_prob
);
2292 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2294 rtx taken_label
= operands
[3];
2296 /* Operands were possibly modified, but msw_skip doesn't expect this.
2297 Always use the original ones. */
2298 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2302 if (reload_completed
2303 && ! arith_reg_or_0_operand (op2h
, SImode
)
2304 && (true_regnum (op1h
) || (comparison
!= EQ
&& comparison
!= NE
)))
2306 emit_move_insn (scratch
, operands
[2]);
2307 operands
[2] = scratch
;
2311 operands
[3] = skip_label
= gen_label_rtx ();
2312 expand_cbranchsi4 (operands
, msw_skip
, msw_skip_prob
);
2313 operands
[3] = taken_label
;
2317 if (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2319 if (reload_completed
2320 && ! arith_reg_or_0_operand (op2l
, SImode
)
2321 && (true_regnum (op1l
) || (lsw_taken
!= EQ
&& lsw_taken
!= NE
)))
2323 emit_move_insn (scratch
, operands
[2]);
2324 operands
[2] = scratch
;
2326 expand_cbranchsi4 (operands
, lsw_taken
, lsw_taken_prob
);
2328 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2329 emit_label (skip_label
);
2333 /* Given an operand, return 1 if the evaluated operand plugged into an
2334 if_then_else will result in a branch_true, 0 if branch_false, or
2335 -1 if neither nor applies. The truth table goes like this:
2337 op | cmpval | code | result
2338 ---------+--------+---------+--------------------
2339 T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1)
2340 T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1)
2341 T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0)
2342 T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0)
2343 !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1)
2344 !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1)
2345 !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0)
2346 !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */
2348 sh_eval_treg_value (rtx op
)
2350 if (t_reg_operand (op
, GET_MODE (op
)))
2352 if (negt_reg_operand (op
, GET_MODE (op
)))
2355 rtx_code code
= GET_CODE (op
);
2356 if ((code
!= EQ
&& code
!= NE
) || !CONST_INT_P (XEXP (op
, 1)))
2359 int cmpop
= code
== EQ
? 1 : 0;
2360 int cmpval
= INTVAL (XEXP (op
, 1));
2361 if (cmpval
!= 0 && cmpval
!= 1)
2365 if (t_reg_operand (XEXP (op
, 0), GET_MODE (XEXP (op
, 0))))
2367 else if (negt_reg_operand (XEXP (op
, 0), GET_MODE (XEXP (op
, 0))))
2372 return t
^ (cmpval
== cmpop
);
2375 /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case
2376 of floating-point comparisons. */
2378 sh_emit_set_t_insn (rtx insn
, machine_mode mode
)
2380 if (TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
2381 && GET_CODE (insn
) != PARALLEL
)
2383 insn
= gen_rtx_PARALLEL (VOIDmode
,
2385 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, FPSCR_STAT_REG
)),
2386 gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, FPSCR_MODES_REG
))));
2391 /* Prepare the operands for an scc instruction; make sure that the
2392 compare has been done and the result is in T_REG. */
2394 sh_emit_scc_to_t (enum rtx_code code
, rtx op0
, rtx op1
)
2396 rtx t_reg
= get_t_reg_rtx ();
2397 enum rtx_code oldcode
= code
;
2400 /* First need a compare insn. */
2404 /* It isn't possible to handle this case. */
2421 if (code
!= oldcode
)
2422 std::swap (op0
, op1
);
2424 mode
= GET_MODE (op0
);
2425 if (mode
== VOIDmode
)
2426 mode
= GET_MODE (op1
);
2428 op0
= force_reg (mode
, op0
);
2429 if ((code
!= EQ
&& code
!= NE
2430 && (op1
!= const0_rtx
2431 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2432 || (mode
== DImode
&& op1
!= const0_rtx
)
2433 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2434 op1
= force_reg (mode
, op1
);
2436 sh_emit_set_t_insn (gen_rtx_SET (t_reg
,
2437 gen_rtx_fmt_ee (code
, SImode
, op0
, op1
)),
2442 sh_emit_cheap_store_flag (machine_mode mode
, enum rtx_code code
,
2445 rtx target
= gen_reg_rtx (SImode
);
2448 gcc_assert (TARGET_SHMEDIA
);
2457 tmp
= gen_rtx_fmt_ee (code
, SImode
, op0
, op1
);
2458 emit_insn (gen_cstore4_media (target
, tmp
, op0
, op1
));
2468 tmp
= gen_rtx_fmt_ee (reverse_condition (code
), mode
, op0
, op1
);
2469 emit_insn (gen_cstore4_media (target
, tmp
, op0
, op1
));
2487 rtx t2
= gen_reg_rtx (DImode
);
2488 emit_insn (gen_extendsidi2 (t2
, target
));
2492 return gen_rtx_fmt_ee (code
, VOIDmode
, target
, const0_rtx
);
2495 /* Called from the md file, set up the operands of a compare instruction. */
2497 sh_emit_compare_and_branch (rtx
*operands
, machine_mode mode
)
2499 enum rtx_code code
= GET_CODE (operands
[0]);
2500 enum rtx_code branch_code
;
2501 rtx op0
= operands
[1];
2502 rtx op1
= operands
[2];
2504 bool need_ccmpeq
= false;
2506 if (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2508 op0
= force_reg (mode
, op0
);
2509 op1
= force_reg (mode
, op1
);
2513 if (code
!= EQ
|| mode
== DImode
)
2515 /* Force args into regs, since we can't use constants here. */
2516 op0
= force_reg (mode
, op0
);
2517 if (op1
!= const0_rtx
|| code
== GTU
|| code
== GEU
)
2518 op1
= force_reg (mode
, op1
);
2522 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2525 || (code
== LE
&& TARGET_IEEE
&& TARGET_SH2E
)
2526 || (code
== GE
&& !(TARGET_IEEE
&& TARGET_SH2E
)))
2528 std::swap (op0
, op1
);
2529 code
= swap_condition (code
);
2532 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2535 gcc_assert (TARGET_IEEE
&& TARGET_SH2E
);
2540 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2541 to EQ/GT respectively. */
2542 gcc_assert (code
== EQ
|| code
== GT
|| code
== NE
|| code
== LE
);
2559 branch_code
= reverse_condition (code
);
2565 insn
= gen_rtx_SET (get_t_reg_rtx (),
2566 gen_rtx_fmt_ee (branch_code
, SImode
, op0
, op1
));
2568 sh_emit_set_t_insn (insn
, mode
);
2570 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0
, op1
), mode
);
2572 if (branch_code
== code
)
2573 emit_jump_insn (gen_branch_true (operands
[3]));
2575 emit_jump_insn (gen_branch_false (operands
[3]));
2579 sh_emit_compare_and_set (rtx
*operands
, machine_mode mode
)
2581 enum rtx_code code
= GET_CODE (operands
[1]);
2582 rtx op0
= operands
[2];
2583 rtx op1
= operands
[3];
2584 rtx_code_label
*lab
= NULL
;
2585 bool invert
= false;
2587 op0
= force_reg (mode
, op0
);
2588 if ((code
!= EQ
&& code
!= NE
2589 && (op1
!= const0_rtx
2590 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2591 || (mode
== DImode
&& op1
!= const0_rtx
)
2592 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2593 op1
= force_reg (mode
, op1
);
2595 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2597 if (code
== LT
|| code
== LE
)
2599 std::swap (op0
, op1
);
2600 code
= swap_condition (code
);
2606 lab
= gen_label_rtx ();
2607 sh_emit_scc_to_t (EQ
, op0
, op1
);
2608 emit_jump_insn (gen_branch_true (lab
));
2625 sh_emit_scc_to_t (code
, op0
, op1
);
2629 emit_insn (gen_movnegt (operands
[0], get_t_reg_rtx ()));
2631 emit_move_insn (operands
[0], get_t_reg_rtx ());
2634 /* Functions to output assembly code. */
2636 /* Return a sequence of instructions to perform DI or DF move.
2638 Since the SH cannot move a DI or DF in one instruction, we have
2639 to take care when we see overlapping source and dest registers. */
2641 output_movedouble (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
2644 rtx dst
= operands
[0];
2645 rtx src
= operands
[1];
2648 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
2649 return "mov.l %T1,%0" "\n"
2652 if (register_operand (dst
, mode
)
2653 && register_operand (src
, mode
))
2655 if (REGNO (src
) == MACH_REG
)
2656 return "sts mach,%S0" "\n"
2659 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2660 when mov.d r1,r0 do r1->r0 then r2->r1. */
2661 if (REGNO (src
) + 1 == REGNO (dst
))
2662 return "mov %T1,%T0" "\n"
2665 return "mov %1,%0" "\n"
2668 else if (CONST_INT_P (src
))
2670 if (INTVAL (src
) < 0)
2671 output_asm_insn ("mov #-1,%S0", operands
);
2673 output_asm_insn ("mov #0,%S0", operands
);
2675 return "mov %1,%R0";
2677 else if (MEM_P (src
))
2680 int dreg
= REGNO (dst
);
2681 rtx inside
= XEXP (src
, 0);
2683 switch (GET_CODE (inside
))
2686 ptrreg
= REGNO (inside
);
2690 ptrreg
= subreg_regno (inside
);
2694 ptrreg
= REGNO (XEXP (inside
, 0));
2695 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2696 an offsettable address. Unfortunately, offsettable addresses use
2697 QImode to check the offset, and a QImode offsettable address
2698 requires r0 for the other operand, which is not currently
2699 supported, so we can't use the 'o' constraint.
2700 Thus we must check for and handle r0+REG addresses here.
2701 We punt for now, since this is likely very rare. */
2702 gcc_assert (!REG_P (XEXP (inside
, 1)));
2706 return "mov.l %1,%0" "\n"
2709 return "mov.l %1,%0" "\n"
2715 /* Work out the safe way to copy. Copy into the second half first. */
2717 return "mov.l %T1,%T0" "\n"
2721 return "mov.l %1,%0" "\n"
2725 /* Print an instruction which would have gone into a delay slot after
2726 another instruction, but couldn't because the other instruction expanded
2727 into a sequence where putting the slot insn at the end wouldn't work. */
2729 print_slot (rtx_sequence
*seq
)
2731 final_scan_insn (seq
->insn (1), asm_out_file
, optimize
, 1, NULL
);
2733 seq
->insn (1)->set_deleted ();
2737 output_far_jump (rtx_insn
*insn
, rtx op
)
2739 struct { rtx lab
, reg
, op
; } this_jmp
;
2740 rtx_code_label
*braf_base_lab
= NULL
;
2743 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2746 this_jmp
.lab
= gen_label_rtx ();
2750 && offset
- get_attr_length (insn
) <= 32766
2751 && ! CROSSING_JUMP_P (insn
))
2754 jump
= "mov.w %O0,%1" "\n"
2763 jump
= "mov.l %O0,%1" "\n"
2766 jump
= "mov.l r0,@-r15" "\n"
2768 " mov.l @r0,%1" "\n"
2770 " mov.l @r15+,r0" "\n"
2774 jump
= "mov.l %O0,%1" "\n"
2777 /* If we have a scratch register available, use it. */
2778 if (NONJUMP_INSN_P ((prev
= prev_nonnote_insn (insn
)))
2779 && INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
2781 this_jmp
.reg
= SET_DEST (XVECEXP (PATTERN (prev
), 0, 0));
2782 if (REGNO (this_jmp
.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
2783 jump
= "mov.l r1,@-r15" "\n"
2785 " mov.l @r0,r1" "\n"
2787 " mov.l @r15+,r1" "\n"
2789 output_asm_insn (jump
, &this_jmp
.lab
);
2790 if (dbr_sequence_length ())
2791 print_slot (final_sequence
);
2793 output_asm_insn ("nop", 0);
2797 /* Output the delay slot insn first if any. */
2798 if (dbr_sequence_length ())
2799 print_slot (final_sequence
);
2801 this_jmp
.reg
= gen_rtx_REG (SImode
, 13);
2802 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2803 Fortunately, MACL is fixed and call-clobbered, and we never
2804 need its value across jumps, so save r13 in it instead of in
2807 output_asm_insn ("lds r13,macl", 0);
2809 output_asm_insn ("mov.l r13,@-r15", 0);
2810 output_asm_insn (jump
, &this_jmp
.lab
);
2812 output_asm_insn ("sts macl,r13", 0);
2814 output_asm_insn ("mov.l @r15+,r13", 0);
2816 if (far
&& flag_pic
&& TARGET_SH2
)
2818 braf_base_lab
= gen_label_rtx ();
2819 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
2820 CODE_LABEL_NUMBER (braf_base_lab
));
2823 output_asm_insn (".align 2", 0);
2824 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (this_jmp
.lab
));
2826 if (far
&& flag_pic
)
2829 this_jmp
.lab
= braf_base_lab
;
2830 output_asm_insn (".long %O2-%O0", &this_jmp
.lab
);
2833 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this_jmp
.lab
);
2837 /* Local label counter, used for constants in the pool and inside
2838 pattern branches. */
2839 static int lf
= 100;
2841 /* Output code for ordinary branches. */
2843 output_branch (int logic
, rtx_insn
*insn
, rtx
*operands
)
2845 switch (get_attr_length (insn
))
2848 /* This can happen if filling the delay slot has caused a forward
2849 branch to exceed its range (we could reverse it, but only
2850 when we know we won't overextend other branches; this should
2851 best be handled by relaxation).
2852 It can also happen when other condbranches hoist delay slot insn
2853 from their destination, thus leading to code size increase.
2854 But the branch will still be in the range -4092..+4098 bytes. */
2858 /* The call to print_slot will clobber the operands. */
2859 rtx op0
= operands
[0];
2861 /* If the instruction in the delay slot is annulled (true), then
2862 there is no delay slot where we can put it now. The only safe
2863 place for it is after the label. final will do that by default. */
2866 && ! INSN_ANNULLED_BRANCH_P (final_sequence
->insn (0))
2867 && get_attr_length (final_sequence
->insn (1)))
2869 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
2870 ASSEMBLER_DIALECT
? "/" : ".", label
);
2871 print_slot (final_sequence
);
2874 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
2876 output_asm_insn ("bra\t%l0", &op0
);
2877 fprintf (asm_out_file
, "\tnop\n");
2878 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2882 /* When relaxing, handle this like a short branch. The linker
2883 will fix it up if it still doesn't fit after relaxation. */
2885 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
2887 /* These are for SH2e, in which we have to account for the
2888 extra nop because of the hardware bug in annulled branches. */
2894 gcc_assert (!final_sequence
2895 || !(INSN_ANNULLED_BRANCH_P
2896 (XVECEXP (final_sequence
, 0, 0))));
2897 asm_fprintf (asm_out_file
, "b%s%ss\t%LLF%d\n",
2899 ASSEMBLER_DIALECT
? "/" : ".", label
);
2900 fprintf (asm_out_file
, "\tnop\n");
2901 output_asm_insn ("bra\t%l0", operands
);
2902 fprintf (asm_out_file
, "\tnop\n");
2903 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2907 /* When relaxing, fall through. */
2912 sprintf (buffer
, "b%s%ss\t%%l0",
2914 ASSEMBLER_DIALECT
? "/" : ".");
2915 output_asm_insn (buffer
, &operands
[0]);
2920 /* There should be no longer branches now - that would
2921 indicate that something has destroyed the branches set
2922 up in machine_dependent_reorg. */
2927 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2928 fill in operands 9 as a label to the successor insn.
2929 We try to use jump threading where possible.
2930 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2931 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2932 follow jmp and bt, if the address is in range. */
2934 output_branchy_insn (enum rtx_code code
, const char *templ
,
2935 rtx_insn
*insn
, rtx
*operands
)
2937 rtx_insn
*next_insn
= NEXT_INSN (insn
);
2939 if (next_insn
&& JUMP_P (next_insn
) && condjump_p (next_insn
))
2941 rtx src
= SET_SRC (PATTERN (next_insn
));
2942 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
2944 /* Following branch not taken */
2945 rtx_code_label
*lab
= gen_label_rtx ();
2946 emit_label_after (lab
, next_insn
);
2947 INSN_ADDRESSES_NEW (lab
,
2948 INSN_ADDRESSES (INSN_UID (next_insn
))
2949 + get_attr_length (next_insn
));
2955 int offset
= (branch_dest (next_insn
)
2956 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
2957 if (offset
>= -252 && offset
<= 258)
2959 if (GET_CODE (src
) == IF_THEN_ELSE
)
2961 src
= XEXP (src
, 1);
2967 rtx_code_label
*lab
= gen_label_rtx ();
2968 emit_label_after (lab
, insn
);
2969 INSN_ADDRESSES_NEW (lab
,
2970 INSN_ADDRESSES (INSN_UID (insn
))
2971 + get_attr_length (insn
));
2977 output_ieee_ccmpeq (rtx_insn
*insn
, rtx
*operands
)
2979 return output_branchy_insn (NE
, "bt %l9" "\n"
2984 /* Output the start of the assembler file. */
2986 sh_file_start (void)
2988 default_file_start ();
2991 /* We need to show the text section with the proper
2992 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2993 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2994 will complain. We can teach GAS specifically about the
2995 default attributes for our choice of text section, but
2996 then we would have to change GAS again if/when we change
2997 the text section name. */
2998 fprintf (asm_out_file
, "%s\n", TEXT_SECTION_ASM_OP
);
3000 /* Switch to the data section so that the coffsem symbol
3001 isn't in the text section. */
3002 switch_to_section (data_section
);
3004 if (TARGET_LITTLE_ENDIAN
)
3005 fputs ("\t.little\n", asm_out_file
);
3009 if (TARGET_SHCOMPACT
)
3010 fputs ("\t.mode\tSHcompact\n", asm_out_file
);
3011 else if (TARGET_SHMEDIA
)
3012 fprintf (asm_out_file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
3013 TARGET_SHMEDIA64
? 64 : 32);
3017 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
3019 unspec_caller_rtx_p (rtx pat
)
3024 split_const (pat
, &base
, &offset
);
3025 if (GET_CODE (base
) == UNSPEC
)
3027 if (XINT (base
, 1) == UNSPEC_CALLER
)
3029 for (i
= 0; i
< XVECLEN (base
, 0); i
++)
3030 if (unspec_caller_rtx_p (XVECEXP (base
, 0, i
)))
3036 /* Indicate that INSN cannot be duplicated. This is true for insn
3037 that generates a unique label. */
3039 sh_cannot_copy_insn_p (rtx_insn
*insn
)
3043 if (!reload_completed
|| !flag_pic
)
3046 if (!NONJUMP_INSN_P (insn
))
3048 if (asm_noperands (insn
) >= 0)
3051 pat
= PATTERN (insn
);
3052 if (GET_CODE (pat
) != SET
)
3054 pat
= SET_SRC (pat
);
3056 if (unspec_caller_rtx_p (pat
))
3062 /* Number of instructions used to make an arithmetic right shift by N. */
3063 static const char ashiftrt_insns
[] =
3064 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
3066 /* Description of a logical left or right shift, when expanded to a sequence
3068 Notice that one bit right shifts clobber the T bit. One bit left shifts
3069 are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */
3072 ASHL_CLOBBERS_T
= 1 << 0,
3073 LSHR_CLOBBERS_T
= 1 << 1
3076 struct ashl_lshr_sequence
3079 signed char amount
[6];
3083 static const struct ashl_lshr_sequence ashl_lshr_seq
[32] =
3085 { 0, { 0 }, 0 }, // 0
3086 { 1, { 1 }, LSHR_CLOBBERS_T
},
3088 { 2, { 2, 1 }, LSHR_CLOBBERS_T
},
3089 { 2, { 2, 2 }, 0 }, // 4
3090 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T
},
3091 { 3, { 2, 2, 2 }, 0 },
3092 { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3093 { 1, { 8 }, 0 }, // 8
3094 { 2, { 8, 1 }, LSHR_CLOBBERS_T
},
3096 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T
},
3097 { 3, { 8, 2, 2 }, 0 }, // 12
3098 { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3099 { 3, { 8, -2, 8 }, 0 },
3100 { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T
},
3101 { 1, { 16 }, 0 }, // 16
3102 { 2, { 16, 1 }, LSHR_CLOBBERS_T
},
3103 { 2, { 16, 2 }, 0 },
3104 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T
},
3105 { 3, { 16, 2, 2 }, 0 }, // 20
3106 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3107 { 3, { 16, -2, 8 }, 0 },
3108 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T
},
3109 { 2, { 16, 8 }, 0 }, // 24
3110 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T
},
3111 { 3, { 16, 8, 2 }, 0 },
3112 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T
},
3113 { 4, { 16, 8, 2, 2 }, 0 }, // 28
3114 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T
},
3115 { 3, { 16, -2, 16 }, 0 },
3117 /* For a right shift by 31 a 2 insn shll-movt sequence can be used.
3118 For a left shift by 31 a 2 insn and-rotl sequences can be used.
3119 However, the shift-and combiner code needs this entry here to be in
3120 terms of real shift insns. */
3121 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T
}
3124 /* Individual shift amounts for shift amounts < 16, up to three highmost
3125 bits might be clobbered. This is typically used when combined with some
3126 kind of sign or zero extension. */
3127 static const struct ashl_lshr_sequence ext_ashl_lshr_seq
[32] =
3129 { 0, { 0 }, 0 }, // 0
3130 { 1, { 1 }, LSHR_CLOBBERS_T
},
3132 { 2, { 2, 1 }, LSHR_CLOBBERS_T
},
3133 { 2, { 2, 2 }, 0 }, // 4
3134 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T
},
3135 { 2, { 8, -2 }, 0 },
3136 { 2, { 8, -1 }, ASHL_CLOBBERS_T
},
3137 { 1, { 8 }, 0 }, // 8
3138 { 2, { 8, 1 }, LSHR_CLOBBERS_T
},
3140 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T
},
3141 { 3, { 8, 2, 2 }, 0 }, // 12
3142 { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T
},
3143 { 2, { 16, -2 }, 0 },
3144 { 2, { 16, -1 }, ASHL_CLOBBERS_T
},
3145 { 1, { 16 }, 0 }, // 16
3146 { 2, { 16, 1 }, LSHR_CLOBBERS_T
},
3147 { 2, { 16, 2 }, 0 },
3148 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T
},
3149 { 3, { 16, 2, 2 }, 0 }, // 20
3150 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3151 { 3, { 16, -2, 8 }, 0 },
3152 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T
},
3153 { 2, { 16, 8 }, 0 }, // 24
3154 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T
},
3155 { 3, { 16, 8, 2 }, 0 },
3156 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T
},
3157 { 4, { 16, 8, 2, 2 }, 0 }, // 28
3158 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T
},
3159 { 3, { 16, -2, 16 }, 0 },
3160 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T
}
3163 /* Return true if a shift left consisting of 1/2/8/16 shift instructions
3164 will clobber the T bit. */
3166 sh_ashlsi_clobbers_t_reg_p (rtx shift_amount
)
3168 gcc_assert (CONST_INT_P (shift_amount
));
3170 const int shift_amount_i
= INTVAL (shift_amount
) & 31;
3172 /* Special case for shift count of 31: use and-rotl sequence. */
3173 if (shift_amount_i
== 31)
3176 return (ashl_lshr_seq
[shift_amount_i
].clobbers_t
3177 & ASHL_CLOBBERS_T
) != 0;
3180 /* Return true if a logical right shift consisting of 1/2/8/16 shift
3181 instructions will clobber the T bit. */
3183 sh_lshrsi_clobbers_t_reg_p (rtx shift_amount
)
3185 gcc_assert (CONST_INT_P (shift_amount
));
3187 const int shift_amount_i
= INTVAL (shift_amount
) & 31;
3189 /* Special case for shift count of 31: use shll-movt sequence. */
3190 if (shift_amount_i
== 31)
3193 return (ashl_lshr_seq
[shift_amount_i
].clobbers_t
3194 & LSHR_CLOBBERS_T
) != 0;
3197 /* Return true if it is potentially beneficial to use a dynamic shift
3198 instruction (shad / shar) instead of a combination of 1/2/8/16
3199 shift instructions for the specified shift count.
3200 If dynamic shifts are not available, always return false. */
3202 sh_dynamicalize_shift_p (rtx count
)
3204 gcc_assert (CONST_INT_P (count
));
3206 const int shift_amount_i
= INTVAL (count
) & 31;
3209 /* For left and right shifts, there are shorter 2 insn sequences for
3210 shift amounts of 31. */
3211 if (shift_amount_i
== 31)
3214 insn_count
= ashl_lshr_seq
[shift_amount_i
].insn_count
;
3216 return TARGET_DYNSHIFT
&& (insn_count
> 1 + SH_DYNAMIC_SHIFT_COST
);
3219 /* Assuming we have a value that has been sign-extended by at least one bit,
3220 can we use the ext_shift_amounts with the last shift turned to an
3221 arithmetic shift to shift it by N without data loss, and quicker than by
3223 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
3225 /* Return the cost of a shift. */
3234 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
3236 if (GET_MODE (x
) == DImode
3237 && CONST_INT_P (XEXP (x
, 1))
3238 && INTVAL (XEXP (x
, 1)) == 1)
3241 /* Everything else is invalid, because there is no pattern for it. */
3244 /* If shift by a non constant, then this will be expensive. */
3245 if (!CONST_INT_P (XEXP (x
, 1)))
3246 return SH_DYNAMIC_SHIFT_COST
;
3248 /* Otherwise, return the true cost in instructions. Cope with out of range
3249 shift counts more or less arbitrarily. */
3250 value
= INTVAL (XEXP (x
, 1)) & 31;
3252 if (GET_CODE (x
) == ASHIFTRT
)
3254 int cost
= ashiftrt_insns
[value
];
3255 /* If dynamic shifts are available and profitable in this case, then we
3256 put the constant in a reg and use shad. */
3257 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
3258 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
3262 return ashl_lshr_seq
[value
].insn_count
;
3265 /* Return the cost of an AND/XOR/IOR operation. */
3267 and_xor_ior_costs (rtx x
, int code
)
3269 /* On SH1-4 we have only max. SImode operations.
3270 Double the cost for modes > SImode. */
3271 const int cost_scale
= !TARGET_SHMEDIA
3272 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
3275 /* A logical operation with two registers is a single cycle
3277 if (!CONST_INT_P (XEXP (x
, 1)))
3278 return 1 * cost_scale
;
3280 int i
= INTVAL (XEXP (x
, 1));
3284 if (satisfies_constraint_I10 (XEXP (x
, 1))
3285 || satisfies_constraint_J16 (XEXP (x
, 1)))
3288 return 1 + rtx_cost (XEXP (x
, 1), GET_MODE (x
), AND
, 1, !optimize_size
);
3291 /* These constants are single cycle extu.[bw] instructions. */
3292 if ((i
== 0xff || i
== 0xffff) && code
== AND
)
3293 return 1 * cost_scale
;
3294 /* Constants that can be used in an instruction as an immediate are
3295 a single cycle, but this requires r0, so make it a little more
3297 if (CONST_OK_FOR_K08 (i
))
3298 return 2 * cost_scale
;
3299 /* Constants that can be loaded with a mov immediate need one more cycle.
3300 This case is probably unnecessary. */
3301 if (CONST_OK_FOR_I08 (i
))
3302 return 2 * cost_scale
;
3303 /* Any other constant requires an additional 2 cycle pc-relative load.
3304 This case is probably unnecessary. */
3305 return 3 * cost_scale
;
3308 /* Return the cost of an addition or a subtraction. */
3312 if (GET_MODE (x
) == SImode
)
3314 /* The addc or subc patterns will eventually become one or two
3315 instructions. Below are some costs for some of the patterns
3316 which combine would reject because the costs of the individual
3317 insns in the patterns are lower.
3319 FIXME: It would be much easier if we had something like insn cost
3320 attributes and the cost calculation machinery used those attributes
3321 in the first place. This would eliminate redundant recog-like C
3322 code to calculate costs of complex patterns. */
3323 rtx op0
= XEXP (x
, 0);
3324 rtx op1
= XEXP (x
, 1);
3326 if (GET_CODE (x
) == PLUS
)
3328 if (GET_CODE (op0
) == AND
3329 && XEXP (op0
, 1) == const1_rtx
3330 && (GET_CODE (op1
) == PLUS
3331 || (GET_CODE (op1
) == MULT
&& XEXP (op1
, 1) == const2_rtx
)))
3334 if (GET_CODE (op0
) == MULT
&& XEXP (op0
, 1) == const2_rtx
3335 && GET_CODE (op1
) == LSHIFTRT
3336 && CONST_INT_P (XEXP (op1
, 1)) && INTVAL (XEXP (op1
, 1)) == 31)
3339 /* Let's assume that adding the result of an insns that stores into
3340 the T bit is cheap. */
3341 if (treg_set_expr (op1
, SImode
))
3343 if (treg_set_expr (op0
, SImode
))
3347 /* On SH1-4 we have only max. SImode operations.
3348 Double the cost for modes > SImode. */
3349 const int cost_scale
= !TARGET_SHMEDIA
3350 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
3353 /* Adding a register is a single cycle insn. */
3354 if (REG_P (XEXP (x
, 1))
3355 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
3356 return 1 * cost_scale
;
3358 /* Likewise for small constants. */
3359 if (CONST_INT_P (XEXP (x
, 1))
3360 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
3361 return 1 * cost_scale
;
3364 switch (GET_CODE (XEXP (x
, 1)))
3369 return TARGET_SHMEDIA64
? 5 : 3;
3372 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1))))
3374 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1)) >> 16))
3376 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
3384 /* Any other constant requires a 2 cycle pc-relative load plus an
3386 return 3 * cost_scale
;
3389 /* Return the cost of a multiply. */
3391 multcosts (rtx x ATTRIBUTE_UNUSED
)
3393 if (sh_multcost
>= 0)
3396 /* ??? We have a mul insn, but it has a latency of three, and doesn't
3397 accept constants. Ideally, we would use a cost of one or two and
3398 add the cost of the operand, but disregard the latter when inside loops
3399 and loop invariant code motion is still to follow.
3400 Using a multiply first and splitting it later if it's a loss
3401 doesn't work because of different sign / zero extension semantics
3402 of multiplies vs. shifts. */
3403 return optimize_size
? 2 : 3;
3407 /* We have a mul insn, so we can never take more than the mul and the
3408 read of the mac reg, but count more because of the latency and extra
3415 /* If we're aiming at small code, then just count the number of
3416 insns in a multiply call sequence. */
3420 /* Otherwise count all the insns in the routine we'd be calling too. */
3424 /* Compute a (partial) cost for rtx X. Return true if the complete
3425 cost has been computed, and false if subexpressions should be
3426 scanned. In either case, *TOTAL contains the cost result. */
3428 sh_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
3429 int opno ATTRIBUTE_UNUSED
,
3430 int *total
, bool speed ATTRIBUTE_UNUSED
)
3432 int code
= GET_CODE (x
);
3436 /* The lower-subreg pass decides whether to split multi-word regs
3437 into individual regs by looking at the cost for a SET of certain
3438 modes with the following patterns:
3440 (set (reg) (const_int 0))
3441 On machines that support vector-move operations a multi-word move
3442 is the same cost as individual reg move. On SH there is no
3443 vector-move, so we have to provide the correct cost in the number
3444 of move insns to load/store the reg of the mode in question. */
3446 if (register_operand (SET_DEST (x
), VOIDmode
)
3447 && (register_operand (SET_SRC (x
), VOIDmode
)
3448 || satisfies_constraint_Z (SET_SRC (x
))))
3450 const machine_mode mode
= GET_MODE (SET_DEST (x
));
3451 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
)
3452 / mov_insn_size (mode
, TARGET_SH2A
));
3457 /* The cost of a mem access is mainly the cost of the address mode. */
3459 *total
= sh_address_cost (XEXP (x
, 0), GET_MODE (x
), MEM_ADDR_SPACE (x
),
3464 /* This case is required for the if_then_else negc pattern. */
3465 if (treg_set_expr (XEXP (x
, 0), SImode
))
3467 *total
= COSTS_N_INSNS (1);
3473 /* Zero extracts of single bits are usually combine patterns for the
3476 if (GET_CODE (XEXP (x
, 0)) == XOR
3477 && arith_reg_operand (XEXP (XEXP (x
, 0), 0), VOIDmode
)
3478 && XEXP (x
, 1) == const1_rtx
3479 && CONST_INT_P (XEXP (x
, 2))
3480 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3481 /* Check that the xor constaint overlaps with the extracted bit. */
3482 && (INTVAL (XEXP (XEXP (x
, 0), 1)) & (1LL << INTVAL (XEXP (x
, 2)))))
3484 *total
= 1; //COSTS_N_INSNS (1);
3489 /* The cost of a sign or zero extend depends on whether the source is a
3490 reg or a mem. In case of a mem take the address into acount. */
3492 if (arith_reg_operand (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
3494 *total
= COSTS_N_INSNS (1);
3497 if (MEM_P (XEXP (x
, 0)))
3499 *total
= sh_address_cost (XEXP (XEXP (x
, 0), 0),
3500 GET_MODE (XEXP (x
, 0)),
3501 MEM_ADDR_SPACE (XEXP (x
, 0)), true);
3507 if (arith_reg_operand (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
3509 *total
= COSTS_N_INSNS (1);
3512 else if (TARGET_SH2A
&& MEM_P (XEXP (x
, 0))
3513 && (GET_MODE (XEXP (x
, 0)) == QImode
3514 || GET_MODE (XEXP (x
, 0)) == HImode
))
3516 /* Handle SH2A's movu.b and movu.w insn. */
3517 *total
= sh_address_cost (XEXP (XEXP (x
, 0), 0),
3518 GET_MODE (XEXP (x
, 0)),
3519 MEM_ADDR_SPACE (XEXP (x
, 0)), true);
3524 /* mems for SFmode and DFmode can be inside a parallel due to
3525 the way the fpscr is handled. */
3527 for (int i
= 0; i
< XVECLEN (x
, 0); i
++)
3529 rtx xx
= XVECEXP (x
, 0, i
);
3530 if (GET_CODE (xx
) == SET
&& MEM_P (XEXP (xx
, 0)))
3532 *total
= sh_address_cost (XEXP (XEXP (xx
, 0), 0),
3533 GET_MODE (XEXP (xx
, 0)),
3534 MEM_ADDR_SPACE (XEXP (xx
, 0)), true);
3537 if (GET_CODE (xx
) == SET
&& MEM_P (XEXP (xx
, 1)))
3539 *total
= sh_address_cost (XEXP (XEXP (xx
, 1), 0),
3540 GET_MODE (XEXP (xx
, 1)),
3541 MEM_ADDR_SPACE (XEXP (xx
, 1)), true);
3546 if (sh_1el_vec (x
, VOIDmode
))
3547 *total
= outer_code
!= SET
;
3548 else if (sh_rep_vec (x
, VOIDmode
))
3549 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3550 + (outer_code
!= SET
));
3552 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3558 if (INTVAL (x
) == 0)
3560 else if (outer_code
== AND
&& and_operand ((x
), DImode
))
3562 else if ((outer_code
== IOR
|| outer_code
== XOR
3563 || outer_code
== PLUS
)
3564 && CONST_OK_FOR_I10 (INTVAL (x
)))
3566 else if (CONST_OK_FOR_I16 (INTVAL (x
)))
3567 *total
= COSTS_N_INSNS (outer_code
!= SET
);
3568 else if (CONST_OK_FOR_I16 (INTVAL (x
) >> 16))
3569 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 1);
3570 else if (CONST_OK_FOR_I16 ((INTVAL (x
) >> 16) >> 16))
3571 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 2);
3573 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 3);
3576 if (CONST_OK_FOR_I08 (INTVAL (x
)))
3578 else if ((outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
3579 && CONST_OK_FOR_K08 (INTVAL (x
)))
3581 /* prepare_cmp_insn will force costly constants int registers before
3582 the cbranch[sd]i4 patterns can see them, so preserve potentially
3583 interesting ones not covered by I08 above. */
3584 else if (outer_code
== COMPARE
3585 && ((unsigned HOST_WIDE_INT
) INTVAL (x
)
3586 == (unsigned HOST_WIDE_INT
) 0x7fffffff + 1
3587 || INTVAL (x
) == 0x7fffffff
3588 || INTVAL (x
) == 0x80 || INTVAL (x
) == -0x81))
3595 /* An and with a constant compared against zero is
3596 most likely going to be a TST #imm, R0 instruction.
3597 Notice that this does not catch the zero_extract variants from
3599 if (XEXP (x
, 1) == const0_rtx
3600 && (GET_CODE (XEXP (x
, 0)) == AND
3601 || (SUBREG_P (XEXP (x
, 0))
3602 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == AND
)))
3608 else if (XEXP (x
, 1) == const0_rtx
3609 && GET_CODE (XEXP (x
, 0)) == AND
3610 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3611 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == ASHIFT
3612 && arith_reg_operand (XEXP (XEXP (XEXP (x
, 0), 0), 0), SImode
)
3613 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3623 /* This is most likely a clips.b or clips.w insn that is being made up
3626 && (GET_CODE (XEXP (x
, 0)) == SMAX
|| GET_CODE (XEXP (x
, 0)) == SMIN
)
3627 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3628 && REG_P (XEXP (XEXP (x
, 0), 0))
3629 && CONST_INT_P (XEXP (x
, 1)))
3631 *total
= COSTS_N_INSNS (1);
3640 if (TARGET_SHMEDIA64
)
3641 *total
= COSTS_N_INSNS (4);
3642 else if (TARGET_SHMEDIA32
)
3643 *total
= COSTS_N_INSNS (2);
3650 *total
= COSTS_N_INSNS (4);
3651 /* prepare_cmp_insn will force costly constants int registers before
3652 the cbranchdi4 pattern can see them, so preserve potentially
3653 interesting ones. */
3654 else if (outer_code
== COMPARE
&& GET_MODE (x
) == DImode
)
3661 /* FIXME: This looks broken. Only the last statement has any effect.
3662 Probably this could be folded with the PARALLEL case? */
3663 if (x
== CONST0_RTX (GET_MODE (x
)))
3665 else if (sh_1el_vec (x
, VOIDmode
))
3666 *total
= outer_code
!= SET
;
3667 if (sh_rep_vec (x
, VOIDmode
))
3668 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3669 + (outer_code
!= SET
));
3670 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3675 *total
= COSTS_N_INSNS (addsubcosts (x
));
3679 /* Check for (and (not (reg)) (const_int 1)) which is a tst insn. */
3680 if (GET_CODE (XEXP (x
, 0)) == NOT
&& XEXP (x
, 1) == const1_rtx
)
3682 *total
= COSTS_N_INSNS (1);
3689 *total
= COSTS_N_INSNS (and_xor_ior_costs (x
, code
));
3693 *total
= COSTS_N_INSNS (multcosts (x
));
3698 /* div0s sign comparison. */
3699 if (GET_CODE (XEXP (x
, 0)) == XOR
3700 && REG_P ((XEXP (XEXP (x
, 0), 0)))
3701 && REG_P ((XEXP (XEXP (x
, 0), 1)))
3702 && satisfies_constraint_Z (XEXP (x
, 1)))
3704 *total
= COSTS_N_INSNS (1);
3711 /* div0s sign comparison. */
3712 if (GET_CODE (XEXP (x
, 0)) == XOR
3713 && REG_P ((XEXP (XEXP (x
, 0), 0)))
3714 && REG_P ((XEXP (XEXP (x
, 0), 1)))
3715 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 31)
3717 *total
= COSTS_N_INSNS (1);
3720 /* Fall through to shiftcosts. */
3724 int cost
= shiftcosts (x
);
3727 *total
= COSTS_N_INSNS (cost
);
3735 *total
= COSTS_N_INSNS (20);
3748 /* Determine the size of the fundamental move insn that will be used
3749 for the specified mode. */
3751 mov_insn_size (machine_mode mode
, bool consider_sh2a
)
3753 const int mode_sz
= GET_MODE_SIZE (mode
);
3755 if ((consider_sh2a
&& TARGET_SH2A_DOUBLE
&& mode
== DFmode
)
3756 || (TARGET_FMOVD
&& mode
== DFmode
))
3760 /* The max. available mode for actual move insns is SImode.
3761 Larger accesses will be split into multiple loads/stores. */
3762 const int max_mov_sz
= GET_MODE_SIZE (SImode
);
3763 return mode_sz
>= max_mov_sz
? max_mov_sz
: mode_sz
;
3767 /* Determine the maximum possible displacement for a move insn for the
3770 sh_max_mov_insn_displacement (machine_mode mode
, bool consider_sh2a
)
3772 /* The 4 byte displacement move insns are the same as the 2 byte
3773 versions but take a 12 bit displacement. All we need to do is to
3774 scale the max. displacement value accordingly. */
3775 const int disp_scale
= consider_sh2a
? (4095 / 15) : 1;
3777 /* SH2A supports FPU move insns with 12 bit displacements.
3778 Other variants to do not support any kind of displacements for
3780 if (! consider_sh2a
&& TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3784 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3785 const int mode_sz
= GET_MODE_SIZE (mode
);
3786 int r
= 15 * mov_insn_sz
* disp_scale
;
3788 /* If the mov insn will be split into multiple loads/stores, the
3789 maximum possible displacement is a bit smaller. */
3790 if (mode_sz
> mov_insn_sz
)
3791 r
-= mode_sz
- mov_insn_sz
;
3796 /* Determine the alignment mask for a move insn of the
3799 mov_insn_alignment_mask (machine_mode mode
, bool consider_sh2a
)
3801 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3802 return mov_insn_sz
> 0 ? (mov_insn_sz
- 1) : 0;
3805 /* Return the displacement value of a displacement address. */
3807 sh_disp_addr_displacement (rtx x
)
3809 gcc_assert (satisfies_constraint_Sdd (x
));
3810 return INTVAL (XEXP (XEXP (x
, 0), 1));
3813 /* Compute the cost of an address. */
3815 sh_address_cost (rtx x
, machine_mode mode
,
3816 addr_space_t as ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
3818 /* 'GBR + 0'. Account one more because of R0 restriction. */
3819 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
3822 /* Simple reg, post-inc, pre-dec addressing. */
3823 if (REG_P (x
) || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
3826 /* 'reg + disp' addressing. */
3827 if (GET_CODE (x
) == PLUS
3828 && REG_P (XEXP (x
, 0)) && CONST_INT_P (XEXP (x
, 1)))
3830 /* 'GBR + disp'. Account one more because of R0 restriction. */
3831 if (REGNO (XEXP (x
, 0)) == GBR_REG
3832 && gbr_displacement (XEXP (x
, 1), mode
))
3835 const HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
3840 /* The displacement would fit into a 2 byte move insn.
3841 HImode and QImode loads/stores with displacement put pressure on
3842 R0 which will most likely require another reg copy. Thus account
3843 a higher cost for that. */
3844 if (offset
> 0 && offset
<= sh_max_mov_insn_displacement (mode
, false))
3845 return (mode
== HImode
|| mode
== QImode
) ? 2 : 1;
3847 /* The displacement would fit into a 4 byte move insn (SH2A). */
3849 && offset
> 0 && offset
<= sh_max_mov_insn_displacement (mode
, true))
3852 /* The displacement is probably out of range and will require extra
3857 /* 'reg + reg' addressing. Account a slightly higher cost because of
3858 increased pressure on R0. */
3859 if (GET_CODE (x
) == PLUS
&& ! CONSTANT_P (XEXP (x
, 1))
3860 && ! TARGET_SHMEDIA
)
3863 /* Not sure what it is - probably expensive. */
3867 /* Code to expand a shift. */
3869 gen_ashift (int type
, int n
, rtx reg
)
3873 /* Negative values here come from the shift_amounts array. */
3883 n_rtx
= GEN_INT (n
);
3884 gcc_assert (satisfies_constraint_P27 (n_rtx
));
3889 emit_insn (gen_ashrsi3_k (reg
, reg
, n_rtx
));
3893 emit_insn (gen_shlr (reg
, reg
));
3895 emit_insn (gen_lshrsi3_k (reg
, reg
, n_rtx
));
3898 emit_insn (gen_ashlsi3_k (reg
, reg
, n_rtx
));
3905 /* Code to expand a HImode shift. */
3907 gen_ashift_hi (int type
, int n
, rtx reg
)
3909 /* Negative values here come from the shift_amounts array. */
3923 /* We don't have HImode right shift operations because using the
3924 ordinary 32 bit shift instructions for that doesn't generate proper
3925 zero/sign extension.
3926 gen_ashift_hi is only called in contexts where we know that the
3927 sign extension works out correctly. */
3930 if (GET_CODE (reg
) == SUBREG
)
3932 offset
= SUBREG_BYTE (reg
);
3933 reg
= SUBREG_REG (reg
);
3935 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
3939 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
3944 /* Output RTL to split a constant shift into its component SH constant
3945 shift instructions. */
3947 gen_shifty_op (int code
, rtx
*operands
)
3949 int value
= INTVAL (operands
[2]);
3952 /* Truncate the shift count in case it is out of bounds. */
3957 if (code
== LSHIFTRT
)
3959 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
3960 emit_insn (gen_movt (operands
[0], get_t_reg_rtx ()));
3963 else if (code
== ASHIFT
)
3965 /* There is a two instruction sequence for 31 bit left shifts,
3966 but it requires r0. */
3967 if (REG_P (operands
[0]) && REGNO (operands
[0]) == 0)
3969 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
3970 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
3975 else if (value
== 0)
3977 /* This can happen even when optimizing, if there were subregs before
3978 reload. Don't output a nop here, as this is never optimized away;
3979 use a no-op move instead. */
3980 emit_insn (gen_rtx_SET (operands
[0], operands
[0]));
3984 max
= ashl_lshr_seq
[value
].insn_count
;
3985 for (i
= 0; i
< max
; i
++)
3986 gen_ashift (code
, ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3989 /* Same as gen_shifty_op, but optimized for values where the topmost bits
3992 gen_shifty_hi_op (int code
, rtx
*operands
)
3994 int value
= INTVAL (operands
[2]);
3996 void (*gen_fun
) (int, int, rtx
);
3998 /* This operation is used by and_shl for SImode values with a few
3999 high bits known to be cleared. */
4003 emit_insn (gen_nop ());
4007 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
4010 max
= ext_ashl_lshr_seq
[value
].insn_count
;
4011 for (i
= 0; i
< max
; i
++)
4012 gen_fun (code
, ext_ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
4015 /* When shifting right, emit the shifts in reverse order, so that
4016 solitary negative values come first. */
4017 for (i
= ext_ashl_lshr_seq
[value
].insn_count
- 1; i
>= 0; i
--)
4018 gen_fun (code
, ext_ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
4021 /* Output RTL for an arithmetic right shift.
4022 ??? Rewrite to use super-optimizer sequences. */
4024 expand_ashiftrt (rtx
*operands
)
4030 if (TARGET_DYNSHIFT
)
4032 if (!CONST_INT_P (operands
[2]))
4034 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
4035 emit_insn (gen_negsi2 (count
, count
));
4036 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
4039 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
4040 > 1 + SH_DYNAMIC_SHIFT_COST
)
4043 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
4044 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
4048 if (!CONST_INT_P (operands
[2]))
4051 value
= INTVAL (operands
[2]) & 31;
4055 /* If we are called from abs expansion, arrange things so that we
4056 we can use a single MT instruction that doesn't clobber the source,
4057 if LICM can hoist out the load of the constant zero. */
4058 if (currently_expanding_to_rtl
)
4060 emit_insn (gen_cmpgtsi_t (force_reg (SImode
, CONST0_RTX (SImode
)),
4062 emit_insn (gen_mov_neg_si_t (operands
[0], get_t_reg_rtx ()));
4065 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
4068 else if (value
>= 16 && value
<= 19)
4070 wrk
= gen_reg_rtx (SImode
);
4071 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
4074 gen_ashift (ASHIFTRT
, 1, wrk
);
4075 emit_move_insn (operands
[0], wrk
);
4078 /* Expand a short sequence inline, longer call a magic routine. */
4079 else if (value
<= 5)
4081 wrk
= gen_reg_rtx (SImode
);
4082 emit_move_insn (wrk
, operands
[1]);
4084 gen_ashift (ASHIFTRT
, 1, wrk
);
4085 emit_move_insn (operands
[0], wrk
);
4089 wrk
= gen_reg_rtx (Pmode
);
4091 /* Load the value into an arg reg and call a helper. */
4092 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
4093 sprintf (func
, "__ashiftrt_r4_%d", value
);
4094 function_symbol (wrk
, func
, SFUNC_STATIC
);
4095 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
4096 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
4100 /* Try to find a good way to implement the combiner pattern
4101 [(set (match_operand:SI 0 "register_operand" "r")
4102 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4103 (match_operand:SI 2 "const_int_operand" "n"))
4104 (match_operand:SI 3 "const_int_operand" "n"))) .
4105 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
4106 return 0 for simple right / left or left/right shift combination.
4107 return 1 for a combination of shifts with zero_extend.
4108 return 2 for a combination of shifts with an AND that needs r0.
4109 return 3 for a combination of shifts with an AND that needs an extra
4110 scratch register, when the three highmost bits of the AND mask are clear.
4111 return 4 for a combination of shifts with an AND that needs an extra
4112 scratch register, when any of the three highmost bits of the AND mask
4114 If ATTRP is set, store an initial right shift width in ATTRP[0],
4115 and the instruction length in ATTRP[1] . These values are not valid
4117 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
4118 shift_amounts for the last shift value that is to be used before the
4121 shl_and_kind (rtx left_rtx
, rtx mask_rtx
, int *attrp
)
4123 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
4124 int left
= INTVAL (left_rtx
), right
;
4126 int cost
, best_cost
= 10000;
4127 int best_right
= 0, best_len
= 0;
4131 if (left
< 0 || left
> 31)
4133 if (CONST_INT_P (mask_rtx
))
4134 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
4136 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
4137 /* Can this be expressed as a right shift / left shift pair? */
4138 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
4139 right
= exact_log2 (lsb
);
4140 mask2
= ~(mask
+ lsb
- 1);
4141 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
4142 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
4144 best_cost
= ashl_lshr_seq
[right
].insn_count
4145 + ashl_lshr_seq
[right
+ left
].insn_count
;
4146 /* mask has no trailing zeroes <==> ! right */
4147 else if (! right
&& mask2
== ~(lsb2
- 1))
4149 int late_right
= exact_log2 (lsb2
);
4150 best_cost
= ashl_lshr_seq
[left
+ late_right
].insn_count
4151 + ashl_lshr_seq
[late_right
].insn_count
;
4153 /* Try to use zero extend. */
4154 if (mask2
== ~(lsb2
- 1))
4158 for (width
= 8; width
<= 16; width
+= 8)
4160 /* Can we zero-extend right away? */
4161 if (lsb2
== (unsigned HOST_WIDE_INT
) 1 << width
)
4163 cost
= 1 + ext_ashl_lshr_seq
[right
].insn_count
4164 + ext_ashl_lshr_seq
[left
+ right
].insn_count
;
4165 if (cost
< best_cost
)
4176 /* ??? Could try to put zero extend into initial right shift,
4177 or even shift a bit left before the right shift. */
4178 /* Determine value of first part of left shift, to get to the
4179 zero extend cut-off point. */
4180 first
= width
- exact_log2 (lsb2
) + right
;
4181 if (first
>= 0 && right
+ left
- first
>= 0)
4183 cost
= ext_ashl_lshr_seq
[right
].insn_count
4184 + ext_ashl_lshr_seq
[first
].insn_count
+ 1
4185 + ext_ashl_lshr_seq
[right
+ left
- first
].insn_count
;
4187 if (cost
< best_cost
)
4199 /* Try to use r0 AND pattern */
4200 for (i
= 0; i
<= 2; i
++)
4204 if (! CONST_OK_FOR_K08 (mask
>> i
))
4206 cost
= (i
!= 0) + 2 + ext_ashl_lshr_seq
[left
+ i
].insn_count
;
4207 if (cost
< best_cost
)
4212 best_len
= cost
- 1;
4215 /* Try to use a scratch register to hold the AND operand. */
4216 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
) 3 << 30)) == 0;
4217 for (i
= 0; i
<= 2; i
++)
4221 cost
= (i
!= 0) + (CONST_OK_FOR_I08 (mask
>> i
) ? 2 : 3)
4224 : ashl_lshr_seq
)[left
+ i
].insn_count
;
4225 if (cost
< best_cost
)
4230 best_len
= cost
- 1 - ! CONST_OK_FOR_I08 (mask
>> i
);
4236 attrp
[0] = best_right
;
4237 attrp
[1] = best_len
;
4242 /* This is used in length attributes of the unnamed instructions
4243 corresponding to shl_and_kind return values of 1 and 2. */
4245 shl_and_length (rtx insn
)
4247 rtx set_src
, left_rtx
, mask_rtx
;
4250 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4251 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
4252 mask_rtx
= XEXP (set_src
, 1);
4253 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
4254 return attributes
[1];
4257 /* This is used in length attribute of the and_shl_scratch instruction. */
4259 shl_and_scr_length (rtx insn
)
4261 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4262 int len
= ashl_lshr_seq
[INTVAL (XEXP (set_src
, 1)) & 31].insn_count
;
4263 rtx op
= XEXP (set_src
, 0);
4264 len
+= ashl_lshr_seq
[INTVAL (XEXP (op
, 1)) & 31].insn_count
+ 1;
4265 op
= XEXP (XEXP (op
, 0), 0);
4266 return len
+ ashl_lshr_seq
[INTVAL (XEXP (op
, 1)) & 31].insn_count
;
4269 /* Generate rtl for instructions for which shl_and_kind advised a particular
4270 method of generating them, i.e. returned zero. */
4272 gen_shl_and (rtx dest
, rtx left_rtx
, rtx mask_rtx
, rtx source
)
4275 unsigned HOST_WIDE_INT mask
;
4276 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
4277 int right
, total_shift
;
4278 void (*shift_gen_fun
) (int, rtx
*) = gen_shifty_hi_op
;
4280 right
= attributes
[0];
4281 total_shift
= INTVAL (left_rtx
) + right
;
4282 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
4289 int first
= attributes
[2];
4294 emit_insn ((mask
<< right
) <= 0xff
4295 ? gen_zero_extendqisi2 (dest
,
4296 gen_lowpart (QImode
, source
))
4297 : gen_zero_extendhisi2 (dest
,
4298 gen_lowpart (HImode
, source
)));
4302 emit_insn (gen_movsi (dest
, source
));
4306 operands
[2] = GEN_INT (right
);
4307 gen_shifty_hi_op (LSHIFTRT
, operands
);
4311 operands
[2] = GEN_INT (first
);
4312 gen_shifty_hi_op (ASHIFT
, operands
);
4313 total_shift
-= first
;
4317 emit_insn (mask
<= 0xff
4318 ? gen_zero_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4319 : gen_zero_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4320 if (total_shift
> 0)
4322 operands
[2] = GEN_INT (total_shift
);
4323 gen_shifty_hi_op (ASHIFT
, operands
);
4328 shift_gen_fun
= gen_shifty_op
;
4330 /* If the topmost bit that matters is set, set the topmost bits
4331 that don't matter. This way, we might be able to get a shorter
4333 if (mask
& ((HOST_WIDE_INT
) 1 << (31 - total_shift
)))
4334 mask
|= (HOST_WIDE_INT
) ~0 << (31 - total_shift
);
4336 /* Don't expand fine-grained when combining, because that will
4337 make the pattern fail. */
4338 if (currently_expanding_to_rtl
4339 || reload_in_progress
|| reload_completed
)
4343 /* Cases 3 and 4 should be handled by this split
4344 only while combining */
4345 gcc_assert (kind
<= 2);
4348 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
4351 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
4356 operands
[2] = GEN_INT (total_shift
);
4357 shift_gen_fun (ASHIFT
, operands
);
4364 if (kind
!= 4 && total_shift
< 16)
4366 neg
= -ext_ashl_lshr_seq
[total_shift
].amount
[1];
4368 neg
-= ext_ashl_lshr_seq
[total_shift
].amount
[2];
4372 emit_insn (gen_and_shl_scratch (dest
, source
,
4375 GEN_INT (total_shift
+ neg
),
4377 emit_insn (gen_movsi (dest
, dest
));
4384 /* Try to find a good way to implement the combiner pattern
4385 [(set (match_operand:SI 0 "register_operand" "=r")
4386 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4387 (match_operand:SI 2 "const_int_operand" "n")
4388 (match_operand:SI 3 "const_int_operand" "n")
4390 (clobber (reg:SI T_REG))]
4391 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
4392 return 0 for simple left / right shift combination.
4393 return 1 for left shift / 8 bit sign extend / left shift.
4394 return 2 for left shift / 16 bit sign extend / left shift.
4395 return 3 for left shift / 8 bit sign extend / shift / sign extend.
4396 return 4 for left shift / 16 bit sign extend / shift / sign extend.
4397 return 5 for left shift / 16 bit sign extend / right shift
4398 return 6 for < 8 bit sign extend / left shift.
4399 return 7 for < 8 bit sign extend / left shift / single right shift.
4400 If COSTP is nonzero, assign the calculated cost to *COSTP. */
4402 shl_sext_kind (rtx left_rtx
, rtx size_rtx
, int *costp
)
4404 int left
, size
, insize
, ext
;
4405 int cost
= 0, best_cost
;
4408 left
= INTVAL (left_rtx
);
4409 size
= INTVAL (size_rtx
);
4410 insize
= size
- left
;
4411 gcc_assert (insize
> 0);
4412 /* Default to left / right shift. */
4414 best_cost
= ashl_lshr_seq
[32 - insize
].insn_count
4415 + ashl_lshr_seq
[32 - size
].insn_count
;
4418 /* 16 bit shift / sign extend / 16 bit shift */
4419 cost
= ashl_lshr_seq
[16 - insize
].insn_count
+ 1
4420 + ashl_lshr_seq
[16 - size
].insn_count
;
4421 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
4422 below, by alternative 3 or something even better. */
4423 if (cost
< best_cost
)
4429 /* Try a plain sign extend between two shifts. */
4430 for (ext
= 16; ext
>= insize
; ext
-= 8)
4434 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
+ 1
4435 + ashl_lshr_seq
[size
- ext
].insn_count
;
4436 if (cost
< best_cost
)
4438 kind
= ext
/ (unsigned) 8;
4442 /* Check if we can do a sloppy shift with a final signed shift
4443 restoring the sign. */
4444 if (EXT_SHIFT_SIGNED (size
- ext
))
4445 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
4446 + ext_ashl_lshr_seq
[size
- ext
].insn_count
+ 1;
4447 /* If not, maybe it's still cheaper to do the second shift sloppy,
4448 and do a final sign extend? */
4449 else if (size
<= 16)
4450 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
+ 1
4451 + ext_ashl_lshr_seq
[size
> ext
? size
- ext
: ext
- size
].insn_count
4455 if (cost
< best_cost
)
4457 kind
= ext
/ (unsigned) 8 + 2;
4461 /* Check if we can sign extend in r0 */
4464 cost
= 3 + ashl_lshr_seq
[left
].insn_count
;
4465 if (cost
< best_cost
)
4470 /* Try the same with a final signed shift. */
4473 cost
= 3 + ext_ashl_lshr_seq
[left
+ 1].insn_count
+ 1;
4474 if (cost
< best_cost
)
4481 if (TARGET_DYNSHIFT
)
4483 /* Try to use a dynamic shift. */
4484 cost
= ashl_lshr_seq
[32 - insize
].insn_count
+ 1 + SH_DYNAMIC_SHIFT_COST
;
4485 if (cost
< best_cost
)
4496 /* Function to be used in the length attribute of the instructions
4497 implementing this pattern. */
4499 shl_sext_length (rtx insn
)
4501 rtx set_src
, left_rtx
, size_rtx
;
4504 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4505 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
4506 size_rtx
= XEXP (set_src
, 1);
4507 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
4511 /* Generate rtl for this pattern */
4513 gen_shl_sext (rtx dest
, rtx left_rtx
, rtx size_rtx
, rtx source
)
4516 int left
, size
, insize
, cost
;
4519 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
4520 left
= INTVAL (left_rtx
);
4521 size
= INTVAL (size_rtx
);
4522 insize
= size
- left
;
4530 int ext
= kind
& 1 ? 8 : 16;
4531 int shift2
= size
- ext
;
4533 /* Don't expand fine-grained when combining, because that will
4534 make the pattern fail. */
4535 if (! currently_expanding_to_rtl
4536 && ! reload_in_progress
&& ! reload_completed
)
4538 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4539 emit_insn (gen_movsi (dest
, source
));
4543 emit_insn (gen_movsi (dest
, source
));
4547 operands
[2] = GEN_INT (ext
- insize
);
4548 gen_shifty_hi_op (ASHIFT
, operands
);
4551 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4552 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4557 operands
[2] = GEN_INT (shift2
);
4558 gen_shifty_op (ASHIFT
, operands
);
4565 if (EXT_SHIFT_SIGNED (shift2
))
4567 operands
[2] = GEN_INT (shift2
+ 1);
4568 gen_shifty_op (ASHIFT
, operands
);
4569 operands
[2] = const1_rtx
;
4570 gen_shifty_op (ASHIFTRT
, operands
);
4573 operands
[2] = GEN_INT (shift2
);
4574 gen_shifty_hi_op (ASHIFT
, operands
);
4578 operands
[2] = GEN_INT (-shift2
);
4579 gen_shifty_hi_op (LSHIFTRT
, operands
);
4581 emit_insn (size
<= 8
4582 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4583 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4590 if (! currently_expanding_to_rtl
4591 && ! reload_in_progress
&& ! reload_completed
)
4592 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4596 operands
[2] = GEN_INT (16 - insize
);
4597 gen_shifty_hi_op (ASHIFT
, operands
);
4598 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4600 /* Don't use gen_ashrsi3 because it generates new pseudos. */
4602 gen_ashift (ASHIFTRT
, 1, dest
);
4607 /* Don't expand fine-grained when combining, because that will
4608 make the pattern fail. */
4609 if (! currently_expanding_to_rtl
4610 && ! reload_in_progress
&& ! reload_completed
)
4612 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4613 emit_insn (gen_movsi (dest
, source
));
4616 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
4617 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
4618 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
4620 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
4621 gen_shifty_op (ASHIFT
, operands
);
4623 emit_insn (gen_ashrsi3_k (dest
, dest
, const1_rtx
));
4631 /* Prefix a symbol_ref name with "datalabel". */
4633 gen_datalabel_ref (rtx sym
)
4637 if (GET_CODE (sym
) == LABEL_REF
)
4638 return gen_rtx_CONST (GET_MODE (sym
),
4639 gen_rtx_UNSPEC (GET_MODE (sym
),
4643 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
);
4645 str
= XSTR (sym
, 0);
4646 /* Share all SYMBOL_REF strings with the same value - that is important
4648 str
= IDENTIFIER_POINTER (get_identifier (str
));
4649 XSTR (sym
, 0) = str
;
4655 typedef struct label_ref_list_d
4657 rtx_code_label
*label
;
4658 struct label_ref_list_d
*next
;
4659 } *label_ref_list_t
;
4661 static object_allocator
<label_ref_list_d
> label_ref_list_d_pool
4662 ("label references list", 30);
4664 /* The SH cannot load a large constant into a register, constants have to
4665 come from a pc relative load. The reference of a pc relative load
4666 instruction must be less than 1k in front of the instruction. This
4667 means that we often have to dump a constant inside a function, and
4668 generate code to branch around it.
4670 It is important to minimize this, since the branches will slow things
4671 down and make things bigger.
4673 Worst case code looks like:
4691 We fix this by performing a scan before scheduling, which notices which
4692 instructions need to have their operands fetched from the constant table
4693 and builds the table.
4697 scan, find an instruction which needs a pcrel move. Look forward, find the
4698 last barrier which is within MAX_COUNT bytes of the requirement.
4699 If there isn't one, make one. Process all the instructions between
4700 the find and the barrier.
4702 In the above example, we can tell that L3 is within 1k of L1, so
4703 the first move can be shrunk from the 3 insn+constant sequence into
4704 just 1 insn, and the constant moved to L3 to make:
4715 Then the second move becomes the target for the shortening process. */
4719 rtx value
; /* Value in table. */
4720 rtx_code_label
*label
; /* Label of value. */
4721 label_ref_list_t wend
; /* End of window. */
4722 machine_mode mode
; /* Mode of value. */
4724 /* True if this constant is accessed as part of a post-increment
4725 sequence. Note that HImode constants are never accessed in this way. */
4726 bool part_of_sequence_p
;
4729 /* The maximum number of constants that can fit into one pool, since
4730 constants in the range 0..510 are at least 2 bytes long, and in the
4731 range from there to 1018 at least 4 bytes. */
4733 #define MAX_POOL_SIZE 372
4734 static pool_node pool_vector
[MAX_POOL_SIZE
];
4735 static int pool_size
;
4736 static rtx_code_label
*pool_window_label
;
4737 static int pool_window_last
;
4739 static int max_labelno_before_reorg
;
4741 /* ??? If we need a constant in HImode which is the truncated value of a
4742 constant we need in SImode, we could combine the two entries thus saving
4743 two bytes. Is this common enough to be worth the effort of implementing
4746 /* ??? This stuff should be done at the same time that we shorten branches.
4747 As it is now, we must assume that all branches are the maximum size, and
4748 this causes us to almost always output constant pools sooner than
4751 /* Add a constant to the pool and return its label. */
4752 static rtx_code_label
*
4753 add_constant (rtx x
, machine_mode mode
, rtx last_value
)
4756 rtx_code_label
*lab
, *new_rtx
;
4757 label_ref_list_t ref
, newref
;
4759 /* First see if we've already got it. */
4760 for (i
= 0; i
< pool_size
; i
++)
4762 if (x
->code
== pool_vector
[i
].value
->code
4763 && mode
== pool_vector
[i
].mode
)
4765 if (x
->code
== CODE_LABEL
)
4767 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
4770 if (rtx_equal_p (x
, pool_vector
[i
].value
))
4775 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
4777 new_rtx
= gen_label_rtx ();
4778 LABEL_REFS (new_rtx
) = pool_vector
[i
].label
;
4779 pool_vector
[i
].label
= lab
= new_rtx
;
4781 if (lab
&& pool_window_label
)
4783 newref
= label_ref_list_d_pool
.allocate ();
4784 newref
->label
= pool_window_label
;
4785 ref
= pool_vector
[pool_window_last
].wend
;
4787 pool_vector
[pool_window_last
].wend
= newref
;
4790 pool_window_label
= new_rtx
;
4791 pool_window_last
= i
;
4797 /* Need a new one. */
4798 pool_vector
[pool_size
].value
= x
;
4799 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
4802 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
4805 lab
= gen_label_rtx ();
4806 pool_vector
[pool_size
].mode
= mode
;
4807 pool_vector
[pool_size
].label
= lab
;
4808 pool_vector
[pool_size
].wend
= NULL
;
4809 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
4810 if (lab
&& pool_window_label
)
4812 newref
= label_ref_list_d_pool
.allocate ();
4813 newref
->label
= pool_window_label
;
4814 ref
= pool_vector
[pool_window_last
].wend
;
4816 pool_vector
[pool_window_last
].wend
= newref
;
4819 pool_window_label
= lab
;
4820 pool_window_last
= pool_size
;
4825 /* Output the literal table. START, if nonzero, is the first instruction
4826 this table is needed for, and also indicates that there is at least one
4827 casesi_worker_2 instruction; We have to emit the operand3 labels from
4828 these insns at a 4-byte aligned position. BARRIER is the barrier
4829 after which we are to place the table. */
4831 dump_table (rtx_insn
*start
, rtx_insn
*barrier
)
4833 rtx_insn
*scan
= barrier
;
4835 bool need_align
= true;
4837 label_ref_list_t ref
;
4838 bool have_df
= false;
4840 /* Do two passes, first time dump out the HI sized constants. */
4842 for (i
= 0; i
< pool_size
; i
++)
4844 pool_node
*p
= &pool_vector
[i
];
4846 if (p
->mode
== HImode
)
4850 scan
= emit_insn_after (gen_align_2 (), scan
);
4853 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4854 scan
= emit_label_after (lab
, scan
);
4855 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
4857 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4860 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4863 else if (p
->mode
== DFmode
)
4871 scan
= emit_insn_after (gen_align_4 (), scan
);
4873 for (; start
!= barrier
; start
= NEXT_INSN (start
))
4874 if (NONJUMP_INSN_P (start
)
4875 && recog_memoized (start
) == CODE_FOR_casesi_worker_2
)
4877 rtx src
= SET_SRC (XVECEXP (PATTERN (start
), 0, 0));
4878 rtx lab
= XEXP (XVECEXP (src
, 0, 3), 0);
4880 scan
= emit_label_after (lab
, scan
);
4883 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
4885 rtx_insn
*align_insn
= NULL
;
4887 scan
= emit_label_after (gen_label_rtx (), scan
);
4888 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4891 for (i
= 0; i
< pool_size
; i
++)
4893 pool_node
*p
= &pool_vector
[i
];
4901 if (align_insn
&& !p
->part_of_sequence_p
)
4903 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4904 emit_label_before (lab
, align_insn
);
4905 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
4907 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4910 emit_insn_before (gen_consttable_window_end (lab
),
4913 delete_insn (align_insn
);
4919 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4920 scan
= emit_label_after (lab
, scan
);
4921 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
4923 need_align
= ! need_align
;
4929 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4934 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4935 scan
= emit_label_after (lab
, scan
);
4936 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4943 if (p
->mode
!= HImode
)
4945 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4948 scan
= emit_insn_after (gen_consttable_window_end (lab
),
4957 for (i
= 0; i
< pool_size
; i
++)
4959 pool_node
*p
= &pool_vector
[i
];
4970 scan
= emit_label_after (gen_label_rtx (), scan
);
4971 scan
= emit_insn_after (gen_align_4 (), scan
);
4973 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4974 scan
= emit_label_after (lab
, scan
);
4975 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
4983 scan
= emit_label_after (gen_label_rtx (), scan
);
4984 scan
= emit_insn_after (gen_align_4 (), scan
);
4986 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4987 scan
= emit_label_after (lab
, scan
);
4988 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4995 if (p
->mode
!= HImode
)
4997 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
5000 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
5005 scan
= emit_insn_after (gen_consttable_end (), scan
);
5006 scan
= emit_barrier_after (scan
);
5008 pool_window_label
= NULL
;
5009 pool_window_last
= 0;
5012 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
5014 /* Nonzero if the insn is a move instruction which needs to be fixed. */
5016 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
5017 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
5018 need to fix it if the input value is CONST_OK_FOR_I08. */
5020 broken_move (rtx_insn
*insn
)
5022 if (NONJUMP_INSN_P (insn
))
5024 rtx pat
= PATTERN (insn
);
5025 if (GET_CODE (pat
) == PARALLEL
)
5026 pat
= XVECEXP (pat
, 0, 0);
5027 if (GET_CODE (pat
) == SET
5028 /* We can load any 8-bit value if we don't care what the high
5029 order bits end up as. */
5030 && GET_MODE (SET_DEST (pat
)) != QImode
5031 && (CONSTANT_P (SET_SRC (pat
))
5032 || (GET_CODE (SET_SRC (pat
)) == UNSPEC_VOLATILE
5033 && XINT (SET_SRC (pat
), 1) == UNSPECV_SP_SWITCH_B
)
5034 /* Match mova_const. */
5035 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
5036 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
5037 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
5039 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
5040 && (fp_zero_operand (SET_SRC (pat
))
5041 || fp_one_operand (SET_SRC (pat
)))
5042 /* In general we don't know the current setting of fpscr, so
5044 There is an exception if this was a register-register move
5045 before reload - and hence it was ascertained that we have
5046 single precision setting - and in a post-reload optimization
5047 we changed this to do a constant load. In that case
5048 we don't have an r0 clobber, hence we must use fldi. */
5050 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
5052 && REG_P (SET_DEST (pat
))
5053 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
5055 && GET_MODE (SET_DEST (pat
)) == SImode
5056 && (satisfies_constraint_I20 (SET_SRC (pat
))
5057 || satisfies_constraint_I28 (SET_SRC (pat
))))
5058 && ! satisfies_constraint_I08 (SET_SRC (pat
)))
5065 /* Return true if the specified insn is a mova insn. */
5067 mova_p (rtx_insn
*insn
)
5069 return (NONJUMP_INSN_P (insn
)
5070 && GET_CODE (PATTERN (insn
)) == SET
5071 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
5072 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
5073 /* Don't match mova_const. */
5074 && GET_CODE (MOVA_LABELREF (insn
)) == LABEL_REF
);
5077 /* Fix up a mova from a switch that went out of range. */
5079 fixup_mova (rtx_insn
*mova
)
5081 PUT_MODE (XEXP (MOVA_LABELREF (mova
), 0), QImode
);
5084 SET_SRC (PATTERN (mova
)) = MOVA_LABELREF (mova
);
5085 INSN_CODE (mova
) = -1;
5089 rtx_insn
*worker
= mova
;
5090 rtx_code_label
*lab
= gen_label_rtx ();
5091 rtx wpat
, wpat0
, wpat1
, wsrc
, target
, base
, diff
;
5095 worker
= NEXT_INSN (worker
);
5097 && !LABEL_P (worker
)
5098 && !JUMP_P (worker
));
5099 } while (NOTE_P (worker
)
5100 || recog_memoized (worker
) != CODE_FOR_casesi_worker_1
);
5101 wpat
= PATTERN (worker
);
5102 wpat0
= XVECEXP (wpat
, 0, 0);
5103 wpat1
= XVECEXP (wpat
, 0, 1);
5104 wsrc
= SET_SRC (wpat0
);
5105 PATTERN (worker
) = (gen_casesi_worker_2
5106 (SET_DEST (wpat0
), XVECEXP (wsrc
, 0, 1),
5107 XEXP (XVECEXP (wsrc
, 0, 2), 0), lab
,
5109 INSN_CODE (worker
) = -1;
5110 target
= XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
5111 base
= gen_rtx_LABEL_REF (Pmode
, lab
);
5112 diff
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, target
, base
), UNSPEC_SYMOFF
);
5113 SET_SRC (PATTERN (mova
)) = gen_rtx_CONST (Pmode
, diff
);
5114 INSN_CODE (mova
) = -1;
5118 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
5119 *num_mova, and check if the new mova is not nested within the first one.
5120 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
5121 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
5123 untangle_mova (int *num_mova
, rtx_insn
**first_mova
, rtx_insn
*new_mova
)
5125 int n_addr
= 0; /* Initialization to shut up spurious warning. */
5126 int f_target
, n_target
= 0; /* Likewise. */
5130 /* If NEW_MOVA has no address yet, it will be handled later. */
5131 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova
))
5134 n_addr
= INSN_ADDRESSES (INSN_UID (new_mova
));
5135 n_target
= INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova
), 0)));
5136 if (n_addr
> n_target
|| n_addr
+ 1022 < n_target
)
5138 /* Change the mova into a load.
5139 broken_move will then return true for it. */
5140 fixup_mova (new_mova
);
5146 *first_mova
= new_mova
;
5151 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova
), 0))))
5156 if (f_target
- INSN_ADDRESSES (INSN_UID (*first_mova
))
5157 > n_target
- n_addr
)
5159 fixup_mova (*first_mova
);
5164 fixup_mova (new_mova
);
5169 /* Find the last barrier from insn FROM which is close enough to hold the
5170 constant pool. If we can't find one, then create one near the end of
5173 find_barrier (int num_mova
, rtx_insn
*mova
, rtx_insn
*from
)
5182 int leading_mova
= num_mova
;
5183 rtx_insn
*barrier_before_mova
= NULL
;
5184 rtx_insn
*found_barrier
= NULL
;
5185 rtx_insn
*good_barrier
= NULL
;
5188 rtx_insn
*orig
= from
;
5189 rtx_insn
*last_got
= NULL
;
5190 rtx_insn
*last_symoff
= NULL
;
5192 /* For HImode: range is 510, add 4 because pc counts from address of
5193 second instruction after this one, subtract 2 for the jump instruction
5194 that we may need to emit before the table, subtract 2 for the instruction
5195 that fills the jump delay slot (in very rare cases, reorg will take an
5196 instruction from after the constant pool or will leave the delay slot
5197 empty). This gives 510.
5198 For SImode: range is 1020, add 4 because pc counts from address of
5199 second instruction after this one, subtract 2 in case pc is 2 byte
5200 aligned, subtract 2 for the jump instruction that we may need to emit
5201 before the table, subtract 2 for the instruction that fills the jump
5202 delay slot. This gives 1018. */
5204 /* The branch will always be shortened now that the reference address for
5205 forward branches is the successor address, thus we need no longer make
5206 adjustments to the [sh]i_limit for -O0. */
5211 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
5213 int inc
= get_attr_length (from
);
5216 /* If this is a label that existed at the time of the compute_alignments
5217 call, determine the alignment. N.B. When find_barrier recurses for
5218 an out-of-reach mova, we might see labels at the start of previously
5219 inserted constant tables. */
5221 && CODE_LABEL_NUMBER (from
) <= max_labelno_before_reorg
)
5224 new_align
= 1 << label_to_alignment (from
);
5225 else if (BARRIER_P (prev_nonnote_insn (from
)))
5226 new_align
= 1 << barrier_align (from
);
5231 /* In case we are scanning a constant table because of recursion, check
5232 for explicit alignments. If the table is long, we might be forced
5233 to emit the new table in front of it; the length of the alignment
5234 might be the last straw. */
5235 else if (NONJUMP_INSN_P (from
)
5236 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
5237 && XINT (PATTERN (from
), 1) == UNSPECV_ALIGN
)
5238 new_align
= INTVAL (XVECEXP (PATTERN (from
), 0, 0));
5239 /* When we find the end of a constant table, paste the new constant
5240 at the end. That is better than putting it in front because
5241 this way, we don't need extra alignment for adding a 4-byte-aligned
5242 mov(a) label to a 2/4 or 8/4 byte aligned table. */
5243 else if (NONJUMP_INSN_P (from
)
5244 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
5245 && XINT (PATTERN (from
), 1) == UNSPECV_CONST_END
)
5248 if (BARRIER_P (from
))
5252 found_barrier
= from
;
5254 /* If we are at the end of the function, or in front of an alignment
5255 instruction, we need not insert an extra alignment. We prefer
5256 this kind of barrier. */
5257 if (barrier_align (from
) > 2)
5258 good_barrier
= from
;
5260 /* If we are at the end of a hot/cold block, dump the constants
5262 next
= NEXT_INSN (from
);
5265 && NOTE_KIND (next
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
5269 if (broken_move (from
))
5274 pat
= PATTERN (from
);
5275 if (GET_CODE (pat
) == PARALLEL
)
5276 pat
= XVECEXP (pat
, 0, 0);
5277 src
= SET_SRC (pat
);
5278 dst
= SET_DEST (pat
);
5279 mode
= GET_MODE (dst
);
5281 /* GOT pcrelat setting comes in pair of
5284 instructions. (plus add r0,r12).
5285 Remember if we see one without the other. */
5286 if (GET_CODE (src
) == UNSPEC
&& PIC_ADDR_P (XVECEXP (src
, 0, 0)))
5287 last_got
= last_got
? NULL
: from
;
5288 else if (PIC_ADDR_P (src
))
5289 last_got
= last_got
? NULL
: from
;
5291 /* We must explicitly check the mode, because sometimes the
5292 front end will generate code to load unsigned constants into
5293 HImode targets without properly sign extending them. */
5295 || (mode
== SImode
&& satisfies_constraint_I16 (src
)
5296 && REGNO (dst
) != FPUL_REG
))
5299 /* We put the short constants before the long constants, so
5300 we must count the length of short constants in the range
5301 for the long constants. */
5302 /* ??? This isn't optimal, but is easy to do. */
5307 /* We dump DF/DI constants before SF/SI ones, because
5308 the limit is the same, but the alignment requirements
5309 are higher. We may waste up to 4 additional bytes
5310 for alignment, and the DF/DI constant may have
5311 another SF/SI constant placed before it. */
5312 if (TARGET_SHCOMPACT
5314 && (mode
== DFmode
|| mode
== DImode
))
5319 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
5321 if (found_si
> count_si
)
5322 count_si
= found_si
;
5323 found_si
+= GET_MODE_SIZE (mode
);
5325 si_limit
-= GET_MODE_SIZE (mode
);
5331 switch (untangle_mova (&num_mova
, &mova
, from
))
5336 rtx src
= SET_SRC (PATTERN (from
));
5337 if (GET_CODE (src
) == CONST
5338 && GET_CODE (XEXP (src
, 0)) == UNSPEC
5339 && XINT (XEXP (src
, 0), 1) == UNSPEC_SYMOFF
)
5343 case 0: return find_barrier (0, 0, mova
);
5348 = good_barrier
? good_barrier
: found_barrier
;
5352 if (found_si
> count_si
)
5353 count_si
= found_si
;
5355 else if (JUMP_TABLE_DATA_P (from
)
5356 && GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
)
5358 if ((num_mova
> 1 && GET_MODE (prev_nonnote_insn (from
)) == VOIDmode
)
5360 && (prev_nonnote_insn (from
)
5361 == XEXP (MOVA_LABELREF (mova
), 0))))
5363 if (barrier_align (next_real_insn (from
)) == align_jumps_log
)
5365 /* We have just passed the barrier in front of the
5366 ADDR_DIFF_VEC, which is stored in found_barrier. Since
5367 the ADDR_DIFF_VEC is accessed as data, just like our pool
5368 constants, this is a good opportunity to accommodate what
5369 we have gathered so far.
5370 If we waited any longer, we could end up at a barrier in
5371 front of code, which gives worse cache usage for separated
5372 instruction / data caches. */
5373 good_barrier
= found_barrier
;
5378 rtx body
= PATTERN (from
);
5379 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
5382 /* For the SH1, we generate alignments even after jumps-around-jumps. */
5383 else if (JUMP_P (from
)
5388 /* There is a possibility that a bf is transformed into a bf/s by the
5389 delay slot scheduler. */
5391 && get_attr_type (from
) == TYPE_CBRANCH
5392 && ! sequence_insn_p (from
))
5398 if (new_align
> si_align
)
5400 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
5401 si_align
= new_align
;
5403 count_si
= (count_si
+ new_align
- 1) & -new_align
;
5408 if (new_align
> hi_align
)
5410 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
5411 hi_align
= new_align
;
5413 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
5415 from
= NEXT_INSN (from
);
5422 /* Try as we might, the leading mova is out of range. Change
5423 it into a load (which will become a pcload) and retry. */
5425 return find_barrier (0, 0, mova
);
5429 /* Insert the constant pool table before the mova instruction,
5430 to prevent the mova label reference from going out of range. */
5432 good_barrier
= found_barrier
= barrier_before_mova
;
5438 if (good_barrier
&& next_real_insn (found_barrier
))
5439 found_barrier
= good_barrier
;
5443 /* We didn't find a barrier in time to dump our stuff,
5444 so we'll make one. */
5445 rtx_code_label
*label
= gen_label_rtx ();
5447 /* Don't emit a constant table in the middle of insns for
5448 casesi_worker_2. This is a bit overkill but is enough
5449 because casesi_worker_2 wouldn't appear so frequently. */
5453 /* If we exceeded the range, then we must back up over the last
5454 instruction we looked at. Otherwise, we just need to undo the
5455 NEXT_INSN at the end of the loop. */
5456 if (PREV_INSN (from
) != orig
5457 && (count_hi
> hi_limit
|| count_si
> si_limit
))
5458 from
= PREV_INSN (PREV_INSN (from
));
5460 from
= PREV_INSN (from
);
5462 /* Don't emit a constant table int the middle of global pointer setting,
5463 since that that would move the addressing base GOT into another table.
5464 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
5465 in the pool anyway, so just move up the whole constant pool.
5467 However, avoid doing so when the last single GOT mov is the starting
5468 insn itself. Going past above the start insn would create a negative
5469 offset, causing errors. */
5470 if (last_got
&& last_got
!= orig
)
5471 from
= PREV_INSN (last_got
);
5473 /* Don't insert the constant pool table at the position which
5474 may be the landing pad. */
5477 && find_reg_note (from
, REG_EH_REGION
, NULL_RTX
))
5478 from
= PREV_INSN (from
);
5480 /* Walk back to be just before any jump or label.
5481 Putting it before a label reduces the number of times the branch
5482 around the constant pool table will be hit. Putting it before
5483 a jump makes it more likely that the bra delay slot will be
5485 while (NOTE_P (from
) || JUMP_P (from
)
5487 from
= PREV_INSN (from
);
5489 /* Make sure we do not split between a call and its corresponding
5490 CALL_ARG_LOCATION note. */
5493 rtx_insn
*next
= NEXT_INSN (from
);
5494 if (next
&& NOTE_P (next
)
5495 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
5499 from
= emit_jump_insn_after (gen_jump (label
), from
);
5500 JUMP_LABEL (from
) = label
;
5501 LABEL_NUSES (label
) = 1;
5502 found_barrier
= emit_barrier_after (from
);
5503 emit_label_after (label
, found_barrier
);
5506 return found_barrier
;
5509 /* If the instruction INSN is implemented by a special function, and we can
5510 positively find the register that is used to call the sfunc, and this
5511 register is not used anywhere else in this instruction - except as the
5512 destination of a set, return this register; else, return 0. */
5514 sfunc_uses_reg (rtx_insn
*insn
)
5517 rtx pattern
, part
, reg_part
, reg
;
5519 if (!NONJUMP_INSN_P (insn
))
5521 pattern
= PATTERN (insn
);
5522 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
5525 for (reg_part
= NULL_RTX
, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
5527 part
= XVECEXP (pattern
, 0, i
);
5528 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
5533 reg
= XEXP (reg_part
, 0);
5534 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
5536 part
= XVECEXP (pattern
, 0, i
);
5537 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
5539 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
5540 && REG_P (SET_DEST (part
)))
5541 ? SET_SRC (part
) : part
)))
5547 /* See if the only way in which INSN uses REG is by calling it, or by
5548 setting it while calling it. Set *SET to a SET rtx if the register
5551 noncall_uses_reg (rtx reg
, rtx_insn
*insn
, rtx
*set
)
5557 reg2
= sfunc_uses_reg (insn
);
5558 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
5560 pattern
= single_set (insn
);
5562 && REG_P (SET_DEST (pattern
))
5563 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
5569 /* We don't use rtx_equal_p because we don't care if the mode is
5571 pattern
= single_set (insn
);
5573 && REG_P (SET_DEST (pattern
))
5574 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
5580 par
= PATTERN (insn
);
5581 if (GET_CODE (par
) == PARALLEL
)
5582 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
5584 part
= XVECEXP (par
, 0, i
);
5585 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
5588 return reg_mentioned_p (reg
, SET_SRC (pattern
));
5594 pattern
= PATTERN (insn
);
5596 if (GET_CODE (pattern
) == PARALLEL
)
5600 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
5601 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
5603 pattern
= XVECEXP (pattern
, 0, 0);
5606 if (GET_CODE (pattern
) == SET
)
5608 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
5610 /* We don't use rtx_equal_p, because we don't care if the
5611 mode is different. */
5612 if (!REG_P (SET_DEST (pattern
))
5613 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
5619 pattern
= SET_SRC (pattern
);
5622 if (GET_CODE (pattern
) != CALL
5623 || !MEM_P (XEXP (pattern
, 0))
5624 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
5630 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5631 general registers. Bits 0..15 mean that the respective registers
5632 are used as inputs in the instruction. Bits 16..31 mean that the
5633 registers 0..15, respectively, are used as outputs, or are clobbered.
5634 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5636 regs_used (rtx x
, int is_dest
)
5644 code
= GET_CODE (x
);
5649 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
5650 << (REGNO (x
) + is_dest
));
5654 rtx y
= SUBREG_REG (x
);
5659 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
5661 subreg_regno_offset (REGNO (y
),
5664 GET_MODE (x
)) + is_dest
));
5668 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
5670 /* If there was a return value, it must have been indicated with USE. */
5685 fmt
= GET_RTX_FORMAT (code
);
5687 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5692 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5693 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
5695 else if (fmt
[i
] == 'e')
5696 used
|= regs_used (XEXP (x
, i
), is_dest
);
5701 /* Create an instruction that prevents redirection of a conditional branch
5702 to the destination of the JUMP with address ADDR.
5703 If the branch needs to be implemented as an indirect jump, try to find
5704 a scratch register for it.
5705 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5706 If any preceding insn that doesn't fit into a delay slot is good enough,
5707 pass 1. Pass 2 if a definite blocking insn is needed.
5708 -1 is used internally to avoid deep recursion.
5709 If a blocking instruction is made or recognized, return it. */
5711 gen_block_redirect (rtx_insn
*jump
, int addr
, int need_block
)
5714 rtx_insn
*prev
= prev_nonnote_insn (jump
);
5717 /* First, check if we already have an instruction that satisfies our need. */
5718 if (prev
&& NONJUMP_INSN_P (prev
) && ! prev
->deleted ())
5720 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
5722 if (GET_CODE (PATTERN (prev
)) == USE
5723 || GET_CODE (PATTERN (prev
)) == CLOBBER
5724 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5726 else if ((need_block
&= ~1) < 0)
5728 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
5731 if (GET_CODE (PATTERN (jump
)) == RETURN
)
5735 /* Reorg even does nasty things with return insns that cause branches
5736 to go out of range - see find_end_label and callers. */
5737 return emit_insn_before (gen_block_branch_redirect (const0_rtx
) , jump
);
5739 /* We can't use JUMP_LABEL here because it might be undefined
5740 when not optimizing. */
5741 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
5742 /* If the branch is out of range, try to find a scratch register for it. */
5744 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5748 /* Don't look for the stack pointer as a scratch register,
5749 it would cause trouble if an interrupt occurred. */
5750 unsigned attempt
= 0x7fff, used
;
5751 int jump_left
= flag_expensive_optimizations
+ 1;
5753 /* It is likely that the most recent eligible instruction is wanted for
5754 the delay slot. Therefore, find out which registers it uses, and
5755 try to avoid using them. */
5757 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
5761 if (scan
->deleted ())
5763 code
= GET_CODE (scan
);
5764 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
5767 && GET_CODE (PATTERN (scan
)) != USE
5768 && GET_CODE (PATTERN (scan
)) != CLOBBER
5769 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
5771 attempt
&= ~regs_used (PATTERN (scan
), 0);
5775 for (used
= dead
= 0, scan
= JUMP_LABEL_AS_INSN (jump
);
5776 (scan
= NEXT_INSN (scan
)); )
5780 if (scan
->deleted ())
5782 code
= GET_CODE (scan
);
5785 used
|= regs_used (PATTERN (scan
), 0);
5786 if (code
== CALL_INSN
)
5787 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
5788 dead
|= (used
>> 16) & ~used
;
5794 if (code
== JUMP_INSN
)
5796 if (jump_left
-- && simplejump_p (scan
))
5797 scan
= JUMP_LABEL_AS_INSN (scan
);
5803 /* Mask out the stack pointer again, in case it was
5804 the only 'free' register we have found. */
5807 /* If the immediate destination is still in range, check for possible
5808 threading with a jump beyond the delay slot insn.
5809 Don't check if we are called recursively; the jump has been or will be
5810 checked in a different invocation then. */
5812 else if (optimize
&& need_block
>= 0)
5814 rtx_insn
*next
= next_active_insn (next_active_insn (dest
));
5815 if (next
&& JUMP_P (next
)
5816 && GET_CODE (PATTERN (next
)) == SET
5817 && recog_memoized (next
) == CODE_FOR_jump_compact
)
5819 dest
= JUMP_LABEL (next
);
5821 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5823 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
5829 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
5831 /* It would be nice if we could convert the jump into an indirect
5832 jump / far branch right now, and thus exposing all constituent
5833 instructions to further optimization. However, reorg uses
5834 simplejump_p to determine if there is an unconditional jump where
5835 it should try to schedule instructions from the target of the
5836 branch; simplejump_p fails for indirect jumps even if they have
5838 rtx_insn
*insn
= emit_insn_before (gen_indirect_jump_scratch
5839 (reg
, GEN_INT (unspec_bbr_uid
++)),
5841 /* ??? We would like this to have the scope of the jump, but that
5842 scope will change when a delay slot insn of an inner scope is added.
5843 Hence, after delay slot scheduling, we'll have to expect
5844 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5847 INSN_LOCATION (insn
) = INSN_LOCATION (jump
);
5848 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
5851 else if (need_block
)
5852 /* We can't use JUMP_LABEL here because it might be undefined
5853 when not optimizing. */
5854 return emit_insn_before (gen_block_branch_redirect
5855 (GEN_INT (unspec_bbr_uid
++)),
5860 #define CONDJUMP_MIN -252
5861 #define CONDJUMP_MAX 262
5864 /* A label (to be placed) in front of the jump
5865 that jumps to our ultimate destination. */
5866 rtx_insn
*near_label
;
5867 /* Where we are going to insert it if we cannot move the jump any farther,
5868 or the jump itself if we have picked up an existing jump. */
5869 rtx_insn
*insert_place
;
5870 /* The ultimate destination. */
5871 rtx_insn
*far_label
;
5872 struct far_branch
*prev
;
5873 /* If the branch has already been created, its address;
5874 else the address of its first prospective user. */
5878 static void gen_far_branch (struct far_branch
*);
5879 enum mdep_reorg_phase_e mdep_reorg_phase
;
5881 gen_far_branch (struct far_branch
*bp
)
5883 rtx_insn
*insn
= bp
->insert_place
;
5884 rtx_jump_insn
*jump
;
5885 rtx_code_label
*label
= gen_label_rtx ();
5888 emit_label_after (label
, insn
);
5891 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
5892 LABEL_NUSES (bp
->far_label
)++;
5895 jump
= emit_jump_insn_after (gen_return (), insn
);
5897 /* Emit a barrier so that reorg knows that any following instructions
5898 are not reachable via a fall-through path.
5899 But don't do this when not optimizing, since we wouldn't suppress the
5900 alignment for the barrier then, and could end up with out-of-range
5901 pc-relative loads. */
5903 emit_barrier_after (jump
);
5904 emit_label_after (bp
->near_label
, insn
);
5907 JUMP_LABEL (jump
) = bp
->far_label
;
5910 rtx pat
= PATTERN (jump
);
5911 gcc_assert (ANY_RETURN_P (pat
));
5912 JUMP_LABEL (jump
) = pat
;
5915 ok
= invert_jump (as_a
<rtx_jump_insn
*> (insn
), label
, 1);
5918 /* If we are branching around a jump (rather than a return), prevent
5919 reorg from using an insn from the jump target as the delay slot insn -
5920 when reorg did this, it pessimized code (we rather hide the delay slot)
5921 and it could cause branches to go out of range. */
5924 (gen_stuff_delay_slot
5925 (GEN_INT (unspec_bbr_uid
++),
5926 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
5928 /* Prevent reorg from undoing our splits. */
5929 gen_block_redirect (jump
, bp
->address
+= 2, 2);
5932 /* Fix up ADDR_DIFF_VECs. */
5934 fixup_addr_diff_vecs (rtx_insn
*first
)
5938 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5940 rtx vec_lab
, pat
, prevpat
, x
, braf_label
;
5943 if (! JUMP_TABLE_DATA_P (insn
)
5944 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
5946 pat
= PATTERN (insn
);
5947 vec_lab
= XEXP (XEXP (pat
, 0), 0);
5949 /* Search the matching casesi_jump_2. */
5950 for (prev
= as_a
<rtx_insn
*> (vec_lab
); ; prev
= PREV_INSN (prev
))
5954 prevpat
= PATTERN (prev
);
5955 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
5957 x
= XVECEXP (prevpat
, 0, 1);
5958 if (GET_CODE (x
) != USE
)
5961 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
5964 /* FIXME: This is a bug in the optimizer, but it seems harmless
5965 to just avoid panicing. */
5969 /* Emit the reference label of the braf where it belongs, right after
5970 the casesi_jump_2 (i.e. braf). */
5971 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
5972 emit_label_after (braf_label
, prev
);
5974 /* Fix up the ADDR_DIF_VEC to be relative
5975 to the reference address of the braf. */
5976 XEXP (XEXP (pat
, 0), 0) = braf_label
;
5980 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5981 a barrier. Return the base 2 logarithm of the desired alignment. */
5983 barrier_align (rtx_insn
*barrier_or_label
)
5987 if (! barrier_or_label
)
5990 if (LABEL_P (barrier_or_label
)
5991 && NEXT_INSN (barrier_or_label
)
5992 && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label
)))
5995 if (BARRIER_P (barrier_or_label
)
5996 && PREV_INSN (barrier_or_label
)
5997 && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label
)))
5999 pat
= PATTERN (PREV_INSN (barrier_or_label
));
6000 /* If this is a very small table, we want to keep the alignment after
6001 the table to the minimum for proper code alignment. */
6002 return ((optimize_size
6003 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
6004 <= (unsigned) 1 << (CACHE_LOG
- 2)))
6005 ? 1 << TARGET_SHMEDIA
: align_jumps_log
);
6008 next
= next_active_insn (barrier_or_label
);
6013 pat
= PATTERN (next
);
6015 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
6016 /* This is a barrier in front of a constant table. */
6022 if (! TARGET_SH2
|| ! optimize
)
6023 return align_jumps_log
;
6025 /* When fixing up pcloads, a constant table might be inserted just before
6026 the basic block that ends with the barrier. Thus, we can't trust the
6027 instruction lengths before that. */
6028 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
6030 /* Check if there is an immediately preceding branch to the insn beyond
6031 the barrier. We must weight the cost of discarding useful information
6032 from the current cache line when executing this branch and there is
6033 an alignment, against that of fetching unneeded insn in front of the
6034 branch target when there is no alignment. */
6036 /* There are two delay_slot cases to consider. One is the simple case
6037 where the preceding branch is to the insn beyond the barrier (simple
6038 delay slot filling), and the other is where the preceding branch has
6039 a delay slot that is a duplicate of the insn after the barrier
6040 (fill_eager_delay_slots) and the branch is to the insn after the insn
6041 after the barrier. */
6044 bool jump_to_next
= false;
6046 /* Skip to the insn before the JUMP_INSN before the barrier under
6048 rtx_insn
*prev
= prev_real_insn (prev_active_insn (barrier_or_label
));
6050 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
6051 credit
>= 0 && prev
&& NONJUMP_INSN_P (prev
);
6052 prev
= prev_real_insn (prev
))
6054 jump_to_next
= false;
6055 if (GET_CODE (PATTERN (prev
)) == USE
6056 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
6058 if (rtx_sequence
*prev_seq
= dyn_cast
<rtx_sequence
*> (PATTERN (prev
)))
6060 prev
= prev_seq
->insn (1);
6061 if (INSN_UID (prev
) == INSN_UID (next
))
6063 /* Delay slot was filled with insn at jump target. */
6064 jump_to_next
= true;
6070 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
6072 credit
-= get_attr_length (prev
);
6074 if (prev
&& jump_to_label_p (prev
))
6078 || next_real_insn (JUMP_LABEL (prev
)) == next
6079 /* If relax_delay_slots() decides NEXT was redundant
6080 with some previous instruction, it will have
6081 redirected PREV's jump to the following insn. */
6082 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
6083 /* There is no upper bound on redundant instructions
6084 that might have been skipped, but we must not put an
6085 alignment where none had been before. */
6086 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
6088 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
6089 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
6090 || INSN_CODE (x
) == CODE_FOR_stuff_delay_slot
))))
6092 rtx pat
= PATTERN (prev
);
6093 if (GET_CODE (pat
) == PARALLEL
)
6094 pat
= XVECEXP (pat
, 0, 0);
6095 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
6101 return align_jumps_log
;
6104 /* If we are inside a phony loop, almost any kind of label can turn up as the
6105 first one in the loop. Aligning a braf label causes incorrect switch
6106 destination addresses; we can detect braf labels because they are
6107 followed by a BARRIER.
6108 Applying loop alignment to small constant or switch tables is a waste
6109 of space, so we suppress this too. */
6111 sh_loop_align (rtx_insn
*label
)
6113 rtx_insn
*next
= label
;
6115 if (! optimize
|| optimize_size
)
6119 next
= next_nonnote_insn (next
);
6120 while (next
&& LABEL_P (next
));
6124 || recog_memoized (next
) == CODE_FOR_consttable_2
)
6127 return align_loops_log
;
6130 /* Do a final pass over the function, just before delayed branch
6135 rtx_insn
*first
, *insn
, *mova
= NULL
;
6137 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
6138 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
6140 first
= get_insns ();
6141 max_labelno_before_reorg
= max_label_num ();
6143 /* We must split call insns before introducing `mova's. If we're
6144 optimizing, they'll have already been split. Otherwise, make
6145 sure we don't split them too late. */
6147 split_all_insns_noflow ();
6152 /* If relaxing, generate pseudo-ops to associate function calls with
6153 the symbols they call. It does no harm to not generate these
6154 pseudo-ops. However, when we can generate them, it enables the
6155 linker to potentially relax the jsr to a bsr, and eliminate the
6156 register load and, possibly, the constant pool entry. */
6158 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
6161 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
6162 own purposes. This works because none of the remaining passes
6163 need to look at them.
6165 ??? But it may break in the future. We should use a machine
6166 dependent REG_NOTE, or some other approach entirely. */
6167 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6173 while ((note
= find_reg_note (insn
, REG_LABEL_OPERAND
,
6175 remove_note (insn
, note
);
6179 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6181 rtx pattern
, reg
, set
, dies
;
6182 rtx_code_label
*label
;
6183 rtx_insn
*link
, *scan
;
6184 int rescan
= 0, foundinsn
= 0;
6188 pattern
= PATTERN (insn
);
6190 if (GET_CODE (pattern
) == PARALLEL
)
6191 pattern
= XVECEXP (pattern
, 0, 0);
6192 if (GET_CODE (pattern
) == SET
)
6193 pattern
= SET_SRC (pattern
);
6195 if (GET_CODE (pattern
) != CALL
6196 || !MEM_P (XEXP (pattern
, 0)))
6199 reg
= XEXP (XEXP (pattern
, 0), 0);
6203 reg
= sfunc_uses_reg (insn
);
6211 /* Try scanning backward to find where the register is set. */
6213 for (scan
= PREV_INSN (insn
);
6214 scan
&& !LABEL_P (scan
);
6215 scan
= PREV_INSN (scan
))
6217 if (! INSN_P (scan
))
6220 if (! reg_mentioned_p (reg
, scan
))
6223 if (noncall_uses_reg (reg
, scan
, &set
))
6236 /* The register is set at LINK. */
6238 /* We can only optimize the function call if the register is
6239 being set to a symbol. In theory, we could sometimes
6240 optimize calls to a constant location, but the assembler
6241 and linker do not support that at present. */
6242 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
6243 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
6246 /* Scan forward from LINK to the place where REG dies, and
6247 make sure that the only insns which use REG are
6248 themselves function calls. */
6250 /* ??? This doesn't work for call targets that were allocated
6251 by reload, since there may not be a REG_DEAD note for the
6255 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
6259 /* Don't try to trace forward past a CODE_LABEL if we haven't
6260 seen INSN yet. Ordinarily, we will only find the setting insn
6261 if it is in the same basic block. However,
6262 cross-jumping can insert code labels in between the load and
6263 the call, and can result in situations where a single call
6264 insn may have two targets depending on where we came from. */
6266 if (LABEL_P (scan
) && ! foundinsn
)
6269 if (! INSN_P (scan
))
6272 /* Don't try to trace forward past a JUMP. To optimize
6273 safely, we would have to check that all the
6274 instructions at the jump destination did not use REG. */
6279 if (! reg_mentioned_p (reg
, scan
))
6282 if (noncall_uses_reg (reg
, scan
, &scanset
))
6289 && (CALL_P (scan
) || sfunc_uses_reg (scan
)))
6291 /* There is a function call to this register other
6292 than the one we are checking. If we optimize
6293 this call, we need to rescan again below. */
6297 /* ??? We shouldn't have to worry about SCANSET here.
6298 We should just be able to check for a REG_DEAD note
6299 on a function call. However, the REG_DEAD notes are
6300 apparently not dependable around libcalls; c-torture
6301 execute/920501-2 is a test case. If SCANSET is set,
6302 then this insn sets the register, so it must have
6303 died earlier. Unfortunately, this will only handle
6304 the cases in which the register is, in fact, set in a
6307 /* ??? We shouldn't have to use FOUNDINSN here.
6308 This dates back to when we used LOG_LINKS to find
6309 the most recent insn which sets the register. */
6313 || find_reg_note (scan
, REG_DEAD
, reg
)))
6322 /* Either there was a branch, or some insn used REG
6323 other than as a function call address. */
6327 /* Create a code label, and put it in a REG_LABEL_OPERAND note
6328 on the insn which sets the register, and on each call insn
6329 which uses the register. In final_prescan_insn we look for
6330 the REG_LABEL_OPERAND notes, and output the appropriate label
6333 label
= gen_label_rtx ();
6334 add_reg_note (link
, REG_LABEL_OPERAND
, label
);
6335 add_reg_note (insn
, REG_LABEL_OPERAND
, label
);
6343 scan
= NEXT_INSN (scan
);
6346 && reg_mentioned_p (reg
, scan
))
6347 || ((reg2
= sfunc_uses_reg (scan
))
6348 && REGNO (reg2
) == REGNO (reg
))))
6349 add_reg_note (scan
, REG_LABEL_OPERAND
, label
);
6351 while (scan
!= dies
);
6357 fixup_addr_diff_vecs (first
);
6361 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
6362 shorten_branches (first
);
6365 /* Scan the function looking for move instructions which have to be
6366 changed to pc-relative loads and insert the literal tables. */
6367 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
6368 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
6372 /* ??? basic block reordering can move a switch table dispatch
6373 below the switch table. Check if that has happened.
6374 We only have the addresses available when optimizing; but then,
6375 this check shouldn't be needed when not optimizing. */
6376 if (!untangle_mova (&num_mova
, &mova
, insn
))
6382 else if (JUMP_TABLE_DATA_P (insn
)
6383 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
6385 /* ??? loop invariant motion can also move a mova out of a
6386 loop. Since loop does this code motion anyway, maybe we
6387 should wrap UNSPEC_MOVA into a CONST, so that reload can
6390 && GET_MODE (prev_nonnote_insn (insn
)) == VOIDmode
)
6391 || (prev_nonnote_insn (insn
)
6392 == XEXP (MOVA_LABELREF (mova
), 0))))
6399 /* Some code might have been inserted between the mova and
6400 its ADDR_DIFF_VEC. Check if the mova is still in range. */
6401 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
6402 total
+= get_attr_length (scan
);
6404 /* range of mova is 1020, add 4 because pc counts from address of
6405 second instruction after this one, subtract 2 in case pc is 2
6406 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
6407 cancels out with alignment effects of the mova itself. */
6410 /* Change the mova into a load, and restart scanning
6411 there. broken_move will then return true for mova. */
6416 if (broken_move (insn
)
6417 || (NONJUMP_INSN_P (insn
)
6418 && recog_memoized (insn
) == CODE_FOR_casesi_worker_2
))
6421 /* Scan ahead looking for a barrier to stick the constant table
6423 rtx_insn
*barrier
= find_barrier (num_mova
, mova
, insn
);
6424 rtx_insn
*last_float_move
= NULL
;
6425 rtx last_float
= 0, *last_float_addr
= NULL
;
6426 int need_aligned_label
= 0;
6428 if (num_mova
&& ! mova_p (mova
))
6430 /* find_barrier had to change the first mova into a
6431 pcload; thus, we have to start with this new pcload. */
6435 /* Now find all the moves between the points and modify them. */
6436 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
6440 if (NONJUMP_INSN_P (scan
)
6441 && recog_memoized (scan
) == CODE_FOR_casesi_worker_2
)
6442 need_aligned_label
= 1;
6443 if (broken_move (scan
))
6445 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
6451 if (GET_CODE (pat
) == PARALLEL
)
6452 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
6453 src
= SET_SRC (pat
);
6454 dst
= SET_DEST (pat
);
6455 mode
= GET_MODE (dst
);
6457 if (mode
== SImode
&& satisfies_constraint_I16 (src
)
6458 && REGNO (dst
) != FPUL_REG
)
6463 while (GET_CODE (dst
) == SUBREG
)
6465 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
6466 GET_MODE (SUBREG_REG (dst
)),
6469 dst
= SUBREG_REG (dst
);
6471 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
6473 if (REG_P (dst
) && FP_ANY_REGISTER_P (REGNO (dst
)))
6475 /* This must be an insn that clobbers r0. */
6476 rtx
*clobberp
= &XVECEXP (PATTERN (scan
), 0,
6477 XVECLEN (PATTERN (scan
), 0)
6479 rtx clobber
= *clobberp
;
6481 gcc_assert (GET_CODE (clobber
) == CLOBBER
6482 && rtx_equal_p (XEXP (clobber
, 0), r0_rtx
));
6485 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
6489 && GET_MODE_SIZE (mode
) != 4
6490 && GET_MODE_SIZE (GET_MODE (last_float
)) == 4)
6492 lab
= add_constant (src
, mode
, last_float
);
6494 emit_insn_before (gen_mova (lab
), scan
);
6497 /* There will be a REG_UNUSED note for r0 on
6498 LAST_FLOAT_MOVE; we have to change it to REG_INC,
6499 lest reorg:mark_target_live_regs will not
6500 consider r0 to be used, and we end up with delay
6501 slot insn in front of SCAN that clobbers r0. */
6503 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
6505 /* If we are not optimizing, then there may not be
6508 PUT_REG_NOTE_KIND (note
, REG_INC
);
6510 *last_float_addr
= r0_inc_rtx
;
6512 last_float_move
= scan
;
6514 newsrc
= gen_const_mem (mode
,
6515 (((TARGET_SH4
&& ! TARGET_FMOVD
)
6516 || REGNO (dst
) == FPUL_REG
)
6519 last_float_addr
= &XEXP (newsrc
, 0);
6521 /* Remove the clobber of r0. */
6522 *clobberp
= gen_rtx_CLOBBER (GET_MODE (clobber
),
6523 gen_rtx_SCRATCH (Pmode
));
6525 /* This is a mova needing a label. Create it. */
6526 else if (GET_CODE (src
) == UNSPEC
6527 && XINT (src
, 1) == UNSPEC_MOVA
6528 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
6530 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
6531 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
6532 newsrc
= gen_rtx_UNSPEC (SImode
,
6533 gen_rtvec (1, newsrc
),
6536 else if (GET_CODE (src
) == UNSPEC_VOLATILE
6537 && XINT (src
, 1) == UNSPECV_SP_SWITCH_B
)
6539 newsrc
= XVECEXP (src
, 0, 0);
6540 XVECEXP (src
, 0, 0) = gen_const_mem (mode
, newsrc
);
6541 INSN_CODE (scan
) = -1;
6546 lab
= add_constant (src
, mode
, 0);
6547 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
6548 newsrc
= gen_const_mem (mode
, newsrc
);
6550 *patp
= gen_rtx_SET (dst
, newsrc
);
6551 INSN_CODE (scan
) = -1;
6554 dump_table (need_aligned_label
? insn
: 0, barrier
);
6558 label_ref_list_d_pool
.release ();
6559 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6560 PUT_MODE (insn
, VOIDmode
);
6562 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
6563 INSN_ADDRESSES_FREE ();
6564 split_branches (first
);
6566 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
6567 also has an effect on the register that holds the address of the sfunc.
6568 Insert an extra dummy insn in front of each sfunc that pretends to
6569 use this register. */
6570 if (flag_delayed_branch
)
6572 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6574 rtx reg
= sfunc_uses_reg (insn
);
6578 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
6581 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
6584 /* Return the UID of the insn that follows the specified label. */
6586 get_dest_uid (rtx label
, int max_uid
)
6588 rtx_insn
*dest
= next_real_insn (label
);
6591 /* This can happen for an undefined label. */
6593 dest_uid
= INSN_UID (dest
);
6594 /* If this is a newly created branch redirection blocking instruction,
6595 we cannot index the branch_uid or insn_addresses arrays with its
6596 uid. But then, we won't need to, because the actual destination is
6597 the following branch. */
6598 while (dest_uid
>= max_uid
)
6600 dest
= NEXT_INSN (dest
);
6601 dest_uid
= INSN_UID (dest
);
6603 if (JUMP_P (dest
) && GET_CODE (PATTERN (dest
)) == RETURN
)
6608 /* Split condbranches that are out of range. Also add clobbers for
6609 scratch registers that are needed in far jumps.
6610 We do this before delay slot scheduling, so that it can take our
6611 newly created instructions into account. It also allows us to
6612 find branches with common targets more easily. */
6614 split_branches (rtx_insn
*first
)
6617 struct far_branch
**uid_branch
, *far_branch_list
= 0;
6618 int max_uid
= get_max_uid ();
6621 /* Find out which branches are out of range. */
6622 shorten_branches (first
);
6624 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
6625 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
6627 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6628 if (! INSN_P (insn
))
6630 else if (insn
->deleted ())
6632 /* Shorten_branches would split this instruction again,
6633 so transform it into a note. */
6634 SET_INSN_DELETED (insn
);
6636 else if (JUMP_P (insn
))
6638 enum attr_type type
= get_attr_type (insn
);
6639 if (type
== TYPE_CBRANCH
)
6641 rtx_insn
*next
, *beyond
;
6643 if (get_attr_length (insn
) > 4)
6645 rtx src
= SET_SRC (PATTERN (insn
));
6646 rtx olabel
= XEXP (XEXP (src
, 1), 0);
6647 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6648 rtx_insn
*label
= 0;
6649 int dest_uid
= get_dest_uid (olabel
, max_uid
);
6650 struct far_branch
*bp
= uid_branch
[dest_uid
];
6652 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6653 the label if the LABEL_NUSES count drops to zero. There is
6654 always a jump_optimize pass that sets these values, but it
6655 proceeds to delete unreferenced code, and then if not
6656 optimizing, to un-delete the deleted instructions, thus
6657 leaving labels with too low uses counts. */
6660 JUMP_LABEL (insn
) = olabel
;
6661 LABEL_NUSES (olabel
)++;
6665 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6666 uid_branch
[dest_uid
] = bp
;
6667 bp
->prev
= far_branch_list
;
6668 far_branch_list
= bp
;
6669 bp
->far_label
= as_a
<rtx_insn
*> (
6670 XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
6672 LABEL_NUSES (bp
->far_label
)++;
6676 label
= bp
->near_label
;
6677 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
6679 rtx_insn
*block
= bp
->insert_place
;
6681 if (GET_CODE (PATTERN (block
)) == RETURN
)
6682 block
= PREV_INSN (block
);
6684 block
= gen_block_redirect (block
,
6686 label
= emit_label_after (gen_label_rtx (),
6688 bp
->near_label
= label
;
6690 else if (label
&& ! NEXT_INSN (label
))
6692 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
6693 bp
->insert_place
= insn
;
6695 gen_far_branch (bp
);
6699 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
6701 bp
->near_label
= label
= gen_label_rtx ();
6702 bp
->insert_place
= insn
;
6705 ok
= redirect_jump (as_a
<rtx_jump_insn
*> (insn
), label
, 0);
6710 /* get_attr_length (insn) == 2 */
6711 /* Check if we have a pattern where reorg wants to redirect
6712 the branch to a label from an unconditional branch that
6714 /* We can't use JUMP_LABEL here because it might be undefined
6715 when not optimizing. */
6716 /* A syntax error might cause beyond to be NULL_RTX. */
6718 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
6723 || ((beyond
= next_active_insn (beyond
))
6724 && JUMP_P (beyond
)))
6725 && GET_CODE (PATTERN (beyond
)) == SET
6726 && recog_memoized (beyond
) == CODE_FOR_jump_compact
6728 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
6729 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6731 gen_block_redirect (beyond
,
6732 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
6735 next
= next_active_insn (insn
);
6739 || ((next
= next_active_insn (next
))
6741 && GET_CODE (PATTERN (next
)) == SET
6742 && recog_memoized (next
) == CODE_FOR_jump_compact
6744 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
6745 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6747 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
6749 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
6751 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6752 rtx_insn
*far_label
= 0;
6754 struct far_branch
*bp
;
6756 if (type
== TYPE_JUMP
)
6758 if (CROSSING_JUMP_P (insn
))
6760 emit_insn_before (gen_block_branch_redirect (const0_rtx
),
6765 far_label
= as_a
<rtx_insn
*> (
6766 XEXP (SET_SRC (PATTERN (insn
)), 0));
6767 dest_uid
= get_dest_uid (far_label
, max_uid
);
6770 /* Parse errors can lead to labels outside
6772 if (! NEXT_INSN (far_label
))
6777 JUMP_LABEL (insn
) = far_label
;
6778 LABEL_NUSES (far_label
)++;
6780 redirect_jump (as_a
<rtx_jump_insn
*> (insn
), ret_rtx
, 1);
6784 bp
= uid_branch
[dest_uid
];
6787 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6788 uid_branch
[dest_uid
] = bp
;
6789 bp
->prev
= far_branch_list
;
6790 far_branch_list
= bp
;
6792 bp
->far_label
= far_label
;
6794 LABEL_NUSES (far_label
)++;
6796 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
6797 if (addr
- bp
->address
<= CONDJUMP_MAX
)
6798 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
6801 gen_far_branch (bp
);
6807 bp
->insert_place
= insn
;
6809 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
6811 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
6814 /* Generate all pending far branches,
6815 and free our references to the far labels. */
6816 while (far_branch_list
)
6818 if (far_branch_list
->near_label
6819 && ! NEXT_INSN (far_branch_list
->near_label
))
6820 gen_far_branch (far_branch_list
);
6822 && far_branch_list
->far_label
6823 && ! --LABEL_NUSES (far_branch_list
->far_label
))
6824 delete_insn (far_branch_list
->far_label
);
6825 far_branch_list
= far_branch_list
->prev
;
6828 /* Instruction length information is no longer valid due to the new
6829 instructions that have been generated. */
6830 init_insn_lengths ();
6833 /* Dump out instruction addresses, which is useful for debugging the
6834 constant pool table stuff.
6836 If relaxing, output the label and pseudo-ops used to link together
6837 calls and the instruction which set the registers.
6839 ??? The addresses printed by this routine for insns are nonsense for
6840 insns which are inside of a sequence where none of the inner insns have
6841 variable length. This is because the second pass of shorten_branches
6842 does not bother to update them. */
6844 final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
6845 int noperands ATTRIBUTE_UNUSED
)
6847 if (TARGET_DUMPISIZE
)
6848 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
6854 note
= find_reg_note (insn
, REG_LABEL_OPERAND
, NULL_RTX
);
6859 pattern
= PATTERN (insn
);
6860 if (GET_CODE (pattern
) == PARALLEL
)
6861 pattern
= XVECEXP (pattern
, 0, 0);
6862 switch (GET_CODE (pattern
))
6865 if (GET_CODE (SET_SRC (pattern
)) != CALL
6866 && get_attr_type (insn
) != TYPE_SFUNC
)
6868 targetm
.asm_out
.internal_label
6869 (asm_out_file
, "L", CODE_LABEL_NUMBER (XEXP (note
, 0)));
6872 /* else FALLTHROUGH */
6874 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
6875 CODE_LABEL_NUMBER (XEXP (note
, 0)));
6885 /* Dump out any constants accumulated in the final pass. These will
6888 output_jump_label_table (void)
6894 fprintf (asm_out_file
, "\t.align 2\n");
6895 for (i
= 0; i
< pool_size
; i
++)
6897 pool_node
*p
= &pool_vector
[i
];
6899 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
6900 CODE_LABEL_NUMBER (p
->label
));
6901 output_asm_insn (".long %O0", &p
->value
);
6909 /* A full frame looks like:
6913 [ if current_function_anonymous_args
6926 local-0 <- fp points here.
6928 Number of bytes pushed for anonymous args, used to pass information
6929 between expand_prologue and expand_epilogue.
6931 Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6932 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6933 for an epilogue and a negative value means that it's for a sibcall
6934 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6935 all the registers that are about to be restored, and hence dead. */
6937 output_stack_adjust (int size
, rtx reg
, int epilogue_p
,
6938 HARD_REG_SET
*live_regs_mask
, bool frame_p
)
6940 rtx_insn
*(*emit_fn
) (rtx
) = frame_p
? &frame_insn
: &emit_insn
;
6943 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6945 /* This test is bogus, as output_stack_adjust is used to re-align the
6948 gcc_assert (!(size
% align
));
6951 if (CONST_OK_FOR_ADD (size
))
6952 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
6953 /* Try to do it with two partial adjustments; however, we must make
6954 sure that the stack is properly aligned at all times, in case
6955 an interrupt occurs between the two partial adjustments. */
6956 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
6957 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
6959 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
6960 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
6966 int temp
= epilogue_p
? 7 : (TARGET_SH5
? 0 : 1);
6969 /* If TEMP is invalid, we could temporarily save a general
6970 register to MACL. However, there is currently no need
6971 to handle this case, so just die when we see it. */
6973 || current_function_interrupt
6974 || ! call_really_used_regs
[temp
] || fixed_regs
[temp
])
6976 if (temp
< 0 && ! current_function_interrupt
6977 && (TARGET_SHMEDIA
|| epilogue_p
>= 0))
6980 COPY_HARD_REG_SET (temps
, call_used_reg_set
);
6981 AND_COMPL_HARD_REG_SET (temps
, call_fixed_reg_set
);
6985 if (crtl
->return_rtx
)
6988 mode
= GET_MODE (crtl
->return_rtx
);
6989 if (BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
)
6990 nreg
= HARD_REGNO_NREGS (FIRST_RET_REG
, mode
);
6992 for (i
= 0; i
< nreg
; i
++)
6993 CLEAR_HARD_REG_BIT (temps
, FIRST_RET_REG
+ i
);
6994 if (crtl
->calls_eh_return
)
6996 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_STACKADJ_REGNO
);
6997 for (i
= 0; i
<= 3; i
++)
6998 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_DATA_REGNO (i
));
7001 if (TARGET_SHMEDIA
&& epilogue_p
< 0)
7002 for (i
= FIRST_TARGET_REG
; i
<= LAST_TARGET_REG
; i
++)
7003 CLEAR_HARD_REG_BIT (temps
, i
);
7004 if (epilogue_p
<= 0)
7006 for (i
= FIRST_PARM_REG
;
7007 i
< FIRST_PARM_REG
+ NPARM_REGS (SImode
); i
++)
7008 CLEAR_HARD_REG_BIT (temps
, i
);
7009 if (cfun
->static_chain_decl
!= NULL
)
7010 CLEAR_HARD_REG_BIT (temps
, STATIC_CHAIN_REGNUM
);
7012 temp
= scavenge_reg (&temps
);
7014 if (temp
< 0 && live_regs_mask
)
7018 COPY_HARD_REG_SET (temps
, *live_regs_mask
);
7019 CLEAR_HARD_REG_BIT (temps
, REGNO (reg
));
7020 temp
= scavenge_reg (&temps
);
7024 rtx adj_reg
, tmp_reg
, mem
;
7026 /* If we reached here, the most likely case is the (sibcall)
7027 epilogue for non SHmedia. Put a special push/pop sequence
7028 for such case as the last resort. This looks lengthy but
7029 would not be problem because it seems to be very
7032 gcc_assert (!TARGET_SHMEDIA
&& epilogue_p
);
7035 /* ??? There is still the slight possibility that r4 or
7036 r5 have been reserved as fixed registers or assigned
7037 as global registers, and they change during an
7038 interrupt. There are possible ways to handle this:
7040 - If we are adjusting the frame pointer (r14), we can do
7041 with a single temp register and an ordinary push / pop
7043 - Grab any call-used or call-saved registers (i.e. not
7044 fixed or globals) for the temps we need. We might
7045 also grab r14 if we are adjusting the stack pointer.
7046 If we can't find enough available registers, issue
7047 a diagnostic and die - the user must have reserved
7048 way too many registers.
7049 But since all this is rather unlikely to happen and
7050 would require extra testing, we just die if r4 / r5
7051 are not available. */
7052 gcc_assert (!fixed_regs
[4] && !fixed_regs
[5]
7053 && !global_regs
[4] && !global_regs
[5]);
7055 adj_reg
= gen_rtx_REG (GET_MODE (reg
), 4);
7056 tmp_reg
= gen_rtx_REG (GET_MODE (reg
), 5);
7057 emit_move_insn (gen_tmp_stack_mem (Pmode
, reg
), adj_reg
);
7058 emit_insn (GEN_MOV (adj_reg
, GEN_INT (size
)));
7059 emit_insn (GEN_ADD3 (adj_reg
, adj_reg
, reg
));
7060 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
7061 emit_move_insn (mem
, tmp_reg
);
7062 emit_move_insn (tmp_reg
, gen_tmp_stack_mem (Pmode
, reg
));
7063 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
7064 emit_move_insn (mem
, tmp_reg
);
7065 emit_move_insn (reg
, adj_reg
);
7066 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
7067 emit_move_insn (adj_reg
, mem
);
7068 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
7069 emit_move_insn (tmp_reg
, mem
);
7070 /* Tell flow the insns that pop r4/r5 aren't dead. */
7075 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
7077 /* If SIZE is negative, subtract the positive value.
7078 This sometimes allows a constant pool entry to be shared
7079 between prologue and epilogue code. */
7082 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
7083 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
7087 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
7088 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
7090 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7091 gen_rtx_SET (reg
, gen_rtx_PLUS (SImode
, reg
,
7097 /* Emit the specified insn and mark it as frame related.
7098 FIXME: Rename this to emit_frame_insn. */
7102 rtx_insn
*insn
= emit_insn (x
);
7103 RTX_FRAME_RELATED_P (insn
) = 1;
7107 /* Output RTL to push register RN onto the stack. */
7113 x
= gen_push_fpul ();
7114 else if (rn
== FPSCR_REG
)
7115 x
= gen_push_fpscr ();
7116 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
7117 && ! TARGET_FPU_SINGLE
&& FP_OR_XD_REGISTER_P (rn
))
7119 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
7121 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
7123 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
7124 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
7126 x
= gen_push (gen_rtx_REG (SImode
, rn
));
7129 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
7133 /* Output RTL to pop register RN from the stack. */
7139 x
= gen_pop_fpul ();
7140 else if (rn
== FPSCR_REG
)
7141 x
= gen_pop_fpscr ();
7142 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
7143 && ! TARGET_FPU_SINGLE
&& FP_OR_XD_REGISTER_P (rn
))
7145 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
7147 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
7149 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
7150 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
7152 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
7156 sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
7157 reg
= copy_rtx (GET_CODE (PATTERN (x
)) == PARALLEL
7158 ? SET_DEST (XVECEXP (PATTERN (x
), 0, 0))
7159 : SET_DEST (PATTERN (x
)));
7160 add_reg_note (x
, REG_CFA_RESTORE
, reg
);
7161 add_reg_note (x
, REG_CFA_ADJUST_CFA
,
7162 gen_rtx_SET (sp_reg
,
7163 plus_constant (SImode
, sp_reg
,
7164 GET_MODE_SIZE (GET_MODE (reg
)))));
7165 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
7166 RTX_FRAME_RELATED_P (x
) = 1;
7169 /* Generate code to push the regs specified in the mask. */
7171 push_regs (HARD_REG_SET
*mask
, int interrupt_handler
)
7173 int i
= interrupt_handler
? LAST_BANKED_REG
+ 1 : 0;
7176 /* Push PR last; this gives better latencies after the prologue, and
7177 candidates for the return delay slot when there are no general
7178 registers pushed. */
7179 for (; i
< FIRST_PSEUDO_REGISTER
; i
++)
7181 /* If this is an interrupt handler, and the SZ bit varies,
7182 and we have to push any floating point register, we need
7183 to switch to the correct precision first. */
7184 if (i
== FIRST_FP_REG
&& interrupt_handler
&& TARGET_FMOVD
7185 && hard_reg_set_intersect_p (*mask
, reg_class_contents
[DF_REGS
]))
7187 HARD_REG_SET unsaved
;
7190 COMPL_HARD_REG_SET (unsaved
, *mask
);
7191 fpscr_set_from_mem (NORMAL_MODE (FP_MODE
), unsaved
);
7195 && (i
!= FPSCR_REG
|| ! skip_fpscr
)
7196 && TEST_HARD_REG_BIT (*mask
, i
))
7198 /* If the ISR has RESBANK attribute assigned, don't push any of
7199 the following registers - R0-R14, MACH, MACL and GBR. */
7200 if (! (sh_cfun_resbank_handler_p ()
7201 && ((i
>= FIRST_GENERAL_REG
&& i
< LAST_GENERAL_REG
)
7209 /* Push banked registers last to improve delay slot opportunities. */
7210 if (interrupt_handler
)
7212 bool use_movml
= false;
7216 unsigned int count
= 0;
7218 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7219 if (TEST_HARD_REG_BIT (*mask
, i
))
7224 /* Use movml when all banked registers are pushed. */
7225 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
7229 if (sh_cfun_resbank_handler_p ())
7233 rtx x
, mem
, reg
, set
;
7234 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
7236 /* We must avoid scheduling multiple store insn with another
7238 emit_insn (gen_blockage ());
7239 x
= gen_movml_push_banked (sp_reg
);
7241 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7243 mem
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp_reg
, i
* 4));
7244 reg
= gen_rtx_REG (SImode
, i
);
7245 add_reg_note (x
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, reg
));
7248 set
= gen_rtx_SET (sp_reg
, plus_constant (Pmode
, sp_reg
, - 32));
7249 add_reg_note (x
, REG_CFA_ADJUST_CFA
, set
);
7250 emit_insn (gen_blockage ());
7253 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7254 if (TEST_HARD_REG_BIT (*mask
, i
))
7258 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
7259 if (TEST_HARD_REG_BIT (*mask
, PR_REG
) && !sh_cfun_resbank_handler_p ())
7263 /* Calculate how much extra space is needed to save all callee-saved
7265 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
7267 shmedia_target_regs_stack_space (HARD_REG_SET
*live_regs_mask
)
7270 int stack_space
= 0;
7271 int interrupt_handler
= sh_cfun_interrupt_handler_p ();
7273 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
7274 if ((! call_really_used_regs
[reg
] || interrupt_handler
)
7275 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
7276 /* Leave space to save this target register on the stack,
7277 in case target register allocation wants to use it. */
7278 stack_space
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7282 /* Decide whether we should reserve space for callee-save target registers,
7283 in case target register allocation wants to use them. REGS_SAVED is
7284 the space, in bytes, that is already required for register saves.
7285 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
7287 shmedia_reserve_space_for_target_registers_p (int regs_saved
,
7288 HARD_REG_SET
*live_regs_mask
)
7292 return shmedia_target_regs_stack_space (live_regs_mask
) <= regs_saved
;
7295 /* Decide how much space to reserve for callee-save target registers
7296 in case target register allocation wants to use them.
7297 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
7299 shmedia_target_regs_stack_adjust (HARD_REG_SET
*live_regs_mask
)
7301 if (shmedia_space_reserved_for_target_registers
)
7302 return shmedia_target_regs_stack_space (live_regs_mask
);
7307 /* Work out the registers which need to be saved, both as a mask and a
7308 count of saved words. Return the count.
7310 If doing a pragma interrupt function, then push all regs used by the
7311 function, and if we call another function (we can tell by looking at PR),
7312 make sure that all the regs it clobbers are safe too. */
7314 calc_live_regs (HARD_REG_SET
*live_regs_mask
)
7319 bool interrupt_or_trapa_handler
, trapa_handler
, interrupt_handler
;
7320 bool nosave_low_regs
;
7321 int pr_live
, has_call
;
7323 attrs
= DECL_ATTRIBUTES (current_function_decl
);
7324 interrupt_or_trapa_handler
= sh_cfun_interrupt_handler_p ();
7325 trapa_handler
= lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
;
7326 interrupt_handler
= interrupt_or_trapa_handler
&& ! trapa_handler
;
7327 nosave_low_regs
= lookup_attribute ("nosave_low_regs", attrs
) != NULL_TREE
;
7329 CLEAR_HARD_REG_SET (*live_regs_mask
);
7330 if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
&& interrupt_handler
7331 && df_regs_ever_live_p (FPSCR_REG
))
7332 target_flags
&= ~MASK_FPU_SINGLE
;
7333 /* If we can save a lot of saves by switching to double mode, do that. */
7334 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
7335 && TARGET_FPU_SINGLE
)
7336 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
7337 if (df_regs_ever_live_p (reg
) && df_regs_ever_live_p (reg
+1)
7338 && (! call_really_used_regs
[reg
]
7339 || interrupt_handler
)
7342 target_flags
&= ~MASK_FPU_SINGLE
;
7345 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
7346 knows how to use it. That means the pseudo originally allocated for
7347 the initial value can become the PR_MEDIA_REG hard register, as seen for
7348 execute/20010122-1.c:test9. */
7350 /* ??? this function is called from initial_elimination_offset, hence we
7351 can't use the result of sh_media_register_for_return here. */
7352 pr_live
= sh_pr_n_sets ();
7355 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
7356 pr_live
= (pr_initial
7357 ? (!REG_P (pr_initial
)
7358 || REGNO (pr_initial
) != (PR_REG
))
7359 : df_regs_ever_live_p (PR_REG
));
7360 /* For Shcompact, if not optimizing, we end up with a memory reference
7361 using the return address pointer for __builtin_return_address even
7362 though there is no actual need to put the PR register on the stack. */
7363 pr_live
|= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM
);
7365 /* Force PR to be live if the prologue has to call the SHmedia
7366 argument decoder or register saver. */
7367 if (TARGET_SHCOMPACT
7368 && ((crtl
->args
.info
.call_cookie
7369 & ~ CALL_COOKIE_RET_TRAMP (1))
7370 || crtl
->saves_all_registers
))
7372 has_call
= TARGET_SHMEDIA
? ! leaf_function_p () : pr_live
;
7373 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
; reg
-- != 0; )
7375 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
7378 ? (/* Need to save all the regs ever live. */
7379 (df_regs_ever_live_p (reg
)
7380 || (call_really_used_regs
[reg
]
7381 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
7382 || reg
== PIC_OFFSET_TABLE_REGNUM
)
7384 || (TARGET_SHMEDIA
&& has_call
7385 && REGISTER_NATURAL_MODE (reg
) == SImode
7386 && (GENERAL_REGISTER_P (reg
) || TARGET_REGISTER_P (reg
))))
7387 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
7388 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
7389 && reg
!= T_REG
&& reg
!= GBR_REG
7390 && reg
!= FPSCR_MODES_REG
&& reg
!= FPSCR_STAT_REG
7391 /* Push fpscr only on targets which have FPU */
7392 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
7393 : (/* Only push those regs which are used and need to be saved. */
7396 && crtl
->args
.info
.call_cookie
7397 && reg
== PIC_OFFSET_TABLE_REGNUM
)
7398 || (df_regs_ever_live_p (reg
)
7399 && ((!call_really_used_regs
[reg
]
7400 && !(reg
!= PIC_OFFSET_TABLE_REGNUM
7401 && fixed_regs
[reg
] && call_used_regs
[reg
]))
7402 || (trapa_handler
&& reg
== FPSCR_REG
&& TARGET_FPU_ANY
)))
7403 || (crtl
->calls_eh_return
7404 && (reg
== EH_RETURN_DATA_REGNO (0)
7405 || reg
== EH_RETURN_DATA_REGNO (1)
7406 || reg
== EH_RETURN_DATA_REGNO (2)
7407 || reg
== EH_RETURN_DATA_REGNO (3)))
7408 || ((reg
== MACL_REG
|| reg
== MACH_REG
)
7409 && df_regs_ever_live_p (reg
)
7410 && sh_cfun_attr_renesas_p ())
7413 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
7414 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7416 if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
|| TARGET_SH5
) && TARGET_FMOVD
7417 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
7419 if (FP_REGISTER_P (reg
))
7421 if (! TARGET_FPU_SINGLE
&& ! df_regs_ever_live_p (reg
^ 1))
7423 SET_HARD_REG_BIT (*live_regs_mask
, (reg
^ 1));
7424 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
7427 else if (XD_REGISTER_P (reg
))
7429 /* Must switch to double mode to access these registers. */
7430 target_flags
&= ~MASK_FPU_SINGLE
;
7434 if (nosave_low_regs
&& reg
== R8_REG
)
7437 /* If we have a target register optimization pass after prologue / epilogue
7438 threading, we need to assume all target registers will be live even if
7440 if (flag_branch_target_load_optimize2
7441 && TARGET_SAVE_ALL_TARGET_REGS
7442 && shmedia_space_reserved_for_target_registers
)
7443 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
7444 if ((! call_really_used_regs
[reg
] || interrupt_handler
)
7445 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
7447 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
7448 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7450 /* If this is an interrupt handler, we don't have any call-clobbered
7451 registers we can conveniently use for target register save/restore.
7452 Make sure we save at least one general purpose register when we need
7453 to save target registers. */
7454 if (interrupt_handler
7455 && hard_reg_set_intersect_p (*live_regs_mask
,
7456 reg_class_contents
[TARGET_REGS
])
7457 && ! hard_reg_set_intersect_p (*live_regs_mask
,
7458 reg_class_contents
[GENERAL_REGS
]))
7460 SET_HARD_REG_BIT (*live_regs_mask
, R0_REG
);
7461 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG
));
7467 /* Code to generate prologue and epilogue sequences */
7469 /* PUSHED is the number of bytes that are being pushed on the
7470 stack for register saves. Return the frame size, padded
7471 appropriately so that the stack stays properly aligned. */
7472 static HOST_WIDE_INT
7473 rounded_frame_size (int pushed
)
7475 HOST_WIDE_INT size
= get_frame_size ();
7476 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7478 if (ACCUMULATE_OUTGOING_ARGS
)
7479 size
+= crtl
->outgoing_args_size
;
7481 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
7484 /* Choose a call-clobbered target-branch register that remains
7485 unchanged along the whole function. We set it up as the return
7486 value in the prologue. */
7488 sh_media_register_for_return (void)
7493 if (! crtl
->is_leaf
)
7495 if (lookup_attribute ("interrupt_handler",
7496 DECL_ATTRIBUTES (current_function_decl
)))
7498 if (sh_cfun_interrupt_handler_p ())
7501 tr0_used
= flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7503 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
7504 if (call_really_used_regs
[regno
] && ! df_regs_ever_live_p (regno
))
7510 /* The maximum registers we need to save are:
7511 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
7512 - 32 floating point registers (for each pair, we save none,
7513 one single precision value, or a double precision value).
7514 - 8 target registers
7515 - add 1 entry for a delimiter. */
7516 #define MAX_SAVED_REGS (62+32+8)
7518 typedef struct save_entry_s
7527 /* There will be a delimiter entry with VOIDmode both at the start and the
7528 end of a filled in schedule. The end delimiter has the offset of the
7529 save with the smallest (i.e. most negative) offset. */
7530 typedef struct save_schedule_s
7532 save_entry entries
[MAX_SAVED_REGS
+ 2];
7533 int temps
[MAX_TEMPS
+1];
7536 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
7537 use reverse order. Returns the last entry written to (not counting
7538 the delimiter). OFFSET_BASE is a number to be added to all offset
7541 sh5_schedule_saves (HARD_REG_SET
*live_regs_mask
, save_schedule
*schedule
,
7545 save_entry
*entry
= schedule
->entries
;
7549 if (! current_function_interrupt
)
7550 for (i
= FIRST_GENERAL_REG
; tmpx
< MAX_TEMPS
&& i
<= LAST_GENERAL_REG
; i
++)
7551 if (call_really_used_regs
[i
] && ! fixed_regs
[i
] && i
!= PR_MEDIA_REG
7552 && ! FUNCTION_ARG_REGNO_P (i
)
7553 && i
!= FIRST_RET_REG
7554 && ! (cfun
->static_chain_decl
!= NULL
&& i
== STATIC_CHAIN_REGNUM
)
7555 && ! (crtl
->calls_eh_return
7556 && (i
== EH_RETURN_STACKADJ_REGNO
7557 || ((unsigned) i
>= EH_RETURN_DATA_REGNO (0)
7558 && (unsigned) i
<= EH_RETURN_DATA_REGNO (3)))))
7559 schedule
->temps
[tmpx
++] = i
;
7561 entry
->mode
= VOIDmode
;
7562 entry
->offset
= offset_base
;
7564 /* We loop twice: first, we save 8-byte aligned registers in the
7565 higher addresses, that are known to be aligned. Then, we
7566 proceed to saving 32-bit registers that don't need 8-byte
7568 If this is an interrupt function, all registers that need saving
7569 need to be saved in full. moreover, we need to postpone saving
7570 target registers till we have saved some general purpose registers
7571 we can then use as scratch registers. */
7572 offset
= offset_base
;
7573 for (align
= 1; align
>= 0; align
--)
7575 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
7576 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
7578 machine_mode mode
= REGISTER_NATURAL_MODE (i
);
7581 if (current_function_interrupt
)
7583 if (TARGET_REGISTER_P (i
))
7585 if (GENERAL_REGISTER_P (i
))
7588 if (mode
== SFmode
&& (i
% 2) == 1
7589 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
7590 && (TEST_HARD_REG_BIT (*live_regs_mask
, (i
^ 1))))
7597 /* If we're doing the aligned pass and this is not aligned,
7598 or we're doing the unaligned pass and this is aligned,
7600 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
) == 0)
7604 if (current_function_interrupt
7605 && GENERAL_REGISTER_P (i
)
7606 && tmpx
< MAX_TEMPS
)
7607 schedule
->temps
[tmpx
++] = i
;
7609 offset
-= GET_MODE_SIZE (mode
);
7612 entry
->offset
= offset
;
7615 if (align
&& current_function_interrupt
)
7616 for (i
= LAST_TARGET_REG
; i
>= FIRST_TARGET_REG
; i
--)
7617 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
7619 offset
-= GET_MODE_SIZE (DImode
);
7621 entry
->mode
= DImode
;
7622 entry
->offset
= offset
;
7627 entry
->mode
= VOIDmode
;
7628 entry
->offset
= offset
;
7629 schedule
->temps
[tmpx
] = -1;
7633 /* Expand code for the function prologue. */
7635 sh_expand_prologue (void)
7637 HARD_REG_SET live_regs_mask
;
7640 int save_flags
= target_flags
;
7644 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
));
7646 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
7648 /* We have pretend args if we had an object sent partially in registers
7649 and partially on the stack, e.g. a large structure. */
7650 pretend_args
= crtl
->args
.pretend_args_size
;
7651 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
)
7652 && (NPARM_REGS(SImode
)
7653 > crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]))
7656 output_stack_adjust (-pretend_args
7657 - crtl
->args
.info
.stack_regs
* 8,
7658 stack_pointer_rtx
, 0, NULL
, true);
7659 stack_usage
= pretend_args
+ crtl
->args
.info
.stack_regs
* 8;
7661 if (TARGET_SHCOMPACT
&& flag_pic
&& crtl
->args
.info
.call_cookie
)
7662 /* We're going to use the PIC register to load the address of the
7663 incoming-argument decoder and/or of the return trampoline from
7664 the GOT, so make sure the PIC register is preserved and
7666 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
7668 if (TARGET_SHCOMPACT
7669 && (crtl
->args
.info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
7673 /* First, make all registers with incoming arguments that will
7674 be pushed onto the stack live, so that register renaming
7675 doesn't overwrite them. */
7676 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
7677 if (CALL_COOKIE_STACKSEQ_GET (crtl
->args
.info
.call_cookie
)
7678 >= NPARM_REGS (SImode
) - reg
)
7679 for (; reg
< NPARM_REGS (SImode
); reg
++)
7680 emit_insn (gen_shcompact_preserve_incoming_args
7681 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
7682 else if (CALL_COOKIE_INT_REG_GET
7683 (crtl
->args
.info
.call_cookie
, reg
) == 1)
7684 emit_insn (gen_shcompact_preserve_incoming_args
7685 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
7687 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
7689 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
7690 GEN_INT (crtl
->args
.info
.call_cookie
));
7691 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
7692 gen_rtx_REG (SImode
, R0_REG
));
7694 else if (TARGET_SHMEDIA
)
7696 int tr
= sh_media_register_for_return ();
7699 emit_move_insn (gen_rtx_REG (DImode
, tr
),
7700 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
7703 /* Emit the code for SETUP_VARARGS. */
7706 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
7708 /* Push arg regs as if they'd been provided by caller in stack. */
7709 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
7711 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
7713 if (i
>= (NPARM_REGS(SImode
)
7714 - crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]
7718 stack_usage
+= GET_MODE_SIZE (SImode
);
7723 /* If we're supposed to switch stacks at function entry, do so now. */
7727 /* The argument specifies a variable holding the address of the
7728 stack the interrupt function should switch to/from at entry/exit. */
7729 tree arg
= TREE_VALUE ( TREE_VALUE (sp_switch_attr
));
7731 = ggc_strdup (TREE_STRING_POINTER (arg
));
7732 rtx sp_switch
= gen_rtx_SYMBOL_REF (Pmode
, s
);
7734 lab
= add_constant (sp_switch
, SImode
, 0);
7735 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
7737 emit_insn (gen_sp_switch_1 (newsrc
));
7740 d
= calc_live_regs (&live_regs_mask
);
7741 /* ??? Maybe we could save some switching if we can move a mode switch
7742 that already happens to be at the function start into the prologue. */
7743 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7744 emit_insn (gen_toggle_sz ());
7748 int offset_base
, offset
;
7750 int offset_in_r0
= -1;
7752 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
7753 int total_size
, save_size
;
7754 save_schedule schedule
;
7758 if (call_really_used_regs
[R0_REG
] && ! fixed_regs
[R0_REG
]
7759 && ! current_function_interrupt
)
7760 r0
= gen_rtx_REG (Pmode
, R0_REG
);
7762 /* D is the actual number of bytes that we need for saving registers,
7763 however, in initial_elimination_offset we have committed to using
7764 an additional TREGS_SPACE amount of bytes - in order to keep both
7765 addresses to arguments supplied by the caller and local variables
7766 valid, we must keep this gap. Place it between the incoming
7767 arguments and the actually saved registers in a bid to optimize
7768 locality of reference. */
7769 total_size
= d
+ tregs_space
;
7770 total_size
+= rounded_frame_size (total_size
);
7771 save_size
= total_size
- rounded_frame_size (d
);
7772 if (save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
7773 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
7774 - save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
7776 /* If adjusting the stack in a single step costs nothing extra, do so.
7777 I.e. either if a single addi is enough, or we need a movi anyway,
7778 and we don't exceed the maximum offset range (the test for the
7779 latter is conservative for simplicity). */
7781 && (CONST_OK_FOR_I10 (-total_size
)
7782 || (! CONST_OK_FOR_I10 (-(save_size
+ d_rounding
))
7783 && total_size
<= 2044)))
7784 d_rounding
= total_size
- save_size
;
7786 offset_base
= d
+ d_rounding
;
7788 output_stack_adjust (-(save_size
+ d_rounding
), stack_pointer_rtx
,
7790 stack_usage
+= save_size
+ d_rounding
;
7792 sh5_schedule_saves (&live_regs_mask
, &schedule
, offset_base
);
7793 tmp_pnt
= schedule
.temps
;
7794 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
7796 machine_mode mode
= (machine_mode
) entry
->mode
;
7797 unsigned int reg
= entry
->reg
;
7798 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
7801 offset
= entry
->offset
;
7803 reg_rtx
= gen_rtx_REG (mode
, reg
);
7805 mem_rtx
= gen_frame_mem (mode
,
7806 gen_rtx_PLUS (Pmode
,
7810 if (!memory_address_p (mode
, XEXP (mem_rtx
, 0)))
7816 if (HAVE_PRE_DECREMENT
7817 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
7818 || mem_rtx
== NULL_RTX
7819 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
7821 pre_dec
= gen_frame_mem (mode
, gen_rtx_PRE_DEC (Pmode
, r0
));
7823 if (!memory_address_p (mode
, XEXP (pre_dec
, 0)))
7828 offset
+= GET_MODE_SIZE (mode
);
7832 if (mem_rtx
!= NULL_RTX
)
7835 if (offset_in_r0
== -1)
7837 emit_move_insn (r0
, GEN_INT (offset
));
7838 offset_in_r0
= offset
;
7840 else if (offset
!= offset_in_r0
)
7845 GEN_INT (offset
- offset_in_r0
)));
7846 offset_in_r0
+= offset
- offset_in_r0
;
7849 if (pre_dec
!= NULL_RTX
)
7855 (Pmode
, r0
, stack_pointer_rtx
));
7859 offset
-= GET_MODE_SIZE (mode
);
7860 offset_in_r0
-= GET_MODE_SIZE (mode
);
7865 mem_rtx
= gen_frame_mem (mode
, r0
);
7867 mem_rtx
= gen_frame_mem (mode
,
7868 gen_rtx_PLUS (Pmode
,
7872 /* We must not use an r0-based address for target-branch
7873 registers or for special registers without pre-dec
7874 memory addresses, since we store their values in r0
7876 gcc_assert (!TARGET_REGISTER_P (reg
)
7877 && ((reg
!= PR_REG
&& !SPECIAL_REGISTER_P (reg
))
7878 || mem_rtx
== pre_dec
));
7881 orig_reg_rtx
= reg_rtx
;
7882 if (TARGET_REGISTER_P (reg
)
7883 || ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
7884 && mem_rtx
!= pre_dec
))
7886 rtx tmp_reg
= gen_rtx_REG (GET_MODE (reg_rtx
), *tmp_pnt
);
7888 emit_move_insn (tmp_reg
, reg_rtx
);
7890 if (REGNO (tmp_reg
) == R0_REG
)
7894 gcc_assert (!refers_to_regno_p (R0_REG
, mem_rtx
));
7897 if (*++tmp_pnt
<= 0)
7898 tmp_pnt
= schedule
.temps
;
7905 /* Mark as interesting for dwarf cfi generator */
7906 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
7907 RTX_FRAME_RELATED_P (insn
) = 1;
7908 /* If we use an intermediate register for the save, we can't
7909 describe this exactly in cfi as a copy of the to-be-saved
7910 register into the temporary register and then the temporary
7911 register on the stack, because the temporary register can
7912 have a different natural size than the to-be-saved register.
7913 Thus, we gloss over the intermediate copy and pretend we do
7914 a direct save from the to-be-saved register. */
7915 if (REGNO (reg_rtx
) != reg
)
7919 set
= gen_rtx_SET (mem_rtx
, orig_reg_rtx
);
7920 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
7923 if (TARGET_SHCOMPACT
&& (offset_in_r0
!= -1))
7925 rtx reg_rtx
= gen_rtx_REG (mode
, reg
);
7927 rtx mem_rtx
= gen_frame_mem (mode
,
7928 gen_rtx_PLUS (Pmode
,
7932 set
= gen_rtx_SET (mem_rtx
, reg_rtx
);
7933 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
7938 gcc_assert (entry
->offset
== d_rounding
);
7942 push_regs (&live_regs_mask
, current_function_interrupt
);
7946 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7947 emit_insn (gen_GOTaddr2picreg (const0_rtx
));
7949 if (SHMEDIA_REGS_STACK_ADJUST ())
7951 /* This must NOT go through the PLT, otherwise mach and macl
7952 may be clobbered. */
7953 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7955 ? "__GCC_push_shmedia_regs"
7956 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT
);
7957 emit_insn (gen_shmedia_save_restore_regs_compact
7958 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7961 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7962 emit_insn (gen_toggle_sz ());
7964 target_flags
= save_flags
;
7966 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
7967 stack_pointer_rtx
, 0, NULL
, true);
7968 stack_usage
+= rounded_frame_size (d
) - d_rounding
;
7970 if (frame_pointer_needed
)
7971 frame_insn (GEN_MOV (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7973 if (TARGET_SHCOMPACT
7974 && (crtl
->args
.info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
7976 /* This must NOT go through the PLT, otherwise mach and macl
7977 may be clobbered. */
7978 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7979 "__GCC_shcompact_incoming_args", SFUNC_GOT
);
7980 emit_insn (gen_shcompact_incoming_args ());
7983 /* If we are profiling, make sure no instructions are scheduled before
7984 the call to mcount. Similarly if some call instructions are swapped
7985 before frame related insns, it'll confuse the unwinder because
7986 currently SH has no unwind info for function epilogues. */
7987 if (crtl
->profile
|| flag_exceptions
|| flag_unwind_tables
)
7988 emit_insn (gen_blockage ());
7990 if (flag_stack_usage_info
)
7991 current_function_static_stack_size
= stack_usage
;
7994 /* Expand code for the function epilogue. */
7996 sh_expand_epilogue (bool sibcall_p
)
7998 HARD_REG_SET live_regs_mask
;
8002 int save_flags
= target_flags
;
8003 int frame_size
, save_size
;
8004 int fpscr_deferred
= 0;
8005 int e
= sibcall_p
? -1 : 1;
8007 d
= calc_live_regs (&live_regs_mask
);
8010 frame_size
= rounded_frame_size (d
);
8014 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
8016 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
8017 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
8018 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
8020 total_size
= d
+ tregs_space
;
8021 total_size
+= rounded_frame_size (total_size
);
8022 save_size
= total_size
- frame_size
;
8024 /* If adjusting the stack in a single step costs nothing extra, do so.
8025 I.e. either if a single addi is enough, or we need a movi anyway,
8026 and we don't exceed the maximum offset range (the test for the
8027 latter is conservative for simplicity). */
8029 && ! frame_pointer_needed
8030 && (CONST_OK_FOR_I10 (total_size
)
8031 || (! CONST_OK_FOR_I10 (save_size
+ d_rounding
)
8032 && total_size
<= 2044)))
8033 d_rounding
= frame_size
;
8035 frame_size
-= d_rounding
;
8038 if (frame_pointer_needed
)
8040 /* We must avoid scheduling the epilogue with previous basic blocks.
8041 See PR/18032 and PR/40313. */
8042 emit_insn (gen_blockage ());
8043 output_stack_adjust (frame_size
, hard_frame_pointer_rtx
, e
,
8044 &live_regs_mask
, true);
8046 /* We must avoid moving the stack pointer adjustment past code
8047 which reads from the local frame, else an interrupt could
8048 occur after the SP adjustment and clobber data in the local
8050 emit_insn (gen_blockage ());
8051 frame_insn (GEN_MOV (stack_pointer_rtx
, hard_frame_pointer_rtx
));
8053 else if (frame_size
)
8055 /* We must avoid moving the stack pointer adjustment past code
8056 which reads from the local frame, else an interrupt could
8057 occur after the SP adjustment and clobber data in the local
8059 emit_insn (gen_blockage ());
8060 output_stack_adjust (frame_size
, stack_pointer_rtx
, e
,
8061 &live_regs_mask
, true);
8064 if (SHMEDIA_REGS_STACK_ADJUST ())
8066 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
8068 ? "__GCC_pop_shmedia_regs"
8069 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT
);
8070 /* This must NOT go through the PLT, otherwise mach and macl
8071 may be clobbered. */
8072 emit_insn (gen_shmedia_save_restore_regs_compact
8073 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
8076 /* Pop all the registers. */
8078 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
8079 emit_insn (gen_toggle_sz ());
8082 int offset_base
, offset
;
8083 int offset_in_r0
= -1;
8085 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
8086 save_schedule schedule
;
8090 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, d_rounding
);
8091 offset_base
= -entry
[1].offset
+ d_rounding
;
8092 tmp_pnt
= schedule
.temps
;
8093 for (; entry
->mode
!= VOIDmode
; entry
--)
8095 machine_mode mode
= (machine_mode
) entry
->mode
;
8096 int reg
= entry
->reg
;
8097 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
;
8099 offset
= offset_base
+ entry
->offset
;
8100 reg_rtx
= gen_rtx_REG (mode
, reg
);
8102 mem_rtx
= gen_frame_mem (mode
,
8103 gen_rtx_PLUS (Pmode
,
8107 if (!memory_address_p (mode
, XEXP (mem_rtx
, 0)))
8110 if (HAVE_POST_INCREMENT
8111 && (offset
== offset_in_r0
8112 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
8113 && mem_rtx
== NULL_RTX
)
8114 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
8116 post_inc
= gen_frame_mem (mode
, gen_rtx_POST_INC (Pmode
, r0
));
8118 if (!memory_address_p (mode
, XEXP (post_inc
, 0)))
8119 post_inc
= NULL_RTX
;
8124 if (mem_rtx
!= NULL_RTX
)
8127 if (offset_in_r0
== -1)
8129 emit_move_insn (r0
, GEN_INT (offset
));
8130 offset_in_r0
= offset
;
8132 else if (offset
!= offset_in_r0
)
8137 GEN_INT (offset
- offset_in_r0
)));
8138 offset_in_r0
+= offset
- offset_in_r0
;
8141 if (post_inc
!= NULL_RTX
)
8147 (Pmode
, r0
, stack_pointer_rtx
));
8153 offset_in_r0
+= GET_MODE_SIZE (mode
);
8156 mem_rtx
= gen_frame_mem (mode
, r0
);
8158 mem_rtx
= gen_frame_mem (mode
,
8159 gen_rtx_PLUS (Pmode
,
8163 gcc_assert ((reg
!= PR_REG
&& !SPECIAL_REGISTER_P (reg
))
8164 || mem_rtx
== post_inc
);
8167 if ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
8168 && mem_rtx
!= post_inc
)
8170 emit_move_insn (r0
, mem_rtx
);
8173 else if (TARGET_REGISTER_P (reg
))
8175 rtx tmp_reg
= gen_rtx_REG (mode
, *tmp_pnt
);
8177 /* Give the scheduler a bit of freedom by using up to
8178 MAX_TEMPS registers in a round-robin fashion. */
8179 emit_move_insn (tmp_reg
, mem_rtx
);
8182 tmp_pnt
= schedule
.temps
;
8185 emit_move_insn (reg_rtx
, mem_rtx
);
8188 gcc_assert (entry
->offset
+ offset_base
== d
+ d_rounding
);
8190 else /* ! TARGET_SH5 */
8195 /* For an ISR with RESBANK attribute assigned, don't pop PR
8197 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
)
8198 && !sh_cfun_resbank_handler_p ())
8200 if (!frame_pointer_needed
)
8201 emit_insn (gen_blockage ());
8205 /* Banked registers are popped first to avoid being scheduled in the
8206 delay slot. RTE switches banks before the ds instruction. */
8207 if (current_function_interrupt
)
8209 bool use_movml
= false;
8213 unsigned int count
= 0;
8215 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
8216 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
8221 /* Use movml when all banked register are poped. */
8222 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
8226 if (sh_cfun_resbank_handler_p ())
8230 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
8232 /* We must avoid scheduling multiple load insn with another
8234 emit_insn (gen_blockage ());
8235 emit_insn (gen_movml_pop_banked (sp_reg
));
8236 emit_insn (gen_blockage ());
8239 for (i
= LAST_BANKED_REG
; i
>= FIRST_BANKED_REG
; i
--)
8240 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
8243 last_reg
= FIRST_PSEUDO_REGISTER
- LAST_BANKED_REG
- 1;
8246 last_reg
= FIRST_PSEUDO_REGISTER
;
8248 for (i
= 0; i
< last_reg
; i
++)
8250 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
8252 if (j
== FPSCR_REG
&& current_function_interrupt
&& TARGET_FMOVD
8253 && hard_reg_set_intersect_p (live_regs_mask
,
8254 reg_class_contents
[DF_REGS
]))
8256 /* For an ISR with RESBANK attribute assigned, don't pop
8257 following registers, R0-R14, MACH, MACL and GBR. */
8258 else if (j
!= PR_REG
&& TEST_HARD_REG_BIT (live_regs_mask
, j
)
8259 && ! (sh_cfun_resbank_handler_p ()
8260 && ((j
>= FIRST_GENERAL_REG
8261 && j
< LAST_GENERAL_REG
)
8267 if (j
== FIRST_FP_REG
&& fpscr_deferred
)
8271 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
8272 emit_insn (gen_toggle_sz ());
8273 target_flags
= save_flags
;
8275 output_stack_adjust (crtl
->args
.pretend_args_size
8276 + save_size
+ d_rounding
8277 + crtl
->args
.info
.stack_regs
* 8,
8278 stack_pointer_rtx
, e
, NULL
, true);
8280 if (crtl
->calls_eh_return
)
8281 emit_insn (GEN_ADD3 (stack_pointer_rtx
, stack_pointer_rtx
,
8282 EH_RETURN_STACKADJ_RTX
));
8284 /* Switch back to the normal stack if necessary. */
8285 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
)))
8286 emit_insn (gen_sp_switch_2 ());
8288 /* Tell flow the insn that pops PR isn't dead. */
8289 /* PR_REG will never be live in SHmedia mode, and we don't need to
8290 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
8291 by the return pattern. */
8292 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
8293 emit_use (gen_rtx_REG (SImode
, PR_REG
));
8296 /* Emit code to change the current function's return address to RA.
8297 TEMP is available as a scratch register, if needed. */
8299 sh_set_return_address (rtx ra
, rtx tmp
)
8301 HARD_REG_SET live_regs_mask
;
8303 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
8306 d
= calc_live_regs (&live_regs_mask
);
8308 /* If pr_reg isn't life, we can set it (or the register given in
8309 sh_media_register_for_return) directly. */
8310 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
8316 int rr_regno
= sh_media_register_for_return ();
8321 rr
= gen_rtx_REG (DImode
, rr_regno
);
8324 rr
= gen_rtx_REG (SImode
, pr_reg
);
8326 emit_insn (GEN_MOV (rr
, ra
));
8327 /* Tell flow the register for return isn't dead. */
8335 save_schedule schedule
;
8338 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, 0);
8339 offset
= entry
[1].offset
;
8340 for (; entry
->mode
!= VOIDmode
; entry
--)
8341 if (entry
->reg
== pr_reg
)
8344 /* We can't find pr register. */
8348 offset
= entry
->offset
- offset
;
8349 pr_offset
= (rounded_frame_size (d
) + offset
8350 + SHMEDIA_REGS_STACK_ADJUST ());
8353 pr_offset
= rounded_frame_size (d
);
8355 emit_insn (GEN_MOV (tmp
, GEN_INT (pr_offset
)));
8357 if (frame_pointer_needed
)
8358 emit_insn (GEN_ADD3 (tmp
, tmp
, hard_frame_pointer_rtx
));
8360 emit_insn (GEN_ADD3 (tmp
, tmp
, stack_pointer_rtx
));
8362 tmp
= gen_frame_mem (Pmode
, tmp
);
8363 emit_insn (GEN_MOV (tmp
, ra
));
8364 /* Tell this store isn't dead. */
8368 /* Clear variables at function end. */
8370 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8371 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8376 sh_builtin_saveregs (void)
8378 /* First unnamed integer register. */
8379 int first_intreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
];
8380 /* Number of integer registers we need to save. */
8381 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
8382 /* First unnamed SFmode float reg */
8383 int first_floatreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_FLOAT
];
8384 /* Number of SFmode float regs to save. */
8385 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
8388 alias_set_type alias_set
;
8394 int pushregs
= n_intregs
;
8396 while (pushregs
< NPARM_REGS (SImode
) - 1
8397 && (CALL_COOKIE_INT_REG_GET
8398 (crtl
->args
.info
.call_cookie
,
8399 NPARM_REGS (SImode
) - pushregs
)
8402 crtl
->args
.info
.call_cookie
8403 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
8408 if (pushregs
== NPARM_REGS (SImode
))
8409 crtl
->args
.info
.call_cookie
8410 |= (CALL_COOKIE_INT_REG (0, 1)
8411 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
8413 crtl
->args
.info
.call_cookie
8414 |= CALL_COOKIE_STACKSEQ (pushregs
);
8416 crtl
->args
.pretend_args_size
+= 8 * n_intregs
;
8418 if (TARGET_SHCOMPACT
)
8422 if (! TARGET_SH2E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
8424 error ("__builtin_saveregs not supported by this subtarget");
8431 /* Allocate block of memory for the regs. */
8432 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
8433 Or can assign_stack_local accept a 0 SIZE argument? */
8434 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
8437 regbuf
= gen_frame_mem (BLKmode
, gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
8438 else if (n_floatregs
& 1)
8442 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
8443 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
8444 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
8445 regbuf
= change_address (regbuf
, BLKmode
, addr
);
8447 else if (STACK_BOUNDARY
< 64 && TARGET_FPU_DOUBLE
&& n_floatregs
)
8451 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
8452 addr
= copy_to_mode_reg (Pmode
, plus_constant (Pmode
,
8453 XEXP (regbuf
, 0), 4));
8454 mask
= copy_to_mode_reg (Pmode
, GEN_INT (-8));
8455 emit_insn (gen_andsi3 (addr
, addr
, mask
));
8456 regbuf
= change_address (regbuf
, BLKmode
, addr
);
8459 regbuf
= assign_stack_local (BLKmode
, bufsize
, TARGET_FPU_DOUBLE
? 64 : 0);
8460 alias_set
= get_varargs_alias_set ();
8461 set_mem_alias_set (regbuf
, alias_set
);
8464 This is optimized to only save the regs that are necessary. Explicitly
8465 named args need not be saved. */
8467 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
8468 adjust_address (regbuf
, BLKmode
,
8469 n_floatregs
* UNITS_PER_WORD
),
8473 /* Return the address of the regbuf. */
8474 return XEXP (regbuf
, 0);
8477 This is optimized to only save the regs that are necessary. Explicitly
8478 named args need not be saved.
8479 We explicitly build a pointer to the buffer because it halves the insn
8480 count when not optimizing (otherwise the pointer is built for each reg
8482 We emit the moves in reverse order so that we can use predecrement. */
8484 fpregs
= copy_to_mode_reg (Pmode
,
8485 plus_constant (Pmode
, XEXP (regbuf
, 0),
8486 n_floatregs
* UNITS_PER_WORD
));
8487 if (TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8490 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
8492 emit_insn (gen_addsi3 (fpregs
, fpregs
,
8493 GEN_INT (-2 * UNITS_PER_WORD
)));
8494 mem
= change_address (regbuf
, DFmode
, fpregs
);
8495 emit_move_insn (mem
,
8496 gen_rtx_REG (DFmode
, BASE_ARG_REG (DFmode
) + regno
));
8498 regno
= first_floatreg
;
8501 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
8502 mem
= change_address (regbuf
, SFmode
, fpregs
);
8503 emit_move_insn (mem
,
8504 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
)
8505 + regno
- SH_REG_MSW_OFFSET
));
8509 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
8513 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
8514 mem
= change_address (regbuf
, SFmode
, fpregs
);
8515 emit_move_insn (mem
,
8516 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
8519 /* Return the address of the regbuf. */
8520 return XEXP (regbuf
, 0);
8523 /* Define the `__builtin_va_list' type for the ABI. */
8525 sh_build_builtin_va_list (void)
8527 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8528 tree record
, type_decl
;
8530 if (TARGET_SH5
|| (! TARGET_SH2E
&& ! TARGET_SH4
)
8531 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
8532 return ptr_type_node
;
8534 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
8535 type_decl
= build_decl (BUILTINS_LOCATION
,
8536 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8538 f_next_o
= build_decl (BUILTINS_LOCATION
,
8539 FIELD_DECL
, get_identifier ("__va_next_o"),
8541 f_next_o_limit
= build_decl (BUILTINS_LOCATION
,
8543 get_identifier ("__va_next_o_limit"),
8545 f_next_fp
= build_decl (BUILTINS_LOCATION
,
8546 FIELD_DECL
, get_identifier ("__va_next_fp"),
8548 f_next_fp_limit
= build_decl (BUILTINS_LOCATION
,
8550 get_identifier ("__va_next_fp_limit"),
8552 f_next_stack
= build_decl (BUILTINS_LOCATION
,
8553 FIELD_DECL
, get_identifier ("__va_next_stack"),
8556 DECL_FIELD_CONTEXT (f_next_o
) = record
;
8557 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
8558 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
8559 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
8560 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
8562 TYPE_STUB_DECL (record
) = type_decl
;
8563 TYPE_NAME (record
) = type_decl
;
8564 TYPE_FIELDS (record
) = f_next_o
;
8565 DECL_CHAIN (f_next_o
) = f_next_o_limit
;
8566 DECL_CHAIN (f_next_o_limit
) = f_next_fp
;
8567 DECL_CHAIN (f_next_fp
) = f_next_fp_limit
;
8568 DECL_CHAIN (f_next_fp_limit
) = f_next_stack
;
8570 layout_type (record
);
8575 /* Implement `va_start' for varargs and stdarg. */
8577 sh_va_start (tree valist
, rtx nextarg
)
8579 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8580 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
8586 expand_builtin_saveregs ();
8587 std_expand_builtin_va_start (valist
, nextarg
);
8591 if ((! TARGET_SH2E
&& ! TARGET_SH4
)
8592 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
8594 std_expand_builtin_va_start (valist
, nextarg
);
8598 f_next_o
= TYPE_FIELDS (va_list_type_node
);
8599 f_next_o_limit
= DECL_CHAIN (f_next_o
);
8600 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
8601 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
8602 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
8604 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
8606 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
8607 valist
, f_next_o_limit
, NULL_TREE
);
8608 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
,
8610 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
8611 valist
, f_next_fp_limit
, NULL_TREE
);
8612 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
8613 valist
, f_next_stack
, NULL_TREE
);
8615 /* Call __builtin_saveregs. */
8616 u
= make_tree (sizetype
, expand_builtin_saveregs ());
8617 u
= fold_convert (ptr_type_node
, u
);
8618 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
8619 TREE_SIDE_EFFECTS (t
) = 1;
8620 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8622 nfp
= crtl
->args
.info
.arg_count
[SH_ARG_FLOAT
];
8627 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nfp
);
8628 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
8629 TREE_SIDE_EFFECTS (t
) = 1;
8630 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8632 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
8633 TREE_SIDE_EFFECTS (t
) = 1;
8634 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8636 nint
= crtl
->args
.info
.arg_count
[SH_ARG_INT
];
8641 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nint
);
8642 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
8643 TREE_SIDE_EFFECTS (t
) = 1;
8644 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8646 u
= make_tree (ptr_type_node
, nextarg
);
8647 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
8648 TREE_SIDE_EFFECTS (t
) = 1;
8649 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8652 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
8653 member, return it. */
8655 find_sole_member (tree type
)
8657 tree field
, member
= NULL_TREE
;
8659 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8661 if (TREE_CODE (field
) != FIELD_DECL
)
8663 if (!DECL_SIZE (field
))
8665 if (integer_zerop (DECL_SIZE (field
)))
8674 /* Implement `va_arg'. */
8676 sh_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
8677 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8679 HOST_WIDE_INT size
, rsize
;
8680 tree tmp
, pptr_type_node
;
8681 tree addr
, lab_over
= NULL
, result
= NULL
;
8685 if (!VOID_TYPE_P (type
))
8686 pass_by_ref
= targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
);
8688 pass_by_ref
= false;
8691 type
= build_pointer_type (type
);
8693 size
= int_size_in_bytes (type
);
8694 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
8695 pptr_type_node
= build_pointer_type (ptr_type_node
);
8697 if (! TARGET_SH5
&& (TARGET_SH2E
|| TARGET_SH4
)
8698 && ! (TARGET_HITACHI
|| sh_cfun_attr_renesas_p ()))
8700 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8701 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
8706 f_next_o
= TYPE_FIELDS (va_list_type_node
);
8707 f_next_o_limit
= DECL_CHAIN (f_next_o
);
8708 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
8709 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
8710 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
8712 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
8714 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
8715 valist
, f_next_o_limit
, NULL_TREE
);
8716 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
8717 valist
, f_next_fp
, NULL_TREE
);
8718 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
8719 valist
, f_next_fp_limit
, NULL_TREE
);
8720 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
8721 valist
, f_next_stack
, NULL_TREE
);
8723 /* Structures with a single member with a distinct mode are passed
8724 like their member. This is relevant if the latter has a REAL_TYPE
8725 or COMPLEX_TYPE type. */
8727 while (TREE_CODE (eff_type
) == RECORD_TYPE
8728 && (member
= find_sole_member (eff_type
))
8729 && (TREE_CODE (TREE_TYPE (member
)) == REAL_TYPE
8730 || TREE_CODE (TREE_TYPE (member
)) == COMPLEX_TYPE
8731 || TREE_CODE (TREE_TYPE (member
)) == RECORD_TYPE
))
8733 tree field_type
= TREE_TYPE (member
);
8735 if (TYPE_MODE (eff_type
) == TYPE_MODE (field_type
))
8736 eff_type
= field_type
;
8739 gcc_assert ((TYPE_ALIGN (eff_type
)
8740 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type
)))
8741 || (TYPE_ALIGN (eff_type
)
8742 > GET_MODE_BITSIZE (TYPE_MODE (field_type
))));
8747 if (TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8749 pass_as_float
= ((TREE_CODE (eff_type
) == REAL_TYPE
&& size
<= 8)
8750 || (TREE_CODE (eff_type
) == COMPLEX_TYPE
8751 && TREE_CODE (TREE_TYPE (eff_type
)) == REAL_TYPE
8756 pass_as_float
= (TREE_CODE (eff_type
) == REAL_TYPE
&& size
== 4);
8759 addr
= create_tmp_var (pptr_type_node
);
8760 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8761 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8763 valist
= build_simple_mem_ref (addr
);
8767 tree next_fp_tmp
= create_tmp_var (TREE_TYPE (f_next_fp
));
8769 bool is_double
= size
== 8 && TREE_CODE (eff_type
) == REAL_TYPE
;
8771 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_fp
));
8772 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8774 gimplify_assign (unshare_expr (next_fp_tmp
), valist
, pre_p
);
8775 tmp
= next_fp_limit
;
8776 if (size
> 4 && !is_double
)
8777 tmp
= fold_build_pointer_plus_hwi (unshare_expr (tmp
), 4 - size
);
8778 tmp
= build2 (GE_EXPR
, boolean_type_node
,
8779 unshare_expr (next_fp_tmp
), unshare_expr (tmp
));
8780 cmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
8781 build1 (GOTO_EXPR
, void_type_node
,
8782 unshare_expr (lab_false
)), NULL_TREE
);
8784 gimplify_and_add (cmp
, pre_p
);
8786 if (TYPE_ALIGN (eff_type
) > BITS_PER_WORD
8787 || (is_double
|| size
== 16))
8789 tmp
= fold_convert (sizetype
, next_fp_tmp
);
8790 tmp
= build2 (BIT_AND_EXPR
, sizetype
, tmp
,
8791 size_int (UNITS_PER_WORD
));
8792 tmp
= fold_build_pointer_plus (unshare_expr (next_fp_tmp
), tmp
);
8793 gimplify_assign (unshare_expr (next_fp_tmp
), tmp
, pre_p
);
8796 gimplify_and_add (cmp
, pre_p
);
8798 #ifdef FUNCTION_ARG_SCmode_WART
8799 if (TYPE_MODE (eff_type
) == SCmode
8800 && TARGET_SH4
&& TARGET_LITTLE_ENDIAN
)
8802 tree subtype
= TREE_TYPE (eff_type
);
8806 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
8807 imag
= get_initialized_tmp_var (imag
, pre_p
, NULL
);
8810 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
8811 real
= get_initialized_tmp_var (real
, pre_p
, NULL
);
8813 result
= build2 (COMPLEX_EXPR
, eff_type
, real
, imag
);
8814 if (type
!= eff_type
)
8815 result
= build1 (VIEW_CONVERT_EXPR
, type
, result
);
8816 result
= get_initialized_tmp_var (result
, pre_p
, NULL
);
8818 #endif /* FUNCTION_ARG_SCmode_WART */
8820 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
8821 gimplify_and_add (tmp
, pre_p
);
8823 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
8824 gimplify_and_add (tmp
, pre_p
);
8826 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
8827 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8828 gimplify_assign (unshare_expr (next_fp_tmp
),
8829 unshare_expr (valist
), pre_p
);
8831 gimplify_assign (unshare_expr (valist
),
8832 unshare_expr (next_fp_tmp
), post_p
);
8833 valist
= next_fp_tmp
;
8837 tmp
= fold_build_pointer_plus_hwi (unshare_expr (next_o
), rsize
);
8838 tmp
= build2 (GT_EXPR
, boolean_type_node
, tmp
,
8839 unshare_expr (next_o_limit
));
8840 tmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
8841 build1 (GOTO_EXPR
, void_type_node
,
8842 unshare_expr (lab_false
)),
8844 gimplify_and_add (tmp
, pre_p
);
8846 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_o
));
8847 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8849 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
8850 gimplify_and_add (tmp
, pre_p
);
8852 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
8853 gimplify_and_add (tmp
, pre_p
);
8855 if (size
> 4 && ! (TARGET_SH4
|| TARGET_SH2A
))
8856 gimplify_assign (unshare_expr (next_o
),
8857 unshare_expr (next_o_limit
), pre_p
);
8859 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
8860 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8865 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
8866 gimplify_and_add (tmp
, pre_p
);
8870 /* ??? In va-sh.h, there had been code to make values larger than
8871 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8873 tmp
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, NULL
);
8876 gimplify_assign (result
, tmp
, pre_p
);
8877 result
= build1 (NOP_EXPR
, TREE_TYPE (result
), result
);
8878 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
8879 gimplify_and_add (tmp
, pre_p
);
8885 result
= build_va_arg_indirect_ref (result
);
8890 /* 64 bit floating points memory transfers are paired single precision loads
8891 or store. So DWARF information needs fixing in little endian (unless
8892 PR=SZ=1 in FPSCR). */
8894 sh_dwarf_register_span (rtx reg
)
8896 unsigned regno
= REGNO (reg
);
8898 if (WORDS_BIG_ENDIAN
|| GET_MODE (reg
) != DFmode
)
8902 gen_rtx_PARALLEL (VOIDmode
,
8904 gen_rtx_REG (SFmode
, regno
+ 1),
8905 gen_rtx_REG (SFmode
, regno
)));
8909 sh_promote_function_mode (const_tree type
, machine_mode mode
,
8910 int *punsignedp
, const_tree funtype
,
8913 if (sh_promote_prototypes (funtype
))
8914 return promote_mode (type
, mode
, punsignedp
);
8916 return default_promote_function_mode (type
, mode
, punsignedp
, funtype
,
8921 sh_promote_prototypes (const_tree type
)
8927 return ! sh_attr_renesas_p (type
);
8930 /* Whether an argument must be passed by reference. On SHcompact, we
8931 pretend arguments wider than 32-bits that would have been passed in
8932 registers are passed by reference, so that an SHmedia trampoline
8933 loads them into the full 64-bits registers. */
8935 shcompact_byref (const CUMULATIVE_ARGS
*cum
, machine_mode mode
,
8936 const_tree type
, bool named
)
8938 unsigned HOST_WIDE_INT size
;
8941 size
= int_size_in_bytes (type
);
8943 size
= GET_MODE_SIZE (mode
);
8945 if (cum
->arg_count
[SH_ARG_INT
] < NPARM_REGS (SImode
)
8947 || GET_SH_ARG_CLASS (mode
) == SH_ARG_INT
8948 || (GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
8949 && cum
->arg_count
[SH_ARG_FLOAT
] >= NPARM_REGS (SFmode
)))
8951 && !SHCOMPACT_FORCE_ON_STACK (mode
, type
)
8952 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum
, mode
, type
, named
))
8959 sh_pass_by_reference (cumulative_args_t cum_v
, machine_mode mode
,
8960 const_tree type
, bool named
)
8962 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8964 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
8967 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8968 wants to know about pass-by-reference semantics for incoming
8973 if (TARGET_SHCOMPACT
)
8975 cum
->byref
= shcompact_byref (cum
, mode
, type
, named
);
8976 return cum
->byref
!= 0;
8983 sh_callee_copies (cumulative_args_t cum
, machine_mode mode
,
8984 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8986 /* ??? How can it possibly be correct to return true only on the
8987 caller side of the equation? Is there someplace else in the
8988 sh backend that's magically producing the copies? */
8989 return (get_cumulative_args (cum
)->outgoing
8990 && ((mode
== BLKmode
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
))
8991 % SH_MIN_ALIGN_FOR_CALLEE_COPY
== 0));
8994 /* Round a register number up to a proper boundary for an arg of mode
8996 The SH doesn't care about double alignment, so we only
8997 round doubles to even regs when asked to explicitly. */
8999 sh_round_reg (const CUMULATIVE_ARGS
& cum
, machine_mode mode
)
9001 /* FIXME: This used to be a macro and has been copy pasted into this
9002 function as is. Make this more readable. */
9004 (((TARGET_ALIGN_DOUBLE
9005 || ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
9006 && (mode
== DFmode
|| mode
== DCmode
)
9007 && cum
.arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (mode
)))
9008 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_WORD
)
9009 ? (cum
.arg_count
[(int) GET_SH_ARG_CLASS (mode
)]
9010 + (cum
.arg_count
[(int) GET_SH_ARG_CLASS (mode
)] & 1))
9011 : cum
.arg_count
[(int) GET_SH_ARG_CLASS (mode
)]);
9014 /* Return true if arg of the specified mode should be passed in a register
9015 or false otherwise. */
9017 sh_pass_in_reg_p (const CUMULATIVE_ARGS
& cum
, machine_mode mode
,
9020 /* FIXME: This used to be a macro and has been copy pasted into this
9021 function as is. Make this more readable. */
9024 || (! TREE_ADDRESSABLE (type
)
9025 && (! (TARGET_HITACHI
|| cum
.renesas_abi
)
9026 || ! (AGGREGATE_TYPE_P (type
)
9028 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
9029 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (SFmode
)))))))
9032 ? ((mode
) == BLKmode
9033 ? ((cum
.arg_count
[(int) SH_ARG_INT
] * UNITS_PER_WORD
9034 + int_size_in_bytes (type
))
9035 <= NPARM_REGS (SImode
) * UNITS_PER_WORD
)
9036 : ((sh_round_reg (cum
, mode
)
9037 + HARD_REGNO_NREGS (BASE_ARG_REG (mode
), mode
))
9038 <= NPARM_REGS (mode
)))
9039 : sh_round_reg (cum
, mode
) < NPARM_REGS (mode
)));
9043 sh_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
9044 tree type
, bool named ATTRIBUTE_UNUSED
)
9046 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9050 && sh_pass_in_reg_p (*cum
, mode
, type
)
9051 && !(TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
9052 && (sh_round_reg (*cum
, mode
)
9054 ? CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
9055 : CEIL (int_size_in_bytes (type
), UNITS_PER_WORD
))
9056 > NPARM_REGS (mode
)))
9057 words
= NPARM_REGS (mode
) - sh_round_reg (*cum
, mode
);
9059 else if (!TARGET_SHCOMPACT
9060 && SH5_WOULD_BE_PARTIAL_NREGS (*cum
, mode
, type
, named
))
9061 words
= NPARM_REGS (SImode
) - cum
->arg_count
[SH_ARG_INT
];
9063 return words
* UNITS_PER_WORD
;
9067 /* Define where to put the arguments to a function.
9068 Value is zero to push the argument on the stack,
9069 or a hard register in which to store the argument.
9071 MODE is the argument's machine mode.
9072 TYPE is the data type of the argument (as a tree).
9073 This is null for libcalls where that information may
9075 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9076 the preceding args and about the function being called.
9077 NAMED is nonzero if this argument is a named parameter
9078 (otherwise it is an extra parameter matching an ellipsis).
9080 On SH the first args are normally in registers
9081 and the rest are pushed. Any arg that starts within the first
9082 NPARM_REGS words is at least partially passed in a register unless
9083 its data type forbids. */
9085 sh_function_arg (cumulative_args_t ca_v
, machine_mode mode
,
9086 const_tree type
, bool named
)
9088 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
9090 if (! TARGET_SH5
&& mode
== VOIDmode
)
9091 return GEN_INT (ca
->renesas_abi
? 1 : 0);
9094 && sh_pass_in_reg_p (*ca
, mode
, type
)
9095 && (named
|| ! (TARGET_HITACHI
|| ca
->renesas_abi
)))
9099 if (mode
== SCmode
&& TARGET_SH4
&& TARGET_LITTLE_ENDIAN
9100 && (! FUNCTION_ARG_SCmode_WART
|| (sh_round_reg (*ca
, mode
) & 1)))
9102 rtx r1
= gen_rtx_EXPR_LIST (VOIDmode
,
9103 gen_rtx_REG (SFmode
,
9105 + (sh_round_reg (*ca
, mode
) ^ 1)),
9107 rtx r2
= gen_rtx_EXPR_LIST (VOIDmode
,
9108 gen_rtx_REG (SFmode
,
9110 + ((sh_round_reg (*ca
, mode
) + 1) ^ 1)),
9112 return gen_rtx_PARALLEL(SCmode
, gen_rtvec(2, r1
, r2
));
9115 /* If the alignment of a DF value causes an SF register to be
9116 skipped, we will use that skipped register for the next SF
9118 if ((TARGET_HITACHI
|| ca
->renesas_abi
)
9119 && ca
->free_single_fp_reg
9121 return gen_rtx_REG (mode
, ca
->free_single_fp_reg
);
9123 regno
= (BASE_ARG_REG (mode
) + sh_round_reg (*ca
, mode
))
9124 ^ (mode
== SFmode
&& TARGET_SH4
9125 && TARGET_LITTLE_ENDIAN
9126 && ! TARGET_HITACHI
&& ! ca
->renesas_abi
);
9127 return gen_rtx_REG (mode
, regno
);
9133 if (mode
== VOIDmode
&& TARGET_SHCOMPACT
)
9134 return GEN_INT (ca
->call_cookie
);
9136 /* The following test assumes unnamed arguments are promoted to
9138 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
9139 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
, ca
->free_single_fp_reg
);
9141 if ((GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
)
9142 && (named
|| ! ca
->prototype_p
)
9143 && ca
->arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (SFmode
))
9145 if (! ca
->prototype_p
&& TARGET_SHMEDIA
)
9146 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca
, mode
);
9148 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
,
9150 + ca
->arg_count
[(int) SH_ARG_FLOAT
]);
9153 if (ca
->arg_count
[(int) SH_ARG_INT
] < NPARM_REGS (SImode
)
9154 && (! TARGET_SHCOMPACT
9155 || (! SHCOMPACT_FORCE_ON_STACK (mode
, type
)
9156 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca
, mode
,
9159 return gen_rtx_REG (mode
, (FIRST_PARM_REG
9160 + ca
->arg_count
[(int) SH_ARG_INT
]));
9169 /* Update the data in CUM to advance over an argument
9170 of mode MODE and data type TYPE.
9171 (TYPE is null for libcalls where that information may not be
9174 sh_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
9175 const_tree type
, bool named
)
9177 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
9181 else if (TARGET_SH5
)
9183 const_tree type2
= (ca
->byref
&& type
9186 machine_mode mode2
= (ca
->byref
&& type
9189 int dwords
= ((ca
->byref
9192 ? int_size_in_bytes (type2
)
9193 : GET_MODE_SIZE (mode2
)) + 7) / 8;
9194 int numregs
= MIN (dwords
, NPARM_REGS (SImode
)
9195 - ca
->arg_count
[(int) SH_ARG_INT
]);
9199 ca
->arg_count
[(int) SH_ARG_INT
] += numregs
;
9200 if (TARGET_SHCOMPACT
9201 && SHCOMPACT_FORCE_ON_STACK (mode2
, type2
))
9204 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
9206 /* N.B. We want this also for outgoing. */
9207 ca
->stack_regs
+= numregs
;
9212 ca
->stack_regs
+= numregs
;
9213 ca
->byref_regs
+= numregs
;
9217 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
9221 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
9224 else if (dwords
> numregs
)
9226 int pushregs
= numregs
;
9228 if (TARGET_SHCOMPACT
)
9229 ca
->stack_regs
+= numregs
;
9230 while (pushregs
< NPARM_REGS (SImode
) - 1
9231 && (CALL_COOKIE_INT_REG_GET
9233 NPARM_REGS (SImode
) - pushregs
)
9237 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
9241 if (numregs
== NPARM_REGS (SImode
))
9243 |= CALL_COOKIE_INT_REG (0, 1)
9244 | CALL_COOKIE_STACKSEQ (numregs
- 1);
9247 |= CALL_COOKIE_STACKSEQ (numregs
);
9250 if (GET_SH_ARG_CLASS (mode2
) == SH_ARG_FLOAT
9251 && (named
|| ! ca
->prototype_p
))
9253 if (mode2
== SFmode
&& ca
->free_single_fp_reg
)
9254 ca
->free_single_fp_reg
= 0;
9255 else if (ca
->arg_count
[(int) SH_ARG_FLOAT
]
9256 < NPARM_REGS (SFmode
))
9259 = MIN ((GET_MODE_SIZE (mode2
) + 7) / 8 * 2,
9261 - ca
->arg_count
[(int) SH_ARG_FLOAT
]);
9263 ca
->arg_count
[(int) SH_ARG_FLOAT
] += numfpregs
;
9265 if (TARGET_SHCOMPACT
&& ! ca
->prototype_p
)
9267 if (ca
->outgoing
&& numregs
> 0)
9271 |= (CALL_COOKIE_INT_REG
9272 (ca
->arg_count
[(int) SH_ARG_INT
]
9273 - numregs
+ ((numfpregs
- 2) / 2),
9274 4 + (ca
->arg_count
[(int) SH_ARG_FLOAT
]
9277 while (numfpregs
-= 2);
9279 else if (mode2
== SFmode
&& (named
)
9280 && (ca
->arg_count
[(int) SH_ARG_FLOAT
]
9281 < NPARM_REGS (SFmode
)))
9282 ca
->free_single_fp_reg
9283 = FIRST_FP_PARM_REG
- numfpregs
9284 + ca
->arg_count
[(int) SH_ARG_FLOAT
] + 1;
9290 if ((TARGET_HITACHI
|| ca
->renesas_abi
) && TARGET_FPU_DOUBLE
)
9292 /* Note that we've used the skipped register. */
9293 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
9295 ca
->free_single_fp_reg
= 0;
9298 /* When we have a DF after an SF, there's an SF register that get
9299 skipped in order to align the DF value. We note this skipped
9300 register, because the next SF value will use it, and not the
9301 SF that follows the DF. */
9303 && sh_round_reg (*ca
, DFmode
) != sh_round_reg (*ca
, SFmode
))
9305 ca
->free_single_fp_reg
= (sh_round_reg (*ca
, SFmode
)
9306 + BASE_ARG_REG (mode
));
9310 if (! ((TARGET_SH4
|| TARGET_SH2A
) || ca
->renesas_abi
)
9311 || sh_pass_in_reg_p (*ca
, mode
, type
))
9312 (ca
->arg_count
[(int) GET_SH_ARG_CLASS (mode
)]
9313 = (sh_round_reg (*ca
, mode
)
9315 ? CEIL (int_size_in_bytes (type
), UNITS_PER_WORD
)
9316 : CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))));
9319 /* The Renesas calling convention doesn't quite fit into this scheme since
9320 the address is passed like an invisible argument, but one that is always
9321 passed in memory. */
9323 sh_struct_value_rtx (tree fndecl
, int incoming ATTRIBUTE_UNUSED
)
9325 if (TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
9327 return gen_rtx_REG (Pmode
, 2);
9330 /* Worker function for TARGET_FUNCTION_VALUE.
9332 For the SH, this is like LIBCALL_VALUE, except that we must change the
9333 mode like PROMOTE_MODE does.
9334 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
9335 tested here has to be kept in sync with the one in
9336 explow.c:promote_mode. */
9338 sh_function_value (const_tree valtype
,
9339 const_tree fn_decl_or_type
,
9340 bool outgoing ATTRIBUTE_UNUSED
)
9343 && !DECL_P (fn_decl_or_type
))
9344 fn_decl_or_type
= NULL
;
9346 return gen_rtx_REG (
9347 ((GET_MODE_CLASS (TYPE_MODE (valtype
)) == MODE_INT
9348 && GET_MODE_SIZE (TYPE_MODE (valtype
)) < 4
9349 && (TREE_CODE (valtype
) == INTEGER_TYPE
9350 || TREE_CODE (valtype
) == ENUMERAL_TYPE
9351 || TREE_CODE (valtype
) == BOOLEAN_TYPE
9352 || TREE_CODE (valtype
) == REAL_TYPE
9353 || TREE_CODE (valtype
) == OFFSET_TYPE
))
9354 && sh_promote_prototypes (fn_decl_or_type
)
9355 ? (TARGET_SHMEDIA64
? DImode
: SImode
) : TYPE_MODE (valtype
)),
9356 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype
)));
9359 /* Worker function for TARGET_LIBCALL_VALUE. */
9361 sh_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
9363 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG (mode
));
9366 /* Return true if N is a possible register number of function value. */
9368 sh_function_value_regno_p (const unsigned int regno
)
9370 return ((regno
) == FIRST_RET_REG
9371 || (TARGET_SH2E
&& (regno
) == FIRST_FP_RET_REG
)
9372 || (TARGET_SHMEDIA_FPU
&& (regno
) == FIRST_FP_RET_REG
));
9375 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9377 sh_return_in_memory (const_tree type
, const_tree fndecl
)
9381 if (TYPE_MODE (type
) == BLKmode
)
9382 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)) > 8;
9384 return GET_MODE_SIZE (TYPE_MODE (type
)) > 8;
9388 return (TYPE_MODE (type
) == BLKmode
9389 || ((TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
9390 && TREE_CODE (type
) == RECORD_TYPE
));
9394 /* We actually emit the code in sh_expand_prologue. We used to use
9395 a static variable to flag that we need to emit this code, but that
9396 doesn't when inlining, when functions are deferred and then emitted
9397 later. Fortunately, we already have two flags that are part of struct
9398 function that tell if a function uses varargs or stdarg. */
9400 sh_setup_incoming_varargs (cumulative_args_t ca
,
9403 int *pretend_arg_size
,
9404 int second_time ATTRIBUTE_UNUSED
)
9406 gcc_assert (cfun
->stdarg
);
9407 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
9409 int named_parm_regs
, anon_parm_regs
;
9411 named_parm_regs
= (sh_round_reg (*get_cumulative_args (ca
), mode
)
9413 ? CEIL (int_size_in_bytes (type
), UNITS_PER_WORD
)
9414 : CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)));
9415 anon_parm_regs
= NPARM_REGS (SImode
) - named_parm_regs
;
9416 if (anon_parm_regs
> 0)
9417 *pretend_arg_size
= anon_parm_regs
* 4;
9422 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
9428 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v
)
9430 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
9432 return ! (TARGET_HITACHI
|| ca
->renesas_abi
) && ! TARGET_SH5
;
9436 /* Define the offset between two registers, one to be eliminated, and
9437 the other its replacement, at the start of a routine. */
9439 initial_elimination_offset (int from
, int to
)
9442 int regs_saved_rounding
= 0;
9443 int total_saved_regs_space
;
9444 int total_auto_space
;
9445 int save_flags
= target_flags
;
9447 HARD_REG_SET live_regs_mask
;
9449 shmedia_space_reserved_for_target_registers
= false;
9450 regs_saved
= calc_live_regs (&live_regs_mask
);
9451 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
9453 if (shmedia_reserve_space_for_target_registers_p (regs_saved
, &live_regs_mask
))
9455 shmedia_space_reserved_for_target_registers
= true;
9456 regs_saved
+= shmedia_target_regs_stack_adjust (&live_regs_mask
);
9459 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
9460 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
9461 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
9463 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
9464 copy_flags
= target_flags
;
9465 target_flags
= save_flags
;
9467 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
9469 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9470 return total_saved_regs_space
+ total_auto_space
9471 + crtl
->args
.info
.byref_regs
* 8;
9473 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9474 return total_saved_regs_space
+ total_auto_space
9475 + crtl
->args
.info
.byref_regs
* 8;
9477 /* Initial gap between fp and sp is 0. */
9478 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9481 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9482 return rounded_frame_size (0);
9484 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9485 return rounded_frame_size (0);
9487 gcc_assert (from
== RETURN_ADDRESS_POINTER_REGNUM
9488 && (to
== HARD_FRAME_POINTER_REGNUM
9489 || to
== STACK_POINTER_REGNUM
));
9492 int n
= total_saved_regs_space
;
9493 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
9494 save_schedule schedule
;
9497 n
+= total_auto_space
;
9499 /* If it wasn't saved, there's not much we can do. */
9500 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
9503 target_flags
= copy_flags
;
9505 sh5_schedule_saves (&live_regs_mask
, &schedule
, n
);
9506 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
9507 if (entry
->reg
== pr_reg
)
9509 target_flags
= save_flags
;
9510 return entry
->offset
;
9515 return total_auto_space
;
9518 /* Parse the -mfixed-range= option string. */
9520 sh_fix_range (const char *const_str
)
9523 char *str
, *dash
, *comma
;
9525 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
9526 REG2 are either register names or register numbers. The effect
9527 of this option is to mark the registers in the range from REG1 to
9528 REG2 as ``fixed'' so they won't be used by the compiler. */
9530 i
= strlen (const_str
);
9531 str
= (char *) alloca (i
+ 1);
9532 memcpy (str
, const_str
, i
+ 1);
9536 dash
= strchr (str
, '-');
9539 warning (0, "value of -mfixed-range must have form REG1-REG2");
9543 comma
= strchr (dash
+ 1, ',');
9547 first
= decode_reg_name (str
);
9550 warning (0, "unknown register name: %s", str
);
9554 last
= decode_reg_name (dash
+ 1);
9557 warning (0, "unknown register name: %s", dash
+ 1);
9565 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
9569 for (i
= first
; i
<= last
; ++i
)
9570 fixed_regs
[i
] = call_used_regs
[i
] = 1;
9580 /* Insert any deferred function attributes from earlier pragmas. */
9582 sh_insert_attributes (tree node
, tree
*attributes
)
9586 if (TREE_CODE (node
) != FUNCTION_DECL
)
9589 /* We are only interested in fields. */
9593 /* Append the attributes to the deferred attributes. */
9594 *sh_deferred_function_attributes_tail
= *attributes
;
9595 attrs
= sh_deferred_function_attributes
;
9599 /* Some attributes imply or require the interrupt attribute. */
9600 if (!lookup_attribute ("interrupt_handler", attrs
)
9601 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node
)))
9603 /* If we have a trapa_handler, but no interrupt_handler attribute,
9604 insert an interrupt_handler attribute. */
9605 if (lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
)
9606 /* We can't use sh_pr_interrupt here because that's not in the
9609 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE
, attrs
);
9610 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
9611 if the interrupt attribute is missing, we ignore the attribute
9613 else if (lookup_attribute ("sp_switch", attrs
)
9614 || lookup_attribute ("trap_exit", attrs
)
9615 || lookup_attribute ("nosave_low_regs", attrs
)
9616 || lookup_attribute ("resbank", attrs
))
9620 for (tail
= attributes
; attrs
; attrs
= TREE_CHAIN (attrs
))
9622 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs
))
9623 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs
))
9624 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs
))
9625 || is_attribute_p ("resbank", TREE_PURPOSE (attrs
)))
9626 warning (OPT_Wattributes
,
9627 "%qE attribute only applies to interrupt functions",
9628 TREE_PURPOSE (attrs
));
9631 *tail
= tree_cons (TREE_PURPOSE (attrs
), NULL_TREE
,
9633 tail
= &TREE_CHAIN (*tail
);
9636 attrs
= *attributes
;
9640 /* Install the processed list. */
9641 *attributes
= attrs
;
9643 /* Clear deferred attributes. */
9644 sh_deferred_function_attributes
= NULL_TREE
;
9645 sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
9650 /*------------------------------------------------------------------------------
9651 Target specific attributes
9652 Supported attributes are:
9655 Specifies this function is an interrupt handler.
9658 Like interrupt_handler, but don't save all registers.
9661 Specifies an alternate stack for an interrupt handler to run on.
9664 Use a trapa to exit an interrupt function instead of rte.
9667 Don't save r0..r7 in an interrupt handler function.
9668 This is useful on SH3* and SH4*, which have a separate set of low
9669 regs for user and privileged modes.
9670 This is mainly to be used for non-reentrant interrupt handlers (i.e.
9671 those that run with interrupts disabled and thus can't be
9672 interrupted thenselves).
9675 Use Renesas calling/layout conventions (functions and structures).
9678 In case of an interrupt handler function, use a register bank to
9679 save registers R0-R14, MACH, MACL, GBR and PR.
9680 This is available only on SH2A targets.
9683 Declares a function to be called using the TBR relative addressing
9684 mode. Takes an argument that specifies the slot number in the table
9685 where this function can be looked up by the JSR/N @@(disp8,TBR) insn.
9688 /* Handle a 'resbank' attribute. */
9690 sh_handle_resbank_handler_attribute (tree
* node
, tree name
,
9691 tree args ATTRIBUTE_UNUSED
,
9692 int flags ATTRIBUTE_UNUSED
,
9693 bool * no_add_attrs
)
9697 warning (OPT_Wattributes
, "%qE attribute is supported only for SH2A",
9699 *no_add_attrs
= true;
9701 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9703 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9705 *no_add_attrs
= true;
9711 /* Handle an "interrupt_handler" attribute; arguments as in
9712 struct attribute_spec.handler. */
9714 sh_handle_interrupt_handler_attribute (tree
*node
, tree name
,
9715 tree args ATTRIBUTE_UNUSED
,
9716 int flags ATTRIBUTE_UNUSED
,
9719 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9721 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9723 *no_add_attrs
= true;
9725 else if (TARGET_SHCOMPACT
)
9727 error ("attribute interrupt_handler is not compatible with -m5-compact");
9728 *no_add_attrs
= true;
9734 /* Handle an 'function_vector' attribute; arguments as in
9735 struct attribute_spec.handler. */
9737 sh2a_handle_function_vector_handler_attribute (tree
* node
, tree name
,
9738 tree args ATTRIBUTE_UNUSED
,
9739 int flags ATTRIBUTE_UNUSED
,
9740 bool * no_add_attrs
)
9744 warning (OPT_Wattributes
, "%qE attribute only applies to SH2A",
9746 *no_add_attrs
= true;
9748 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
9750 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9752 *no_add_attrs
= true;
9754 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
9756 /* The argument must be a constant integer. */
9757 warning (OPT_Wattributes
,
9758 "%qE attribute argument not an integer constant",
9760 *no_add_attrs
= true;
9762 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
9764 /* The argument value must be between 0 to 255. */
9765 warning (OPT_Wattributes
,
9766 "%qE attribute argument should be between 0 to 255",
9768 *no_add_attrs
= true;
9773 /* Returns true if current function has been assigned the attribute
9774 'function_vector'. */
9776 sh2a_is_function_vector_call (rtx x
)
9778 if (GET_CODE (x
) == SYMBOL_REF
9779 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
9781 tree tr
= SYMBOL_REF_DECL (x
);
9783 if (sh2a_function_vector_p (tr
))
9790 /* Returns the function vector number, if the attribute
9791 'function_vector' is assigned, otherwise returns zero. */
9793 sh2a_get_function_vector_number (rtx x
)
9798 if ((GET_CODE (x
) == SYMBOL_REF
)
9799 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
9801 t
= SYMBOL_REF_DECL (x
);
9803 if (TREE_CODE (t
) != FUNCTION_DECL
)
9806 list
= SH_ATTRIBUTES (t
);
9809 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
9811 num
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
9815 list
= TREE_CHAIN (list
);
9824 /* Handle an "sp_switch" attribute; arguments as in
9825 struct attribute_spec.handler. */
9827 sh_handle_sp_switch_attribute (tree
*node
, tree name
, tree args
,
9828 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
9830 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9832 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9834 *no_add_attrs
= true;
9836 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
9838 /* The argument must be a constant string. */
9839 warning (OPT_Wattributes
, "%qE attribute argument not a string constant",
9841 *no_add_attrs
= true;
9847 /* Handle an "trap_exit" attribute; arguments as in
9848 struct attribute_spec.handler. */
9850 sh_handle_trap_exit_attribute (tree
*node
, tree name
, tree args
,
9851 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
9853 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9855 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9857 *no_add_attrs
= true;
9859 /* The argument specifies a trap number to be used in a trapa instruction
9860 at function exit (instead of an rte instruction). */
9861 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
9863 /* The argument must be a constant integer. */
9864 warning (OPT_Wattributes
, "%qE attribute argument not an "
9865 "integer constant", name
);
9866 *no_add_attrs
= true;
9873 sh_handle_renesas_attribute (tree
*node ATTRIBUTE_UNUSED
,
9874 tree name ATTRIBUTE_UNUSED
,
9875 tree args ATTRIBUTE_UNUSED
,
9876 int flags ATTRIBUTE_UNUSED
,
9877 bool *no_add_attrs ATTRIBUTE_UNUSED
)
9882 /* True if __attribute__((renesas)) or -mrenesas. */
9884 sh_attr_renesas_p (const_tree td
)
9888 if (td
== NULL_TREE
)
9891 td
= TREE_TYPE (td
);
9892 if (td
== error_mark_node
)
9894 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td
))
9898 /* True if __attribute__((renesas)) or -mrenesas, for the current
9901 sh_cfun_attr_renesas_p (void)
9903 return sh_attr_renesas_p (current_function_decl
);
9906 /* Returns true if the current function has the "interrupt_handler"
9909 sh_cfun_interrupt_handler_p (void)
9911 return (lookup_attribute ("interrupt_handler",
9912 DECL_ATTRIBUTES (current_function_decl
))
9916 /* Returns true if FUNC has been assigned the attribute
9917 "function_vector". */
9919 sh2a_function_vector_p (tree func
)
9922 if (TREE_CODE (func
) != FUNCTION_DECL
)
9925 list
= SH_ATTRIBUTES (func
);
9928 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
9931 list
= TREE_CHAIN (list
);
9936 /* Returns true if given tree has the "resbank" attribute set. */
9938 sh_cfun_resbank_handler_p (void)
9940 return ((lookup_attribute ("resbank",
9941 DECL_ATTRIBUTES (current_function_decl
))
9943 && (lookup_attribute ("interrupt_handler",
9944 DECL_ATTRIBUTES (current_function_decl
))
9945 != NULL_TREE
) && TARGET_SH2A
);
9948 /* Returns true if the current function has a "trap_exit" attribute set. */
9950 sh_cfun_trap_exit_p (void)
9952 return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl
))
9956 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9958 sh_check_pch_target_flags (int old_flags
)
9960 if ((old_flags
^ target_flags
) & (MASK_SH1
| MASK_SH2
| MASK_SH3
9961 | MASK_SH_E
| MASK_HARD_SH4
9962 | MASK_FPU_SINGLE
| MASK_SH4
))
9963 return _("created and used with different architectures / ABIs");
9964 if ((old_flags
^ target_flags
) & MASK_HITACHI
)
9965 return _("created and used with different ABIs");
9966 if ((old_flags
^ target_flags
) & MASK_LITTLE_ENDIAN
)
9967 return _("created and used with different endianness");
9971 /* Predicates used by the templates. */
9973 /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
9974 Used only in general_movsrc_operand. */
9976 system_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
9988 /* Returns true if OP is a floating point value with value 0.0. */
9990 fp_zero_operand (rtx op
)
9994 if (GET_MODE (op
) != SFmode
)
9997 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
9998 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
10001 /* Returns true if OP is a floating point value with value 1.0. */
10003 fp_one_operand (rtx op
)
10007 if (GET_MODE (op
) != SFmode
)
10010 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
10011 return REAL_VALUES_EQUAL (r
, dconst1
);
10014 /* Return the TLS type for TLS symbols. */
10016 tls_symbolic_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
10018 if (GET_CODE (op
) != SYMBOL_REF
)
10019 return TLS_MODEL_NONE
;
10020 return SYMBOL_REF_TLS_MODEL (op
);
10023 /* Return the destination address of a branch. */
10025 branch_dest (rtx branch
)
10027 rtx dest
= SET_SRC (PATTERN (branch
));
10030 if (GET_CODE (dest
) == IF_THEN_ELSE
)
10031 dest
= XEXP (dest
, 1);
10032 dest
= XEXP (dest
, 0);
10033 dest_uid
= INSN_UID (dest
);
10034 return INSN_ADDRESSES (dest_uid
);
10037 /* Return nonzero if REG is not used after INSN.
10038 We assume REG is a reload reg, and therefore does
10039 not live past labels. It may live past calls or jumps though. */
10041 reg_unused_after (rtx reg
, rtx_insn
*insn
)
10043 enum rtx_code code
;
10046 /* If the reg is set by this instruction, then it is safe for our
10047 case. Disregard the case where this is a store to memory, since
10048 we are checking a register used in the store address. */
10049 set
= single_set (insn
);
10050 if (set
&& !MEM_P (SET_DEST (set
))
10051 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
10054 while ((insn
= NEXT_INSN (insn
)))
10057 if (!INSN_P (insn
))
10060 code
= GET_CODE (insn
);
10063 /* If this is a label that existed before reload, then the register
10064 is dead here. However, if this is a label added by reorg, then
10065 the register may still be live here. We can't tell the difference,
10066 so we just ignore labels completely. */
10067 if (code
== CODE_LABEL
)
10072 if (code
== JUMP_INSN
)
10075 /* If this is a sequence, we must handle them all at once.
10076 We could have for instance a call that sets the target register,
10077 and an insn in a delay slot that uses the register. In this case,
10078 we must return 0. */
10079 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
10081 rtx_sequence
*seq
= as_a
<rtx_sequence
*> (PATTERN (insn
));
10085 for (i
= 0; i
< seq
->len (); i
++)
10087 rtx_insn
*this_insn
= seq
->insn (i
);
10088 rtx set
= single_set (this_insn
);
10090 if (CALL_P (this_insn
))
10092 else if (JUMP_P (this_insn
))
10094 if (INSN_ANNULLED_BRANCH_P (this_insn
))
10099 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
10101 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
10103 if (!MEM_P (SET_DEST (set
)))
10108 if (set
== NULL_RTX
10109 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
10114 else if (code
== JUMP_INSN
)
10118 set
= single_set (insn
);
10119 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
10121 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
10122 return !MEM_P (SET_DEST (set
));
10123 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
10126 if (code
== CALL_INSN
&& call_really_used_regs
[REGNO (reg
)])
10133 static GTY(()) rtx t_reg_rtx
;
10135 get_t_reg_rtx (void)
10138 t_reg_rtx
= gen_rtx_REG (SImode
, T_REG
);
10142 static GTY(()) tree fpscr_values
;
10145 emit_fpu_switch (rtx scratch
, int index
)
10149 if (fpscr_values
== NULL
)
10153 t
= build_index_type (integer_one_node
);
10154 t
= build_array_type (integer_type_node
, t
);
10155 t
= build_decl (BUILTINS_LOCATION
,
10156 VAR_DECL
, get_identifier ("__fpscr_values"), t
);
10157 DECL_ARTIFICIAL (t
) = 1;
10158 DECL_IGNORED_P (t
) = 1;
10159 DECL_EXTERNAL (t
) = 1;
10160 TREE_STATIC (t
) = 1;
10161 TREE_PUBLIC (t
) = 1;
10167 src
= DECL_RTL (fpscr_values
);
10168 if (!can_create_pseudo_p ())
10170 emit_move_insn (scratch
, XEXP (src
, 0));
10172 emit_insn (gen_addsi3 (scratch
, scratch
, GEN_INT (index
* 4)));
10173 src
= adjust_automodify_address (src
, SImode
, scratch
, index
* 4);
10176 src
= adjust_address (src
, SImode
, index
* 4);
10178 emit_insn (gen_lds_fpscr (src
));
10181 static rtx
get_free_reg (HARD_REG_SET
);
10183 /* This function returns a register to use to load the address to load
10184 the fpscr from. Currently it always returns r1 or r7, but when we are
10185 able to use pseudo registers after combine, or have a better mechanism
10186 for choosing a register, it should be done here. */
10187 /* REGS_LIVE is the liveness information for the point for which we
10188 need this allocation. In some bare-bones exit blocks, r1 is live at the
10189 start. We can even have all of r0..r3 being live:
10190 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
10191 INSN before which new insns are placed with will clobber the register
10192 we return. If a basic block consists only of setting the return value
10193 register to a pseudo and using that register, the return value is not
10194 live before or after this block, yet we we'll insert our insns right in
10197 get_free_reg (HARD_REG_SET regs_live
)
10199 if (! TEST_HARD_REG_BIT (regs_live
, 1))
10200 return gen_rtx_REG (Pmode
, 1);
10202 /* Hard reg 1 is live; since this is a small register classes target,
10203 there shouldn't be anything but a jump before the function end. */
10204 gcc_assert (!TEST_HARD_REG_BIT (regs_live
, 7));
10205 return gen_rtx_REG (Pmode
, 7);
10208 /* This function will set the fpscr from memory.
10209 MODE is the mode we are setting it to. */
10211 fpscr_set_from_mem (int mode
, HARD_REG_SET regs_live
)
10213 enum attr_fp_mode fp_mode
= (enum attr_fp_mode
) mode
;
10214 enum attr_fp_mode norm_mode
= ACTUAL_NORMAL_MODE (FP_MODE
);
10217 addr_reg
= !can_create_pseudo_p () ? get_free_reg (regs_live
) : NULL_RTX
;
10218 emit_fpu_switch (addr_reg
, fp_mode
== norm_mode
);
10221 /* Is the given character a logical line separator for the assembler? */
10222 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
10223 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
10227 sequence_insn_p (rtx_insn
*insn
)
10229 rtx_insn
*prev
, *next
;
10231 prev
= PREV_INSN (insn
);
10235 next
= NEXT_INSN (prev
);
10239 return INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
;
10243 sh_insn_length_adjustment (rtx_insn
*insn
)
10245 /* Instructions with unfilled delay slots take up an extra two bytes for
10246 the nop in the delay slot. */
10247 if (((NONJUMP_INSN_P (insn
)
10248 && GET_CODE (PATTERN (insn
)) != USE
10249 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10250 || CALL_P (insn
) || JUMP_P (insn
))
10251 && ! sequence_insn_p (insn
)
10252 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
10255 /* Increase the insn length of a cbranch without a delay slot insn to
10256 force a delay slot which will be stuffed with a nop. */
10257 if (TARGET_CBRANCH_FORCE_DELAY_SLOT
&& TARGET_SH2
10258 && JUMP_P (insn
) && get_attr_type (insn
) == TYPE_CBRANCH
10259 && ! sequence_insn_p (insn
))
10262 /* sh-dsp parallel processing insn take four bytes instead of two. */
10264 if (NONJUMP_INSN_P (insn
))
10267 rtx body
= PATTERN (insn
);
10270 bool maybe_label
= true;
10272 if (GET_CODE (body
) == ASM_INPUT
)
10273 templ
= XSTR (body
, 0);
10274 else if (asm_noperands (body
) >= 0)
10276 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
, NULL
);
10281 int ppi_adjust
= 0;
10285 while (c
== ' ' || c
== '\t');
10286 /* all sh-dsp parallel-processing insns start with p.
10287 The only non-ppi sh insn starting with p is pref.
10288 The only ppi starting with pr is prnd. */
10289 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", templ
, 2))
10291 /* The repeat pseudo-insn expands two three insns, a total of
10292 six bytes in size. */
10293 else if ((c
== 'r' || c
== 'R')
10294 && ! strncasecmp ("epeat", templ
, 5))
10296 while (c
&& c
!= '\n'
10297 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
, templ
))
10299 /* If this is a label, it is obviously not a ppi insn. */
10300 if (c
== ':' && maybe_label
)
10305 else if (c
== '\'' || c
== '"')
10306 maybe_label
= false;
10310 maybe_label
= c
!= ':';
10318 /* Return TRUE for a valid displacement for the REG+disp addressing
10321 sh_legitimate_index_p (machine_mode mode
, rtx op
, bool consider_sh2a
,
10324 if (! CONST_INT_P (op
))
10327 if (TARGET_SHMEDIA
)
10331 /* Check if this is the address of an unaligned load / store. */
10332 if (mode
== VOIDmode
)
10333 return satisfies_constraint_I06 (op
);
10335 size
= GET_MODE_SIZE (mode
);
10336 return (!(INTVAL (op
) & (size
- 1))
10337 && INTVAL (op
) >= -512 * size
10338 && INTVAL (op
) < 512 * size
);
10342 const HOST_WIDE_INT offset
= INTVAL (op
);
10343 const int max_disp
= sh_max_mov_insn_displacement (mode
, consider_sh2a
);
10344 const int align_mask
= mov_insn_alignment_mask (mode
, consider_sh2a
);
10346 /* If the mode does not support any displacement always return false.
10347 Even though an index of '0' is actually always valid, it will cause
10348 troubles when e.g. a DFmode move is split into two SFmode moves,
10349 where one SFmode move will have index '0' and the other move will
10351 if (!allow_zero
&& max_disp
< 1)
10354 return offset
>= 0 && offset
<= max_disp
&& (offset
& align_mask
) == 0;
10358 /* Recognize an RTL expression that is a valid memory address for
10360 The MODE argument is the machine mode for the MEM expression
10361 that wants to use this address.
10370 sh_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
10372 if (! ALLOW_INDEXED_ADDRESS
10373 && GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0)) && REG_P (XEXP (x
, 1)))
10376 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
10379 if (MAYBE_BASE_REGISTER_RTX_P (x
, strict
))
10381 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
10382 && ! TARGET_SHMEDIA
10383 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x
, 0), strict
))
10385 else if (GET_CODE (x
) == PLUS
)
10387 rtx xop0
= XEXP (x
, 0);
10388 rtx xop1
= XEXP (x
, 1);
10390 if (REG_P (xop0
) && REGNO (xop0
) == GBR_REG
)
10391 return gbr_displacement (xop1
, mode
);
10393 if (GET_MODE_SIZE (mode
) <= 8
10394 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
)
10395 && sh_legitimate_index_p (mode
, xop1
, TARGET_SH2A
, false))
10398 if ((ALLOW_INDEXED_ADDRESS
|| GET_MODE (x
) == DImode
10399 || ((xop0
== stack_pointer_rtx
10400 || xop0
== hard_frame_pointer_rtx
)
10401 && REG_P (xop1
) && REGNO (xop1
) == R0_REG
)
10402 || ((xop1
== stack_pointer_rtx
10403 || xop1
== hard_frame_pointer_rtx
)
10404 && REG_P (xop0
) && REGNO (xop0
) == R0_REG
))
10405 && ((!TARGET_SHMEDIA
&& GET_MODE_SIZE (mode
) <= 4)
10406 || (TARGET_SHMEDIA
&& GET_MODE_SIZE (mode
) <= 8)
10407 || ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
10408 && TARGET_FMOVD
&& mode
== DFmode
)))
10410 if (MAYBE_BASE_REGISTER_RTX_P (xop1
, strict
)
10411 && MAYBE_INDEX_REGISTER_RTX_P (xop0
, strict
))
10413 if (MAYBE_INDEX_REGISTER_RTX_P (xop1
, strict
)
10414 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
))
10422 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
10423 isn't protected by a PIC unspec. */
10425 nonpic_symbol_mentioned_p (rtx x
)
10430 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
10431 || GET_CODE (x
) == PC
)
10434 /* We don't want to look into the possible MEM location of a
10435 CONST_DOUBLE, since we're not going to use it, in general. */
10436 if (GET_CODE (x
) == CONST_DOUBLE
)
10439 if (GET_CODE (x
) == UNSPEC
10440 && (XINT (x
, 1) == UNSPEC_PIC
10441 || XINT (x
, 1) == UNSPEC_GOT
10442 || XINT (x
, 1) == UNSPEC_GOTOFF
10443 || XINT (x
, 1) == UNSPEC_GOTPLT
10444 || XINT (x
, 1) == UNSPEC_GOTTPOFF
10445 || XINT (x
, 1) == UNSPEC_DTPOFF
10446 || XINT (x
, 1) == UNSPEC_TPOFF
10447 || XINT (x
, 1) == UNSPEC_PLT
10448 || XINT (x
, 1) == UNSPEC_PCREL
10449 || XINT (x
, 1) == UNSPEC_SYMOFF
10450 || XINT (x
, 1) == UNSPEC_PCREL_SYMOFF
))
10453 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10454 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
10459 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10460 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
10463 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
10470 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
10471 @GOTOFF in `reg'. */
10473 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
10476 if (tls_symbolic_operand (orig
, Pmode
) != TLS_MODEL_NONE
)
10479 if (GET_CODE (orig
) == LABEL_REF
10480 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
10482 if (reg
== NULL_RTX
)
10483 reg
= gen_reg_rtx (Pmode
);
10485 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
10488 else if (GET_CODE (orig
) == SYMBOL_REF
)
10490 if (reg
== NULL_RTX
)
10491 reg
= gen_reg_rtx (Pmode
);
10493 emit_insn (gen_symGOT2reg (reg
, orig
));
10499 /* Given a (logical) mode size and an offset in bytes, try to find a the
10500 appropriate displacement value for a mov insn. On SH the displacements
10501 are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max.
10502 15 bytes in QImode. To compensate this we create a new base address by
10503 adding an adjustment value to it.
10505 If the originally requested offset is greater than 127 we prefer using
10506 values 124..127 over 128..131 to increase opportunities to use the
10509 In some cases it is possible that a requested offset might seem unaligned
10510 or inappropriate for the mode size, like offset = 2 and mode size = 4.
10511 This is compensated by adjusting the base address so that the effective
10512 address of the displacement move insn will be aligned.
10514 This is not the best possible way of rebasing the base address, as it
10515 does not look at other present displacement addressings around it.
10516 In some cases this can create more base address adjustments than would
10517 actually be necessary. */
10524 static struct disp_adjust
10525 sh_find_mov_disp_adjust (machine_mode mode
, HOST_WIDE_INT offset
)
10527 struct disp_adjust res
= { NULL_RTX
, NULL_RTX
};
10529 /* Do not try to use SH2A's large displacements here, because this would
10530 effectively disable the small displacement insns. */
10531 const int mode_sz
= GET_MODE_SIZE (mode
);
10532 const int mov_insn_sz
= mov_insn_size (mode
, false);
10533 const int max_disp
= sh_max_mov_insn_displacement (mode
, false);
10534 const int max_disp_next
= max_disp
+ mov_insn_sz
;
10535 HOST_WIDE_INT align_modifier
= offset
> 127 ? mov_insn_sz
: 0;
10536 HOST_WIDE_INT offset_adjust
;
10538 /* In some cases this actually does happen and we must check for it. */
10539 if (mode_sz
< 1 || mode_sz
> 8 || max_disp
< 1)
10542 /* Keeps the previous behavior for QImode displacement addressing.
10543 This just decides how the offset is re-based. Removing this special
10544 case will result in slightly bigger code on average, but it's not that
10546 if (mov_insn_sz
== 1)
10547 align_modifier
= 0;
10549 offset_adjust
= ((offset
+ align_modifier
) & ~max_disp
) - align_modifier
;
10551 if (mode_sz
+ offset
- offset_adjust
<= max_disp_next
)
10553 res
.offset_adjust
= GEN_INT (offset_adjust
);
10554 res
.mov_disp
= GEN_INT (offset
- offset_adjust
);
10560 /* Try to modify an illegitimate address and make it legitimate.
10561 If we find one, return the new, valid address.
10562 Otherwise, return the original address. */
10564 sh_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
10567 x
= legitimize_pic_address (oldx
, mode
, NULL_RTX
);
10569 if (TARGET_SHMEDIA
)
10572 if (((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
10573 || (TARGET_SH2E
&& mode
== SFmode
))
10576 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
10577 && BASE_REGISTER_RTX_P (XEXP (x
, 0)))
10579 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
,
10580 INTVAL (XEXP (x
, 1)));
10582 if (adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
10584 rtx sum
= expand_binop (Pmode
, add_optab
, XEXP (x
, 0),
10585 adj
.offset_adjust
, NULL_RTX
, 0,
10587 return gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
10593 /* Attempt to replace *p, which is an address that needs reloading, with
10594 a valid memory address for an operand of mode MODE.
10595 Like for sh_legitimize_address, for the SH we try to get a normal form
10596 of the address. That will allow inheritance of the address reloads. */
10598 sh_legitimize_reload_address (rtx
*p
, machine_mode mode
, int opnum
,
10601 enum reload_type type
= (enum reload_type
) itype
;
10602 const int mode_sz
= GET_MODE_SIZE (mode
);
10607 if (! ALLOW_INDEXED_ADDRESS
10608 && GET_CODE (*p
) == PLUS
10609 && REG_P (XEXP (*p
, 0)) && REG_P (XEXP (*p
, 1)))
10611 *p
= copy_rtx (*p
);
10612 push_reload (*p
, NULL_RTX
, p
, NULL
,
10613 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10617 if (! ALLOW_INDEXED_ADDRESS
10618 && GET_CODE (*p
) == PLUS
10619 && GET_CODE (XEXP (*p
, 0)) == PLUS
)
10621 rtx sum
= gen_rtx_PLUS (Pmode
, XEXP (XEXP (*p
, 0), 0),
10622 XEXP (XEXP (*p
, 0), 1));
10623 *p
= gen_rtx_PLUS (Pmode
, sum
, XEXP (*p
, 1));
10624 push_reload (sum
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
10625 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10629 if (TARGET_SHMEDIA
)
10632 if (GET_CODE (*p
) == PLUS
&& CONST_INT_P (XEXP (*p
, 1))
10633 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p
, 0), true)
10634 && (ALLOW_INDEXED_ADDRESS
10635 || XEXP (*p
, 0) == stack_pointer_rtx
10636 || XEXP (*p
, 0) == hard_frame_pointer_rtx
))
10638 const HOST_WIDE_INT offset
= INTVAL (XEXP (*p
, 1));
10639 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
, offset
);
10641 if (TARGET_SH2A
&& mode
== DFmode
&& (offset
& 0x7))
10643 push_reload (*p
, NULL_RTX
, p
, NULL
,
10644 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10648 if (TARGET_SH2E
&& mode
== SFmode
)
10650 *p
= copy_rtx (*p
);
10651 push_reload (*p
, NULL_RTX
, p
, NULL
,
10652 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10656 /* FIXME: Do not allow to legitimize QImode and HImode displacement
10657 moves because then reload has a problem figuring the constraint
10658 that the move insn target/source reg must be R0.
10659 Or maybe some handling is wrong in sh_secondary_reload for this
10660 to work properly? */
10661 if ((mode_sz
== 4 || mode_sz
== 8)
10662 && ! (TARGET_SH4
&& mode
== DFmode
)
10663 && adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
10665 rtx sum
= gen_rtx_PLUS (Pmode
, XEXP (*p
, 0), adj
.offset_adjust
);
10666 *p
= gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
10667 push_reload (sum
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
10668 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10673 /* We must re-recognize what we created before. */
10674 if (GET_CODE (*p
) == PLUS
10675 && (mode_sz
== 4 || mode_sz
== 8)
10676 && GET_CODE (XEXP (*p
, 0)) == PLUS
10677 && CONST_INT_P (XEXP (XEXP (*p
, 0), 1))
10678 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p
, 0), 0), true)
10679 && CONST_INT_P (XEXP (*p
, 1))
10680 && ! (TARGET_SH2E
&& mode
== SFmode
))
10682 /* Because this address is so complex, we know it must have
10683 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
10684 it is already unshared, and needs no further unsharing. */
10685 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
10686 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10693 /* In the name of slightly smaller debug output, and to cater to
10694 general assembler lossage, recognize various UNSPEC sequences
10695 and turn them back into a direct symbol reference. */
10697 sh_delegitimize_address (rtx orig_x
)
10701 orig_x
= delegitimize_mem_from_attrs (orig_x
);
10706 if (GET_CODE (x
) == CONST
)
10709 if (GET_CODE (y
) == UNSPEC
)
10711 if (XINT (y
, 1) == UNSPEC_GOT
10712 || XINT (y
, 1) == UNSPEC_GOTOFF
10713 || XINT (y
, 1) == UNSPEC_SYMOFF
)
10714 return XVECEXP (y
, 0, 0);
10715 else if (XINT (y
, 1) == UNSPEC_PCREL_SYMOFF
)
10717 if (GET_CODE (XVECEXP (y
, 0, 0)) == CONST
)
10719 rtx symplt
= XEXP (XVECEXP (y
, 0, 0), 0);
10721 if (GET_CODE (symplt
) == UNSPEC
10722 && (XINT (symplt
, 1) == UNSPEC_PLT
10723 || XINT (symplt
, 1) == UNSPEC_PCREL
))
10724 return XVECEXP (symplt
, 0, 0);
10727 else if (TARGET_SHMEDIA
10728 && (XINT (y
, 1) == UNSPEC_EXTRACT_S16
10729 || XINT (y
, 1) == UNSPEC_EXTRACT_U16
))
10731 rtx offset
= XVECEXP (y
, 0, 1);
10733 x
= gen_rtx_PLUS (Pmode
, XVECEXP (y
, 0, 0), offset
);
10734 if (MEM_P (orig_x
))
10735 x
= replace_equiv_address_nv (orig_x
, x
);
10744 /* Mark the use of a constant in the literal table. If the constant
10745 has multiple labels, make it unique. */
10747 mark_constant_pool_use (rtx x
)
10749 rtx_insn
*insn
, *lab
;
10755 switch (GET_CODE (x
))
10765 /* Get the first label in the list of labels for the same constant
10766 and delete another labels in the list. */
10767 lab
= as_a
<rtx_insn
*> (x
);
10768 for (insn
= PREV_INSN (lab
); insn
; insn
= PREV_INSN (insn
))
10770 if (!LABEL_P (insn
)
10771 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
10776 for (rtx insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
10777 as_a
<rtx_insn
*> (insn
)->set_deleted ();
10779 /* Mark constants in a window. */
10780 for (insn
= NEXT_INSN (as_a
<rtx_insn
*> (x
)); insn
; insn
= NEXT_INSN (insn
))
10782 if (!NONJUMP_INSN_P (insn
))
10785 pattern
= PATTERN (insn
);
10786 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
10789 switch (XINT (pattern
, 1))
10791 case UNSPECV_CONST2
:
10792 case UNSPECV_CONST4
:
10793 case UNSPECV_CONST8
:
10794 XVECEXP (pattern
, 0, 1) = const1_rtx
;
10796 case UNSPECV_WINDOW_END
:
10797 if (XVECEXP (pattern
, 0, 0) == x
)
10800 case UNSPECV_CONST_END
:
10810 /* Return true if it's possible to redirect BRANCH1 to the destination
10811 of an unconditional jump BRANCH2. We only want to do this if the
10812 resulting branch will have a short displacement. */
10814 sh_can_follow_jump (const rtx_insn
*branch1
, const rtx_insn
*branch2
)
10816 /* Don't follow if BRANCH2 is possible to be a jump crossing between
10817 hot and cold partitions. */
10819 && flag_reorder_blocks_and_partition
10820 && simplejump_p (branch2
)
10821 && CROSSING_JUMP_P (branch2
))
10824 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
10826 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
10830 for (distance
= 0, insn
= NEXT_INSN (branch1
);
10831 insn
&& distance
< 256;
10832 insn
= PREV_INSN (insn
))
10837 distance
+= get_attr_length (insn
);
10839 for (distance
= 0, insn
= NEXT_INSN (branch1
);
10840 insn
&& distance
< 256;
10841 insn
= NEXT_INSN (insn
))
10846 distance
+= get_attr_length (insn
);
10852 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10854 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
10855 unsigned int new_reg
)
10857 /* Interrupt functions can only use registers that have already been
10858 saved by the prologue, even if they would normally be
10860 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg
))
10866 /* Function to update the integer COST
10867 based on the relationship between INSN that is dependent on
10868 DEP_INSN through the dependence LINK. The default is to make no
10869 adjustment to COST. This can be used for example to specify to
10870 the scheduler that an output- or anti-dependence does not incur
10871 the same cost as a data-dependence. The return value should be
10872 the new value for COST. */
10874 sh_adjust_cost (rtx_insn
*insn
, rtx link ATTRIBUTE_UNUSED
,
10875 rtx_insn
*dep_insn
, int cost
)
10879 if (TARGET_SHMEDIA
)
10881 /* On SHmedia, if the dependence is an anti-dependence or
10882 output-dependence, there is no cost. */
10883 if (REG_NOTE_KIND (link
) != 0)
10885 /* However, dependencies between target register loads and
10886 uses of the register in a subsequent block that are separated
10887 by a conditional branch are not modelled - we have to do with
10888 the anti-dependency between the target register load and the
10889 conditional branch that ends the current block. */
10890 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
10891 && GET_CODE (PATTERN (dep_insn
)) == SET
10892 && (get_attr_type (dep_insn
) == TYPE_PT_MEDIA
10893 || get_attr_type (dep_insn
) == TYPE_PTABS_MEDIA
)
10894 && get_attr_type (insn
) == TYPE_CBRANCH_MEDIA
)
10896 int orig_cost
= cost
;
10897 rtx note
= find_reg_note (insn
, REG_BR_PROB
, 0);
10898 rtx target
= ((!note
|| XINT (note
, 0) * 2 < REG_BR_PROB_BASE
)
10899 ? insn
: JUMP_LABEL (insn
));
10900 /* On the likely path, the branch costs 1, on the unlikely path,
10904 target
= next_active_insn (target
);
10905 while (target
&& ! flow_dependent_p (target
, dep_insn
)
10907 /* If two branches are executed in immediate succession, with the
10908 first branch properly predicted, this causes a stall at the
10909 second branch, hence we won't need the target for the
10910 second branch for two cycles after the launch of the first
10912 if (cost
> orig_cost
- 2)
10913 cost
= orig_cost
- 2;
10919 else if (get_attr_is_mac_media (insn
)
10920 && get_attr_is_mac_media (dep_insn
))
10923 else if (! reload_completed
10924 && GET_CODE (PATTERN (insn
)) == SET
10925 && GET_CODE (SET_SRC (PATTERN (insn
))) == FLOAT
10926 && GET_CODE (PATTERN (dep_insn
)) == SET
10927 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn
)), VOIDmode
)
10930 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10931 that is needed at the target. */
10932 else if (get_attr_type (insn
) == TYPE_JUMP_MEDIA
10933 && ! flow_dependent_p (insn
, dep_insn
))
10936 else if (REG_NOTE_KIND (link
) == 0)
10938 enum attr_type type
;
10941 if (recog_memoized (insn
) < 0
10942 || recog_memoized (dep_insn
) < 0)
10945 dep_set
= single_set (dep_insn
);
10947 /* The latency that we specify in the scheduling description refers
10948 to the actual output, not to an auto-increment register; for that,
10949 the latency is one. */
10950 if (dep_set
&& MEM_P (SET_SRC (dep_set
)) && cost
> 1)
10952 rtx set
= single_set (insn
);
10955 && !reg_mentioned_p (SET_DEST (dep_set
), SET_SRC (set
))
10956 && (!MEM_P (SET_DEST (set
))
10957 || !reg_mentioned_p (SET_DEST (dep_set
),
10958 XEXP (SET_DEST (set
), 0))))
10961 /* The only input for a call that is timing-critical is the
10962 function's address. */
10965 rtx call
= get_call_rtx_from (insn
);
10967 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10968 && (GET_CODE (XEXP (XEXP (call
, 0), 0)) == UNSPEC
10969 || ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
)))
10970 cost
-= TARGET_SH4_300
? 3 : 6;
10972 /* Likewise, the most timing critical input for an sfuncs call
10973 is the function address. However, sfuncs typically start
10974 using their arguments pretty quickly.
10975 Assume a four cycle delay for SH4 before they are needed.
10976 Cached ST40-300 calls are quicker, so assume only a one
10978 ??? Maybe we should encode the delays till input registers
10979 are needed by sfuncs into the sfunc call insn. */
10980 /* All sfunc calls are parallels with at least four components.
10981 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10982 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
10983 && XVECLEN (PATTERN (insn
), 0) >= 4
10984 && (reg
= sfunc_uses_reg (insn
)))
10986 if (! reg_set_p (reg
, dep_insn
))
10987 cost
-= TARGET_SH4_300
? 1 : 4;
10989 if (TARGET_HARD_SH4
&& !TARGET_SH4_300
)
10991 enum attr_type dep_type
= get_attr_type (dep_insn
);
10993 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
10995 else if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
10996 && (type
= get_attr_type (insn
)) != TYPE_CALL
10997 && type
!= TYPE_SFUNC
)
10999 /* When the preceding instruction loads the shift amount of
11000 the following SHAD/SHLD, the latency of the load is increased
11002 if (get_attr_type (insn
) == TYPE_DYN_SHIFT
11003 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
11004 && reg_overlap_mentioned_p (SET_DEST (dep_set
),
11005 XEXP (SET_SRC (single_set (insn
)),
11008 /* When an LS group instruction with a latency of less than
11009 3 cycles is followed by a double-precision floating-point
11010 instruction, FIPR, or FTRV, the latency of the first
11011 instruction is increased to 3 cycles. */
11013 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
11014 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
11016 /* The lsw register of a double-precision computation is ready one
11018 else if (reload_completed
11019 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
11020 && (use_pat
= single_set (insn
))
11021 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
11022 SET_SRC (use_pat
)))
11025 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
11026 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
11029 else if (TARGET_SH4_300
)
11031 /* Stores need their input register two cycles later. */
11032 if (dep_set
&& cost
>= 1
11033 && ((type
= get_attr_type (insn
)) == TYPE_STORE
11034 || type
== TYPE_PSTORE
11035 || type
== TYPE_FSTORE
|| type
== TYPE_MAC_MEM
))
11037 rtx set
= single_set (insn
);
11039 if (!reg_mentioned_p (SET_SRC (set
), XEXP (SET_DEST (set
), 0))
11040 && rtx_equal_p (SET_SRC (set
), SET_DEST (dep_set
)))
11043 /* But don't reduce the cost below 1 if the address depends
11044 on a side effect of dep_insn. */
11046 && modified_in_p (XEXP (SET_DEST (set
), 0), dep_insn
))
11052 /* An anti-dependence penalty of two applies if the first insn is a double
11053 precision fadd / fsub / fmul. */
11054 else if (!TARGET_SH4_300
11055 && REG_NOTE_KIND (link
) == REG_DEP_ANTI
11056 && recog_memoized (dep_insn
) >= 0
11057 && (get_attr_type (dep_insn
) == TYPE_DFP_ARITH
11058 || get_attr_type (dep_insn
) == TYPE_DFP_MUL
)
11059 /* A lot of alleged anti-flow dependences are fake,
11060 so check this one is real. */
11061 && flow_dependent_p (dep_insn
, insn
))
11067 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
11068 if DEP_INSN is anti-flow dependent on INSN. */
11070 flow_dependent_p (rtx insn
, rtx dep_insn
)
11072 rtx tmp
= PATTERN (insn
);
11074 note_stores (PATTERN (dep_insn
), flow_dependent_p_1
, &tmp
);
11075 return tmp
== NULL_RTX
;
11078 /* A helper function for flow_dependent_p called through note_stores. */
11080 flow_dependent_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
11082 rtx
* pinsn
= (rtx
*) data
;
11084 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
11088 /* For use by sh_allocate_initial_value. Note that sh.md contains some
11089 'special function' patterns (type sfunc) that clobber pr, but that
11090 do not look like function calls to leaf_function_p. Hence we must
11091 do this extra check. */
11093 sh_pr_n_sets (void)
11095 return DF_REG_DEF_COUNT (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
11098 /* Return where to allocate pseudo for a given hard register initial
11101 sh_allocate_initial_value (rtx hard_reg
)
11105 if (REGNO (hard_reg
) == (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
))
11108 && ! sh_pr_n_sets ()
11109 && ! (TARGET_SHCOMPACT
11110 && ((crtl
->args
.info
.call_cookie
11111 & ~ CALL_COOKIE_RET_TRAMP (1))
11112 || crtl
->saves_all_registers
)))
11115 x
= gen_frame_mem (Pmode
, return_address_pointer_rtx
);
11123 /* This function returns "2" to indicate dual issue for the SH4
11124 processor. To be used by the DFA pipeline description. */
11126 sh_issue_rate (void)
11128 if (TARGET_SUPERSCALAR
)
11134 /* Functions for ready queue reordering for sched1. */
11136 /* Get weight for mode for a set x. */
11138 find_set_regmode_weight (rtx x
, machine_mode mode
)
11140 if (GET_CODE (x
) == CLOBBER
&& register_operand (SET_DEST (x
), mode
))
11142 if (GET_CODE (x
) == SET
&& register_operand (SET_DEST (x
), mode
))
11144 if (REG_P (SET_DEST (x
)))
11146 if (!reg_mentioned_p (SET_DEST (x
), SET_SRC (x
)))
11156 /* Get regmode weight for insn. */
11158 find_insn_regmode_weight (rtx insn
, machine_mode mode
)
11160 short reg_weight
= 0;
11163 /* Increment weight for each register born here. */
11164 x
= PATTERN (insn
);
11165 reg_weight
+= find_set_regmode_weight (x
, mode
);
11166 if (GET_CODE (x
) == PARALLEL
)
11169 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
11171 x
= XVECEXP (PATTERN (insn
), 0, j
);
11172 reg_weight
+= find_set_regmode_weight (x
, mode
);
11175 /* Decrement weight for each register that dies here. */
11176 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
11178 if (REG_NOTE_KIND (x
) == REG_DEAD
|| REG_NOTE_KIND (x
) == REG_UNUSED
)
11180 rtx note
= XEXP (x
, 0);
11181 if (REG_P (note
) && GET_MODE (note
) == mode
)
11188 /* Calculate regmode weights for all insns of a basic block. */
11190 find_regmode_weight (basic_block b
, machine_mode mode
)
11192 rtx_insn
*insn
, *next_tail
, *head
, *tail
;
11194 get_ebb_head_tail (b
, b
, &head
, &tail
);
11195 next_tail
= NEXT_INSN (tail
);
11197 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
11199 /* Handle register life information. */
11200 if (!INSN_P (insn
))
11203 if (mode
== SFmode
)
11204 INSN_REGMODE_WEIGHT (insn
, mode
) =
11205 find_insn_regmode_weight (insn
, mode
)
11206 + 2 * find_insn_regmode_weight (insn
, DFmode
);
11207 else if (mode
== SImode
)
11208 INSN_REGMODE_WEIGHT (insn
, mode
) =
11209 find_insn_regmode_weight (insn
, mode
)
11210 + 2 * find_insn_regmode_weight (insn
, DImode
);
11214 /* Comparison function for ready queue sorting. */
11216 rank_for_reorder (const void *x
, const void *y
)
11218 rtx_insn
*tmp
= *(rtx_insn
* const *) y
;
11219 rtx_insn
*tmp2
= *(rtx_insn
* const *) x
;
11221 /* The insn in a schedule group should be issued the first. */
11222 if (SCHED_GROUP_P (tmp
) != SCHED_GROUP_P (tmp2
))
11223 return SCHED_GROUP_P (tmp2
) ? 1 : -1;
11225 /* If insns are equally good, sort by INSN_LUID (original insn order), This
11226 minimizes instruction movement, thus minimizing sched's effect on
11227 register pressure. */
11228 return INSN_LUID (tmp
) - INSN_LUID (tmp2
);
11231 /* Resort the array A in which only element at index N may be out of order. */
11233 swap_reorder (rtx_insn
**a
, int n
)
11235 rtx_insn
*insn
= a
[n
- 1];
11238 while (i
>= 0 && rank_for_reorder (a
+ i
, &insn
) >= 0)
11246 /* Sort the ready list by ascending priority. */
11248 ready_reorder (rtx_insn
**ready
, int nready
)
11251 swap_reorder (ready
, nready
);
11252 else if (nready
> 2)
11253 qsort (ready
, nready
, sizeof (rtx_insn
*), rank_for_reorder
);
11256 /* Count life regions of r0 for a block. */
11258 find_r0_life_regions (basic_block b
)
11260 rtx_insn
*end
, *insn
;
11267 if (REGNO_REG_SET_P (df_get_live_in (b
), R0_REG
))
11278 insn
= BB_HEAD (b
);
11280 r0_reg
= gen_rtx_REG (SImode
, R0_REG
);
11285 if (find_regno_note (insn
, REG_DEAD
, R0_REG
))
11291 && (pset
= single_set (insn
))
11292 && reg_overlap_mentioned_p (r0_reg
, SET_DEST (pset
))
11293 && !find_regno_note (insn
, REG_UNUSED
, R0_REG
))
11301 insn
= NEXT_INSN (insn
);
11303 return set
- death
;
11306 /* Calculate regmode weights for all insns of all basic block. */
11308 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED
,
11309 int verbose ATTRIBUTE_UNUSED
,
11314 regmode_weight
[0] = (short *) xcalloc (old_max_uid
, sizeof (short));
11315 regmode_weight
[1] = (short *) xcalloc (old_max_uid
, sizeof (short));
11316 r0_life_regions
= 0;
11318 FOR_EACH_BB_REVERSE_FN (b
, cfun
)
11320 find_regmode_weight (b
, SImode
);
11321 find_regmode_weight (b
, SFmode
);
11322 if (!reload_completed
)
11323 r0_life_regions
+= find_r0_life_regions (b
);
11326 CURR_REGMODE_PRESSURE (SImode
) = 0;
11327 CURR_REGMODE_PRESSURE (SFmode
) = 0;
11332 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
11333 int verbose ATTRIBUTE_UNUSED
)
11335 if (regmode_weight
[0])
11337 free (regmode_weight
[0]);
11338 regmode_weight
[0] = NULL
;
11340 if (regmode_weight
[1])
11342 free (regmode_weight
[1]);
11343 regmode_weight
[1] = NULL
;
11347 /* The scalar modes supported differs from the default version in TImode
11348 for 32-bit SHMEDIA. */
11350 sh_scalar_mode_supported_p (machine_mode mode
)
11352 if (TARGET_SHMEDIA32
&& mode
== TImode
)
11355 return default_scalar_mode_supported_p (mode
);
11358 /* Cache the can_issue_more so that we can return it from reorder2. Also,
11359 keep count of register pressures on SImode and SFmode. */
11361 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
11362 int sched_verbose ATTRIBUTE_UNUSED
,
11364 int can_issue_more
)
11366 if (GET_CODE (PATTERN (insn
)) != USE
11367 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
11368 cached_can_issue_more
= can_issue_more
- 1;
11370 cached_can_issue_more
= can_issue_more
;
11372 if (reload_completed
)
11373 return cached_can_issue_more
;
11375 CURR_REGMODE_PRESSURE (SImode
) += INSN_REGMODE_WEIGHT (insn
, SImode
);
11376 CURR_REGMODE_PRESSURE (SFmode
) += INSN_REGMODE_WEIGHT (insn
, SFmode
);
11378 return cached_can_issue_more
;
11382 sh_md_init (FILE *dump ATTRIBUTE_UNUSED
,
11383 int verbose ATTRIBUTE_UNUSED
,
11384 int veclen ATTRIBUTE_UNUSED
)
11386 CURR_REGMODE_PRESSURE (SImode
) = 0;
11387 CURR_REGMODE_PRESSURE (SFmode
) = 0;
11390 /* Some magic numbers. */
11391 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
11392 functions that already have high pressure on r0. */
11393 #define R0_MAX_LIFE_REGIONS 2
11394 /* Register Pressure thresholds for SImode and SFmode registers. */
11395 #define SIMODE_MAX_WEIGHT 5
11396 #define SFMODE_MAX_WEIGHT 10
11398 /* Return true if the pressure is high for MODE. */
11400 high_pressure (machine_mode mode
)
11402 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
11403 functions that already have high pressure on r0. */
11404 if (r0_life_regions
>= R0_MAX_LIFE_REGIONS
)
11407 if (mode
== SFmode
)
11408 return (CURR_REGMODE_PRESSURE (SFmode
) > SFMODE_MAX_WEIGHT
);
11410 return (CURR_REGMODE_PRESSURE (SImode
) > SIMODE_MAX_WEIGHT
);
11413 /* Reorder ready queue if register pressure is high. */
11415 sh_reorder (FILE *dump ATTRIBUTE_UNUSED
,
11416 int sched_verbose ATTRIBUTE_UNUSED
,
11419 int clock_var ATTRIBUTE_UNUSED
)
11421 if (reload_completed
)
11422 return sh_issue_rate ();
11424 if (high_pressure (SFmode
) || high_pressure (SImode
))
11426 ready_reorder (ready
, *n_readyp
);
11429 return sh_issue_rate ();
11432 /* Skip cycles if the current register pressure is high. */
11434 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
11435 int sched_verbose ATTRIBUTE_UNUSED
,
11436 rtx_insn
**ready ATTRIBUTE_UNUSED
,
11437 int *n_readyp ATTRIBUTE_UNUSED
,
11438 int clock_var ATTRIBUTE_UNUSED
)
11440 if (reload_completed
)
11441 return cached_can_issue_more
;
11443 if (high_pressure(SFmode
) || high_pressure (SImode
))
11446 return cached_can_issue_more
;
11449 /* Skip cycles without sorting the ready queue. This will move insn from
11450 Q->R. If this is the last cycle we are skipping; allow sorting of ready
11451 queue by sh_reorder. */
11453 /* Generally, skipping these many cycles are sufficient for all insns to move
11455 #define MAX_SKIPS 8
11458 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED
,
11459 int sched_verbose ATTRIBUTE_UNUSED
,
11460 rtx_insn
*insn ATTRIBUTE_UNUSED
,
11461 int last_clock_var
,
11465 if (reload_completed
)
11470 if ((clock_var
- last_clock_var
) < MAX_SKIPS
)
11475 /* If this is the last cycle we are skipping, allow reordering of R. */
11476 if ((clock_var
- last_clock_var
) == MAX_SKIPS
)
11488 /* SHmedia requires registers for branches, so we can't generate new
11489 branches past reload. */
11491 sh_cannot_modify_jumps_p (void)
11493 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
11497 sh_target_reg_class (void)
11499 return TARGET_SHMEDIA
? TARGET_REGS
: NO_REGS
;
11503 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen
)
11505 if (! shmedia_space_reserved_for_target_registers
)
11507 if (after_prologue_epilogue_gen
&& ! TARGET_SAVE_ALL_TARGET_REGS
)
11510 HARD_REG_SET dummy
;
11511 if (calc_live_regs (&dummy
) >= 6 * 8)
11517 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED
)
11519 return (TARGET_SH5
|| TARGET_HITACHI
|| sh_attr_renesas_p (record_type
));
11523 On the SH1..SH4, the trampoline looks like
11524 2 0002 D202 mov.l l2,r2
11525 1 0000 D301 mov.l l1,r3
11526 3 0004 422B jmp @r2
11528 5 0008 00000000 l1: .long area
11529 6 000c 00000000 l2: .long function
11531 SH5 (compact) uses r1 instead of r3 for the static chain. */
11534 /* Emit RTL insns to initialize the variable parts of a trampoline.
11535 FNADDR is an RTX for the address of the function's pure code.
11536 CXT is an RTX for the static chain value for the function. */
11538 sh_trampoline_init (rtx tramp_mem
, tree fndecl
, rtx cxt
)
11540 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
11541 rtx tramp
= force_reg (Pmode
, XEXP (tramp_mem
, 0));
11543 if (TARGET_SHMEDIA64
)
11548 rtx movi1
= GEN_INT (0xcc000010);
11549 rtx shori1
= GEN_INT (0xc8000010);
11552 /* The following trampoline works within a +- 128 KB range for cxt:
11553 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
11554 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
11555 gettr tr1,r1; blink tr0,r63 */
11556 /* Address rounding makes it hard to compute the exact bounds of the
11557 offset for this trampoline, but we have a rather generous offset
11558 range, so frame_offset should do fine as an upper bound. */
11559 if (cxt
== virtual_stack_vars_rtx
&& frame_offset
< 0x20000)
11561 /* ??? could optimize this trampoline initialization
11562 by writing DImode words with two insns each. */
11563 rtx mask
= force_reg (DImode
, GEN_INT (0x3fffc00));
11564 rtx insn
= gen_rtx_MINUS (DImode
, cxt
, tramp
);
11565 insn
= gen_rtx_ASHIFT (DImode
, insn
, GEN_INT (10-2));
11566 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11567 /* Or in ptb/u .,tr1 pattern */
11568 insn
= gen_rtx_IOR (DImode
, insn
, gen_int_mode (0xec000010, SImode
));
11569 insn
= force_operand (insn
, NULL_RTX
);
11570 insn
= gen_lowpart (SImode
, insn
);
11571 emit_move_insn (change_address (tramp_mem
, SImode
, NULL_RTX
), insn
);
11572 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (38));
11573 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11574 insn
= force_operand (gen_rtx_IOR (DImode
, movi1
, insn
), NULL_RTX
);
11575 insn
= gen_lowpart (SImode
, insn
);
11576 emit_move_insn (adjust_address (tramp_mem
, SImode
, 4), insn
);
11577 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (22));
11578 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11579 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
11580 insn
= gen_lowpart (SImode
, insn
);
11581 emit_move_insn (adjust_address (tramp_mem
, SImode
, 8), insn
);
11582 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (6));
11583 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11584 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
11585 insn
= gen_lowpart (SImode
, insn
);
11586 emit_move_insn (adjust_address (tramp_mem
, SImode
, 12), insn
);
11587 insn
= gen_rtx_ASHIFT (DImode
, fnaddr
, GEN_INT (10));
11588 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11589 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
11590 insn
= gen_lowpart (SImode
, insn
);
11591 emit_move_insn (adjust_address (tramp_mem
, SImode
, 16), insn
);
11592 emit_move_insn (adjust_address (tramp_mem
, SImode
, 20),
11593 GEN_INT (0x6bf10600));
11594 emit_move_insn (adjust_address (tramp_mem
, SImode
, 24),
11595 GEN_INT (0x4415fc10));
11596 emit_move_insn (adjust_address (tramp_mem
, SImode
, 28),
11597 GEN_INT (0x4401fff0));
11598 emit_insn (gen_ic_invalidate_line (tramp
));
11601 tramp_templ
= gen_rtx_SYMBOL_REF (Pmode
,"__GCC_nested_trampoline");
11602 fixed_len
= TRAMPOLINE_SIZE
- 2 * GET_MODE_SIZE (Pmode
);
11604 tramp_templ
= gen_datalabel_ref (tramp_templ
);
11606 src
= gen_const_mem (BLKmode
, tramp_templ
);
11607 set_mem_align (dst
, 256);
11608 set_mem_align (src
, 64);
11609 emit_block_move (dst
, src
, GEN_INT (fixed_len
), BLOCK_OP_NORMAL
);
11611 emit_move_insn (adjust_address (tramp_mem
, Pmode
, fixed_len
), fnaddr
);
11612 emit_move_insn (adjust_address (tramp_mem
, Pmode
,
11613 fixed_len
+ GET_MODE_SIZE (Pmode
)),
11615 emit_insn (gen_ic_invalidate_line (tramp
));
11618 else if (TARGET_SHMEDIA
)
11620 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
11621 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
11622 rtx quad0
= gen_reg_rtx (DImode
), cxtload
= gen_reg_rtx (DImode
);
11623 rtx quad1
= gen_reg_rtx (DImode
), quad2
= gen_reg_rtx (DImode
);
11624 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
11625 rotated 10 right, and higher 16 bit of every 32 selected. */
11627 = force_reg (V2HImode
, (simplify_gen_subreg
11628 (V2HImode
, GEN_INT (0x4330432), SImode
, 0)));
11629 rtx ptabs
= force_reg (DImode
, GEN_INT (0x6bf10600));
11630 rtx blink
= force_reg (DImode
, GEN_INT (0x4401fff0));
11632 fnaddr
= force_reg (SImode
, fnaddr
);
11633 cxt
= force_reg (SImode
, cxt
);
11634 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, quad0
, 0),
11635 gen_rtx_SUBREG (V2HImode
, fnaddr
, 0),
11637 emit_insn (gen_rotrdi3_mextr (quad0
, quad0
,
11638 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
11639 emit_insn (gen_ashldi3_media (quad0
, quad0
, const2_rtx
));
11640 emit_move_insn (change_address (tramp_mem
, DImode
, NULL_RTX
), quad0
);
11641 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, cxtload
, 0),
11642 gen_rtx_SUBREG (V2HImode
, cxt
, 0),
11644 emit_insn (gen_rotrdi3_mextr (cxtload
, cxtload
,
11645 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
11646 emit_insn (gen_ashldi3_media (cxtload
, cxtload
, const2_rtx
));
11647 if (TARGET_LITTLE_ENDIAN
)
11649 emit_insn (gen_mshflo_l_di (quad1
, ptabs
, cxtload
));
11650 emit_insn (gen_mextr4 (quad2
, cxtload
, blink
));
11654 emit_insn (gen_mextr4 (quad1
, cxtload
, ptabs
));
11655 emit_insn (gen_mshflo_l_di (quad2
, blink
, cxtload
));
11657 emit_move_insn (adjust_address (tramp_mem
, DImode
, 8), quad1
);
11658 emit_move_insn (adjust_address (tramp_mem
, DImode
, 16), quad2
);
11659 emit_insn (gen_ic_invalidate_line (tramp
));
11662 else if (TARGET_SHCOMPACT
)
11664 emit_insn (gen_initialize_trampoline (tramp
, cxt
, fnaddr
));
11667 emit_move_insn (change_address (tramp_mem
, SImode
, NULL_RTX
),
11668 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0xd301d202 : 0xd202d301,
11670 emit_move_insn (adjust_address (tramp_mem
, SImode
, 4),
11671 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0x0009422b : 0x422b0009,
11673 emit_move_insn (adjust_address (tramp_mem
, SImode
, 8), cxt
);
11674 emit_move_insn (adjust_address (tramp_mem
, SImode
, 12), fnaddr
);
11675 if (TARGET_HARD_SH4
|| TARGET_SH5
)
11677 if (!TARGET_INLINE_IC_INVALIDATE
11678 || (!(TARGET_SH4A
|| TARGET_SH4_300
) && TARGET_USERMODE
))
11679 emit_library_call (function_symbol (NULL
, "__ic_invalidate",
11680 FUNCTION_ORDINARY
),
11681 LCT_NORMAL
, VOIDmode
, 1, tramp
, SImode
);
11683 emit_insn (gen_ic_invalidate_line (tramp
));
11687 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
11689 sh_trampoline_adjust_address (rtx tramp
)
11691 if (TARGET_SHMEDIA
)
11692 tramp
= expand_simple_binop (Pmode
, PLUS
, tramp
, const1_rtx
,
11693 gen_reg_rtx (Pmode
), 0, OPTAB_LIB_WIDEN
);
11697 /* FIXME: This is overly conservative. A SHcompact function that
11698 receives arguments ``by reference'' will have them stored in its
11699 own stack frame, so it must not pass pointers or references to
11700 these arguments to other functions by means of sibling calls. */
11701 /* If PIC, we cannot make sibling calls to global functions
11702 because the PLT requires r12 to be live. */
11704 sh_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
11707 && (! TARGET_SHCOMPACT
11708 || crtl
->args
.info
.stack_regs
== 0)
11709 && ! sh_cfun_interrupt_handler_p ()
11711 || (decl
&& ! (TREE_PUBLIC (decl
) || DECL_WEAK (decl
)))
11712 || (decl
&& DECL_VISIBILITY (decl
) != VISIBILITY_DEFAULT
)));
11715 /* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
11717 sh_expand_sym_label2reg (rtx reg
, rtx sym
, rtx lab
, bool sibcall_p
)
11719 const_tree decl
= SYMBOL_REF_DECL (sym
);
11720 bool is_weak
= (decl
&& DECL_P (decl
) && DECL_WEAK (decl
));
11722 if (!is_weak
&& SYMBOL_REF_LOCAL_P (sym
))
11723 emit_insn (gen_sym_label2reg (reg
, sym
, lab
));
11724 else if (sibcall_p
)
11725 emit_insn (gen_symPCREL_label2reg (reg
, sym
, lab
));
11727 emit_insn (gen_symPLT_label2reg (reg
, sym
, lab
));
11730 /* Machine specific built-in functions. */
11732 struct builtin_description
11734 bool (* const is_enabled
) (void);
11735 const enum insn_code icode
;
11736 const char *const name
;
11742 shmedia_builtin_p (void)
11744 return TARGET_SHMEDIA
;
11747 /* This function can be used if there are any built-ins that are not for
11748 SHmedia. It's commented out to avoid the defined-but-unused warning. */
11750 sh1_builtin_p (void)
11755 /* describe number and signedness of arguments; arg[0] == result
11756 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
11757 /* 9: 64-bit pointer, 10: 32-bit pointer */
11758 static const char signature_args
[][4] =
11760 #define SH_BLTIN_V2SI2 0
11762 #define SH_BLTIN_V4HI2 1
11764 #define SH_BLTIN_V2SI3 2
11766 #define SH_BLTIN_V4HI3 3
11768 #define SH_BLTIN_V8QI3 4
11770 #define SH_BLTIN_MAC_HISI 5
11772 #define SH_BLTIN_SH_HI 6
11774 #define SH_BLTIN_SH_SI 7
11776 #define SH_BLTIN_V4HI2V2SI 8
11778 #define SH_BLTIN_V4HI2V8QI 9
11780 #define SH_BLTIN_SISF 10
11782 #define SH_BLTIN_LDUA_L 11
11784 #define SH_BLTIN_LDUA_Q 12
11786 #define SH_BLTIN_STUA_L 13
11788 #define SH_BLTIN_STUA_Q 14
11790 #define SH_BLTIN_LDUA_L64 15
11792 #define SH_BLTIN_LDUA_Q64 16
11794 #define SH_BLTIN_STUA_L64 17
11796 #define SH_BLTIN_STUA_Q64 18
11798 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
11799 #define SH_BLTIN_2 19
11800 #define SH_BLTIN_SU 19
11802 #define SH_BLTIN_3 20
11803 #define SH_BLTIN_SUS 20
11805 #define SH_BLTIN_PSSV 21
11807 #define SH_BLTIN_XXUU 22
11808 #define SH_BLTIN_UUUU 22
11810 #define SH_BLTIN_PV 23
11812 #define SH_BLTIN_VP 24
11814 #define SH_BLTIN_UV 25
11816 #define SH_BLTIN_VU 26
11819 /* mcmv: operands considered unsigned. */
11820 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
11821 /* mperm: control value considered unsigned int. */
11822 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
11823 /* mshards_q: returns signed short. */
11824 /* nsb: takes long long arg, returns unsigned char. */
11825 static struct builtin_description bdesc
[] =
11827 { shmedia_builtin_p
,
11828 CODE_FOR_absv2si2
, "__builtin_absv2si2", SH_BLTIN_V2SI2
, 0 },
11829 { shmedia_builtin_p
,
11830 CODE_FOR_absv4hi2
, "__builtin_absv4hi2", SH_BLTIN_V4HI2
, 0 },
11831 { shmedia_builtin_p
,
11832 CODE_FOR_addv2si3
, "__builtin_addv2si3", SH_BLTIN_V2SI3
, 0 },
11833 { shmedia_builtin_p
,
11834 CODE_FOR_addv4hi3
, "__builtin_addv4hi3", SH_BLTIN_V4HI3
, 0 },
11835 { shmedia_builtin_p
,
11836 CODE_FOR_ssaddv2si3
,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3
, 0 },
11837 { shmedia_builtin_p
,
11838 CODE_FOR_usaddv8qi3
,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3
, 0 },
11839 { shmedia_builtin_p
,
11840 CODE_FOR_ssaddv4hi3
,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3
, 0 },
11841 { shmedia_builtin_p
,
11842 CODE_FOR_alloco_i
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
, 0 },
11843 { shmedia_builtin_p
,
11844 CODE_FOR_negcmpeqv8qi
,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3
, 0 },
11845 { shmedia_builtin_p
,
11846 CODE_FOR_negcmpeqv2si
,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3
, 0 },
11847 { shmedia_builtin_p
,
11848 CODE_FOR_negcmpeqv4hi
,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3
, 0 },
11849 { shmedia_builtin_p
,
11850 CODE_FOR_negcmpgtuv8qi
,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3
, 0 },
11851 { shmedia_builtin_p
,
11852 CODE_FOR_negcmpgtv2si
,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3
, 0 },
11853 { shmedia_builtin_p
,
11854 CODE_FOR_negcmpgtv4hi
,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3
, 0 },
11855 { shmedia_builtin_p
,
11856 CODE_FOR_mcmv
, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU
, 0 },
11857 { shmedia_builtin_p
,
11858 CODE_FOR_mcnvs_lw
, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3
, 0 },
11859 { shmedia_builtin_p
,
11860 CODE_FOR_mcnvs_wb
, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI
, 0 },
11861 { shmedia_builtin_p
,
11862 CODE_FOR_mcnvs_wub
, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI
, 0 },
11863 { shmedia_builtin_p
,
11864 CODE_FOR_mextr1
, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3
, 0 },
11865 { shmedia_builtin_p
,
11866 CODE_FOR_mextr2
, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3
, 0 },
11867 { shmedia_builtin_p
,
11868 CODE_FOR_mextr3
, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3
, 0 },
11869 { shmedia_builtin_p
,
11870 CODE_FOR_mextr4
, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3
, 0 },
11871 { shmedia_builtin_p
,
11872 CODE_FOR_mextr5
, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3
, 0 },
11873 { shmedia_builtin_p
,
11874 CODE_FOR_mextr6
, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3
, 0 },
11875 { shmedia_builtin_p
,
11876 CODE_FOR_mextr7
, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3
, 0 },
11877 { shmedia_builtin_p
,
11878 CODE_FOR_mmacfx_wl
, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI
, 0 },
11879 { shmedia_builtin_p
,
11880 CODE_FOR_mmacnfx_wl
,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI
, 0 },
11881 { shmedia_builtin_p
,
11882 CODE_FOR_mulv2si3
, "__builtin_mulv2si3", SH_BLTIN_V2SI3
, 0 },
11883 { shmedia_builtin_p
,
11884 CODE_FOR_mulv4hi3
, "__builtin_mulv4hi3", SH_BLTIN_V4HI3
, 0 },
11885 { shmedia_builtin_p
,
11886 CODE_FOR_mmulfx_l
, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3
, 0 },
11887 { shmedia_builtin_p
,
11888 CODE_FOR_mmulfx_w
, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3
, 0 },
11889 { shmedia_builtin_p
,
11890 CODE_FOR_mmulfxrp_w
,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3
, 0 },
11891 { shmedia_builtin_p
,
11892 CODE_FOR_mmulhi_wl
, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI
, 0 },
11893 { shmedia_builtin_p
,
11894 CODE_FOR_mmullo_wl
, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI
, 0 },
11895 { shmedia_builtin_p
,
11896 CODE_FOR_mmulsum_wq
,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU
, 0 },
11897 { shmedia_builtin_p
,
11898 CODE_FOR_mperm_w
, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI
, 0 },
11899 { shmedia_builtin_p
,
11900 CODE_FOR_msad_ubq
, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU
, 0 },
11901 { shmedia_builtin_p
,
11902 CODE_FOR_mshalds_l
, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI
, 0 },
11903 { shmedia_builtin_p
,
11904 CODE_FOR_mshalds_w
, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI
, 0 },
11905 { shmedia_builtin_p
,
11906 CODE_FOR_ashrv2si3
, "__builtin_ashrv2si3", SH_BLTIN_SH_SI
, 0 },
11907 { shmedia_builtin_p
,
11908 CODE_FOR_ashrv4hi3
, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI
, 0 },
11909 { shmedia_builtin_p
,
11910 CODE_FOR_mshards_q
, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS
, 0 },
11911 { shmedia_builtin_p
,
11912 CODE_FOR_mshfhi_b
, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3
, 0 },
11913 { shmedia_builtin_p
,
11914 CODE_FOR_mshfhi_l
, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3
, 0 },
11915 { shmedia_builtin_p
,
11916 CODE_FOR_mshfhi_w
, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3
, 0 },
11917 { shmedia_builtin_p
,
11918 CODE_FOR_mshflo_b
, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3
, 0 },
11919 { shmedia_builtin_p
,
11920 CODE_FOR_mshflo_l
, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3
, 0 },
11921 { shmedia_builtin_p
,
11922 CODE_FOR_mshflo_w
, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3
, 0 },
11923 { shmedia_builtin_p
,
11924 CODE_FOR_ashlv2si3
, "__builtin_ashlv2si3", SH_BLTIN_SH_SI
, 0 },
11925 { shmedia_builtin_p
,
11926 CODE_FOR_ashlv4hi3
, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI
, 0 },
11927 { shmedia_builtin_p
,
11928 CODE_FOR_lshrv2si3
, "__builtin_lshrv2si3", SH_BLTIN_SH_SI
, 0 },
11929 { shmedia_builtin_p
,
11930 CODE_FOR_lshrv4hi3
, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI
, 0 },
11931 { shmedia_builtin_p
,
11932 CODE_FOR_subv2si3
, "__builtin_subv2si3", SH_BLTIN_V2SI3
, 0 },
11933 { shmedia_builtin_p
,
11934 CODE_FOR_subv4hi3
, "__builtin_subv4hi3", SH_BLTIN_V4HI3
, 0 },
11935 { shmedia_builtin_p
,
11936 CODE_FOR_sssubv2si3
,"__builtin_sssubv2si3", SH_BLTIN_V2SI3
, 0 },
11937 { shmedia_builtin_p
,
11938 CODE_FOR_ussubv8qi3
,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3
, 0 },
11939 { shmedia_builtin_p
,
11940 CODE_FOR_sssubv4hi3
,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3
, 0 },
11941 { shmedia_builtin_p
,
11942 CODE_FOR_fcosa_s
, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF
, 0 },
11943 { shmedia_builtin_p
,
11944 CODE_FOR_fsina_s
, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF
, 0 },
11945 { shmedia_builtin_p
,
11946 CODE_FOR_fipr
, "__builtin_sh_media_FIPR_S", SH_BLTIN_3
, 0 },
11947 { shmedia_builtin_p
,
11948 CODE_FOR_ftrv
, "__builtin_sh_media_FTRV_S", SH_BLTIN_3
, 0 },
11949 { shmedia_builtin_p
,
11950 CODE_FOR_sqrtdf2
, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2
, 0 },
11951 { shmedia_builtin_p
,
11952 CODE_FOR_sqrtsf2
, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2
, 0 },
11953 { shmedia_builtin_p
,
11954 CODE_FOR_fsrra_s
, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2
, 0 },
11955 { shmedia_builtin_p
,
11956 CODE_FOR_ldhi_l
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
, 0 },
11957 { shmedia_builtin_p
,
11958 CODE_FOR_ldhi_q
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
, 0 },
11959 { shmedia_builtin_p
,
11960 CODE_FOR_ldlo_l
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
, 0 },
11961 { shmedia_builtin_p
,
11962 CODE_FOR_ldlo_q
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
, 0 },
11963 { shmedia_builtin_p
,
11964 CODE_FOR_sthi_l
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
, 0 },
11965 { shmedia_builtin_p
,
11966 CODE_FOR_sthi_q
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
, 0 },
11967 { shmedia_builtin_p
,
11968 CODE_FOR_stlo_l
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
, 0 },
11969 { shmedia_builtin_p
,
11970 CODE_FOR_stlo_q
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
, 0 },
11971 { shmedia_builtin_p
,
11972 CODE_FOR_ldhi_l64
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64
, 0 },
11973 { shmedia_builtin_p
,
11974 CODE_FOR_ldhi_q64
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64
, 0 },
11975 { shmedia_builtin_p
,
11976 CODE_FOR_ldlo_l64
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64
, 0 },
11977 { shmedia_builtin_p
,
11978 CODE_FOR_ldlo_q64
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64
, 0 },
11979 { shmedia_builtin_p
,
11980 CODE_FOR_sthi_l64
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64
, 0 },
11981 { shmedia_builtin_p
,
11982 CODE_FOR_sthi_q64
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64
, 0 },
11983 { shmedia_builtin_p
,
11984 CODE_FOR_stlo_l64
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64
, 0 },
11985 { shmedia_builtin_p
,
11986 CODE_FOR_stlo_q64
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64
, 0 },
11987 { shmedia_builtin_p
,
11988 CODE_FOR_nsb
, "__builtin_sh_media_NSB", SH_BLTIN_SU
, 0 },
11989 { shmedia_builtin_p
,
11990 CODE_FOR_byterev
, "__builtin_sh_media_BYTEREV", SH_BLTIN_2
, 0 },
11991 { shmedia_builtin_p
,
11992 CODE_FOR_prefetch
, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV
, 0 },
11995 CODE_FOR_sts_fpscr
, "__builtin_sh_get_fpscr", SH_BLTIN_UV
, 0 },
11997 CODE_FOR_set_fpscr
, "__builtin_sh_set_fpscr", SH_BLTIN_VU
, 0 },
12000 static tree sh_builtin_get_fpscr
;
12001 static tree sh_builtin_set_fpscr
;
12004 sh_init_builtins (void)
12006 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
12007 memset (shared
, 0, sizeof shared
);
12009 for (unsigned int di
= 0; di
< ARRAY_SIZE (bdesc
); ++di
)
12011 builtin_description
* d
= &bdesc
[di
];
12013 if (!d
->is_enabled ())
12016 tree type
, arg_type
= NULL_TREE
;
12017 int signature
= d
->signature
;
12019 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
12020 type
= shared
[signature
];
12023 int has_result
= signature_args
[signature
][0] != 0;
12026 if ((signature_args
[signature
][1] & 8)
12027 && (((signature_args
[signature
][1] & 1) && TARGET_SHMEDIA32
)
12028 || ((signature_args
[signature
][1] & 2) && TARGET_SHMEDIA64
)))
12030 if (! TARGET_FPU_ANY
12031 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
12033 for (unsigned int i
= 0; i
< ARRAY_SIZE (args
); i
++)
12034 args
[i
] = NULL_TREE
;
12035 for (int i
= 3; ; i
--)
12037 int arg
= signature_args
[signature
][i
];
12038 int opno
= i
- 1 + has_result
;
12041 arg_type
= ptr_type_node
;
12043 arg_type
= (*lang_hooks
.types
.type_for_mode
)
12044 (insn_data
[d
->icode
].operand
[opno
].mode
, (arg
& 1));
12048 arg_type
= void_type_node
;
12051 args
[i
-1] = arg_type
;
12053 type
= build_function_type_list (arg_type
, args
[0], args
[1],
12054 args
[2], NULL_TREE
);
12055 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
12056 shared
[signature
] = type
;
12059 add_builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
12061 /* Recode {sts,set}_fpscr decls for sh_atomic_assign_expand_fenv. */
12062 if (d
->icode
== CODE_FOR_sts_fpscr
)
12063 sh_builtin_get_fpscr
= d
->fndecl
;
12064 else if (d
->icode
== CODE_FOR_set_fpscr
)
12065 sh_builtin_set_fpscr
= d
->fndecl
;
12069 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
12072 sh_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
12074 const unsigned SH_FE_INVALID
= 64;
12075 const unsigned SH_FE_DIVBYZERO
= 32;
12076 const unsigned SH_FE_OVERFLOW
= 16;
12077 const unsigned SH_FE_UNDERFLOW
= 8;
12078 const unsigned SH_FE_INEXACT
= 4;
12079 const unsigned HOST_WIDE_INT SH_FE_ALL_EXCEPT
= (SH_FE_INVALID
12084 const unsigned HOST_WIDE_INT SH_FE_EXCEPT_SHIFT
= 5;
12085 tree fenv_var
, mask
, ld_fenv
, masked_fenv
;
12086 tree new_fenv_var
, reload_fenv
, restore_fnenv
;
12087 tree update_call
, atomic_feraiseexcept
, hold_fnclex
;
12089 if (! TARGET_FPU_ANY
)
12092 /* Generate the equivalent of :
12093 unsigned int fenv_var;
12094 fenv_var = __builtin_sh_get_fpscr ();
12096 unsigned int masked_fenv;
12097 masked_fenv = fenv_var & mask;
12099 __builtin_sh_set_fpscr (masked_fenv); */
12101 fenv_var
= create_tmp_var (unsigned_type_node
);
12102 mask
= build_int_cst (unsigned_type_node
,
12103 ~((SH_FE_ALL_EXCEPT
<< SH_FE_EXCEPT_SHIFT
)
12104 | SH_FE_ALL_EXCEPT
));
12105 ld_fenv
= build2 (MODIFY_EXPR
, unsigned_type_node
,
12106 fenv_var
, build_call_expr (sh_builtin_get_fpscr
, 0));
12107 masked_fenv
= build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
, mask
);
12108 hold_fnclex
= build_call_expr (sh_builtin_set_fpscr
, 1, masked_fenv
);
12109 *hold
= build2 (COMPOUND_EXPR
, void_type_node
,
12110 build2 (COMPOUND_EXPR
, void_type_node
, masked_fenv
, ld_fenv
),
12113 /* Store the value of masked_fenv to clear the exceptions:
12114 __builtin_sh_set_fpscr (masked_fenv); */
12116 *clear
= build_call_expr (sh_builtin_set_fpscr
, 1, masked_fenv
);
12118 /* Generate the equivalent of :
12119 unsigned int new_fenv_var;
12120 new_fenv_var = __builtin_sh_get_fpscr ();
12122 __builtin_sh_set_fpscr (fenv_var);
12124 __atomic_feraiseexcept (new_fenv_var); */
12126 new_fenv_var
= create_tmp_var (unsigned_type_node
);
12127 reload_fenv
= build2 (MODIFY_EXPR
, unsigned_type_node
, new_fenv_var
,
12128 build_call_expr (sh_builtin_get_fpscr
, 0));
12129 restore_fnenv
= build_call_expr (sh_builtin_set_fpscr
, 1, fenv_var
);
12130 atomic_feraiseexcept
= builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
12131 update_call
= build_call_expr (atomic_feraiseexcept
, 1,
12132 fold_convert (integer_type_node
,
12134 *update
= build2 (COMPOUND_EXPR
, void_type_node
,
12135 build2 (COMPOUND_EXPR
, void_type_node
,
12136 reload_fenv
, restore_fnenv
), update_call
);
12139 /* Implements target hook vector_mode_supported_p. */
12141 sh_vector_mode_supported_p (machine_mode mode
)
12144 && ((mode
== V2SFmode
)
12145 || (mode
== V4SFmode
)
12146 || (mode
== V16SFmode
)))
12149 else if (TARGET_SHMEDIA
12150 && ((mode
== V8QImode
)
12151 || (mode
== V2HImode
)
12152 || (mode
== V4HImode
)
12153 || (mode
== V2SImode
)))
12160 sh_frame_pointer_required (void)
12162 /* If needed override this in other tm.h files to cope with various OS
12163 lossage requiring a frame pointer. */
12164 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
12173 /* Implements target hook dwarf_calling_convention. Return an enum
12174 of dwarf_calling_convention. */
12176 sh_dwarf_calling_convention (const_tree func
)
12178 if (sh_attr_renesas_p (func
))
12179 return DW_CC_GNU_renesas_sh
;
12181 return DW_CC_normal
;
12184 /* Returns the sh builtin decl for CODE. */
12186 sh_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
12188 if (code
>= ARRAY_SIZE (bdesc
))
12189 return error_mark_node
;
12191 if (!bdesc
[code
].is_enabled ())
12192 return error_mark_node
;
12194 return bdesc
[code
].fndecl
;
12197 /* Expand an expression EXP that calls a built-in function,
12198 with result going to TARGET if that's convenient
12199 (and in mode MODE if that's convenient).
12200 SUBTARGET may be used as the target for computing one of EXP's operands.
12201 IGNORE is nonzero if the value is to be ignored. */
12203 sh_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
12204 machine_mode mode ATTRIBUTE_UNUSED
, int ignore
)
12206 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12207 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12208 const struct builtin_description
*d
= &bdesc
[fcode
];
12209 enum insn_code icode
= d
->icode
;
12210 int signature
= d
->signature
;
12214 if (signature_args
[signature
][0])
12219 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12220 if (! target
|| GET_MODE (target
) != tmode
12221 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12222 target
= gen_reg_rtx (tmode
);
12223 op
[nop
++] = target
;
12228 for (int i
= 1; i
<= 3; i
++, nop
++)
12231 machine_mode opmode
, argmode
;
12234 if (! signature_args
[signature
][i
])
12236 arg
= CALL_EXPR_ARG (exp
, i
- 1);
12237 if (arg
== error_mark_node
)
12239 if (signature_args
[signature
][i
] & 8)
12242 optype
= ptr_type_node
;
12246 opmode
= insn_data
[icode
].operand
[nop
].mode
;
12247 optype
= (*lang_hooks
.types
.type_for_mode
) (opmode
, 0);
12249 argmode
= TYPE_MODE (TREE_TYPE (arg
));
12250 if (argmode
!= opmode
)
12251 arg
= build1 (NOP_EXPR
, optype
, arg
);
12252 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, EXPAND_NORMAL
);
12253 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
12254 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
12257 rtx pat
= NULL_RTX
;
12262 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
12265 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
12268 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
12271 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
12274 gcc_unreachable ();
12283 sh_expand_unop_v2sf (enum rtx_code code
, rtx op0
, rtx op1
)
12285 rtx sel0
= const0_rtx
;
12286 rtx sel1
= const1_rtx
;
12287 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
, rtx
) = gen_unary_sf_op
;
12288 rtx op
= gen_rtx_fmt_e (code
, SFmode
, op1
);
12290 emit_insn ((*fn
) (op0
, op1
, op
, sel0
, sel0
));
12291 emit_insn ((*fn
) (op0
, op1
, op
, sel1
, sel1
));
12295 sh_expand_binop_v2sf (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
12297 rtx op
= gen_rtx_fmt_ee (code
, SFmode
, op1
, op2
);
12299 emit_insn (gen_binary_sf_op0 (op0
, op1
, op2
, op
));
12300 emit_insn (gen_binary_sf_op1 (op0
, op1
, op2
, op
));
12303 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
12304 We can allow any mode in any general register. The special registers
12305 only allow SImode. Don't allow any mode in the PR.
12307 We cannot hold DCmode values in the XD registers because alter_reg
12308 handles subregs of them incorrectly. We could work around this by
12309 spacing the XD registers like the DR registers, but this would require
12310 additional memory in every compilation to hold larger register vectors.
12311 We could hold SFmode / SCmode values in XD registers, but that
12312 would require a tertiary reload when reloading from / to memory,
12313 and a secondary reload to reload from / to general regs; that
12314 seems to be a losing proposition.
12316 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
12317 it won't be ferried through GP registers first. */
12319 sh_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
12321 if (SPECIAL_REGISTER_P (regno
))
12322 return mode
== SImode
;
12324 if (regno
== FPUL_REG
)
12325 return (mode
== SImode
|| mode
== SFmode
);
12327 if (FP_REGISTER_P (regno
) && mode
== SFmode
)
12330 if (mode
== V2SFmode
)
12332 if (((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 2 == 0)
12333 || GENERAL_REGISTER_P (regno
)))
12339 if (mode
== V4SFmode
)
12341 if ((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 4 == 0)
12342 || GENERAL_REGISTER_P (regno
))
12348 if (mode
== V16SFmode
)
12350 if (TARGET_SHMEDIA
)
12352 if (FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 16 == 0)
12358 return regno
== FIRST_XD_REG
;
12361 if (FP_REGISTER_P (regno
))
12365 || ((TARGET_SH2E
|| TARGET_SHMEDIA
) && mode
== SCmode
)
12366 || ((((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
12369 && (mode
== DFmode
|| mode
== DImode
12370 || mode
== V2SFmode
|| mode
== TImode
)))
12371 && ((regno
- FIRST_FP_REG
) & 1) == 0)
12372 || ((TARGET_SH4
|| TARGET_SHMEDIA
) && mode
== TImode
12373 && ((regno
- FIRST_FP_REG
) & 3) == 0))
12379 if (XD_REGISTER_P (regno
))
12380 return mode
== DFmode
;
12382 if (TARGET_REGISTER_P (regno
))
12383 return (mode
== DImode
|| mode
== SImode
|| mode
== PDImode
);
12385 if (regno
== PR_REG
)
12386 return mode
== SImode
;
12388 if (regno
== FPSCR_REG
)
12389 return mode
== SImode
;
12391 /* FIXME. This works around PR target/37633 for -O0. */
12392 if (!optimize
&& TARGET_SHMEDIA32
&& GET_MODE_SIZE (mode
) > 4)
12394 unsigned int n
= GET_MODE_SIZE (mode
) / 8;
12396 if (regno
>= FIRST_GENERAL_REG
+ 10 - n
+ 1
12397 && regno
<= FIRST_GENERAL_REG
+ 14)
12404 /* Specify the modes required to caller save a given hard regno.
12405 choose_hard_reg_mode chooses mode based on HARD_REGNO_MODE_OK
12406 and returns ?Imode for float regs when sh_hard_regno_mode_ok
12407 permits integer modes on them. That makes LRA's split process
12408 unhappy. See PR55212.
12411 sh_hard_regno_caller_save_mode (unsigned int regno
, unsigned int nregs
,
12414 if (FP_REGISTER_P (regno
)
12417 || ((mode
== DFmode
|| mode
== DCmode
)
12418 && ((regno
- FIRST_FP_REG
) & 1) == 0)))
12421 return choose_hard_reg_mode (regno
, nregs
, false);
12424 /* Return the class of registers for which a mode change from FROM to TO
12427 sh_cannot_change_mode_class (machine_mode from
, machine_mode to
,
12428 enum reg_class rclass
)
12430 /* We want to enable the use of SUBREGs as a means to
12431 VEC_SELECT a single element of a vector. */
12433 /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
12434 This can be problematic when SFmode vector subregs need to be accessed
12435 on the stack with displacement addressing, as it happens with -O0.
12436 Thus we disallow the mode change for -O0. */
12437 if (to
== SFmode
&& VECTOR_MODE_P (from
) && GET_MODE_INNER (from
) == SFmode
)
12438 return optimize
? (reg_classes_intersect_p (GENERAL_REGS
, rclass
)) : false;
12440 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
12442 if (TARGET_LITTLE_ENDIAN
)
12444 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
12445 return reg_classes_intersect_p (DF_REGS
, rclass
);
12449 if (GET_MODE_SIZE (from
) < 8)
12450 return reg_classes_intersect_p (DF_REGS
, rclass
);
12456 /* Return true if registers in machine mode MODE will likely be
12457 allocated to registers in small register classes. */
12459 sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED
)
12461 return (! TARGET_SHMEDIA
);
12464 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
12465 that label is used. */
12467 sh_mark_label (rtx address
, int nuses
)
12469 if (GOTOFF_P (address
))
12471 /* Extract the label or symbol. */
12472 address
= XEXP (address
, 0);
12473 if (GET_CODE (address
) == PLUS
)
12474 address
= XEXP (address
, 0);
12475 address
= XVECEXP (address
, 0, 0);
12477 if (GET_CODE (address
) == LABEL_REF
12478 && LABEL_P (XEXP (address
, 0)))
12479 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
12482 /* Compute extra cost of moving data between one register class
12485 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
12486 uses this information. Hence, the general register <-> floating point
12487 register information here is not used for SFmode. */
12489 sh_register_move_cost (machine_mode mode
,
12490 reg_class_t srcclass
, reg_class_t dstclass
)
12492 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
12495 if (dstclass
== MAC_REGS
&& srcclass
== MAC_REGS
)
12498 if (mode
== SImode
&& ! TARGET_SHMEDIA
&& TARGET_FMOVD
12499 && REGCLASS_HAS_FP_REG (srcclass
)
12500 && REGCLASS_HAS_FP_REG (dstclass
))
12503 if (REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== T_REGS
)
12504 return ((TARGET_HARD_SH4
&& !optimize_size
) ? 10 : 7);
12506 if ((REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== MAC_REGS
)
12507 || (dstclass
== MAC_REGS
&& REGCLASS_HAS_FP_REG (srcclass
)))
12510 if ((REGCLASS_HAS_FP_REG (dstclass
)
12511 && REGCLASS_HAS_GENERAL_REG (srcclass
))
12512 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
12513 && REGCLASS_HAS_FP_REG (srcclass
)))
12515 /* Discourage trying to use fp regs for a pointer. This also
12516 discourages fp regs with SImode because Pmode is an alias
12517 of SImode on this target. See PR target/48596. */
12518 int addend
= (mode
== Pmode
) ? 40 : 0;
12520 return (((TARGET_SHMEDIA
? 4 : TARGET_FMOVD
? 8 : 12) + addend
)
12521 * ((GET_MODE_SIZE (mode
) + 7) / 8U));
12524 if ((dstclass
== FPUL_REGS
12525 && REGCLASS_HAS_GENERAL_REG (srcclass
))
12526 || (srcclass
== FPUL_REGS
12527 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
12530 if ((dstclass
== FPUL_REGS
12531 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
12532 || (srcclass
== FPUL_REGS
12533 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
12536 if ((srcclass
== TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
12537 || ((dstclass
) == TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
12540 /* ??? ptabs faults on (value & 0x3) == 0x3 */
12542 && ((srcclass
) == TARGET_REGS
|| (srcclass
) == SIBCALL_REGS
))
12544 if (sh_gettrcost
>= 0)
12545 return sh_gettrcost
;
12546 else if (!TARGET_PT_FIXED
)
12550 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
12551 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
12556 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
12557 && ! REGCLASS_HAS_GENERAL_REG (dstclass
)))
12558 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
12560 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
12564 emit_load_ptr (rtx reg
, rtx addr
)
12566 rtx mem
= gen_const_mem (ptr_mode
, addr
);
12568 if (Pmode
!= ptr_mode
)
12569 mem
= gen_rtx_SIGN_EXTEND (Pmode
, mem
);
12570 return emit_move_insn (reg
, mem
);
12574 sh_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
12575 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12578 CUMULATIVE_ARGS cum
;
12579 int structure_value_byref
= 0;
12580 rtx this_rtx
, this_value
, sibcall
, funexp
;
12582 tree funtype
= TREE_TYPE (function
);
12583 int simple_add
= CONST_OK_FOR_ADD (delta
);
12585 rtx scratch0
, scratch1
, scratch2
;
12588 reload_completed
= 1;
12589 epilogue_completed
= 1;
12590 crtl
->uses_only_leaf_regs
= 1;
12592 emit_note (NOTE_INSN_PROLOGUE_END
);
12594 /* Find the "this" pointer. We have such a wide range of ABIs for the
12595 SH that it's best to do this completely machine independently.
12596 "this" is passed as first argument, unless a structure return pointer
12597 comes first, in which case "this" comes second. */
12598 INIT_CUMULATIVE_ARGS (cum
, funtype
, NULL_RTX
, 0, 1);
12599 #ifndef PCC_STATIC_STRUCT_RETURN
12600 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12601 structure_value_byref
= 1;
12602 #endif /* not PCC_STATIC_STRUCT_RETURN */
12603 if (structure_value_byref
&& sh_struct_value_rtx (function
, 0) == 0)
12605 tree ptype
= build_pointer_type (TREE_TYPE (funtype
));
12607 sh_function_arg_advance (pack_cumulative_args (&cum
), Pmode
, ptype
, true);
12610 = sh_function_arg (pack_cumulative_args (&cum
), Pmode
, ptr_type_node
, true);
12612 /* For SHcompact, we only have r0 for a scratch register: r1 is the
12613 static chain pointer (even if you can't have nested virtual functions
12614 right now, someone might implement them sometime), and the rest of the
12615 registers are used for argument passing, are callee-saved, or reserved. */
12616 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
12617 -ffixed-reg has been used. */
12618 if (! call_used_regs
[0] || fixed_regs
[0])
12619 error ("r0 needs to be available as a call-clobbered register");
12620 scratch0
= scratch1
= scratch2
= gen_rtx_REG (Pmode
, 0);
12623 if (call_used_regs
[1] && ! fixed_regs
[1])
12624 scratch1
= gen_rtx_REG (ptr_mode
, 1);
12625 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
12626 pointing where to return struct values. */
12627 if (call_used_regs
[3] && ! fixed_regs
[3])
12628 scratch2
= gen_rtx_REG (Pmode
, 3);
12630 else if (TARGET_SHMEDIA
)
12632 for (i
= FIRST_GENERAL_REG
; i
<= LAST_GENERAL_REG
; i
++)
12633 if (i
!= REGNO (scratch0
) &&
12634 call_used_regs
[i
] && ! fixed_regs
[i
] && ! FUNCTION_ARG_REGNO_P (i
))
12636 scratch1
= gen_rtx_REG (ptr_mode
, i
);
12639 if (scratch1
== scratch0
)
12640 error ("need a second call-clobbered general purpose register");
12641 for (i
= FIRST_TARGET_REG
; i
<= LAST_TARGET_REG
; i
++)
12642 if (call_used_regs
[i
] && ! fixed_regs
[i
])
12644 scratch2
= gen_rtx_REG (Pmode
, i
);
12647 if (scratch2
== scratch0
)
12648 error ("need a call-clobbered target register");
12651 this_value
= plus_constant (Pmode
, this_rtx
, delta
);
12653 && (simple_add
|| scratch0
!= scratch1
)
12654 && strict_memory_address_p (ptr_mode
, this_value
))
12656 emit_load_ptr (scratch0
, this_value
);
12661 ; /* Do nothing. */
12662 else if (simple_add
)
12663 emit_move_insn (this_rtx
, this_value
);
12666 emit_move_insn (scratch1
, GEN_INT (delta
));
12667 emit_insn (gen_add2_insn (this_rtx
, scratch1
));
12675 emit_load_ptr (scratch0
, this_rtx
);
12677 offset_addr
= plus_constant (Pmode
, scratch0
, vcall_offset
);
12678 if (strict_memory_address_p (ptr_mode
, offset_addr
))
12679 ; /* Do nothing. */
12680 else if (! TARGET_SH5
&& scratch0
!= scratch1
)
12682 /* scratch0 != scratch1, and we have indexed loads. Get better
12683 schedule by loading the offset into r1 and using an indexed
12684 load - then the load of r1 can issue before the load from
12685 (this_rtx + delta) finishes. */
12686 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
12687 offset_addr
= gen_rtx_PLUS (Pmode
, scratch0
, scratch1
);
12689 else if (CONST_OK_FOR_ADD (vcall_offset
))
12691 emit_insn (gen_add2_insn (scratch0
, GEN_INT (vcall_offset
)));
12692 offset_addr
= scratch0
;
12694 else if (scratch0
!= scratch1
)
12696 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
12697 emit_insn (gen_add2_insn (scratch0
, scratch1
));
12698 offset_addr
= scratch0
;
12701 gcc_unreachable (); /* FIXME */
12702 emit_load_ptr (scratch0
, offset_addr
);
12704 if (Pmode
!= ptr_mode
)
12705 scratch0
= gen_rtx_TRUNCATE (ptr_mode
, scratch0
);
12706 emit_insn (gen_add2_insn (this_rtx
, scratch0
));
12709 /* Generate a tail call to the target function. */
12710 if (! TREE_USED (function
))
12712 assemble_external (function
);
12713 TREE_USED (function
) = 1;
12715 funexp
= XEXP (DECL_RTL (function
), 0);
12716 /* If the function is overridden, so is the thunk, hence we don't
12717 need GOT addressing even if this is a public symbol. */
12719 if (TARGET_SH1
&& ! flag_weak
)
12720 sibcall
= gen_sibcalli_thunk (funexp
, const0_rtx
);
12723 if (TARGET_SH2
&& flag_pic
)
12725 sibcall
= gen_sibcall_pcrel (funexp
, const0_rtx
);
12726 XEXP (XVECEXP (sibcall
, 0, 2), 0) = scratch2
;
12730 if (TARGET_SHMEDIA
&& flag_pic
)
12732 funexp
= gen_sym2PIC (funexp
);
12733 PUT_MODE (funexp
, Pmode
);
12735 emit_move_insn (scratch2
, funexp
);
12736 funexp
= gen_rtx_MEM (FUNCTION_MODE
, scratch2
);
12737 sibcall
= gen_sibcall (funexp
, const0_rtx
, NULL_RTX
);
12739 sibcall
= emit_call_insn (sibcall
);
12740 SIBLING_CALL_P (sibcall
) = 1;
12741 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall
), this_rtx
);
12744 /* Run just enough of rest_of_compilation to do scheduling and get
12745 the insns emitted. Note that use_thunk calls
12746 assemble_start_function and assemble_end_function. */
12748 insns
= get_insns ();
12754 split_all_insns_noflow ();
12758 shorten_branches (insns
);
12759 final_start_function (insns
, file
, 1);
12760 final (insns
, file
, 1);
12761 final_end_function ();
12763 reload_completed
= 0;
12764 epilogue_completed
= 0;
12768 function_symbol (rtx target
, const char *name
, enum sh_function_kind kind
)
12772 /* If this is not an ordinary function, the name usually comes from a
12773 string literal or an sprintf buffer. Make sure we use the same
12774 string consistently, so that cse will be able to unify address loads. */
12775 if (kind
!= FUNCTION_ORDINARY
)
12776 name
= IDENTIFIER_POINTER (get_identifier (name
));
12777 sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
12778 SYMBOL_REF_FLAGS (sym
) = SYMBOL_FLAG_FUNCTION
;
12782 case FUNCTION_ORDINARY
:
12786 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
12788 emit_insn (gen_symGOT2reg (reg
, sym
));
12794 /* ??? To allow cse to work, we use GOTOFF relocations.
12795 We could add combiner patterns to transform this into
12796 straight pc-relative calls with sym2PIC / bsrf when
12797 label load and function call are still 1:1 and in the
12798 same basic block during combine. */
12799 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
12801 emit_insn (gen_symGOTOFF2reg (reg
, sym
));
12806 if (target
&& sym
!= target
)
12808 emit_move_insn (target
, sym
);
12814 /* Find the number of a general purpose register in S. */
12816 scavenge_reg (HARD_REG_SET
*s
)
12819 for (r
= FIRST_GENERAL_REG
; r
<= LAST_GENERAL_REG
; r
++)
12820 if (TEST_HARD_REG_BIT (*s
, r
))
12826 sh_get_pr_initial_val (void)
12830 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
12831 PR register on SHcompact, because it might be clobbered by the prologue.
12832 We check first if that is known to be the case. */
12833 if (TARGET_SHCOMPACT
12834 && ((crtl
->args
.info
.call_cookie
12835 & ~ CALL_COOKIE_RET_TRAMP (1))
12836 || crtl
->saves_all_registers
))
12837 return gen_frame_mem (SImode
, return_address_pointer_rtx
);
12839 /* If we haven't finished rtl generation, there might be a nonlocal label
12840 that we haven't seen yet.
12841 ??? get_hard_reg_initial_val fails if it is called after register
12842 allocation has started, unless it has been called before for the
12843 same register. And even then, we end in trouble if we didn't use
12844 the register in the same basic block before. So call
12845 get_hard_reg_initial_val now and wrap it in an unspec if we might
12846 need to replace it. */
12847 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
12848 combine can put the pseudo returned by get_hard_reg_initial_val into
12849 instructions that need a general purpose registers, which will fail to
12850 be recognized when the pseudo becomes allocated to PR. */
12852 = get_hard_reg_initial_val (Pmode
, TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
12854 return gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_RA
);
12859 sh_expand_t_scc (rtx operands
[])
12861 enum rtx_code code
= GET_CODE (operands
[1]);
12862 rtx target
= operands
[0];
12863 rtx op0
= operands
[2];
12864 rtx op1
= operands
[3];
12865 rtx result
= target
;
12868 if (!REG_P (op0
) || REGNO (op0
) != T_REG
12869 || !CONST_INT_P (op1
))
12871 if (!REG_P (result
))
12872 result
= gen_reg_rtx (SImode
);
12873 val
= INTVAL (op1
);
12874 if ((code
== EQ
&& val
== 1) || (code
== NE
&& val
== 0))
12875 emit_insn (gen_movt (result
, get_t_reg_rtx ()));
12876 else if ((code
== EQ
&& val
== 0) || (code
== NE
&& val
== 1))
12877 emit_insn (gen_movnegt (result
, get_t_reg_rtx ()));
12878 else if (code
== EQ
|| code
== NE
)
12879 emit_insn (gen_move_insn (result
, GEN_INT (code
== NE
)));
12882 if (result
!= target
)
12883 emit_move_insn (target
, result
);
12887 /* INSN is an sfunc; return the rtx that describes the address used. */
12889 extract_sfunc_addr (rtx insn
)
12891 rtx pattern
, part
= NULL_RTX
;
12894 pattern
= PATTERN (insn
);
12895 len
= XVECLEN (pattern
, 0);
12896 for (i
= 0; i
< len
; i
++)
12898 part
= XVECEXP (pattern
, 0, i
);
12899 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == Pmode
12900 && GENERAL_REGISTER_P (true_regnum (XEXP (part
, 0))))
12901 return XEXP (part
, 0);
12903 gcc_assert (GET_CODE (XVECEXP (pattern
, 0, 0)) == UNSPEC_VOLATILE
);
12904 return XVECEXP (XVECEXP (pattern
, 0, 0), 0, 1);
12907 /* Verify that the register in use_sfunc_addr still agrees with the address
12908 used in the sfunc. This prevents fill_slots_from_thread from changing
12910 INSN is the use_sfunc_addr instruction, and REG is the register it
12913 check_use_sfunc_addr (rtx_insn
*insn
, rtx reg
)
12915 /* Search for the sfunc. It should really come right after INSN. */
12916 while ((insn
= NEXT_INSN (insn
)))
12918 if (LABEL_P (insn
) || JUMP_P (insn
))
12920 if (! INSN_P (insn
))
12923 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
12924 insn
= seq
->insn (0);
12925 if (GET_CODE (PATTERN (insn
)) != PARALLEL
12926 || get_attr_type (insn
) != TYPE_SFUNC
)
12928 return rtx_equal_p (extract_sfunc_addr (insn
), reg
);
12930 gcc_unreachable ();
12933 /* This function returns a constant rtx that represents 2**15 / pi in
12934 SFmode. It's used to scale a fixed-point signed 16.16-bit fraction
12935 of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */
12936 static GTY(()) rtx sh_fsca_sf2int_rtx
;
12939 sh_fsca_sf2int (void)
12941 if (! sh_fsca_sf2int_rtx
)
12943 REAL_VALUE_TYPE rv
;
12945 real_from_string (&rv
, "10430.378350470453");
12946 sh_fsca_sf2int_rtx
= const_double_from_real_value (rv
, SFmode
);
12949 return sh_fsca_sf2int_rtx
;
12952 /* This function returns a constant rtx that represents pi / 2**15 in
12953 SFmode. It's used to scale SFmode angles, in radians, to a
12954 fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi
12955 maps to 0x10000. */
12956 static GTY(()) rtx sh_fsca_int2sf_rtx
;
12959 sh_fsca_int2sf (void)
12961 if (! sh_fsca_int2sf_rtx
)
12963 REAL_VALUE_TYPE rv
;
12965 real_from_string (&rv
, "9.587379924285257e-5");
12966 sh_fsca_int2sf_rtx
= const_double_from_real_value (rv
, SFmode
);
12969 return sh_fsca_int2sf_rtx
;
12972 /* Initialize the CUMULATIVE_ARGS structure. */
12974 sh_init_cumulative_args (CUMULATIVE_ARGS
* pcum
,
12976 rtx libname ATTRIBUTE_UNUSED
,
12978 signed int n_named_args
,
12981 pcum
->arg_count
[(int) SH_ARG_FLOAT
] = 0;
12982 pcum
->free_single_fp_reg
= 0;
12983 pcum
->stack_regs
= 0;
12984 pcum
->byref_regs
= 0;
12986 pcum
->outgoing
= (n_named_args
== -1) ? 0 : 1;
12988 /* XXX - Should we check TARGET_HITACHI here ??? */
12989 pcum
->renesas_abi
= sh_attr_renesas_p (fntype
) ? 1 : 0;
12993 pcum
->force_mem
= ((TARGET_HITACHI
|| pcum
->renesas_abi
)
12994 && aggregate_value_p (TREE_TYPE (fntype
), fndecl
));
12995 pcum
->prototype_p
= prototype_p (fntype
);
12996 pcum
->arg_count
[(int) SH_ARG_INT
]
12997 = TARGET_SH5
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
);
13000 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
13001 && pcum
->arg_count
[(int) SH_ARG_INT
] == 0
13002 && (TYPE_MODE (TREE_TYPE (fntype
)) == BLKmode
13003 ? int_size_in_bytes (TREE_TYPE (fntype
))
13004 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype
)))) > 4
13005 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype
)))
13006 == FIRST_RET_REG
));
13010 pcum
->arg_count
[(int) SH_ARG_INT
] = 0;
13011 pcum
->prototype_p
= FALSE
;
13012 if (mode
!= VOIDmode
)
13014 pcum
->call_cookie
=
13015 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
13016 && GET_MODE_SIZE (mode
) > 4
13017 && BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
);
13019 /* If the default ABI is the Renesas ABI then all library
13020 calls must assume that the library will be using the
13021 Renesas ABI. So if the function would return its result
13022 in memory then we must force the address of this memory
13023 block onto the stack. Ideally we would like to call
13024 targetm.calls.return_in_memory() here but we do not have
13025 the TYPE or the FNDECL available so we synthesize the
13026 contents of that function as best we can. */
13028 (TARGET_DEFAULT
& MASK_HITACHI
)
13029 && (mode
== BLKmode
13030 || (GET_MODE_SIZE (mode
) > 4
13031 && !(mode
== DFmode
13032 && TARGET_FPU_DOUBLE
)));
13036 pcum
->call_cookie
= 0;
13037 pcum
->force_mem
= FALSE
;
13043 sh_gen_truncate (machine_mode mode
, rtx x
, int need_sign_ext
)
13045 enum rtx_code code
= TRUNCATE
;
13047 if (GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
13049 rtx inner
= XEXP (x
, 0);
13050 machine_mode inner_mode
= GET_MODE (inner
);
13052 if (inner_mode
== mode
)
13054 else if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
13056 else if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
)
13057 && (! need_sign_ext
|| GET_CODE (x
) == SIGN_EXTEND
))
13059 code
= GET_CODE (x
);
13063 return gen_rtx_fmt_e (code
, mode
, x
);
13066 /* Look through X cleaning up truncates of registers that span multiple
13067 actual hard registers. Return the number of changes made. */
13069 shmedia_cleanup_truncate (rtx x
)
13072 subrtx_var_iterator::array_type array
;
13073 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
13076 if (GET_CODE (x
) == TRUNCATE
)
13078 rtx reg
= XEXP (x
, 0);
13079 machine_mode reg_mode
= GET_MODE (reg
);
13080 if (REG_P (reg
) && GET_MODE_SIZE (reg_mode
) > 8)
13082 int offset
= subreg_lowpart_offset (DImode
, reg_mode
);
13083 XEXP (x
, 0) = simplify_subreg (DImode
, reg
, reg_mode
, offset
);
13085 iter
.skip_subrtxes ();
13092 /* Load and store depend on the highpart of the address. However,
13093 set_attr_alternative does not give well-defined results before reload,
13094 so we must look at the rtl ourselves to see if any of the feeding
13095 registers is used in a memref.
13097 Return true iff INSN contains a MEM. */
13099 sh_contains_memref_p (rtx insn
)
13101 subrtx_iterator::array_type array
;
13102 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
13108 /* Return true iff INSN loads a banked register. */
13110 sh_loads_bankedreg_p (rtx insn
)
13112 if (GET_CODE (PATTERN (insn
)) == SET
)
13114 rtx op
= SET_DEST (PATTERN(insn
));
13115 if (REG_P (op
) && BANKED_REGISTER_P (REGNO (op
)))
13122 /* FNADDR is the MEM expression from a call expander. Return an address
13123 to use in an SHmedia insn pattern. */
13125 shmedia_prepare_call_address (rtx fnaddr
, int is_sibcall
)
13129 fnaddr
= XEXP (fnaddr
, 0);
13130 is_sym
= GET_CODE (fnaddr
) == SYMBOL_REF
;
13131 if (flag_pic
&& is_sym
)
13133 if (! SYMBOL_REF_LOCAL_P (fnaddr
))
13135 rtx reg
= gen_reg_rtx (Pmode
);
13137 /* We must not use GOTPLT for sibcalls, because PIC_REG
13138 must be restored before the PLT code gets to run. */
13140 emit_insn (gen_symGOT2reg (reg
, fnaddr
));
13142 emit_insn (gen_symGOTPLT2reg (reg
, fnaddr
));
13147 fnaddr
= gen_sym2PIC (fnaddr
);
13148 PUT_MODE (fnaddr
, Pmode
);
13151 /* If ptabs might trap, make this visible to the rest of the compiler.
13152 We generally assume that symbols pertain to valid locations, but
13153 it is possible to generate invalid symbols with asm or linker tricks.
13154 In a list of functions where each returns its successor, an invalid
13155 symbol might denote an empty list. */
13156 if (!TARGET_PT_FIXED
13157 && (!is_sym
|| TARGET_INVALID_SYMBOLS
)
13158 && (!REG_P (fnaddr
) || ! TARGET_REGISTER_P (REGNO (fnaddr
))))
13160 rtx tr
= gen_reg_rtx (PDImode
);
13162 emit_insn (gen_ptabs (tr
, fnaddr
));
13165 else if (! target_reg_operand (fnaddr
, Pmode
))
13166 fnaddr
= copy_to_mode_reg (Pmode
, fnaddr
);
13170 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
13172 sh_preferred_reload_class (rtx x
, reg_class_t rclass
)
13174 if (rclass
== NO_REGS
13176 && (CONST_DOUBLE_P (x
)
13177 || GET_CODE (x
) == SYMBOL_REF
13178 || PIC_ADDR_P (x
)))
13179 return GENERAL_REGS
;
13184 /* Implement TARGET_SECONDARY_RELOAD. */
13186 sh_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13187 machine_mode mode
, secondary_reload_info
*sri
)
13189 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13191 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
13192 && REG_P (XEXP (XEXP (x
, 0), 0))
13193 && REGNO (XEXP (XEXP (x
, 0), 0)) == GBR_REG
)
13194 return rclass
== R0_REGS
? NO_REGS
: R0_REGS
;
13196 if (MEM_P (x
) && REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == GBR_REG
)
13197 return rclass
== R0_REGS
? NO_REGS
: R0_REGS
;
13199 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
13204 if (REGCLASS_HAS_FP_REG (rclass
)
13205 && ! TARGET_SHMEDIA
13206 && immediate_operand ((x
), mode
)
13207 && ! ((fp_zero_operand (x
) || fp_one_operand (x
)) && mode
== SFmode
))
13211 sri
->icode
= CODE_FOR_reload_insf__frn
;
13214 sri
->icode
= CODE_FOR_reload_indf__frn
;
13217 /* ??? If we knew that we are in the appropriate mode -
13218 single precision - we could use a reload pattern directly. */
13223 if (rclass
== FPUL_REGS
13224 && ((REG_P (x
) && (REGNO (x
) == MACL_REG
|| REGNO (x
) == MACH_REG
13225 || REGNO (x
) == T_REG
))
13226 || GET_CODE (x
) == PLUS
))
13227 return GENERAL_REGS
;
13228 if (rclass
== FPUL_REGS
&& immediate_operand (x
, mode
))
13230 if (satisfies_constraint_I08 (x
) || fp_zero_operand (x
))
13231 return GENERAL_REGS
;
13232 else if (mode
== SFmode
)
13234 sri
->icode
= CODE_FOR_reload_insi__i_fpul
;
13237 if (rclass
== FPSCR_REGS
13238 && ((REG_P (x
) && REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
13239 || (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
)))
13240 return GENERAL_REGS
;
13241 if (REGCLASS_HAS_FP_REG (rclass
)
13243 && immediate_operand (x
, mode
)
13244 && x
!= CONST0_RTX (GET_MODE (x
))
13245 && GET_MODE (x
) != V4SFmode
)
13246 return GENERAL_REGS
;
13247 if ((mode
== QImode
|| mode
== HImode
)
13248 && TARGET_SHMEDIA
&& inqhi_operand (x
, mode
))
13250 sri
->icode
= ((mode
== QImode
)
13251 ? CODE_FOR_reload_inqi
: CODE_FOR_reload_inhi
);
13254 if (TARGET_SHMEDIA
&& rclass
== GENERAL_REGS
13255 && (GET_CODE (x
) == LABEL_REF
|| PIC_ADDR_P (x
)))
13256 return TARGET_REGS
;
13257 } /* end of input-only processing. */
13259 if (((REGCLASS_HAS_FP_REG (rclass
)
13261 && (GENERAL_OR_AP_REGISTER_P (REGNO (x
))
13262 || (FP_REGISTER_P (REGNO (x
)) && mode
== SImode
13263 && TARGET_FMOVD
))))
13264 || (REGCLASS_HAS_GENERAL_REG (rclass
)
13266 && FP_REGISTER_P (REGNO (x
))))
13267 && ! TARGET_SHMEDIA
13268 && (mode
== SFmode
|| mode
== SImode
))
13270 if ((rclass
== FPUL_REGS
13271 || (REGCLASS_HAS_FP_REG (rclass
)
13272 && ! TARGET_SHMEDIA
&& mode
== SImode
))
13275 && (REGNO (x
) >= FIRST_PSEUDO_REGISTER
13276 || REGNO (x
) == T_REG
13277 || system_reg_operand (x
, VOIDmode
)))))
13279 if (rclass
== FPUL_REGS
)
13280 return GENERAL_REGS
;
13281 return NO_REGS
; // LRA wants NO_REGS here, it used to be FPUL_REGS;
13283 if ((rclass
== TARGET_REGS
13284 || (TARGET_SHMEDIA
&& rclass
== SIBCALL_REGS
))
13285 && !satisfies_constraint_Csy (x
)
13286 && (!REG_P (x
) || ! GENERAL_REGISTER_P (REGNO (x
))))
13287 return GENERAL_REGS
;
13288 if ((rclass
== MAC_REGS
|| rclass
== PR_REGS
)
13289 && REG_P (x
) && ! GENERAL_REGISTER_P (REGNO (x
))
13290 && rclass
!= REGNO_REG_CLASS (REGNO (x
)))
13291 return GENERAL_REGS
;
13292 if (rclass
!= GENERAL_REGS
&& REG_P (x
)
13293 && TARGET_REGISTER_P (REGNO (x
)))
13294 return GENERAL_REGS
;
13296 /* If here fall back to loading FPUL register through general registers.
13297 This case can happen when movsi_ie insn is picked initially to
13298 load/store the FPUL register from/to another register, and then the
13299 other register is allocated on the stack. */
13300 if (rclass
== FPUL_REGS
&& true_regnum (x
) == -1)
13301 return GENERAL_REGS
;
13303 /* Force mov.b / mov.w displacement addressing insn to use R0 as
13305 On SH2A could also just leave it alone here, which would result in a
13306 4 byte move insn being generated instead. However, for this to work
13307 the insns must have the appropriate alternatives. */
13308 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
13309 && satisfies_constraint_Sdd (x
)
13310 && sh_disp_addr_displacement (x
)
13311 <= sh_max_mov_insn_displacement (mode
, false))
13314 /* When reload is trying to address a QImode or HImode subreg on the stack,
13315 force any subreg byte into R0_REGS, as this is going to become a
13316 displacement address.
13317 We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg
13318 is on the stack, the memref to it might already require a displacement
13319 and that has to be added to the final address. At this point we don't
13320 know the cumulative displacement so we assume the worst case. */
13321 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
13322 && GET_CODE (x
) == SUBREG
&& true_regnum (x
) == -1)
13328 /* Return true if SUBST can't safely replace its equivalent during RA. */
13330 sh_cannot_substitute_mem_equiv_p (rtx
)
13332 if (TARGET_SHMEDIA
)
13335 /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn
13336 uses R0 and may cause spill failure when R0 is already used.
13337 We have to return true for that case at least.
13338 Moreover SH has strong R0 parity and also have not enough numbers of
13339 the hard registers to make the equiv substitution win in the size
13340 and the speed on average working sets. The pseudos produced to
13341 hold the equiv values can't get good hard registers for bad cases
13342 and end up memory save/restore insns which make the code worse. */
13346 /* Return true if DISP can be legitimized. */
13348 sh_legitimize_address_displacement (rtx
*disp
, rtx
*offs
,
13351 if (TARGET_SHMEDIA
)
13354 if (((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
13355 || (TARGET_SH2E
&& mode
== SFmode
))
13358 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
, INTVAL (*disp
));
13359 if (adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
13361 *disp
= adj
.mov_disp
;
13362 *offs
= adj
.offset_adjust
;
13369 /* Return true if movsf insn should be splited with an additional
13372 sh_movsf_ie_ra_split_p (rtx op0
, rtx op1
, rtx op2
)
13375 if (rtx_equal_p (op0
, op1
))
13378 if (GET_CODE (op1
) == CONST_DOUBLE
13379 && ! satisfies_constraint_G (op1
)
13380 && ! satisfies_constraint_H (op1
)
13385 if (REG_P (op0
) && FP_REGISTER_P (REGNO (op0
))
13386 && REG_P (op1
) && GENERAL_REGISTER_P (REGNO (op1
))
13387 && REG_P (op2
) && (REGNO (op2
) == FPUL_REG
))
13390 if (REG_P (op1
) && FP_REGISTER_P (REGNO (op1
))
13391 && REG_P (op0
) && GENERAL_REGISTER_P (REGNO (op0
))
13392 && REG_P (op2
) && (REGNO (op2
) == FPUL_REG
))
13399 sh_conditional_register_usage (void)
13402 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
13403 if (! VALID_REGISTER_P (regno
))
13404 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
13405 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
13408 call_used_regs
[FIRST_GENERAL_REG
+ 8]
13409 = call_used_regs
[FIRST_GENERAL_REG
+ 9] = 1;
13410 call_really_used_regs
[FIRST_GENERAL_REG
+ 8]
13411 = call_really_used_regs
[FIRST_GENERAL_REG
+ 9] = 1;
13413 if (TARGET_SHMEDIA
)
13415 regno_reg_class
[FIRST_GENERAL_REG
] = GENERAL_REGS
;
13416 CLEAR_HARD_REG_SET (reg_class_contents
[FP0_REGS
]);
13417 regno_reg_class
[FIRST_FP_REG
] = FP_REGS
;
13421 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13422 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13424 /* Renesas saves and restores mac registers on call. */
13425 if (TARGET_HITACHI
&& ! TARGET_NOMACSAVE
)
13427 call_really_used_regs
[MACH_REG
] = 0;
13428 call_really_used_regs
[MACL_REG
] = 0;
13431 if (TARGET_SHMEDIA
)
13433 for (regno
= FIRST_TARGET_REG
; regno
<= LAST_TARGET_REG
; regno
++)
13434 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
13435 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
13438 for (regno
= FIRST_GENERAL_REG
; regno
<= LAST_GENERAL_REG
; regno
++)
13439 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
13440 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
13442 call_really_used_regs
[FPSCR_MODES_REG
] = 0;
13443 call_really_used_regs
[FPSCR_STAT_REG
] = 0;
13446 /* Implement TARGET_LEGITIMATE_CONSTANT_P
13448 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
13450 sh_legitimate_constant_p (machine_mode mode
, rtx x
)
13452 return (TARGET_SHMEDIA
13453 ? ((mode
!= DFmode
&& GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
13454 || x
== CONST0_RTX (mode
)
13455 || !TARGET_SHMEDIA_FPU
13456 || TARGET_SHMEDIA64
)
13457 : (GET_CODE (x
) != CONST_DOUBLE
13458 || mode
== DFmode
|| mode
== SFmode
13459 || mode
== DImode
|| GET_MODE (x
) == VOIDmode
));
13462 enum sh_divide_strategy_e sh_div_strategy
= SH_DIV_STRATEGY_DEFAULT
;
13465 sh_init_sync_libfuncs (void)
13467 init_sync_libfuncs (UNITS_PER_WORD
);
13470 /* Return true if it is appropriate to emit `ret' instructions in the
13471 body of a function. */
13473 sh_can_use_simple_return_p (void)
13475 HARD_REG_SET live_regs_mask
;
13478 /* Some targets require special return insns. */
13480 || (TARGET_SHCOMPACT
13481 && (crtl
->args
.info
.call_cookie
& CALL_COOKIE_RET_TRAMP (1))))
13484 if (! reload_completed
|| frame_pointer_needed
)
13487 /* Moving prologue around does't reduce the size. */
13488 if (optimize_function_for_size_p (cfun
))
13491 /* Finally, allow for pr save. */
13492 d
= calc_live_regs (&live_regs_mask
);
13494 if (rounded_frame_size (d
) > 4)
13500 /*------------------------------------------------------------------------------
13501 Address mode optimization support code
13504 typedef HOST_WIDE_INT disp_t
;
13505 static const disp_t MIN_DISP
= HOST_WIDE_INT_MIN
;
13506 static const disp_t MAX_DISP
= HOST_WIDE_INT_MAX
;
13507 static const disp_t INVALID_DISP
= MAX_DISP
;
13509 /* A memory reference which is described by a base register and a
13511 class base_reg_disp
13514 base_reg_disp (rtx br
, disp_t d
);
13516 bool is_reg (void) const;
13517 bool is_disp (void) const;
13518 rtx
reg (void) const;
13519 disp_t
disp (void) const;
13527 base_reg_disp::base_reg_disp (rtx br
, disp_t d
)
13528 : reg_ (br
), disp_ (d
)
13533 base_reg_disp::is_reg (void) const
13535 return reg_
!= NULL_RTX
&& disp_
!= INVALID_DISP
;
13539 base_reg_disp::is_disp (void) const
13541 return reg_
== NULL_RTX
&& disp_
!= INVALID_DISP
;
13545 base_reg_disp::reg (void) const
13551 base_reg_disp::disp (void) const
13556 /* Find the base register and calculate the displacement for a given
13557 address rtx 'x'. */
13558 static base_reg_disp
13559 sh_find_base_reg_disp (rtx_insn
* insn
, rtx x
, disp_t disp
= 0,
13560 rtx base_reg
= NULL
)
13564 if (REGNO (x
) == GBR_REG
)
13565 return base_reg_disp (x
, disp
);
13567 /* We've reached a hard-reg. This is probably the point where
13568 function args are copied to pseudos. Do not go any further and
13569 stick to the pseudo. If the original mem addr was in a hard reg
13570 from the beginning, it will become the base reg. */
13571 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13572 return base_reg_disp (base_reg
!= NULL
? base_reg
: x
, disp
);
13574 /* Find the def of the reg and trace it. If there are more than one
13575 defs and they are not the same, assume it's not safe to proceed. */
13576 rtx_insn
* last_i
= NULL
;
13577 rtx last_set
= NULL
;
13578 for (df_ref d
= DF_REG_DEF_CHAIN (REGNO (x
)); d
!= NULL
;
13579 d
= DF_REF_NEXT_REG (d
))
13581 rtx set
= const_cast<rtx
> (set_of (x
, DF_REF_INSN (d
)));
13583 /* Accept multiple defs, as long as they are equal. */
13584 if (last_set
== NULL
|| rtx_equal_p (last_set
, set
))
13586 last_i
= DF_REF_INSN (d
);
13597 if (last_set
!= NULL
&& last_i
!= NULL
)
13598 return sh_find_base_reg_disp (last_i
, XEXP (last_set
, 1), disp
,
13599 XEXP (last_set
, 0));
13601 /* When here, no previous insn was found that sets the reg.
13602 The input reg is already the base reg. */
13603 return base_reg_disp (x
, disp
);
13606 else if (GET_CODE (x
) == PLUS
)
13608 base_reg_disp left_val
= sh_find_base_reg_disp (insn
, XEXP (x
, 0));
13609 base_reg_disp right_val
= sh_find_base_reg_disp (insn
, XEXP (x
, 1));
13611 /* Either left or right val must be a reg.
13612 We don't handle the case of 'reg + reg' here. */
13613 if (left_val
.is_reg () && right_val
.is_disp ())
13614 return base_reg_disp (left_val
.reg (), left_val
.disp ()
13615 + right_val
.disp () + disp
);
13616 else if (right_val
.is_reg () && left_val
.is_disp ())
13617 return base_reg_disp (right_val
.reg (), right_val
.disp ()
13618 + left_val
.disp () + disp
);
13620 return base_reg_disp (base_reg
, disp
);
13623 else if (CONST_INT_P (x
))
13624 return base_reg_disp (NULL
, disp
+ INTVAL (x
));
13626 /* Didn't find anything useful. */
13627 return base_reg_disp (base_reg
, disp
);
13630 /* Given an insn and a memory operand, try to find an equivalent GBR
13631 based memory address and return the corresponding new memory address.
13632 Return NULL_RTX if not found. */
13634 sh_find_equiv_gbr_addr (rtx_insn
* insn
, rtx mem
)
13636 if (!MEM_P (mem
) || gbr_address_mem (mem
, GET_MODE (mem
)))
13639 /* Leave post/pre inc/dec or any other side effect addresses alone. */
13640 if (side_effects_p (XEXP (mem
, 0)))
13643 /* When not optimizing there might be no dataflow available. */
13647 base_reg_disp gbr_disp
= sh_find_base_reg_disp (insn
, XEXP (mem
, 0));
13649 if (gbr_disp
.is_reg () && REGNO (gbr_disp
.reg ()) == GBR_REG
)
13651 /* If GBR is marked as call clobbered we bail out if we see a call.
13652 FIXME: Actually should check if this mem refers to the gbr value
13653 before or after the call. If there is a store_gbr preceeding this
13654 mem, it's safe to use GBR for this mem.
13656 If GBR is not marked as call clobbered, but there is some other
13657 def than a call, it's probably a load_gbr upon which we also
13658 bail out to be on the safe side.
13659 FIXME: Should check if we have a use-after-def case, such as
13660 the call case above. */
13661 for (df_ref d
= DF_REG_DEF_CHAIN (GBR_REG
); d
!= NULL
;
13662 d
= DF_REF_NEXT_REG (d
))
13664 if (CALL_P (DF_REF_INSN (d
)))
13666 if (REGNO_REG_SET_P (regs_invalidated_by_call_regset
, GBR_REG
))
13675 rtx disp
= GEN_INT (gbr_disp
.disp ());
13676 if (gbr_displacement (disp
, GET_MODE (mem
)))
13677 return gen_rtx_PLUS (SImode
, gen_rtx_REG (SImode
, GBR_REG
), disp
);
13683 /*------------------------------------------------------------------------------
13684 Manual insn combine support code.
13687 /* Return true if the specified insn contains any UNSPECs or
13688 UNSPEC_VOLATILEs. */
13690 sh_unspec_insn_p (rtx x
)
13692 subrtx_iterator::array_type array
;
13693 FOR_EACH_SUBRTX (i
, array
, x
, ALL
)
13695 && (GET_CODE (*i
) == UNSPEC
|| GET_CODE (*i
) == UNSPEC_VOLATILE
))
13701 /* Return true if the register operands of the specified insn are modified
13702 between the specified from and to insns (exclusive of those two). */
13704 sh_insn_operands_modified_between_p (rtx_insn
* operands_insn
,
13705 const rtx_insn
* from
,
13706 const rtx_insn
* to
)
13708 /* FIXME: Return true for multiple sets for now. */
13709 rtx s
= single_set (operands_insn
);
13713 subrtx_iterator::array_type array
;
13714 FOR_EACH_SUBRTX (i
, array
, SET_SRC (s
), ALL
)
13716 ((REG_P (*i
) || SUBREG_P (*i
)) && reg_set_between_p (*i
, from
, to
)))
13722 /* Given an insn, determine whether it's a 'nott' insn, i.e. an insn that
13723 negates the T bit and stores the result in the T bit. */
13725 sh_is_nott_insn (const rtx_insn
* i
)
13727 return i
!= NULL
&& GET_CODE (PATTERN (i
)) == SET
13728 && t_reg_operand (XEXP (PATTERN (i
), 0), VOIDmode
)
13729 && negt_reg_operand (XEXP (PATTERN (i
), 1), VOIDmode
);
13733 sh_movt_set_dest (const rtx_insn
* i
)
13738 const_rtx p
= PATTERN (i
);
13739 return GET_CODE (p
) == SET
13740 && arith_reg_dest (XEXP (p
, 0), SImode
)
13741 && t_reg_operand (XEXP (p
, 1), VOIDmode
) ? XEXP (p
, 0) : NULL
;
13744 /* Given an insn, check whether it's a 'movrt' kind of insn, i.e. an insn
13745 that stores the negated T bit in a register, and return the destination
13746 register rtx, or null. */
13748 sh_movrt_set_dest (const rtx_insn
* i
)
13753 const_rtx p
= PATTERN (i
);
13755 /* The negc movrt replacement is inside a parallel. */
13756 if (GET_CODE (p
) == PARALLEL
)
13757 p
= XVECEXP (p
, 0, 0);
13759 return GET_CODE (p
) == SET
13760 && arith_reg_dest (XEXP (p
, 0), SImode
)
13761 && negt_reg_operand (XEXP (p
, 1), VOIDmode
) ? XEXP (p
, 0) : NULL
;
13764 /* Given an insn and a reg number, tell whether the reg dies or is unused
13767 sh_reg_dead_or_unused_after_insn (const rtx_insn
* i
, int regno
)
13769 return find_regno_note (i
, REG_DEAD
, regno
) != NULL
13770 || find_regno_note (i
, REG_UNUSED
, regno
) != NULL
;
13773 /* Given an insn and a reg number, remove reg dead or reg unused notes to
13774 mark it as being used after the insn. */
13776 sh_remove_reg_dead_or_unused_notes (rtx_insn
* i
, int regno
)
13778 if (rtx n
= find_regno_note (i
, REG_DEAD
, regno
))
13779 remove_note (i
, n
);
13780 if (rtx n
= find_regno_note (i
, REG_UNUSED
, regno
))
13781 remove_note (i
, n
);
13784 /* Given an insn check if it contains any post/pre inc/dec mem operands and
13785 add the REG_INC notes accordingly.
13786 FIXME: This function is very similar to lra.c (add_auto_inc_notes).
13787 FIXME: This function is currently used by peephole2 patterns because
13788 the peephole2 pass does not preserve REG_INC notes. If the notes
13789 are dropped the following passes will do wrong things. */
13791 sh_check_add_incdec_notes (rtx_insn
* i
)
13793 struct for_each_inc_dec_clb
13795 static int func (rtx mem ATTRIBUTE_UNUSED
, rtx op ATTRIBUTE_UNUSED
,
13796 rtx dest
, rtx src ATTRIBUTE_UNUSED
,
13797 rtx srcoff ATTRIBUTE_UNUSED
, void* arg
)
13799 gcc_assert (REG_P (dest
));
13801 rtx_insn
* i
= (rtx_insn
*)arg
;
13802 if (find_regno_note (i
, REG_INC
, REGNO (dest
)) == NULL
)
13803 add_reg_note (i
, REG_INC
, dest
);
13809 for_each_inc_dec (PATTERN (i
), for_each_inc_dec_clb::func
, i
);
13813 /* Given an op rtx and an insn, try to find out whether the result of the
13814 specified op consists only of logical operations on T bit stores. */
13816 sh_is_logical_t_store_expr (rtx op
, rtx_insn
* insn
)
13818 if (!logical_operator (op
, SImode
))
13821 rtx ops
[2] = { XEXP (op
, 0), XEXP (op
, 1) };
13822 int op_is_t_count
= 0;
13824 for (int i
= 0; i
< 2; ++i
)
13826 if (t_reg_operand (ops
[i
], VOIDmode
)
13827 || negt_reg_operand (ops
[i
], VOIDmode
))
13832 set_of_reg op_set
= sh_find_set_of_reg (ops
[i
], insn
,
13833 prev_nonnote_insn_bb
);
13834 if (op_set
.set_src
== NULL_RTX
)
13837 if (t_reg_operand (op_set
.set_src
, VOIDmode
)
13838 || negt_reg_operand (op_set
.set_src
, VOIDmode
)
13839 || sh_is_logical_t_store_expr (op_set
.set_src
, op_set
.insn
))
13844 return op_is_t_count
== 2;
13847 /* Given the operand that is extended in a sign/zero extend insn, and the
13848 insn, try to figure out whether the sign/zero extension can be replaced
13849 by a simple reg-reg copy. If so, the replacement reg rtx is returned,
13850 NULL_RTX otherwise. */
13852 sh_try_omit_signzero_extend (rtx extended_op
, rtx_insn
* insn
)
13854 if (REG_P (extended_op
))
13855 extended_op
= extended_op
;
13856 else if (GET_CODE (extended_op
) == SUBREG
&& REG_P (SUBREG_REG (extended_op
)))
13857 extended_op
= SUBREG_REG (extended_op
);
13861 /* Reg moves must be of the same mode. */
13862 if (GET_MODE (extended_op
) != SImode
)
13865 set_of_reg s
= sh_find_set_of_reg (extended_op
, insn
, prev_nonnote_insn_bb
);
13866 if (s
.set_src
== NULL_RTX
)
13869 if (t_reg_operand (s
.set_src
, VOIDmode
)
13870 || negt_reg_operand (s
.set_src
, VOIDmode
))
13871 return extended_op
;
13873 /* If the zero extended reg was formed by a logical operation, check the
13874 operands of the logical operation. If both originated from T bit
13875 stores the zero extension can be eliminated. */
13876 else if (sh_is_logical_t_store_expr (s
.set_src
, s
.insn
))
13877 return extended_op
;
13882 /* Given the current insn, which is assumed to be a movrt_negc insn, try to
13883 figure out whether it should be converted into a movt-xor sequence in
13884 the movrt_negc splitter.
13885 Returns true if insns have been modified and the splitter has succeeded. */
13887 sh_split_movrt_negc_to_movt_xor (rtx_insn
* curr_insn
, rtx operands
[])
13889 /* In cases such as
13894 we can replace the T bit clobbering negc with a movt-xor sequence and
13895 eliminate the redundant comparison.
13896 Because the xor insn depends on register allocation results, allow this
13897 only before reload. */
13898 if (!can_create_pseudo_p ())
13901 set_of_reg t_before_negc
= sh_find_set_of_reg (get_t_reg_rtx (), curr_insn
,
13902 prev_nonnote_insn_bb
);
13903 set_of_reg t_after_negc
= sh_find_set_of_reg (get_t_reg_rtx (), curr_insn
,
13904 next_nonnote_insn_bb
);
13906 if (t_before_negc
.set_rtx
!= NULL_RTX
&& t_after_negc
.set_rtx
!= NULL_RTX
13907 && rtx_equal_p (t_before_negc
.set_rtx
, t_after_negc
.set_rtx
)
13908 && !reg_used_between_p (get_t_reg_rtx (), curr_insn
, t_after_negc
.insn
)
13909 && !sh_insn_operands_modified_between_p (t_before_negc
.insn
,
13910 t_before_negc
.insn
,
13912 && !modified_between_p (get_t_reg_rtx (), curr_insn
, t_after_negc
.insn
)
13913 && !sh_unspec_insn_p (t_after_negc
.insn
)
13914 && !volatile_insn_p (PATTERN (t_after_negc
.insn
))
13915 && !side_effects_p (PATTERN (t_after_negc
.insn
))
13916 && !may_trap_or_fault_p (PATTERN (t_after_negc
.insn
)))
13918 emit_insn (gen_movrt_xor (operands
[0], get_t_reg_rtx ()));
13919 set_insn_deleted (t_after_negc
.insn
);
13926 /* Given a reg and the current insn, see if the value of the reg originated
13927 from a sign or zero extension and return the discovered information. */
13928 sh_extending_set_of_reg
13929 sh_find_extending_set_of_reg (rtx reg
, rtx_insn
* curr_insn
)
13932 return sh_extending_set_of_reg (curr_insn
);
13934 if (SUBREG_P (reg
))
13935 reg
= SUBREG_REG (reg
);
13938 return sh_extending_set_of_reg (curr_insn
);
13940 /* FIXME: Also search the predecessor basic blocks. It seems that checking
13941 only the adjacent predecessor blocks would cover most of the cases.
13942 Also try to look through the first extension that we hit. There are some
13943 cases, where a zero_extend is followed an (implicit) sign_extend, and it
13944 fails to see the sign_extend. */
13945 sh_extending_set_of_reg result
=
13946 sh_find_set_of_reg (reg
, curr_insn
, prev_nonnote_insn_bb
, true);
13948 if (result
.set_src
!= NULL
)
13950 if (GET_CODE (result
.set_src
) == SIGN_EXTEND
13951 || GET_CODE (result
.set_src
) == ZERO_EXTEND
)
13954 fprintf (dump_file
, "sh_find_extending_set_of_reg: reg %d is "
13955 "explicitly sign/zero extended in insn %d\n",
13956 REGNO (reg
), INSN_UID (result
.insn
));
13957 result
.from_mode
= GET_MODE (XEXP (result
.set_src
, 0));
13958 result
.ext_code
= GET_CODE (result
.set_src
);
13960 else if (MEM_P (result
.set_src
)
13961 && (GET_MODE (result
.set_src
) == QImode
13962 || GET_MODE (result
.set_src
) == HImode
)
13963 && !sh_unspec_insn_p (result
.insn
))
13965 /* On SH QIHImode memory loads always sign extend. However, in
13966 some cases where it seems that the higher bits are not
13967 interesting, the loads will not be expanded as sign extending
13968 insns, but as QIHImode loads into QIHImode regs. We report that
13969 the reg has been sign extended by the mem load. When it is used
13970 as such, we must convert the mem load into a sign extending insn,
13971 see also sh_extending_set_of_reg::use_as_extended_reg. */
13973 fprintf (dump_file
, "sh_find_extending_set_of_reg: reg %d is "
13974 "implicitly sign extended in insn %d\n",
13975 REGNO (reg
), INSN_UID (result
.insn
));
13976 result
.from_mode
= GET_MODE (result
.set_src
);
13977 result
.ext_code
= SIGN_EXTEND
;
13984 /* Given a reg that is known to be sign or zero extended at some insn,
13985 take the appropriate measures so that the extended value can be used as
13986 a reg at the specified insn and return the resulting reg rtx. */
13988 sh_extending_set_of_reg::use_as_extended_reg (rtx_insn
* use_at_insn
) const
13990 gcc_assert (insn
!= NULL
&& set_src
!= NULL
&& set_rtx
!= NULL
);
13991 gcc_assert (ext_code
== SIGN_EXTEND
|| ext_code
== ZERO_EXTEND
);
13992 gcc_assert (from_mode
== QImode
|| from_mode
== HImode
);
13994 if (MEM_P (set_src
) && ext_code
== SIGN_EXTEND
)
13997 fprintf (dump_file
,
13998 "use_as_extended_reg: converting non-extending mem load in "
13999 "insn %d into sign-extending load\n", INSN_UID (insn
));
14001 rtx r
= gen_reg_rtx (SImode
);
14003 if (from_mode
== QImode
)
14004 i0
= emit_insn_after (gen_extendqisi2 (r
, set_src
), insn
);
14005 else if (from_mode
== HImode
)
14006 i0
= emit_insn_after (gen_extendhisi2 (r
, set_src
), insn
);
14008 gcc_unreachable ();
14011 gen_move_insn (XEXP (set_rtx
, 0),
14012 gen_lowpart (GET_MODE (set_src
), r
)), i0
);
14013 set_insn_deleted (insn
);
14018 rtx extension_dst
= XEXP (set_rtx
, 0);
14019 if (GET_MODE (extension_dst
) != SImode
)
14020 extension_dst
= simplify_gen_subreg (SImode
, extension_dst
,
14021 GET_MODE (extension_dst
), 0);
14022 if (modified_between_p (extension_dst
, insn
, use_at_insn
))
14025 fprintf (dump_file
,
14026 "use_as_extended_reg: dest reg %d of extending insn %d is "
14027 "modified, inserting a reg-reg copy\n",
14028 REGNO (extension_dst
), INSN_UID (insn
));
14030 rtx r
= gen_reg_rtx (SImode
);
14031 emit_insn_after (gen_move_insn (r
, extension_dst
), insn
);
14036 sh_remove_reg_dead_or_unused_notes (insn
, REGNO (extension_dst
));
14037 return extension_dst
;
14043 sh_extending_set_of_reg::can_use_as_unextended_reg (void) const
14045 if ((ext_code
== SIGN_EXTEND
|| ext_code
== ZERO_EXTEND
)
14046 && (from_mode
== QImode
|| from_mode
== HImode
)
14047 && set_src
!= NULL
)
14048 return arith_reg_operand (XEXP (set_src
, 0), from_mode
);
14054 sh_extending_set_of_reg::use_as_unextended_reg (rtx_insn
* use_at_insn
) const
14056 gcc_assert (can_use_as_unextended_reg ());
14058 rtx r
= XEXP (set_src
, 0);
14059 rtx r0
= simplify_gen_subreg (SImode
, r
, from_mode
, 0);
14061 if (modified_between_p (r
, insn
, use_at_insn
))
14063 rtx r1
= gen_reg_rtx (SImode
);
14064 emit_insn_after (gen_move_insn (r1
, r0
), insn
);
14069 sh_remove_reg_dead_or_unused_notes (insn
, SUBREG_P (r
)
14070 ? REGNO (SUBREG_REG (r
))
14076 /* Given the current insn, which is assumed to be the *tst<mode>_t_subregs insn,
14077 perform the necessary checks on the operands and split it accordingly. */
14079 sh_split_tst_subregs (rtx_insn
* curr_insn
, machine_mode subreg_mode
,
14080 int subreg_offset
, rtx operands
[])
14082 gcc_assert (subreg_mode
== QImode
|| subreg_mode
== HImode
);
14084 sh_extending_set_of_reg eop0
= sh_find_extending_set_of_reg (operands
[0],
14086 sh_extending_set_of_reg eop1
= sh_find_extending_set_of_reg (operands
[1],
14089 /* If one of the operands is known to be zero extended, that's already
14090 sufficient to mask out the unwanted high bits. */
14091 if (eop0
.ext_code
== ZERO_EXTEND
&& eop0
.from_mode
== subreg_mode
)
14093 emit_insn (gen_tstsi_t (eop0
.use_as_extended_reg (curr_insn
),
14097 if (eop1
.ext_code
== ZERO_EXTEND
&& eop1
.from_mode
== subreg_mode
)
14099 emit_insn (gen_tstsi_t (operands
[0],
14100 eop1
.use_as_extended_reg (curr_insn
)));
14104 /* None of the operands seem to be zero extended.
14105 If both are sign extended it's OK, too. */
14106 if (eop0
.ext_code
== SIGN_EXTEND
&& eop1
.ext_code
== SIGN_EXTEND
14107 && eop0
.from_mode
== subreg_mode
&& eop1
.from_mode
== subreg_mode
)
14109 emit_insn (gen_tstsi_t (eop0
.use_as_extended_reg (curr_insn
),
14110 eop1
.use_as_extended_reg (curr_insn
)));
14114 /* Otherwise we have to insert a zero extension on one of the operands to
14115 mask out the unwanted high bits.
14116 Prefer the operand that has no known extension. */
14117 if (eop0
.ext_code
!= UNKNOWN
&& eop1
.ext_code
== UNKNOWN
)
14118 std::swap (operands
[0], operands
[1]);
14120 rtx tmp0
= gen_reg_rtx (SImode
);
14121 rtx tmp1
= simplify_gen_subreg (subreg_mode
, operands
[0],
14122 GET_MODE (operands
[0]), subreg_offset
);
14123 emit_insn (subreg_mode
== QImode
14124 ? gen_zero_extendqisi2 (tmp0
, tmp1
)
14125 : gen_zero_extendhisi2 (tmp0
, tmp1
));
14126 emit_insn (gen_tstsi_t (tmp0
, operands
[1]));
14129 /* A helper class to increment/decrement a counter variable each time a
14130 function is entered/left. */
14131 class scope_counter
14134 scope_counter (int& counter
) : m_counter (counter
) { ++m_counter
; }
14136 ~scope_counter (void)
14139 gcc_assert (m_counter
>= 0);
14142 int count (void) const { return m_counter
; }
14148 /* Given an rtx x, determine whether the expression can be used to create
14149 an insn that calulates x and stores the result in the T bit.
14150 This is used by the 'treg_set_expr' predicate to construct insns sequences
14151 where T bit results are fed into other insns, such as addc, subc, negc
14154 FIXME: The patterns that expand 'treg_set_expr' operands tend to
14155 distinguish between 'positive' and 'negative' forms. For now this has to
14156 be done in the preparation code. We could also introduce
14157 'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write
14158 two different patterns for the 'postive' and 'negative' forms. However,
14159 the total amount of lines of code seems to be about the same and the
14160 '{pos|neg}_treg_set_expr' predicates would be more expensive, because the
14161 recog function would need to look inside the expression by temporarily
14163 static int sh_recog_treg_set_expr_reent_count
= 0;
14166 sh_recog_treg_set_expr (rtx op
, machine_mode mode
)
14168 scope_counter
recursion (sh_recog_treg_set_expr_reent_count
);
14170 /* Limit the recursion count to avoid nested expressions which we can't
14171 resolve to a single treg set insn. */
14172 if (recursion
.count () > 1)
14175 /* Early accept known possible operands before doing recog. */
14176 if (op
== const0_rtx
|| op
== const1_rtx
|| t_reg_operand (op
, mode
))
14179 /* Early reject impossible operands before doing recog.
14180 There are some (set ((t) (subreg ...))) patterns, but we must be careful
14181 not to allow any invalid reg-reg or mem-reg moves, or else other passes
14182 such as lower-subreg will bail out. Some insns such as SH4A movua are
14183 done with UNSPEC, so must reject those, too, or else it would result
14184 in an invalid reg -> treg move. */
14185 if (register_operand (op
, mode
) || memory_operand (op
, mode
)
14186 || sh_unspec_insn_p (op
))
14189 if (!can_create_pseudo_p ())
14192 /* expand_debug_locations may call this to compute rtx costs at
14193 very early stage. In that case, don't make new insns here to
14194 avoid codegen differences with -g. */
14195 if (currently_expanding_to_rtl
)
14198 /* We are going to invoke recog in a re-entrant way and thus
14199 have to capture its current state and restore it afterwards. */
14200 recog_data_d prev_recog_data
= recog_data
;
14202 rtx_insn
* i
= make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op
));
14203 SET_PREV_INSN (i
) = NULL
;
14204 SET_NEXT_INSN (i
) = NULL
;
14206 int result
= recog (PATTERN (i
), i
, 0);
14208 /* It seems there is no insn like that. Create a simple negated
14209 version and try again. If we hit a negated form, we'll allow that
14210 and append a nott sequence when splitting out the insns. Insns that
14211 do the split can then remove the trailing nott if they know how to
14213 if (result
< 0 && GET_CODE (op
) == EQ
)
14216 result
= recog (PATTERN (i
), i
, 0);
14219 if (result
< 0 && GET_CODE (op
) == NE
)
14222 result
= recog (PATTERN (i
), i
, 0);
14226 recog_data
= prev_recog_data
;
14227 return result
>= 0;
14230 /* Returns true when recog of a 'treg_set_expr' is currently in progress.
14231 This can be used as a condition for insn/split patterns to allow certain
14232 T bit setting patters only to be matched as sub expressions of other
14235 sh_in_recog_treg_set_expr (void)
14237 return sh_recog_treg_set_expr_reent_count
> 0;
14240 /* Given an rtx x, which is assumed to be some expression that has been
14241 matched by the 'treg_set_expr' predicate before, split and emit the
14242 insns that are necessary to calculate the expression and store the result
14244 The splitting is done recursively similar to 'try_split' in emit-rt.c.
14245 Unfortunately we can't use 'try_split' here directly, as it tries to invoke
14246 'delete_insn' which then causes the DF parts to bail out, because we
14247 currently are inside another gen_split* function and would invoke
14248 'try_split' in a reentrant way. */
14249 static std::pair
<rtx_insn
*, rtx_insn
*>
14250 sh_try_split_insn_simple (rtx_insn
* i
, rtx_insn
* curr_insn
, int n
= 0)
14254 fprintf (dump_file
, "sh_try_split_insn_simple n = %d i = \n", n
);
14255 print_rtl_single (dump_file
, i
);
14256 fprintf (dump_file
, "\n");
14259 rtx_insn
* seq
= split_insns (PATTERN (i
), curr_insn
);
14262 return std::make_pair (i
, i
);
14264 /* Avoid infinite splitter loops if any insn of the result matches
14265 the original pattern. */
14266 for (rtx_insn
* s
= seq
; s
!= NULL
; s
= NEXT_INSN (s
))
14267 if (INSN_P (s
) && rtx_equal_p (PATTERN (s
), PATTERN (i
)))
14268 return std::make_pair (i
, i
);
14270 unshare_all_rtl_in_chain (seq
);
14272 /* 'seq' is now a replacement for 'i'. Assuming that 'i' is an insn in
14273 a linked list, replace the single insn with the new insns. */
14274 rtx_insn
* seqlast
= seq
;
14275 while (NEXT_INSN (seqlast
) != NULL
)
14276 seqlast
= NEXT_INSN (seqlast
);
14278 if (rtx_insn
* iprev
= PREV_INSN (i
))
14279 SET_NEXT_INSN (iprev
) = seq
;
14280 if (rtx_insn
* inext
= NEXT_INSN (i
))
14281 SET_PREV_INSN (inext
) = seqlast
;
14283 SET_PREV_INSN (seq
) = PREV_INSN (i
);
14284 SET_NEXT_INSN (seqlast
) = NEXT_INSN (i
);
14286 SET_PREV_INSN (i
) = NULL
;
14287 SET_NEXT_INSN (i
) = NULL
;
14289 /* Recursively split all insns. */
14290 for (i
= seq
; ; i
= NEXT_INSN (i
))
14292 std::pair
<rtx_insn
*, rtx_insn
*> ii
=
14293 sh_try_split_insn_simple (i
, curr_insn
, n
+ 1);
14298 seqlast
= ii
.second
;
14304 return std::make_pair (seq
, seqlast
);
14308 sh_split_treg_set_expr (rtx x
, rtx_insn
* curr_insn
)
14310 if (t_reg_operand (x
, VOIDmode
))
14311 return sh_treg_insns ();
14313 scope_counter
in_treg_set_expr (sh_recog_treg_set_expr_reent_count
);
14315 rtx_insn
* i
= make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), x
));
14316 SET_PREV_INSN (i
) = NULL
;
14317 SET_NEXT_INSN (i
) = NULL
;
14321 fprintf (dump_file
, "split_treg_set_expr insn:\n");
14322 print_rtl (dump_file
, i
);
14323 fprintf (dump_file
, "\n");
14326 /* We are going to invoke recog/split_insns in a re-entrant way and thus
14327 have to capture its current state and restore it afterwards. */
14328 recog_data_d prev_recog_data
= recog_data
;
14330 int insn_code
= recog (PATTERN (i
), i
, 0);
14332 /* If the insn was not found, see if we matched the negated form before
14333 and append a nott. */
14334 bool append_nott
= false;
14336 if (insn_code
< 0 && GET_CODE (x
) == EQ
)
14339 insn_code
= recog (PATTERN (i
), i
, 0);
14340 if (insn_code
>= 0)
14341 append_nott
= true;
14345 if (insn_code
< 0 && GET_CODE (x
) == NE
)
14348 insn_code
= recog (PATTERN (i
), i
, 0);
14349 if (insn_code
>= 0)
14350 append_nott
= true;
14355 gcc_assert (insn_code
>= 0);
14357 /* Try to recursively split the insn. Some insns might refuse to split
14358 any further while we are in the treg_set_expr splitting phase. They
14359 will be emitted as part of the outer insn and then split again. */
14360 std::pair
<rtx_insn
*, rtx_insn
*> insnlist
=
14361 sh_try_split_insn_simple (i
, curr_insn
);
14363 /* Restore recog state. */
14364 recog_data
= prev_recog_data
;
14366 rtx_insn
* nott_insn
= sh_is_nott_insn (insnlist
.second
)
14371 fprintf (dump_file
, "split_treg_set_expr insnlist:\n");
14372 print_rtl (dump_file
, insnlist
.first
);
14373 fprintf (dump_file
, "\n");
14375 if (nott_insn
!= NULL
)
14376 fprintf (dump_file
, "trailing nott insn %d\n", INSN_UID (nott_insn
));
14379 emit_insn (insnlist
.first
);
14381 if (nott_insn
!= NULL
&& append_nott
)
14384 fprintf (dump_file
, "removing trailing nott\n");
14385 remove_insn (nott_insn
);
14387 append_nott
= false;
14391 nott_insn
= emit_insn (gen_nott (get_t_reg_rtx ()));
14393 rtx_insn
* first_insn
= get_insns ();
14397 fprintf (dump_file
, "resulting insns:\n");
14398 print_rtl (dump_file
, first_insn
);
14399 fprintf (dump_file
, "\n");
14402 return sh_treg_insns (first_insn
, nott_insn
);
14405 /*------------------------------------------------------------------------------
14406 Mode switching support code.
14410 sh_emit_mode_set (int entity ATTRIBUTE_UNUSED
, int mode
,
14411 int prev_mode
, HARD_REG_SET regs_live ATTRIBUTE_UNUSED
)
14413 if ((TARGET_SH4A_FP
|| TARGET_SH4_300
)
14414 && prev_mode
!= FP_MODE_NONE
&& prev_mode
!= mode
)
14416 emit_insn (gen_toggle_pr ());
14418 emit_insn (gen_toggle_sz ());
14420 else if (mode
!= FP_MODE_NONE
)
14422 rtx tmp
= gen_reg_rtx (SImode
);
14423 emit_insn (gen_sts_fpscr (tmp
));
14426 const unsigned HOST_WIDE_INT fpbits
=
14427 TARGET_FMOVD
? (FPSCR_PR
| FPSCR_SZ
) : FPSCR_PR
;
14429 if (prev_mode
!= FP_MODE_NONE
&& prev_mode
!= mode
)
14430 i
= gen_xorsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (fpbits
)));
14431 else if (mode
== FP_MODE_SINGLE
)
14432 i
= gen_andsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (~fpbits
)));
14433 else if (mode
== FP_MODE_DOUBLE
)
14434 i
= gen_iorsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (fpbits
)));
14436 gcc_unreachable ();
14439 emit_insn (gen_lds_fpscr (tmp
));
14444 sh_mode_needed (int entity ATTRIBUTE_UNUSED
, rtx_insn
*insn
)
14446 return recog_memoized (insn
) >= 0 ? get_attr_fp_mode (insn
) : FP_MODE_NONE
;
14450 sh_mode_after (int entity ATTRIBUTE_UNUSED
, int mode
, rtx_insn
*insn
)
14452 if (TARGET_HITACHI
&& recog_memoized (insn
) >= 0 &&
14453 get_attr_fp_set (insn
) != FP_SET_NONE
)
14454 return (int) get_attr_fp_set (insn
);
14460 sh_mode_entry (int entity ATTRIBUTE_UNUSED
)
14462 return NORMAL_MODE (entity
);
14466 sh_mode_exit (int entity ATTRIBUTE_UNUSED
)
14468 return sh_cfun_attr_renesas_p () ? FP_MODE_NONE
: NORMAL_MODE (entity
);
14472 sh_mode_priority (int entity ATTRIBUTE_UNUSED
, int n
)
14474 return ((TARGET_FPU_SINGLE
!= 0) ^ (n
) ? FP_MODE_SINGLE
: FP_MODE_DOUBLE
);
14477 /*------------------------------------------------------------------------------
14481 /* Return true if we use LRA instead of reload pass. */
14485 return sh_lra_flag
;
14488 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
14491 sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
14492 unsigned int align
,
14493 enum by_pieces_operation op
,
14498 case MOVE_BY_PIECES
:
14499 return move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
14500 < (!speed_p
? 2 : (align
>= 32) ? 16 : 2);
14501 case STORE_BY_PIECES
:
14502 case SET_BY_PIECES
:
14503 return move_by_pieces_ninsns (size
, align
, STORE_MAX_PIECES
+ 1)
14504 < (!speed_p
? 2 : (align
>= 32) ? 16 : 2);
14506 return default_use_by_pieces_infrastructure_p (size
, align
,