gcc/doc/gcc/extensions-to-the-c-language-family/target-builtins/mips-paired-single-support.rst

   1 ..
   2   Copyright 1988-2022 Free Software Foundation, Inc.
   3   This is part of the GCC manual.
   4   For copying conditions, see the copyright.rst file.
   5
   6 .. _mips-paired-single-support:
   7
   8 MIPS Paired-Single Support
   9 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  10
  11 The MIPS64 architecture includes a number of instructions that
  12 operate on pairs of single-precision floating-point values.
  13 Each pair is packed into a 64-bit floating-point register,
  14 with one element being designated the 'upper half' and
  15 the other being designated the 'lower half'.
  16
  17 GCC supports paired-single operations using both the generic
  18 vector extensions (see :ref:`vector-extensions`) and a collection of
  19 MIPS-specific built-in functions.  Both kinds of support are
  20 enabled by the :option:`-mpaired-single` command-line option.
  21
  22 The vector type associated with paired-single values is usually
  23 called ``v2sf``.  It can be defined in C as follows:
  24
  25 .. code-block:: c++
  26
  27   typedef float v2sf __attribute__ ((vector_size (8)));
  28
  29 ``v2sf`` values are initialized in the same way as aggregates.
  30 For example:
  31
  32 .. code-block:: c++
  33
  34   v2sf a = {1.5, 9.1};
  35   v2sf b;
  36   float e, f;
  37   b = (v2sf) {e, f};
  38
  39 .. note::
  40   The CPU's endianness determines which value is stored in
  41   the upper half of a register and which value is stored in the lower half.
  42   On little-endian targets, the first value is the lower one and the second
  43   value is the upper one.  The opposite order applies to big-endian targets.
  44   For example, the code above sets the lower half of ``a`` to
  45   ``1.5`` on little-endian targets and ``9.1`` on big-endian targets.