2 Copyright 1988-2022 Free Software Foundation, Inc.
3 This is part of the GCC manual.
4 For copying conditions, see the copyright.rst file.
8 .. index:: AArch64 Options
15 These options are defined for AArch64 implementations:
17 .. option:: -mabi={name}
19 Generate code for the specified data model. Permissible values
20 are :samp:`ilp32` for SysV-like data model where int, long int and pointers
21 are 32 bits, and :samp:`lp64` for SysV-like data model where int is 32 bits,
22 but long int and pointers are 64 bits.
24 The default depends on the specific target configuration. Note that
25 the LP64 and ILP32 ABIs are not link-compatible; you must compile your
26 entire program with the same ABI, and link with a compatible set of libraries.
28 .. option:: -mbig-endian
30 Generate big-endian code. This is the default when GCC is configured for an
31 :samp:`aarch64_be-*-*` target.
33 .. option:: -mgeneral-regs-only
35 Generate code which uses only the general-purpose registers. This will prevent
36 the compiler from using floating-point and Advanced SIMD registers but will not
37 impose any restrictions on the assembler.
39 .. option:: -mlittle-endian
41 Generate little-endian code. This is the default when GCC is configured for an
42 :samp:`aarch64-*-*` but not an :samp:`aarch64_be-*-*` target.
44 .. option:: -mcmodel=tiny
46 Generate code for the tiny code model. The program and its statically defined
47 symbols must be within 1MB of each other. Programs can be statically or
50 .. option:: -mcmodel=small
52 Generate code for the small code model. The program and its statically defined
53 symbols must be within 4GB of each other. Programs can be statically or
54 dynamically linked. This is the default code model.
56 .. option:: -mcmodel=large
58 Generate code for the large code model. This makes no assumptions about
59 addresses and sizes of sections. Programs can be statically linked only. The
60 :option:`-mcmodel=large` option is incompatible with :option:`-mabi=ilp32`,
61 :option:`-fpic` and :option:`-fPIC`.
63 .. option:: -mstrict-align, -mno-strict-align
65 Avoid or allow generating memory accesses that may not be aligned on a natural
66 object boundary as described in the architecture specification.
68 .. option:: -momit-leaf-frame-pointer, -mno-omit-leaf-frame-pointer
70 Omit or keep the frame pointer in leaf functions. The former behavior is the
73 .. option:: -mstack-protector-guard={guard}
75 Generate stack protection code using canary at :samp:`{guard}`. Supported
76 locations are :samp:`global` for a global canary or :samp:`sysreg` for a
77 canary in an appropriate system register.
79 With the latter choice the options
80 :option:`-mstack-protector-guard-reg=reg` and
81 :option:`-mstack-protector-guard-offset=offset` furthermore specify
82 which system register to use as base register for reading the canary,
83 and from what offset from that base register. There is no default
84 register or offset as this is entirely for use within the Linux
87 .. option:: -mtls-dialect=desc
89 Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
90 of TLS variables. This is the default.
92 .. option:: -mtls-dialect=traditional
94 Use traditional TLS as the thread-local storage mechanism for dynamic accesses
97 .. option:: -mtls-size={size}
99 Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
100 This option requires binutils 2.26 or newer.
102 .. option:: -mfix-cortex-a53-835769, -mno-fix-cortex-a53-835769
104 Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
105 This involves inserting a NOP instruction between memory instructions and
106 64-bit integer multiply-accumulate instructions.
108 .. option:: -mfix-cortex-a53-843419, -mno-fix-cortex-a53-843419
110 Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
111 This erratum workaround is made at link time and this will only pass the
112 corresponding flag to the linker.
114 .. option:: -mlow-precision-recip-sqrt, -mno-low-precision-recip-sqrt
116 Enable or disable the reciprocal square root approximation.
117 This option only has an effect if :option:`-ffast-math` or
118 :option:`-funsafe-math-optimizations` is used as well. Enabling this reduces
119 precision of reciprocal square root results to about 16 bits for
120 single precision and to 32 bits for double precision.
122 .. option:: -mlow-precision-sqrt, -mno-low-precision-sqrt
124 Enable or disable the square root approximation.
125 This option only has an effect if :option:`-ffast-math` or
126 :option:`-funsafe-math-optimizations` is used as well. Enabling this reduces
127 precision of square root results to about 16 bits for
128 single precision and to 32 bits for double precision.
129 If enabled, it implies :option:`-mlow-precision-recip-sqrt`.
131 .. option:: -mlow-precision-div, -mno-low-precision-div
133 Enable or disable the division approximation.
134 This option only has an effect if :option:`-ffast-math` or
135 :option:`-funsafe-math-optimizations` is used as well. Enabling this reduces
136 precision of division results to about 16 bits for
137 single precision and to 32 bits for double precision.
139 .. option:: -mtrack-speculation, -mno-track-speculation
141 Enable or disable generation of additional code to track speculative
142 execution through conditional branches. The tracking state can then
143 be used by the compiler when expanding calls to
144 ``__builtin_speculation_safe_copy`` to permit a more efficient code
145 sequence to be generated.
147 .. option:: -moutline-atomics, -mno-outline-atomics
149 Enable or disable calls to out-of-line helpers to implement atomic operations.
150 These helpers will, at runtime, determine if the LSE instructions from
151 ARMv8.1-A can be used; if not, they will use the load/store-exclusive
152 instructions that are present in the base ARMv8.0 ISA.
154 This option is only applicable when compiling for the base ARMv8.0
155 instruction set. If using a later revision, e.g. :option:`-march=armv8.1-a`
156 or :option:`-march=armv8-a+lse`, the ARMv8.1-Atomics instructions will be
157 used directly. The same applies when using :option:`-mcpu=` when the
158 selected cpu supports the :samp:`lse` feature.
159 This option is on by default.
161 .. option:: -march={name}
163 Specify the name of the target architecture and, optionally, one or
164 more feature modifiers. This option has the form
165 :option:`-march=arch{+[no]feature}*`.
167 The table below summarizes the permissible values for :samp:`{arch}`
168 and the features that they enable by default:
173 * - :samp:`{arch}` value
175 - Includes by default
179 - :samp:`+fp`, :samp:`+simd`
180 * - :samp:`armv8.1-a`
182 - :samp:`armv8-a`, :samp:`+crc`, :samp:`+lse`, :samp:`+rdma`
183 * - :samp:`armv8.2-a`
186 * - :samp:`armv8.3-a`
188 - :samp:`armv8.2-a`, :samp:`+pauth`
189 * - :samp:`armv8.4-a`
191 - :samp:`armv8.3-a`, :samp:`+flagm`, :samp:`+fp16fml`, :samp:`+dotprod`
192 * - :samp:`armv8.5-a`
194 - :samp:`armv8.4-a`, :samp:`+sb`, :samp:`+ssbs`, :samp:`+predres`
195 * - :samp:`armv8.6-a`
197 - :samp:`armv8.5-a`, :samp:`+bf16`, :samp:`+i8mm`
198 * - :samp:`armv8.7-a`
200 - :samp:`armv8.6-a`, :samp:`+ls64`
201 * - :samp:`armv8.8-a`
203 - :samp:`armv8.7-a`, :samp:`+mops`
206 - :samp:`armv8.5-a`, :samp:`+sve`, :samp:`+sve2`
207 * - :samp:`armv9.1-a`
209 - :samp:`armv9-a`, :samp:`+bf16`, :samp:`+i8mm`
210 * - :samp:`armv9.2-a`
212 - :samp:`armv9.1-a`, :samp:`+ls64`
213 * - :samp:`armv9.3-a`
215 - :samp:`armv9.2-a`, :samp:`+mops`
220 The value :samp:`native` is available on native AArch64 GNU/Linux and
221 causes the compiler to pick the architecture of the host system. This
222 option has no effect if the compiler is unable to recognize the
223 architecture of the host system,
225 The permissible values for :samp:`{feature}` are listed in the sub-section
226 on :ref:`aarch64-feature-modifiers`.
227 Where conflicting feature modifiers are
228 specified, the right-most feature is used.
230 GCC uses :samp:`{name}` to determine what kind of instructions it can emit
231 when generating assembly code. If :option:`-march` is specified
232 without either of :option:`-mtune` or :option:`-mcpu` also being
233 specified, the code is tuned to perform well across a range of target
234 processors implementing the target architecture.
236 .. option:: -mtune={name}
238 Specify the name of the target processor for which GCC should tune the
239 performance of the code. Permissible values for this option are:
240 :samp:`generic`, :samp:`cortex-a35`, :samp:`cortex-a53`, :samp:`cortex-a55`,
241 :samp:`cortex-a57`, :samp:`cortex-a72`, :samp:`cortex-a73`, :samp:`cortex-a75`,
242 :samp:`cortex-a76`, :samp:`cortex-a76ae`, :samp:`cortex-a77`,
243 :samp:`cortex-a65`, :samp:`cortex-a65ae`, :samp:`cortex-a34`,
244 :samp:`cortex-a78`, :samp:`cortex-a78ae`, :samp:`cortex-a78c`,
245 :samp:`ares`, :samp:`exynos-m1`, :samp:`emag`, :samp:`falkor`,
246 :samp:`neoverse-512tvb`, :samp:`neoverse-e1`, :samp:`neoverse-n1`,
247 :samp:`neoverse-n2`, :samp:`neoverse-v1`, :samp:`neoverse-v2`, :samp:`qdf24xx`,
248 :samp:`saphira`, :samp:`phecda`, :samp:`xgene1`, :samp:`vulcan`,
249 :samp:`octeontx`, :samp:`octeontx81`, :samp:`octeontx83`,
250 :samp:`octeontx2`, :samp:`octeontx2t98`, :samp:`octeontx2t96`
251 :samp:`octeontx2t93`, :samp:`octeontx2f95`, :samp:`octeontx2f95n`,
252 :samp:`octeontx2f95mm`,
254 :samp:`thunderx`, :samp:`thunderxt88`,
255 :samp:`thunderxt88p1`, :samp:`thunderxt81`, :samp:`tsv110`,
256 :samp:`thunderxt83`, :samp:`thunderx2t99`, :samp:`thunderx3t110`, :samp:`zeus`,
257 :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
258 :samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
259 :samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
260 :samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
261 :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`ampere1`, :samp:`native`.
263 The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
264 :samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
265 :samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55` specify that GCC
266 should tune for a big.LITTLE system.
268 The value :samp:`neoverse-512tvb` specifies that GCC should tune
269 for Neoverse cores that (a) implement SVE and (b) have a total vector
270 bandwidth of 512 bits per cycle. In other words, the option tells GCC to
271 tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic
272 instructions a cycle and that can execute an equivalent number of SVE
273 arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE).
274 This is more general than tuning for a specific core like Neoverse V1
275 but is more specific than the default tuning described below.
277 Additionally on native AArch64 GNU/Linux systems the value
278 :samp:`native` tunes performance to the host system. This option has no effect
279 if the compiler is unable to recognize the processor of the host system.
281 Where none of :option:`-mtune=`, :option:`-mcpu=` or :option:`-march=`
282 are specified, the code is tuned to perform well across a range
283 of target processors.
285 This option cannot be suffixed by feature modifiers.
287 .. option:: -mcpu={name}
289 Specify the name of the target processor, optionally suffixed by one
290 or more feature modifiers. This option has the form
291 :option:`-mcpu=cpu{+[no]feature}*`, where
292 the permissible values for :samp:`{cpu}` are the same as those available
293 for :option:`-mtune`. The permissible values for :samp:`{feature}` are
294 documented in the sub-section on :ref:`aarch64-feature-modifiers`.
295 Where conflicting feature modifiers are
296 specified, the right-most feature is used.
298 GCC uses :samp:`{name}` to determine what kind of instructions it can emit when
299 generating assembly code (as if by :option:`-march`) and to determine
300 the target processor for which to tune for performance (as if
301 by :option:`-mtune`). Where this option is used in conjunction
302 with :option:`-march` or :option:`-mtune`, those options take precedence
303 over the appropriate part of this option.
305 :option:`-mcpu=neoverse-512tvb` is special in that it does not refer
306 to a specific core, but instead refers to all Neoverse cores that
307 (a) implement SVE and (b) have a total vector bandwidth of 512 bits
308 a cycle. Unless overridden by :option:`-march`,
309 :option:`-mcpu=neoverse-512tvb` generates code that can run on a
310 Neoverse V1 core, since Neoverse V1 is the first Neoverse core with
311 these properties. Unless overridden by :option:`-mtune`,
312 :option:`-mcpu=neoverse-512tvb` tunes code in the same way as for
313 :option:`-mtune=neoverse-512tvb`.
315 .. option:: -moverride={string}
317 Override tuning decisions made by the back-end in response to a
318 :option:`-mtune=` switch. The syntax, semantics, and accepted values
319 for :samp:`{string}` in this option are not guaranteed to be consistent
322 This option is only intended to be useful when developing GCC.
324 .. option:: -mverbose-cost-dump
326 Enable verbose cost model dumping in the debug dump files. This option is
327 provided for use in debugging the compiler.
329 .. option:: -mpc-relative-literal-loads, -mno-pc-relative-literal-loads
331 Enable or disable PC-relative literal loads. With this option literal pools are
332 accessed using a single instruction and emitted after each function. This
333 limits the maximum size of functions to 1MB. This is enabled by default for
334 :option:`-mcmodel=tiny`.
336 .. option:: -msign-return-address={scope}
338 Select the function scope on which return address signing will be applied.
339 Permissible values are :samp:`none`, which disables return address signing,
340 :samp:`non-leaf`, which enables pointer signing for functions which are not leaf
341 functions, and :samp:`all`, which enables pointer signing for all functions. The
342 default value is :samp:`none`. This option has been deprecated by
345 .. option:: -mbranch-protection={none}|{standard}|{pac-ret}[+{leaf}+{b-key}]|{bti}
347 Select the branch protection features to use.
348 :samp:`none` is the default and turns off all types of branch protection.
349 :samp:`standard` turns on all types of branch protection features. If a feature
350 has additional tuning options, then :samp:`standard` sets it to its standard
352 :samp:`pac-ret[+{leaf}]` turns on return address signing to its standard
353 level: signing functions that save the return address to memory (non-leaf
354 functions will practically always do this) using the a-key. The optional
355 argument :samp:`leaf` can be used to extend the signing to include leaf
356 functions. The optional argument :samp:`b-key` can be used to sign the functions
357 with the B-key instead of the A-key.
358 :samp:`bti` turns on branch target identification mechanism.
360 .. option:: -mharden-sls={opts}
362 Enable compiler hardening against straight line speculation (SLS).
363 :samp:`{opts}` is a comma-separated list of the following options:
365 :samp:`retbr` :samp:`blr`
367 In addition, :option:`-mharden-sls`:samp:`=all` enables all SLS hardening while
368 :option:`-mharden-sls`:samp:`=none` disables all SLS hardening.
370 .. option:: -msve-vector-bits={bits}
372 Specify the number of bits in an SVE vector register. This option only has
373 an effect when SVE is enabled.
375 GCC supports two forms of SVE code generation: 'vector-length
376 agnostic' output that works with any size of vector register and
377 'vector-length specific' output that allows GCC to make assumptions
378 about the vector length when it is useful for optimization reasons.
379 The possible values of :samp:`bits` are: :samp:`scalable`, :samp:`128`,
380 :samp:`256`, :samp:`512`, :samp:`1024` and :samp:`2048`.
381 Specifying :samp:`scalable` selects vector-length agnostic
382 output. At present :samp:`-msve-vector-bits=128` also generates vector-length
383 agnostic output for big-endian targets. All other values generate
384 vector-length specific code. The behavior of these values may change
385 in future releases and no value except :samp:`scalable` should be
386 relied on for producing code that is portable across different
387 hardware SVE vector lengths.
389 The default is :samp:`-msve-vector-bits=scalable`, which produces
390 vector-length agnostic code.
393 .. _aarch64-feature-modifiers:
395 -march and -mcpu Feature Modifiers
396 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
398 .. index:: -march feature modifiers, -mcpu feature modifiers
400 Feature modifiers used with :option:`-march` and :option:`-mcpu` can be any of
401 the following and their inverses no :samp:`{feature}` :
404 Enable CRC extension. This is on by default for
405 :option:`-march=armv8.1-a`.
408 Enable Crypto extension. This also enables Advanced SIMD and floating-point
412 Enable floating-point instructions. This is on by default for all possible
413 values for options :option:`-march` and :option:`-mcpu`.
416 Enable Advanced SIMD instructions. This also enables floating-point
417 instructions. This is on by default for all possible values for options
418 :option:`-march` and :option:`-mcpu`.
421 Enable Scalable Vector Extension instructions. This also enables Advanced
422 SIMD and floating-point instructions.
425 Enable Large System Extension instructions. This is on by default for
426 :option:`-march=armv8.1-a`.
429 Enable Round Double Multiply Accumulate instructions. This is on by default
430 for :option:`-march=armv8.1-a`.
433 Enable FP16 extension. This also enables floating-point instructions.
436 Enable FP16 fmla extension. This also enables FP16 extensions and
437 floating-point instructions. This option is enabled by default for :option:`-march=armv8.4-a`. Use of this option with architectures prior to Armv8.2-A is not supported.
440 Enable the RcPc extension. This does not change code generation from GCC,
441 but is passed on to the assembler, enabling inline asm statements to use
442 instructions from the RcPc extension.
445 Enable the Dot Product extension. This also enables Advanced SIMD instructions.
448 Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced
452 Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions.
455 Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMD
456 instructions. Use of this option with architectures prior to Armv8.2-A is not supported.
459 Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions.
460 Use of this option with architectures prior to Armv8.2-A is not supported.
463 Enable the Statistical Profiling extension. This option is only to enable the
464 extension at the assembler level and does not affect code generation.
467 Enable the Armv8.5-a Random Number instructions. This option is only to
468 enable the extension at the assembler level and does not affect code
472 Enable the Armv8.5-a Memory Tagging Extensions.
473 Use of this option with architectures prior to Armv8.5-A is not supported.
476 Enable the Armv8-a Speculation Barrier instruction. This option is only to
477 enable the extension at the assembler level and does not affect code
478 generation. This option is enabled by default for :option:`-march=armv8.5-a`.
481 Enable the Armv8-a Speculative Store Bypass Safe instruction. This option
482 is only to enable the extension at the assembler level and does not affect code
483 generation. This option is enabled by default for :option:`-march=armv8.5-a`.
486 Enable the Armv8-a Execution and Data Prediction Restriction instructions.
487 This option is only to enable the extension at the assembler level and does
488 not affect code generation. This option is enabled by default for
489 :option:`-march=armv8.5-a`.
492 Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE
496 Enable SVE2 bitperm instructions. This also enables SVE2 instructions.
499 Enable SVE2 sm4 instructions. This also enables SVE2 instructions.
502 Enable SVE2 aes instructions. This also enables SVE2 instructions.
505 Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
508 Enable the Transactional Memory Extension.
511 Enable 8-bit Integer Matrix Multiply instructions. This also enables
512 Advanced SIMD and floating-point instructions. This option is enabled by
513 default for :option:`-march=armv8.6-a`. Use of this option with architectures
514 prior to Armv8.2-A is not supported.
517 Enable 32-bit Floating point Matrix Multiply instructions. This also enables
518 SVE instructions. Use of this option with architectures prior to Armv8.2-A is
522 Enable 64-bit Floating point Matrix Multiply instructions. This also enables
523 SVE instructions. Use of this option with architectures prior to Armv8.2-A is
527 Enable brain half-precision floating-point instructions. This also enables
528 Advanced SIMD and floating-point instructions. This option is enabled by
529 default for :option:`-march=armv8.6-a`. Use of this option with architectures
530 prior to Armv8.2-A is not supported.
533 Enable the 64-byte atomic load and store instructions for accelerators.
534 This option is enabled by default for :option:`-march=armv8.7-a`.
537 Enable the instructions to accelerate memory operations like ``memcpy``,
538 ``memmove``, ``memset``. This option is enabled by default for
539 :option:`-march=armv8.8-a`
542 Enable the Flag Manipulation instructions Extension.
545 Enable the Pointer Authentication Extension.
547 Feature ``crypto`` implies ``aes``, ``sha2``, and ``simd``,
548 which implies ``fp``.
549 Conversely, ``nofp`` implies ``nosimd``, which implies
550 ``nocrypto``, ``noaes`` and ``nosha2``.