gcc/doc/gcc/gcc-command-options/machine-dependent-options/arc-options.rst

   1 ..
   2   Copyright 1988-2022 Free Software Foundation, Inc.
   3   This is part of the GCC manual.
   4   For copying conditions, see the copyright.rst file.
   5
   6 .. program:: ARC
   7
   8 .. index:: ARC options
   9
  10 .. _arc-options:
  11
  12 ARC Options
  13 ^^^^^^^^^^^
  14
  15 The following options control the architecture variant for which code
  16 is being compiled:
  17
  18 .. architecture variants
  19
  20 .. option:: -mbarrel-shifter
  21
  22   Generate instructions supported by barrel shifter.  This is the default
  23   unless :option:`-mcpu=ARC601` or :samp:`-mcpu=ARCEM` is in effect.
  24
  25 .. option:: -mjli-always
  26
  27   Force to call a function using jli_s instruction.  This option is
  28   valid only for ARCv2 architecture.
  29
  30 .. option:: -mcpu={cpu}
  31
  32   Set architecture type, register usage, and instruction scheduling
  33   parameters for :samp:`{cpu}`.  There are also shortcut alias options
  34   available for backward compatibility and convenience.  Supported
  35   values for :samp:`{cpu}` are
  36
  37   .. index:: mA6, mARC600
  38
  39   :samp:`arc600`
  40     Compile for ARC600.  Aliases: :option:`-mA6`, :option:`-mARC600`.
  41
  42   :samp:`arc601`
  43     Compile for ARC601.  Alias: :option:`-mARC601`.
  44
  45   :samp:`arc700`
  46     Compile for ARC700.  Aliases: :option:`-mA7`, :option:`-mARC700`.
  47     This is the default when configured with :option:`--with-cpu=arc700`.
  48
  49   :samp:`arcem`
  50     Compile for ARC EM.
  51
  52   :samp:`archs`
  53     Compile for ARC HS.
  54
  55   :samp:`em`
  56     Compile for ARC EM CPU with no hardware extensions.
  57
  58   :samp:`em4`
  59     Compile for ARC EM4 CPU.
  60
  61   :samp:`em4_dmips`
  62     Compile for ARC EM4 DMIPS CPU.
  63
  64   :samp:`em4_fpus`
  65     Compile for ARC EM4 DMIPS CPU with the single-precision floating-point
  66     extension.
  67
  68   :samp:`em4_fpuda`
  69     Compile for ARC EM4 DMIPS CPU with single-precision floating-point and
  70     double assist instructions.
  71
  72   :samp:`hs`
  73     Compile for ARC HS CPU with no hardware extensions except the atomic
  74     instructions.
  75
  76   :samp:`hs34`
  77     Compile for ARC HS34 CPU.
  78
  79   :samp:`hs38`
  80     Compile for ARC HS38 CPU.
  81
  82   :samp:`hs38_linux`
  83     Compile for ARC HS38 CPU with all hardware extensions on.
  84
  85   :samp:`hs4x`
  86     Compile for ARC HS4x CPU.
  87
  88   :samp:`hs4xd`
  89     Compile for ARC HS4xD CPU.
  90
  91   :samp:`hs4x_rel31`
  92     Compile for ARC HS4x CPU release 3.10a.
  93
  94   :samp:`arc600_norm`
  95     Compile for ARC 600 CPU with ``norm`` instructions enabled.
  96
  97   :samp:`arc600_mul32x16`
  98     Compile for ARC 600 CPU with ``norm`` and 32x16-bit multiply
  99     instructions enabled.
 100
 101   :samp:`arc600_mul64`
 102     Compile for ARC 600 CPU with ``norm`` and ``mul64`` -family
 103     instructions enabled.
 104
 105   :samp:`arc601_norm`
 106     Compile for ARC 601 CPU with ``norm`` instructions enabled.
 107
 108   :samp:`arc601_mul32x16`
 109     Compile for ARC 601 CPU with ``norm`` and 32x16-bit multiply
 110     instructions enabled.
 111
 112   :samp:`arc601_mul64`
 113     Compile for ARC 601 CPU with ``norm`` and ``mul64`` -family
 114     instructions enabled.
 115
 116   :samp:`nps400`
 117     Compile for ARC 700 on NPS400 chip.
 118
 119   :samp:`em_mini`
 120     Compile for ARC EM minimalist configuration featuring reduced register
 121     set.
 122
 123 .. option:: -mdpfp, -mdpfp-compact
 124
 125   Generate double-precision FPX instructions, tuned for the compact
 126   implementation.
 127
 128 .. option:: -mdpfp-fast
 129
 130   Generate double-precision FPX instructions, tuned for the fast
 131   implementation.
 132
 133 .. option:: -mno-dpfp-lrsr
 134
 135   Disable ``lr`` and ``sr`` instructions from using FPX extension
 136   aux registers.
 137
 138 .. option:: -mea
 139
 140   Generate extended arithmetic instructions.  Currently only
 141   ``divaw``, ``adds``, ``subs``, and ``sat16`` are
 142   supported.  Only valid for :option:`-mcpu=ARC700`.
 143
 144 .. option:: -mno-mpy
 145
 146   Do not generate ``mpy`` -family instructions for ARC700.  This option is
 147   deprecated.
 148
 149 .. option:: -mmpy
 150
 151   Default setting; overrides :option:`-mno-mpy`.
 152
 153 .. option:: -mmul32x16
 154
 155   Generate 32x16-bit multiply and multiply-accumulate instructions.
 156
 157 .. option:: -mmul64
 158
 159   Generate ``mul64`` and ``mulu64`` instructions.
 160   Only valid for :option:`-mcpu=ARC600`.
 161
 162 .. option:: -mnorm
 163
 164   Generate ``norm`` instructions.  This is the default if :option:`-mcpu=ARC700`
 165   is in effect.
 166
 167 .. option:: -mspfp, -mspfp-compact
 168
 169   Generate single-precision FPX instructions, tuned for the compact
 170   implementation.
 171
 172 .. option:: -mspfp-fast
 173
 174   Generate single-precision FPX instructions, tuned for the fast
 175   implementation.
 176
 177 .. option:: -msimd
 178
 179   Enable generation of ARC SIMD instructions via target-specific
 180   builtins.  Only valid for :option:`-mcpu=ARC700`.
 181
 182 .. option:: -msoft-float
 183
 184   This option ignored; it is provided for compatibility purposes only.
 185   Software floating-point code is emitted by default, and this default
 186   can overridden by FPX options; :option:`-mspfp`, :option:`-mspfp-compact`, or
 187   :option:`-mspfp-fast` for single precision, and :option:`-mdpfp`,
 188   :option:`-mdpfp-compact`, or :option:`-mdpfp-fast` for double precision.
 189
 190 .. option:: -mswap
 191
 192   Generate ``swap`` instructions.
 193
 194 .. option:: -matomic
 195
 196   This enables use of the locked load/store conditional extension to implement
 197   atomic memory built-in functions.  Not available for ARC 6xx or ARC
 198   EM cores.
 199
 200 .. option:: -mdiv-rem
 201
 202   Enable ``div`` and ``rem`` instructions for ARCv2 cores.
 203
 204 .. option:: -mcode-density
 205
 206   Enable code density instructions for ARC EM.
 207   This option is on by default for ARC HS.
 208
 209 .. option:: -mll64
 210
 211   Enable double load/store operations for ARC HS cores.
 212
 213 .. option:: -mtp-regno={regno}
 214
 215   Specify thread pointer register number.
 216
 217 .. option:: -mmpy-option={multo}
 218
 219   Compile ARCv2 code with a multiplier design option.  You can specify
 220   the option using either a string or numeric value for :samp:`{multo}`.
 221   :samp:`wlh1` is the default value.  The recognized values are:
 222
 223   :samp:`0` :samp:`none`
 224     No multiplier available.
 225
 226   :samp:`1` :samp:`w`
 227     16x16 multiplier, fully pipelined.
 228     The following instructions are enabled: ``mpyw`` and ``mpyuw``.
 229
 230   :samp:`2` :samp:`wlh1`
 231     32x32 multiplier, fully
 232     pipelined (1 stage).  The following instructions are additionally
 233     enabled: ``mpy``, ``mpyu``, ``mpym``, ``mpymu``, and ``mpy_s``.
 234
 235   :samp:`3` :samp:`wlh2`
 236     32x32 multiplier, fully pipelined
 237     (2 stages).  The following instructions are additionally enabled: ``mpy``,
 238     ``mpyu``, ``mpym``, ``mpymu``, and ``mpy_s``.
 239
 240   :samp:`4` :samp:`wlh3`
 241     Two 16x16 multipliers, blocking,
 242     sequential.  The following instructions are additionally enabled: ``mpy``,
 243     ``mpyu``, ``mpym``, ``mpymu``, and ``mpy_s``.
 244
 245   :samp:`5` :samp:`wlh4`
 246     One 16x16 multiplier, blocking,
 247     sequential.  The following instructions are additionally enabled: ``mpy``,
 248     ``mpyu``, ``mpym``, ``mpymu``, and ``mpy_s``.
 249
 250   :samp:`6` :samp:`wlh5`
 251     One 32x4 multiplier, blocking,
 252     sequential.  The following instructions are additionally enabled: ``mpy``,
 253     ``mpyu``, ``mpym``, ``mpymu``, and ``mpy_s``.
 254
 255   :samp:`7` :samp:`plus_dmpy`
 256     ARC HS SIMD support.
 257
 258   :samp:`8` :samp:`plus_macd`
 259     ARC HS SIMD support.
 260
 261   :samp:`9` :samp:`plus_qmacw`
 262     ARC HS SIMD support.
 263
 264     This option is only available for ARCv2 cores.
 265
 266 .. option:: -mfpu={fpu}
 267
 268   Enables support for specific floating-point hardware extensions for ARCv2
 269   cores.  Supported values for :samp:`{fpu}` are:
 270
 271   :samp:`fpus`
 272     Enables support for single-precision floating-point hardware
 273     extensions.
 274
 275   :samp:`fpud`
 276     Enables support for double-precision floating-point hardware
 277     extensions.  The single-precision floating-point extension is also
 278     enabled.  Not available for ARC EM.
 279
 280   :samp:`fpuda`
 281     Enables support for double-precision floating-point hardware
 282     extensions using double-precision assist instructions.  The single-precision
 283     floating-point extension is also enabled.  This option is
 284     only available for ARC EM.
 285
 286   :samp:`fpuda_div`
 287     Enables support for double-precision floating-point hardware
 288     extensions using double-precision assist instructions.
 289     The single-precision floating-point, square-root, and divide
 290     extensions are also enabled.  This option is
 291     only available for ARC EM.
 292
 293   :samp:`fpuda_fma`
 294     Enables support for double-precision floating-point hardware
 295     extensions using double-precision assist instructions.
 296     The single-precision floating-point and fused multiply and add
 297     hardware extensions are also enabled.  This option is
 298     only available for ARC EM.
 299
 300   :samp:`fpuda_all`
 301     Enables support for double-precision floating-point hardware
 302     extensions using double-precision assist instructions.
 303     All single-precision floating-point hardware extensions are also
 304     enabled.  This option is only available for ARC EM.
 305
 306   :samp:`fpus_div`
 307     Enables support for single-precision floating-point, square-root and divide
 308     hardware extensions.
 309
 310   :samp:`fpud_div`
 311     Enables support for double-precision floating-point, square-root and divide
 312     hardware extensions.  This option
 313     includes option :samp:`fpus_div`. Not available for ARC EM.
 314
 315   :samp:`fpus_fma`
 316     Enables support for single-precision floating-point and
 317     fused multiply and add hardware extensions.
 318
 319   :samp:`fpud_fma`
 320     Enables support for double-precision floating-point and
 321     fused multiply and add hardware extensions.  This option
 322     includes option :samp:`fpus_fma`.  Not available for ARC EM.
 323
 324   :samp:`fpus_all`
 325     Enables support for all single-precision floating-point hardware
 326     extensions.
 327
 328   :samp:`fpud_all`
 329     Enables support for all single- and double-precision floating-point
 330     hardware extensions.  Not available for ARC EM.
 331
 332 .. option:: -mirq-ctrl-saved={register-range},{blink},{lp_count}
 333
 334   Specifies general-purposes registers that the processor automatically
 335   saves/restores on interrupt entry and exit.  :samp:`{register-range}` is
 336   specified as two registers separated by a dash.  The register range
 337   always starts with ``r0``, the upper limit is ``fp`` register.
 338   :samp:`{blink}` and :samp:`{lp_count}` are optional.  This option is only
 339   valid for ARC EM and ARC HS cores.
 340
 341 .. option:: -mrgf-banked-regs={number}
 342
 343   Specifies the number of registers replicated in second register bank
 344   on entry to fast interrupt.  Fast interrupts are interrupts with the
 345   highest priority level P0.  These interrupts save only PC and STATUS32
 346   registers to avoid memory transactions during interrupt entry and exit
 347   sequences.  Use this option when you are using fast interrupts in an
 348   ARC V2 family processor.  Permitted values are 4, 8, 16, and 32.
 349
 350 .. option:: -mlpc-width={width}
 351
 352   Specify the width of the ``lp_count`` register.  Valid values for
 353   :samp:`{width}` are 8, 16, 20, 24, 28 and 32 bits.  The default width is
 354   fixed to 32 bits.  If the width is less than 32, the compiler does not
 355   attempt to transform loops in your program to use the zero-delay loop
 356   mechanism unless it is known that the ``lp_count`` register can
 357   hold the required loop-counter value.  Depending on the width
 358   specified, the compiler and run-time library might continue to use the
 359   loop mechanism for various needs.  This option defines macro
 360   ``__ARC_LPC_WIDTH__`` with the value of :samp:`{width}`.
 361
 362 .. option:: -mrf16
 363
 364   This option instructs the compiler to generate code for a 16-entry
 365   register file.  This option defines the ``__ARC_RF16__``
 366   preprocessor macro.
 367
 368 .. option:: -mbranch-index
 369
 370   Enable use of ``bi`` or ``bih`` instructions to implement jump
 371   tables.
 372
 373 The following options are passed through to the assembler, and also
 374 define preprocessor macro symbols.
 375
 376 .. Flags used by the assembler, but for which we define preprocessor
 377    macro symbols as well.
 378
 379 .. option:: -mdsp-packa
 380
 381   Passed down to the assembler to enable the DSP Pack A extensions.
 382   Also sets the preprocessor symbol ``__Xdsp_packa``.  This option is
 383   deprecated.
 384
 385 .. option:: -mdvbf
 386
 387   Passed down to the assembler to enable the dual Viterbi butterfly
 388   extension.  Also sets the preprocessor symbol ``__Xdvbf``.  This
 389   option is deprecated.
 390
 391   .. ARC700 4.10 extension instruction
 392
 393 .. option:: -mlock
 394
 395   Passed down to the assembler to enable the locked load/store
 396   conditional extension.  Also sets the preprocessor symbol
 397   ``__Xlock``.
 398
 399 .. option:: -mmac-d16
 400
 401   Passed down to the assembler.  Also sets the preprocessor symbol
 402   ``__Xxmac_d16``.  This option is deprecated.
 403
 404 .. option:: -mmac-24
 405
 406   Passed down to the assembler.  Also sets the preprocessor symbol
 407   ``__Xxmac_24``.  This option is deprecated.
 408
 409   .. ARC700 4.10 extension instruction
 410
 411 .. option:: -mrtsc
 412
 413   Passed down to the assembler to enable the 64-bit time-stamp counter
 414   extension instruction.  Also sets the preprocessor symbol
 415   ``__Xrtsc``.  This option is deprecated.
 416
 417   .. ARC700 4.10 extension instruction
 418
 419 .. option:: -mswape
 420
 421   Passed down to the assembler to enable the swap byte ordering
 422   extension instruction.  Also sets the preprocessor symbol
 423   ``__Xswape``.
 424
 425 .. option:: -mtelephony
 426
 427   Passed down to the assembler to enable dual- and single-operand
 428   instructions for telephony.  Also sets the preprocessor symbol
 429   ``__Xtelephony``.  This option is deprecated.
 430
 431 .. option:: -mxy
 432
 433   Passed down to the assembler to enable the XY memory extension.  Also
 434   sets the preprocessor symbol ``__Xxy``.
 435
 436 The following options control how the assembly code is annotated:
 437
 438 .. Assembly annotation options
 439
 440 .. option:: -misize
 441
 442   Annotate assembler instructions with estimated addresses.
 443
 444 .. option:: -mannotate-align
 445
 446   Explain what alignment considerations lead to the decision to make an
 447   instruction short or long.
 448
 449 The following options are passed through to the linker:
 450
 451 .. options passed through to the linker
 452
 453 .. option:: -marclinux
 454
 455   Passed through to the linker, to specify use of the ``arclinux`` emulation.
 456   This option is enabled by default in tool chains built for
 457   ``arc-linux-uclibc`` and ``arceb-linux-uclibc`` targets
 458   when profiling is not requested.
 459
 460 .. option:: -marclinux_prof
 461
 462   Passed through to the linker, to specify use of the
 463   ``arclinux_prof`` emulation.  This option is enabled by default in
 464   tool chains built for ``arc-linux-uclibc`` and
 465   ``arceb-linux-uclibc`` targets when profiling is requested.
 466
 467 The following options control the semantics of generated code:
 468
 469 .. semantically relevant code generation options
 470
 471 .. option:: -mlong-calls
 472
 473   Generate calls as register indirect calls, thus providing access
 474   to the full 32-bit address range.
 475
 476 .. option:: -mmedium-calls
 477
 478   Don't use less than 25-bit addressing range for calls, which is the
 479   offset available for an unconditional branch-and-link
 480   instruction.  Conditional execution of function calls is suppressed, to
 481   allow use of the 25-bit range, rather than the 21-bit range with
 482   conditional branch-and-link.  This is the default for tool chains built
 483   for ``arc-linux-uclibc`` and ``arceb-linux-uclibc`` targets.
 484
 485 .. option:: -G {num}
 486
 487   Put definitions of externally-visible data in a small data section if
 488   that data is no bigger than :samp:`{num}` bytes.  The default value of
 489   :samp:`{num}` is 4 for any ARC configuration, or 8 when we have double
 490   load/store operations.
 491
 492 .. option:: -mno-sdata
 493
 494   Do not generate sdata references.  This is the default for tool chains
 495   built for ``arc-linux-uclibc`` and ``arceb-linux-uclibc``
 496   targets.
 497
 498 .. option:: -msdata
 499
 500   Default setting; overrides :option:`-mno-sdata`.
 501
 502 .. option:: -mvolatile-cache
 503
 504   Use ordinarily cached memory accesses for volatile references.  This is the
 505   default.
 506
 507 .. option:: -mno-volatile-cache
 508
 509   Enable cache bypass for volatile references.
 510
 511 .. option:: -mvolatile-cache
 512
 513   Default setting; overrides :option:`-mno-volatile-cache`.
 514
 515 The following options fine tune code generation:
 516
 517 .. code generation tuning options
 518
 519 .. option:: -malign-call
 520
 521   Does nothing.  Preserved for backward compatibility.
 522
 523 .. option:: -mauto-modify-reg
 524
 525   Enable the use of pre/post modify with register displacement.
 526
 527 .. option:: -mbbit-peephole
 528
 529   Enable bbit peephole2.
 530
 531 .. option:: -mno-brcc
 532
 533   This option disables a target-specific pass in :samp:`arc_reorg` to
 534   generate compare-and-branch (``brcc``) instructions.
 535   It has no effect on
 536   generation of these instructions driven by the combiner pass.
 537
 538 .. option:: -mcase-vector-pcrel
 539
 540   Use PC-relative switch case tables to enable case table shortening.
 541   This is the default for :option:`-Os`.
 542
 543 .. option:: -mcompact-casesi
 544
 545   Enable compact ``casesi`` pattern.  This is the default for :option:`-Os`,
 546   and only available for ARCv1 cores.  This option is deprecated.
 547
 548 .. option:: -mno-cond-exec
 549
 550   Disable the ARCompact-specific pass to generate conditional
 551   execution instructions.
 552
 553   Due to delay slot scheduling and interactions between operand numbers,
 554   literal sizes, instruction lengths, and the support for conditional execution,
 555   the target-independent pass to generate conditional execution is often lacking,
 556   so the ARC port has kept a special pass around that tries to find more
 557   conditional execution generation opportunities after register allocation,
 558   branch shortening, and delay slot scheduling have been done.  This pass
 559   generally, but not always, improves performance and code size, at the cost of
 560   extra compilation time, which is why there is an option to switch it off.
 561   If you have a problem with call instructions exceeding their allowable
 562   offset range because they are conditionalized, you should consider using
 563   :option:`-mmedium-calls` instead.
 564
 565 .. option:: -mearly-cbranchsi
 566
 567   Enable pre-reload use of the ``cbranchsi`` pattern.
 568
 569 .. option:: -mexpand-adddi
 570
 571   Expand ``adddi3`` and ``subdi3`` at RTL generation time into
 572   ``add.f``, ``adc`` etc.  This option is deprecated.
 573
 574 .. option:: -mindexed-loads
 575
 576   Enable the use of indexed loads.  This can be problematic because some
 577   optimizers then assume that indexed stores exist, which is not
 578   the case.
 579
 580 .. option:: -mlra
 581
 582   Enable Local Register Allocation.  This is still experimental for ARC,
 583   so by default the compiler uses standard reload
 584   (i.e. :option:`-mno-lra`).
 585
 586 .. option:: -mlra-priority-none
 587
 588   Don't indicate any priority for target registers.
 589
 590 .. option:: -mlra-priority-compact
 591
 592   Indicate target register priority for ``r0`` .. ``r3`` / ``r12`` .. ``r15``.
 593
 594 .. option:: -mlra-priority-noncompact
 595
 596   Reduce target register priority for ``r0`` .. ``r3`` / ``r12`` .. ``r15``.
 597
 598 .. option:: -mmillicode
 599
 600   When optimizing for size (using :option:`-Os`), prologues and epilogues
 601   that have to save or restore a large number of registers are often
 602   shortened by using call to a special function in libgcc; this is
 603   referred to as a *millicode* call.  As these calls can pose
 604   performance issues, and/or cause linking issues when linking in a
 605   nonstandard way, this option is provided to turn on or off millicode
 606   call generation.
 607
 608 .. option:: -mcode-density-frame
 609
 610   This option enable the compiler to emit ``enter`` and ``leave``
 611   instructions.  These instructions are only valid for CPUs with
 612   code-density feature.
 613
 614 .. option:: -mmixed-code
 615
 616   Does nothing.  Preserved for backward compatibility.
 617
 618 .. option:: -mq-class
 619
 620   Ths option is deprecated.  Enable :samp:`q` instruction alternatives.
 621   This is the default for :option:`-Os`.
 622
 623 .. option:: -mRcq
 624
 625   Does nothing.  Preserved for backward compatibility.
 626
 627 .. option:: -mRcw
 628
 629   Does nothing.  Preserved for backward compatibility.
 630
 631 .. option:: -msize-level={level}
 632
 633   Fine-tune size optimization with regards to instruction lengths and alignment.
 634   The recognized values for :samp:`{level}` are:
 635
 636   :samp:`0`
 637     No size optimization.  This level is deprecated and treated like :samp:`1`.
 638
 639   :samp:`1`
 640     Short instructions are used opportunistically.
 641
 642   :samp:`2`
 643     In addition, alignment of loops and of code after barriers are dropped.
 644
 645   :samp:`3`
 646     In addition, optional data alignment is dropped, and the option Os is enabled.
 647
 648   This defaults to :samp:`3` when :option:`-Os` is in effect.  Otherwise,
 649   the behavior when this is not set is equivalent to level :samp:`1`.
 650
 651 .. option:: -mtune={cpu}
 652
 653   Set instruction scheduling parameters for :samp:`{cpu}`, overriding any implied
 654   by :option:`-mcpu=`.
 655
 656   Supported values for :samp:`{cpu}` are
 657
 658   :samp:`ARC600`
 659     Tune for ARC600 CPU.
 660
 661   :samp:`ARC601`
 662     Tune for ARC601 CPU.
 663
 664   :samp:`ARC700`
 665     Tune for ARC700 CPU with standard multiplier block.
 666
 667   :samp:`ARC700-xmac`
 668     Tune for ARC700 CPU with XMAC block.
 669
 670   :samp:`ARC725D`
 671     Tune for ARC725D CPU.
 672
 673   :samp:`ARC750D`
 674     Tune for ARC750D CPU.
 675
 676   :samp:`core3`
 677     Tune for ARCv2 core3 type CPU.  This option enable usage of
 678     ``dbnz`` instruction.
 679
 680   :samp:`release31a`
 681     Tune for ARC4x release 3.10a.
 682
 683 .. option:: -mmultcost={num}
 684
 685   Cost to assume for a multiply instruction, with :samp:`4` being equal to a
 686   normal instruction.
 687
 688 .. option:: -munalign-prob-threshold={probability}
 689
 690   Does nothing.  Preserved for backward compatibility.
 691
 692 The following options are maintained for backward compatibility, but
 693 are now deprecated and will be removed in a future release:
 694
 695 .. Deprecated options
 696
 697 .. option:: -margonaut
 698
 699   Obsolete FPX.
 700
 701 .. option:: -mbig-endian, -EB
 702
 703   Compile code for big-endian targets.  Use of these options is now
 704   deprecated.  Big-endian code is supported by configuring GCC to build
 705   ``arceb-elf32`` and ``arceb-linux-uclibc`` targets,
 706   for which big endian is the default.
 707
 708 .. option:: -mlittle-endian, -EL
 709
 710   Compile code for little-endian targets.  Use of these options is now
 711   deprecated.  Little-endian code is supported by configuring GCC to build
 712   ``arc-elf32`` and ``arc-linux-uclibc`` targets,
 713   for which little endian is the default.
 714
 715 .. option:: -mbarrel_shifter
 716
 717   Replaced by :option:`-mbarrel-shifter`.
 718
 719 .. option:: -mdpfp_compact
 720
 721   Replaced by :option:`-mdpfp-compact`.
 722
 723 .. option:: -mdpfp_fast
 724
 725   Replaced by :option:`-mdpfp-fast`.
 726
 727 .. option:: -mdsp_packa
 728
 729   Replaced by :option:`-mdsp-packa`.
 730
 731 .. option:: -mEA
 732
 733   Replaced by :option:`-mea`.
 734
 735 .. option:: -mmac_24
 736
 737   Replaced by :option:`-mmac-24`.
 738
 739 .. option:: -mmac_d16
 740
 741   Replaced by :option:`-mmac-d16`.
 742
 743 .. option:: -mspfp_compact
 744
 745   Replaced by :option:`-mspfp-compact`.
 746
 747 .. option:: -mspfp_fast
 748
 749   Replaced by :option:`-mspfp-fast`.
 750
 751 .. option:: -mtune={cpu}
 752
 753   Values :samp:`arc600`, :samp:`arc601`, :samp:`arc700` and
 754   :samp:`arc700-xmac` for :samp:`{cpu}` are replaced by :samp:`ARC600`,
 755   :samp:`ARC601`, :samp:`ARC700` and :samp:`ARC700-xmac` respectively.
 756
 757 .. option:: -multcost={num}
 758
 759   Replaced by :option:`-mmultcost`.