1 # Copyright (C) 1999-2024 Free Software Foundation, Inc.
3 # This program is free software; you can redistribute it and/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation; either version 3 of the License, or
6 # (at your option) any later version.
8 # This program is distributed in the hope that it will be useful,
9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with GCC; see the file COPYING3. If not see
15 # <http://www.gnu.org/licenses/>.
17 # Please email any bugs, comments, and/or additions to this file to:
18 # gcc-patches@gcc.gnu.org
20 # This file defines procs for determining features supported by the target.
22 # Try to compile the code given by CONTENTS into an output file of
23 # type TYPE, where TYPE is as for target_compile. Return a list
24 # whose first element contains the compiler messages and whose
25 # second element is the name of the output file.
27 # BASENAME is a prefix to use for source and output files.
28 # If ARGS is not empty, its first element is a string that
29 # should be added to the command line.
31 # Assume by default that CONTENTS is C code.
32 # Otherwise, code should contain:
33 # "/* Assembly" for assembly code,
36 # "! Fortran" for Fortran code,
38 # "// ObjC++" for ObjC++
41 # and "(* Modula-2" for Modula-2
42 # If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
43 # allow for ObjC/ObjC++ specific flags.
45 proc check_compile {basename type contents args} {
47 verbose "check_compile tool: $tool for $basename"
49 # Save additional_sources to avoid compiling testsuite's sources
50 # against check_compile's source.
51 global additional_sources
52 if [info exists additional_sources] {
53 set tmp_additional_sources "$additional_sources"
54 set additional_sources ""
57 if { [llength $args] > 0 } {
58 set options [list "additional_flags=[lindex $args 0]"]
62 # Silence "command-line option [...] is valid for [...] but not for [...]"
63 # that we may easily run into here, if more than one language is involved.
64 lappend options additional_flags=-Wno-complain-wrong-lang
66 switch -glob -- $contents {
67 "*/\\* Assembly*" { set src ${basename}[pid].S }
68 "*! Fortran*" { set src ${basename}[pid].f90 }
69 "*// C++*" { set src ${basename}[pid].cc }
70 "*// D*" { set src ${basename}[pid].d }
71 "*// ObjC++*" { set src ${basename}[pid].mm }
72 "*/\\* ObjC*" { set src ${basename}[pid].m }
73 "*// Go*" { set src ${basename}[pid].go }
74 "*// Rust*" { set src ${basename}[pid].rs }
75 "*(\\* Modula-2*" { set src ${basename}[pid].mod }
78 "objc" { set src ${basename}[pid].m }
79 "obj-c++" { set src ${basename}[pid].mm }
80 default { set src ${basename}[pid].c }
85 set compile_type $type
87 assembly { set output ${basename}[pid].s }
88 object { set output ${basename}[pid].o }
89 executable { set output ${basename}[pid].exe }
92 set output ${basename}[pid].s
93 lappend options "additional_flags=-fdump-$type"
94 set compile_type assembly
100 global compiler_flags
101 set save_compiler_flags $compiler_flags
102 set lines [${tool}_target_compile $src $output $compile_type "$options"]
103 set compiler_flags $save_compiler_flags
106 set scan_output $output
107 # Don't try folding this into the switch above; calling "glob" before the
108 # file is created won't work.
109 if [regexp "rtl-(.*)" $type dummy rtl_type] {
110 set scan_output "[glob $src.\[0-9\]\[0-9\]\[0-9\]r.$rtl_type]"
112 } elseif [regexp "tree-(.*)" $type dummy tree_type] {
113 set scan_output "[glob $src.\[0-9\]\[0-9\]\[0-9\]t.$tree_type]"
117 # Restore additional_sources.
118 if [info exists additional_sources] {
119 set additional_sources "$tmp_additional_sources"
122 return [list $lines $scan_output]
125 proc current_target_name { } {
127 if [info exists target_info(target,name)] {
128 set answer $target_info(target,name)
135 # Implement an effective-target check for property PROP by invoking
136 # the Tcl command ARGS and seeing if it returns true.
138 proc check_cached_effective_target { prop args } {
141 set target [current_target_name]
142 if {![info exists et_cache($prop,$target)]} {
143 verbose "check_cached_effective_target $prop: checking $target" 2
144 if {[string is true -strict $args] || [string is false -strict $args]} {
145 error {check_cached_effective_target condition already evaluated; did you pass [...] instead of the expected {...}?}
147 set code [catch {uplevel eval $args} result]
148 if {$code != 0 && $code != 2} {
149 return -code $code $result
151 set et_cache($prop,$target) $result
154 set value $et_cache($prop,$target)
155 verbose "check_cached_effective_target $prop: returning $value for $target" 2
159 # Implements a version of check_cached_effective_target that also takes et_index
160 # into account when creating the key for the cache.
161 proc check_cached_effective_target_indexed { prop args } {
163 set key "$et_index $prop"
164 verbose "check_cached_effective_target_index $prop: returning $key" 2
166 return [check_cached_effective_target $key [list uplevel eval $args]]
169 # Clear effective-target cache. This is useful after testing
170 # effective-target features and overriding TEST_ALWAYS_FLAGS and/or
172 # If one changes ALWAYS_CXXFLAGS or TEST_ALWAYS_FLAGS then they should
173 # do a clear_effective_target_cache at the end as the target cache can
174 # make decisions based upon the flags, and those decisions need to be
175 # redone when the flags change. An example of this is the
176 # asan_init/asan_finish pair.
178 proc clear_effective_target_cache { } {
183 # Like check_compile, but delete the output file and return true if the
184 # compiler printed no messages.
185 proc check_no_compiler_messages_nocache {args} {
186 set result [eval check_compile $args]
187 set lines [lindex $result 0]
188 set output [lindex $result 1]
189 remote_file build delete $output
190 return [string match "" $lines]
193 # Like check_no_compiler_messages_nocache, but cache the result.
194 # PROP is the property we're checking, and doubles as a prefix for
195 # temporary filenames.
196 proc check_no_compiler_messages {prop args} {
197 return [check_cached_effective_target $prop {
198 eval [list check_no_compiler_messages_nocache $prop] $args
202 # Like check_compile, but return true if the compiler printed no
203 # messages and if the contents of the output file satisfy PATTERN.
204 # If PATTERN has the form "!REGEXP", the contents satisfy it if they
205 # don't match regular expression REGEXP, otherwise they satisfy it
206 # if they do match regular expression PATTERN. (PATTERN can start
207 # with something like "[!]" if the regular expression needs to match
208 # "!" as the first character.)
210 # Delete the output file before returning. The other arguments are
211 # as for check_compile.
212 proc check_no_messages_and_pattern_nocache {basename pattern args} {
215 set result [eval [list check_compile $basename] $args]
216 set lines [lindex $result 0]
217 set output [lindex $result 1]
220 if { [string match "" $lines] } {
221 set chan [open "$output"]
222 set invert [regexp {^!(.*)} $pattern dummy pattern]
223 set ok [expr { [regexp $pattern [read $chan]] != $invert }]
227 remote_file build delete $output
231 # Like check_no_messages_and_pattern_nocache, but cache the result.
232 # PROP is the property we're checking, and doubles as a prefix for
233 # temporary filenames.
234 proc check_no_messages_and_pattern {prop pattern args} {
235 return [check_cached_effective_target $prop {
236 eval [list check_no_messages_and_pattern_nocache $prop $pattern] $args
240 # Try to compile and run an executable from code CONTENTS. Return true
241 # if the compiler reports no messages and if execution "passes" in the
242 # usual DejaGNU sense. The arguments are as for check_compile, with
243 # TYPE implicitly being "executable".
244 proc check_runtime_nocache {basename contents args} {
247 set result [eval [list check_compile $basename executable $contents] $args]
248 set lines [lindex $result 0]
249 set output [lindex $result 1]
252 if { [string match "" $lines] } {
253 # No error messages, everything is OK.
254 set result [remote_load target "./$output" "" ""]
255 set status [lindex $result 0]
256 verbose "check_runtime_nocache $basename: status is <$status>" 2
257 if { $status == "pass" } {
261 remote_file build delete $output
265 # Like check_runtime_nocache, but cache the result. PROP is the
266 # property we're checking, and doubles as a prefix for temporary
268 proc check_runtime {prop args} {
271 return [check_cached_effective_target $prop {
272 eval [list check_runtime_nocache $prop] $args
276 # Return 1 if GCC was configured with $pattern.
277 proc check_configured_with { pattern } {
280 set options [list "additional_flags=-v"]
281 set gcc_output [${tool}_target_compile "" "" "none" $options]
282 if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
283 verbose "Matched: $pattern" 2
287 verbose "Failed to match: $pattern" 2
291 ###############################
292 # proc check_weak_available { }
293 ###############################
295 # weak symbols are only supported in some configs/object formats
296 # this proc returns 1 if they're supported, 0 if they're not, or -1 if unsure
298 proc check_weak_available { } {
301 # All mips targets should support it
303 if { [ string first "mips" $target_cpu ] >= 0 } {
307 # All AIX targets should support it
309 if { [istarget *-*-aix*] } {
313 # All solaris2 targets should support it
315 if { [istarget *-*-solaris2*] } {
319 # Windows targets Cygwin and MingW32 support it
321 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
325 # nvptx (nearly) supports it
327 if { [istarget nvptx-*-*] } {
331 # pdp11 doesn't support it
333 if { [istarget pdp11*-*-*] } {
337 # VxWorks hardly supports it (vx7 RTPs only)
339 if { [istarget *-*-vxworks*] } {
343 # ELF and ECOFF support it. a.out does with gas/gld but may also with
344 # other linkers, so we should try it
346 set objformat [gcc_target_object_format]
354 unknown { return -1 }
359 # return options to add to enable weak undefined symbols.
361 proc add_options_for_weak_undefined { flags } {
362 if { [istarget *-*-darwin*] } {
363 lappend flags "-Wl,-undefined,dynamic_lookup"
364 if { [istarget *-*-darwin\[89\]*] } {
365 lappend flags "-Wl,-flat_namespace"
371 # return 1 if weak undefined symbols are supported.
373 proc check_effective_target_weak_undefined { } {
374 if { [istarget hppa*-*-hpux*] } {
377 return [check_runtime weak_undefined {
378 extern void foo () __attribute__((weak));
379 int main (void) { if (foo) return 1; return 0; }
380 } [add_options_for_weak_undefined ""]]
383 ###############################
384 # proc check_weak_override_available { }
385 ###############################
387 # Like check_weak_available, but return 0 if weak symbol definitions
388 # cannot be overridden.
390 proc check_weak_override_available { } {
391 if { [istarget *-*-mingw*] } {
394 return [check_weak_available]
397 # Return 1 if VMA is equal to LMA for the .data section, 0
398 # otherwise. Cache the result.
400 proc check_effective_target_vma_equals_lma { } {
403 return [check_cached_effective_target vma_equals_lma {
404 set src vma_equals_lma[pid].c
405 set exe vma_equals_lma[pid].exe
406 verbose "check_effective_target_vma_equals_lma compiling testfile $src" 2
407 set f [open $src "w"]
408 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
409 puts $f "int foo = 42; void main() {}"
411 set lines [${tool}_target_compile $src $exe executable ""]
414 if [string match "" $lines] then {
417 set objdump_name [find_binutils_prog objdump]
418 set output [remote_exec host "$objdump_name" "--section-headers --section=.data $exe"]
419 set output [lindex $output 1]
421 remote_file build delete $exe
423 # Example output of objdump:
424 #vma_equals_lma9059.exe: file format elf32-littlearm
427 #Idx Name Size VMA LMA File off Algn
428 # 6 .data 00000558 20000000 08002658 00020000 2**3
429 # CONTENTS, ALLOC, LOAD, DATA
431 # Capture LMA and VMA columns for .data section
432 if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy vma lma ] {
433 verbose "Could not parse objdump output" 2
436 return [string equal $vma $lma]
439 remote_file build delete $exe
440 verbose "Could not determine if VMA is equal to LMA. Assuming not equal." 2
446 # The "noinit" attribute is only supported by some targets.
447 # This proc returns 1 if it's supported, 0 if it's not.
449 proc check_effective_target_noinit { } {
450 if { [istarget arm*-*-eabi]
451 || [istarget msp430-*-*] } {
458 # The "persistent" attribute is only supported by some targets.
459 # This proc returns 1 if it's supported, 0 if it's not.
461 proc check_effective_target_persistent { } {
462 if { [istarget arm*-*-eabi]
463 || [istarget msp430-*-*] } {
470 ###############################
471 # proc check_visibility_available { what_kind }
472 ###############################
474 # The visibility attribute is only support in some object formats
475 # This proc returns 1 if it is supported, 0 if not.
476 # The argument is the kind of visibility, default/protected/hidden/internal.
478 proc check_visibility_available { what_kind } {
479 if [string match "" $what_kind] { set what_kind "hidden" }
481 return [check_no_compiler_messages visibility_available_$what_kind object "
482 void f() __attribute__((visibility(\"$what_kind\")));
487 ###############################
488 # proc check_alias_available { }
489 ###############################
491 # Determine if the target toolchain supports the alias attribute.
493 # Returns 2 if the target supports aliases. Returns 1 if the target
494 # only supports weak aliased. Returns 0 if the target does not
495 # support aliases at all. Returns -1 if support for aliases could not
498 proc check_alias_available { } {
501 return [check_cached_effective_target alias_available {
504 verbose "check_alias_available compiling testfile $src" 2
505 set f [open $src "w"]
506 # Compile a small test program. The definition of "g" is
507 # necessary to keep the Solaris assembler from complaining
509 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
510 puts $f "void g() {} void f() __attribute__((alias(\"g\")));"
512 set lines [${tool}_target_compile $src $obj object ""]
514 remote_file build delete $obj
516 if [string match "" $lines] then {
517 # No error messages, everything is OK.
520 if [regexp "alias definitions not supported" $lines] {
521 verbose "check_alias_available target does not support aliases" 2
523 set objformat [gcc_target_object_format]
525 if { $objformat == "elf" } {
526 verbose "check_alias_available but target uses ELF format, so it ought to" 2
532 if [regexp "only weak aliases are supported" $lines] {
533 verbose "check_alias_available target supports only weak aliases" 2
543 # Returns 1 if the target toolchain supports strong aliases, 0 otherwise.
545 proc check_effective_target_alias { } {
546 if { [check_alias_available] < 2 } {
553 # Returns 1 if the target uses the ELF object format, 0 otherwise.
555 proc check_effective_target_elf { } {
556 if { [gcc_target_object_format] == "elf" } {
563 # Returns 1 if the target toolchain supports ifunc, 0 otherwise.
565 proc check_ifunc_available { } {
566 return [check_no_compiler_messages ifunc_available object {
571 typedef void F (void);
572 F* g (void) { return &f_; }
573 void f () __attribute__ ((ifunc ("g")));
580 # Returns true if --gc-sections is supported on the target.
582 proc check_gc_sections_available { } {
585 return [check_cached_effective_target gc_sections_available {
586 # Some targets don't support gc-sections despite whatever's
587 # advertised by ld's options.
588 if { [istarget alpha*-*-*]
589 || [istarget ia64-*-*] } {
593 # elf2flt uses -q (--emit-relocs), which is incompatible with
595 if { [board_info target exists ldflags]
596 && [regexp " -elf2flt\[ =\]" " [board_info target ldflags] "] } {
600 # VxWorks kernel modules are relocatable objects linked with -r,
601 # while RTP executables are linked with -q (--emit-relocs).
602 # Both of these options are incompatible with --gc-sections.
603 if { [istarget *-*-vxworks*] } {
607 # Check if the ld used by gcc supports --gc-sections.
608 set options [list "additional_flags=-print-prog-name=ld"]
609 set gcc_ld [lindex [${tool}_target_compile "" "" "none" $options] 0]
610 set ld_output [remote_exec host "$gcc_ld" "--help"]
611 if { [ string first "--gc-sections" $ld_output ] >= 0 } {
619 # Returns 1 if "dot" is supported on the host.
621 proc check_dot_available { } {
622 verbose "check_dot_available" 2
624 set status [remote_exec host "dot" "-V"]
625 verbose " status: $status" 2
626 if { [lindex $status 0] != 0 } {
632 # Return 1 if according to target_info struct and explicit target list
633 # target is supposed to support trampolines.
635 proc check_effective_target_trampolines { } {
636 if [target_info exists gcc,no_trampolines] {
639 if { [istarget avr-*-*]
640 || [istarget msp430-*-*]
641 || [istarget nvptx-*-*]
642 || [istarget pru-*-*]
643 || [istarget bpf-*-*] } {
649 # Return 1 if target has limited stack size.
651 proc check_effective_target_stack_size { } {
652 # For nvptx target, stack size limits are relevant for execution only.
653 if { [istarget nvptx-*-*] } {
654 # Find 'dg-do-what' in an outer frame.
657 upvar $level dg-do-what dg-do-what
658 if [info exists dg-do-what] then break
661 verbose "check_effective_target_stack_size: found dg-do-what at level $level" 2
663 if { ![string equal [lindex ${dg-do-what} 0] run] } {
668 if [target_info exists gcc,stack_size] {
674 # Return the value attribute of an effective target, otherwise return 0.
676 proc dg-effective-target-value { effective_target } {
677 if { "$effective_target" == "stack_size" } {
678 if [check_effective_target_stack_size] {
679 return [target_info gcc,stack_size]
686 # Return 1 if signal.h is supported.
688 proc check_effective_target_signal { } {
689 if [target_info exists gcc,signal_suppress] {
695 # Return 1 if according to target_info struct and explicit target list
696 # target disables -fdelete-null-pointer-checks. Targets should return 0
697 # if they simply default to -fno-delete-null-pointer-checks but obey
698 # -fdelete-null-pointer-checks when passed explicitly (and tests that
699 # depend on this option should do that).
701 proc check_effective_target_keeps_null_pointer_checks { } {
702 if [target_info exists keeps_null_pointer_checks] {
705 if { [istarget msp430-*-*]
706 || [istarget avr-*-*] } {
712 # Return the autofdo profile wrapper
714 # Linux by default allows 516KB of perf event buffers
715 # in /proc/sys/kernel/perf_event_mlock_kb
716 # Each individual perf tries to grab it
717 # This causes problems with parallel test suite runs. Instead
718 # limit us to 8 pages (32K), which should be good enough
719 # for the small test programs. With the default settings
720 # this allows parallelism of 16 and higher of parallel gcc-auto-profile
721 proc profopt-perf-wrapper { } {
723 return "$srcdir/../config/i386/gcc-auto-profile --all -m8 "
726 # Return true if profiling is supported on the target.
728 proc check_profiling_available { test_what } {
729 verbose "Profiling argument is <$test_what>" 1
731 # These conditions depend on the argument so examine them before
732 # looking at the cache variable.
734 # Tree profiling requires TLS runtime support.
735 if { $test_what == "-fprofile-generate" } {
736 if { ![check_effective_target_tls_runtime] } {
741 if { $test_what == "-fauto-profile" } {
742 if { !([istarget i?86-*-linux*] || [istarget x86_64-*-linux*]) } {
743 verbose "autofdo only supported on linux"
746 # not cross compiling?
748 verbose "autofdo not supported for non native builds"
751 set event [profopt-perf-wrapper]
753 verbose "autofdo not supported"
757 set status [remote_exec host "$srcdir/../config/i386/gcc-auto-profile" "-m8 true -v >/dev/null"]
758 if { [lindex $status 0] != 0 } {
759 verbose "autofdo not supported because perf does not work"
763 # no good way to check this in advance -- check later instead.
764 #set status [remote_exec host "create_gcov" "2>/dev/null"]
765 #if { [lindex $status 0] != 255 } {
766 # verbose "autofdo not supported due to missing create_gcov"
771 # Support for -p on solaris2 relies on mcrt1.o which comes with the
772 # vendor compiler. We cannot reliably predict the directory where the
773 # vendor compiler (and thus mcrt1.o) is installed so we can't
774 # necessarily find mcrt1.o even if we have it.
775 if { [istarget *-*-solaris2*] && $test_what == "-p" } {
779 # We don't yet support profiling for MIPS16.
780 if { [istarget mips*-*-*]
781 && ![check_effective_target_nomips16]
782 && ($test_what == "-p" || $test_what == "-pg") } {
786 # MinGW does not support -p.
787 if { [istarget *-*-mingw*] && $test_what == "-p" } {
791 # cygwin does not support -p.
792 if { [istarget *-*-cygwin*] && $test_what == "-p" } {
796 # uClibc does not have gcrt1.o.
797 if { [check_effective_target_uclibc]
798 && ($test_what == "-p" || $test_what == "-pg") } {
802 # Now examine the cache variable.
803 set profiling_working \
804 [check_cached_effective_target profiling_available {
805 # Some targets don't have any implementation of __bb_init_func or are
806 # missing other needed machinery.
807 if {[istarget aarch64*-*-elf]
808 || [istarget am3*-*-linux*]
809 || [istarget amdgcn-*-*]
810 || [istarget arm*-*-eabi*]
811 || [istarget arm*-*-elf]
812 || [istarget arm*-*-symbianelf*]
813 || [istarget avr-*-*]
814 || [istarget bfin-*-*]
815 || [istarget cris-*-*]
816 || [istarget csky-*-elf*]
817 || [istarget fido-*-elf]
818 || [istarget h8300-*-*]
819 || [istarget lm32-*-*]
820 || [istarget m32c-*-elf]
821 || [istarget m68k-*-elf]
822 || [istarget m68k-*-uclinux*]
823 || [istarget mips*-*-elf*]
824 || [istarget mmix-*-*]
825 || [istarget mn10300-*-elf*]
826 || [istarget moxie-*-elf*]
827 || [istarget msp430-*-*]
828 || [istarget nds32*-*-elf]
829 || [istarget nios2-*-elf]
830 || [istarget nvptx-*-*]
831 || [istarget powerpc-*-eabi*]
832 || [istarget powerpc-*-elf]
833 || [istarget pru-*-*]
835 || [istarget tic6x-*-elf]
836 || [istarget visium-*-*]
837 || [istarget xstormy16-*]
838 || [istarget xtensa*-*-elf]
839 || [istarget *-*-rtems*]
840 || [istarget *-*-vxworks*] } {
847 # -pg link test result can't be cached since it may change between
849 if { $profiling_working == 1
850 && ![check_no_compiler_messages_nocache profiling executable {
851 int main() { return 0; } } "-pg"] } {
852 set profiling_working 0
855 return $profiling_working
858 # Check to see if a target is "freestanding". This is as per the definition
859 # in Section 4 of C99 standard. Effectively, it is a target which supports no
860 # extra headers or libraries other than what is considered essential.
861 proc check_effective_target_freestanding { } {
862 if { [istarget nvptx-*-*] } {
868 # Check to see that file I/O functions are available.
869 proc check_effective_target_fileio { } {
870 return [check_no_compiler_messages fileio_available executable {
873 char *n = tmpnam (NULL);
874 FILE *f = fopen (n, "w");
881 # Return 1 if target has packed layout of structure members by
882 # default, 0 otherwise. Note that this is slightly different than
883 # whether the target has "natural alignment": both attributes may be
886 proc check_effective_target_default_packed { } {
887 return [check_no_compiler_messages default_packed assembly {
888 struct x { char a; long b; } c;
889 int s[sizeof (c) == sizeof (char) + sizeof (long) ? 1 : -1];
893 # Return 1 if target has PCC_BITFIELD_TYPE_MATTERS defined. See
894 # documentation, where the test also comes from.
896 proc check_effective_target_pcc_bitfield_type_matters { } {
897 # PCC_BITFIELD_TYPE_MATTERS isn't just about unnamed or empty
898 # bitfields, but let's stick to the example code from the docs.
899 return [check_no_compiler_messages pcc_bitfield_type_matters assembly {
900 struct foo1 { char x; char :0; char y; };
901 struct foo2 { char x; int :0; char y; };
902 int s[sizeof (struct foo1) != sizeof (struct foo2) ? 1 : -1];
906 # Add to FLAGS all the target-specific flags needed to use thread-local storage.
908 proc add_options_for_tls { flags } {
909 # On AIX, __tls_get_addr/___tls_get_addr only lives in
910 # libthread, so always pass -pthread for native TLS.
911 # Need to duplicate native TLS check from
912 # check_effective_target_tls_native to avoid recursion.
913 if { ([istarget powerpc-ibm-aix*]) &&
914 [check_no_messages_and_pattern tls_native "!emutls" assembly {
916 int f (void) { return i; }
917 void g (int j) { i = j; }
919 return "-pthread [g++_link_flags [get_multilibs "-pthread"] ] $flags "
924 # Return 1 if indirect jumps are supported, 0 otherwise.
926 proc check_effective_target_indirect_jumps {} {
927 if { [istarget nvptx-*-*] || [istarget bpf-*-*] } {
933 # Return 1 if nonlocal goto is supported, 0 otherwise.
935 proc check_effective_target_nonlocal_goto {} {
936 if { [istarget nvptx-*-*] || [istarget bpf-*-*] } {
942 # Return 1 if global constructors are supported, 0 otherwise.
944 proc check_effective_target_global_constructor {} {
945 if { [istarget nvptx-*-*]
946 || [istarget bpf-*-*] } {
952 # Return 1 if taking label values is supported, 0 otherwise.
954 proc check_effective_target_label_values {} {
955 if { [istarget nvptx-*-*] || [target_info exists gcc,no_label_values] } {
962 # Return 1 if builtin_return_address and builtin_frame_address are
963 # supported, 0 otherwise.
965 proc check_effective_target_return_address {} {
966 if { [istarget nvptx-*-*] } {
969 # No notion of return address in eBPF.
970 if { [istarget bpf-*-*] } {
973 # It could be supported on amdgcn, but isn't yet.
974 if { [istarget amdgcn*-*-*] } {
980 # Return 1 if the assembler does not verify function types against
981 # calls, 0 otherwise. Such verification will typically show up problems
982 # with K&R C function declarations.
984 proc check_effective_target_untyped_assembly {} {
985 if { [istarget nvptx-*-*] } {
991 # Return 1 if alloca is supported, 0 otherwise.
993 proc check_effective_target_alloca {} {
994 if { [istarget bpf-*-*] } {
997 if { [istarget nvptx-*-*] } {
998 return [check_no_compiler_messages alloca assembly {
1000 void g (int n) { f (__builtin_alloca (n)); }
1006 # Return 1 if thread local storage (TLS) is supported, 0 otherwise.
1008 proc check_effective_target_tls {} {
1009 return [check_no_compiler_messages tls assembly {
1011 int f (void) { return i; }
1012 void g (int j) { i = j; }
1016 # Return 1 if *native* thread local storage (TLS) is supported, 0 otherwise.
1018 proc check_effective_target_tls_native {} {
1019 # VxWorks uses emulated TLS machinery, but with non-standard helper
1020 # functions, so we fail to automatically detect it.
1021 if { [istarget *-*-vxworks*] } {
1025 return [check_no_messages_and_pattern tls_native "!emutls" assembly {
1027 int f (void) { return i; }
1028 void g (int j) { i = j; }
1032 # Return 1 if *emulated* thread local storage (TLS) is supported, 0 otherwise.
1034 proc check_effective_target_tls_emulated {} {
1035 # VxWorks uses emulated TLS machinery, but with non-standard helper
1036 # functions, so we fail to automatically detect it.
1037 if { [istarget *-*-vxworks*] } {
1041 return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
1043 int f (void) { return i; }
1044 void g (int j) { i = j; }
1048 # Return 1 if TLS executables can run correctly, 0 otherwise.
1050 proc check_effective_target_tls_runtime {} {
1051 return [check_runtime tls_runtime {
1052 __thread int thr __attribute__((tls_model("global-dynamic"))) = 0;
1053 int main (void) { return thr; }
1054 } [add_options_for_tls ""]]
1057 # Return 1 if atomic compare-and-swap is supported on 'int'
1059 proc check_effective_target_cas_char {} {
1060 return [check_no_compiler_messages cas_char assembly {
1061 #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
1067 proc check_effective_target_cas_int {} {
1068 return [check_no_compiler_messages cas_int assembly {
1069 #if __INT_MAX__ == 0x7fff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
1071 #elif __INT_MAX__ == 0x7fffffff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
1079 # Return 1 if -ffunction-sections is supported, 0 otherwise.
1081 proc check_effective_target_function_sections {} {
1082 # Darwin has its own scheme and silently accepts -ffunction-sections.
1083 if { [istarget *-*-darwin*] } {
1087 return [check_no_compiler_messages functionsections assembly {
1089 } "-ffunction-sections"]
1092 # Return 1 if instruction scheduling is available, 0 otherwise.
1094 proc check_effective_target_scheduling {} {
1095 return [check_no_compiler_messages scheduling object {
1097 } "-fschedule-insns"]
1100 # Return 1 if trapping arithmetic is available, 0 otherwise.
1102 proc check_effective_target_trapping {} {
1103 return [check_no_compiler_messages trapping object {
1104 int add (int a, int b) { return a + b; }
1108 # Return 1 if compilation with -fgraphite is error-free for trivial
1109 # code, 0 otherwise.
1111 proc check_effective_target_fgraphite {} {
1112 return [check_no_compiler_messages fgraphite object {
1117 # Return 1 if compiled with --enable-offload-targets=
1118 # This affects host compilation as ENABLE_OFFLOAD then evaluates to true.
1119 proc check_effective_target_offloading_enabled {} {
1120 return [check_configured_with "--enable-offload-targets"]
1123 # Return 1 if compilation with -fopenacc is error-free for trivial
1124 # code, 0 otherwise.
1126 proc check_effective_target_fopenacc {} {
1127 # nvptx/amdgcn can be built with the device-side bits of openacc, but it
1128 # does not make sense to test it as an openacc host.
1129 if [istarget nvptx-*-*] { return 0 }
1130 if [istarget amdgcn-*-*] { return 0 }
1132 return [check_no_compiler_messages fopenacc object {
1137 # Return 1 if compilation with -fopenmp is error-free for trivial
1138 # code, 0 otherwise.
1140 proc check_effective_target_fopenmp {} {
1141 # nvptx/amdgcn can be built with the device-side bits of libgomp, but it
1142 # does not make sense to test it as an openmp host.
1143 if [istarget nvptx-*-*] { return 0 }
1144 if [istarget amdgcn-*-*] { return 0 }
1146 return [check_no_compiler_messages fopenmp object {
1151 # Return 1 if compilation with -fgnu-tm is error-free for trivial
1152 # code, 0 otherwise.
1154 proc check_effective_target_fgnu_tm {} {
1155 return [check_no_compiler_messages fgnu_tm object {
1160 # Return 1 if the target supports mmap, 0 otherwise.
1162 proc check_effective_target_mmap {} {
1163 return [check_function_available "mmap"]
1166 # Return 1 if the target supports sysconf, 0 otherwise.
1168 proc check_effective_target_sysconf {} {
1169 # VxWorks has sysconf in rtp mode only, but our way to test can't
1170 # tell kernel mode doesn't, as we're doing partial links for
1171 # kernel modules. We can tell by checking for a declaration, or
1172 # for some sysconf parm, because configurations that don't offer
1173 # sysconf don't have either.
1174 if { [istarget *-*-vxworks*] } {
1175 return [check_no_compiler_messages sysconfdecl assembly {
1177 int f() { return sysconf(_SC_PAGESIZE); }
1180 return [check_function_available "sysconf"]
1183 # Return 1 if the target supports dlopen, 0 otherwise.
1184 proc check_effective_target_dlopen {} {
1185 return [check_no_compiler_messages dlopen executable {
1187 int main(void) { dlopen ("dummy.so", RTLD_NOW); }
1188 } [add_options_for_dlopen ""]]
1191 proc add_options_for_dlopen { flags } {
1192 return "$flags -ldl"
1195 # Return 1 if the target supports clone, 0 otherwise.
1196 proc check_effective_target_clone {} {
1197 return [check_function_available "clone"]
1200 # Return 1 if the target supports posix_memalign, 0 otherwise.
1201 proc check_effective_target_posix_memalign {} {
1202 if { [istarget *-*-vxworks*] } {
1203 # VxWorks doesn't have posix_memalign but our way to test
1204 # can't tell as we're doing partial links for kernel modules.
1207 return [check_function_available "posix_memalign"]
1210 # Return 1 if the target supports setrlimit, 0 otherwise.
1211 proc check_effective_target_setrlimit {} {
1212 # Darwin has non-posix compliant RLIMIT_AS
1213 if { [istarget *-*-darwin*] } {
1216 return [check_function_available "setrlimit"]
1219 # Return 1 if the target supports gettimeofday, 0 otherwise.
1220 proc check_effective_target_gettimeofday {} {
1221 return [check_function_available "gettimeofday"]
1224 # Return 1 if the target supports swapcontext, 0 otherwise.
1225 proc check_effective_target_swapcontext {} {
1226 return [check_no_compiler_messages swapcontext executable {
1227 #include <ucontext.h>
1230 ucontext_t orig_context,child_context;
1231 if (swapcontext(&child_context, &orig_context) < 0) { }
1236 # Return 1 if the target supports POSIX threads, 0 otherwise.
1237 proc check_effective_target_pthread {} {
1238 return [check_no_compiler_messages pthread object {
1239 #include <pthread.h>
1244 # Return 1 if the target supports both Unix and internet sockets, 0 otherwise.
1245 proc check_effective_target_sockets {} {
1246 return [check_no_compiler_messages socket executable {
1247 #include <sys/socket.h>
1249 #include <netinet/in.h>
1251 socket(AF_UNIX, SOCK_STREAM, 0);
1252 socket(AF_INET, SOCK_DGRAM, 0);
1258 # Return 1 if compilation with -mpe-aligned-commons is error-free
1259 # for trivial code, 0 otherwise.
1261 proc check_effective_target_pe_aligned_commons {} {
1262 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
1263 return [check_no_compiler_messages pe_aligned_commons object {
1265 } "-mpe-aligned-commons"]
1270 # Return 1 if the target supports -static
1271 proc check_effective_target_static {} {
1272 if { [istarget arm*-*-uclinuxfdpiceabi] } {
1275 return [check_no_compiler_messages static executable {
1276 int main (void) { return 0; }
1280 # Return 1 if the target supports -fstack-protector
1281 proc check_effective_target_fstack_protector {} {
1282 if { [istarget hppa*-*-*] } {
1285 return [check_runtime fstack_protector {
1287 int main (int argc, char *argv[]) {
1289 return !strcpy (buf, strrchr (argv[0], '/'));
1291 } "-fstack-protector"]
1294 # Return 1 if the target supports -fstack-check or -fstack-check=$stack_kind
1295 proc check_stack_check_available { stack_kind } {
1296 if [string match "" $stack_kind] then {
1297 set stack_opt "-fstack-check"
1298 } else { set stack_opt "-fstack-check=$stack_kind" }
1300 return [check_no_compiler_messages stack_check_$stack_kind executable {
1301 int main (void) { return 0; }
1305 # Return 1 if the target supports stack scrubbing.
1306 proc check_effective_target_strub {} {
1307 # strub is not supported on AIX.
1308 if { [istarget powerpc*-*-aix*] } {
1311 return [check_no_compiler_messages strub assembly {
1312 void __attribute__ ((__strub__)) fn (void) {}
1316 # Return 1 if compilation with -freorder-blocks-and-partition is error-free
1317 # for trivial code, 0 otherwise. As some targets (ARM for example) only
1318 # warn when -fprofile-use is also supplied we test that combination too.
1320 proc check_effective_target_freorder {} {
1321 if { [check_no_compiler_messages freorder object {
1323 } "-freorder-blocks-and-partition"]
1324 && [check_no_compiler_messages fprofile_use_freorder object {
1326 } "-fprofile-use -freorder-blocks-and-partition -Wno-missing-profile"] } {
1332 # Return 1 if -fpic and -fPIC are supported, as in no warnings or errors
1333 # emitted, 0 otherwise. Whether a shared library can actually be built is
1334 # out of scope for this test.
1336 proc check_effective_target_fpic { } {
1337 # Note that M68K has a multilib that supports -fpic but not
1338 # -fPIC, so we need to check both. We test with a program that
1339 # requires GOT references.
1340 foreach arg {fpic fPIC} {
1341 if [check_no_compiler_messages $arg object {
1342 extern int foo (void); extern int bar;
1343 int baz (void) { return foo () + bar; }
1351 # On AArch64, if -fpic is not supported, then we will fall back to -fPIC
1352 # silently. So, we can't rely on above "check_effective_target_fpic" as it
1353 # assumes compiler will give warning if -fpic not supported. Here we check
1354 # whether binutils supports those new -fpic relocation modifiers, and assume
1355 # -fpic is supported if there is binutils support. GCC configuration will
1356 # enable -fpic for AArch64 in this case.
1358 # "check_effective_target_aarch64_small_fpic" is dedicated for checking small
1359 # memory model -fpic relocation types.
1361 proc check_effective_target_aarch64_small_fpic { } {
1362 if { [istarget aarch64*-*-*] } {
1363 return [check_no_compiler_messages aarch64_small_fpic object {
1364 void foo (void) { asm ("ldr x0, [x2, #:gotpage_lo15:globalsym]"); }
1371 # On AArch64, instruction sequence for TLS LE under -mtls-size=32 will utilize
1372 # the relocation modifier "tprel_g0_nc" together with MOVK, it's only supported
1373 # in binutils since 2015-03-04 as PR gas/17843.
1375 # This test directive make sure binutils support all features needed by TLS LE
1376 # under -mtls-size=32 on AArch64.
1378 proc check_effective_target_aarch64_tlsle32 { } {
1379 if { [istarget aarch64*-*-*] } {
1380 return [check_no_compiler_messages aarch64_tlsle32 object {
1381 void foo (void) { asm ("movk x1,#:tprel_g0_nc:t1"); }
1388 # Return 1 if -shared is supported, as in no warnings or errors
1389 # emitted, 0 otherwise.
1391 proc check_effective_target_shared { } {
1392 # Note that M68K has a multilib that supports -fpic but not
1393 # -fPIC, so we need to check both. We test with a program that
1394 # requires GOT references.
1395 return [check_no_compiler_messages shared executable {
1396 extern int foo (void); extern int bar;
1397 int baz (void) { return foo () + bar; }
1401 # Return 1 if -pie, -fpie and -fPIE are supported, 0 otherwise.
1403 proc check_effective_target_pie { } {
1404 if { [istarget *-*-darwin\[912\]*]
1405 || [istarget *-*-dragonfly*]
1406 || [istarget *-*-freebsd*]
1407 || [istarget *-*-linux*]
1408 || [istarget arm*-*-uclinuxfdpiceabi]
1409 || [istarget *-*-gnu*]
1410 || [istarget *-*-amdhsa]} {
1413 if { [istarget *-*-solaris2.1\[1-9\]*] } {
1414 # Full PIE support was added in Solaris 11.3, but gcc errors out
1415 # if missing, so check for that.
1416 return [check_no_compiler_messages pie executable {
1417 int main (void) { return 0; }
1423 # Return true if the target supports -mpaired-single (as used on MIPS).
1425 proc check_effective_target_mpaired_single { args } {
1426 return [check_no_compiler_messages mpaired_single object {
1431 # Return true if the target has access to FPU instructions.
1433 proc check_effective_target_hard_float { } {
1434 # This should work on cores that only have single-precision,
1435 # and should also correctly handle legacy cores that had thumb1 and
1436 # lacked FP support for that, but had it in Arm state.
1437 if { [istarget arm*-*-*] } {
1438 return [check_no_compiler_messages hard_float assembly {
1440 #error __arm_soft_float
1445 if { [istarget loongarch*-*-*] } {
1446 return [check_no_compiler_messages hard_float assembly {
1447 #if (defined __loongarch_soft_float)
1448 #error __loongarch_soft_float
1453 if { [istarget mips*-*-*] } {
1454 return [check_no_compiler_messages hard_float assembly {
1455 #if (defined __mips_soft_float || defined __mips16)
1456 #error __mips_soft_float || __mips16
1461 # This proc is actually checking the availabilty of FPU
1462 # support for doubles, so on the RX we must fail if the
1463 # 64-bit double multilib has been selected.
1464 if { [istarget rx-*-*] } {
1466 # return [check_no_compiler_messages hard_float assembly {
1467 #if defined __RX_64_BIT_DOUBLES__
1468 #error __RX_64_BIT_DOUBLES__
1473 # The generic test doesn't work for C-SKY because some cores have
1474 # hard float for single precision only.
1475 if { [istarget csky*-*-*] } {
1476 return [check_no_compiler_messages hard_float assembly {
1477 #if defined __csky_soft_float__
1478 #error __csky_soft_float__
1483 # The generic test equates hard_float with "no call for adding doubles".
1484 return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
1485 double a (double b, double c) { return b + c; }
1489 # Return true if the target is a 64-bit MIPS target.
1491 proc check_effective_target_mips64 { } {
1492 return [check_no_compiler_messages mips64 assembly {
1499 # Return true if the target is a MIPS target that does not produce
1502 proc check_effective_target_nomips16 { } {
1503 return [check_no_compiler_messages nomips16 object {
1507 /* A cheap way of testing for -mflip-mips16. */
1508 void foo (void) { asm ("addiu $20,$20,1"); }
1509 void bar (void) { asm ("addiu $20,$20,1"); }
1514 # Add the options needed for MIPS16 function attributes. At the moment,
1515 # we don't support MIPS16 PIC.
1517 proc add_options_for_mips16_attribute { flags } {
1518 return "$flags -mno-abicalls -fno-pic -DMIPS16=__attribute__((mips16))"
1521 # Return true if we can force a mode that allows MIPS16 code generation.
1522 # We don't support MIPS16 PIC, and only support MIPS16 -mhard-float
1525 proc check_effective_target_mips16_attribute { } {
1526 return [check_no_compiler_messages mips16_attribute assembly {
1530 #if defined __mips_hard_float \
1531 && (!defined _ABIO32 || _MIPS_SIM != _ABIO32) \
1532 && (!defined _ABIO64 || _MIPS_SIM != _ABIO64)
1533 #error __mips_hard_float && (!_ABIO32 || !_ABIO64)
1535 } [add_options_for_mips16_attribute ""]]
1538 # Return 1 if the target supports long double larger than double when
1539 # using the new ABI, 0 otherwise.
1541 proc check_effective_target_mips_newabi_large_long_double { } {
1542 return [check_no_compiler_messages mips_newabi_large_long_double object {
1543 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
1547 # Return true if the target is a MIPS target that has access
1548 # to the LL and SC instructions.
1550 proc check_effective_target_mips_llsc { } {
1551 if { ![istarget mips*-*-*] } {
1554 # Assume that these instructions are always implemented for
1555 # non-elf* targets, via emulation if necessary.
1556 if { ![istarget *-*-elf*] } {
1559 # Otherwise assume LL/SC support for everything but MIPS I.
1560 return [check_no_compiler_messages mips_llsc assembly {
1567 # Return true if the target is a MIPS target that uses in-place relocations.
1569 proc check_effective_target_mips_rel { } {
1570 if { ![istarget mips*-*-*] } {
1573 return [check_no_compiler_messages mips_rel object {
1574 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1575 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1576 #error _ABIN32 && (_ABIN32 || _ABI64)
1581 # Return true if the target is a MIPS target that uses the EABI.
1583 proc check_effective_target_mips_eabi { } {
1584 if { ![istarget mips*-*-*] } {
1587 return [check_no_compiler_messages mips_eabi object {
1594 # Return 1 if the current multilib does not generate PIC by default.
1596 proc check_effective_target_nonpic { } {
1597 return [check_no_compiler_messages nonpic assembly {
1604 # Return 1 if the current multilib generates PIE by default.
1606 proc check_effective_target_pie_enabled { } {
1607 return [check_no_compiler_messages pie_enabled assembly {
1614 # Return 1 if the target generates -fstack-protector by default.
1616 proc check_effective_target_fstack_protector_enabled {} {
1617 return [ check_no_compiler_messages fstack_protector_enabled assembly {
1618 #if !defined(__SSP__) && !defined(__SSP_ALL__) && \
1619 !defined(__SSP_STRONG__) && !defined(__SSP_EXPICIT__)
1625 # Return 1 if the target does not use a status wrapper.
1627 proc check_effective_target_unwrapped { } {
1628 if { [target_info needs_status_wrapper] != "" \
1629 && [target_info needs_status_wrapper] != "0" } {
1635 # Return true if iconv is supported on the target. In particular IBM1047.
1637 proc check_iconv_available { test_what } {
1640 # If the tool configuration file has not set libiconv, try "-liconv"
1641 if { ![info exists libiconv] } {
1642 set libiconv "-liconv"
1644 set test_what [lindex $test_what 1]
1645 return [check_runtime_nocache $test_what [subst {
1651 cd = iconv_open ("$test_what", "UTF-8");
1652 if (cd == (iconv_t) -1)
1659 # Return true if the atomic library is supported on the target.
1660 proc check_effective_target_libatomic_available { } {
1661 return [check_no_compiler_messages libatomic_available executable {
1662 int main (void) { return 0; }
1666 # Return 1 if an ASCII locale is supported on this host, 0 otherwise.
1668 proc check_ascii_locale_available { } {
1672 # Return true if named sections are supported on this target.
1674 proc check_named_sections_available { } {
1675 return [check_no_compiler_messages named_sections assembly {
1676 int __attribute__ ((section("whatever"))) foo;
1680 # Return true if the "naked" function attribute is supported on this target.
1682 proc check_effective_target_naked_functions { } {
1683 return [check_no_compiler_messages naked_functions assembly {
1684 void f() __attribute__((naked));
1688 # Return 1 if the target supports Fortran real kinds larger than real(8),
1691 # When the target name changes, replace the cached result.
1693 proc check_effective_target_fortran_large_real { } {
1694 return [check_no_compiler_messages fortran_large_real executable {
1696 integer,parameter :: k = selected_real_kind (precision (0.0_8) + 1)
1703 # Return 1 if the target supports Fortran real kind real(16),
1704 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1705 # this checks for Real(16) only; the other returned real(10) if
1706 # both real(10) and real(16) are available.
1708 # When the target name changes, replace the cached result.
1710 proc check_effective_target_fortran_real_16 { } {
1711 return [check_no_compiler_messages fortran_real_16 executable {
1719 # Return 1 if the target supports Fortran real kind 10,
1720 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1721 # this checks for real(10) only.
1723 # When the target name changes, replace the cached result.
1725 proc check_effective_target_fortran_real_10 { } {
1726 return [check_no_compiler_messages fortran_real_10 executable {
1734 # Return 1 if the target supports Fortran real kind C_FLOAT128,
1735 # 0 otherwise. This differs from check_effective_target_fortran_real_16
1736 # because _Float128 has the additional requirement that it be the
1737 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
1738 # have a corresponding Fortran kind on targets (PowerPC) that use some
1739 # other encoding for long double/TFmode/real(16).
1740 proc check_effective_target_fortran_real_c_float128 { } {
1741 return [check_no_compiler_messages fortran_real_c_float128 executable {
1744 real(kind=c_float128) :: x
1750 # Return 1 if the target supports Fortran's IEEE modules,
1753 # When the target name changes, replace the cached result.
1755 proc check_effective_target_fortran_ieee { flags } {
1756 return [check_no_compiler_messages fortran_ieee executable {
1758 use, intrinsic :: ieee_features
1764 # Return 1 if the target supports SQRT for the largest floating-point
1765 # type. (Some targets lack the libm support for this FP type.)
1766 # On most targets, this check effectively checks either whether sqrtl is
1767 # available or on __float128 systems whether libquadmath is installed,
1768 # which provides sqrtq.
1770 # When the target name changes, replace the cached result.
1772 proc check_effective_target_fortran_largest_fp_has_sqrt { } {
1773 return [check_no_compiler_messages fortran_largest_fp_has_sqrt executable {
1775 use iso_fortran_env, only: real_kinds
1776 integer,parameter:: maxFP = real_kinds(ubound(real_kinds,dim=1))
1777 real(kind=maxFP), volatile :: x
1785 # Return 1 if the target supports Fortran integer kinds larger than
1786 # integer(8), 0 otherwise.
1788 # When the target name changes, replace the cached result.
1790 proc check_effective_target_fortran_large_int { } {
1791 return [check_no_compiler_messages fortran_large_int executable {
1793 integer,parameter :: k = selected_int_kind (range (0_8) + 1)
1794 integer(kind=k) :: i
1799 # Return 1 if the target supports Fortran integer(16), 0 otherwise.
1801 # When the target name changes, replace the cached result.
1803 proc check_effective_target_fortran_integer_16 { } {
1804 return [check_no_compiler_messages fortran_integer_16 executable {
1811 # Return 1 if we can statically link libgfortran, 0 otherwise.
1813 # When the target name changes, replace the cached result.
1815 proc check_effective_target_static_libgfortran { } {
1816 return [check_no_compiler_messages static_libgfortran executable {
1823 # Return 1 if we can use the -rdynamic option, 0 otherwise.
1825 proc check_effective_target_rdynamic { } {
1826 return [check_no_compiler_messages rdynamic executable {
1827 int main() { return 0; }
1831 proc check_linker_plugin_available { } {
1832 return [check_no_compiler_messages_nocache linker_plugin executable {
1833 int main() { return 0; }
1834 } "-flto -fuse-linker-plugin"]
1837 # Return 1 if the target is RV32, 0 otherwise. Cache the result.
1839 proc check_effective_target_rv32 { } {
1840 # Check that we are compiling for RV32 by checking the xlen size.
1841 return [check_no_compiler_messages riscv_rv32 assembly {
1842 #if !defined(__riscv_xlen)
1843 #error "__riscv_xlen not defined!"
1845 #if __riscv_xlen != 32
1852 # Return 1 if the target is RV64, 0 otherwise. Cache the result.
1854 proc check_effective_target_rv64 { } {
1855 # Check that we are compiling for RV64 by checking the xlen size.
1856 return [check_no_compiler_messages riscv_rv64 assembly {
1857 #if !defined(__riscv_xlen)
1858 #error "__riscv_xlen not defined!"
1860 #if __riscv_xlen != 64
1867 # Return 1 if the target abi is __riscv_float_abi_soft, 0 otherwise.
1870 proc check_effective_target_rv_float_abi_soft { } {
1871 # Check that we are compiling for RV64 by checking the xlen size.
1872 return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly {
1873 #ifndef __riscv_float_abi_soft
1874 #error "Not __riscv_float_abi_soft"
1879 # Return 1 if the target arch supports the atomic extension, 0 otherwise.
1882 proc check_effective_target_riscv_a { } {
1883 return [check_no_compiler_messages riscv_ext_a assembly {
1885 #error "Not __riscv_a"
1890 # Return 1 if the target arch supports the double precision floating point
1891 # extension, 0 otherwise. Cache the result.
1893 proc check_effective_target_riscv_d { } {
1894 return [check_no_compiler_messages riscv_ext_d assembly {
1896 #error "Not __riscv_d"
1901 # Return 1 if the target arch supports the vector extension, 0 otherwise.
1904 proc check_effective_target_riscv_v { } {
1905 return [check_no_compiler_messages riscv_ext_v assembly {
1907 #error "Not __riscv_v"
1912 # Return 1 if the target arch supports the Zvfh extension, 0 otherwise.
1915 proc check_effective_target_riscv_zvfh { } {
1916 return [check_no_compiler_messages riscv_ext_zvfh assembly {
1917 #ifndef __riscv_zvfh
1918 #error "Not __riscv_zvfh"
1923 # Return 1 if the target arch supports half float, 0 otherwise.
1924 # Note, this differs from the test performed by
1925 # /* dg-skip-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */
1926 # in that it takes default behaviour into account.
1929 proc check_effective_target_riscv_zfh { } {
1930 return [check_no_compiler_messages riscv_ext_zfh assembly {
1932 #error "Not __riscv_zfh"
1937 # Return 1 if the target arch supports the TSO memory ordering extension,
1938 # 0 otherwise. Cache the result.
1940 proc check_effective_target_riscv_ztso { } {
1941 return [check_no_compiler_messages riscv_ext_ztso assembly {
1942 #ifndef __riscv_ztso
1943 #error "Not __riscv_ztso"
1948 # Return 1 if the target arch supports the Zbb extension, 0 otherwise.
1951 proc check_effective_target_riscv_zbb { } {
1952 return [check_no_compiler_messages riscv_ext_zbb assembly {
1954 #error "Not __riscv_zbb"
1959 # Return 1 if we can execute code when using dg-add-options riscv_v
1961 proc check_effective_target_riscv_v_ok { } {
1962 # If the target already supports v without any added options,
1963 # we may assume we can execute just fine.
1964 if { [check_effective_target_riscv_v] } {
1968 # check if we can execute vector insns with the given hardware or
1970 set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
1971 if { [check_runtime ${gcc_march}_exec {
1972 int main() { asm("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } {
1976 # Possible future extensions: If the target is a simulator, dg-add-options
1977 # might change its config to make it allow vector insns, or we might use
1978 # options to set special elf flags / sections to effect that.
1983 # Return 1 if we can execute code when using dg-add-options riscv_zfh
1985 proc check_effective_target_riscv_zfh_ok { } {
1986 # If the target already supports zfh without any added options,
1987 # we may assume we can execute just fine.
1988 # ??? Other cases we should consider:
1989 # - target / simulator already supports zfh extension - test for that.
1990 # - target is a simulator, and dg-add-options knows how to enable zfh support in that simulator
1991 if { [check_effective_target_riscv_zfh] } {
1995 # check if we can execute zfh insns with the given hardware or
1997 set gcc_march [riscv_get_arch]
1998 if { [check_runtime ${gcc_march}_zfh_exec {
1999 int main() { asm("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } {
2003 # Possible future extensions: If the target is a simulator, dg-add-options
2004 # might change its config to make it allow half float insns, or we might
2005 # use options to set special elf flags / sections to effect that.
2010 # Return 1 if we can execute code when using dg-add-options riscv_zvfh
2012 proc check_effective_target_riscv_zvfh_ok { } {
2013 # If the target already supports v without any added options,
2014 # we may assume we can execute just fine.
2015 if { [check_effective_target_riscv_zvfh] } {
2019 # check if we can execute vector insns with the given hardware or
2021 set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
2022 if { [check_runtime ${gcc_march}_exec {
2025 asm ("vsetivli zero,8,e16,m1,ta,ma");
2026 asm ("vfadd.vv v8,v8,v16" : : : "v8");
2028 } } "-march=${gcc_march}"] } {
2035 proc riscv_get_arch { } {
2037 # ??? do we neeed to add more extensions to the list below?
2038 foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso } {
2039 if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
2044 if { [string length $ext] > 1 } {
2047 set gcc_march $gcc_march$ext
2049 if { [string equal $gcc_march "imafd"] } {
2053 if { [check_effective_target_rv32] } {
2054 set gcc_march rv32$gcc_march
2055 } elseif { [check_effective_target_rv64] } {
2056 set gcc_march rv64$gcc_march
2063 proc add_options_for_riscv_a { flags } {
2064 if { [lsearch $flags -march=*] >= 0 } {
2065 # If there are multiple -march flags, we have to adjust all of them.
2066 set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ]
2067 return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1a ]
2069 if { [check_effective_target_riscv_a] } {
2072 return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]"
2075 proc add_options_for_riscv_d { flags } {
2076 if { [lsearch $flags -march=*] >= 0 } {
2077 # If there are multiple -march flags, we have to adjust all of them.
2078 return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ]
2080 if { [check_effective_target_riscv_d] } {
2083 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]"
2086 proc add_options_for_riscv_v { flags } {
2087 if { [lsearch $flags -march=*] >= 0 } {
2088 # If there are multiple -march flags, we have to adjust all of them.
2089 return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1v ]
2091 if { [check_effective_target_riscv_v] } {
2094 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
2097 proc add_options_for_riscv_zfh { flags } {
2098 if { [lsearch $flags -march=*] >= 0 } {
2099 # If there are multiple -march flags, we have to adjust all of them.
2100 set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zfh ]
2101 return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zfh[[:alnum:]_.]*)_zfh} $flags \\1 ]
2103 if { [check_effective_target_riscv_zfh] } {
2106 return "$flags -march=[riscv_get_arch]_zfh"
2109 proc add_options_for_riscv_ztso { flags } {
2110 if { [lsearch $flags -march=*] >= 0 } {
2111 # If there are multiple -march flags, we have to adjust all of them.
2112 set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_ztso ]
2113 return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_ztso[[:alnum:]_.]*)_ztso} $flags \\1 ]
2115 if { [check_effective_target_riscv_ztso] } {
2118 return "$flags -march=[riscv_get_arch]_ztso"
2121 proc add_options_for_riscv_zvfh { flags } {
2122 if { [lsearch $flags -march=*] >= 0 } {
2123 # If there are multiple -march flags, we have to adjust all of them.
2124 set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvfh ]
2125 return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvfh[[:alnum:]_.]*)_zvfh} $flags \\1 ]
2127 if { [check_effective_target_riscv_zvfh] } {
2130 return "$flags -march=[riscv_get_arch]_zvfh"
2133 # Return 1 if the target OS supports running SSE executables, 0
2134 # otherwise. Cache the result.
2136 proc check_sse_os_support_available { } {
2137 return [check_cached_effective_target sse_os_support_available {
2138 # If this is not the right target then we can skip the test.
2139 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2147 # Return 1 if the target OS supports running AVX executables, 0
2148 # otherwise. Cache the result.
2150 proc check_avx_os_support_available { } {
2151 return [check_cached_effective_target avx_os_support_available {
2152 # If this is not the right target then we can skip the test.
2153 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2156 # Check that OS has AVX and SSE saving enabled.
2157 check_runtime_nocache avx_os_support_available {
2160 unsigned int eax, edx;
2162 asm ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2163 return (eax & 0x06) != 0x06;
2170 # Return 1 if the target OS supports running AVX executables, 0
2171 # otherwise. Cache the result.
2173 proc check_avx512_os_support_available { } {
2174 return [check_cached_effective_target avx512_os_support_available {
2175 # If this is not the right target then we can skip the test.
2176 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2179 # Check that OS has AVX512, AVX and SSE saving enabled.
2180 check_runtime_nocache avx512_os_support_available {
2183 unsigned int eax, edx;
2185 asm ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2186 return (eax & 0xe6) != 0xe6;
2193 # Return 1 if the target supports executing SSE instructions, 0
2194 # otherwise. Cache the result.
2196 proc check_sse_hw_available { } {
2197 return [check_cached_effective_target sse_hw_available {
2198 # If this is not the right target then we can skip the test.
2199 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2202 check_runtime_nocache sse_hw_available {
2206 unsigned int eax, ebx, ecx, edx;
2207 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2210 return !(edx & bit_SSE);
2217 # Return 1 if the target supports executing SSE2 instructions, 0
2218 # otherwise. Cache the result.
2220 proc check_sse2_hw_available { } {
2221 return [check_cached_effective_target sse2_hw_available {
2222 # If this is not the right target then we can skip the test.
2223 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2226 check_runtime_nocache sse2_hw_available {
2230 unsigned int eax, ebx, ecx, edx;
2231 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2234 return !(edx & bit_SSE2);
2241 # Return 1 if the target supports executing SSE4 instructions, 0
2242 # otherwise. Cache the result.
2244 proc check_sse4_hw_available { } {
2245 return [check_cached_effective_target sse4_hw_available {
2246 # If this is not the right target then we can skip the test.
2247 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2250 check_runtime_nocache sse4_hw_available {
2254 unsigned int eax, ebx, ecx, edx;
2255 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2258 return !(ecx & bit_SSE4_2);
2265 # Return 1 if the target supports executing AVX instructions, 0
2266 # otherwise. Cache the result.
2268 proc check_avx_hw_available { } {
2269 return [check_cached_effective_target avx_hw_available {
2270 # If this is not the right target then we can skip the test.
2271 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2274 check_runtime_nocache avx_hw_available {
2278 unsigned int eax, ebx, ecx, edx;
2279 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2282 return ((ecx & (bit_AVX | bit_OSXSAVE))
2283 != (bit_AVX | bit_OSXSAVE));
2290 # Return 1 if the target supports executing AVX2 instructions, 0
2291 # otherwise. Cache the result.
2293 proc check_avx2_hw_available { } {
2294 return [check_cached_effective_target avx2_hw_available {
2295 # If this is not the right target then we can skip the test.
2296 if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
2299 check_runtime_nocache avx2_hw_available {
2304 unsigned int eax, ebx, ecx, edx;
2306 if (__get_cpuid_max (0, NULL) < 7)
2309 __cpuid (1, eax, ebx, ecx, edx);
2311 if (!(ecx & bit_OSXSAVE))
2314 __cpuid_count (7, 0, eax, ebx, ecx, edx);
2316 return !(ebx & bit_AVX2);
2323 # Return 1 if the target supports executing AVX512 foundation instructions, 0
2324 # otherwise. Cache the result.
2326 proc check_avx512f_hw_available { } {
2327 return [check_cached_effective_target avx512f_hw_available {
2328 # If this is not the right target then we can skip the test.
2329 if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
2332 check_runtime_nocache avx512f_hw_available {
2337 unsigned int eax, ebx, ecx, edx;
2339 if (__get_cpuid_max (0, NULL) < 7)
2342 __cpuid (1, eax, ebx, ecx, edx);
2344 if (!(ecx & bit_OSXSAVE))
2347 __cpuid_count (7, 0, eax, ebx, ecx, edx);
2349 return !(ebx & bit_AVX512F);
2356 # Return 1 if the target supports running SSE executables, 0 otherwise.
2358 proc check_effective_target_sse_runtime { } {
2359 if { [check_effective_target_sse]
2360 && [check_sse_hw_available]
2361 && [check_sse_os_support_available] } {
2367 # Return 1 if the target supports running SSE2 executables, 0 otherwise.
2369 proc check_effective_target_sse2_runtime { } {
2370 if { [check_effective_target_sse2]
2371 && [check_sse2_hw_available]
2372 && [check_sse_os_support_available] } {
2378 # Return 1 if the target supports running SSE4 executables, 0 otherwise.
2380 proc check_effective_target_sse4_runtime { } {
2381 if { [check_effective_target_sse4]
2382 && [check_sse4_hw_available]
2383 && [check_sse_os_support_available] } {
2389 # Return 1 if the target supports running AVX executables, 0 otherwise.
2391 proc check_effective_target_avx_runtime { } {
2392 if { [check_effective_target_avx]
2393 && [check_avx_hw_available]
2394 && [check_avx_os_support_available] } {
2400 # Return 1 if the target supports running AVX2 executables, 0 otherwise.
2402 proc check_effective_target_avx2_runtime { } {
2403 if { [check_effective_target_avx2]
2404 && [check_avx2_hw_available]
2405 && [check_avx_os_support_available] } {
2411 # Return 1 if the target supports running AVX512f executables, 0 otherwise.
2413 proc check_effective_target_avx512f_runtime { } {
2414 if { [check_effective_target_avx512f]
2415 && [check_avx512f_hw_available]
2416 && [check_avx512_os_support_available] } {
2422 # Return 1 if bmi2 instructions can be compiled.
2423 proc check_effective_target_bmi2 { } {
2424 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2427 return [check_no_compiler_messages bmi2 object {
2429 _bzhi_u32 (unsigned int __X, unsigned int __Y)
2431 return __builtin_ia32_bzhi_si (__X, __Y);
2436 # Return 1 if the target supports executing MIPS Paired-Single instructions,
2437 # 0 otherwise. Cache the result.
2439 proc check_mpaired_single_hw_available { } {
2440 return [check_cached_effective_target mpaired_single_hw_available {
2441 # If this is not the right target then we can skip the test.
2442 if { !([istarget mips*-*-*]) } {
2445 check_runtime_nocache mpaired_single_hw_available {
2448 asm volatile ("pll.ps $f2,$f4,$f6");
2456 # Return 1 if the target supports executing Loongson vector instructions,
2457 # 0 otherwise. Cache the result.
2459 proc check_mips_loongson_mmi_hw_available { } {
2460 return [check_cached_effective_target mips_loongson_mmi_hw_available {
2461 # If this is not the right target then we can skip the test.
2462 if { !([istarget mips*-*-*]) } {
2465 check_runtime_nocache mips_loongson_mmi_hw_available {
2466 #include <loongson-mmiintrin.h>
2469 asm volatile ("paddw $f2,$f4,$f6");
2477 # Return 1 if the target supports executing MIPS MSA instructions, 0
2478 # otherwise. Cache the result.
2480 proc check_mips_msa_hw_available { } {
2481 return [check_cached_effective_target mips_msa_hw_available {
2482 # If this is not the right target then we can skip the test.
2483 if { !([istarget mips*-*-*]) } {
2486 check_runtime_nocache mips_msa_hw_available {
2487 #if !defined(__mips_msa)
2488 #error "MSA NOT AVAIL"
2490 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
2491 #error "MSA NOT AVAIL FOR ISA REV < 2"
2493 #if !defined(__mips_hard_float)
2494 #error "MSA HARD_FLOAT REQUIRED"
2496 #if __mips_fpr != 64
2497 #error "MSA 64-bit FPR REQUIRED"
2503 v8i16 v = __builtin_msa_ldi_h (0);
2513 # Return 1 if the target supports running MIPS Paired-Single
2514 # executables, 0 otherwise.
2516 proc check_effective_target_mpaired_single_runtime { } {
2517 if { [check_effective_target_mpaired_single "-mpaired-single"]
2518 && [check_mpaired_single_hw_available] } {
2524 # Return 1 if the target supports running Loongson executables, 0 otherwise.
2526 proc check_effective_target_mips_loongson_mmi_runtime { } {
2527 if { [check_effective_target_mips_loongson_mmi "-mloongson-mmi"]
2528 && [check_mips_loongson_mmi_hw_available] } {
2534 # Return 1 if the target supports running MIPS MSA executables, 0 otherwise.
2536 proc check_effective_target_mips_msa_runtime { } {
2537 if { [check_effective_target_mips_msa "-mmsa"]
2538 && [check_mips_msa_hw_available] } {
2544 # Return 1 if we are compiling for 64-bit PowerPC but we do not use direct
2545 # move instructions for moves from GPR to FPR.
2547 proc check_effective_target_powerpc64_no_dm { } {
2548 # The "mulld" checks if we are generating PowerPC64 code. The "lfd"
2549 # checks if we do not use direct moves, but use the old-fashioned
2550 # slower move-via-the-stack.
2551 return [check_no_messages_and_pattern powerpc64_no_dm \
2552 {\mmulld\M.*\mlfd} assembly {
2553 double f(long long x) { return x*x; }
2557 # Return 1 if the target supports the __builtin_cpu_supports built-in,
2558 # including having a new enough library to support the test. Cache the result.
2559 # Require at least a power7 to run on.
2561 proc check_ppc_cpu_supports_hw_available { } {
2562 return [check_cached_effective_target ppc_cpu_supports_hw_available {
2563 # Some simulators are known to not support VSX/power8 instructions.
2564 # For now, disable on Darwin
2565 if { [istarget powerpc-*-eabi]
2566 || [istarget powerpc*-*-eabispe]
2567 || [istarget *-*-darwin*]} {
2571 check_runtime_nocache ppc_cpu_supports_hw_available {
2575 asm volatile ("xxlor vs0,vs0,vs0");
2577 asm volatile ("xxlor 0,0,0");
2579 if (!__builtin_cpu_supports ("vsx"))
2588 # Return 1 if the target supports executing 750CL paired-single instructions, 0
2589 # otherwise. Cache the result.
2591 proc check_750cl_hw_available { } {
2592 return [check_cached_effective_target 750cl_hw_available {
2593 # If this is not the right target then we can skip the test.
2594 if { ![istarget powerpc-*paired*] } {
2597 check_runtime_nocache 750cl_hw_available {
2601 asm volatile ("ps_mul v0,v0,v0");
2603 asm volatile ("ps_mul 0,0,0");
2612 # Return 1 if the target supports executing power8 vector instructions, 0
2613 # otherwise. Cache the result.
2615 proc check_p8vector_hw_available { } {
2616 return [check_cached_effective_target p8vector_hw_available {
2617 # Some simulators are known to not support VSX/power8 instructions.
2618 # For now, disable on Darwin
2619 if { [istarget powerpc-*-eabi]
2620 || [istarget powerpc*-*-eabispe]
2621 || [istarget *-*-darwin*]} {
2624 set options "-mpower8-vector"
2625 check_runtime_nocache p8vector_hw_available {
2629 asm volatile ("xxlorc vs0,vs0,vs0");
2631 asm volatile ("xxlorc 0,0,0");
2640 # Return 1 if the target supports executing power9 vector instructions, 0
2641 # otherwise. Cache the result.
2643 proc check_p9vector_hw_available { } {
2644 return [check_cached_effective_target p9vector_hw_available {
2645 # Some simulators are known to not support VSX/power8/power9
2646 # instructions. For now, disable on Darwin.
2647 if { [istarget powerpc-*-eabi]
2648 || [istarget powerpc*-*-eabispe]
2649 || [istarget *-*-darwin*]} {
2652 set options "-mpower9-vector"
2653 check_runtime_nocache p9vector_hw_available {
2657 vector double v = (vector double) { 0.0, 0.0 };
2658 asm ("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
2666 # Return 1 if the PowerPC target generates PC-relative instructions
2667 # automatically for targets that support PC-relative instructions.
2668 proc check_effective_target_powerpc_pcrel { } {
2669 return [check_no_messages_and_pattern powerpc_pcrel \
2670 {\mpla\M} assembly {
2671 static unsigned short s;
2672 unsigned short *p_foo (void) { return &s; }
2673 } {-O2 -mcpu=power10}]
2676 # Return 1 if the PowerPC target generates prefixed instructions automatically
2677 # for targets that support prefixed instructions.
2678 proc check_effective_target_powerpc_prefixed_addr { } {
2679 return [check_no_messages_and_pattern powerpc_prefixed_addr \
2680 {\mplwz\M} assembly {
2681 unsigned int foo (unsigned int *p) { return p[0x12345]; }
2682 } {-O2 -mcpu=power10}]
2685 # Return 1 if the target supports executing power9 modulo instructions, 0
2686 # otherwise. Cache the result.
2688 proc check_p9modulo_hw_available { } {
2689 return [check_cached_effective_target p9modulo_hw_available {
2690 # Some simulators are known to not support VSX/power8/power9
2691 # instructions. For now, disable on Darwin.
2692 if { [istarget powerpc-*-eabi]
2693 || [istarget powerpc*-*-eabispe]
2694 || [istarget *-*-darwin*]} {
2697 set options "-mmodulo"
2698 check_runtime_nocache p9modulo_hw_available {
2701 int i = 5, j = 3, r = -1;
2702 asm ("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
2711 # Return 1 if the target supports executing power10 instructions, 0 otherwise.
2712 # Cache the result. It is assumed that if a simulator does not support the
2713 # power10 instructions, that it will generate an error and this test will fail.
2715 proc check_power10_hw_available { } {
2716 return [check_cached_effective_target power10_hw_available {
2717 check_runtime_nocache power10_hw_available {
2720 /* Set e first and use +r to check if pli actually works. */
2722 asm ("pli %0,%1" : "+r" (e) : "n" (0x12345));
2731 # Return 1 if the target supports executing MMA instructions, 0 otherwise.
2732 # Cache the result. It is assumed that if a simulator does not support the
2733 # MMA instructions, that it will generate an error and this test will fail.
2735 proc check_ppc_mma_hw_available { } {
2736 return [check_cached_effective_target ppc_mma_hw_available {
2737 check_runtime_nocache ppc_mma_hw_available {
2738 #include <altivec.h>
2739 typedef double v4sf_t __attribute__ ((vector_size (16)));
2746 __builtin_mma_xxsetaccz (&acc0);
2747 __builtin_mma_disassemble_acc (result, &acc0);
2748 if (result[0][0] != 0.0)
2756 # Return 1 if the target supports executing __float128 on PowerPC via software
2757 # emulation, 0 otherwise. Cache the result.
2759 proc check_ppc_float128_sw_available { } {
2760 return [check_cached_effective_target ppc_float128_sw_available {
2761 # Some simulators are known to not support VSX/power8/power9
2762 # instructions. For now, disable on Darwin and VxWorks.
2763 if { [istarget *-*-vxworks*]
2764 || [istarget powerpc-*-eabi]
2765 || [istarget powerpc*-*-eabispe]
2766 || [istarget *-*-darwin*]} {
2769 set options "-mfloat128 -mvsx"
2770 check_runtime_nocache ppc_float128_sw_available {
2771 volatile __float128 x = 1.0q;
2772 volatile __float128 y = 2.0q;
2775 __float128 z = x + y;
2783 # Return 1 if the target supports executing __float128 on PowerPC via power9
2784 # hardware instructions, 0 otherwise. Cache the result.
2786 proc check_ppc_float128_hw_available { } {
2787 return [check_cached_effective_target ppc_float128_hw_available {
2788 # Some simulators are known to not support VSX/power8/power9
2789 # instructions. For now, disable on Darwin.
2790 if { [istarget *-*-vxworks*]
2791 || [istarget powerpc-*-eabi]
2792 || [istarget powerpc*-*-eabispe]
2793 || [istarget *-*-darwin*]} {
2796 set options "-mfloat128 -mvsx -mfloat128-hardware -mpower9-vector"
2797 check_runtime_nocache ppc_float128_hw_available {
2798 volatile __float128 x = 1.0q;
2799 volatile __float128 y = 2.0q;
2802 __float128 z = x + y;
2803 __float128 w = -1.0q;
2805 __asm__ ("xsaddqp %0,%1,%2" : "+v" (w) : "v" (x), "v" (y));
2806 return ((z != 3.0q) || (z != w));
2813 # See if the __ieee128 keyword is understood.
2814 proc check_effective_target_ppc_ieee128_ok { } {
2815 return [check_cached_effective_target ppc_ieee128_ok {
2816 # disable on AIX and VxWorks.
2817 if { [istarget *-*-aix*]
2818 || [istarget *-*-vxworks*]} {
2821 set options "-mfloat128"
2822 check_runtime_nocache ppc_ieee128_ok {
2833 # Check if GCC and GLIBC supports explicitly specifying that the long double
2834 # format uses the IBM 128-bit extended double format. Under little endian
2835 # PowerPC Linux, you need GLIBC 2.32 or later to be able to use a different
2836 # long double format for running a program than the system default.
2838 proc check_effective_target_long_double_ibm128 { } {
2839 return [check_runtime_nocache long_double_ibm128 {
2842 /* use volatile to prevent optimization. */
2843 volatile __ibm128 a = (__ibm128) 3.0;
2844 volatile long double one = 1.0L;
2845 volatile long double two = 2.0L;
2846 volatile long double b;
2852 if (sizeof (long double) != 16)
2855 /* eliminate removing volatile cast warning. */
2858 if (memcmp (&a2, &b2, 16) != 0)
2860 sprintf (buffer, "%lg", b);
2861 return strcmp (buffer, "3") != 0;
2863 } [add_options_for_long_double_ibm128 ""]]
2866 # Return the appropriate options to specify that long double uses the IBM
2867 # 128-bit format on PowerPC.
2869 proc add_options_for_long_double_ibm128 { flags } {
2870 if { [istarget powerpc*-*-*] } {
2871 return "$flags -mlong-double-128 -Wno-psabi -mabi=ibmlongdouble"
2876 # Check if GCC and GLIBC supports explicitly specifying that the long double
2877 # format uses the IEEE 128-bit format. Under little endian PowerPC Linux, you
2878 # need GLIBC 2.32 or later to be able to use a different long double format for
2879 # running a program than the system default.
2881 proc check_effective_target_long_double_ieee128 { } {
2882 return [check_runtime_nocache long_double_ieee128 {
2885 /* use volatile to prevent optimization. */
2886 volatile _Float128 a = 3.0f128;
2887 volatile long double one = 1.0L;
2888 volatile long double two = 2.0L;
2889 volatile long double b;
2895 if (sizeof (long double) != 16)
2898 /* eliminate removing volatile cast warning. */
2901 if (memcmp (&a2, &b2, 16) != 0)
2903 sprintf (buffer, "%lg", b);
2904 return strcmp (buffer, "3") != 0;
2906 } [add_options_for_long_double_ieee128 ""]]
2909 # Return the appropriate options to specify that long double uses the IBM
2910 # 128-bit format on PowerPC.
2911 proc add_options_for_long_double_ieee128 { flags } {
2912 if { [istarget powerpc*-*-*] } {
2913 return "$flags -mlong-double-128 -Wno-psabi -mabi=ieeelongdouble"
2918 # Check if GCC and GLIBC supports explicitly specifying that the long double
2919 # format uses the IEEE 64-bit. Under little endian PowerPC Linux, you need
2920 # GLIBC 2.32 or later to be able to use a different long double format for
2921 # running a program than the system default.
2923 proc check_effective_target_long_double_64bit { } {
2924 return [check_runtime_nocache long_double_64bit {
2927 /* use volatile to prevent optimization. */
2928 volatile double a = 3.0;
2929 volatile long double one = 1.0L;
2930 volatile long double two = 2.0L;
2931 volatile long double b;
2937 if (sizeof (long double) != 8)
2940 /* eliminate removing volatile cast warning. */
2943 if (memcmp (&a2, &b2, 16) != 0)
2945 sprintf (buffer, "%lg", b);
2946 return strcmp (buffer, "3") != 0;
2948 } [add_options_for_ppc_long_double_override_64bit ""]]
2951 # Return the appropriate options to specify that long double uses the IEEE
2952 # 64-bit format on PowerPC.
2954 proc add_options_for_long_double_64bit { flags } {
2955 if { [istarget powerpc*-*-*] } {
2956 return "$flags -mlong-double-64"
2961 # Return 1 if the target supports executing VSX instructions, 0
2962 # otherwise. Cache the result.
2964 proc check_vsx_hw_available { } {
2965 return [check_cached_effective_target vsx_hw_available {
2966 # Some simulators are known to not support VSX instructions.
2967 # For now, disable on Darwin
2968 if { [istarget powerpc-*-eabi]
2969 || [istarget powerpc*-*-eabispe]
2970 || [istarget *-*-darwin*]} {
2974 check_runtime_nocache vsx_hw_available {
2978 asm volatile ("xxlor vs0,vs0,vs0");
2980 asm volatile ("xxlor 0,0,0");
2989 # Return 1 if the target supports executing AltiVec instructions, 0
2990 # otherwise. Cache the result.
2992 proc check_vmx_hw_available { } {
2993 return [check_cached_effective_target vmx_hw_available {
2994 # Some simulators are known to not support VMX instructions.
2995 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] } {
2998 # Most targets don't require special flags for this test case, but
2999 # Darwin does. Just to be sure, make sure VSX is not enabled for
3000 # the altivec tests.
3001 if { [istarget *-*-darwin*]
3002 || [istarget *-*-aix*] } {
3003 set options "-maltivec -mno-vsx"
3005 set options "-mno-vsx"
3007 check_runtime_nocache vmx_hw_available {
3011 asm volatile ("vor v0,v0,v0");
3013 asm volatile ("vor 0,0,0");
3022 proc check_ppc_recip_hw_available { } {
3023 return [check_cached_effective_target ppc_recip_hw_available {
3024 # Some simulators may not support FRE/FRES/FRSQRTE/FRSQRTES
3025 # For now, disable on Darwin
3026 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3029 set options "-mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb"
3030 check_runtime_nocache ppc_recip_hw_available {
3031 volatile double d_recip, d_rsqrt, d_four = 4.0;
3032 volatile float f_recip, f_rsqrt, f_four = 4.0f;
3035 asm volatile ("fres %0,%1" : "=f" (f_recip) : "f" (f_four));
3036 asm volatile ("fre %0,%1" : "=d" (d_recip) : "d" (d_four));
3037 asm volatile ("frsqrtes %0,%1" : "=f" (f_rsqrt) : "f" (f_four));
3038 asm volatile ("frsqrte %0,%1" : "=f" (d_rsqrt) : "d" (d_four));
3046 # Return 1 if the target supports executing AltiVec and Cell PPU
3047 # instructions, 0 otherwise. Cache the result.
3049 proc check_effective_target_cell_hw { } {
3050 return [check_cached_effective_target cell_hw_available {
3051 # Some simulators are known to not support VMX and PPU instructions.
3052 if { [istarget powerpc-*-eabi*] } {
3055 # Most targets don't require special flags for this test
3056 # case, but Darwin and AIX do.
3057 if { [istarget *-*-darwin*]
3058 || [istarget *-*-aix*] } {
3059 set options "-maltivec -mcpu=cell"
3061 set options "-mcpu=cell"
3063 check_runtime_nocache cell_hw_available {
3067 asm volatile ("vor v0,v0,v0");
3068 asm volatile ("lvlx v0,r0,r0");
3070 asm volatile ("vor 0,0,0");
3071 asm volatile ("lvlx 0,0,0");
3080 # Return 1 if the target supports executing 64-bit instructions, 0
3081 # otherwise. Cache the result.
3083 proc check_effective_target_powerpc64 { } {
3084 global powerpc64_available_saved
3087 if [info exists powerpc64_available_saved] {
3088 verbose "check_effective_target_powerpc64 returning saved $powerpc64_available_saved" 2
3090 set powerpc64_available_saved 0
3092 # Some simulators are known to not support powerpc64 instructions.
3093 if { [istarget powerpc-*-eabi*] || [istarget powerpc-ibm-aix*] } {
3094 verbose "check_effective_target_powerpc64 returning 0" 2
3095 return $powerpc64_available_saved
3098 # Set up, compile, and execute a test program containing a 64-bit
3099 # instruction. Include the current process ID in the file
3100 # names to prevent conflicts with invocations for multiple
3105 set f [open $src "w"]
3106 puts $f "int main() {"
3107 puts $f "#ifdef __MACH__"
3108 puts $f " asm volatile (\"extsw r0,r0\");"
3110 puts $f " asm volatile (\"extsw 0,0\");"
3112 puts $f " return 0; }"
3115 set opts "additional_flags=-mcpu=G5"
3117 verbose "check_effective_target_powerpc64 compiling testfile $src" 2
3118 set lines [${tool}_target_compile $src $exe executable "$opts"]
3121 if [string match "" $lines] then {
3122 # No error message, compilation succeeded.
3123 set result [${tool}_load "./$exe" "" ""]
3124 set status [lindex $result 0]
3125 remote_file build delete $exe
3126 verbose "check_effective_target_powerpc64 testfile status is <$status>" 2
3128 if { $status == "pass" } then {
3129 set powerpc64_available_saved 1
3132 verbose "check_effective_target_powerpc64 testfile compilation failed" 2
3136 return $powerpc64_available_saved
3139 # GCC 3.4.0 for powerpc64-*-linux* included an ABI fix for passing
3140 # complex float arguments. This affects gfortran tests that call cabsf
3141 # in libm built by an earlier compiler. Return 0 if libm uses the same
3142 # argument passing as the compiler under test, 1 otherwise.
3144 proc check_effective_target_broken_cplxf_arg { } {
3145 # Skip the work for targets known not to be affected.
3146 if { ![istarget powerpc*-*-linux*] || ![is-effective-target lp64] } {
3150 return [check_cached_effective_target broken_cplxf_arg {
3151 check_runtime_nocache broken_cplxf_arg {
3152 #include <complex.h>
3153 extern void abort (void);
3154 float fabsf (float);
3155 float cabsf (_Complex float);
3162 if (fabsf (f - 5.0) > 0.0001)
3163 /* Yes, it's broken. */
3165 /* All fine, not broken. */
3172 # Return 1 is this is a TI C6X target supporting C67X instructions
3173 proc check_effective_target_ti_c67x { } {
3174 return [check_no_compiler_messages ti_c67x assembly {
3175 #if !defined(_TMS320C6700)
3176 #error !_TMS320C6700
3181 # Return 1 is this is a TI C6X target supporting C64X+ instructions
3182 proc check_effective_target_ti_c64xp { } {
3183 return [check_no_compiler_messages ti_c64xp assembly {
3184 #if !defined(_TMS320C6400_PLUS)
3185 #error !_TMS320C6400_PLUS
3190 # Check if a -march=... option is given, as part of (earlier) options.
3191 proc check_effective_target_march_option { } {
3192 return [check-flags [list "" { *-*-* } { "-march=*" } { "" } ]]
3195 proc check_alpha_max_hw_available { } {
3196 return [check_runtime alpha_max_hw_available {
3197 int main() { return __builtin_alpha_amask(1<<8) != 0; }
3201 # Returns true iff the FUNCTION is available on the target system.
3202 # (This is essentially a Tcl implementation of Autoconf's
3205 proc check_function_available { function } {
3206 return [check_no_compiler_messages ${function}_available \
3212 int main () { $function (); }
3216 # Returns true iff "fork" is available on the target system.
3218 proc check_fork_available {} {
3219 if { [istarget *-*-vxworks*] } {
3220 # VxWorks doesn't have fork but our way to test can't
3221 # tell as we're doing partial links for kernel modules.
3224 if { [istarget cris-*-*] } {
3225 # Compiling and linking works, and an executable running e.g.
3226 # gcc.dg/torture/ftrapv-1.c works on now-historical hardware,
3227 # but the GNU simulator emits an error for the fork syscall.
3228 return [check_effective_target_hw]
3230 return [check_function_available "fork"]
3233 # Returns true iff "mkfifo" is available on the target system.
3235 proc check_mkfifo_available {} {
3236 if { [istarget *-*-cygwin*] } {
3237 # Cygwin has mkfifo, but support is incomplete.
3241 return [check_function_available "mkfifo"]
3244 # Returns true iff "__cxa_atexit" is used on the target system.
3246 proc check_cxa_atexit_available { } {
3247 return [check_cached_effective_target cxa_atexit_available {
3248 if { [istarget *-*-vxworks] } {
3249 # vxworks doesn't have __cxa_atexit but subsequent test passes.
3252 check_runtime_nocache cxa_atexit_available {
3255 static unsigned int count;
3272 Y() { f(); count = 2; }
3281 int main() { return 0; }
3287 proc check_effective_target_objc2 { } {
3288 return [check_no_compiler_messages objc2 object {
3297 proc check_effective_target_next_runtime { } {
3298 return [check_no_compiler_messages objc2 object {
3299 #ifdef __NEXT_RUNTIME__
3302 #error !__NEXT_RUNTIME__
3307 # Return 1 if we're generating code for big-endian memory order.
3309 proc check_effective_target_be { } {
3310 return [check_no_compiler_messages be object {
3311 int dummy[__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ? 1 : -1];
3315 # Return 1 if we're generating code for little-endian memory order.
3317 proc check_effective_target_le { } {
3318 return [check_no_compiler_messages le object {
3319 int dummy[__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ? 1 : -1];
3323 # Return 1 if we can link a program with 2+GB of data.
3325 proc check_effective_target_two_plus_gigs { } {
3326 return [check_no_compiler_messages two_plus_gigs executable {
3327 char dummy[0x80000000];
3328 int main () { return 0; }
3332 # Return 1 if we're generating 32-bit code using default options, 0
3335 proc check_effective_target_ilp32 { } {
3336 return [check_no_compiler_messages ilp32 object {
3337 int dummy[sizeof (int) == 4
3338 && sizeof (void *) == 4
3339 && sizeof (long) == 4 ? 1 : -1];
3343 # Return 1 if we're generating ia32 code using default options, 0
3346 proc check_effective_target_ia32 { } {
3347 return [check_no_compiler_messages ia32 object {
3348 int dummy[sizeof (int) == 4
3349 && sizeof (void *) == 4
3350 && sizeof (long) == 4 ? 1 : -1] = { __i386__ };
3354 # Return 1 if we're generating x32 code using default options, 0
3357 proc check_effective_target_x32 { } {
3358 return [check_no_compiler_messages x32 object {
3359 int dummy[sizeof (int) == 4
3360 && sizeof (void *) == 4
3361 && sizeof (long) == 4 ? 1 : -1] = { __x86_64__ };
3365 # Return 1 if we're generating 32-bit integers using default
3366 # options, 0 otherwise.
3368 proc check_effective_target_int32 { } {
3369 return [check_no_compiler_messages int32 object {
3370 int dummy[sizeof (int) == 4 ? 1 : -1];
3374 # Return 1 if we're generating 32-bit or larger integers using default
3375 # options, 0 otherwise.
3377 proc check_effective_target_int32plus { } {
3378 return [check_no_compiler_messages int32plus object {
3379 int dummy[sizeof (int) >= 4 ? 1 : -1];
3383 # Return 1 if we're generating 64-bit long long using default options,
3386 proc check_effective_target_longlong64 { } {
3387 return [check_no_compiler_messages longlong64 object {
3388 int dummy[sizeof (long long) == 8 ? 1 : -1];
3392 # Return 1 if we're generating 32-bit or larger pointers using default
3393 # options, 0 otherwise.
3395 proc check_effective_target_ptr32plus { } {
3396 # The msp430 has 16-bit or 20-bit pointers. The 20-bit pointer is stored
3397 # in a 32-bit slot when in memory, so sizeof(void *) returns 4, but it
3398 # cannot really hold a 32-bit address, so we always return false here.
3399 if { [istarget msp430-*-*] } {
3403 return [check_no_compiler_messages ptr32plus object {
3404 int dummy[sizeof (void *) >= 4 ? 1 : -1];
3408 # Return 1 if we support 16-bit or larger array and structure sizes
3409 # using default options, 0 otherwise.
3410 # This implies at least a 20-bit address space, as no targets have an address
3411 # space between 16 and 20 bits.
3413 proc check_effective_target_size20plus { } {
3414 return [check_no_compiler_messages size20plus object {
3419 # Return 1 if target supports function pointers, 0 otherwise.
3421 proc check_effective_target_function_pointers { } {
3422 if { [istarget pru-*-*] } {
3423 return [check_no_compiler_messages func_ptr_avail assembly {
3424 #ifdef __PRU_EABI_GNU__
3432 # Return 1 if target supports arbitrarily large return values, 0 otherwise.
3434 proc check_effective_target_large_return_values { } {
3435 if { [istarget pru-*-*] } {
3436 return [check_no_compiler_messages large_return_values assembly {
3437 #ifdef __PRU_EABI_GNU__
3444 # Return 1 if we support 20-bit or larger array and structure sizes
3445 # using default options, 0 otherwise.
3446 # This implies at least a 24-bit address space, as no targets have an address
3447 # space between 20 and 24 bits.
3449 proc check_effective_target_size24plus { } {
3450 return [check_no_compiler_messages size24plus object {
3451 char dummy[524289L];
3455 # Return 1 if we support 24-bit or larger array and structure sizes
3456 # using default options, 0 otherwise.
3457 # This implies at least a 32-bit address space, as no targets have an address
3458 # space between 24 and 32 bits.
3460 proc check_effective_target_size32plus { } {
3461 return [check_no_compiler_messages size32plus object {
3462 char dummy[16777217L];
3466 # Returns 1 if we're generating 16-bit or smaller integers with the
3467 # default options, 0 otherwise.
3469 proc check_effective_target_int16 { } {
3470 return [check_no_compiler_messages int16 object {
3471 int dummy[sizeof (int) < 4 ? 1 : -1];
3475 # Return 1 if we're generating 64-bit code using default options, 0
3478 proc check_effective_target_lp64 { } {
3479 return [check_no_compiler_messages lp64 object {
3480 int dummy[sizeof (int) == 4
3481 && sizeof (void *) == 8
3482 && sizeof (long) == 8 ? 1 : -1];
3486 # Return 1 if we're generating 64-bit code using default llp64 options,
3489 proc check_effective_target_llp64 { } {
3490 return [check_no_compiler_messages llp64 object {
3491 int dummy[sizeof (int) == 4
3492 && sizeof (void *) == 8
3493 && sizeof (long long) == 8
3494 && sizeof (long) == 4 ? 1 : -1];
3498 # Return 1 if long and int have different sizes,
3501 proc check_effective_target_long_neq_int { } {
3502 return [check_no_compiler_messages long_ne_int object {
3503 int dummy[sizeof (int) != sizeof (long) ? 1 : -1];
3507 # Return 1 if int size is equal to float size,
3510 proc check_effective_target_int_eq_float { } {
3511 return [check_no_compiler_messages int_eq_float object {
3512 int dummy[sizeof (int) >= sizeof (float) ? 1 : -1];
3516 # Return 1 if short size is equal to int size,
3519 proc check_effective_target_short_eq_int { } {
3520 return [check_no_compiler_messages short_eq_int object {
3521 int dummy[sizeof (short) == sizeof (int) ? 1 : -1];
3525 # Return 1 if pointer size is equal to short size,
3528 proc check_effective_target_ptr_eq_short { } {
3529 return [check_no_compiler_messages ptr_eq_short object {
3530 int dummy[sizeof (void *) == sizeof (short) ? 1 : -1];
3534 # Return 1 if pointer size is equal to long size,
3537 proc check_effective_target_ptr_eq_long { } {
3538 # sizeof (void *) == 4 for msp430-elf -mlarge which is equal to
3539 # sizeof (long). Avoid false positive.
3540 if { [istarget msp430-*-*] } {
3543 return [check_no_compiler_messages ptr_eq_long object {
3544 int dummy[sizeof (void *) == sizeof (long) ? 1 : -1];
3548 # Return 1 if the target supports long double larger than double,
3551 proc check_effective_target_large_long_double { } {
3552 return [check_no_compiler_messages large_long_double object {
3553 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
3557 # Return 1 if the target supports double larger than float,
3560 proc check_effective_target_large_double { } {
3561 return [check_no_compiler_messages large_double object {
3562 int dummy[sizeof(double) > sizeof(float) ? 1 : -1];
3566 # Return 1 if the target supports long double of 128 bits,
3569 proc check_effective_target_longdouble128 { } {
3570 return [check_no_compiler_messages longdouble128 object {
3571 int dummy[sizeof(long double) == 16 ? 1 : -1];
3575 # Return 1 if the target supports long double of 64 bits,
3578 proc check_effective_target_longdouble64 { } {
3579 return [check_no_compiler_messages longdouble64 object {
3580 int dummy[sizeof(long double) == 8 ? 1 : -1];
3584 # Return 1 if the target supports double of 64 bits,
3587 proc check_effective_target_double64 { } {
3588 return [check_no_compiler_messages double64 object {
3589 int dummy[sizeof(double) == 8 ? 1 : -1];
3593 # Return 1 if the target supports double of at least 64 bits,
3596 proc check_effective_target_double64plus { } {
3597 return [check_no_compiler_messages double64plus object {
3598 int dummy[sizeof(double) >= 8 ? 1 : -1];
3602 # Return 1 if the target supports 'w' suffix on floating constant
3605 proc check_effective_target_has_w_floating_suffix { } {
3607 if [check_effective_target_c++] {
3608 append opts "-std=gnu++03"
3610 return [check_no_compiler_messages w_fp_suffix object {
3615 # Return 1 if the target supports 'q' suffix on floating constant
3618 proc check_effective_target_has_q_floating_suffix { } {
3620 if [check_effective_target_c++] {
3621 append opts "-std=gnu++03"
3623 return [check_no_compiler_messages q_fp_suffix object {
3628 # Return 1 if the target supports the _FloatN / _FloatNx type
3629 # indicated in the function name, 0 otherwise.
3631 proc check_effective_target_float16 {} {
3632 return [check_no_compiler_messages_nocache float16 object {
3633 _Float16 foo (_Float16 x) { return x; }
3634 } [add_options_for_float16 ""]]
3637 proc check_effective_target_float32 {} {
3638 return [check_no_compiler_messages_nocache float32 object {
3640 } [add_options_for_float32 ""]]
3643 proc check_effective_target_float64 {} {
3644 return [check_no_compiler_messages_nocache float64 object {
3646 } [add_options_for_float64 ""]]
3649 proc check_effective_target_float128 {} {
3650 return [check_no_compiler_messages_nocache float128 object {
3652 } [add_options_for_float128 ""]]
3655 proc check_effective_target_float32x {} {
3656 return [check_no_compiler_messages_nocache float32x object {
3658 } [add_options_for_float32x ""]]
3661 proc check_effective_target_float64x {} {
3662 return [check_no_compiler_messages_nocache float64x object {
3664 } [add_options_for_float64x ""]]
3667 proc check_effective_target_float128x {} {
3668 return [check_no_compiler_messages_nocache float128x object {
3670 } [add_options_for_float128x ""]]
3673 # Likewise, but runtime support for any special options used as well
3674 # as compile-time support is required.
3676 proc check_effective_target_float16_runtime {} {
3677 return [check_effective_target_float16]
3680 proc check_effective_target_float32_runtime {} {
3681 return [check_effective_target_float32]
3684 proc check_effective_target_float64_runtime {} {
3685 return [check_effective_target_float64]
3688 proc check_effective_target_float128_runtime {} {
3689 if { ![check_effective_target_float128] } {
3692 if { [istarget powerpc*-*-*] } {
3693 return [check_effective_target_base_quadfloat_support]
3698 proc check_effective_target_float32x_runtime {} {
3699 return [check_effective_target_float32x]
3702 proc check_effective_target_float64x_runtime {} {
3703 if { ![check_effective_target_float64x] } {
3706 if { [istarget powerpc*-*-*] } {
3707 return [check_effective_target_base_quadfloat_support]
3712 proc check_effective_target_float128x_runtime {} {
3713 return [check_effective_target_float128x]
3716 # Return 1 if the target hardware supports any options added for
3717 # _FloatN and _FloatNx types, 0 otherwise.
3719 proc check_effective_target_floatn_nx_runtime {} {
3720 if { [istarget powerpc*-*-aix*] } {
3723 if { [istarget powerpc*-*-*] } {
3724 return [check_effective_target_base_quadfloat_support]
3729 # Add options needed to use the _FloatN / _FloatNx type indicated in
3730 # the function name.
3732 proc add_options_for_float16 { flags } {
3733 if { [istarget arm*-*-*] } {
3734 return "$flags -mfp16-format=ieee"
3736 if { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
3737 return "$flags -msse2"
3742 proc add_options_for_float32 { flags } {
3746 proc add_options_for_float64 { flags } {
3750 proc add_options_for_float128 { flags } {
3751 return [add_options_for___float128 "$flags"]
3754 proc add_options_for_float32x { flags } {
3758 proc add_options_for_float64x { flags } {
3759 return [add_options_for___float128 "$flags"]
3762 proc add_options_for_float128x { flags } {
3766 # Return 1 if the target supports __float128,
3769 proc check_effective_target___float128 { } {
3770 if { [istarget powerpc*-*-*] } {
3771 return [check_ppc_float128_sw_available]
3773 if { [istarget ia64-*-*]
3774 || [istarget i?86-*-*] || [istarget x86_64-*-*] } {
3780 proc add_options_for___float128 { flags } {
3781 if { [istarget powerpc*-*-linux*] } {
3782 return "$flags -mfloat128 -mvsx"
3787 # Return 1 if the target supports any special run-time requirements
3788 # for __float128 or _Float128,
3791 proc check_effective_target_base_quadfloat_support { } {
3792 if { [istarget powerpc*-*-*] } {
3793 return [check_vsx_hw_available]
3798 # Return 1 if the target supports the __bf16 type, 0 otherwise.
3800 proc check_effective_target_bfloat16 {} {
3801 return [check_no_compiler_messages_nocache bfloat16 object {
3802 __bf16 foo (__bf16 x) { return x + x; }
3803 } [add_options_for_bfloat16 ""]]
3806 proc check_effective_target_bfloat16_runtime {} {
3807 return [check_effective_target_bfloat16]
3810 proc add_options_for_bfloat16 { flags } {
3814 # Return 1 if the target supports all four forms of fused multiply-add
3815 # (fma, fms, fnma, and fnms) for both float and double.
3817 proc check_effective_target_scalar_all_fma { } {
3818 return [istarget aarch64*-*-*]
3821 # Return 1 if the target supports compiling fixed-point,
3824 proc check_effective_target_fixed_point { } {
3825 return [check_no_compiler_messages fixed_point object {
3826 _Sat _Fract x; _Sat _Accum y;
3830 # Return 1 if the target supports _BitInt(N), 0 otherwise.
3832 proc check_effective_target_bitint { } {
3833 return [check_no_compiler_messages bitint object {
3834 _BitInt (2) a = 1wb;
3835 unsigned _BitInt (__BITINT_MAXWIDTH__) b = 0uwb;
3839 # Return 1 if the target supports _BitInt(128), 0 otherwise.
3841 proc check_effective_target_bitint128 { } {
3842 return [check_no_compiler_messages bitint128 object {
3843 _BitInt (2) a = 1wb;
3844 unsigned _BitInt (128) b = 0uwb;
3848 # Return 1 if the target supports _BitInt(575), 0 otherwise.
3850 proc check_effective_target_bitint575 { } {
3851 return [check_no_compiler_messages bitint575 object {
3852 _BitInt (2) a = 1wb;
3853 unsigned _BitInt (575) b = 0uwb;
3857 # Return 1 if the target supports compiling decimal floating point,
3860 proc check_effective_target_dfp_nocache { } {
3861 verbose "check_effective_target_dfp_nocache: compiling source" 2
3862 set ret [check_no_compiler_messages_nocache dfp object {
3863 float x __attribute__((mode(DD)));
3865 verbose "check_effective_target_dfp_nocache: returning $ret" 2
3869 proc check_effective_target_dfprt_nocache { } {
3870 return [check_runtime_nocache dfprt {
3871 typedef float d64 __attribute__((mode(DD)));
3872 d64 x = 1.2df, y = 2.3dd, z;
3873 int main () { z = x + y; return 0; }
3877 # Return 1 if the target supports compiling Decimal Floating Point,
3880 # This won't change for different subtargets so cache the result.
3882 proc check_effective_target_dfp { } {
3883 return [check_cached_effective_target dfp {
3884 check_effective_target_dfp_nocache
3888 # Return 1 if the target supports linking and executing Decimal Floating
3889 # Point, 0 otherwise.
3891 # This won't change for different subtargets so cache the result.
3893 proc check_effective_target_dfprt { } {
3894 return [check_cached_effective_target dfprt {
3895 check_effective_target_dfprt_nocache
3899 # Return 1 if the target uses the BID format for Decimal Floating
3900 # Point, 0 otherwise.
3902 proc check_effective_target_dfp_bid { } {
3903 if { [istarget aarch64*-*-*]
3904 || [istarget i?86-*-*] || [istarget x86_64-*-*]} {
3910 # Return 1 iff target has unsigned plain 'char' by default.
3912 proc check_effective_target_unsigned_char {} {
3913 return [check_no_compiler_messages unsigned_char assembly {
3918 proc check_effective_target_powerpc_popcntb_ok { } {
3919 return [check_cached_effective_target powerpc_popcntb_ok {
3921 # Disable on Darwin.
3922 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3925 check_runtime_nocache powerpc_popcntb_ok {
3927 volatile int a = 0x12345678;
3930 asm volatile ("popcntb %0,%1" : "=r" (r) : "r" (a));
3938 # Return 1 if the target supports executing DFP hardware instructions,
3939 # 0 otherwise. Cache the result.
3941 proc check_dfp_hw_available { } {
3942 return [check_cached_effective_target dfp_hw_available {
3943 # For now, disable on Darwin
3944 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3947 check_runtime_nocache dfp_hw_available {
3948 volatile _Decimal64 r;
3949 volatile _Decimal64 a = 4.0DD;
3950 volatile _Decimal64 b = 2.0DD;
3953 asm volatile ("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3954 asm volatile ("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3955 asm volatile ("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3956 asm volatile ("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3959 } "-mcpu=power6 -mhard-float"
3964 # Return 1 if the target supports compiling and assembling UCN, 0 otherwise.
3966 proc check_effective_target_ucn_nocache { } {
3967 # -std=c99 is only valid for C
3968 if [check_effective_target_c] {
3969 set ucnopts "-std=c99"
3973 verbose "check_effective_target_ucn_nocache: compiling source" 2
3974 set ret [check_no_compiler_messages_nocache ucn object {
3977 verbose "check_effective_target_ucn_nocache: returning $ret" 2
3981 # Return 1 if the target supports compiling and assembling UCN, 0 otherwise.
3983 # This won't change for different subtargets, so cache the result.
3985 proc check_effective_target_ucn { } {
3986 return [check_cached_effective_target ucn {
3987 check_effective_target_ucn_nocache
3991 # Return 1 if the target needs a command line argument to enable a SIMD
3994 proc check_effective_target_vect_cmdline_needed { } {
3995 global et_vect_cmdline_needed_target_name
3997 if { ![info exists et_vect_cmdline_needed_target_name] } {
3998 set et_vect_cmdline_needed_target_name ""
4001 # If the target has changed since we set the cached value, clear it.
4002 set current_target [current_target_name]
4003 if { $current_target != $et_vect_cmdline_needed_target_name } {
4004 verbose "check_effective_target_vect_cmdline_needed: `$et_vect_cmdline_needed_target_name' `$current_target'" 2
4005 set et_vect_cmdline_needed_target_name $current_target
4006 if { [info exists et_vect_cmdline_needed_saved] } {
4007 verbose "check_effective_target_vect_cmdline_needed: removing cached result" 2
4008 unset et_vect_cmdline_needed_saved
4012 return [check_cached_effective_target vect_cmdline_needed {
4013 if { [istarget alpha*-*-*]
4014 || [istarget ia64-*-*]
4015 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
4016 && ![is-effective-target ia32])
4017 || ([istarget powerpc*-*-*]
4018 && ([check_effective_target_powerpc_spe]
4019 || [check_effective_target_powerpc_altivec]))
4020 || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
4021 || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
4022 || [istarget aarch64*-*-*]
4023 || [istarget amdgcn*-*-*]
4024 || [istarget riscv*-*-*]} {
4031 # Return 1 if the target supports hardware vectors of int, 0 otherwise.
4033 # This won't change for different subtargets so cache the result.
4035 proc check_effective_target_vect_int { } {
4036 return [check_cached_effective_target_indexed vect_int {
4038 [istarget i?86-*-*] || [istarget x86_64-*-*]
4039 || ([istarget powerpc*-*-*]
4040 && ![istarget powerpc-*-linux*paired*])
4041 || [istarget amdgcn-*-*]
4042 || [istarget sparc*-*-*]
4043 || [istarget alpha*-*-*]
4044 || [istarget ia64-*-*]
4045 || [istarget aarch64*-*-*]
4046 || [is-effective-target arm_neon]
4047 || ([istarget mips*-*-*]
4048 && ([et-is-effective-target mips_loongson_mmi]
4049 || [et-is-effective-target mips_msa]))
4050 || ([istarget s390*-*-*]
4051 && [check_effective_target_s390_vx])
4052 || ([istarget riscv*-*-*]
4053 && [check_effective_target_riscv_v])
4057 # Return 1 if the target supports vectorization of early breaks,
4060 # This won't change for different subtargets so cache the result.
4062 proc check_effective_target_vect_early_break { } {
4063 return [check_cached_effective_target_indexed vect_early_break {
4065 [istarget aarch64*-*-*]
4066 || [check_effective_target_sse4]
4070 # Return 1 if the target supports hardware execution of early breaks,
4073 # This won't change for different subtargets so cache the result.
4075 proc check_effective_target_vect_early_break_hw { } {
4076 return [check_cached_effective_target_indexed vect_early_break_hw {
4078 [istarget aarch64*-*-*]
4079 || [check_sse4_hw_available]
4083 proc add_options_for_vect_early_break { flags } {
4084 if { ! [check_effective_target_vect_early_break] } {
4088 if { [check_effective_target_sse4] } {
4089 return "$flags -msse4.1"
4095 # Return 1 if the target supports hardware vectorization of complex additions of
4096 # byte, 0 otherwise.
4098 # This won't change for different subtargets so cache the result.
4100 proc check_effective_target_vect_complex_add_byte { } {
4101 return [check_cached_effective_target_indexed vect_complex_add_byte {
4103 ([check_effective_target_aarch64_sve2]
4104 && [check_effective_target_aarch64_little_endian])
4105 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4106 && [check_effective_target_arm_little_endian])
4110 # Return 1 if the target supports hardware vectorization of complex additions of
4111 # short, 0 otherwise.
4113 # This won't change for different subtargets so cache the result.
4115 proc check_effective_target_vect_complex_add_short { } {
4116 return [check_cached_effective_target_indexed vect_complex_add_short {
4118 ([check_effective_target_aarch64_sve2]
4119 && [check_effective_target_aarch64_little_endian])
4120 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4121 && [check_effective_target_arm_little_endian])
4125 # Return 1 if the target supports hardware vectorization of complex additions of
4128 # This won't change for different subtargets so cache the result.
4130 proc check_effective_target_vect_complex_add_int { } {
4131 return [check_cached_effective_target_indexed vect_complex_add_int {
4133 ([check_effective_target_aarch64_sve2]
4134 && [check_effective_target_aarch64_little_endian])
4135 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4136 && [check_effective_target_arm_little_endian])
4140 # Return 1 if the target supports hardware vectorization of complex additions of
4141 # long, 0 otherwise.
4143 # This won't change for different subtargets so cache the result.
4145 proc check_effective_target_vect_complex_add_long { } {
4146 return [check_cached_effective_target_indexed vect_complex_add_long {
4148 ([check_effective_target_aarch64_sve2]
4149 && [check_effective_target_aarch64_little_endian])
4150 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4151 && [check_effective_target_arm_little_endian])
4155 # Return 1 if the target supports hardware vectorization of complex additions of
4156 # half, 0 otherwise.
4158 # This won't change for different subtargets so cache the result.
4160 proc check_effective_target_vect_complex_add_half { } {
4161 return [check_cached_effective_target_indexed vect_complex_add_half {
4163 ([check_effective_target_arm_v8_3a_fp16_complex_neon_ok]
4164 && ([check_effective_target_aarch64_little_endian]
4165 || [check_effective_target_arm_little_endian]))
4166 || ([check_effective_target_aarch64_sve2]
4167 && [check_effective_target_aarch64_little_endian])
4168 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4169 && [check_effective_target_arm_little_endian])
4173 # Return 1 if the target supports hardware vectorization of complex additions of
4174 # float, 0 otherwise.
4176 # This won't change for different subtargets so cache the result.
4178 proc check_effective_target_vect_complex_add_float { } {
4179 return [check_cached_effective_target_indexed vect_complex_add_float {
4181 ([check_effective_target_arm_v8_3a_complex_neon_ok]
4182 && ([check_effective_target_aarch64_little_endian]
4183 || [check_effective_target_arm_little_endian]))
4184 || ([check_effective_target_aarch64_sve2]
4185 && [check_effective_target_aarch64_little_endian])
4186 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4187 && [check_effective_target_arm_little_endian])
4191 # Return 1 if the target supports hardware vectorization of complex additions of
4192 # double, 0 otherwise.
4194 # This won't change for different subtargets so cache the result.
4196 proc check_effective_target_vect_complex_add_double { } {
4197 return [check_cached_effective_target_indexed vect_complex_add_double {
4199 (([check_effective_target_arm_v8_3a_complex_neon_ok]
4200 && [check_effective_target_aarch64_little_endian])
4201 || ([check_effective_target_aarch64_sve2]
4202 && [check_effective_target_aarch64_little_endian]))
4206 # Return 1 if the target supports signed int->float conversion
4209 proc check_effective_target_vect_intfloat_cvt { } {
4210 return [check_cached_effective_target_indexed vect_intfloat_cvt {
4211 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4212 || ([istarget powerpc*-*-*]
4213 && ![istarget powerpc-*-linux*paired*])
4214 || [is-effective-target arm_neon]
4215 || ([istarget mips*-*-*]
4216 && [et-is-effective-target mips_msa])
4217 || [istarget amdgcn-*-*]
4218 || ([istarget s390*-*-*]
4219 && [check_effective_target_s390_vxe2])
4220 || ([istarget riscv*-*-*]
4221 && [check_effective_target_riscv_v]) }}]
4224 # Return 1 if the target supports signed double->int conversion
4227 proc check_effective_target_vect_doubleint_cvt { } {
4228 return [check_cached_effective_target_indexed vect_doubleint_cvt {
4229 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4230 && [check_no_compiler_messages vect_doubleint_cvt assembly {
4231 #ifdef __tune_atom__
4232 # error No double vectorizer support.
4235 || [istarget aarch64*-*-*]
4236 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4237 || ([istarget mips*-*-*]
4238 && [et-is-effective-target mips_msa])
4239 || ([istarget s390*-*-*]
4240 && [check_effective_target_s390_vx])
4241 || ([istarget riscv*-*-*]
4242 && [check_effective_target_riscv_v]) }}]
4245 # Return 1 if the target supports signed int->double conversion
4248 proc check_effective_target_vect_intdouble_cvt { } {
4249 return [check_cached_effective_target_indexed vect_intdouble_cvt {
4250 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4251 && [check_no_compiler_messages vect_intdouble_cvt assembly {
4252 #ifdef __tune_atom__
4253 # error No double vectorizer support.
4256 || [istarget aarch64*-*-*]
4257 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4258 || ([istarget mips*-*-*]
4259 && [et-is-effective-target mips_msa])
4260 || ([istarget s390*-*-*]
4261 && [check_effective_target_s390_vx])
4262 || ([istarget riscv*-*-*]
4263 && [check_effective_target_riscv_v]) }}]
4266 #Return 1 if we're supporting __int128 for target, 0 otherwise.
4268 proc check_effective_target_int128 { } {
4269 return [check_no_compiler_messages int128 object {
4271 #ifndef __SIZEOF_INT128__
4280 # Return 1 if the target supports unsigned int->float conversion
4283 proc check_effective_target_vect_uintfloat_cvt { } {
4284 return [check_cached_effective_target_indexed vect_uintfloat_cvt {
4285 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4286 || ([istarget powerpc*-*-*]
4287 && ![istarget powerpc-*-linux*paired*])
4288 || [istarget aarch64*-*-*]
4289 || [is-effective-target arm_neon]
4290 || ([istarget mips*-*-*]
4291 && [et-is-effective-target mips_msa])
4292 || [istarget amdgcn-*-*]
4293 || ([istarget s390*-*-*]
4294 && [check_effective_target_s390_vxe2])
4295 || ([istarget riscv*-*-*]
4296 && [check_effective_target_riscv_v]) }}]
4300 # Return 1 if the target supports signed float->int conversion
4303 proc check_effective_target_vect_floatint_cvt { } {
4304 return [check_cached_effective_target_indexed vect_floatint_cvt {
4305 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4306 || ([istarget powerpc*-*-*]
4307 && ![istarget powerpc-*-linux*paired*])
4308 || [is-effective-target arm_neon]
4309 || ([istarget mips*-*-*]
4310 && [et-is-effective-target mips_msa])
4311 || [istarget amdgcn-*-*]
4312 || ([istarget s390*-*-*]
4313 && [check_effective_target_s390_vxe2])
4314 || ([istarget riscv*-*-*]
4315 && [check_effective_target_riscv_v]) }}]
4318 # Return 1 if the target supports unsigned float->int conversion
4321 proc check_effective_target_vect_floatuint_cvt { } {
4322 return [check_cached_effective_target_indexed vect_floatuint_cvt {
4323 expr { ([istarget powerpc*-*-*]
4324 && ![istarget powerpc-*-linux*paired*])
4325 || [is-effective-target arm_neon]
4326 || ([istarget mips*-*-*]
4327 && [et-is-effective-target mips_msa])
4328 || [istarget amdgcn-*-*]
4329 || ([istarget s390*-*-*]
4330 && [check_effective_target_s390_vxe2])
4331 || ([istarget riscv*-*-*]
4332 && [check_effective_target_riscv_v]) }}]
4335 # Return 1 if the target supports vector integer char -> long long extend optab
4338 proc check_effective_target_vect_ext_char_longlong { } {
4339 return [check_cached_effective_target_indexed vect_ext_char_longlong {
4340 expr { ([istarget riscv*-*-*]
4341 && [check_effective_target_riscv_v]) }}]
4344 # Return 1 if peeling for alignment might be profitable on the target
4347 proc check_effective_target_vect_peeling_profitable { } {
4348 return [check_cached_effective_target_indexed vect_peeling_profitable {
4349 expr { ([istarget s390*-*-*]
4350 && [check_effective_target_s390_vx])
4351 || [check_effective_target_vect_element_align_preferred] }}]
4354 # Return 1 if the target supports #pragma omp declare simd, 0 otherwise.
4356 # This won't change for different subtargets so cache the result.
4358 proc check_effective_target_vect_simd_clones { } {
4359 # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx,
4360 # avx2 and avx512f clone. Only the right clone for the
4361 # specified arch will be chosen, but still we need to at least
4362 # be able to assemble avx512f.
4363 return [check_cached_effective_target_indexed vect_simd_clones {
4364 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4365 && [check_effective_target_avx512f])
4366 || [istarget amdgcn-*-*]
4367 || [istarget aarch64*-*-*] }}]
4370 # Return 1 if this is a AArch64 target supporting big endian
4371 proc check_effective_target_aarch64_big_endian { } {
4372 return [check_no_compiler_messages aarch64_big_endian assembly {
4373 #if !defined(__aarch64__) || !defined(__AARCH64EB__)
4374 #error !__aarch64__ || !__AARCH64EB__
4379 # Return 1 if this is a AArch64 target supporting little endian
4380 proc check_effective_target_aarch64_little_endian { } {
4381 if { ![istarget aarch64*-*-*] } {
4385 return [check_no_compiler_messages aarch64_little_endian assembly {
4386 #if !defined(__aarch64__) || defined(__AARCH64EB__)
4392 # Return 1 if this is an AArch64 target supporting SVE.
4393 proc check_effective_target_aarch64_sve { } {
4394 if { ![istarget aarch64*-*-*] } {
4397 return [check_no_compiler_messages aarch64_sve assembly {
4398 #if !defined (__ARM_FEATURE_SVE)
4404 # Return 1 if this is an AArch64 target supporting SVE2.
4405 proc check_effective_target_aarch64_sve2 { } {
4406 if { ![istarget aarch64*-*-*] } {
4409 return [check_no_compiler_messages aarch64_sve2 assembly {
4410 #if !defined (__ARM_FEATURE_SVE2)
4416 # Return 1 if this is an AArch64 target only supporting SVE (not SVE2).
4417 proc check_effective_target_aarch64_sve1_only { } {
4418 return [expr { [check_effective_target_aarch64_sve]
4419 && ![check_effective_target_aarch64_sve2] }]
4422 # Return the size in bits of an SVE vector, or 0 if the size is variable.
4423 proc aarch64_sve_bits { } {
4424 return [check_cached_effective_target aarch64_sve_bits {
4427 set src dummy[pid].c
4428 set f [open $src "w"]
4429 puts $f "int bits = __ARM_FEATURE_SVE_BITS;"
4431 set output [${tool}_target_compile $src "" preprocess ""]
4434 regsub {.*bits = ([^;]*);.*} $output {\1} bits
4439 # Return 1 if this is an AArch64 target that generates instructions for SME.
4440 proc check_effective_target_aarch64_sme { } {
4441 if { ![istarget aarch64*-*-*] } {
4444 return [check_no_compiler_messages aarch64_sme assembly {
4445 #if !defined (__ARM_FEATURE_SME)
4451 # Return 1 if this is an AArch64 target that generates instructions for SME.
4452 proc check_effective_target_aarch64_sme2 { } {
4453 if { ![istarget aarch64*-*-*] } {
4456 return [check_no_compiler_messages aarch64_sme2 assembly {
4457 #if !defined (__ARM_FEATURE_SME2)
4463 # Return 1 if this is a compiler supporting ARC atomic operations
4464 proc check_effective_target_arc_atomic { } {
4465 return [check_no_compiler_messages arc_atomic assembly {
4466 #if !defined(__ARC_ATOMIC__)
4472 # Return 1 if this is an arm target using 32-bit instructions
4473 proc check_effective_target_arm32 { } {
4474 if { ![istarget arm*-*-*] } {
4478 return [check_no_compiler_messages arm32 assembly {
4479 #if !defined(__arm__) || (defined(__thumb__) && !defined(__thumb2__))
4480 #error !__arm || __thumb__ && !__thumb2__
4485 # Return 1 if this is an arm target not using Thumb
4486 proc check_effective_target_arm_nothumb { } {
4487 if { ![istarget arm*-*-*] } {
4491 return [check_no_compiler_messages arm_nothumb assembly {
4492 #if !defined(__arm__) || (defined(__thumb__) || defined(__thumb2__))
4493 #error !__arm__ || __thumb || __thumb2__
4498 # Return 1 if this is a little-endian ARM target
4499 proc check_effective_target_arm_little_endian { } {
4500 if { ![istarget arm*-*-*] } {
4504 return [check_no_compiler_messages arm_little_endian assembly {
4505 #if !defined(__arm__) || !defined(__ARMEL__)
4506 #error !__arm__ || !__ARMEL__
4511 # Return 1 if this is an ARM target that only supports aligned vector accesses
4512 proc check_effective_target_arm_vect_no_misalign { } {
4513 if { ![istarget arm*-*-*] } {
4517 return [check_no_compiler_messages arm_vect_no_misalign assembly {
4518 #if !defined(__arm__) \
4519 || (defined(__ARM_FEATURE_UNALIGNED) \
4520 && defined(__ARMEL__))
4521 #error !__arm__ || (__ARMEL__ && __ARM_FEATURE_UNALIGNED)
4527 # Return 1 if this is an ARM target supporting -mfloat-abi=soft. Some
4528 # multilibs may be incompatible with this option.
4530 proc check_effective_target_arm_soft_ok { } {
4531 return [check_no_compiler_messages arm_soft_ok object {
4534 int main (void) { return 0; }
4535 } "-mfloat-abi=soft"]
4538 # Return 1 if this is an ARM target supporting -mfloat-abi=soft even
4539 # for linking. Some multilibs may be incompatible with this option,
4540 # and some linkers may reject incompatible options.
4542 proc check_effective_target_arm_soft_ok_link { } {
4543 return [check_no_compiler_messages arm_soft_ok_link executable {
4546 int main (void) { return 0; }
4547 } "-mfloat-abi=soft"]
4550 # Return 1 if this is an ARM target supporting -mfpu=vfp with an
4553 proc check_effective_target_arm_vfp_ok_nocache { } {
4554 global et_arm_vfp_flags
4555 set et_arm_vfp_flags ""
4556 if { [check_effective_target_arm32] } {
4557 foreach flags {"-mfpu=vfp" "-mfpu=vfp -mfloat-abi=softfp" "-mfpu=vfp -mfloat-abi=hard"} {
4558 if { [check_no_compiler_messages_nocache arm_vfp_ok object {
4560 #error __ARM_FP not defined
4563 set et_arm_vfp_flags $flags
4572 proc check_effective_target_arm_vfp_ok { } {
4573 return [check_cached_effective_target arm_vfp_ok \
4574 check_effective_target_arm_vfp_ok_nocache]
4577 # Add the options needed to compile code with -mfpu=vfp. We need either
4578 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4579 # specified by the multilib, use it.
4581 proc add_options_for_arm_vfp { flags } {
4582 if { ! [check_effective_target_arm_vfp_ok] } {
4585 global et_arm_vfp_flags
4586 return "$flags $et_arm_vfp_flags"
4589 # Return 1 if this is an ARM target supporting -mfpu=vfp3
4590 # -mfloat-abi=softfp.
4592 proc check_effective_target_arm_vfp3_ok { } {
4593 if { [check_effective_target_arm32] } {
4594 return [check_no_compiler_messages arm_vfp3_ok object {
4596 } "-mfpu=vfp3 -mfloat-abi=softfp"]
4602 # Return 1 if this is an ARM target supporting -mfpu=fp-armv8
4603 # -mfloat-abi=softfp.
4604 proc check_effective_target_arm_v8_vfp_ok {} {
4605 if { [check_effective_target_arm32] } {
4606 return [check_no_compiler_messages arm_v8_vfp_ok object {
4609 __asm__ volatile ("vrinta.f32.f32 s0, s0");
4612 } "-mfpu=fp-armv8 -mfloat-abi=softfp"]
4618 # Return 1 if this is an ARM target supporting -mfpu=vfp
4619 # -mfloat-abi=hard. Some multilibs may be incompatible with these
4622 proc check_effective_target_arm_hard_vfp_ok { } {
4623 if { [check_effective_target_arm32]
4624 && ! [check-flags [list "" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" }]] } {
4625 return [check_no_compiler_messages arm_hard_vfp_ok executable {
4626 int main() { return 0;}
4627 } "-mfpu=vfp -mfloat-abi=hard"]
4633 # Return 1 if this is an ARM target defining __ARM_FP. We may need
4634 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4635 # incompatible with these options. Also set et_arm_fp_flags to the
4636 # best options to add.
4638 proc check_effective_target_arm_fp_ok_nocache { } {
4639 global et_arm_fp_flags
4640 set et_arm_fp_flags ""
4641 if { [check_effective_target_arm32] } {
4642 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4643 if { [check_no_compiler_messages_nocache arm_fp_ok object {
4645 #error __ARM_FP not defined
4648 set et_arm_fp_flags $flags
4657 proc check_effective_target_arm_fp_ok { } {
4658 return [check_cached_effective_target arm_fp_ok \
4659 check_effective_target_arm_fp_ok_nocache]
4662 # Add the options needed to define __ARM_FP. We need either
4663 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4664 # specified by the multilib, use it.
4666 proc add_options_for_arm_fp { flags } {
4667 if { ! [check_effective_target_arm_fp_ok] } {
4670 global et_arm_fp_flags
4671 return "$flags $et_arm_fp_flags"
4674 # Return 1 if this is an ARM target defining __ARM_FP with
4675 # double-precision support. We may need -mfloat-abi=softfp or
4676 # equivalent options. Some multilibs may be incompatible with these
4677 # options. Also set et_arm_fp_dp_flags to the best options to add.
4679 proc check_effective_target_arm_fp_dp_ok_nocache { } {
4680 global et_arm_fp_dp_flags
4681 set et_arm_fp_dp_flags ""
4682 if { [check_effective_target_arm32] } {
4683 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4684 if { [check_no_compiler_messages_nocache arm_fp_dp_ok object {
4686 #error __ARM_FP not defined
4688 #if ((__ARM_FP & 8) == 0)
4689 #error __ARM_FP indicates that double-precision is not supported
4692 set et_arm_fp_dp_flags $flags
4701 proc check_effective_target_arm_fp_dp_ok { } {
4702 return [check_cached_effective_target arm_fp_dp_ok \
4703 check_effective_target_arm_fp_dp_ok_nocache]
4706 # Add the options needed to define __ARM_FP with double-precision
4707 # support. We need either -mfloat-abi=softfp or -mfloat-abi=hard, but
4708 # if one is already specified by the multilib, use it.
4710 proc add_options_for_arm_fp_dp { flags } {
4711 if { ! [check_effective_target_arm_fp_dp_ok] } {
4714 global et_arm_fp_dp_flags
4715 return "$flags $et_arm_fp_dp_flags"
4718 # Return 1 if this is an ARM target that supports DSP multiply with
4719 # current multilib flags.
4721 proc check_effective_target_arm_dsp { } {
4722 return [check_no_compiler_messages arm_dsp assembly {
4723 #ifndef __ARM_FEATURE_DSP
4726 #include <arm_acle.h>
4731 # Return 1 if this is an ARM target that supports unaligned word/halfword
4732 # load/store instructions.
4734 proc check_effective_target_arm_unaligned { } {
4735 return [check_no_compiler_messages arm_unaligned assembly {
4736 #ifndef __ARM_FEATURE_UNALIGNED
4737 #error no unaligned support
4743 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4744 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4745 # incompatible with these options. Also set et_arm_crypto_flags to the
4746 # best options to add.
4748 proc check_effective_target_arm_crypto_ok_nocache { } {
4749 global et_arm_crypto_flags
4750 set et_arm_crypto_flags ""
4751 if { [check_effective_target_arm_v8_neon_ok] } {
4752 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=crypto-neon-fp-armv8" "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"} {
4753 if { [check_no_compiler_messages_nocache arm_crypto_ok object {
4754 #include "arm_neon.h"
4756 foo (uint8x16_t a, uint8x16_t b)
4758 return vaeseq_u8 (a, b);
4761 set et_arm_crypto_flags $flags
4770 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4772 proc check_effective_target_arm_crypto_ok { } {
4773 return [check_cached_effective_target arm_crypto_ok \
4774 check_effective_target_arm_crypto_ok_nocache]
4777 # Add options for crypto extensions.
4778 proc add_options_for_arm_crypto { flags } {
4779 if { ! [check_effective_target_arm_crypto_ok] } {
4782 global et_arm_crypto_flags
4783 return "$flags $et_arm_crypto_flags"
4786 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4787 # or -mfloat-abi=hard, but if one is already specified by the
4788 # multilib, use it. Similarly, if a -mfpu option already enables
4789 # NEON, do not add -mfpu=neon.
4791 proc add_options_for_arm_neon { flags } {
4792 if { ! [check_effective_target_arm_neon_ok] } {
4795 global et_arm_neon_flags
4796 return "$flags $et_arm_neon_flags"
4799 proc add_options_for_arm_v8_vfp { flags } {
4800 if { ! [check_effective_target_arm_v8_vfp_ok] } {
4803 return "$flags -mfpu=fp-armv8 -mfloat-abi=softfp"
4806 proc add_options_for_arm_v8_neon { flags } {
4807 if { ! [check_effective_target_arm_v8_neon_ok] } {
4810 global et_arm_v8_neon_flags
4811 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4814 # Add the options needed for ARMv8.1 Adv.SIMD. Also adds the ARMv8 NEON
4815 # options for AArch64 and for ARM.
4817 proc add_options_for_arm_v8_1a_neon { flags } {
4818 if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
4821 global et_arm_v8_1a_neon_flags
4822 return "$flags $et_arm_v8_1a_neon_flags"
4825 # Add the options needed for ARMv8.2 with the scalar FP16 extension.
4826 # Also adds the ARMv8 FP options for ARM and for AArch64.
4828 proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
4829 if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
4832 global et_arm_v8_2a_fp16_scalar_flags
4833 return "$flags $et_arm_v8_2a_fp16_scalar_flags"
4836 # Add the options needed for ARMv8.2 with the FP16 extension. Also adds
4837 # the ARMv8 NEON options for ARM and for AArch64.
4839 proc add_options_for_arm_v8_2a_fp16_neon { flags } {
4840 if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
4843 global et_arm_v8_2a_fp16_neon_flags
4844 return "$flags $et_arm_v8_2a_fp16_neon_flags"
4847 proc add_options_for_arm_crc { flags } {
4848 if { ! [check_effective_target_arm_crc_ok] } {
4851 global et_arm_crc_flags
4852 return "$flags $et_arm_crc_flags"
4855 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4856 # or -mfloat-abi=hard, but if one is already specified by the
4857 # multilib, use it. Similarly, if a -mfpu option already enables
4858 # NEON, do not add -mfpu=neon.
4860 proc add_options_for_arm_neonv2 { flags } {
4861 if { ! [check_effective_target_arm_neonv2_ok] } {
4864 global et_arm_neonv2_flags
4865 return "$flags $et_arm_neonv2_flags"
4868 # Add the options needed for vfp3.
4869 proc add_options_for_arm_vfp3 { flags } {
4870 if { ! [check_effective_target_arm_vfp3_ok] } {
4873 return "$flags -mfpu=vfp3 -mfloat-abi=softfp"
4876 # Return 1 if this is an ARM target supporting -mfpu=neon
4877 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4878 # incompatible with these options. Also set et_arm_neon_flags to the
4879 # best options to add.
4881 proc check_effective_target_arm_neon_ok_nocache { } {
4882 global et_arm_neon_flags
4883 set et_arm_neon_flags ""
4884 if { [check_effective_target_arm32] } {
4885 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -march=armv7-a"} {
4886 if { [check_no_compiler_messages_nocache arm_neon_ok object {
4887 #include <arm_neon.h>
4889 #ifndef __ARM_NEON__
4892 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
4893 configured for -mcpu=arm926ej-s, for example. */
4894 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M'
4895 #error Architecture does not support NEON.
4898 set et_arm_neon_flags $flags
4907 proc check_effective_target_arm_neon_ok { } {
4908 return [check_cached_effective_target arm_neon_ok \
4909 check_effective_target_arm_neon_ok_nocache]
4913 # Return 1 if this is an ARM target supporting the SIMD32 intrinsics
4914 # from arm_acle.h. Some multilibs may be incompatible with these options.
4915 # Also set et_arm_simd32_flags to the best options to add.
4916 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4917 # -mfloat-abi= options.
4919 proc check_effective_target_arm_simd32_ok_nocache { } {
4920 global et_arm_simd32_flags
4921 set et_arm_simd32_flags ""
4922 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard"} {
4923 if { [check_no_compiler_messages_nocache arm_simd32_ok object {
4924 #include <arm_acle.h>
4926 #ifndef __ARM_FEATURE_SIMD32
4930 set et_arm_simd32_flags $flags
4938 proc check_effective_target_arm_simd32_ok { } {
4939 return [check_cached_effective_target arm_simd32_ok \
4940 check_effective_target_arm_simd32_ok_nocache]
4943 proc add_options_for_arm_simd32 { flags } {
4944 if { ! [check_effective_target_arm_simd32_ok] } {
4947 global et_arm_simd32_flags
4948 return "$flags $et_arm_simd32_flags"
4951 # Return 1 if this is an ARM target supporting the __ssat and __usat
4952 # saturation intrinsics from arm_acle.h. Some multilibs may be
4953 # incompatible with these options. Also set et_arm_sat_flags to the
4954 # best options to add. arm_acle.h includes stdint.h which can cause
4955 # trouble with incompatible -mfloat-abi= options.
4957 proc check_effective_target_arm_sat_ok_nocache { } {
4958 global et_arm_sat_flags
4959 set et_arm_sat_flags ""
4960 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard -mfpu=vfp"} {
4961 if { [check_no_compiler_messages_nocache et_arm_sat_flags object {
4962 #include <arm_acle.h>
4964 #ifndef __ARM_FEATURE_SAT
4968 set et_arm_sat_flags $flags
4976 proc check_effective_target_arm_sat_ok { } {
4977 return [check_cached_effective_target et_arm_sat_flags \
4978 check_effective_target_arm_sat_ok_nocache]
4981 proc add_options_for_arm_sat { flags } {
4982 if { ! [check_effective_target_arm_sat_ok] } {
4985 global et_arm_sat_flags
4986 return "$flags $et_arm_sat_flags"
4989 # Return 1 if this is an ARM target supporting the DSP intrinsics from
4990 # arm_acle.h. Some multilibs may be incompatible with these options.
4991 # Also set et_arm_dsp_flags to the best options to add.
4992 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4993 # -mfloat-abi= options.
4994 # check_effective_target_arm_dsp also exists, which checks the current
4995 # multilib, without trying other options.
4997 proc check_effective_target_arm_dsp_ok_nocache { } {
4998 global et_arm_dsp_flags
4999 set et_arm_dsp_flags ""
5000 foreach flags {"" "-march=armv5te" "-march=armv5te -mfloat-abi=softfp" "-march=armv5te -mfloat-abi=hard"} {
5001 if { [check_no_compiler_messages_nocache et_arm_dsp_ok object {
5002 #include <arm_acle.h>
5004 #ifndef __ARM_FEATURE_DSP
5008 set et_arm_dsp_flags $flags
5016 proc check_effective_target_arm_dsp_ok { } {
5017 return [check_cached_effective_target et_arm_dsp_flags \
5018 check_effective_target_arm_dsp_ok_nocache]
5021 proc add_options_for_arm_dsp { flags } {
5022 if { ! [check_effective_target_arm_dsp_ok] } {
5025 global et_arm_dsp_flags
5026 return "$flags $et_arm_dsp_flags"
5029 # Return 1 if this is an ARM target supporting -mfpu=neon without any
5030 # -mfloat-abi= option. Useful in tests where add_options is not
5031 # supported (such as lto tests).
5033 proc check_effective_target_arm_neon_ok_no_float_abi_nocache { } {
5034 if { [check_effective_target_arm32] } {
5035 foreach flags {"-mfpu=neon"} {
5036 if { [check_no_compiler_messages_nocache arm_neon_ok_no_float_abi object {
5037 #include <arm_neon.h>
5039 #ifndef __ARM_NEON__
5042 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
5043 configured for -mcpu=arm926ej-s, for example. */
5044 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M'
5045 #error Architecture does not support NEON.
5056 proc check_effective_target_arm_neon_ok_no_float_abi { } {
5057 return [check_cached_effective_target arm_neon_ok_no_float_abi \
5058 check_effective_target_arm_neon_ok_no_float_abi_nocache]
5061 proc check_effective_target_arm_crc_ok_nocache { } {
5062 global et_arm_crc_flags
5063 set et_arm_crc_flags "-march=armv8-a+crc"
5064 return [check_no_compiler_messages_nocache arm_crc_ok object {
5065 #if !defined (__ARM_FEATURE_CRC32)
5068 #include <arm_acle.h>
5069 } "$et_arm_crc_flags"]
5072 proc check_effective_target_arm_crc_ok { } {
5073 return [check_cached_effective_target arm_crc_ok \
5074 check_effective_target_arm_crc_ok_nocache]
5077 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5078 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5079 # incompatible with these options. Also set et_arm_neon_fp16_flags to
5080 # the best options to add.
5082 proc check_effective_target_arm_neon_fp16_ok_nocache { } {
5083 global et_arm_neon_fp16_flags
5084 global et_arm_neon_flags
5085 set et_arm_neon_fp16_flags ""
5086 if { [check_effective_target_arm32]
5087 && [check_effective_target_arm_neon_ok] } {
5088 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5089 "-mfpu=neon-fp16 -mfloat-abi=softfp"
5090 "-mfp16-format=ieee"
5091 "-mfloat-abi=softfp -mfp16-format=ieee"
5092 "-mfpu=neon-fp16 -mfp16-format=ieee"
5093 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5094 if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
5095 #include "arm_neon.h"
5097 foo (float32x4_t arg)
5099 return vcvt_f16_f32 (arg);
5101 } "$et_arm_neon_flags $flags"] } {
5102 set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
5111 proc check_effective_target_arm_neon_fp16_ok { } {
5112 return [check_cached_effective_target arm_neon_fp16_ok \
5113 check_effective_target_arm_neon_fp16_ok_nocache]
5116 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5117 # and -mfloat-abi=softfp together. Some multilibs may be
5118 # incompatible with these options. Also set et_arm_neon_softfp_fp16_flags to
5119 # the best options to add.
5121 proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } {
5122 global et_arm_neon_softfp_fp16_flags
5123 global et_arm_neon_flags
5124 set et_arm_neon_softfp_fp16_flags ""
5125 if { [check_effective_target_arm32]
5126 && [check_effective_target_arm_neon_ok] } {
5127 foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp"
5128 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5129 if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object {
5130 #include "arm_neon.h"
5132 foo (float32x4_t arg)
5134 return vcvt_f16_f32 (arg);
5136 } "$et_arm_neon_flags $flags"] } {
5137 set et_arm_neon_softfp_fp16_flags [concat $et_arm_neon_flags $flags]
5146 proc check_effective_target_arm_neon_softfp_fp16_ok { } {
5147 return [check_cached_effective_target arm_neon_softfp_fp16_ok \
5148 check_effective_target_arm_neon_softfp_fp16_ok_nocache]
5153 proc check_effective_target_arm_neon_fp16_hw { } {
5154 if {! [check_effective_target_arm_neon_fp16_ok] } {
5157 global et_arm_neon_fp16_flags
5158 check_runtime arm_neon_fp16_hw {
5160 main (int argc, char **argv)
5162 asm ("vcvt.f32.f16 q1, d0");
5165 } $et_arm_neon_fp16_flags
5168 proc add_options_for_arm_neon_fp16 { flags } {
5169 if { ! [check_effective_target_arm_neon_fp16_ok] } {
5172 global et_arm_neon_fp16_flags
5173 return "$flags $et_arm_neon_fp16_flags"
5176 proc add_options_for_arm_neon_softfp_fp16 { flags } {
5177 if { ! [check_effective_target_arm_neon_softfp_fp16_ok] } {
5180 global et_arm_neon_softfp_fp16_flags
5181 return "$flags $et_arm_neon_softfp_fp16_flags"
5184 proc add_options_for_aarch64_sve { flags } {
5185 if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
5188 return "$flags -march=armv8.2-a+sve"
5191 # Return 1 if this is an ARM target supporting the FP16 alternative
5192 # format. Some multilibs may be incompatible with the options needed. Also
5193 # set et_arm_neon_fp16_flags to the best options to add.
5195 proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
5196 if { [istarget *-*-vxworks7*] } {
5197 # Not supported by the target system.
5200 global et_arm_neon_fp16_flags
5201 set et_arm_neon_fp16_flags ""
5202 if { [check_effective_target_arm32] } {
5203 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5204 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5205 if { [check_no_compiler_messages_nocache \
5206 arm_fp16_alternative_ok object {
5207 #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5208 #error __ARM_FP16_FORMAT_ALTERNATIVE not defined
5210 } "$flags -mfp16-format=alternative"] } {
5211 set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative"
5220 proc check_effective_target_arm_fp16_alternative_ok { } {
5221 return [check_cached_effective_target arm_fp16_alternative_ok \
5222 check_effective_target_arm_fp16_alternative_ok_nocache]
5225 # Return 1 if this is an ARM target supports specifying the FP16 none
5226 # format. Some multilibs may be incompatible with the options needed.
5228 proc check_effective_target_arm_fp16_none_ok_nocache { } {
5229 if { [check_effective_target_arm32] } {
5230 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5231 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5232 if { [check_no_compiler_messages_nocache \
5233 arm_fp16_none_ok object {
5234 #if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5235 #error __ARM_FP16_FORMAT_ALTERNATIVE defined
5237 #if defined (__ARM_FP16_FORMAT_IEEE)
5238 #error __ARM_FP16_FORMAT_IEEE defined
5240 } "$flags -mfp16-format=none"] } {
5249 proc check_effective_target_arm_fp16_none_ok { } {
5250 return [check_cached_effective_target arm_fp16_none_ok \
5251 check_effective_target_arm_fp16_none_ok_nocache]
5254 # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
5255 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5256 # incompatible with these options. Also set et_arm_v8_neon_flags to the
5257 # best options to add.
5259 proc check_effective_target_arm_v8_neon_ok_nocache { } {
5260 global et_arm_v8_neon_flags
5261 set et_arm_v8_neon_flags ""
5262 if { [check_effective_target_arm32] } {
5263 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5264 if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {
5266 #error not armv8 or later
5268 #include "arm_neon.h"
5272 __asm__ volatile ("vrintn.f32 q0, q0");
5274 } "$flags -march=armv8-a"] } {
5275 set et_arm_v8_neon_flags $flags
5284 proc check_effective_target_arm_v8_neon_ok { } {
5285 return [check_cached_effective_target arm_v8_neon_ok \
5286 check_effective_target_arm_v8_neon_ok_nocache]
5289 # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4
5290 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5291 # incompatible with these options. Also set et_arm_neonv2_flags to the
5292 # best options to add.
5294 proc check_effective_target_arm_neonv2_ok_nocache { } {
5295 global et_arm_neonv2_flags
5296 global et_arm_neon_flags
5297 set et_arm_neonv2_flags ""
5298 if { [check_effective_target_arm32]
5299 && [check_effective_target_arm_neon_ok] } {
5300 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
5301 if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
5302 #include "arm_neon.h"
5304 foo (float32x2_t a, float32x2_t b, float32x2_t c)
5306 return vfma_f32 (a, b, c);
5308 } "$et_arm_neon_flags $flags"] } {
5309 set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
5318 proc check_effective_target_arm_neonv2_ok { } {
5319 return [check_cached_effective_target arm_neonv2_ok \
5320 check_effective_target_arm_neonv2_ok_nocache]
5323 # Add the options needed for VFP FP16 support. We need either
5324 # -mfloat-abi=softfp or -mfloat-abi=hard. If one is already specified by
5325 # the multilib, use it.
5327 proc add_options_for_arm_fp16 { flags } {
5328 if { ! [check_effective_target_arm_fp16_ok] } {
5331 global et_arm_fp16_flags
5332 return "$flags $et_arm_fp16_flags"
5335 # Add the options needed to enable support for IEEE format
5336 # half-precision support. This is valid for ARM targets.
5338 proc add_options_for_arm_fp16_ieee { flags } {
5339 if { ! [check_effective_target_arm_fp16_ok] } {
5342 global et_arm_fp16_flags
5343 return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
5346 # Add the options needed to enable support for ARM Alternative format
5347 # half-precision support. This is valid for ARM targets.
5349 proc add_options_for_arm_fp16_alternative { flags } {
5350 if { ! [check_effective_target_arm_fp16_ok] } {
5353 global et_arm_fp16_flags
5354 return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
5357 # Return 1 if this is an ARM target that can support a VFP fp16 variant.
5358 # Skip multilibs that are incompatible with these options and set
5359 # et_arm_fp16_flags to the best options to add. This test is valid for
5362 proc check_effective_target_arm_fp16_ok_nocache { } {
5363 global et_arm_fp16_flags
5364 set et_arm_fp16_flags ""
5365 if { ! [check_effective_target_arm32] } {
5369 [list "" { *-*-* } { "-mfpu=*" } \
5370 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
5371 "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
5372 # Multilib flags would override -mfpu.
5375 if [check-flags [list "" { *-*-* } { "-mfloat-abi=soft" } { "" } ]] {
5376 # Must generate floating-point instructions.
5379 if [check_effective_target_arm_hf_eabi] {
5380 # Use existing float-abi and force an fpu which supports fp16
5381 set et_arm_fp16_flags "-mfpu=vfpv4"
5384 if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "" } ]] {
5385 # The existing -mfpu value is OK; use it, but add softfp.
5386 set et_arm_fp16_flags "-mfloat-abi=softfp"
5389 # Add -mfpu for a VFP fp16 variant since there is no preprocessor
5390 # macro to check for this support.
5391 set flags "-mfpu=vfpv4 -mfloat-abi=softfp"
5392 if { [check_no_compiler_messages_nocache arm_fp16_ok assembly {
5395 set et_arm_fp16_flags "$flags"
5402 proc check_effective_target_arm_fp16_ok { } {
5403 return [check_cached_effective_target arm_fp16_ok \
5404 check_effective_target_arm_fp16_ok_nocache]
5407 # Return 1 if the target supports executing VFP FP16 instructions, 0
5408 # otherwise. This test is valid for ARM only.
5410 proc check_effective_target_arm_fp16_hw { } {
5411 if {! [check_effective_target_arm_fp16_ok] } {
5414 global et_arm_fp16_flags
5415 check_runtime arm_fp16_hw {
5417 main (int argc, char **argv)
5421 asm ("vcvtb.f32.f16 %0, %1"
5422 : "=w" (r) : "w" (a)
5423 : /* No clobbers. */);
5424 return (r == 1.0) ? 0 : 1;
5426 } "$et_arm_fp16_flags -mfp16-format=ieee"
5429 # Creates a series of routines that return 1 if the given architecture
5430 # can be selected and a routine to give the flags to select that architecture
5431 # Note: Extra flags may be added to disable options from newer compilers
5432 # (Thumb in particular - but others may be added in the future).
5433 # Warning: Do not use check_effective_target_arm_arch_*_ok for architecture
5434 # extension (eg. ARMv8.1-A) since there is no macro defined for them. See
5435 # how only __ARM_ARCH_8A__ is checked for ARMv8.1-A.
5436 # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
5437 # /* { dg-add-options arm_arch_v5t } */
5438 # /* { dg-require-effective-target arm_arch_v5t_multilib } */
5439 foreach { armfunc armflag armdefs } {
5440 v4 "-march=armv4 -marm" __ARM_ARCH_4__
5441 v4t "-march=armv4t -mfloat-abi=softfp" __ARM_ARCH_4T__
5442 v4t_arm "-march=armv4t -marm" "__ARM_ARCH_4T__ && !__thumb__"
5443 v4t_thumb "-march=armv4t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_4T__ && __thumb__"
5444 v5t "-march=armv5t -mfloat-abi=softfp" __ARM_ARCH_5T__
5445 v5t_arm "-march=armv5t -marm" "__ARM_ARCH_5T__ && !__thumb__"
5446 v5t_thumb "-march=armv5t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5T__ && __thumb__"
5447 v5te "-march=armv5te+fp -mfloat-abi=softfp" __ARM_ARCH_5TE__
5448 v5te_arm "-march=armv5te+fp -marm" "__ARM_ARCH_5TE__ && !__thumb__"
5449 v5te_thumb "-march=armv5te+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5TE__ && __thumb__"
5450 xscale_arm "-mcpu=xscale -mfloat-abi=soft -marm" "__XSCALE__ && !__thumb__"
5451 v6 "-march=armv6+fp -mfloat-abi=softfp" __ARM_ARCH_6__
5452 v6_arm "-march=armv6+fp -marm" "__ARM_ARCH_6__ && !__thumb__"
5453 v6_thumb "-march=armv6+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6__ && __thumb__"
5454 v6k "-march=armv6k+fp -mfloat-abi=softfp" __ARM_ARCH_6K__
5455 v6k_arm "-march=armv6k+fp -marm" "__ARM_ARCH_6K__ && !__thumb__"
5456 v6k_thumb "-march=armv6k+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6K__ && __thumb__"
5457 v6t2 "-march=armv6t2+fp" __ARM_ARCH_6T2__
5458 v6z "-march=armv6z+fp -mfloat-abi=softfp" __ARM_ARCH_6Z__
5459 v6z_arm "-march=armv6z+fp -marm" "__ARM_ARCH_6Z__ && !__thumb__"
5460 v6z_thumb "-march=armv6z+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6Z__ && __thumb__"
5461 v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
5462 v7a "-march=armv7-a+fp" __ARM_ARCH_7A__
5463 v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__"
5464 v7a_neon "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp" "__ARM_ARCH_7A__ && __ARM_NEON__"
5465 v7r "-march=armv7-r+fp" __ARM_ARCH_7R__
5466 v7m "-march=armv7-m -mthumb -mfloat-abi=soft" __ARM_ARCH_7M__
5467 v7em "-march=armv7e-m+fp -mthumb" __ARM_ARCH_7EM__
5468 v7ve "-march=armv7ve+fp -marm"
5469 "__ARM_ARCH_7A__ && __ARM_FEATURE_IDIV"
5470 v8a "-march=armv8-a+simd" __ARM_ARCH_8A__
5471 v8a_hard "-march=armv8-a+simd -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_8A__
5472 v8_1a "-march=armv8.1-a+simd" __ARM_ARCH_8A__
5473 v8_2a "-march=armv8.2-a+simd" __ARM_ARCH_8A__
5474 v8r "-march=armv8-r+fp.sp" __ARM_ARCH_8R__
5475 v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
5476 __ARM_ARCH_8M_BASE__
5477 v8m_main "-march=armv8-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5478 v8_1m_main "-march=armv8.1-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5479 v9a "-march=armv9-a+simd" __ARM_ARCH_9A__ } {
5480 eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
5481 proc check_effective_target_arm_arch_FUNC_ok { } {
5482 return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
5494 proc add_options_for_arm_arch_FUNC { flags } {
5495 return "$flags FLAG"
5498 proc check_effective_target_arm_arch_FUNC_link { } {
5499 return [check_no_compiler_messages arm_arch_FUNC_link executable {
5502 int main (void) { return 0; }
5503 } [add_options_for_arm_arch_FUNC ""]]
5506 proc check_effective_target_arm_arch_FUNC_multilib { } {
5507 return [check_runtime arm_arch_FUNC_multilib {
5513 } [add_options_for_arm_arch_FUNC ""]]
5518 # Return 1 if GCC was configured with --with-mode=
5519 proc check_effective_target_default_mode { } {
5521 return [check_configured_with "with-mode="]
5524 # Return 1 if this is an ARM target where -marm causes ARM to be
5527 proc check_effective_target_arm_arm_ok { } {
5528 return [check_no_compiler_messages arm_arm_ok assembly {
5529 #if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
5530 #error !__arm__ || __thumb__ || __thumb2__
5536 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
5539 proc check_effective_target_arm_thumb1_ok { } {
5540 return [check_no_compiler_messages arm_thumb1_ok assembly {
5541 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5542 #error !__arm__ || !__thumb__ || __thumb2__
5544 int foo (int i) { return i; }
5548 # Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be
5551 proc check_effective_target_arm_thumb2_ok { } {
5552 return [check_no_compiler_messages arm_thumb2_ok assembly {
5553 #if !defined(__thumb2__)
5556 int foo (int i) { return i; }
5560 # Return 1 if this is an ARM target where Thumb-1 is used without options
5561 # added by the test.
5563 proc check_effective_target_arm_thumb1 { } {
5564 return [check_no_compiler_messages arm_thumb1 assembly {
5565 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5566 #error !__arm__ || !__thumb__ || __thumb2__
5572 # Return 1 if this is an ARM target where Thumb-2 is used without options
5573 # added by the test.
5575 proc check_effective_target_arm_thumb2 { } {
5576 return [check_no_compiler_messages arm_thumb2 assembly {
5577 #if !defined(__thumb2__)
5584 # Return 1 if this is an ARM target where conditional execution is available.
5586 proc check_effective_target_arm_cond_exec { } {
5587 return [check_no_compiler_messages arm_cond_exec assembly {
5588 #if defined(__arm__) && defined(__thumb__) && !defined(__thumb2__)
5595 # Return 1 if this is an ARM cortex-M profile cpu
5597 proc check_effective_target_arm_cortex_m { } {
5598 if { ![istarget arm*-*-*] } {
5601 return [check_no_compiler_messages arm_cortex_m assembly {
5602 #if defined(__ARM_ARCH_ISA_ARM)
5603 #error __ARM_ARCH_ISA_ARM is defined
5609 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5610 # used and MOVT/MOVW instructions to be available.
5612 proc check_effective_target_arm_thumb1_movt_ok {} {
5613 if [check_effective_target_arm_thumb1_ok] {
5614 return [check_no_compiler_messages arm_movt object {
5618 asm ("movt r0, #42");
5626 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5627 # used and CBZ and CBNZ instructions are available.
5629 proc check_effective_target_arm_thumb1_cbz_ok {} {
5630 if [check_effective_target_arm_thumb1_ok] {
5631 return [check_no_compiler_messages arm_cbz object {
5635 asm ("cbz r0, 2f\n2:");
5643 # Return 1 if this is an Arm target which supports the Armv6t2 extensions.
5644 # This can be either in Arm state or in Thumb state.
5646 proc check_effective_target_arm_arch_v6t2_hw {} {
5647 if [check_effective_target_arm_arch_v6t2_ok] {
5648 return [check_runtime arm_arch_v6t2 {
5652 asm ("bfc r0, #1, #2");
5655 } [add_options_for_arm_arch_v6t2 ""]]
5661 # Return 1 if this is an ARM target where ARMv8-M Security Extensions is
5664 proc check_effective_target_arm_cmse_ok {} {
5665 return [check_no_compiler_messages arm_cmse object {
5674 # Return 1 if the target supports executing CMSE instructions, 0
5675 # otherwise. Cache the result.
5677 proc check_effective_target_arm_cmse_hw { } {
5678 return [check_runtime arm_cmse_hw_available {
5682 asm ("ldr\t%0, =0xe000ed44\n" \
5684 "sg" : "=l" (id_pfr1));
5685 /* Exit with code 0 iff security extension is available. */
5686 return !(id_pfr1 & 0xf0);
5691 # Return 1 if the target supports executing MVE instructions, 0
5694 proc check_effective_target_arm_mve_hw {} {
5695 return [check_runtime arm_mve_hw_available {
5701 asm ("sqrshrl %Q1, %R1, #64, %2"
5703 : "0" (a), "r" (b));
5706 } [add_options_for_arm_v8_1m_mve_fp ""]]
5709 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
5710 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.
5712 proc check_effective_target_arm_cmse_clear_ok {} {
5713 return [check_no_compiler_messages arm_cmse_clear object {
5717 asm ("clrm {r1, r2}");
5722 # Return 1 if this is an ARM target supporting
5723 # -mbranch-protection=standard, 0 otherwise.
5725 proc check_effective_target_mbranch_protection_ok {} {
5727 return [check_no_compiler_messages mbranch_protection_ok object {
5728 int main (void) { return 0; }
5729 } "-mbranch-protection=standard"]
5732 # Return 1 if the target supports executing PACBTI instructions, 0
5735 proc check_effective_target_arm_pacbti_hw {} {
5736 return [check_runtime arm_pacbti_hw_available {
5737 __attribute__ ((naked)) int
5740 asm ("pac r12, lr, sp");
5742 asm ("autg r12, lr, sp");
5745 } "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mthumb -mfloat-abi=hard"]
5748 # Return 1 if this compilation turns on string_ops_prefer_neon on.
5750 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
5751 return [check_no_messages_and_pattern arm_tune_string_ops_prefer_neon "@string_ops_prefer_neon:\t1" assembly {
5752 int foo (void) { return 0; }
5753 } "-O2 -mprint-tune-info" ]
5756 # Return 1 if the target supports executing NEON instructions, 0
5757 # otherwise. Cache the result.
5759 proc check_effective_target_arm_neon_hw { } {
5760 return [check_runtime arm_neon_hw_available {
5764 long long a = 0, b = 1;
5765 asm ("vorr %P0, %P1, %P2"
5767 : "0" (a), "w" (b));
5770 } [add_options_for_arm_neon ""]]
5773 # Return true if this is an AArch64 target that can run SVE code.
5775 proc check_effective_target_aarch64_sve_hw { } {
5776 if { ![istarget aarch64*-*-*] } {
5779 return [check_runtime aarch64_sve_hw_available {
5783 asm volatile ("ptrue p0.b");
5786 } [add_options_for_aarch64_sve ""]]
5789 # Return true if this is an AArch64 target that can run SVE2 code.
5791 proc check_effective_target_aarch64_sve2_hw { } {
5792 if { ![istarget aarch64*-*-*] } {
5795 return [check_runtime aarch64_sve2_hw_available {
5799 asm volatile ("addp z0.b, p0/m, z0.b, z1.b");
5805 # Return true if this is an AArch64 target that can run SVE code and
5806 # if its SVE vectors have exactly BITS bits.
5808 proc aarch64_sve_hw_bits { bits } {
5809 if { ![check_effective_target_aarch64_sve_hw] } {
5812 return [check_runtime aarch64_sve${bits}_hw [subst {
5817 asm volatile ("cntd %0" : "=r" (res));
5818 if (res * 64 != $bits)
5822 }] [add_options_for_aarch64_sve ""]]
5825 # Return true if this is an AArch64 target that can run SVE code and
5826 # if its SVE vectors have exactly 256 bits.
5828 foreach N { 128 256 512 1024 2048 } {
5829 eval [string map [list N $N] {
5830 proc check_effective_target_aarch64_sveN_hw { } {
5831 return [aarch64_sve_hw_bits N]
5836 proc check_effective_target_arm_neonv2_hw { } {
5837 return [check_runtime arm_neon_hwv2_available {
5838 #include "arm_neon.h"
5842 float32x2_t a, b, c;
5843 asm ("vfma.f32 %P0, %P1, %P2"
5845 : "w" (b), "w" (c));
5848 } [add_options_for_arm_neonv2 ""]]
5851 # ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented.
5852 proc check_effective_target_aarch64_bti_hw { } {
5853 if { ![istarget aarch64*-*-*] } {
5856 return [check_runtime aarch64_bti_hw_available {
5861 asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a));
5862 return !((a & 0xf) == 1);
5867 # Return 1 if the target supports executing the armv8.3-a FJCVTZS
5869 proc check_effective_target_aarch64_fjcvtzs_hw { } {
5870 if { ![istarget aarch64*-*-*] } {
5873 return [check_runtime aarch64_fjcvtzs_hw_available {
5879 asm volatile ("fjcvtzs %w0, %d1"
5882 : /* No clobbers. */);
5885 } "-march=armv8.3-a" ]
5888 # Return 1 if GCC was configured with --enable-standard-branch-protection
5889 proc check_effective_target_default_branch_protection { } {
5890 return [check_configured_with "enable-standard-branch-protection"]
5893 # Return 1 if this is an ARM target supporting -mfloat-abi=softfp.
5895 proc check_effective_target_arm_softfp_ok { } {
5896 return [check_no_compiler_messages arm_softfp_ok object {
5899 int main (void) { return 0; }
5900 } "-mfloat-abi=softfp"]
5903 # Return 1 if this is an ARM target supporting -mfloat-abi=hard.
5905 proc check_effective_target_arm_hard_ok { } {
5906 return [check_no_compiler_messages arm_hard_ok object {
5909 int main (void) { return 0; }
5910 } "-mfloat-abi=hard"]
5913 # Return 1 if this is an ARM target supporting MVE.
5914 proc check_effective_target_arm_mve { } {
5915 if { ![istarget arm*-*-*] } {
5918 return [check_no_compiler_messages arm_mve assembly {
5919 #if !defined (__ARM_FEATURE_MVE)
5925 # Return 1 if the target supports ARMv8.1-M MVE with floating point
5926 # instructions, 0 otherwise. The test is valid for ARM.
5927 # Record the command line options needed.
5929 proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } {
5930 global et_arm_v8_1m_mve_fp_flags
5931 set et_arm_v8_1m_mve_fp_flags ""
5933 if { ![istarget arm*-*-*] } {
5937 # Iterate through sets of options to find the compiler flags that
5938 # need to be added to the -march option.
5939 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp"} {
5940 if { [check_no_compiler_messages_nocache \
5941 arm_v8_1m_mve_fp_ok object {
5942 #include <arm_mve.h>
5943 #if !(__ARM_FEATURE_MVE & 2)
5944 #error "__ARM_FEATURE_MVE for floating point not defined"
5946 #if __ARM_BIG_ENDIAN
5947 #error "MVE intrinsics are not supported in Big-Endian mode."
5949 } "$flags -mthumb"] } {
5950 set et_arm_v8_1m_mve_fp_flags "$flags -mthumb --save-temps"
5958 proc check_effective_target_arm_v8_1m_mve_fp_ok { } {
5959 return [check_cached_effective_target arm_v8_1m_mve_fp_ok \
5960 check_effective_target_arm_v8_1m_mve_fp_ok_nocache]
5963 proc add_options_for_arm_v8_1m_mve_fp { flags } {
5964 if { ! [check_effective_target_arm_v8_1m_mve_fp_ok] } {
5967 global et_arm_v8_1m_mve_fp_flags
5968 return "$flags $et_arm_v8_1m_mve_fp_flags"
5971 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
5972 # otherwise. The test is valid for AArch64 and ARM. Record the command
5973 # line options needed.
5975 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
5976 global et_arm_v8_1a_neon_flags
5977 set et_arm_v8_1a_neon_flags ""
5979 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
5983 # Iterate through sets of options to find the compiler flags that
5984 # need to be added to the -march option. Start with the empty set
5985 # since AArch64 only needs the -march setting.
5986 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
5987 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5988 foreach arches { "-march=armv8-a+rdma" "-march=armv8.1-a" } {
5989 if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
5990 #if !defined (__ARM_FEATURE_QRDMX)
5991 #error "__ARM_FEATURE_QRDMX not defined"
5993 } "$flags $arches"] } {
5994 set et_arm_v8_1a_neon_flags "$flags $arches"
6003 proc check_effective_target_arm_v8_1a_neon_ok { } {
6004 return [check_cached_effective_target arm_v8_1a_neon_ok \
6005 check_effective_target_arm_v8_1a_neon_ok_nocache]
6008 # Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
6009 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6010 # Record the command line options needed.
6012 proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
6013 global et_arm_v8_2a_fp16_scalar_flags
6014 set et_arm_v8_2a_fp16_scalar_flags ""
6016 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6020 # Iterate through sets of options to find the compiler flags that
6021 # need to be added to the -march option.
6022 foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
6023 "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
6024 if { [check_no_compiler_messages_nocache \
6025 arm_v8_2a_fp16_scalar_ok object {
6026 #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
6027 #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
6029 } "$flags -march=armv8.2-a+fp16"] } {
6030 set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
6038 proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
6039 return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
6040 check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
6043 # Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
6044 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6045 # Record the command line options needed.
6047 proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
6048 global et_arm_v8_2a_fp16_neon_flags
6049 set et_arm_v8_2a_fp16_neon_flags ""
6051 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6055 # Iterate through sets of options to find the compiler flags that
6056 # need to be added to the -march option.
6057 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6058 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6059 if { [check_no_compiler_messages_nocache \
6060 arm_v8_2a_fp16_neon_ok object {
6061 #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
6062 #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
6064 } "$flags -march=armv8.2-a+fp16"] } {
6065 set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
6073 proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
6074 return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
6075 check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
6078 # Return 1 if the target supports ARMv8.2 Adv.SIMD Dot Product
6079 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6080 # Record the command line options needed.
6082 proc check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {
6083 global et_arm_v8_2a_dotprod_neon_flags
6084 set et_arm_v8_2a_dotprod_neon_flags ""
6086 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6090 # Iterate through sets of options to find the compiler flags that
6091 # need to be added to the -march option.
6092 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6093 if { [check_no_compiler_messages_nocache \
6094 arm_v8_2a_dotprod_neon_ok object {
6096 #if !defined (__ARM_FEATURE_DOTPROD)
6097 #error "__ARM_FEATURE_DOTPROD not defined"
6099 } "$flags -march=armv8.2-a+dotprod"] } {
6100 set et_arm_v8_2a_dotprod_neon_flags "$flags -march=armv8.2-a+dotprod"
6108 # Return 1 if the target supports ARMv8.1-M MVE
6109 # instructions, 0 otherwise. The test is valid for ARM.
6110 # Record the command line options needed.
6112 proc check_effective_target_arm_v8_1m_mve_ok_nocache { } {
6113 global et_arm_v8_1m_mve_flags
6114 set et_arm_v8_1m_mve_flags ""
6116 if { ![istarget arm*-*-*] } {
6120 # Iterate through sets of options to find the compiler flags that
6121 # need to be added to the -march option.
6122 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve"} {
6123 if { [check_no_compiler_messages_nocache \
6124 arm_v8_1m_mve_ok object {
6125 #if !defined (__ARM_FEATURE_MVE)
6126 #error "__ARM_FEATURE_MVE not defined"
6128 #if __ARM_BIG_ENDIAN
6129 #error "MVE intrinsics are not supported in Big-Endian mode."
6131 #include <arm_mve.h>
6132 } "$flags -mthumb"] } {
6133 set et_arm_v8_1m_mve_flags "$flags -mthumb --save-temps"
6141 proc check_effective_target_arm_v8_1m_mve_ok { } {
6142 return [check_cached_effective_target arm_v8_1m_mve_ok \
6143 check_effective_target_arm_v8_1m_mve_ok_nocache]
6146 proc add_options_for_arm_v8_1m_mve { flags } {
6147 if { ! [check_effective_target_arm_v8_1m_mve_ok] } {
6150 global et_arm_v8_1m_mve_flags
6151 return "$flags $et_arm_v8_1m_mve_flags"
6154 proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {
6155 return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \
6156 check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]
6159 proc add_options_for_arm_v8_2a_dotprod_neon { flags } {
6160 if { ! [check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6163 global et_arm_v8_2a_dotprod_neon_flags
6164 return "$flags $et_arm_v8_2a_dotprod_neon_flags"
6167 # Return 1 if the target supports ARMv8.2+i8mm Adv.SIMD Dot Product
6168 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6169 # Record the command line options needed.
6171 proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } {
6172 global et_arm_v8_2a_i8mm_flags
6173 set et_arm_v8_2a_i8mm_flags ""
6175 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6179 # Iterate through sets of options to find the compiler flags that
6180 # need to be added to the -march option.
6181 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6182 if { [check_no_compiler_messages_nocache \
6183 arm_v8_2a_i8mm_ok object {
6184 #include <arm_neon.h>
6185 #if !defined (__ARM_FEATURE_MATMUL_INT8)
6186 #error "__ARM_FEATURE_MATMUL_INT8 not defined"
6188 } "$flags -march=armv8.2-a+i8mm"] } {
6189 set et_arm_v8_2a_i8mm_flags "$flags -march=armv8.2-a+i8mm"
6197 proc check_effective_target_arm_v8_2a_i8mm_ok { } {
6198 return [check_cached_effective_target arm_v8_2a_i8mm_ok \
6199 check_effective_target_arm_v8_2a_i8mm_ok_nocache]
6202 proc add_options_for_arm_v8_2a_i8mm { flags } {
6203 if { ! [check_effective_target_arm_v8_2a_i8mm_ok] } {
6206 global et_arm_v8_2a_i8mm_flags
6207 return "$flags $et_arm_v8_2a_i8mm_flags"
6210 # Return 1 if the target supports FP16 VFMAL and VFMSL
6211 # instructions, 0 otherwise.
6212 # Record the command line options needed.
6214 proc check_effective_target_arm_fp16fml_neon_ok_nocache { } {
6215 global et_arm_fp16fml_neon_flags
6216 set et_arm_fp16fml_neon_flags ""
6218 if { ![istarget arm*-*-*] } {
6222 # Iterate through sets of options to find the compiler flags that
6223 # need to be added to the -march option.
6224 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6225 if { [check_no_compiler_messages_nocache \
6226 arm_fp16fml_neon_ok assembly {
6227 #include <arm_neon.h>
6229 foo (float32x2_t r, float16x4_t a, float16x4_t b)
6231 return vfmlal_high_f16 (r, a, b);
6233 } "$flags -march=armv8.2-a+fp16fml"] } {
6234 set et_arm_fp16fml_neon_flags "$flags -march=armv8.2-a+fp16fml"
6242 proc check_effective_target_arm_fp16fml_neon_ok { } {
6243 return [check_cached_effective_target arm_fp16fml_neon_ok \
6244 check_effective_target_arm_fp16fml_neon_ok_nocache]
6247 proc add_options_for_arm_fp16fml_neon { flags } {
6248 if { ! [check_effective_target_arm_fp16fml_neon_ok] } {
6251 global et_arm_fp16fml_neon_flags
6252 return "$flags $et_arm_fp16fml_neon_flags"
6255 # Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise.
6256 # The test is valid for ARM and for AArch64.
6258 proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
6259 global et_arm_v8_2a_bf16_neon_flags
6260 set et_arm_v8_2a_bf16_neon_flags ""
6262 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6266 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6267 if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
6268 #include <arm_neon.h>
6269 #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)
6270 #error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC not defined"
6272 } "$flags -march=armv8.2-a+bf16"] } {
6273 set et_arm_v8_2a_bf16_neon_flags "$flags -march=armv8.2-a+bf16"
6281 proc check_effective_target_arm_v8_2a_bf16_neon_ok { } {
6282 return [check_cached_effective_target arm_v8_2a_bf16_neon_ok \
6283 check_effective_target_arm_v8_2a_bf16_neon_ok_nocache]
6286 proc add_options_for_arm_v8_2a_bf16_neon { flags } {
6287 if { ! [check_effective_target_arm_v8_2a_bf16_neon_ok] } {
6290 global et_arm_v8_2a_bf16_neon_flags
6291 return "$flags $et_arm_v8_2a_bf16_neon_flags"
6294 # A series of routines are created to 1) check if a given architecture is
6295 # effective (check_effective_target_*_ok) and then 2) give the corresponding
6296 # flags that enable the architecture (add_options_for_*).
6297 # The series includes:
6298 # arm_v8m_main_cde: Armv8-m CDE (Custom Datapath Extension).
6299 # arm_v8m_main_cde_fp: Armv8-m CDE with FP registers.
6300 # arm_v8_1m_main_cde_mve: Armv8.1-m CDE with MVE.
6301 # arm_v8_1m_main_cde_mve_fp: Armv8.1-m CDE with MVE with FP support.
6303 # /* { dg-require-effective-target arm_v8m_main_cde_ok } */
6304 # /* { dg-add-options arm_v8m_main_cde } */
6305 # The tests are valid for Arm.
6307 foreach { armfunc armflag armdef arminc } {
6309 "-march=armv8-m.main+cdecp0+cdecp6 -mthumb"
6310 "defined (__ARM_FEATURE_CDE)"
6313 "-march=armv8-m.main+fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6314 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FP)"
6316 arm_v8_1m_main_cde_mve
6317 "-march=armv8.1-m.main+mve+cdecp0+cdecp6 -mthumb -mfpu=auto"
6318 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FEATURE_MVE)"
6319 "#include <arm_mve.h>"
6320 arm_v8_1m_main_cde_mve_fp
6321 "-march=armv8.1-m.main+mve.fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6322 "defined (__ARM_FEATURE_CDE) || __ARM_FEATURE_MVE == 3"
6323 "#include <arm_mve.h>"
6325 eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef INC $arminc ] {
6326 proc check_effective_target_FUNC_ok_nocache { } {
6327 global et_FUNC_flags
6328 set et_FUNC_flags ""
6330 if { ![istarget arm*-*-*] } {
6334 if { [check_no_compiler_messages_nocache FUNC_ok assembly {
6338 #include <arm_cde.h>
6341 set et_FUNC_flags "FLAG"
6348 proc check_effective_target_FUNC_ok { } {
6349 return [check_cached_effective_target FUNC_ok \
6350 check_effective_target_FUNC_ok_nocache]
6353 proc add_options_for_FUNC { flags } {
6354 if { ! [check_effective_target_FUNC_ok] } {
6357 global et_FUNC_flags
6358 return "$flags $et_FUNC_flags"
6361 proc check_effective_target_FUNC_link { } {
6362 if { ! [check_effective_target_FUNC_ok] } {
6365 return [check_no_compiler_messages FUNC_link executable {
6369 #include <arm_cde.h>
6376 } [add_options_for_FUNC ""]]
6379 proc check_effective_target_FUNC_multilib { } {
6380 if { ! [check_effective_target_FUNC_ok] } {
6383 return [check_runtime FUNC_multilib {
6387 #include <arm_cde.h>
6394 } [add_options_for_FUNC ""]]
6399 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
6402 proc check_effective_target_arm_v8_neon_hw { } {
6403 return [check_runtime arm_v8_neon_hw_available {
6404 #include "arm_neon.h"
6408 float32x2_t a = { 1.0f, 2.0f };
6409 #ifdef __ARM_ARCH_ISA_A64
6410 asm ("frinta %0.2s, %1.2s"
6414 asm ("vrinta.f32 %P0, %P1"
6418 return a[0] == 2.0f;
6420 } [add_options_for_arm_v8_neon ""]]
6423 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
6424 # otherwise. The test is valid for AArch64 and ARM.
6426 proc check_effective_target_arm_v8_1a_neon_hw { } {
6427 if { ![check_effective_target_arm_v8_1a_neon_ok] } {
6430 return [check_runtime arm_v8_1a_neon_hw_available {
6434 #ifdef __ARM_ARCH_ISA_A64
6435 __Int32x2_t a = {0, 1};
6436 __Int32x2_t b = {0, 2};
6439 asm ("sqrdmlah %0.2s, %1.2s, %2.2s"
6442 : /* No clobbers. */);
6446 __simd64_int32_t a = {0, 1};
6447 __simd64_int32_t b = {0, 2};
6448 __simd64_int32_t result;
6450 asm ("vqrdmlah.s32 %P0, %P1, %P2"
6453 : /* No clobbers. */);
6458 } [add_options_for_arm_v8_1a_neon ""]]
6461 # Return 1 if the target supports executing floating point instructions from
6462 # ARMv8.2 with the FP16 extension, 0 otherwise. The test is valid for ARM and
6465 proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
6466 if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
6469 return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
6476 #ifdef __ARM_ARCH_ISA_A64
6478 asm ("fabs %h0, %h1"
6481 : /* No clobbers. */);
6485 asm ("vabs.f16 %0, %1"
6488 : /* No clobbers. */);
6492 return (result == 1.0) ? 0 : 1;
6494 } [add_options_for_arm_v8_2a_fp16_scalar ""]]
6497 # Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
6498 # with the FP16 extension, 0 otherwise. The test is valid for ARM and for
6501 proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
6502 if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
6505 return [check_runtime arm_v8_2a_fp16_neon_hw_available {
6509 #ifdef __ARM_ARCH_ISA_A64
6511 __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
6512 __Float16x4_t result;
6514 asm ("fabs %0.4h, %1.4h"
6517 : /* No clobbers. */);
6521 __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
6522 __simd64_float16_t result;
6524 asm ("vabs.f16 %P0, %P1"
6527 : /* No clobbers. */);
6531 return (result[0] == 1.0) ? 0 : 1;
6533 } [add_options_for_arm_v8_2a_fp16_neon ""]]
6536 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6537 # with the Dot Product extension, 0 otherwise. The test is valid for ARM and for
6540 proc check_effective_target_arm_v8_2a_dotprod_neon_hw { } {
6541 if { ![check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6544 return [check_runtime arm_v8_2a_dotprod_neon_hw_available {
6545 #include "arm_neon.h"
6550 uint32x2_t results = {0,0};
6551 uint8x8_t a = {1,1,1,1,2,2,2,2};
6552 uint8x8_t b = {2,2,2,2,3,3,3,3};
6554 #ifdef __ARM_ARCH_ISA_A64
6555 asm ("udot %0.2s, %1.8b, %2.8b"
6558 : /* No clobbers. */);
6561 asm ("vudot.u8 %P0, %P1, %P2"
6564 : /* No clobbers. */);
6567 return (results[0] == 8 && results[1] == 24) ? 1 : 0;
6569 } [add_options_for_arm_v8_2a_dotprod_neon ""]]
6572 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6573 # with the i8mm extension, 0 otherwise. The test is valid for ARM and for
6576 proc check_effective_target_arm_v8_2a_i8mm_neon_hw { } {
6577 if { ![check_effective_target_arm_v8_2a_i8mm_ok] } {
6580 return [check_runtime arm_v8_2a_i8mm_neon_hw_available {
6581 #include "arm_neon.h"
6586 uint32x2_t results = {0,0};
6587 uint8x8_t a = {1,1,1,1,2,2,2,2};
6588 int8x8_t b = {2,2,2,2,3,3,3,3};
6590 #ifdef __ARM_ARCH_ISA_A64
6591 asm ("usdot %0.2s, %1.8b, %2.8b"
6594 : /* No clobbers. */);
6597 asm ("vusdot.u8 %P0, %P1, %P2"
6600 : /* No clobbers. */);
6603 return (vget_lane_u32 (results, 0) == 8
6604 && vget_lane_u32 (results, 1) == 24) ? 1 : 0;
6606 } [add_options_for_arm_v8_2a_i8mm ""]]
6609 # Return 1 if this is a ARM target with NEON enabled.
6611 proc check_effective_target_arm_neon { } {
6612 if { [check_effective_target_arm32] } {
6613 return [check_no_compiler_messages arm_neon object {
6614 #ifndef __ARM_NEON__
6625 proc check_effective_target_arm_neonv2 { } {
6626 if { [check_effective_target_arm32] } {
6627 return [check_no_compiler_messages arm_neon object {
6628 #ifndef __ARM_NEON__
6631 #ifndef __ARM_FEATURE_FMA
6643 # Return 1 if this is an ARM target with load acquire and store release
6644 # instructions for 8-, 16- and 32-bit types.
6646 proc check_effective_target_arm_acq_rel { } {
6647 return [check_no_compiler_messages arm_acq_rel object {
6649 load_acquire_store_release (void)
6651 asm ("lda r0, [r1]\n\t"
6657 : : : "r0", "memory");
6662 # Add the options needed for MIPS Paired-Single.
6664 proc add_options_for_mpaired_single { flags } {
6665 if { ! [check_effective_target_mpaired_single "-mpaired-single"] } {
6668 return "$flags -mpaired-single"
6671 # Add the options needed for MIPS SIMD Architecture.
6673 proc add_options_for_mips_msa { flags } {
6674 if { ! [check_effective_target_mips_msa "-mmsa"] } {
6677 return "$flags -mmsa"
6680 # Add the options needed for MIPS Loongson MMI Architecture.
6682 proc add_options_for_mips_loongson_mmi { flags } {
6683 if { ! [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
6686 return "$flags -mloongson-mmi"
6690 # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
6691 # the Loongson vector modes.
6693 proc check_effective_target_mips_loongson_mmi { args } {
6694 return [check_no_compiler_messages loongson assembly {
6695 #if !defined(__mips_loongson_mmi)
6696 #error !__mips_loongson_mmi
6698 #if !defined(__mips_loongson_vector_rev)
6699 #error !__mips_loongson_vector_rev
6704 # Return 1 if this is a MIPS target that supports the legacy NAN.
6706 proc check_effective_target_mips_nanlegacy { } {
6707 return [check_no_compiler_messages nanlegacy assembly {
6709 int main () { return 0; }
6713 # Return 1 if an MSA program can be compiled to object
6715 proc check_effective_target_mips_msa { args } {
6716 if ![check_effective_target_nomips16] {
6719 return [check_no_compiler_messages msa object {
6720 #if !defined(__mips_msa)
6721 #error "MSA NOT AVAIL"
6723 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
6724 #error "MSA NOT AVAIL FOR ISA REV < 2"
6726 #if !defined(__mips_hard_float)
6727 #error "MSA HARD_FLOAT REQUIRED"
6729 #if __mips_fpr != 64
6730 #error "MSA 64-bit FPR REQUIRED"
6736 v8i16 v = __builtin_msa_ldi_h (1);
6744 # Return 1 if this is an ARM target that adheres to the ABI for the ARM
6747 proc check_effective_target_arm_eabi { } {
6748 return [check_no_compiler_messages arm_eabi object {
6749 #ifndef __ARM_EABI__
6757 # Return 1 if this is an ARM target that adheres to the hard-float variant of
6758 # the ABI for the ARM Architecture (e.g. -mfloat-abi=hard).
6760 proc check_effective_target_arm_hf_eabi { } {
6761 return [check_no_compiler_messages arm_hf_eabi object {
6762 #if !defined(__ARM_EABI__) || !defined(__ARM_PCS_VFP)
6763 #error not hard-float EABI
6770 # Return 1 if this is an ARM target uses emulated floating point
6773 proc check_effective_target_arm_softfloat { } {
6774 return [check_no_compiler_messages arm_softfloat object {
6775 #if !defined(__SOFTFP__)
6776 #error not soft-float EABI
6783 # Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
6784 # Some multilibs may be incompatible with this option.
6786 proc check_effective_target_arm_iwmmxt_ok { } {
6787 if { [check_effective_target_arm32] } {
6788 return [check_no_compiler_messages arm_iwmmxt_ok object {
6796 # Return true if LDRD/STRD instructions are prefered over LDM/STM instructions
6797 # for an ARM target.
6798 proc check_effective_target_arm_prefer_ldrd_strd { } {
6799 if { ![check_effective_target_arm32] } {
6803 return [check_no_messages_and_pattern arm_prefer_ldrd_strd "strd\tr" assembly {
6804 void foo (void) { __asm__ ("" ::: "r4", "r5"); }
6808 # Return true if LDRD/STRD instructions are available on this target.
6809 proc check_effective_target_arm_ldrd_strd_ok { } {
6810 if { ![check_effective_target_arm32] } {
6814 return [check_no_compiler_messages arm_ldrd_strd_ok object {
6817 __UINT64_TYPE__ a = 1, b = 10;
6818 __UINT64_TYPE__ *c = &b;
6819 // `a` will be in a valid register since it's a DImode quantity.
6828 # Return 1 if this is a PowerPC target supporting -meabi.
6830 proc check_effective_target_powerpc_eabi_ok { } {
6831 if { [istarget powerpc*-*-*] } {
6832 return [check_no_compiler_messages powerpc_eabi_ok object {
6840 # Return 1 if this is a PowerPC target with floating-point registers.
6842 proc check_effective_target_powerpc_fprs { } {
6843 if { [istarget powerpc*-*-*]
6844 || [istarget rs6000-*-*] } {
6845 return [check_no_compiler_messages powerpc_fprs object {
6857 # Return 1 if this is a PowerPC target with hardware double-precision
6860 proc check_effective_target_powerpc_hard_double { } {
6861 if { [istarget powerpc*-*-*]
6862 || [istarget rs6000-*-*] } {
6863 return [check_no_compiler_messages powerpc_hard_double object {
6875 # Return 1 if this is a PowerPC target with hardware floating point sqrt.
6877 proc check_effective_target_powerpc_sqrt { } {
6878 # We need to be PowerPC, and we need to have hardware fp enabled.
6879 if {![check_effective_target_powerpc_fprs]} {
6883 return [check_no_compiler_messages powerpc_sqrt object {
6887 #error _ARCH_PPCSQ is not defined
6893 # Return 1 if this is a PowerPC target supporting -maltivec.
6895 proc check_effective_target_powerpc_altivec_ok { } {
6896 # Not PowerPC, then not ok
6897 if { !([istarget powerpc*-*-*] || [istarget rs6000-*-*]) } { return 0 }
6899 # Paired Single, then not ok
6900 if { [istarget powerpc-*-linux*paired*] } { return 0 }
6902 # AltiVec is not supported on AIX before 5.3.
6903 if { [istarget powerpc*-*-aix4*]
6904 || [istarget powerpc*-*-aix5.1*]
6905 || [istarget powerpc*-*-aix5.2*] } { return 0 }
6907 # Return true iff compiling with -maltivec does not error.
6908 return [check_no_compiler_messages powerpc_altivec_ok object {
6913 # Return 1 if this is a PowerPC target supporting -mpower8-vector
6915 proc check_effective_target_powerpc_p8vector_ok { } {
6916 if { ([istarget powerpc*-*-*]
6917 && ![istarget powerpc-*-linux*paired*])
6918 || [istarget rs6000-*-*] } {
6919 # AltiVec is not supported on AIX before 5.3.
6920 if { [istarget powerpc*-*-aix4*]
6921 || [istarget powerpc*-*-aix5.1*]
6922 || [istarget powerpc*-*-aix5.2*] } {
6925 # Darwin doesn't run on power8, so far.
6926 if { [istarget *-*-darwin*] } {
6929 return [check_no_compiler_messages powerpc_p8vector_ok object {
6931 asm volatile ("xxlorc 0,0,0");
6934 } "-mpower8-vector"]
6940 # Return 1 if this is a PowerPC target supporting -mpower9-vector
6942 proc check_effective_target_powerpc_p9vector_ok { } {
6943 if { ([istarget powerpc*-*-*]
6944 && ![istarget powerpc-*-linux*paired*])
6945 || [istarget rs6000-*-*] } {
6946 # AltiVec is not supported on AIX before 5.3.
6947 if { [istarget powerpc*-*-aix4*]
6948 || [istarget powerpc*-*-aix5.1*]
6949 || [istarget powerpc*-*-aix5.2*] } {
6952 # Darwin doesn't run on power9, so far.
6953 if { [istarget *-*-darwin*] } {
6956 return [check_no_compiler_messages powerpc_p9vector_ok object {
6959 vector double v = (vector double) { 0.0, 0.0 };
6960 asm ("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
6963 } "-mpower9-vector"]
6969 # Return 1 if this is a PowerPC target supporting -mmodulo
6971 proc check_effective_target_powerpc_p9modulo_ok { } {
6972 if { ([istarget powerpc*-*-*]
6973 && ![istarget powerpc-*-linux*paired*])
6974 || [istarget rs6000-*-*] } {
6975 # AltiVec is not supported on AIX before 5.3.
6976 if { [istarget powerpc*-*-aix4*]
6977 || [istarget powerpc*-*-aix5.1*]
6978 || [istarget powerpc*-*-aix5.2*] } {
6981 return [check_no_compiler_messages powerpc_p9modulo_ok object {
6983 int i = 5, j = 3, r = -1;
6984 asm ("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
6993 # return 1 if our compiler returns the ARCH_PWR defines with the options
6994 # as provided by the test.
6995 proc check_effective_target_has_arch_pwr5 { } {
6996 return [check_no_compiler_messages_nocache arch_pwr5 assembly {
7000 #error does not have power5 support.
7002 /* "has power5 support" */
7005 } [current_compiler_flags]]
7008 proc check_effective_target_has_arch_pwr6 { } {
7009 return [check_no_compiler_messages_nocache arch_pwr6 assembly {
7013 #error does not have power6 support.
7015 /* "has power6 support" */
7018 } [current_compiler_flags]]
7021 proc check_effective_target_has_arch_pwr7 { } {
7022 return [check_no_compiler_messages_nocache arch_pwr7 assembly {
7026 #error does not have power7 support.
7028 /* "has power7 support" */
7031 } [current_compiler_flags]]
7034 proc check_effective_target_has_arch_pwr8 { } {
7035 return [check_no_compiler_messages_nocache arch_pwr8 assembly {
7039 #error does not have power8 support.
7041 /* "has power8 support" */
7044 } [current_compiler_flags]]
7047 proc check_effective_target_has_arch_pwr9 { } {
7048 return [check_no_compiler_messages_nocache arch_pwr9 assembly {
7052 #error does not have power9 support.
7054 /* "has power9 support" */
7057 } [current_compiler_flags]]
7060 proc check_effective_target_has_arch_pwr10 { } {
7061 return [check_no_compiler_messages_nocache arch_pwr10 assembly {
7065 #error does not have power10 support.
7067 /* "has power10 support" */
7070 } [current_compiler_flags]]
7073 proc check_effective_target_has_arch_ppc64 { } {
7074 return [check_no_compiler_messages_nocache arch_ppc64 assembly {
7078 #error does not have ppc64 support.
7080 /* "has ppc64 support" */
7083 } [current_compiler_flags]]
7086 # Return 1 if this is a PowerPC target supporting -mcpu=power10.
7087 # Limit this to 64-bit linux systems for now until other targets support
7090 proc check_effective_target_power10_ok { } {
7091 if { ([istarget powerpc64*-*-linux*]) } {
7092 return [check_no_compiler_messages power10_ok object {
7095 asm ("pli %0,%1" : "=r" (e) : "n" (0x12345));
7104 # Return 1 if this is a PowerPC target supporting -mfloat128 via either
7105 # software emulation on power7/power8 systems or hardware support on power9.
7107 proc check_effective_target_powerpc_float128_sw_ok { } {
7108 if { ([istarget powerpc*-*-*]
7109 && ![istarget powerpc-*-linux*paired*])
7110 || [istarget rs6000-*-*] } {
7111 # AltiVec is not supported on AIX before 5.3.
7112 if { [istarget powerpc*-*-aix4*]
7113 || [istarget powerpc*-*-aix5.1*]
7114 || [istarget powerpc*-*-aix5.2*] } {
7117 # Darwin doesn't have VSX, so no soft support for float128.
7118 if { [istarget *-*-darwin*] } {
7121 return [check_no_compiler_messages powerpc_float128_sw_ok object {
7122 volatile __float128 x = 1.0q;
7123 volatile __float128 y = 2.0q;
7125 __float128 z = x + y;
7128 } "-mfloat128 -mvsx"]
7134 # Return 1 if this is a PowerPC target supporting -mfloat128 via hardware
7135 # support on power9.
7137 proc check_effective_target_powerpc_float128_hw_ok { } {
7138 if { ([istarget powerpc*-*-*]
7139 && ![istarget powerpc-*-linux*paired*])
7140 || [istarget rs6000-*-*] } {
7141 # AltiVec is not supported on AIX before 5.3.
7142 if { [istarget powerpc*-*-aix4*]
7143 || [istarget powerpc*-*-aix5.1*]
7144 || [istarget powerpc*-*-aix5.2*] } {
7147 # Darwin doesn't run on any machine with float128 h/w so far.
7148 if { [istarget *-*-darwin*] } {
7151 return [check_no_compiler_messages powerpc_float128_hw_ok object {
7152 volatile __float128 x = 1.0q;
7153 volatile __float128 y = 2.0q;
7156 __asm__ ("xsaddqp %0,%1,%2" : "=v" (z) : "v" (x), "v" (y));
7159 } "-mfloat128-hardware"]
7165 # Return 1 if current options define float128, 0 otherwise.
7167 proc check_effective_target_ppc_float128 { } {
7168 return [check_no_compiler_messages_nocache ppc_float128 object {
7171 #ifndef __FLOAT128__
7178 # Return 1 if current options generate float128 insns, 0 otherwise.
7180 proc check_effective_target_ppc_float128_insns { } {
7181 return [check_no_compiler_messages_nocache ppc_float128 object {
7184 #ifndef __FLOAT128_HARDWARE__
7191 # Return 1 if current options generate VSX instructions, 0 otherwise.
7193 proc check_effective_target_powerpc_vsx { } {
7194 return [check_no_compiler_messages_nocache powerpc_vsx object {
7204 # Return 1 if this is a PowerPC target supporting -mvsx
7206 proc check_effective_target_powerpc_vsx_ok { } {
7207 if { ([istarget powerpc*-*-*]
7208 && ![istarget powerpc-*-linux*paired*])
7209 || [istarget rs6000-*-*] } {
7210 # VSX is not supported on AIX before 7.1.
7211 if { [istarget powerpc*-*-aix4*]
7212 || [istarget powerpc*-*-aix5*]
7213 || [istarget powerpc*-*-aix6*] } {
7216 # Darwin doesn't have VSX, even if it's used with an assembler
7217 # which recognises the insns.
7218 if { [istarget *-*-darwin*] } {
7221 return [check_no_compiler_messages powerpc_vsx_ok object {
7223 asm volatile ("xxlor 0,0,0");
7232 # Return 1 if this is a PowerPC target supporting -mhtm
7234 proc check_effective_target_powerpc_htm_ok { } {
7235 if { ([istarget powerpc*-*-*]
7236 && ![istarget powerpc-*-linux*paired*])
7237 || [istarget rs6000-*-*] } {
7238 # HTM is not supported on AIX yet.
7239 if { [istarget powerpc*-*-aix*] } {
7242 return [check_no_compiler_messages powerpc_htm_ok object {
7244 asm volatile ("tbegin. 0");
7253 # Return 1 if the target supports executing HTM hardware instructions,
7254 # 0 otherwise. Cache the result.
7256 proc check_htm_hw_available { } {
7257 return [check_cached_effective_target htm_hw_available {
7258 # For now, disable on Darwin
7259 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
7262 check_runtime_nocache htm_hw_available {
7272 # Return 1 if this is a PowerPC target supporting -mcpu=cell.
7274 proc check_effective_target_powerpc_ppu_ok { } {
7275 if [check_effective_target_powerpc_altivec_ok] {
7276 return [check_no_compiler_messages cell_asm_available object {
7279 asm volatile ("lvlx v0,v0,v0");
7281 asm volatile ("lvlx 0,0,0");
7291 # Return 1 if this is a PowerPC target that supports SPU.
7293 proc check_effective_target_powerpc_spu { } {
7294 if { [istarget powerpc*-*-linux*] } {
7295 return [check_effective_target_powerpc_altivec_ok]
7301 # Return 1 if this is a PowerPC SPE target. The check includes options
7302 # specified by dg-options for this test, so don't cache the result.
7304 proc check_effective_target_powerpc_spe_nocache { } {
7305 if { [istarget powerpc*-*-*] } {
7306 return [check_no_compiler_messages_nocache powerpc_spe object {
7312 } [current_compiler_flags]]
7318 # Return 1 if this is a PowerPC target with SPE enabled.
7320 proc check_effective_target_powerpc_spe { } {
7321 if { [istarget powerpc*-*-*] } {
7322 return [check_no_compiler_messages powerpc_spe object {
7334 # Return 1 if this is a PowerPC target with Altivec enabled.
7336 proc check_effective_target_powerpc_altivec { } {
7337 if { [istarget powerpc*-*-*] } {
7338 return [check_no_compiler_messages powerpc_altivec object {
7350 # Return 1 if this is a PowerPC 405 target. The check includes options
7351 # specified by dg-options for this test, so don't cache the result.
7353 proc check_effective_target_powerpc_405_nocache { } {
7354 if { [istarget powerpc*-*-*] || [istarget rs6000-*-*] } {
7355 return [check_no_compiler_messages_nocache powerpc_405 object {
7361 } [current_compiler_flags]]
7367 # Return 1 if this is a PowerPC target using the ELFv2 ABI.
7369 proc check_effective_target_powerpc_elfv2 { } {
7370 if { [istarget powerpc*-*-*] } {
7371 return [check_no_compiler_messages powerpc_elfv2 object {
7373 #error not ELF v2 ABI
7383 # Return 1 if this is a PowerPC target supporting -mrop-protect
7385 proc check_effective_target_rop_ok { } {
7386 return [check_effective_target_power10_ok] && [check_effective_target_powerpc_elfv2]
7389 # The VxWorks SPARC simulator accepts only EM_SPARC executables and
7390 # chokes on EM_SPARC32PLUS or EM_SPARCV9 executables. Return 1 if the
7391 # test environment appears to run executables on such a simulator.
7393 proc check_effective_target_ultrasparc_hw { } {
7394 return [check_runtime ultrasparc_hw {
7395 int main() { return 0; }
7396 } "-mcpu=ultrasparc"]
7399 # Return 1 if the test environment supports executing UltraSPARC VIS2
7400 # instructions. We check this by attempting: "bmask %g0, %g0, %g0"
7402 proc check_effective_target_ultrasparc_vis2_hw { } {
7403 return [check_runtime ultrasparc_vis2_hw {
7404 int main() { __asm__(".word 0x81b00320"); return 0; }
7405 } "-mcpu=ultrasparc3"]
7408 # Return 1 if the test environment supports executing UltraSPARC VIS3
7409 # instructions. We check this by attempting: "addxc %g0, %g0, %g0"
7411 proc check_effective_target_ultrasparc_vis3_hw { } {
7412 return [check_runtime ultrasparc_vis3_hw {
7413 int main() { __asm__(".word 0x81b00220"); return 0; }
7417 # Return 1 if this is a SPARC-V9 target.
7419 proc check_effective_target_sparc_v9 { } {
7420 if { [istarget sparc*-*-*] } {
7421 return [check_no_compiler_messages sparc_v9 object {
7423 asm volatile ("return %i7+8");
7432 # Return 1 if this is a SPARC target with VIS enabled.
7434 proc check_effective_target_sparc_vis { } {
7435 if { [istarget sparc*-*-*] } {
7436 return [check_no_compiler_messages sparc_vis object {
7448 # Return 1 if the target supports hardware vector shift operation.
7450 proc check_effective_target_vect_shift { } {
7451 return [check_cached_effective_target_indexed vect_shift {
7452 expr {([istarget powerpc*-*-*]
7453 && ![istarget powerpc-*-linux*paired*])
7454 || [istarget ia64-*-*]
7455 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7456 || [istarget aarch64*-*-*]
7457 || [is-effective-target arm_neon]
7458 || ([istarget mips*-*-*]
7459 && ([et-is-effective-target mips_msa]
7460 || [et-is-effective-target mips_loongson_mmi]))
7461 || ([istarget s390*-*-*]
7462 && [check_effective_target_s390_vx])
7463 || [istarget amdgcn-*-*]
7464 || ([istarget riscv*-*-*]
7465 && [check_effective_target_riscv_v]) }}]
7468 # Return 1 if the target supports hardware vector shift by register operation.
7470 proc check_effective_target_vect_var_shift { } {
7471 return [check_cached_effective_target_indexed vect_var_shift {
7472 expr {(([istarget i?86-*-*] || [istarget x86_64-*-*])
7473 && [check_avx2_available])
7474 || [istarget aarch64*-*-*]
7475 || ([istarget riscv*-*-*]
7476 && [check_effective_target_riscv_v])
7480 proc check_effective_target_whole_vector_shift { } {
7481 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
7482 || [istarget ia64-*-*]
7483 || [istarget aarch64*-*-*]
7484 || [istarget powerpc64*-*-*]
7485 || ([is-effective-target arm_neon]
7486 && [check_effective_target_arm_little_endian])
7487 || ([istarget mips*-*-*]
7488 && [et-is-effective-target mips_loongson_mmi])
7489 || ([istarget s390*-*-*]
7490 && [check_effective_target_s390_vx])
7491 || [istarget amdgcn-*-*]
7492 || ([istarget riscv*-*-*]
7493 && [check_effective_target_riscv_v]) } {
7499 verbose "check_effective_target_vect_long: returning $answer" 2
7503 # Return 1 if the target supports vector bswap operations.
7505 proc check_effective_target_vect_bswap { } {
7506 return [check_cached_effective_target_indexed vect_bswap {
7507 expr { ([istarget aarch64*-*-*]
7508 || [is-effective-target arm_neon]
7509 || [istarget amdgcn-*-*])
7510 || ([istarget s390*-*-*]
7511 && [check_effective_target_s390_vx]) }}]
7514 # Return 1 if the target supports comparison of bool vectors for at
7515 # least one vector length.
7517 proc check_effective_target_vect_bool_cmp { } {
7518 return [check_cached_effective_target_indexed vect_bool_cmp {
7519 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7520 || [istarget aarch64*-*-*]
7521 || [is-effective-target arm_neon]
7522 || ([istarget riscv*-*-*]
7523 && [check_effective_target_riscv_v]) }}]
7526 # Return 1 if the target supports addition of char vectors for at least
7527 # one vector length.
7529 proc check_effective_target_vect_char_add { } {
7530 return [check_cached_effective_target_indexed vect_char_add {
7532 [istarget i?86-*-*] || [istarget x86_64-*-*]
7533 || ([istarget powerpc*-*-*]
7534 && ![istarget powerpc-*-linux*paired*])
7535 || [istarget amdgcn-*-*]
7536 || [istarget ia64-*-*]
7537 || [istarget aarch64*-*-*]
7538 || [is-effective-target arm_neon]
7539 || ([istarget mips*-*-*]
7540 && ([et-is-effective-target mips_loongson_mmi]
7541 || [et-is-effective-target mips_msa]))
7542 || ([istarget s390*-*-*]
7543 && [check_effective_target_s390_vx])
7544 || ([istarget riscv*-*-*]
7545 && [check_effective_target_riscv_v])
7549 # Return 1 if the target supports hardware vector shift operation for char.
7551 proc check_effective_target_vect_shift_char { } {
7552 return [check_cached_effective_target_indexed vect_shift_char {
7553 expr { ([istarget powerpc*-*-*]
7554 && ![istarget powerpc-*-linux*paired*])
7555 || [is-effective-target arm_neon]
7556 || ([istarget mips*-*-*]
7557 && [et-is-effective-target mips_msa])
7558 || ([istarget s390*-*-*]
7559 && [check_effective_target_s390_vx])
7560 || [istarget amdgcn-*-*]
7561 || ([istarget riscv*-*-*]
7562 && [check_effective_target_riscv_v]) }}]
7565 # Return 1 if the target supports hardware vectors of long, 0 otherwise.
7567 # This can change for different subtargets so do not cache the result.
7569 proc check_effective_target_vect_long { } {
7570 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
7571 || (([istarget powerpc*-*-*]
7572 && ![istarget powerpc-*-linux*paired*])
7573 && [check_effective_target_ilp32])
7574 || [is-effective-target arm_neon]
7575 || ([istarget sparc*-*-*] && [check_effective_target_ilp32])
7576 || [istarget aarch64*-*-*]
7577 || ([istarget mips*-*-*]
7578 && [et-is-effective-target mips_msa])
7579 || ([istarget s390*-*-*]
7580 && [check_effective_target_s390_vx])
7581 || [istarget amdgcn-*-*]
7582 || ([istarget riscv*-*-*]
7583 && [check_effective_target_riscv_v]) } {
7589 verbose "check_effective_target_vect_long: returning $answer" 2
7593 # Return 1 if the target supports hardware vectors of float when
7594 # -funsafe-math-optimizations is enabled, 0 otherwise.
7596 # This won't change for different subtargets so cache the result.
7598 proc check_effective_target_vect_float { } {
7599 return [check_cached_effective_target_indexed vect_float {
7600 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7601 || [istarget powerpc*-*-*]
7602 || [istarget mips-sde-elf]
7603 || [istarget mipsisa64*-*-*]
7604 || [istarget ia64-*-*]
7605 || [istarget aarch64*-*-*]
7606 || ([istarget mips*-*-*]
7607 && [et-is-effective-target mips_msa])
7608 || [is-effective-target arm_neon]
7609 || ([istarget s390*-*-*]
7610 && [check_effective_target_s390_vxe])
7611 || [istarget amdgcn-*-*]
7612 || ([istarget riscv*-*-*]
7613 && [check_effective_target_riscv_v]) }}]
7616 # Return 1 if the target supports hardware vectors of float without
7617 # -funsafe-math-optimizations being enabled, 0 otherwise.
7619 proc check_effective_target_vect_float_strict { } {
7620 return [expr { [check_effective_target_vect_float]
7621 && ![istarget arm*-*-*] }]
7624 # Return 1 if the target supports hardware vectors of double, 0 otherwise.
7626 # This won't change for different subtargets so cache the result.
7628 proc check_effective_target_vect_double { } {
7629 return [check_cached_effective_target_indexed vect_double {
7630 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
7631 && [check_no_compiler_messages vect_double assembly {
7632 #ifdef __tune_atom__
7633 # error No double vectorizer support.
7636 || [istarget aarch64*-*-*]
7637 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
7638 || ([istarget mips*-*-*]
7639 && [et-is-effective-target mips_msa])
7640 || ([istarget s390*-*-*]
7641 && [check_effective_target_s390_vx])
7642 || [istarget amdgcn-*-*]
7643 || ([istarget riscv*-*-*]
7644 && [check_effective_target_riscv_v])} }]
7647 # Return 1 if the target supports conditional addition, subtraction,
7648 # multiplication, division, minimum and maximum on vectors of double,
7649 # via the cond_ optabs. Return 0 otherwise.
7651 proc check_effective_target_vect_double_cond_arith { } {
7652 return [expr { [check_effective_target_aarch64_sve]
7653 || [check_effective_target_riscv_v] }]
7656 # Return 1 if the target supports hardware vectors of long long, 0 otherwise.
7658 # This won't change for different subtargets so cache the result.
7660 proc check_effective_target_vect_long_long { } {
7661 return [check_cached_effective_target_indexed vect_long_long {
7662 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7663 || ([istarget mips*-*-*]
7664 && [et-is-effective-target mips_msa])
7665 || ([istarget s390*-*-*]
7666 && [check_effective_target_s390_vx])
7667 || ([istarget powerpc*-*-*]
7668 && ![istarget powerpc-*-linux*paired*]
7669 && [check_effective_target_has_arch_pwr8])
7670 || [istarget aarch64*-*-*]
7671 || ([istarget riscv*-*-*]
7672 && [check_effective_target_riscv_v])}}]
7676 # Return 1 if the target plus current options does not support a vector
7677 # max instruction on "int", 0 otherwise.
7679 # This won't change for different subtargets so cache the result.
7681 proc check_effective_target_vect_no_int_min_max { } {
7682 return [check_cached_effective_target_indexed vect_no_int_min_max {
7683 expr { [istarget sparc*-*-*]
7684 || [istarget alpha*-*-*]
7685 || ([istarget mips*-*-*]
7686 && [et-is-effective-target mips_loongson_mmi]) }}]
7689 # Return 1 if the target plus current options does not support a vector
7690 # add instruction on "int", 0 otherwise.
7692 # This won't change for different subtargets so cache the result.
7694 proc check_effective_target_vect_no_int_add { } {
7695 # Alpha only supports vector add on V8QI and V4HI.
7696 return [check_cached_effective_target_indexed vect_no_int_add {
7697 expr { [istarget alpha*-*-*] }}]
7700 # Return 1 if the target plus current options does not support vector
7701 # bitwise instructions, 0 otherwise.
7703 # This won't change for different subtargets so cache the result.
7705 proc check_effective_target_vect_no_bitwise { } {
7706 return [check_cached_effective_target_indexed vect_no_bitwise { return 0 }]
7709 # Return 1 if the target plus current options supports vector permutation,
7712 # This won't change for different subtargets so cache the result.
7714 proc check_effective_target_vect_perm { } {
7715 return [check_cached_effective_target_indexed vect_perm {
7716 expr { [is-effective-target arm_neon]
7717 || [istarget aarch64*-*-*]
7718 || [istarget powerpc*-*-*]
7719 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7720 || ([istarget mips*-*-*]
7721 && ([et-is-effective-target mpaired_single]
7722 || [et-is-effective-target mips_msa]))
7723 || ([istarget s390*-*-*]
7724 && [check_effective_target_s390_vx])
7725 || [istarget amdgcn-*-*]
7726 || ([istarget riscv*-*-*]
7727 && [check_effective_target_riscv_v]) }}]
7730 # Return 1 if, for some VF:
7732 # - the target's default vector size is VF * ELEMENT_BITS bits
7734 # - it is possible to implement the equivalent of:
7736 # int<ELEMENT_BITS>_t s1[COUNT][COUNT * VF], s2[COUNT * VF];
7737 # for (int i = 0; i < COUNT; ++i)
7738 # for (int j = 0; j < COUNT * VF; ++j)
7739 # s1[i][j] = s2[j - j % COUNT + i]
7741 # using only a single 2-vector permute for each vector in s1.
7743 # E.g. for COUNT == 3 and vector length 4, the two arrays would be:
7745 # s2 | a0 a1 a2 a3 | b0 b1 b2 b3 | c0 c1 c2 c3
7746 # ------+-------------+-------------+------------
7747 # s1[0] | a0 a0 a0 a3 | a3 a3 b2 b2 | b2 c1 c1 c1
7748 # s1[1] | a1 a1 a1 b0 | b0 b0 b3 b3 | b3 c2 c2 c2
7749 # s1[2] | a2 a2 a2 b1 | b1 b1 c0 c0 | c0 c3 c3 c3
7751 # Each s1 permute requires only two of a, b and c.
7753 # The distance between the start of vector n in s1[0] and the start
7754 # of vector n in s2 is:
7756 # A = (n * VF) % COUNT
7758 # The corresponding value for the end of vector n is:
7760 # B = (n * VF + VF - 1) % COUNT
7762 # Subtracting i from each value gives the corresponding difference
7763 # for s1[i]. The condition being tested by this function is false
7764 # iff A - i > 0 and B - i < 0 for some i and n, such that the first
7765 # element for s1[i] comes from vector n - 1 of s2 and the last element
7766 # comes from vector n + 1 of s2. The condition is therefore true iff
7767 # A <= B for all n. This is turn means the condition is true iff:
7769 # (n * VF) % COUNT + (VF - 1) % COUNT < COUNT
7771 # for all n. COUNT - (n * VF) % COUNT is bounded by gcd (VF, COUNT),
7772 # and will be that value for at least one n in [0, COUNT), so we want:
7774 # (VF - 1) % COUNT < gcd (VF, COUNT)
7776 proc vect_perm_supported { count element_bits } {
7777 set vector_bits [lindex [available_vector_sizes] 0]
7778 # The number of vectors has to be a power of 2 when permuting
7779 # variable-length vectors.
7780 if { $vector_bits <= 0 && ($count & -$count) != $count } {
7783 set vf [expr { $vector_bits / $element_bits }]
7785 # Compute gcd (VF, COUNT).
7788 while { $temp1 > 0 } {
7789 set temp2 [expr { $gcd % $temp1 }]
7793 return [expr { ($vf - 1) % $count < $gcd }]
7796 # Return 1 if the target supports SLP permutation of 3 vectors when each
7797 # element has 32 bits.
7799 proc check_effective_target_vect_perm3_int { } {
7800 return [expr { [check_effective_target_vect_perm]
7801 && [vect_perm_supported 3 32] }]
7804 # Return 1 if the target plus current options supports vector permutation
7805 # on byte-sized elements, 0 otherwise.
7807 # This won't change for different subtargets so cache the result.
7809 proc check_effective_target_vect_perm_byte { } {
7810 return [check_cached_effective_target_indexed vect_perm_byte {
7811 expr { ([is-effective-target arm_neon]
7812 && [is-effective-target arm_little_endian])
7813 || ([istarget aarch64*-*-*]
7814 && [is-effective-target aarch64_little_endian])
7815 || [istarget powerpc*-*-*]
7816 || ([istarget mips-*.*]
7817 && [et-is-effective-target mips_msa])
7818 || ([istarget s390*-*-*]
7819 && [check_effective_target_s390_vx])
7820 || [istarget amdgcn-*-*]
7821 || ([istarget riscv*-*-*]
7822 && [check_effective_target_riscv_v]) }}]
7825 # Return 1 if the target supports SLP permutation of 3 vectors when each
7826 # element has 8 bits.
7828 proc check_effective_target_vect_perm3_byte { } {
7829 return [expr { [check_effective_target_vect_perm_byte]
7830 && [vect_perm_supported 3 8] }]
7833 # Return 1 if the target plus current options supports vector permutation
7834 # on short-sized elements, 0 otherwise.
7836 # This won't change for different subtargets so cache the result.
7838 proc check_effective_target_vect_perm_short { } {
7839 return [check_cached_effective_target_indexed vect_perm_short {
7840 expr { ([is-effective-target arm_neon]
7841 && [is-effective-target arm_little_endian])
7842 || ([istarget aarch64*-*-*]
7843 && [is-effective-target aarch64_little_endian])
7844 || [istarget powerpc*-*-*]
7845 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
7846 && [check_ssse3_available])
7847 || ([istarget mips*-*-*]
7848 && [et-is-effective-target mips_msa])
7849 || ([istarget s390*-*-*]
7850 && [check_effective_target_s390_vx])
7851 || [istarget amdgcn-*-*]
7852 || ([istarget riscv*-*-*]
7853 && [check_effective_target_riscv_v]) }}]
7856 # Return 1 if the target supports SLP permutation of 3 vectors when each
7857 # element has 16 bits.
7859 proc check_effective_target_vect_perm3_short { } {
7860 return [expr { [check_effective_target_vect_perm_short]
7861 && [vect_perm_supported 3 16] }]
7864 # Return 1 if the target plus current options supports folding of
7865 # copysign into XORSIGN.
7867 # This won't change for different subtargets so cache the result.
7869 proc check_effective_target_xorsign { } {
7870 return [check_cached_effective_target_indexed xorsign {
7871 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7872 || [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
7875 # Return 1 if the target plus current options supports a vector
7876 # widening summation of *short* args into *int* result, 0 otherwise.
7878 # This won't change for different subtargets so cache the result.
7880 proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
7881 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si_pattern {
7882 expr { [istarget powerpc*-*-*]
7883 || ([istarget aarch64*-*-*]
7884 && ![check_effective_target_aarch64_sve])
7885 || [is-effective-target arm_neon]
7886 || [istarget ia64-*-*] }}]
7889 # Return 1 if the target plus current options supports a vector
7890 # widening summation of *short* args into *int* result, 0 otherwise.
7891 # A target can also support this widening summation if it can support
7892 # promotion (unpacking) from shorts to ints.
7894 # This won't change for different subtargets so cache the result.
7896 proc check_effective_target_vect_widen_sum_hi_to_si { } {
7897 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si {
7898 expr { [check_effective_target_vect_unpack]
7899 || [istarget powerpc*-*-*]
7900 || [istarget ia64-*-*]
7901 || [istarget riscv*-*-*] }}]
7904 # Return 1 if the target plus current options supports a vector
7905 # widening summation of *char* args into *short* result, 0 otherwise.
7906 # A target can also support this widening summation if it can support
7907 # promotion (unpacking) from chars to shorts.
7909 # This won't change for different subtargets so cache the result.
7911 proc check_effective_target_vect_widen_sum_qi_to_hi { } {
7912 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi {
7913 expr { [check_effective_target_vect_unpack]
7914 || [is-effective-target arm_neon]
7915 || [istarget ia64-*-*]
7916 || [istarget riscv*-*-*] }}]
7919 # Return 1 if the target plus current options supports a vector
7920 # widening summation of *char* args into *int* result, 0 otherwise.
7922 # This won't change for different subtargets so cache the result.
7924 proc check_effective_target_vect_widen_sum_qi_to_si { } {
7925 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
7926 expr { [istarget powerpc*-*-*]
7927 || [istarget riscv*-*-*] }}]
7930 # Return 1 if the target plus current options supports a vector
7931 # widening multiplication of *char* args into *short* result, 0 otherwise.
7932 # A target can also support this widening multplication if it can support
7933 # promotion (unpacking) from chars to shorts, and vect_short_mult (non-widening
7934 # multiplication of shorts).
7936 # This won't change for different subtargets so cache the result.
7939 proc check_effective_target_vect_widen_mult_qi_to_hi { } {
7940 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi {
7941 expr { ([check_effective_target_vect_unpack]
7942 && [check_effective_target_vect_short_mult])
7943 || ([istarget powerpc*-*-*]
7944 || ([istarget aarch64*-*-*]
7945 && ![check_effective_target_aarch64_sve])
7946 || [is-effective-target arm_neon]
7947 || ([istarget s390*-*-*]
7948 && [check_effective_target_s390_vx]))
7949 || [istarget amdgcn-*-*] }}]
7952 # Return 1 if the target plus current options supports a vector
7953 # widening multiplication of *short* args into *int* result, 0 otherwise.
7954 # A target can also support this widening multplication if it can support
7955 # promotion (unpacking) from shorts to ints, and vect_int_mult (non-widening
7956 # multiplication of ints).
7958 # This won't change for different subtargets so cache the result.
7961 proc check_effective_target_vect_widen_mult_hi_to_si { } {
7962 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si {
7963 expr { ([check_effective_target_vect_unpack]
7964 && [check_effective_target_vect_int_mult])
7965 || ([istarget powerpc*-*-*]
7966 || [istarget ia64-*-*]
7967 || ([istarget aarch64*-*-*]
7968 && ![check_effective_target_aarch64_sve])
7969 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7970 || [is-effective-target arm_neon]
7971 || ([istarget s390*-*-*]
7972 && [check_effective_target_s390_vx]))
7973 || [istarget amdgcn-*-*] }}]
7976 # Return 1 if the target plus current options supports a vector
7977 # widening multiplication of *char* args into *short* result, 0 otherwise.
7979 # This won't change for different subtargets so cache the result.
7981 proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
7982 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi_pattern {
7983 expr { [istarget powerpc*-*-*]
7984 || ([is-effective-target arm_neon]
7985 && [check_effective_target_arm_little_endian])
7986 || ([istarget s390*-*-*]
7987 && [check_effective_target_s390_vx])
7988 || [istarget amdgcn-*-*] }}]
7991 # Return 1 if the target plus current options supports a vector
7992 # widening multiplication of *short* args into *int* result, 0 otherwise.
7994 # This won't change for different subtargets so cache the result.
7996 proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
7997 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern {
7998 expr { [istarget powerpc*-*-*]
7999 || [istarget ia64-*-*]
8000 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8001 || ([is-effective-target arm_neon]
8002 && [check_effective_target_arm_little_endian])
8003 || ([istarget s390*-*-*]
8004 && [check_effective_target_s390_vx])
8005 || [istarget amdgcn-*-*] }}]
8008 # Return 1 if the target plus current options supports a vector
8009 # widening multiplication of *int* args into *long* result, 0 otherwise.
8011 # This won't change for different subtargets so cache the result.
8013 proc check_effective_target_vect_widen_mult_si_to_di_pattern { } {
8014 return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern {
8015 expr { [istarget ia64-*-*]
8016 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8017 || ([istarget s390*-*-*]
8018 && [check_effective_target_s390_vx]) }}]
8021 # Return 1 if the target plus current options supports a vector
8022 # widening shift, 0 otherwise.
8024 # This won't change for different subtargets so cache the result.
8026 proc check_effective_target_vect_widen_shift { } {
8027 return [check_cached_effective_target_indexed vect_widen_shift {
8028 expr { [is-effective-target arm_neon] }}]
8031 # Return 1 if the target plus current options supports a vector
8032 # dot-product of signed chars, 0 otherwise.
8034 # This won't change for different subtargets so cache the result.
8036 proc check_effective_target_vect_sdot_qi { } {
8037 return [check_cached_effective_target_indexed vect_sdot_qi {
8038 expr { [istarget ia64-*-*]
8039 || [istarget aarch64*-*-*]
8040 || [istarget arm*-*-*]
8041 || ([istarget mips*-*-*]
8042 && [et-is-effective-target mips_msa])
8043 || ([istarget riscv*-*-*]
8044 && [check_effective_target_riscv_v]) }}]
8047 # Return 1 if the target plus current options supports a vector
8048 # dot-product of unsigned chars, 0 otherwise.
8050 # This won't change for different subtargets so cache the result.
8052 proc check_effective_target_vect_udot_qi { } {
8053 return [check_cached_effective_target_indexed vect_udot_qi {
8054 expr { [istarget powerpc*-*-*]
8055 || [istarget aarch64*-*-*]
8056 || [istarget arm*-*-*]
8057 || [istarget ia64-*-*]
8058 || ([istarget mips*-*-*]
8059 && [et-is-effective-target mips_msa])
8060 || ([istarget riscv*-*-*]
8061 && [check_effective_target_riscv_v]) }}]
8064 # Return 1 if the target plus current options supports a vector
8065 # dot-product where one operand of the multiply is signed char
8066 # and the other unsigned chars, 0 otherwise.
8068 # This won't change for different subtargets so cache the result.
8070 proc check_effective_target_vect_usdot_qi { } {
8071 return [check_cached_effective_target_indexed vect_usdot_qi {
8072 expr { [istarget aarch64*-*-*]
8073 || [istarget arm*-*-*] }}]
8077 # Return 1 if the target plus current options supports a vector
8078 # dot-product of signed shorts, 0 otherwise.
8080 # This won't change for different subtargets so cache the result.
8082 proc check_effective_target_vect_sdot_hi { } {
8083 return [check_cached_effective_target_indexed vect_sdot_hi {
8084 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8085 || [istarget ia64-*-*]
8086 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8087 || ([istarget mips*-*-*]
8088 && [et-is-effective-target mips_msa])
8089 || ([istarget riscv*-*-*]
8090 && [check_effective_target_riscv_v]) }}]
8093 # Return 1 if the target plus current options supports a vector
8094 # dot-product of unsigned shorts, 0 otherwise.
8096 # This won't change for different subtargets so cache the result.
8098 proc check_effective_target_vect_udot_hi { } {
8099 return [check_cached_effective_target_indexed vect_udot_hi {
8100 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8101 || ([istarget mips*-*-*]
8102 && [et-is-effective-target mips_msa])
8103 || ([istarget riscv*-*-*]
8104 && [check_effective_target_riscv_v]) }}]
8107 # Return 1 if the target plus current options supports a vector
8108 # sad operation of unsigned chars, 0 otherwise.
8110 # This won't change for different subtargets so cache the result.
8112 proc check_effective_target_vect_usad_char { } {
8113 return [check_cached_effective_target_indexed vect_usad_char {
8114 expr { [istarget i?86-*-*]
8115 || [istarget x86_64-*-*]
8116 || ([istarget aarch64*-*-*]
8117 && ![check_effective_target_aarch64_sve])
8118 || ([istarget powerpc*-*-*]
8119 && [check_p9vector_hw_available])
8120 || ([istarget riscv*-*-*]
8121 && [check_effective_target_riscv_v]) }}]
8124 # Return 1 if the target plus current options supports both signed
8125 # and unsigned average operations on vectors of bytes.
8127 proc check_effective_target_vect_avg_qi {} {
8128 return [expr { ([istarget aarch64*-*-*]
8129 && ![check_effective_target_aarch64_sve1_only])
8130 || ([istarget riscv*-*-*]
8131 && [check_effective_target_riscv_v]) }]
8134 # Return 1 if the target plus current options supports both signed
8135 # and unsigned multiply-high-with-round-and-scale operations
8136 # on vectors of half-words.
8138 proc check_effective_target_vect_mulhrs_hi {} {
8139 return [expr { [istarget aarch64*-*-*]
8140 && [check_effective_target_aarch64_sve2] }]
8143 # Return 1 if the target plus current options supports signed division
8144 # by power-of-2 operations on vectors of 4-byte integers.
8146 proc check_effective_target_vect_sdiv_pow2_si {} {
8147 return [expr { ([istarget aarch64*-*-*]
8148 && [check_effective_target_aarch64_sve]) }]
8151 # Return 1 if the target plus current options supports a vector
8152 # demotion (packing) of shorts (to chars) and ints (to shorts)
8153 # using modulo arithmetic, 0 otherwise.
8155 # This won't change for different subtargets so cache the result.
8157 proc check_effective_target_vect_pack_trunc { } {
8158 return [check_cached_effective_target_indexed vect_pack_trunc {
8159 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8160 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8161 || [istarget aarch64*-*-*]
8162 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8163 && [check_effective_target_arm_little_endian])
8164 || ([istarget mips*-*-*]
8165 && [et-is-effective-target mips_msa])
8166 || ([istarget s390*-*-*]
8167 && [check_effective_target_s390_vx])
8168 || [istarget amdgcn*-*-*]
8169 || ([istarget riscv*-*-*]
8170 && [check_effective_target_riscv_v]) }}]
8173 # Return 1 if the target plus current options supports a vector
8174 # promotion (unpacking) of chars (to shorts) and shorts (to ints), 0 otherwise.
8176 # This won't change for different subtargets so cache the result.
8178 proc check_effective_target_vect_unpack { } {
8179 return [check_cached_effective_target_indexed vect_unpack {
8180 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
8181 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8182 || [istarget ia64-*-*]
8183 || [istarget aarch64*-*-*]
8184 || ([istarget mips*-*-*]
8185 && [et-is-effective-target mips_msa])
8186 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8187 && [check_effective_target_arm_little_endian])
8188 || ([istarget s390*-*-*]
8189 && [check_effective_target_s390_vx])
8190 || [istarget amdgcn*-*-*]
8191 || ([istarget riscv*-*-*]
8192 && [check_effective_target_riscv_v]) }}]
8195 # Return 1 if the target plus current options does not guarantee
8196 # that its STACK_BOUNDARY is >= the reguired vector alignment.
8198 # This won't change for different subtargets so cache the result.
8200 proc check_effective_target_unaligned_stack { } {
8201 return [check_cached_effective_target_indexed unaligned_stack { expr 0 }]
8204 # Return 1 if the target plus current options does not support a vector
8205 # alignment mechanism, 0 otherwise.
8207 # This won't change for different subtargets so cache the result.
8209 proc check_effective_target_vect_no_align { } {
8210 return [check_cached_effective_target_indexed vect_no_align {
8211 expr { [istarget mipsisa64*-*-*]
8212 || [istarget mips-sde-elf]
8213 || [istarget sparc*-*-*]
8214 || [istarget ia64-*-*]
8215 || [check_effective_target_arm_vect_no_misalign]
8216 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8217 || ([istarget mips*-*-*]
8218 && [et-is-effective-target mips_loongson_mmi]) }}]
8221 # Return 1 if the target supports a vector misalign access, 0 otherwise.
8223 # This won't change for different subtargets so cache the result.
8225 proc check_effective_target_vect_hw_misalign { } {
8226 return [check_cached_effective_target_indexed vect_hw_misalign {
8227 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
8228 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8229 || [istarget aarch64*-*-*]
8230 || ([istarget mips*-*-*] && [et-is-effective-target mips_msa])
8231 || ([istarget s390*-*-*]
8232 && [check_effective_target_s390_vx])
8233 || ([istarget riscv*-*-*]) } {
8236 if { [istarget arm*-*-*]
8237 && ![check_effective_target_arm_vect_no_misalign] } {
8245 # Return 1 if arrays are aligned to the vector alignment
8246 # boundary, 0 otherwise.
8248 proc check_effective_target_vect_aligned_arrays { } {
8249 set et_vect_aligned_arrays 0
8250 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
8251 && !([is-effective-target ia32]
8252 || ([check_avx_available] && ![check_prefer_avx128]))) } {
8253 set et_vect_aligned_arrays 1
8256 verbose "check_effective_target_vect_aligned_arrays:\
8257 returning $et_vect_aligned_arrays" 2
8258 return $et_vect_aligned_arrays
8261 # Return 1 if the biggest alignment required by target is 1 * BITS_PER_UNIT.
8262 # In such case the target does not impose any alignment constraints.
8264 proc check_effective_target_no_alignment_constraints { } {
8265 return [check_runtime_nocache no_alignment_constraints {
8269 return __BIGGEST_ALIGNMENT__ == 1 ? 0 : 1;
8274 # Return 1 if types of size 32 bit or less are naturally aligned
8275 # (aligned to their type-size), 0 otherwise.
8277 # This won't change for different subtargets so cache the result.
8279 proc check_effective_target_natural_alignment_32 { } {
8280 # FIXME: 32bit powerpc: guaranteed only if MASK_ALIGN_NATURAL/POWER.
8281 # FIXME: m68k has -malign-int
8282 return [check_cached_effective_target_indexed natural_alignment_32 {
8283 if { ([istarget *-*-darwin*] && [is-effective-target lp64])
8284 || [istarget avr-*-*]
8285 || [istarget m68k-*-linux*]
8286 || [istarget pru-*-*]
8287 || [istarget stormy16-*-*]
8288 || [istarget rl78-*-*]
8289 || [istarget pdp11-*-*]
8290 || [istarget msp430-*-*]
8291 || [istarget m32c-*-*]
8292 || [istarget cris-*-*] } {
8300 # Return 1 if types of size 64 bit or less are naturally aligned (aligned to their
8301 # type-size), 0 otherwise.
8303 # This won't change for different subtargets so cache the result.
8305 proc check_effective_target_natural_alignment_64 { } {
8306 return [check_cached_effective_target_indexed natural_alignment_64 {
8307 expr { [is-effective-target natural_alignment_32]
8308 && [is-effective-target lp64] && ![istarget *-*-darwin*] }
8312 # Return 1 if all vector types are naturally aligned (aligned to their
8313 # type-size), 0 otherwise.
8315 proc check_effective_target_vect_natural_alignment { } {
8316 set et_vect_natural_alignment 1
8317 if { [check_effective_target_arm_eabi]
8318 || [istarget nvptx-*-*]
8319 || [istarget s390*-*-*]
8320 || [istarget amdgcn-*-*] } {
8321 set et_vect_natural_alignment 0
8323 verbose "check_effective_target_vect_natural_alignment:\
8324 returning $et_vect_natural_alignment" 2
8325 return $et_vect_natural_alignment
8328 # Return true if the target supports the check_raw_ptrs and check_war_ptrs
8329 # optabs on vectors.
8331 proc check_effective_target_vect_check_ptrs { } {
8332 return [check_effective_target_aarch64_sve2]
8335 # Return true if fully-masked loops are supported.
8337 proc check_effective_target_vect_fully_masked { } {
8338 return [expr { [check_effective_target_aarch64_sve]
8339 || [istarget amdgcn*-*-*]
8340 || [check_effective_target_riscv_v] }]
8343 # Return true if the target supports the @code{len_load} and
8344 # @code{len_store} optabs.
8346 proc check_effective_target_vect_len_load_store { } {
8347 return [expr { [check_effective_target_has_arch_pwr9]
8348 || [check_effective_target_s390_vx]
8349 || [check_effective_target_riscv_v] }]
8352 # Return the value of parameter vect-partial-vector-usage specified for
8353 # target by checking the output of "-Q --help=params". Return zero if
8354 # the desirable pattern isn't found.
8356 proc check_vect_partial_vector_usage { } {
8359 return [check_cached_effective_target vect_partial_vector_usage {
8360 set result [check_compile vect_partial_vector_usage assembly {
8362 } "-Q --help=params" ]
8364 # Get compiler emitted messages and delete generated file.
8365 set lines [lindex $result 0]
8366 set output [lindex $result 1]
8367 remote_file build delete $output
8369 set pattern {=vect-partial-vector-usage=<0,2>\s+([0-2])}
8370 # Capture the usage value to val, set it to zero if not found.
8371 if { ![regexp $pattern $lines whole val] } then {
8379 # Return true if the target supports loop vectorization with partial vectors
8380 # and @code{vect-partial-vector-usage} is set to 1.
8382 proc check_effective_target_vect_partial_vectors_usage_1 { } {
8383 return [expr { ([check_effective_target_vect_fully_masked]
8384 || [check_effective_target_vect_len_load_store])
8385 && [check_vect_partial_vector_usage] == 1 }]
8388 # Return true if the target supports loop vectorization with partial vectors
8389 # and @code{vect-partial-vector-usage} is set to 2.
8391 proc check_effective_target_vect_partial_vectors_usage_2 { } {
8392 return [expr { ([check_effective_target_vect_fully_masked]
8393 || [check_effective_target_vect_len_load_store])
8394 && [check_vect_partial_vector_usage] == 2 }]
8397 # Return true if the target supports loop vectorization with partial vectors
8398 # and @code{vect-partial-vector-usage} is nonzero.
8400 proc check_effective_target_vect_partial_vectors { } {
8401 return [expr { ([check_effective_target_vect_fully_masked]
8402 || [check_effective_target_vect_len_load_store])
8403 && [check_vect_partial_vector_usage] != 0 }]
8406 # Return 1 if the target doesn't prefer any alignment beyond element
8407 # alignment during vectorization.
8409 proc check_effective_target_vect_element_align_preferred { } {
8410 return [expr { ([check_effective_target_aarch64_sve]
8411 && [check_effective_target_vect_variable_length])
8412 || [check_effective_target_riscv_v] }]
8415 # Return true if vectorization of v2qi/v4qi/v8qi/v16qi/v2hi store is enabed.
8416 # Return zero if the desirable pattern isn't found.
8417 # It's used by Warray-bounds/Wstringop-overflow testcases which are
8418 # regressed by O2 vectorization, refer to PR102697/PR102462/PR102706
8419 proc check_vect_slp_store_usage { pattern macro } {
8422 set result [check_compile slp_aligned_store_usage assembly {
8423 extern void sink (void* );
8424 #define Ac8 (AC8){ 0, 1, 2, 3, 4, 5, 6, 7 }
8425 #define Ac16 (AC16){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
8427 typedef struct AC16 { char a[16]; } AC16;
8428 extern char a16[16];
8435 typedef struct AC8 { char a[8]; } AC8;
8449 extern void sink (void*);
8453 struct A1 a = { 0, { } };
8470 #define Ac4 (AC4){ 0, 1, 2, 3 }
8471 typedef struct AC4 { char a[4]; } AC4;
8519 *(short*) (b + 2) = 1;
8528 foo4_2 (struct Ax *p)
8534 struct A { int i; };
8535 struct B { int j; struct A a[4]; };
8542 char cbuf2[2 * sizeof (struct C)] = { };
8546 struct C *p = (struct C*)&cbuf2;
8553 struct A { int i; };
8554 struct B { int j; struct A a[2]; };
8561 char cbuf2[2 * sizeof (struct C)] = { };
8565 struct C *p = (struct C*)&cbuf2;
8571 } "-O2 -fopt-info-all -D$macro" ]
8573 # Get compiler emitted messages and delete generated file.
8574 set lines [lindex $result 0]
8575 set output [lindex $result 1]
8576 remote_file build delete $output
8578 # Check pattern exits in lines, set it to zero if not found.
8579 if { [regexp $pattern $lines] } then {
8586 # Return the true if target support vectorization of 2-byte char stores
8587 # with 2-byte aligned address at plain O2.
8588 # NB: This target should be removed after real issues are fixed for
8589 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8590 # this target since tests in check_vect_slp_store_usage
8591 # is the exact match of relative testcases
8592 proc check_effective_target_vect_slp_v2qi_store_align { } {
8593 set pattern {add new stmt: MEM <vector\(2\) char>}
8594 set macro "TEST_V2QI"
8595 return [check_cached_effective_target vect_slp_v2qi_store_align {
8596 expr [check_vect_slp_store_usage $pattern $macro] }]
8599 # Return the true if target support vectorization of 2-byte char stores
8600 # with unaligned address at plain O2.
8601 proc check_effective_target_vect_slp_v2qi_store_unalign { } {
8602 set pattern {add new stmt: MEM <vector\(2\) char>}
8603 set macro "TEST_V2QI_2"
8604 return [check_cached_effective_target vect_slp_v2qi_store_unalign {
8605 expr [check_vect_slp_store_usage $pattern $macro ] }]
8608 # Return the true if target support vectorization of 4-byte char stores
8609 # with 4-byte aligned address at plain O2.
8610 # NB: This target should be removed after real issues are fixed for
8611 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8612 # this target since tests in check_vect_slp_store_usage
8613 # is the exact match of relative testcases
8614 proc check_effective_target_vect_slp_v4qi_store_align { } {
8615 set pattern {add new stmt: MEM <vector\(4\) char>}
8616 set macro "TEST_V4QI"
8617 return [check_cached_effective_target vect_slp_v4qi_store_align {
8618 expr [check_vect_slp_store_usage $pattern $macro ] }]
8621 # Return the true if target support vectorization of 4-byte char stores
8622 # with unaligned address at plain O2.
8623 proc check_effective_target_vect_slp_v4qi_store_unalign { } {
8624 set pattern {add new stmt: MEM <vector\(4\) char>}
8625 set macro "TEST_V4QI_2"
8626 return [check_cached_effective_target vect_slp_v4qi_store_unalign {
8627 expr [check_vect_slp_store_usage $pattern $macro ] }]
8630 # Return the true if target support block move for
8631 # 8-byte aligned 4-byte size struct initialization.
8632 proc check_effective_target_struct_4char_block_move { } {
8633 set pattern {not vectorized: more than one data ref in stmt:}
8634 set macro "TEST_V4QI_3"
8635 return [check_cached_effective_target struct_4char_block_move {
8636 expr [check_vect_slp_store_usage $pattern $macro ] }]
8639 # Return the true if target support vectorization of 4-byte char stores
8640 # with unaligned address or store them with a constant pool at plain O2.
8641 proc check_effective_target_vect_slp_v4qi_store_unalign_1 { } {
8642 set pattern {add new stmt: MEM <vector\(4\) char>}
8643 set macro "TEST_V4QI_3"
8644 return [check_cached_effective_target vect_slp_v4qi_store_unalign_1 {
8645 expr { [check_vect_slp_store_usage $pattern $macro ]
8646 || [check_effective_target_struct_4char_block_move] } }]
8649 # Return the true if target support block move for
8650 # 8-byte aligned 8-byte size struct initialization.
8651 proc check_effective_target_struct_8char_block_move { } {
8652 set pattern {not vectorized: more than one data ref in stmt:}
8653 set macro "TEST_V8QI"
8654 return [check_cached_effective_target struct_8char_block_move {
8655 expr [check_vect_slp_store_usage $pattern $macro ] }]
8658 # Return the true if target support vectorization of 8-byte char stores
8659 # with unaligned address or store them with a constant pool at plain O2.
8660 # NB: This target should be removed after real issues are fixed for
8661 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8662 # this target since tests in check_vect_slp_store_usage
8663 # is the exact match of relative testcases
8664 proc check_effective_target_vect_slp_v8qi_store_unalign_1 { } {
8665 set pattern {add new stmt: MEM <vector\(8\) char>}
8666 set macro "TEST_V8QI"
8667 return [check_cached_effective_target vect_slp_v8qi_store_unalign_1 {
8668 expr { [check_vect_slp_store_usage $pattern $macro ]
8669 || [check_effective_target_struct_8char_block_move] } }]
8672 # Return the true if target support block move for
8673 # 8-byte aligned 16-byte size struct initialization.
8674 proc check_effective_target_struct_16char_block_move { } {
8675 set pattern {not vectorized: more than one data ref in stmt:}
8676 set macro "TEST_V16QI"
8677 return [check_cached_effective_target struct_16char_block_move {
8678 expr [check_vect_slp_store_usage $pattern $macro ] }]
8681 # Return the true if target support vectorization of 16-byte char stores
8682 # with unaligned address or store them with a constant pool at plain O2.
8683 # NB: This target should be removed after real issues are fixed for
8684 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8685 # this target since tests in check_vect_slp_store_usage
8686 # is the exact match of relative testcases
8687 proc check_effective_target_vect_slp_v16qi_store_unalign_1 { } {
8688 set pattern {add new stmt: MEM <vector\(16\) char>}
8689 set macro "TEST_V16QI"
8690 return [check_cached_effective_target vect_slp_v16qi_store_unalign_1 {
8691 expr { [check_vect_slp_store_usage $pattern $macro ]
8692 || [check_effective_target_struct_16char_block_move] } }]
8695 # Return the true if target support vectorization of 4-byte short stores
8696 # with unaligned address at plain O2.
8697 # NB: This target should be removed after real issues are fixed for
8698 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8699 # this target since tests in check_vect_slp_store_usage
8700 # is the exact match of relative testcases
8701 proc check_effective_target_vect_slp_v2hi_store_unalign { } {
8702 set pattern {add new stmt: MEM <vector\(2\) short int>}
8703 set macro "TEST_V2HI"
8704 return [check_cached_effective_target vect_slp_v2hi_store_unalign {
8705 expr [check_vect_slp_store_usage $pattern $macro ] }]
8708 # Return the true if target support vectorization of 4-byte short stores
8709 # with 4-byte aligned address at plain O2.
8710 proc check_effective_target_vect_slp_v2hi_store_align { } {
8711 set pattern {add new stmt: MEM <vector\(2\) short int>}
8712 set macro "TEST_V2HI_2"
8713 return [check_cached_effective_target vect_slp_v2hi_store_align {
8714 expr [check_vect_slp_store_usage $pattern $macro ] }]
8717 # Return the true if target support vectorization of 8-byte short stores
8718 # with unaligned address at plain O2.
8719 # NB: This target should be removed after real issues are fixed for
8720 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8721 # this target since tests in check_vect_slp_store_usage
8722 # is the exact match of relative testcases
8723 proc check_effective_target_vect_slp_v4hi_store_unalign { } {
8724 set pattern {add new stmt: MEM <vector\(4\) short int>}
8725 set macro "TEST_V4HI"
8726 return [check_cached_effective_target vect_slp_v4hi_store_unalign {
8727 expr [check_vect_slp_store_usage $pattern $macro ] }]
8730 # Return the true if target support vectorization of 8-byte int stores
8731 # with 8-byte aligned address at plain O2.
8732 # NB: This target should be removed after real issues are fixed for
8733 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8734 # this target since tests in check_vect_slp_store_usage
8735 # is the exact match of relative testcases
8736 proc check_effective_target_vect_slp_v2si_store_align { } {
8737 set pattern {add new stmt: MEM <vector\(2\) int>}
8738 set macro "TEST_V2SI"
8739 return [check_cached_effective_target vect_slp_v2si_store_align {
8740 expr [check_vect_slp_store_usage $pattern $macro ] }]
8743 # Return the true if target support vectorization of 16-byte int stores
8744 # with unaligned address at plain O2.
8745 # NB: This target should be removed after real issues are fixed for
8746 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8747 # this target since tests in check_vect_slp_store_usage
8748 # is the exact match of relative testcases
8749 proc check_effective_target_vect_slp_v4si_store_unalign { } {
8750 set pattern {add new stmt: MEM <vector\(4\) int>}
8751 set macro "TEST_V4SI"
8752 return [check_cached_effective_target vect_slp_v4si_store_unalign {
8753 expr [check_vect_slp_store_usage $pattern $macro ] }]
8756 # Return 1 if we can align stack data to the preferred vector alignment.
8758 proc check_effective_target_vect_align_stack_vars { } {
8759 if { [check_effective_target_aarch64_sve] } {
8760 return [check_effective_target_vect_variable_length]
8765 # Return 1 if vector alignment (for types of size 32 bit or less) is reachable, 0 otherwise.
8767 proc check_effective_target_vector_alignment_reachable { } {
8768 set et_vector_alignment_reachable 0
8769 if { [check_effective_target_vect_aligned_arrays]
8770 || [check_effective_target_natural_alignment_32] } {
8771 set et_vector_alignment_reachable 1
8773 verbose "check_effective_target_vector_alignment_reachable:\
8774 returning $et_vector_alignment_reachable" 2
8775 return $et_vector_alignment_reachable
8778 # Return 1 if vector alignment for 64 bit is reachable, 0 otherwise.
8780 proc check_effective_target_vector_alignment_reachable_for_64bit { } {
8781 set et_vector_alignment_reachable_for_64bit 0
8782 if { [check_effective_target_vect_aligned_arrays]
8783 || [check_effective_target_natural_alignment_64] } {
8784 set et_vector_alignment_reachable_for_64bit 1
8786 verbose "check_effective_target_vector_alignment_reachable_for_64bit:\
8787 returning $et_vector_alignment_reachable_for_64bit" 2
8788 return $et_vector_alignment_reachable_for_64bit
8791 # Return 1 if the target only requires element alignment for vector accesses
8793 proc check_effective_target_vect_element_align { } {
8794 return [check_cached_effective_target_indexed vect_element_align {
8795 expr { ([istarget arm*-*-*]
8796 && ![check_effective_target_arm_vect_no_misalign])
8797 || [check_effective_target_vect_hw_misalign]
8798 || [istarget amdgcn-*-*] }}]
8801 # Return 1 if we expect to see unaligned accesses in at least some
8804 proc check_effective_target_vect_unaligned_possible { } {
8805 return [expr { ![check_effective_target_vect_element_align_preferred]
8806 && (![check_effective_target_vect_no_align]
8807 || [check_effective_target_vect_hw_misalign]) }]
8810 # Return 1 if the target supports vector LOAD_LANES operations, 0 otherwise.
8812 proc check_effective_target_vect_load_lanes { } {
8813 # We don't support load_lanes correctly on big-endian arm.
8814 return [check_cached_effective_target vect_load_lanes {
8815 expr { ([check_effective_target_arm_little_endian]
8816 && [check_effective_target_arm_neon_ok])
8817 || [istarget aarch64*-*-*]
8818 || [istarget riscv*-*-*] }}]
8821 # Return 1 if the target supports vector masked loads.
8823 proc check_effective_target_vect_masked_load { } {
8824 return [expr { [check_avx_available]
8825 || [check_effective_target_aarch64_sve]
8826 || [istarget amdgcn*-*-*]
8827 || [check_effective_target_riscv_v] } ]
8830 # Return 1 if the target supports vector masked stores.
8832 proc check_effective_target_vect_masked_store { } {
8833 return [expr { [check_avx_available]
8834 || [check_effective_target_aarch64_sve]
8835 || [istarget amdgcn*-*-*]
8836 || [check_effective_target_riscv_v] }]
8839 # Return 1 if the target supports vector gather loads via internal functions.
8841 proc check_effective_target_vect_gather_load_ifn { } {
8842 return [expr { [check_effective_target_aarch64_sve]
8843 || [istarget amdgcn*-*-*]
8844 || [check_effective_target_riscv_v] }]
8847 # Return 1 if the target supports vector scatter stores.
8849 proc check_effective_target_vect_scatter_store { } {
8850 return [expr { [check_effective_target_aarch64_sve]
8851 || [istarget amdgcn*-*-*]
8852 || [check_effective_target_riscv_v] }]
8855 # Return 1 if the target supports vector conditional operations, 0 otherwise.
8857 proc check_effective_target_vect_condition { } {
8858 return [check_cached_effective_target_indexed vect_condition {
8859 expr { [istarget aarch64*-*-*]
8860 || [istarget powerpc*-*-*]
8861 || [istarget ia64-*-*]
8862 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8863 || ([istarget mips*-*-*]
8864 && [et-is-effective-target mips_msa])
8865 || ([istarget arm*-*-*]
8866 && [check_effective_target_arm_neon_ok])
8867 || ([istarget s390*-*-*]
8868 && [check_effective_target_s390_vx])
8869 || [istarget amdgcn-*-*]
8870 || ([istarget riscv*-*-*]
8871 && [check_effective_target_riscv_v]) }}]
8874 # Return 1 if the target supports vector conditional operations where
8875 # the comparison has different type from the lhs, 0 otherwise.
8877 proc check_effective_target_vect_cond_mixed { } {
8878 return [check_cached_effective_target_indexed vect_cond_mixed {
8879 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
8880 || [istarget aarch64*-*-*]
8881 || [istarget powerpc*-*-*]
8882 || ([istarget arm*-*-*]
8883 && [check_effective_target_arm_neon_ok])
8884 || ([istarget mips*-*-*]
8885 && [et-is-effective-target mips_msa])
8886 || ([istarget s390*-*-*]
8887 && [check_effective_target_s390_vx])
8888 || [istarget amdgcn-*-*]
8889 || ([istarget riscv*-*-*]
8890 && [check_effective_target_riscv_v]) }}]
8893 # Return 1 if the target supports vector char multiplication, 0 otherwise.
8895 proc check_effective_target_vect_char_mult { } {
8896 return [check_cached_effective_target_indexed vect_char_mult {
8897 expr { [istarget aarch64*-*-*]
8898 || [istarget ia64-*-*]
8899 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8900 || [check_effective_target_arm32]
8901 || [check_effective_target_powerpc_altivec]
8902 || ([istarget mips*-*-*]
8903 && [et-is-effective-target mips_msa])
8904 || ([istarget s390*-*-*]
8905 && [check_effective_target_s390_vx])
8906 || [istarget amdgcn-*-*]
8907 || ([istarget riscv*-*-*]
8908 && [check_effective_target_riscv_v]) }}]
8911 # Return 1 if the target supports vector short multiplication, 0 otherwise.
8913 proc check_effective_target_vect_short_mult { } {
8914 return [check_cached_effective_target_indexed vect_short_mult {
8915 expr { [istarget ia64-*-*]
8916 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8917 || [istarget powerpc*-*-*]
8918 || [istarget aarch64*-*-*]
8919 || [check_effective_target_arm32]
8920 || ([istarget mips*-*-*]
8921 && ([et-is-effective-target mips_msa]
8922 || [et-is-effective-target mips_loongson_mmi]))
8923 || ([istarget s390*-*-*]
8924 && [check_effective_target_s390_vx])
8925 || [istarget amdgcn-*-*]
8926 || ([istarget riscv*-*-*]
8927 && [check_effective_target_riscv_v]) }}]
8930 # Return 1 if the target supports vector int multiplication, 0 otherwise.
8932 proc check_effective_target_vect_int_mult { } {
8933 return [check_cached_effective_target_indexed vect_int_mult {
8934 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8935 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8936 || [istarget ia64-*-*]
8937 || [istarget aarch64*-*-*]
8938 || ([istarget mips*-*-*]
8939 && [et-is-effective-target mips_msa])
8940 || [check_effective_target_arm32]
8941 || ([istarget s390*-*-*]
8942 && [check_effective_target_s390_vx])
8943 || [istarget amdgcn-*-*]
8944 || ([istarget riscv*-*-*]
8945 && [check_effective_target_riscv_v]) }}]
8948 # Return 1 if the target supports 64 bit hardware vector
8949 # multiplication of long operands with a long result, 0 otherwise.
8951 # This can change for different subtargets so do not cache the result.
8953 proc check_effective_target_vect_long_mult { } {
8954 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
8955 || (([istarget powerpc*-*-*]
8956 && ![istarget powerpc-*-linux*paired*])
8957 && [check_effective_target_ilp32])
8958 || [is-effective-target arm_neon]
8959 || ([istarget sparc*-*-*] && [check_effective_target_ilp32])
8960 || [istarget aarch64*-*-*]
8961 || ([istarget mips*-*-*]
8962 && [et-is-effective-target mips_msa])
8963 || ([istarget riscv*-*-*]
8964 && [check_effective_target_riscv_v]) } {
8970 verbose "check_effective_target_vect_long_mult: returning $answer" 2
8974 # Return 1 if the target supports vector int modulus, 0 otherwise.
8976 proc check_effective_target_vect_int_mod { } {
8977 return [check_cached_effective_target_indexed vect_int_mod {
8978 expr { ([istarget powerpc*-*-*]
8979 && [check_effective_target_has_arch_pwr10])
8980 || [istarget amdgcn-*-*]
8981 || ([istarget loongarch*-*-*]
8982 && [check_effective_target_loongarch_sx])
8983 || ([istarget riscv*-*-*]
8984 && [check_effective_target_riscv_v]) }}]
8987 # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise.
8989 proc check_effective_target_vect_extract_even_odd { } {
8990 return [check_cached_effective_target_indexed extract_even_odd {
8991 expr { [istarget aarch64*-*-*]
8992 || [istarget powerpc*-*-*]
8993 || [is-effective-target arm_neon]
8994 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8995 || [istarget ia64-*-*]
8996 || ([istarget mips*-*-*]
8997 && ([et-is-effective-target mips_msa]
8998 || [et-is-effective-target mpaired_single]))
8999 || ([istarget s390*-*-*]
9000 && [check_effective_target_s390_vx])
9001 || ([istarget riscv*-*-*]
9002 && [check_effective_target_riscv_v]) }}]
9005 # Return 1 if the target supports vector interleaving, 0 otherwise.
9007 proc check_effective_target_vect_interleave { } {
9008 return [check_cached_effective_target_indexed vect_interleave {
9009 expr { [istarget aarch64*-*-*]
9010 || [istarget powerpc*-*-*]
9011 || [is-effective-target arm_neon]
9012 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9013 || [istarget ia64-*-*]
9014 || ([istarget mips*-*-*]
9015 && ([et-is-effective-target mpaired_single]
9016 || [et-is-effective-target mips_msa]))
9017 || ([istarget s390*-*-*]
9018 && [check_effective_target_s390_vx])
9019 || ([istarget riscv*-*-*]
9020 && [check_effective_target_riscv_v]) }}]
9023 foreach N {2 3 4 5 6 7 8} {
9024 eval [string map [list N $N] {
9025 # Return 1 if the target supports 2-vector interleaving
9026 proc check_effective_target_vect_stridedN { } {
9027 return [check_cached_effective_target_indexed vect_stridedN {
9029 && [check_effective_target_vect_interleave]
9030 && [check_effective_target_vect_extract_even_odd] } {
9033 if { ([istarget arm*-*-*]
9034 || [istarget aarch64*-*-*]) && N >= 2 && N <= 4 } {
9037 if { ([istarget riscv*-*-*]) && N >= 2 && N <= 8 } {
9040 if [check_effective_target_vect_fully_masked] {
9049 # Return the list of vector sizes (in bits) that each target supports.
9050 # A vector length of "0" indicates variable-length vectors.
9052 proc available_vector_sizes { } {
9054 if { [istarget aarch64*-*-*] } {
9055 if { [check_effective_target_aarch64_sve] } {
9056 lappend result [aarch64_sve_bits]
9058 lappend result 128 64
9059 } elseif { [istarget arm*-*-*]
9060 && [check_effective_target_arm_neon_ok] } {
9061 lappend result 128 64
9062 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
9063 if { [check_avx_available] && ![check_prefer_avx128] } {
9067 if { ![is-effective-target ia32] } {
9071 } elseif { [istarget sparc*-*-*] } {
9073 } elseif { [istarget amdgcn*-*-*] } {
9074 # 6 different lane counts, and 4 element sizes
9075 lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
9076 } elseif { [istarget riscv*-*-*] } {
9077 if { [check_effective_target_riscv_v] } {
9078 lappend result 0 32 64 128
9082 # The traditional default asumption.
9088 # Return 1 if the target supports multiple vector sizes
9090 proc check_effective_target_vect_multiple_sizes { } {
9091 return [expr { [llength [available_vector_sizes]] > 1 }]
9094 # Return true if variable-length vectors are supported.
9096 proc check_effective_target_vect_variable_length { } {
9097 return [expr { [lindex [available_vector_sizes] 0] == 0 }]
9100 # Return 1 if the target supports vectors of 1024 bits.
9102 proc check_effective_target_vect1024 { } {
9103 return [expr { [lsearch -exact [available_vector_sizes] 1024] >= 0 }]
9106 # Return 1 if the target supports vectors of 512 bits.
9108 proc check_effective_target_vect512 { } {
9109 return [expr { [lsearch -exact [available_vector_sizes] 512] >= 0 }]
9112 # Return 1 if the target supports vectors of 256 bits.
9114 proc check_effective_target_vect256 { } {
9115 return [expr { [lsearch -exact [available_vector_sizes] 256] >= 0 }]
9118 # Return 1 if the target supports vectors of 128 bits.
9120 proc check_effective_target_vect128 { } {
9121 return [expr { [lsearch -exact [available_vector_sizes] 128] >= 0 }]
9124 # Return 1 if the target supports vectors of 64 bits.
9126 proc check_effective_target_vect64 { } {
9127 return [expr { [lsearch -exact [available_vector_sizes] 64] >= 0 }]
9130 # Return 1 if the target supports vectors of 32 bits.
9132 proc check_effective_target_vect32 { } {
9133 return [expr { [lsearch -exact [available_vector_sizes] 32] >= 0 }]
9136 # Return 1 if the target supports vector copysignf calls.
9138 proc check_effective_target_vect_call_copysignf { } {
9139 return [check_cached_effective_target_indexed vect_call_copysignf {
9140 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9141 || [istarget powerpc*-*-*]
9142 || [istarget aarch64*-*-*]
9143 || [istarget amdgcn-*-*]
9144 || ([istarget riscv*-*-*]
9145 && [check_effective_target_riscv_v]) }}]
9148 # Return 1 if the target supports hardware square root instructions.
9150 proc check_effective_target_sqrt_insn { } {
9151 return [check_cached_effective_target sqrt_insn {
9152 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9153 || [check_effective_target_powerpc_sqrt]
9154 || [istarget aarch64*-*-*]
9155 || ([istarget arm*-*-*] && [check_effective_target_arm_vfp_ok])
9156 || ([istarget s390*-*-*]
9157 && [check_effective_target_s390_vx])
9158 || [istarget amdgcn-*-*] }}]
9161 # Return any additional options to enable square root intructions.
9163 proc add_options_for_sqrt_insn { flags } {
9164 if { [istarget amdgcn*-*-*] } {
9165 return "$flags -ffast-math"
9167 if { [istarget arm*-*-*] } {
9168 return [add_options_for_arm_vfp "$flags"]
9173 # Return 1 if the target supports vector sqrtf calls.
9175 proc check_effective_target_vect_call_sqrtf { } {
9176 return [check_cached_effective_target_indexed vect_call_sqrtf {
9177 expr { [istarget aarch64*-*-*]
9178 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9179 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
9180 || ([istarget s390*-*-*]
9181 && [check_effective_target_s390_vx])
9182 || [istarget amdgcn-*-*]
9183 || ([istarget riscv*-*-*]
9184 && [check_effective_target_riscv_v]) }}]
9187 # Return 1 if the target supports vector lrint calls.
9189 proc check_effective_target_vect_call_lrint { } {
9190 set et_vect_call_lrint 0
9191 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
9192 && [check_effective_target_ilp32])
9193 || [istarget amdgcn-*-*] } {
9194 set et_vect_call_lrint 1
9197 verbose "check_effective_target_vect_call_lrint: returning $et_vect_call_lrint" 2
9198 return $et_vect_call_lrint
9201 # Return 1 if the target supports vector btrunc calls.
9203 proc check_effective_target_vect_call_btrunc { } {
9204 return [check_cached_effective_target_indexed vect_call_btrunc {
9205 expr { [istarget aarch64*-*-*]
9206 || [istarget amdgcn-*-*] }}]
9209 # Return 1 if the target supports vector btruncf calls.
9211 proc check_effective_target_vect_call_btruncf { } {
9212 return [check_cached_effective_target_indexed vect_call_btruncf {
9213 expr { [istarget aarch64*-*-*]
9214 || [istarget amdgcn-*-*] }}]
9217 # Return 1 if the target supports vector ceil calls.
9219 proc check_effective_target_vect_call_ceil { } {
9220 return [check_cached_effective_target_indexed vect_call_ceil {
9221 expr { [istarget aarch64*-*-*]
9222 || [istarget amdgcn-*-*] }}]
9225 # Return 1 if the target supports vector ceilf calls.
9227 proc check_effective_target_vect_call_ceilf { } {
9228 return [check_cached_effective_target_indexed vect_call_ceilf {
9229 expr { [istarget aarch64*-*-*]
9230 || [istarget amdgcn-*-*] }}]
9233 # Return 1 if the target supports vector floor calls.
9235 proc check_effective_target_vect_call_floor { } {
9236 return [check_cached_effective_target_indexed vect_call_floor {
9237 expr { [istarget aarch64*-*-*]
9238 || [istarget amdgcn-*-*] }}]
9241 # Return 1 if the target supports vector floorf calls.
9243 proc check_effective_target_vect_call_floorf { } {
9244 return [check_cached_effective_target_indexed vect_call_floorf {
9245 expr { [istarget aarch64*-*-*]
9246 || [istarget amdgcn-*-*] }}]
9249 # Return 1 if the target supports vector lceil calls.
9251 proc check_effective_target_vect_call_lceil { } {
9252 return [check_cached_effective_target_indexed vect_call_lceil {
9253 expr { [istarget aarch64*-*-*] }}]
9256 # Return 1 if the target supports vector lfloor calls.
9258 proc check_effective_target_vect_call_lfloor { } {
9259 return [check_cached_effective_target_indexed vect_call_lfloor {
9260 expr { [istarget aarch64*-*-*] }}]
9263 # Return 1 if the target supports vector nearbyint calls.
9265 proc check_effective_target_vect_call_nearbyint { } {
9266 return [check_cached_effective_target_indexed vect_call_nearbyint {
9267 expr { [istarget aarch64*-*-*] }}]
9270 # Return 1 if the target supports vector nearbyintf calls.
9272 proc check_effective_target_vect_call_nearbyintf { } {
9273 return [check_cached_effective_target_indexed vect_call_nearbyintf {
9274 expr { [istarget aarch64*-*-*] }}]
9277 # Return 1 if the target supports vector round calls.
9279 proc check_effective_target_vect_call_round { } {
9280 return [check_cached_effective_target_indexed vect_call_round {
9281 expr { [istarget aarch64*-*-*] }}]
9284 # Return 1 if the target supports vector roundf calls.
9286 proc check_effective_target_vect_call_roundf { } {
9287 return [check_cached_effective_target_indexed vect_call_roundf {
9288 expr { [istarget aarch64*-*-*] }}]
9291 # Return 1 if the target supports AND, OR and XOR reduction.
9293 proc check_effective_target_vect_logical_reduc { } {
9294 return [expr { [check_effective_target_aarch64_sve]
9295 || [istarget amdgcn-*-*]
9296 || [check_effective_target_riscv_v]
9297 || [istarget i?86-*-*] || [istarget x86_64-*-*]}]
9300 # Return 1 if the target supports the fold_extract_last optab.
9302 proc check_effective_target_vect_fold_extract_last { } {
9303 return [expr { [check_effective_target_aarch64_sve]
9304 || [istarget amdgcn*-*-*]
9305 || [check_effective_target_riscv_v] }]
9308 # Return 1 if the target supports section-anchors
9310 proc check_effective_target_section_anchors { } {
9311 return [check_cached_effective_target section_anchors {
9312 expr { [istarget powerpc*-*-*]
9313 || [istarget arm*-*-*]
9314 || [istarget aarch64*-*-*] }}]
9317 # Return 1 if the target supports atomic operations on "int_128" values.
9319 proc check_effective_target_sync_int_128 { } {
9323 # Return 1 if the target supports atomic operations on "int_128" values
9324 # and can execute them.
9325 # This requires support for both compare-and-swap and true atomic loads.
9327 proc check_effective_target_sync_int_128_runtime { } {
9331 # Return 1 if the target supports atomic operations on "long long".
9333 # Note: 32bit x86 targets require -march=pentium in dg-options.
9334 # Note: 32bit s390 targets require -mzarch in dg-options.
9336 proc check_effective_target_sync_long_long { } {
9337 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
9338 || [istarget aarch64*-*-*]
9339 || [istarget arm*-*-*]
9340 || [istarget alpha*-*-*]
9341 || ([istarget sparc*-*-*] && [check_effective_target_lp64])
9342 || [istarget s390*-*-*] } {
9349 # Return 1 if the target supports popcount on long.
9351 proc check_effective_target_popcountl { } {
9352 return [check_no_messages_and_pattern popcountl "!\\(call" rtl-expand {
9355 return __builtin_popcountl (b);
9360 # Return 1 if the target supports popcount on long long.
9362 proc check_effective_target_popcountll { } {
9363 return [check_no_messages_and_pattern popcountll "!\\(call" rtl-expand {
9364 int foo (long long b)
9366 return __builtin_popcountll (b);
9372 # Return 1 if the target supports popcount on int.
9374 proc check_effective_target_popcount { } {
9375 return [check_no_messages_and_pattern popcount "!\\(call" rtl-expand {
9378 return __builtin_popcount (b);
9383 # Return 1 if the target supports clz on int.
9385 proc check_effective_target_clz { } {
9386 return [check_no_messages_and_pattern clz "!\\(call" rtl-expand {
9389 return __builtin_clz (b);
9394 # Return 1 if the target supports clz on long.
9396 proc check_effective_target_clzl { } {
9397 return [check_no_messages_and_pattern clzl "!\\(call" rtl-expand {
9400 return __builtin_clzl (b);
9405 # Return 1 if the target supports clz on long long.
9407 proc check_effective_target_clzll { } {
9408 return [check_no_messages_and_pattern clzll "!\\(call" rtl-expand {
9409 int foo (long long b)
9411 return __builtin_clzll (b);
9416 # Return 1 if the target supports ctz on int.
9418 proc check_effective_target_ctz { } {
9419 return [check_no_messages_and_pattern ctz "!\\(call" rtl-expand {
9422 return __builtin_ctz (b);
9427 # Return 1 if the target supports ctz on long.
9429 proc check_effective_target_ctzl { } {
9430 return [check_no_messages_and_pattern ctzl "!\\(call" rtl-expand {
9433 return __builtin_ctzl (b);
9438 # Return 1 if the target supports ctz on long long.
9440 proc check_effective_target_ctzll { } {
9441 return [check_no_messages_and_pattern ctzll "!\\(call" rtl-expand {
9442 int foo (long long b)
9444 return __builtin_ctzll (b);
9449 # Return 1 if the target supports atomic operations on "long long"
9450 # and can execute them.
9452 # Note: 32bit x86 targets require -march=pentium in dg-options.
9454 proc check_effective_target_sync_long_long_runtime { } {
9455 if { (([istarget x86_64-*-*] || [istarget i?86-*-*])
9456 && [check_cached_effective_target sync_long_long_available {
9457 check_runtime_nocache sync_long_long_available {
9461 unsigned int eax, ebx, ecx, edx;
9462 if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
9463 return !(edx & bit_CMPXCHG8B);
9468 || [istarget aarch64*-*-*]
9469 || [istarget arm*-*-uclinuxfdpiceabi]
9470 || ([istarget arm*-*-linux-*]
9471 && [check_runtime sync_longlong_runtime {
9477 if (sizeof (long long) != 8)
9480 /* Just check for native;
9481 checking for kernel fallback is tricky. */
9482 asm volatile ("ldrexd r0,r1, [%0]"
9483 : : "r" (&l1) : "r0", "r1");
9487 || [istarget alpha*-*-*]
9488 || ([istarget sparc*-*-*]
9489 && [check_effective_target_lp64]
9490 && [check_effective_target_ultrasparc_hw])
9491 || ([istarget powerpc*-*-*] && [check_effective_target_lp64]) } {
9498 # Return 1 if the target supports byte swap instructions.
9500 proc check_effective_target_bswap { } {
9501 return [check_cached_effective_target bswap {
9502 expr { [istarget aarch64*-*-*]
9503 || [istarget alpha*-*-*]
9504 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9505 || [istarget m68k-*-*]
9506 || [istarget powerpc*-*-*]
9507 || [istarget rs6000-*-*]
9508 || [istarget s390*-*-*]
9509 || ([istarget riscv*-*-*]
9510 && [check_no_compiler_messages_nocache riscv_zbb object {
9511 #if __riscv_zbb <= 0
9512 #error ZBB is not enabled
9516 || ([istarget arm*-*-*]
9517 && [check_no_compiler_messages_nocache arm_v6_or_later object {
9519 #error not armv6 or later
9525 # Return 1 if the target supports atomic operations on "int" and "long".
9527 proc check_effective_target_sync_int_long { } {
9528 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9529 # load-reserved/store-conditional instructions.
9530 return [check_cached_effective_target sync_int_long {
9531 expr { [istarget ia64-*-*]
9532 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9533 || [istarget aarch64*-*-*]
9534 || [istarget alpha*-*-*]
9535 || [istarget arm*-*-linux-*]
9536 || [istarget arm*-*-uclinuxfdpiceabi]
9537 || ([istarget arm*-*-*]
9538 && [check_effective_target_arm_acq_rel])
9539 || [istarget bfin*-*linux*]
9540 || [istarget hppa*-*linux*]
9541 || [istarget s390*-*-*]
9542 || [istarget powerpc*-*-*]
9543 || [istarget cris-*-*]
9544 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9545 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9546 || [check_effective_target_mips_llsc]
9547 || [istarget nvptx*-*-*]
9551 # Return 1 if the target supports atomic operations on "int" and "long" on
9554 proc check_effective_target_sync_int_long_stack { } {
9555 return [check_cached_effective_target sync_int_long_stack {
9556 expr { ![istarget nvptx*-*-*]
9557 && [check_effective_target_sync_int_long]
9561 # Return 1 if the target supports atomic operations on "char" and "short".
9563 proc check_effective_target_sync_char_short { } {
9564 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9565 # load-reserved/store-conditional instructions.
9566 return [check_cached_effective_target sync_char_short {
9567 expr { [istarget aarch64*-*-*]
9568 || [istarget ia64-*-*]
9569 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9570 || [istarget alpha*-*-*]
9571 || [istarget arm*-*-linux-*]
9572 || [istarget arm*-*-uclinuxfdpiceabi]
9573 || ([istarget arm*-*-*]
9574 && [check_effective_target_arm_acq_rel])
9575 || [istarget hppa*-*linux*]
9576 || [istarget s390*-*-*]
9577 || [istarget powerpc*-*-*]
9578 || [istarget cris-*-*]
9579 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9580 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9581 || [istarget loongarch*-*-*]
9582 || [check_effective_target_mips_llsc] }}]
9585 # Return 1 if thread_fence does not rely on __sync_synchronize
9588 proc check_effective_target_thread_fence {} {
9589 return [check_no_compiler_messages thread_fence executable {
9591 __atomic_thread_fence (__ATOMIC_SEQ_CST);
9597 # Return 1 if the target uses a ColdFire FPU.
9599 proc check_effective_target_coldfire_fpu { } {
9600 return [check_no_compiler_messages coldfire_fpu assembly {
9607 # Return true if this is a uClibc target.
9609 proc check_effective_target_uclibc {} {
9610 return [check_no_compiler_messages uclibc object {
9611 #include <features.h>
9612 #if !defined (__UCLIBC__)
9618 # Return true if this is a uclibc target and if the uclibc feature
9619 # described by __$feature__ is not present.
9621 proc check_missing_uclibc_feature {feature} {
9622 return [check_no_compiler_messages $feature object "
9623 #include <features.h>
9624 #if !defined (__UCLIBC) || defined (__${feature}__)
9630 # Return true if this is a Newlib target.
9632 proc check_effective_target_newlib {} {
9633 return [check_no_compiler_messages newlib object {
9638 # Return true if GCC was configured with --enable-newlib-nano-formatted-io
9639 proc check_effective_target_newlib_nano_io { } {
9640 return [check_configured_with "--enable-newlib-nano-formatted-io"]
9643 # Some newlib versions don't provide a frexpl and instead depend
9644 # on frexp to implement long double conversions in their printf-like
9645 # functions. This leads to broken results. Detect such versions here.
9647 proc check_effective_target_newlib_broken_long_double_io {} {
9648 if { [is-effective-target newlib] && ![is-effective-target frexpl] } {
9654 # Return true if this is NOT a Bionic target.
9656 proc check_effective_target_non_bionic {} {
9657 return [check_no_compiler_messages non_bionic object {
9659 #if defined (__BIONIC__)
9665 # Return true if this target has error.h header.
9667 proc check_effective_target_error_h {} {
9668 return [check_no_compiler_messages error_h object {
9673 # Return true if this target has tgmath.h header.
9675 proc check_effective_target_tgmath_h {} {
9676 return [check_no_compiler_messages tgmath_h object {
9681 # Return true if target's libc supports complex functions.
9683 proc check_effective_target_libc_has_complex_functions {} {
9684 return [check_no_compiler_messages libc_has_complex_functions object {
9685 #include <complex.h>
9690 # (a) an error of a few ULP is expected in string to floating-point
9691 # conversion functions; and
9692 # (b) overflow is not always detected correctly by those functions.
9694 proc check_effective_target_lax_strtofp {} {
9695 # By default, assume that all uClibc targets suffer from this.
9696 return [check_effective_target_uclibc]
9699 # Return 1 if this is a target for which wcsftime is a dummy
9700 # function that always returns 0.
9702 proc check_effective_target_dummy_wcsftime {} {
9703 # By default, assume that all uClibc targets suffer from this.
9704 return [check_effective_target_uclibc]
9707 # Return 1 if constructors with initialization priority arguments are
9708 # supposed on this target.
9710 proc check_effective_target_init_priority {} {
9711 return [check_no_compiler_messages init_priority assembly "
9712 void f() __attribute__((constructor (1000)));
9717 # Return 1 if the target matches the effective target 'arg', 0 otherwise.
9718 # This can be used with any check_* proc that takes no argument and
9719 # returns only 1 or 0. It could be used with check_* procs that take
9720 # arguments with keywords that pass particular arguments.
9722 proc is-effective-target { arg } {
9725 if { ![info exists et_index] } {
9726 # Initialize the effective target index that is used in some
9727 # check_effective_target_* procs.
9730 if { [info procs check_effective_target_${arg}] != [list] } {
9731 set selected [check_effective_target_${arg}]
9734 "vmx_hw" { set selected [check_vmx_hw_available] }
9735 "vsx_hw" { set selected [check_vsx_hw_available] }
9736 "p8vector_hw" { set selected [check_p8vector_hw_available] }
9737 "p9vector_hw" { set selected [check_p9vector_hw_available] }
9738 "p9modulo_hw" { set selected [check_p9modulo_hw_available] }
9739 "power10_hw" { set selected [check_power10_hw_available] }
9740 "ppc_float128_sw" { set selected [check_ppc_float128_sw_available] }
9741 "ppc_float128_hw" { set selected [check_ppc_float128_hw_available] }
9742 "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }
9743 "ppc_cpu_supports_hw" { set selected [check_ppc_cpu_supports_hw_available] }
9744 "ppc_mma_hw" { set selected [check_ppc_mma_hw_available] }
9745 "dfp_hw" { set selected [check_dfp_hw_available] }
9746 "htm_hw" { set selected [check_htm_hw_available] }
9747 "named_sections" { set selected [check_named_sections_available] }
9748 "gc_sections" { set selected [check_gc_sections_available] }
9749 "cxa_atexit" { set selected [check_cxa_atexit_available] }
9750 default { error "unknown effective target keyword `$arg'" }
9754 verbose "is-effective-target: $arg $selected" 2
9758 # Return 1 if the argument is an effective-target keyword, 0 otherwise.
9760 proc is-effective-target-keyword { arg } {
9761 if { [info procs check_effective_target_${arg}] != [list] } {
9764 # These have different names for their check_* procs.
9766 "vmx_hw" { return 1 }
9767 "vsx_hw" { return 1 }
9768 "p8vector_hw" { return 1 }
9769 "p9vector_hw" { return 1 }
9770 "p9modulo_hw" { return 1 }
9771 "power10_hw" { return 1 }
9772 "ppc_float128_sw" { return 1 }
9773 "ppc_float128_hw" { return 1 }
9774 "ppc_recip_hw" { return 1 }
9775 "ppc_mma_hw" { return 1 }
9776 "dfp_hw" { return 1 }
9777 "htm_hw" { return 1 }
9778 "named_sections" { return 1 }
9779 "gc_sections" { return 1 }
9780 "cxa_atexit" { return 1 }
9781 "ppc_cpu_supports_hw" { return 1 }
9782 default { return 0 }
9787 # Execute tests for all targets in EFFECTIVE_TARGETS list. Set et_index to
9788 # indicate what target is currently being processed. This is for
9789 # the vectorizer tests, e.g. vect_int, to keep track what target supports
9792 proc et-dg-runtest { runtest testcases flags default-extra-flags } {
9793 global dg-do-what-default
9794 global EFFECTIVE_TARGETS
9797 if { [llength $EFFECTIVE_TARGETS] > 0 } {
9798 foreach target $EFFECTIVE_TARGETS {
9799 set target_flags $flags
9800 set dg-do-what-default compile
9801 set et_index [lsearch -exact $EFFECTIVE_TARGETS $target]
9802 if { [info procs add_options_for_${target}] != [list] } {
9803 set target_flags [add_options_for_${target} "$flags"]
9805 if { [info procs check_effective_target_${target}_runtime]
9806 != [list] && [check_effective_target_${target}_runtime] } {
9807 set dg-do-what-default run
9809 $runtest $testcases $target_flags ${default-extra-flags}
9813 $runtest $testcases $flags ${default-extra-flags}
9817 # Return 1 if a target matches the target in EFFECTIVE_TARGETS at index
9818 # et_index, 0 otherwise.
9820 proc et-is-effective-target { target } {
9821 global EFFECTIVE_TARGETS
9824 if { [info exists EFFECTIVE_TARGETS] } {
9825 if { [llength $EFFECTIVE_TARGETS] > $et_index
9826 && [lindex $EFFECTIVE_TARGETS $et_index] == $target } {
9832 return [check_effective_target_${target}]
9836 # Return 1 if target default to short enums
9838 proc check_effective_target_short_enums { } {
9839 return [check_no_compiler_messages short_enums assembly {
9841 int s[sizeof (enum foo) == 1 ? 1 : -1];
9845 # Return 1 if target supports merging string constants at link time.
9847 proc check_effective_target_string_merging { } {
9848 return [check_no_messages_and_pattern string_merging \
9849 "rodata\\.str" assembly {
9850 const char *var = "String";
9854 # Return 1 if target has the basic signed and unsigned types in
9855 # <stdint.h>, 0 otherwise. This will be obsolete when GCC ensures a
9856 # working <stdint.h> for all targets.
9858 proc check_effective_target_stdint_types { } {
9859 return [check_no_compiler_messages stdint_types assembly {
9861 int8_t a; int16_t b; int32_t c; int64_t d;
9862 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
9866 # Like check_effective_target_stdint_types, but test what happens when
9867 # -mbig-endian is passed. This test only makes sense on targets that
9868 # support -mbig-endian; it will fail elsewhere.
9870 proc check_effective_target_stdint_types_mbig_endian { } {
9871 return [check_no_compiler_messages stdint_types_mbig_endian assembly {
9873 int8_t a; int16_t b; int32_t c; int64_t d;
9874 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
9878 # Return 1 if target has the basic signed and unsigned types in
9879 # <inttypes.h>, 0 otherwise. This is for tests that GCC's notions of
9880 # these types agree with those in the header, as some systems have
9881 # only <inttypes.h>.
9883 proc check_effective_target_inttypes_types { } {
9884 return [check_no_compiler_messages inttypes_types assembly {
9885 #include <inttypes.h>
9886 int8_t a; int16_t b; int32_t c; int64_t d;
9887 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
9891 # Return 1 if programs are intended to be run on a simulator
9892 # (i.e. slowly) rather than hardware (i.e. fast).
9894 proc check_effective_target_simulator { } {
9896 # All "src/sim" simulators set this one.
9897 if [board_info target exists is_simulator] {
9898 return [board_info target is_simulator]
9901 # The "sid" simulators don't set that one, but at least they set
9903 if [board_info target exists slow_simulator] {
9904 return [board_info target slow_simulator]
9910 # Return 1 if programs are intended to be run on hardware rather than
9913 proc check_effective_target_hw { } {
9915 # All "src/sim" simulators set this one.
9916 if [board_info target exists is_simulator] {
9917 if [board_info target is_simulator] {
9924 # The "sid" simulators don't set that one, but at least they set
9926 if [board_info target exists slow_simulator] {
9927 if [board_info target slow_simulator] {
9937 # Return 1 if the target is a VxWorks kernel.
9939 proc check_effective_target_vxworks_kernel { } {
9940 return [check_no_compiler_messages vxworks_kernel assembly {
9941 #if !defined __vxworks || defined __RTP__
9947 # Return 1 if the target is a VxWorks RTP.
9949 proc check_effective_target_vxworks_rtp { } {
9950 return [check_no_compiler_messages vxworks_rtp assembly {
9951 #if !defined __vxworks || !defined __RTP__
9957 # Return 1 if the target is expected to provide wide character support.
9959 proc check_effective_target_wchar { } {
9960 if {[check_missing_uclibc_feature UCLIBC_HAS_WCHAR]} {
9963 return [check_no_compiler_messages wchar assembly {
9968 # Return 1 if the target has <pthread.h>.
9970 proc check_effective_target_pthread_h { } {
9971 return [check_no_compiler_messages pthread_h assembly {
9972 #include <pthread.h>
9976 # Return 1 if the target can truncate a file from a file-descriptor,
9977 # as used by libgfortran/io/unix.c:fd_truncate; i.e. ftruncate or
9978 # chsize. We test for a trivially functional truncation; no stubs.
9979 # As libgfortran uses _FILE_OFFSET_BITS 64, we do too; it'll cause a
9980 # different function to be used.
9982 proc check_effective_target_fd_truncate { } {
9984 #define _FILE_OFFSET_BITS 64
9991 FILE *f = fopen ("tst.tmp", "wb");
9993 const char t[] = "test writing more than ten characters";
9997 write (fd, t, sizeof (t) - 1);
9999 if (ftruncate (fd, 10) != 0)
10005 unlink ("tst.tmp");
10008 f = fopen ("tst.tmp", "rb");
10009 if (fread (s, 1, sizeof (s), f) != 10 || strncmp (s, t, 10) != 0)
10012 unlink ("tst.tmp");
10017 if { [check_runtime ftruncate $prog] } {
10021 regsub "ftruncate" $prog "chsize" prog
10022 return [check_runtime chsize $prog]
10025 # Add to FLAGS all the target-specific flags needed to enable
10026 # full IEEE compliance mode.
10028 proc add_options_for_ieee { flags } {
10029 if { [istarget alpha*-*-*]
10030 || [istarget sh*-*-*] } {
10031 return "$flags -mieee"
10033 if { [istarget rx-*-*] } {
10034 return "$flags -mnofpu"
10039 if {![info exists flags_to_postpone]} {
10040 set flags_to_postpone ""
10043 # Add to FLAGS the flags needed to enable functions to bind locally
10044 # when using pic/PIC passes in the testsuite.
10045 proc add_options_for_bind_pic_locally { flags } {
10046 global flags_to_postpone
10048 # Instead of returning 'flags' with the -fPIE or -fpie appended, we save it
10049 # in 'flags_to_postpone' and append it later in gcc_target_compile procedure in
10050 # order to make sure that the multilib_flags doesn't override this.
10052 if {[check_no_compiler_messages using_pic2 assembly {
10054 #error __PIC__ != 2
10057 set flags_to_postpone "-fPIE"
10060 if {[check_no_compiler_messages using_pic1 assembly {
10062 #error __PIC__ != 1
10065 set flags_to_postpone "-fpie"
10071 # Add to FLAGS the flags needed to enable 64-bit vectors.
10073 proc add_options_for_double_vectors { flags } {
10074 if [is-effective-target arm_neon_ok] {
10075 return "$flags -mvectorize-with-neon-double"
10081 # Add to FLAGS the flags needed to define the STACK_SIZE macro.
10083 proc add_options_for_stack_size { flags } {
10084 if [is-effective-target stack_size] {
10085 set stack_size [dg-effective-target-value stack_size]
10086 return "$flags -DSTACK_SIZE=$stack_size"
10092 # Return 1 if the target provides a full C99 runtime.
10094 proc check_effective_target_c99_runtime { } {
10095 return [check_cached_effective_target c99_runtime {
10098 set file [open "$srcdir/gcc.dg/builtins-config.h"]
10099 set contents [read $file]
10102 #ifndef HAVE_C99_RUNTIME
10103 #error !HAVE_C99_RUNTIME
10106 check_no_compiler_messages_nocache c99_runtime assembly $contents
10110 # Return 1 if the target supports DWARF CFI directives.
10112 proc check_effective_target_cfi { } {
10113 return [check_no_compiler_messages cfi assembly {
10114 #ifdef __GCC_HAVE_DWARF2_CFI_ASM
10122 # Return 1 if the target provides the D runtime.
10124 proc check_effective_target_d_runtime { } {
10125 return [check_no_compiler_messages d_runtime executable {
10129 extern(C) int main() {
10135 # Return 1 if the target provides the D standard library.
10137 proc check_effective_target_d_runtime_has_std_library { } {
10138 return [check_no_compiler_messages d_runtime_has_std_library executable {
10142 extern(C) int main() {
10144 real function(real) pcos = &cos;
10150 # Return 1 if target wchar_t is at least 4 bytes.
10152 proc check_effective_target_4byte_wchar_t { } {
10153 return [check_no_compiler_messages 4byte_wchar_t object {
10154 int dummy[sizeof (__WCHAR_TYPE__) >= 4 ? 1 : -1];
10158 # Return 1 if the target supports automatic stack alignment.
10160 proc check_effective_target_automatic_stack_alignment { } {
10161 # Ordinarily x86 supports automatic stack alignment ...
10162 if { [istarget i?86*-*-*] || [istarget x86_64-*-*] } then {
10163 if { [istarget *-*-mingw*] || [istarget *-*-cygwin*] } {
10164 # ... except Win64 SEH doesn't. Succeed for Win32 though.
10165 return [check_effective_target_ilp32];
10172 # Return true if we are compiling for AVX target.
10174 proc check_avx_available { } {
10175 if { [check_no_compiler_messages avx_available assembly {
10185 # Return true if we are compiling for AVX2 target.
10187 proc check_avx2_available { } {
10188 if { [check_no_compiler_messages avx2_available assembly {
10198 # Return true if we are compiling for SSSE3 target.
10200 proc check_ssse3_available { } {
10201 if { [check_no_compiler_messages sse3a_available assembly {
10211 # Return true if 32- and 16-bytes vectors are available.
10213 proc check_effective_target_vect_sizes_32B_16B { } {
10214 return [expr { [available_vector_sizes] == [list 256 128] }]
10217 # Return true if 16- and 8-bytes vectors are available.
10219 proc check_effective_target_vect_sizes_16B_8B { } {
10220 if { [check_avx_available]
10221 || [is-effective-target arm_neon]
10222 || [istarget aarch64*-*-*]
10223 || [check_effective_target_riscv_v] } {
10231 # Return true if 128-bits vectors are preferred even if 256-bits vectors
10234 proc check_prefer_avx128 { } {
10235 if ![check_avx_available] {
10238 return [check_no_messages_and_pattern avx_explicit "xmm" assembly {
10239 float a[1024],b[1024],c[1024];
10240 void foo (void) { int i; for (i = 0; i < 1024; i++) a[i]=b[i]+c[i];}
10241 } "-O2 -ftree-vectorize"]
10245 # Return 1 if avx512fp16 instructions can be compiled.
10247 proc check_effective_target_avx512fp16 { } {
10248 return [check_no_compiler_messages avx512fp16 object {
10251 asm volatile ("vmovw %edi, %xmm0");
10252 asm volatile ("vfcmulcph %xmm1, %xmm2, %xmm3{%k1}");
10254 } "-O2 -mavx512fp16" ]
10257 # Return 1 if avx512f instructions can be compiled.
10259 proc check_effective_target_avx512f { } {
10260 return [check_no_compiler_messages avx512f object {
10261 typedef double __m512d __attribute__ ((__vector_size__ (64)));
10262 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10264 __m512d _mm512_add (__m512d a)
10266 return __builtin_ia32_addpd512_mask (a, a, a, 1, 4);
10269 __m128d _mm128_add (__m128d a)
10271 return __builtin_ia32_addsd_round (a, a, 8);
10274 __m128d _mm128_getmant (__m128d a)
10276 return __builtin_ia32_getmantsd_round (a, a, 0, 8);
10278 } "-O2 -mavx512f" ]
10281 # Return 1 if avx instructions can be compiled.
10283 proc check_effective_target_avx { } {
10284 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
10287 return [check_no_compiler_messages avx object {
10288 void _mm256_zeroall (void)
10290 __builtin_ia32_vzeroall ();
10295 # Return 1 if avx2 instructions can be compiled.
10296 proc check_effective_target_avx2 { } {
10297 return [check_no_compiler_messages avx2 object {
10298 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10300 mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
10302 return __builtin_ia32_andnotsi256 (__X, __Y);
10307 # Return 1 if avxvnni instructions can be compiled.
10308 proc check_effective_target_avxvnni { } {
10309 return [check_no_compiler_messages avxvnni object {
10310 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10312 _mm256_dpbusd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10314 return __builtin_ia32_vpdpbusd_v8si (__A, __B, __C);
10319 # Return 1 if avxifma instructions can be compiled.
10320 proc check_effective_target_avxifma { } {
10321 return [check_no_compiler_messages avxifma object {
10322 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10324 _mm256_maddlo_epu64 (__v4di __A, __v4di __B, __v4di __C)
10326 return __builtin_ia32_vpmadd52luq256 (__A, __B, __C);
10328 } "-O0 -mavxifma" ]
10331 # Return 1 if avxvnniint8 instructions can be compiled.
10332 proc check_effective_target_avxvnniint8 { } {
10333 return [check_no_compiler_messages avxvnniint8 object {
10334 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10336 _mm256_dpbssd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10338 return __builtin_ia32_vpdpbssd256 (__A, __B, __C);
10340 } "-O0 -mavxvnniint8" ]
10343 # Return 1 if avxneconvert instructions can be compiled.
10344 proc check_effective_target_avxneconvert { } {
10345 return [check_no_compiler_messages avxneconvert object {
10346 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
10348 _mm_bcstnebf16_ps (const void *__P)
10350 return (__m128) __builtin_ia32_vbcstnebf162ps128 ((const __bf16 *) __P);
10352 } "-O0 -mavxneconvert" ]
10355 # Return 1 if cmpccxadd instructions can be compiled.
10356 proc check_effective_target_cmpccxadd { } {
10357 return [check_no_compiler_messages cmpccxadd object {
10358 int _cmpccxadd_epi32 (int *__A, int __B, int __C, const int __D)
10360 return (int)__builtin_ia32_cmpccxadd (__A, __B, __C, 1);
10365 # Return 1 if raoint instructions can be compiled.
10366 proc check_effective_target_raoint { } {
10367 return [check_no_compiler_messages raoint object {
10369 _aadd_si32 (int *__A, int __B)
10371 return __builtin_ia32_aadd32((int *)__A, __B);
10376 # Return 1 if amx-complex instructions can be compiled.
10377 proc check_effective_target_amx_complex { } {
10378 return [check_no_compiler_messages amx_complex object {
10382 __asm__ volatile ("tcmmimfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10384 } "-mamx-complex" ]
10387 # Return 1 if avxvnniint16 instructions can be compiled.
10388 proc check_effective_target_avxvnniint16 { } {
10389 return [check_no_compiler_messages avxvnniint16 object {
10390 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10392 _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C)
10394 return __builtin_ia32_vpdpwsud256 (__A, __B, __C);
10396 } "-O0 -mavxvnniint16" ]
10399 # Return 1 if sm3 instructions can be compiled.
10400 proc check_effective_target_sm3 { } {
10401 return [check_no_compiler_messages sm3 object {
10402 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10403 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10405 _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
10407 return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A,
10414 # Return 1 if sha512 instructions can be compiled.
10415 proc check_effective_target_sha512 { } {
10416 return [check_no_compiler_messages sha512 object {
10417 typedef long long __m256i __attribute__ ((__vector_size__ (32)));
10418 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10420 _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
10422 return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A,
10428 # Return 1 if sm4 instructions can be compiled.
10429 proc check_effective_target_sm4 { } {
10430 return [check_no_compiler_messages sm4 object {
10431 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10432 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10434 _mm_sm4key4_epi32 (__m128i __A, __m128i __B)
10436 return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A,
10442 proc check_effective_target_apxf { } {
10443 return [check_no_compiler_messages apxf object {
10447 __asm__ volatile ("add\t%%r16, %%r31" ::);
10452 # Return 1 if sse instructions can be compiled.
10453 proc check_effective_target_sse { } {
10454 return [check_no_compiler_messages sse object {
10457 __builtin_ia32_stmxcsr ();
10463 # Return 1 if sse2 instructions can be compiled.
10464 proc check_effective_target_sse2 { } {
10465 return [check_no_compiler_messages sse2 object {
10466 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10468 __m128i _mm_srli_si128 (__m128i __A, int __N)
10470 return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
10475 # Return 1 if sse4.1 instructions can be compiled.
10476 proc check_effective_target_sse4 { } {
10477 return [check_no_compiler_messages sse4.1 object {
10478 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10479 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10481 __m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
10483 return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
10489 # Return 1 if F16C instructions can be compiled.
10491 proc check_effective_target_f16c { } {
10492 return [check_no_compiler_messages f16c object {
10493 #include "immintrin.h"
10495 foo (unsigned short val)
10497 return _cvtsh_ss (val);
10502 proc check_effective_target_ms_hook_prologue { } {
10503 if { [check_no_compiler_messages ms_hook_prologue object {
10504 void __attribute__ ((__ms_hook_prologue__)) foo ();
10512 # Return 1 if 3dnow instructions can be compiled.
10513 proc check_effective_target_3dnow { } {
10514 return [check_no_compiler_messages 3dnow object {
10515 typedef int __m64 __attribute__ ((__vector_size__ (8)));
10516 typedef float __v2sf __attribute__ ((__vector_size__ (8)));
10518 __m64 _m_pfadd (__m64 __A, __m64 __B)
10520 return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B);
10525 # Return 1 if sse3 instructions can be compiled.
10526 proc check_effective_target_sse3 { } {
10527 return [check_no_compiler_messages sse3 object {
10528 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10529 typedef double __v2df __attribute__ ((__vector_size__ (16)));
10531 __m128d _mm_addsub_pd (__m128d __X, __m128d __Y)
10533 return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
10538 # Return 1 if ssse3 instructions can be compiled.
10539 proc check_effective_target_ssse3 { } {
10540 return [check_no_compiler_messages ssse3 object {
10541 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10542 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10544 __m128i _mm_abs_epi32 (__m128i __X)
10546 return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
10551 # Return 1 if aes instructions can be compiled.
10552 proc check_effective_target_aes { } {
10553 return [check_no_compiler_messages aes object {
10554 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10555 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10557 __m128i _mm_aesimc_si128 (__m128i __X)
10559 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10564 # Return 1 if vaes instructions can be compiled.
10565 proc check_effective_target_vaes { } {
10566 return [check_no_compiler_messages vaes object {
10567 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10568 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10570 __m128i _mm_aesimc_si128 (__m128i __X)
10572 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10574 } "-O2 -maes -mavx" ]
10577 # Return 1 if pclmul instructions can be compiled.
10578 proc check_effective_target_pclmul { } {
10579 return [check_no_compiler_messages pclmul object {
10580 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10581 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10583 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10585 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10592 # Return 1 if vpclmul instructions can be compiled.
10593 proc check_effective_target_vpclmul { } {
10594 return [check_no_compiler_messages vpclmul object {
10595 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10596 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10598 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10600 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10604 } "-O2 -mpclmul -mavx" ]
10607 # Return 1 if sse4a instructions can be compiled.
10608 proc check_effective_target_sse4a { } {
10609 return [check_no_compiler_messages sse4a object {
10610 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10611 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10613 __m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
10615 return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
10620 # Return 1 if fma4 instructions can be compiled.
10621 proc check_effective_target_fma4 { } {
10622 return [check_no_compiler_messages fma4 object {
10623 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10624 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10625 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10627 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10634 # Return 1 if fma instructions can be compiled.
10635 proc check_effective_target_fma { } {
10636 return [check_no_compiler_messages fma object {
10637 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10638 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10639 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10641 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10648 # Return 1 if xop instructions can be compiled.
10649 proc check_effective_target_xop { } {
10650 return [check_no_compiler_messages xop object {
10651 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10652 typedef short __v8hi __attribute__ ((__vector_size__ (16)));
10653 __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
10655 return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A,
10662 # Return 1 if lzcnt instruction can be compiled.
10663 proc check_effective_target_lzcnt { } {
10664 return [check_no_compiler_messages lzcnt object {
10665 unsigned short _lzcnt (unsigned short __X)
10667 return __builtin_clzs (__X);
10672 # Return 1 if bmi instructions can be compiled.
10673 proc check_effective_target_bmi { } {
10674 return [check_no_compiler_messages bmi object {
10675 unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y)
10677 return __builtin_ia32_bextr_u32 (__X, __Y);
10682 # Return 1 if ADX instructions can be compiled.
10683 proc check_effective_target_adx { } {
10684 return [check_no_compiler_messages adx object {
10686 _adxcarry_u32 (unsigned char __CF, unsigned int __X,
10687 unsigned int __Y, unsigned int *__P)
10689 return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P);
10694 # Return 1 if rtm instructions can be compiled.
10695 proc check_effective_target_rtm { } {
10696 return [check_no_compiler_messages rtm object {
10700 return __builtin_ia32_xend ();
10705 # Return 1 if avx512vl instructions can be compiled.
10706 proc check_effective_target_avx512vl { } {
10707 return [check_no_compiler_messages avx512vl object {
10708 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10710 mm256_and_epi64 (__v4di __X, __v4di __Y)
10713 return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1);
10718 # Return 1 if avx512cd instructions can be compiled.
10719 proc check_effective_target_avx512cd { } {
10720 return [check_no_compiler_messages avx512cd_trans object {
10721 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10723 _mm512_conflict_epi64 (__v8di __W, __v8di __A)
10725 return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
10729 } "-Wno-psabi -mavx512cd" ]
10732 # Return 1 if avx512er instructions can be compiled.
10733 proc check_effective_target_avx512er { } {
10734 return [check_no_compiler_messages avx512er_trans object {
10735 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10737 mm512_exp2a23_ps (__v16sf __X)
10739 return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4);
10741 } "-Wno-psabi -mavx512er" ]
10744 # Return 1 if sha instructions can be compiled.
10745 proc check_effective_target_sha { } {
10746 return [check_no_compiler_messages sha object {
10747 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10748 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10750 __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y)
10752 return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X,
10758 # Return 1 if avx512dq instructions can be compiled.
10759 proc check_effective_target_avx512dq { } {
10760 return [check_no_compiler_messages avx512dq object {
10761 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10763 _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B)
10765 return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A,
10773 # Return 1 if avx512bw instructions can be compiled.
10774 proc check_effective_target_avx512bw { } {
10775 return [check_no_compiler_messages avx512bw object {
10776 typedef short __v32hi __attribute__ ((__vector_size__ (64)));
10778 _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B)
10780 return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
10788 # Return 1 if -Wa,-march=+noavx512bw is supported.
10789 proc check_effective_target_assembler_march_noavx512bw {} {
10790 if { [istarget i?86*-*-*] || [istarget x86_64*-*-*] } {
10791 return [check_no_compiler_messages assembler_march_noavx512bw object {
10793 } "-mno-avx512bw -Wa,-march=+noavx512bw"]
10798 # Return 1 if avx512vp2intersect instructions can be compiled.
10799 proc check_effective_target_avx512vp2intersect { } {
10800 return [check_no_compiler_messages avx512vp2intersect object {
10801 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10802 typedef short __mmask16;
10804 _mm512_2intersect_epi32 (__v16si __A, __v16si __B, __mmask16 *__U,
10807 __builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B);
10809 } "-mavx512vp2intersect" ]
10812 # Return 1 if avx512ifma instructions can be compiled.
10813 proc check_effective_target_avx512ifma { } {
10814 return [check_no_compiler_messages avx512ifma object {
10815 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10817 _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z)
10819 return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X,
10827 # Return 1 if avx512vbmi instructions can be compiled.
10828 proc check_effective_target_avx512vbmi { } {
10829 return [check_no_compiler_messages avx512vbmi object {
10830 typedef char __v64qi __attribute__ ((__vector_size__ (64)));
10832 _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y)
10834 return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X,
10842 # Return 1 if avx512_4fmaps instructions can be compiled.
10843 proc check_effective_target_avx5124fmaps { } {
10844 return [check_no_compiler_messages avx5124fmaps object {
10845 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10846 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10849 _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C,
10850 __v16sf __D, __v16sf __E, __v4sf *__F)
10852 return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A,
10857 (const __v4sf *) __F,
10861 } "-mavx5124fmaps" ]
10864 # Return 1 if avx512_4vnniw instructions can be compiled.
10865 proc check_effective_target_avx5124vnniw { } {
10866 return [check_no_compiler_messages avx5124vnniw object {
10867 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10868 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10871 _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C,
10872 __v16si __D, __v16si __E, __v4si *__F)
10874 return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B,
10879 (const __v4si *) __F);
10881 } "-mavx5124vnniw" ]
10884 # Return 1 if avx512_vpopcntdq instructions can be compiled.
10885 proc check_effective_target_avx512vpopcntdq { } {
10886 return [check_no_compiler_messages avx512vpopcntdq object {
10887 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10890 _mm512_popcnt_epi32 (__v16si __A)
10892 return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A);
10894 } "-mavx512vpopcntdq" ]
10897 # Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled.
10898 proc check_effective_target_avx512vpopcntdqvl { } {
10899 return [check_no_compiler_messages avx512vpopcntdqvl object {
10900 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10903 _mm256_popcnt_epi32 (__v8si __A)
10905 return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A);
10907 } "-mavx512vpopcntdq -mavx512vl" ]
10910 # Return 1 if gfni instructions can be compiled.
10911 proc check_effective_target_gfni { } {
10912 return [check_no_compiler_messages gfni object {
10913 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
10916 _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C)
10918 return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A,
10925 # Return 1 if avx512vbmi2 instructions can be compiled.
10926 proc check_effective_target_avx512vbmi2 { } {
10927 return [check_no_compiler_messages avx512vbmi2 object {
10928 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
10929 typedef unsigned long long __mmask16;
10932 _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C)
10934 return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C,
10938 } "-mavx512vbmi2 -mavx512vl" ]
10941 # Return 1 if avx512vbmi2 instructions can be compiled.
10942 proc check_effective_target_avx512vnni { } {
10943 return [check_no_compiler_messages avx512vnni object {
10944 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10947 _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C)
10949 return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A,
10953 } "-mavx512vnni -mavx512f" ]
10956 # Return 1 if vaes instructions can be compiled.
10957 proc check_effective_target_avx512vaes { } {
10958 return [check_no_compiler_messages avx512vaes object {
10960 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10963 _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
10965 return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
10970 # Return 1 if amx-tile instructions can be compiled.
10971 proc check_effective_target_amx_tile { } {
10972 return [check_no_compiler_messages amx_tile object {
10976 __asm__ volatile ("tilerelease" ::);
10981 # Return 1 if amx-int8 instructions can be compiled.
10982 proc check_effective_target_amx_int8 { } {
10983 return [check_no_compiler_messages amx_int8 object {
10987 __asm__ volatile ("tdpbssd\t%%tmm1, %%tmm2, %%tmm3" ::);
10992 # Return 1 if amx-bf16 instructions can be compiled.
10993 proc check_effective_target_amx_bf16 { } {
10994 return [check_no_compiler_messages amx_bf16 object {
10998 __asm__ volatile ("tdpbf16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
11003 # Return 1 if amx-fp16 instructions can be compiled.
11004 proc check_effective_target_amx_fp16 { } {
11005 return [check_no_compiler_messages amx_fp16 object {
11009 __asm__ volatile ("tdpfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
11014 # Return 1 if vpclmulqdq instructions can be compiled.
11015 proc check_effective_target_vpclmulqdq { } {
11016 return [check_no_compiler_messages vpclmulqdq object {
11017 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
11020 _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B)
11022 return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0);
11024 } "-mvpclmulqdq -mavx512vl" ]
11027 # Return 1 if avx512_bitalg instructions can be compiled.
11028 proc check_effective_target_avx512bitalg { } {
11029 return [check_no_compiler_messages avx512bitalg object {
11030 typedef short int __v32hi __attribute__ ((__vector_size__ (64)));
11033 _mm512_popcnt_epi16 (__v32hi __A)
11035 return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
11037 } "-mavx512bitalg" ]
11040 # Return 1 if C wchar_t type is compatible with char16_t.
11042 proc check_effective_target_wchar_t_char16_t_compatible { } {
11043 return [check_no_compiler_messages wchar_t_char16_t object {
11045 __CHAR16_TYPE__ *p16 = &wc;
11046 char t[(((__CHAR16_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11050 # Return 1 if C wchar_t type is compatible with char32_t.
11052 proc check_effective_target_wchar_t_char32_t_compatible { } {
11053 return [check_no_compiler_messages wchar_t_char32_t object {
11055 __CHAR32_TYPE__ *p32 = &wc;
11056 char t[(((__CHAR32_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11060 # Return 1 if pow10 function exists.
11062 proc check_effective_target_pow10 { } {
11063 return [check_runtime pow10 {
11073 # Return 1 if frexpl function exists.
11075 proc check_effective_target_frexpl { } {
11076 return [check_runtime frexpl {
11081 x = frexpl (5.0, &y);
11088 # Return 1 if issignaling function exists.
11089 proc check_effective_target_issignaling {} {
11090 return [check_runtime issignaling {
11091 #define _GNU_SOURCE
11095 return issignaling (0.0);
11100 # Return 1 if current options generate DFP instructions, 0 otherwise.
11101 proc check_effective_target_hard_dfp {} {
11102 return [check_no_messages_and_pattern hard_dfp "!adddd3" assembly {
11103 typedef float d64 __attribute__((mode(DD)));
11105 void foo (void) { z = x + y; }
11109 # Return 1 if string.h and wchar.h headers provide C++ requires overloads
11110 # for strchr etc. functions.
11112 proc check_effective_target_correct_iso_cpp_string_wchar_protos { } {
11113 return [check_no_compiler_messages correct_iso_cpp_string_wchar_protos assembly {
11114 #include <string.h>
11116 #if !defined(__cplusplus) \
11117 || !defined(__CORRECT_ISO_CPP_STRING_H_PROTO) \
11118 || !defined(__CORRECT_ISO_CPP_WCHAR_H_PROTO)
11119 ISO C++ correct string.h and wchar.h protos not supported.
11126 # Return 1 if GNU as is used.
11128 proc check_effective_target_gas { } {
11129 global use_gas_saved
11132 if {![info exists use_gas_saved]} {
11133 # Check if the as used by gcc is GNU as.
11134 set options [list "additional_flags=-print-prog-name=as"]
11135 set gcc_as [lindex [${tool}_target_compile "" "" "none" $options] 0]
11136 # Provide /dev/null as input, otherwise gas times out reading from
11138 set status [remote_exec host "$gcc_as" "-v /dev/null"]
11139 set as_output [lindex $status 1]
11140 if { [ string first "GNU" $as_output ] >= 0 } {
11141 # Some Darwin versions have an assembler which is based on an old
11142 # version of GAS (and reports GNU assembler in its -v output) but
11143 # but doesn't support many of the modern GAS features.
11144 if { [ string first "cctools" $as_output ] >= 0 } {
11145 set use_gas_saved 0
11147 set use_gas_saved 1
11150 set use_gas_saved 0
11153 return $use_gas_saved
11156 # Return 1 if GNU ld is used.
11158 proc check_effective_target_gld { } {
11159 global use_gld_saved
11162 if {![info exists use_gld_saved]} {
11163 # Check if the ld used by gcc is GNU ld.
11164 set options [list "additional_flags=-print-prog-name=ld"]
11165 set gcc_ld [lindex [${tool}_target_compile "" "" "none" $options] 0]
11166 set status [remote_exec host "$gcc_ld" "--version"]
11167 set ld_output [lindex $status 1]
11168 if { [ string first "GNU" $ld_output ] >= 0 } {
11169 set use_gld_saved 1
11171 set use_gld_saved 0
11174 return $use_gld_saved
11177 # Return 1 if the compiler has been configure with link-time optimization
11180 proc check_effective_target_lto { } {
11181 if { [istarget *-*-vxworks*] } {
11182 # No LTO on VxWorks, with kernel modules
11183 # built with partial links
11186 if { [istarget nvptx-*-*]
11187 || [istarget amdgcn-*-*] } {
11190 return [check_no_compiler_messages lto object {
11191 void foo (void) { }
11195 # Return 1 if the compiler and linker support incremental link-time
11198 proc check_effective_target_lto_incremental { } {
11199 if ![check_effective_target_lto] {
11202 return [check_no_compiler_messages lto_incremental executable {
11203 int main () { return 0; }
11204 } "-flto -r -nostdlib"]
11207 # Return 1 if the compiler has been configured with analyzer support.
11209 proc check_effective_target_analyzer { } {
11210 return [check_no_compiler_messages analyzer object {
11211 void foo (void) { }
11215 # Return 1 if -mx32 -maddress-mode=short can compile, 0 otherwise.
11217 proc check_effective_target_maybe_x32 { } {
11218 return [check_no_compiler_messages maybe_x32 object {
11220 } "-mx32 -maddress-mode=short"]
11223 # Return 1 if this target supports the -fsplit-stack option, 0
11226 proc check_effective_target_split_stack {} {
11227 return [check_no_compiler_messages split_stack object {
11228 void foo (void) { }
11232 # Return 1 if this target supports the -masm=intel option, 0
11235 proc check_effective_target_masm_intel {} {
11236 return [check_no_compiler_messages masm_intel object {
11237 extern void abort (void);
11241 # Return 1 if the language for the compiler under test is C.
11243 proc check_effective_target_c { } {
11245 if [string match $tool "gcc"] {
11251 # Return 1 if the language for the compiler under test is C++.
11253 proc check_effective_target_c++ { } {
11255 if { [string match $tool "g++"] || [string match $tool "libstdc++"] } {
11261 set cxx_default "c++17"
11262 # Check whether the current active language standard supports the features
11263 # of C++11/C++14 by checking for the presence of one of the -std flags.
11264 # This assumes that the default for the compiler is $cxx_default, and that
11265 # there will never be multiple -std= arguments on the command line.
11266 proc check_effective_target_c++11_only { } {
11268 if ![check_effective_target_c++] {
11271 if [check-flags { { } { } { -std=c++0x -std=gnu++0x -std=c++11 -std=gnu++11 } }] {
11274 if { $cxx_default == "c++11" && [check-flags { { } { } { } { -std=* } }] } {
11279 proc check_effective_target_c++11 { } {
11280 if [check_effective_target_c++11_only] {
11283 return [check_effective_target_c++14]
11285 proc check_effective_target_c++11_down { } {
11286 if ![check_effective_target_c++] {
11289 return [expr ![check_effective_target_c++14] ]
11292 proc check_effective_target_c++14_only { } {
11294 if ![check_effective_target_c++] {
11297 if [check-flags { { } { } { -std=c++14 -std=gnu++14 -std=c++14 -std=gnu++14 } }] {
11300 if { $cxx_default == "c++14" && [check-flags { { } { } { } { -std=* } }] } {
11306 proc check_effective_target_c++14 { } {
11307 if [check_effective_target_c++14_only] {
11310 return [check_effective_target_c++17]
11312 proc check_effective_target_c++14_down { } {
11313 if ![check_effective_target_c++] {
11316 return [expr ![check_effective_target_c++17] ]
11319 proc check_effective_target_c++98_only { } {
11321 if ![check_effective_target_c++] {
11324 if [check-flags { { } { } { -std=c++98 -std=gnu++98 -std=c++03 -std=gnu++03 } }] {
11327 if { $cxx_default == "c++98" && [check-flags { { } { } { } { -std=* } }] } {
11333 proc check_effective_target_c++17_only { } {
11335 if ![check_effective_target_c++] {
11338 if [check-flags { { } { } { -std=c++17 -std=gnu++17 -std=c++1z -std=gnu++1z } }] {
11341 if { $cxx_default == "c++17" && [check-flags { { } { } { } { -std=* } }] } {
11347 proc check_effective_target_c++17 { } {
11348 if [check_effective_target_c++17_only] {
11351 return [check_effective_target_c++2a]
11353 proc check_effective_target_c++17_down { } {
11354 if ![check_effective_target_c++] {
11357 return [expr ![check_effective_target_c++2a] ]
11360 proc check_effective_target_c++2a_only { } {
11362 if ![check_effective_target_c++] {
11365 if [check-flags { { } { } { -std=c++2a -std=gnu++2a -std=c++20 -std=gnu++20 } }] {
11368 if { $cxx_default == "c++20" && [check-flags { { } { } { } { -std=* } }] } {
11373 proc check_effective_target_c++2a { } {
11374 if [check_effective_target_c++2a_only] {
11377 return [check_effective_target_c++23]
11380 proc check_effective_target_c++20_only { } {
11381 return [check_effective_target_c++2a_only]
11384 proc check_effective_target_c++20 { } {
11385 return [check_effective_target_c++2a]
11387 proc check_effective_target_c++20_down { } {
11388 if ![check_effective_target_c++] {
11391 return [expr ![check_effective_target_c++23] ]
11394 proc check_effective_target_c++23_only { } {
11396 if ![check_effective_target_c++] {
11399 if [check-flags { { } { } { -std=c++23 -std=gnu++23 -std=c++2b -std=gnu++2b } }] {
11402 if { $cxx_default == "c++23" && [check-flags { { } { } { } { -std=* } }] } {
11407 proc check_effective_target_c++23 { } {
11408 if [check_effective_target_c++23_only] {
11411 return [check_effective_target_c++26]
11414 proc check_effective_target_c++23_down { } {
11415 if ![check_effective_target_c++] {
11418 return [expr ![check_effective_target_c++26] ]
11421 proc check_effective_target_c++26_only { } {
11423 if ![check_effective_target_c++] {
11426 if [check-flags { { } { } { -std=c++26 -std=gnu++26 -std=c++2c -std=gnu++2c } }] {
11429 if { $cxx_default == "c++26" && [check-flags { { } { } { } { -std=* } }] } {
11435 proc check_effective_target_c++26 { } {
11436 return [check_effective_target_c++26_only]
11439 # Check for C++ Concepts support, i.e. -fconcepts flag.
11440 proc check_effective_target_concepts { } {
11441 if [check_effective_target_c++2a] {
11444 return [check-flags { "" { } { -fconcepts } }]
11447 proc check_effective_target_implicit_constexpr { } {
11448 return [check-flags { "" { } { -fimplicit-constexpr } }]
11451 # Return 1 if expensive testcases should be run.
11453 proc check_effective_target_run_expensive_tests { } {
11454 if { [getenv GCC_TEST_RUN_EXPENSIVE] != "" } {
11460 # Returns 1 if "mempcpy" is available on the target system.
11462 proc check_effective_target_mempcpy {} {
11463 if { [istarget *-*-vxworks*] } {
11464 # VxWorks doesn't have mempcpy but our way to test fails
11465 # to detect as we're doing partial links for kernel modules.
11468 return [check_function_available "mempcpy"]
11471 # Returns 1 if "stpcpy" is available on the target system.
11473 proc check_effective_target_stpcpy {} {
11474 return [check_function_available "stpcpy"]
11477 # Returns 1 if "sigsetjmp" is available on the target system.
11478 # Also check if "__sigsetjmp" is defined since that's what glibc
11481 proc check_effective_target_sigsetjmp {} {
11482 if { [check_function_available "sigsetjmp"]
11483 || [check_function_available "__sigsetjmp"] } {
11489 # Check whether the vectorizer tests are supported by the target and
11490 # append additional target-dependent compile flags to DEFAULT_VECTCFLAGS.
11491 # If a port wants to execute the tests more than once it should append
11492 # the supported target to EFFECTIVE_TARGETS instead, and the compile flags
11493 # will be added by a call to add_options_for_<target>.
11494 # Set dg-do-what-default to either compile or run, depending on target
11495 # capabilities. Do not set this if the supported target is appended to
11496 # EFFECTIVE_TARGETS. Flags and this variable will be set by et-dg-runtest
11497 # automatically. Return the number of effective targets if vectorizer tests
11498 # are supported, 0 otherwise.
11500 proc check_vect_support_and_set_flags { } {
11501 global DEFAULT_VECTCFLAGS
11502 global dg-do-what-default
11503 global EFFECTIVE_TARGETS
11505 if [istarget powerpc-*paired*] {
11506 lappend DEFAULT_VECTCFLAGS "-mpaired"
11507 if [check_750cl_hw_available] {
11508 set dg-do-what-default run
11510 set dg-do-what-default compile
11512 } elseif [istarget powerpc*-*-*] {
11513 # Skip targets not supporting -maltivec.
11514 if ![is-effective-target powerpc_altivec_ok] {
11518 lappend DEFAULT_VECTCFLAGS "-maltivec"
11519 if [check_p9vector_hw_available] {
11520 lappend DEFAULT_VECTCFLAGS "-mpower9-vector"
11521 } elseif [check_p8vector_hw_available] {
11522 lappend DEFAULT_VECTCFLAGS "-mpower8-vector"
11523 } elseif [check_vsx_hw_available] {
11524 lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
11527 if [check_vmx_hw_available] {
11528 set dg-do-what-default run
11530 if [is-effective-target ilp32] {
11531 # Specify a cpu that supports VMX for compile-only tests.
11532 lappend DEFAULT_VECTCFLAGS "-mcpu=970"
11534 set dg-do-what-default compile
11536 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
11537 lappend DEFAULT_VECTCFLAGS "-msse2"
11538 if { [check_effective_target_sse2_runtime] } {
11539 set dg-do-what-default run
11541 set dg-do-what-default compile
11543 } elseif { [istarget mips*-*-*]
11544 && [check_effective_target_nomips16] } {
11545 if { [check_effective_target_mpaired_single "-mpaired-single"] } {
11546 lappend EFFECTIVE_TARGETS mpaired_single
11548 if { [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
11549 lappend EFFECTIVE_TARGETS mips_loongson_mmi
11551 if { [check_effective_target_mips_msa "-mmsa"] } {
11552 lappend EFFECTIVE_TARGETS mips_msa
11554 return [llength $EFFECTIVE_TARGETS]
11555 } elseif [istarget sparc*-*-*] {
11556 lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
11557 if [check_effective_target_ultrasparc_hw] {
11558 set dg-do-what-default run
11560 set dg-do-what-default compile
11562 } elseif [istarget alpha*-*-*] {
11563 # Alpha's vectorization capabilities are extremely limited.
11564 # It's more effort than its worth disabling all of the tests
11565 # that it cannot pass. But if you actually want to see what
11566 # does work, command out the return.
11569 lappend DEFAULT_VECTCFLAGS "-mmax"
11570 if [check_alpha_max_hw_available] {
11571 set dg-do-what-default run
11573 set dg-do-what-default compile
11575 } elseif [istarget ia64-*-*] {
11576 set dg-do-what-default run
11577 } elseif [is-effective-target arm_neon_ok] {
11578 eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
11579 # NEON does not support denormals, so is not used for vectorization by
11580 # default to avoid loss of precision. We must pass -ffast-math to test
11581 # vectorization of float operations.
11582 lappend DEFAULT_VECTCFLAGS "-ffast-math"
11583 if [is-effective-target arm_neon_hw] {
11584 set dg-do-what-default run
11586 set dg-do-what-default compile
11588 } elseif [istarget aarch64*-*-*] {
11589 set dg-do-what-default run
11590 } elseif [istarget s390*-*-*] {
11591 # The S/390 backend set a default of 2 for that value.
11592 # Override it to have the same situation as with other
11594 lappend DEFAULT_VECTCFLAGS "--param" "min-vect-loop-bound=1"
11595 lappend DEFAULT_VECTCFLAGS "--param" "max-unrolled-insns=200"
11596 lappend DEFAULT_VECTCFLAGS "--param" "max-unroll-times=8"
11597 lappend DEFAULT_VECTCFLAGS "--param" "max-completely-peeled-insns=200"
11598 lappend DEFAULT_VECTCFLAGS "--param" "max-completely-peel-times=16"
11599 if [check_effective_target_s390_vxe2] {
11600 lappend DEFAULT_VECTCFLAGS "-march=z15" "-mzarch"
11601 set dg-do-what-default run
11602 } elseif [check_effective_target_s390_vxe] {
11603 lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
11604 set dg-do-what-default run
11605 } elseif [check_effective_target_s390_vx] {
11606 lappend DEFAULT_VECTCFLAGS "-march=z13" "-mzarch"
11607 set dg-do-what-default run
11609 lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
11610 set dg-do-what-default compile
11612 } elseif [istarget amdgcn-*-*] {
11613 set dg-do-what-default run
11614 } elseif [istarget riscv*-*-*] {
11615 if [check_effective_target_riscv_v] {
11616 lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
11617 set dg-do-what-default run
11619 foreach item [add_options_for_riscv_v ""] {
11620 lappend DEFAULT_VECTCFLAGS $item
11622 lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
11623 set dg-do-what-default compile
11625 } elseif [istarget loongarch*-*-*] {
11626 lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlasx"
11627 if [check_effective_target_loongarch_asx_hw] {
11628 set dg-do-what-default run
11630 set dg-do-what-default compile
11639 # Return 1 if the target does *not* require strict alignment.
11641 proc check_effective_target_non_strict_align {} {
11643 # On ARM, the default is to use STRICT_ALIGNMENT, but there
11644 # are interfaces defined for misaligned access and thus
11645 # depending on the architecture levels unaligned access is
11647 if [istarget "arm*-*-*"] {
11648 return [check_effective_target_arm_unaligned]
11651 return [check_no_compiler_messages non_strict_align assembly {
11653 typedef char __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))) c;
11655 void foo(void) { z = (c *) y; }
11659 # Return 1 if the target supports -mstrict-align (and -mno-strict-align).
11661 proc check_effective_target_opt_mstrict_align {} {
11662 return [check_no_compiler_messages opt_mstrict_align assembly {
11664 } "-mstrict-align -mno-strict-align"]
11667 # Return 1 if the target has <ucontext.h>.
11669 proc check_effective_target_ucontext_h { } {
11670 return [check_no_compiler_messages ucontext_h assembly {
11671 #include <ucontext.h>
11675 proc check_effective_target_aarch64_tiny { } {
11676 if { [istarget aarch64*-*-*] } {
11677 return [check_no_compiler_messages aarch64_tiny object {
11678 #ifdef __AARCH64_CMODEL_TINY__
11681 #error target not AArch64 tiny code model
11689 # Create functions to check that the AArch64 assembler supports the
11690 # various architecture extensions via the .arch_extension pseudo-op.
11692 foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
11693 "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64"
11694 "sme" "sme-i16i64" "sme2" } {
11695 eval [string map [list FUNC $aarch64_ext] {
11696 proc check_effective_target_aarch64_asm_FUNC_ok { } {
11697 if { [istarget aarch64*-*-*] } {
11698 return [check_no_compiler_messages aarch64_FUNC_assembler object {
11699 __asm__ (".arch_extension FUNC");
11700 } "-march=armv8-a+FUNC"]
11708 proc check_effective_target_aarch64_small { } {
11709 if { [istarget aarch64*-*-*] } {
11710 return [check_no_compiler_messages aarch64_small object {
11711 #ifdef __AARCH64_CMODEL_SMALL__
11714 #error target not AArch64 small code model
11722 proc check_effective_target_aarch64_large { } {
11723 if { [istarget aarch64*-*-*] } {
11724 return [check_no_compiler_messages aarch64_large object {
11725 #ifdef __AARCH64_CMODEL_LARGE__
11728 #error target not AArch64 large code model
11736 # Return 1 if the assembler accepts the aarch64 .variant_pcs directive.
11738 proc check_effective_target_aarch64_variant_pcs { } {
11739 if { [istarget aarch64*-*-*] } {
11740 return [check_no_compiler_messages aarch64_variant_pcs object {
11741 __asm__ (".variant_pcs foo");
11748 # Return 1 if this is a reduced AVR Tiny core. Such cores have different
11749 # register set, instruction set, addressing capabilities and ABI.
11751 proc check_effective_target_avr_tiny { } {
11752 if { [istarget avr*-*-*] } {
11753 return [check_no_compiler_messages avr_tiny object {
11754 #ifdef __AVR_TINY__
11757 #error target not a reduced AVR Tiny core
11765 # Return 1 if <fenv.h> is available.
11767 proc check_effective_target_fenv {} {
11768 return [check_no_compiler_messages fenv object {
11770 } [add_options_for_ieee "-std=gnu99"]]
11773 # Return 1 if <fenv.h> is available with all the standard IEEE
11774 # exceptions and floating-point exceptions are raised by arithmetic
11775 # operations. (If the target requires special options for "inexact"
11776 # exceptions, those need to be specified in the testcases.)
11778 proc check_effective_target_fenv_exceptions {} {
11779 return [check_runtime fenv_exceptions {
11781 #include <stdlib.h>
11782 #ifndef FE_DIVBYZERO
11783 # error Missing FE_DIVBYZERO
11786 # error Missing FE_INEXACT
11789 # error Missing FE_INVALID
11791 #ifndef FE_OVERFLOW
11792 # error Missing FE_OVERFLOW
11794 #ifndef FE_UNDERFLOW
11795 # error Missing FE_UNDERFLOW
11797 volatile float a = 0.0f, r;
11802 if (fetestexcept (FE_INVALID))
11807 } [add_options_for_ieee "-std=gnu99"]]
11810 # Return 1 if <fenv.h> is available with all the standard IEEE
11811 # exceptions and floating-point exceptions are raised by arithmetic
11812 # operations for decimal floating point. (If the target requires
11813 # special options for "inexact" exceptions, those need to be specified
11814 # in the testcases.)
11816 proc check_effective_target_fenv_exceptions_dfp {} {
11817 return [check_runtime fenv_exceptions_dfp {
11819 #include <stdlib.h>
11820 #ifndef FE_DIVBYZERO
11821 # error Missing FE_DIVBYZERO
11824 # error Missing FE_INEXACT
11827 # error Missing FE_INVALID
11829 #ifndef FE_OVERFLOW
11830 # error Missing FE_OVERFLOW
11832 #ifndef FE_UNDERFLOW
11833 # error Missing FE_UNDERFLOW
11835 volatile _Decimal64 a = 0.0DD, r;
11840 if (fetestexcept (FE_INVALID))
11845 } [add_options_for_ieee "-std=gnu99"]]
11848 # Return 1 if <fenv.h> is available with all the standard IEEE
11849 # exceptions and floating-point exceptions are raised by arithmetic
11850 # operations. (If the target requires special options for "inexact"
11851 # exceptions, those need to be specified in the testcases.)
11853 proc check_effective_target_fenv_exceptions_double {} {
11854 return [check_runtime fenv_exceptions_double {
11856 #include <stdlib.h>
11857 #ifndef FE_DIVBYZERO
11858 # error Missing FE_DIVBYZERO
11861 # error Missing FE_INEXACT
11864 # error Missing FE_INVALID
11866 #ifndef FE_OVERFLOW
11867 # error Missing FE_OVERFLOW
11869 #ifndef FE_UNDERFLOW
11870 # error Missing FE_UNDERFLOW
11872 volatile double a = 0.0f, r;
11877 if (fetestexcept (FE_INVALID))
11882 } [add_options_for_ieee "-std=gnu99"]]
11885 # Return 1 if <fenv.h> is available with all the standard IEEE
11886 # exceptions and floating-point exceptions are raised by arithmetic
11887 # operations. (If the target requires special options for "inexact"
11888 # exceptions, those need to be specified in the testcases.)
11890 proc check_effective_target_fenv_exceptions_long_double {} {
11891 return [check_runtime fenv_exceptions_long_double {
11893 #include <stdlib.h>
11894 #ifndef FE_DIVBYZERO
11895 # error Missing FE_DIVBYZERO
11898 # error Missing FE_INEXACT
11901 # error Missing FE_INVALID
11903 #ifndef FE_OVERFLOW
11904 # error Missing FE_OVERFLOW
11906 #ifndef FE_UNDERFLOW
11907 # error Missing FE_UNDERFLOW
11909 volatile long double a = 0.0f, r;
11914 if (fetestexcept (FE_INVALID))
11919 } [add_options_for_ieee "-std=gnu99"]]
11922 # Return 1 if -fexceptions is supported.
11924 proc check_effective_target_exceptions {} {
11925 if { [istarget amdgcn*-*-*] } {
11931 # Used to check if the testing configuration supports exceptions.
11932 # Returns 0 if exceptions are unsupported or disabled (e.g. by passing
11933 # -fno-exceptions). Returns 1 if exceptions are enabled.
11934 proc check_effective_target_exceptions_enabled {} {
11935 return [check_cached_effective_target exceptions_enabled {
11936 if { [check_effective_target_exceptions] } {
11937 return [check_no_compiler_messages exceptions_enabled assembly {
11945 # If exceptions aren't supported, then they're not enabled.
11951 proc check_effective_target_tiny {} {
11952 return [check_cached_effective_target tiny {
11953 if { [istarget aarch64*-*-*]
11954 && [check_effective_target_aarch64_tiny] } {
11957 if { [istarget avr-*-*]
11958 && [check_effective_target_avr_tiny] } {
11961 # PRU Program Counter is 16-bits, and trampolines are not supported.
11962 # Hence directly declare as a tiny target.
11963 if [istarget pru-*-*] {
11970 # Return 1 if the target supports -mbranch-cost=N option.
11972 proc check_effective_target_branch_cost {} {
11973 if { [ istarget arm*-*-*]
11974 || [istarget avr*-*-*]
11975 || [istarget csky*-*-*]
11976 || [istarget epiphany*-*-*]
11977 || [istarget frv*-*-*]
11978 || [istarget i?86-*-*] || [istarget x86_64-*-*]
11979 || [istarget loongarch*-*-*]
11980 || [istarget mips*-*-*]
11981 || [istarget s390*-*-*]
11982 || [istarget riscv*-*-*]
11983 || [istarget sh*-*-*] } {
11989 # Record that dg-final test TEST requires convential compilation.
11991 proc set_required_options_for { test } {
11992 if { [info proc $test] == "" } {
11993 perror "$test does not exist"
11996 proc ${test}_required_options {} {
11997 global gcc_set_required_options
11998 upvar 1 extra_tool_flags extra_tool_flags
11999 if {[regexp -- "^scan-assembler" [info level 0]]
12000 && ![string match "*-fident*" $extra_tool_flags]} {
12001 # Do not let .ident confuse assembler scan tests
12002 return [list $gcc_set_required_options "-fno-ident"]
12004 return $gcc_set_required_options
12008 # Record that dg-final test scan-ltrans-tree-dump* requires -flto-partition=one
12009 # in order to force a single partition, allowing scan-ltrans-tree-dump* to scan
12010 # a dump file *.exe.ltrans0.*.
12012 proc scan-ltrans-tree-dump_required_options {} {
12013 return "-flto-partition=one"
12015 proc scan-ltrans-tree-dump-times_required_options {} {
12016 return "-flto-partition=one"
12018 proc scan-ltrans-tree-dump-not_required_options {} {
12019 return "-flto-partition=one"
12021 proc scan-ltrans-tree-dump-dem_required_options {} {
12022 return "-flto-partition=one"
12024 proc scan-ltrans-tree-dump-dem-not_required_options {} {
12025 return "-flto-partition=one"
12028 # Return 1 if the x86-64 target supports PIE with copy reloc, 0
12029 # otherwise. Cache the result.
12031 proc check_effective_target_pie_copyreloc { } {
12033 global GCC_UNDER_TEST
12035 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12039 # Need auto-host.h to check linker support.
12040 if { ![file exists ../../auto-host.h ] } {
12044 return [check_cached_effective_target pie_copyreloc {
12045 # Set up and compile to see if linker supports PIE with copy
12046 # reloc. Include the current process ID in the file names to
12047 # prevent conflicts with invocations for multiple testsuites.
12052 set f [open $src "w"]
12053 puts $f "#include \"../../auto-host.h\""
12054 puts $f "#if HAVE_LD_PIE_COPYRELOC == 0"
12055 puts $f "# error Linker does not support PIE with copy reloc."
12059 verbose "check_effective_target_pie_copyreloc compiling testfile $src" 2
12060 set lines [${tool}_target_compile $src $obj object ""]
12065 if [string match "" $lines] then {
12066 verbose "check_effective_target_pie_copyreloc testfile compilation passed" 2
12069 verbose "check_effective_target_pie_copyreloc testfile compilation failed" 2
12075 # Return 1 if the x86 target supports R_386_GOT32X relocation, 0
12076 # otherwise. Cache the result.
12078 proc check_effective_target_got32x_reloc { } {
12080 global GCC_UNDER_TEST
12082 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12086 # Need auto-host.h to check linker support.
12087 if { ![file exists ../../auto-host.h ] } {
12091 return [check_cached_effective_target got32x_reloc {
12092 # Include the current process ID in the file names to prevent
12093 # conflicts with invocations for multiple testsuites.
12095 set src got32x[pid].c
12096 set obj got32x[pid].o
12098 set f [open $src "w"]
12099 puts $f "#include \"../../auto-host.h\""
12100 puts $f "#if HAVE_AS_IX86_GOT32X == 0"
12101 puts $f "# error Assembler does not support R_386_GOT32X."
12105 verbose "check_effective_target_got32x_reloc compiling testfile $src" 2
12106 set lines [${tool}_target_compile $src $obj object ""]
12111 if [string match "" $lines] then {
12112 verbose "check_effective_target_got32x_reloc testfile compilation passed" 2
12115 verbose "check_effective_target_got32x_reloc testfile compilation failed" 2
12120 return $got32x_reloc_available_saved
12123 # Return 1 if the x86 target supports calling ___tls_get_addr via GOT,
12124 # 0 otherwise. Cache the result.
12126 proc check_effective_target_tls_get_addr_via_got { } {
12128 global GCC_UNDER_TEST
12130 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12134 # Need auto-host.h to check linker support.
12135 if { ![file exists ../../auto-host.h ] } {
12139 return [check_cached_effective_target tls_get_addr_via_got {
12140 # Include the current process ID in the file names to prevent
12141 # conflicts with invocations for multiple testsuites.
12143 set src tls_get_addr_via_got[pid].c
12144 set obj tls_get_addr_via_got[pid].o
12146 set f [open $src "w"]
12147 puts $f "#include \"../../auto-host.h\""
12148 puts $f "#if HAVE_AS_IX86_TLS_GET_ADDR_GOT == 0"
12149 puts $f "# error Assembler/linker do not support calling ___tls_get_addr via GOT."
12153 verbose "check_effective_target_tls_get_addr_via_got compiling testfile $src" 2
12154 set lines [${tool}_target_compile $src $obj object ""]
12159 if [string match "" $lines] then {
12160 verbose "check_effective_target_tls_get_addr_via_got testfile compilation passed" 2
12163 verbose "check_effective_target_tls_get_addr_via_got testfile compilation failed" 2
12169 # Return 1 if the target uses comdat groups.
12171 proc check_effective_target_comdat_group {} {
12172 return [check_no_messages_and_pattern comdat_group "\.section\[^\n\r]*,comdat|\.group\[^\n\r]*,#comdat" assembly {
12174 inline int foo () { return 1; }
12175 int (*fn) () = foo;
12179 # Return 1 if target supports __builtin_eh_return
12180 proc check_effective_target_builtin_eh_return { } {
12181 return [check_no_compiler_messages builtin_eh_return object {
12182 void test (long l, void *p)
12184 __builtin_eh_return (l, p);
12189 # Return 1 if the target supports max reduction for vectors.
12191 proc check_effective_target_vect_max_reduc { } {
12192 if { [istarget aarch64*-*-*] || [is-effective-target arm_neon]
12193 || [check_effective_target_riscv_v] } {
12199 # Return 1 if the compiler has been configured with nvptx offloading.
12201 proc check_effective_target_offload_nvptx { } {
12202 return [check_no_compiler_messages offload_nvptx assembly {
12203 int main () {return 0;}
12204 } "-foffload=nvptx-none" ]
12207 # Return 1 if the compiler has been configured with gcn offloading.
12209 proc check_effective_target_offload_gcn { } {
12210 return [check_no_compiler_messages offload_gcn assembly {
12211 int main () {return 0;}
12212 } "-foffload=amdgcn-amdhsa" ]
12215 # Return 1 if the target support -fprofile-update=atomic
12216 proc check_effective_target_profile_update_atomic {} {
12217 return [check_no_compiler_messages profile_update_atomic assembly {
12218 int main (void) { return 0; }
12219 } "-fprofile-update=atomic -fprofile-generate"]
12222 # Return 1 if vector (va - vector add) instructions are understood by
12223 # the assembler and can be executed. This also covers checking for
12224 # the VX kernel feature. A kernel without that feature does not
12225 # enable the vector facility and the following check will die with a
12227 proc check_effective_target_s390_vx { } {
12228 if ![istarget s390*-*-*] then {
12232 return [check_runtime s390_check_vx {
12235 asm ("va %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12238 } "-march=z13 -mzarch" ]
12241 # Same as above but for the z14 vector enhancement facility. Test
12242 # is performed with the vector nand instruction.
12243 proc check_effective_target_s390_vxe { } {
12244 if ![istarget s390*-*-*] then {
12248 return [check_runtime s390_check_vxe {
12251 asm ("vnn %%v24, %%v26, %%v28" : : : "v24", "v26", "v28");
12254 } "-march=z14 -mzarch" ]
12257 # Same as above but for the arch13 vector enhancement facility. Test
12258 # is performed with the vector shift left double by bit instruction.
12259 proc check_effective_target_s390_vxe2 { } {
12260 if ![istarget s390*-*-*] then {
12264 return [check_runtime s390_check_vxe2 {
12267 asm ("vsld %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12270 } "-march=arch13 -mzarch" ]
12273 # Same as above but for the arch14 NNPA facility.
12274 proc check_effective_target_s390_nnpa { } {
12275 if ![istarget s390*-*-*] then {
12279 return [check_runtime s390_check_nnpa {
12282 asm ("vzero %%v24\n\t"
12283 "vcrnf %%v24,%%v24,%%v24,0,2" : : : "v24");
12286 } "-march=arch14 -mzarch" ]
12289 #For versions of ARM architectures that have hardware div insn,
12290 #disable the divmod transform
12292 proc check_effective_target_arm_divmod_simode { } {
12293 return [check_no_compiler_messages arm_divmod assembly {
12294 #ifdef __ARM_ARCH_EXT_IDIV__
12295 #error has div insn
12301 # Return 1 if target supports divmod hardware insn or divmod libcall.
12303 proc check_effective_target_divmod { } {
12304 #TODO: Add checks for all targets that have either hardware divmod insn
12305 # or define libfunc for divmod.
12306 if { [istarget arm*-*-*]
12307 || [istarget i?86-*-*] || [istarget x86_64-*-*]
12308 || [istarget amdgcn-*-*] } {
12314 # Return 1 if target supports divmod for SImode. The reason for
12315 # separating this from check_effective_target_divmod is that
12316 # some versions of ARM architecture define div instruction
12317 # only for simode, and for these archs, we do not want to enable
12318 # divmod transform for simode.
12320 proc check_effective_target_divmod_simode { } {
12321 if { [istarget arm*-*-*] } {
12322 return [check_effective_target_arm_divmod_simode]
12325 return [check_effective_target_divmod]
12328 # Return 1 if store merging optimization is applicable for target.
12329 # Store merging is not profitable for targets like the avr which
12330 # can load/store only one byte at a time. Use int size as a proxy
12331 # for the number of bytes the target can write, and skip for targets
12332 # with a smallish (< 32) size.
12334 proc check_effective_target_store_merge { } {
12335 if { [is-effective-target non_strict_align ] && [is-effective-target int32plus] } {
12342 # Return 1 if we're able to assemble rdrand
12344 proc check_effective_target_rdrand { } {
12345 return [check_no_compiler_messages_nocache rdrand object {
12350 __builtin_ia32_rdrand32_step(&val);
12356 # Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl,
12357 # stc, stcl, mcr and mrc.
12358 proc check_effective_target_arm_coproc1_ok_nocache { } {
12359 if { ![istarget arm*-*-*] } {
12362 return [check_no_compiler_messages_nocache arm_coproc1_ok assembly {
12363 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 4
12366 #include <arm_acle.h>
12370 proc check_effective_target_arm_coproc1_ok { } {
12371 return [check_cached_effective_target arm_coproc1_ok \
12372 check_effective_target_arm_coproc1_ok_nocache]
12375 # Return 1 if the target supports all coprocessor instructions checked by
12376 # check_effective_target_arm_coproc1_ok in addition to the following: cdp2,
12377 # ldc2, ldc2l, stc2, stc2l, mcr2 and mrc2.
12378 proc check_effective_target_arm_coproc2_ok_nocache { } {
12379 if { ![check_effective_target_arm_coproc1_ok] } {
12382 return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
12383 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5
12386 #include <arm_acle.h>
12390 proc check_effective_target_arm_coproc2_ok { } {
12391 return [check_cached_effective_target arm_coproc2_ok \
12392 check_effective_target_arm_coproc2_ok_nocache]
12395 # Return 1 if the target supports all coprocessor instructions checked by
12396 # check_effective_target_arm_coproc2_ok in addition the following: mcrr and
12398 proc check_effective_target_arm_coproc3_ok_nocache { } {
12399 if { ![check_effective_target_arm_coproc2_ok] } {
12402 return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
12403 #if (__thumb__ && !__thumb2__) \
12404 || (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__))
12407 #include <arm_acle.h>
12411 proc check_effective_target_arm_coproc3_ok { } {
12412 return [check_cached_effective_target arm_coproc3_ok \
12413 check_effective_target_arm_coproc3_ok_nocache]
12416 # Return 1 if the target supports all coprocessor instructions checked by
12417 # check_effective_target_arm_coproc3_ok in addition the following: mcrr2 and
12419 proc check_effective_target_arm_coproc4_ok_nocache { } {
12420 if { ![check_effective_target_arm_coproc3_ok] } {
12423 return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
12424 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6
12427 #include <arm_acle.h>
12431 proc check_effective_target_arm_coproc4_ok { } {
12432 return [check_cached_effective_target arm_coproc4_ok \
12433 check_effective_target_arm_coproc4_ok_nocache]
12436 # Return 1 if the target supports the auto_inc_dec optimization pass.
12437 proc check_effective_target_autoincdec { } {
12438 if { ![check_no_compiler_messages auto_incdec assembly { void f () { }
12439 } "-O2 -fdump-rtl-auto_inc_dec" ] } {
12443 set dumpfile [glob -nocomplain "auto_incdec[pid].c.\[0-9\]\[0-9\]\[0-9\]r.auto_inc_dec"]
12444 if { [file exists $dumpfile ] } {
12445 file delete $dumpfile
12451 # Return 1 if the target has support for stack probing designed
12452 # to avoid stack-clash style attacks.
12454 # This is used to restrict the stack-clash mitigation tests to
12455 # just those targets that have been explicitly supported.
12457 # In addition to the prologue work on those targets, each target's
12458 # properties should be described in the functions below so that
12459 # tests do not become a mess of unreadable target conditions.
12461 proc check_effective_target_supports_stack_clash_protection { } {
12463 if { [istarget x86_64-*-*] || [istarget i?86-*-*]
12464 || [istarget powerpc*-*-*] || [istarget rs6000*-*-*]
12465 || [istarget aarch64*-**] || [istarget s390*-*-*]
12466 || [istarget loongarch64*-**] } {
12472 # Return 1 if the target creates a frame pointer for non-leaf functions
12473 # Note we ignore cases where we apply tail call optimization here.
12474 proc check_effective_target_frame_pointer_for_non_leaf { } {
12475 # Solaris/x86 defaults to -fno-omit-frame-pointer.
12476 if { [istarget i?86-*-solaris*] || [istarget x86_64-*-solaris*] } {
12483 # Return 1 if the target can perform tail-call optimizations of the
12484 # most trivial type.
12485 proc check_effective_target_tail_call { } {
12486 return [check_no_messages_and_pattern tail_call ",SIBCALL" rtl-expand {
12487 __attribute__((__noipa__)) void foo (void) { }
12488 __attribute__((__noipa__)) void bar (void) { foo(); }
12489 } {-O2 -fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed dump.
12492 # Return 1 if the target's calling sequence or its ABI
12493 # create implicit stack probes at or prior to function entry.
12494 proc check_effective_target_caller_implicit_probes { } {
12496 # On x86/x86_64 the call instruction itself pushes the return
12497 # address onto the stack. That is an implicit probe of *sp.
12498 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12502 # On PPC, the ABI mandates that the address of the outer
12503 # frame be stored at *sp. Thus each allocation of stack
12504 # space is itself an implicit probe of *sp.
12505 if { [istarget powerpc*-*-*] || [istarget rs6000*-*-*] } {
12509 # s390's ABI has a register save area allocated by the
12510 # caller for use by the callee. The mere existence does
12511 # not constitute a probe by the caller, but when the slots
12512 # used by the callee those stores are implicit probes.
12513 if { [istarget s390*-*-*] } {
12517 # Not strictly true on aarch64, but we have agreed that we will
12518 # consider any function that pushes SP more than 3kbytes into
12519 # the guard page as broken. This essentially means that we can
12520 # consider the aarch64 as having a caller implicit probe at
12522 if { [istarget aarch64*-*-*] } {
12526 if { [istarget loongarch64*-*-*] } {
12533 # Targets that potentially realign the stack pointer often cause residual
12534 # stack allocations and make it difficult to elimination loops or residual
12535 # allocations for dynamic stack allocations
12536 proc check_effective_target_callee_realigns_stack { } {
12537 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12543 # Return 1 if CET instructions can be compiled.
12544 proc check_effective_target_cet { } {
12545 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12548 return [check_no_compiler_messages cet object {
12553 } "-O2 -fcf-protection" ]
12556 # Return 1 if target supports floating point "infinite"
12557 proc check_effective_target_inf { } {
12558 return [check_no_compiler_messages supports_inf assembly {
12559 const double pinf = __builtin_inf ();
12563 # Return 1 if target supports floating point "infinite" for float.
12564 proc check_effective_target_inff { } {
12565 return [check_no_compiler_messages supports_inff assembly {
12566 const float pinf = __builtin_inff ();
12570 # Return 1 if the target supports ARMv8.3 Adv.SIMD Complex instructions
12571 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
12572 # Record the command line options needed.
12574 proc check_effective_target_arm_v8_3a_complex_neon_ok_nocache { } {
12575 global et_arm_v8_3a_complex_neon_flags
12576 set et_arm_v8_3a_complex_neon_flags ""
12578 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
12582 # Iterate through sets of options to find the compiler flags that
12583 # need to be added to the -march option.
12584 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12585 if { [check_no_compiler_messages_nocache \
12586 arm_v8_3a_complex_neon_ok assembly {
12587 #if !defined (__ARM_FEATURE_COMPLEX)
12588 #error "__ARM_FEATURE_COMPLEX not defined"
12590 } "$flags -march=armv8.3-a"] } {
12591 set et_arm_v8_3a_complex_neon_flags "$flags -march=armv8.3-a"
12599 proc check_effective_target_arm_v8_3a_complex_neon_ok { } {
12600 return [check_cached_effective_target arm_v8_3a_complex_neon_ok \
12601 check_effective_target_arm_v8_3a_complex_neon_ok_nocache]
12604 proc add_options_for_arm_v8_3a_complex_neon { flags } {
12605 if { ! [check_effective_target_arm_v8_3a_complex_neon_ok] } {
12608 global et_arm_v8_3a_complex_neon_flags
12609 return "$flags $et_arm_v8_3a_complex_neon_flags"
12612 # Return 1 if the target supports ARMv8.3 Adv.SIMD + FP16 Complex instructions
12613 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
12614 # Record the command line options needed.
12616 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache { } {
12617 global et_arm_v8_3a_fp16_complex_neon_flags
12618 set et_arm_v8_3a_fp16_complex_neon_flags ""
12620 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
12624 # Iterate through sets of options to find the compiler flags that
12625 # need to be added to the -march option.
12626 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12627 if { [check_no_compiler_messages_nocache \
12628 arm_v8_3a_fp16_complex_neon_ok assembly {
12629 #if !defined (__ARM_FEATURE_COMPLEX)
12630 #error "__ARM_FEATURE_COMPLEX not defined"
12632 } "$flags -march=armv8.3-a+fp16"] } {
12633 set et_arm_v8_3a_fp16_complex_neon_flags \
12634 "$flags -march=armv8.3-a+fp16"
12642 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok { } {
12643 return [check_cached_effective_target arm_v8_3a_fp16_complex_neon_ok \
12644 check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache]
12647 proc add_options_for_arm_v8_3a_fp16_complex_neon { flags } {
12648 if { ! [check_effective_target_arm_v8_3a_fp16_complex_neon_ok] } {
12651 global et_arm_v8_3a_fp16_complex_neon_flags
12652 return "$flags $et_arm_v8_3a_fp16_complex_neon_flags"
12656 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.3
12657 # with the complex instruction extension, 0 otherwise. The test is valid for
12658 # ARM and for AArch64.
12660 proc check_effective_target_arm_v8_3a_complex_neon_hw { } {
12661 if { ![check_effective_target_arm_v8_3a_complex_neon_ok] } {
12664 return [check_runtime arm_v8_3a_complex_neon_hw_available {
12665 #include "arm_neon.h"
12670 float32x2_t results = {-4.0,5.0};
12671 float32x2_t a = {1.0,3.0};
12672 float32x2_t b = {2.0,5.0};
12674 #ifdef __ARM_ARCH_ISA_A64
12675 asm ("fcadd %0.2s, %1.2s, %2.2s, #90"
12678 : /* No clobbers. */);
12681 asm ("vcadd.f32 %P0, %P1, %P2, #90"
12684 : /* No clobbers. */);
12687 return (results[0] == 8 && results[1] == 24) ? 0 : 1;
12689 } [add_options_for_arm_v8_3a_complex_neon ""]]
12692 # Return 1 if the assembler supports assembling the Armv8.3 pointer authentication B key directive
12693 proc check_effective_target_arm_v8_3a_bkey_directive { } {
12694 return [check_no_compiler_messages cet object {
12696 asm (".cfi_b_key_frame");
12702 # Return 1 if the target supports executing the Armv8.1-M Mainline Low
12703 # Overhead Loop, 0 otherwise. The test is valid for ARM.
12705 proc check_effective_target_arm_v8_1_lob_ok { } {
12706 if { ![check_effective_target_arm_cortex_m] } {
12709 return [check_runtime arm_v8_1_lob_hw_available {
12713 asm ("movw r3, #10\n\t" /* movs? */
12714 "dls lr, r3" : : : "r3", "lr");
12717 asm goto ("le lr, %l0" : : : "lr" : loop);
12720 } "-march=armv8.1-m.main -mthumb" ]
12724 # Return 1 if this is an ARM target where Thumb-2 is used without
12725 # options added by the test and the target does not support executing
12726 # the Armv8.1-M Mainline Low Overhead Loop, 0 otherwise. The test is
12729 proc check_effective_target_arm_thumb2_no_arm_v8_1_lob { } {
12730 if { [check_effective_target_arm_thumb2]
12731 && ![check_effective_target_arm_v8_1_lob_ok] } {
12737 # Return 1 if this is an ARM target where -mthumb causes Thumb-2 to be
12738 # used and the target does not support executing the Armv8.1-M
12739 # Mainline Low Overhead Loop, 0 otherwise. The test is valid for ARM.
12741 proc check_effective_target_arm_thumb2_ok_no_arm_v8_1_lob { } {
12742 if { [check_effective_target_arm_thumb2_ok]
12743 && ![check_effective_target_arm_v8_1_lob_ok] } {
12749 # Returns 1 if the target is using glibc, 0 otherwise.
12751 proc check_effective_target_glibc { } {
12752 return [check_no_compiler_messages glibc_object assembly {
12753 #include <stdlib.h>
12754 #if !defined(__GLIBC__)
12760 # Return 1 if the target plus current options supports a vector
12761 # complex addition with rotate of half and single float modes, 0 otherwise.
12763 # This won't change for different subtargets so cache the result.
12765 foreach N {hf sf} {
12766 eval [string map [list N $N] {
12767 proc check_effective_target_vect_complex_rot_N { } {
12768 return [check_cached_effective_target_indexed vect_complex_rot_N {
12769 expr { [istarget aarch64*-*-*]
12770 || [istarget arm*-*-*] }}]
12775 # Return 1 if the target plus current options supports a vector
12776 # complex addition with rotate of double float modes, 0 otherwise.
12778 # This won't change for different subtargets so cache the result.
12781 eval [string map [list N $N] {
12782 proc check_effective_target_vect_complex_rot_N { } {
12783 return [check_cached_effective_target_indexed vect_complex_rot_N {
12784 expr { [istarget aarch64*-*-*] }}]
12789 # Return 1 if this target uses an LLVM assembler and/or linker
12790 proc check_effective_target_llvm_binutils { } {
12791 return [check_cached_effective_target llvm_binutils {
12792 expr { [istarget amdgcn*-*-*]
12793 || [check_effective_target_offload_gcn] }}]
12796 # Return 1 if the compiler supports '-mfentry'.
12798 proc check_effective_target_mfentry { } {
12799 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12802 return [check_no_compiler_messages mfentry object {
12803 void foo (void) { }
12807 # Return 1 if this target supports indirect calls
12808 proc check_effective_target_indirect_calls { } {
12809 if { [istarget bpf-*-*] } {
12815 # Return 1 if we can use the -lgccjit option, 0 otherwise.
12817 proc check_effective_target_lgccjit { } {
12818 if { [info procs jit_target_compile] == "" } then {
12819 global GCC_UNDER_TEST
12820 if ![info exists GCC_UNDER_TEST] {
12821 set GCC_UNDER_TEST "[find_gcc]"
12823 proc jit_target_compile { source dest type options } [info body gcc_target_compile]
12825 return [check_no_compiler_messages lgccjit executable {
12826 int main() { return 0; }
12830 # Return 1 if the MSP430 small memory model is in use.
12831 proc check_effective_target_msp430_small {} {
12832 return [check_no_compiler_messages msp430_small assembly {
12833 #if (!defined __MSP430__ || defined __MSP430X_LARGE__)
12834 #error !msp430 || __MSP430X_LARGE__
12839 # Return 1 if the MSP430 large memory model is in use.
12840 proc check_effective_target_msp430_large {} {
12841 return [check_no_compiler_messages msp430_large assembly {
12842 #ifndef __MSP430X_LARGE__
12843 #error __MSP430X_LARGE__
12848 # Return 1 if GCC was configured with --with-tune=cortex-a76
12849 proc check_effective_target_tune_cortex_a76 { } {
12850 return [check_configured_with "with-tune=cortex-a76"]
12853 # Return 1 if the target has an efficient means to encode large initializers
12856 proc check_effective_target_large_initializer { } {
12857 if { [istarget nvptx*-*-*] } {
12864 # Return 1 if the target allows function prototype mismatches
12867 proc check_effective_target_non_strict_prototype { } {
12868 if { [istarget nvptx*-*-*] } {
12875 # Returns 1 if the target toolchain supports extended
12876 # syntax of .symver directive, 0 otherwise.
12878 proc check_symver_available { } {
12879 return [check_no_compiler_messages symver_available object {
12880 int foo(void) { return 0; }
12882 asm volatile (".symver foo,foo@VER_1, local");
12888 # Return 1 if emitted assembly contains .ident directive.
12890 proc check_effective_target_ident_directive {} {
12891 return [check_no_messages_and_pattern ident_directive \
12892 "(?n)^\[\t\]+\\.ident" assembly {
12897 # Return 1 if we're able to assemble movdiri and movdir64b
12899 proc check_effective_target_movdir { } {
12900 return [check_no_compiler_messages movdir object {
12902 foo (unsigned int *d, unsigned int s)
12904 __builtin_ia32_directstoreu_u32 (d, s);
12907 bar (void *d, const void *s)
12909 __builtin_ia32_movdir64b (d, s);
12911 } "-mmovdiri -mmovdir64b" ]
12914 # Return 1 if the target does not support address sanitizer, 0 otherwise
12916 proc check_effective_target_no_fsanitize_address {} {
12917 if ![check_no_compiler_messages fsanitize_address executable {
12918 int main (void) { return 0; }
12919 } "-fsanitize=address" ] {
12926 # Return 1 if this target supports 'R' flag in .section directive, 0
12927 # otherwise. Cache the result.
12929 proc check_effective_target_R_flag_in_section { } {
12931 global GCC_UNDER_TEST
12933 # Need auto-host.h to check linker support.
12934 if { ![file exists ../../auto-host.h ] } {
12938 return [check_cached_effective_target R_flag_in_section {
12943 set f [open $src "w"]
12944 puts $f "#include \"../../auto-host.h\""
12945 puts $f "#if HAVE_GAS_SHF_GNU_RETAIN == 0 || HAVE_INITFINI_ARRAY_SUPPORT == 0"
12946 puts $f "# error Assembler does not support 'R' flag in .section directive."
12950 verbose "check_effective_target_R_flag_in_section compiling testfile $src" 2
12951 set lines [${tool}_target_compile $src $obj assembly ""]
12956 if [string match "" $lines] then {
12957 verbose "check_effective_target_R_flag_in_section testfile compilation passed" 2
12960 verbose "check_effective_target_R_flag_in_section testfile compilation failed" 2
12966 # Return 1 if this target supports 'o' flag in .section directive, 0
12967 # otherwise. Cache the result.
12969 proc check_effective_target_o_flag_in_section { } {
12971 global GCC_UNDER_TEST
12973 # Need auto-host.h to check linker support.
12974 if { ![file exists ../../auto-host.h ] } {
12978 return [check_cached_effective_target o_flag_in_section {
12983 set f [open $src "w"]
12984 puts $f "#include \"../../auto-host.h\""
12985 puts $f "#if HAVE_GAS_SECTION_LINK_ORDER == 0"
12986 puts $f "# error Assembler does not support 'o' flag in .section directive."
12990 verbose "check_effective_target_o_flag_in_section compiling testfile $src" 2
12991 set lines [${tool}_target_compile $src $obj object ""]
12996 if [string match "" $lines] then {
12997 verbose "check_effective_target_o_flag_in_section testfile compilation passed" 2
13000 verbose "check_effective_target_o_flag_in_section testfile compilation failed" 2
13006 # Return 1 if the given assembler supports hardware transactional memory
13007 # instructions with machine type Power10, 0 otherwise. Cache the result.
13009 proc check_effective_target_powerpc_as_p10_htm { } {
13011 global GCC_UNDER_TEST
13013 # Need auto-host.h to check linker support.
13014 if { ![file exists ../../auto-host.h ] } {
13018 return [check_cached_effective_target powerpc_as_p10_htm {
13023 set f [open $src "w"]
13024 puts $f "#include \"../../auto-host.h\""
13025 puts $f "#if HAVE_AS_POWER10_HTM == 0"
13026 puts $f "# error Assembler does not support htm insns with power10."
13030 verbose "check_effective_target_powerpc_as_p10_htm compiling testfile $src" 2
13031 set lines [${tool}_target_compile $src $obj object ""]
13036 if [string match "" $lines] then {
13037 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation passed" 2
13040 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation failed" 2
13046 # return 1 if LRA is supported.
13048 proc check_effective_target_lra { } {
13049 if { [istarget hppa*-*-*] || [istarget avr-*-*] } {
13055 # Test whether optimizations are enabled ('__OPTIMIZE__') per the
13056 # 'current_compiler_flags' (thus don't cache).
13058 proc check_effective_target___OPTIMIZE__ {} {
13059 return [check_no_compiler_messages_nocache __OPTIMIZE__ assembly {
13060 #ifndef __OPTIMIZE__
13063 /* Avoid pedwarn about empty TU. */
13065 } [current_compiler_flags]]
13068 # Return 1 if python3 (>= 3.6) is available.
13070 proc check_effective_target_recent_python3 { } {
13071 set result [remote_exec host "python3 -c \"import sys; assert sys.version_info >= (3, 6)\""]
13072 set status [lindex $result 0]
13073 if { $status == 0 } then {
13080 # Return 1 if python3 contains a module
13082 proc check_effective_target_python3_module { module } {
13083 set result [remote_exec host "python3 -c \"import $module\""]
13084 set status [lindex $result 0]
13085 if { $status == 0 } then {
13092 # Return 1 if pytest module is available for python3.
13094 proc check_effective_target_pytest3 { } {
13095 set result [remote_exec host "python3 -m pytest --color=no -rap -s --tb=no --version"]
13096 set status [lindex $result 0]
13097 if { $status == 0 } then {
13104 proc check_effective_target_property_1_needed { } {
13105 return [check_no_compiler_messages property_1_needed executable {
13106 /* Assembly code */
13108 # define __PROPERTY_ALIGN 3
13110 # define __PROPERTY_ALIGN 2
13113 .section ".note.gnu.property", "a"
13114 .p2align __PROPERTY_ALIGN
13115 .long 1f - 0f /* name length. */
13116 .long 4f - 1f /* data length. */
13117 /* NT_GNU_PROPERTY_TYPE_0. */
13118 .long 5 /* note type. */
13120 .asciz "GNU" /* vendor name. */
13122 .p2align __PROPERTY_ALIGN
13123 /* GNU_PROPERTY_1_NEEDED. */
13124 .long 0xb0008000 /* pr_type. */
13125 .long 3f - 2f /* pr_datasz. */
13127 /* GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. */
13130 .p2align __PROPERTY_ALIGN
13139 # Return 1 if this target has prog named "$prog", 0 otherwise.
13141 proc check_is_prog_name_available { prog } {
13144 set options [list "additional_flags=-print-prog-name=$prog"]
13145 set output [lindex [${tool}_target_compile "" "" "none" $options] 0]
13147 if { $output == $prog } {
13154 # returns 1 if target does selects a readonly section for const volatile variables.
13155 proc check_effective_target_const_volatile_readonly_section { } {
13157 if { [istarget powerpc-*-*]
13158 || [check-flags { "" { powerpc64-*-* } { -m32 } }] } {
13164 # Return 1 if the CORE-V MAC extension is available.
13165 proc check_effective_target_cv_mac { } {
13166 if { !([istarget riscv*-*-*]) } {
13169 return [check_no_compiler_messages cv_mac object {
13172 asm ("cv.mac t0, t1, t2");
13174 } "-march=rv32i_xcvmac" ]
13177 # Return 1 if the CORE-V ALU extension is available.
13178 proc check_effective_target_cv_alu { } {
13179 if { !([istarget riscv*-*-*]) } {
13182 return [check_no_compiler_messages cv_alu object {
13185 asm ("cv.addn t0, t1, t2, 0");
13187 } "-march=rv32i_xcvalu" ]
13190 # Return 1 if the CORE-V ELW extension is available.
13191 proc check_effective_target_cv_elw { } {
13192 if { !([istarget riscv*-*-*]) } {
13195 return [check_no_compiler_messages cv_elw object {
13198 asm ("cv.elw x0, 0(x0)");
13200 } "-march=rv32i_xcvelw" ]
13203 proc check_effective_target_loongarch_sx { } {
13204 return [check_no_compiler_messages loongarch_lsx assembly {
13205 #if !defined(__loongarch_sx)
13206 #error "LSX not defined"
13211 proc check_effective_target_loongarch_sx_hw { } {
13212 return [check_runtime loongarch_sx_hw {
13213 #include <lsxintrin.h>
13217 c = __lsx_vand_v (a, b);
13223 proc check_effective_target_loongarch_asx { } {
13224 return [check_no_compiler_messages loongarch_asx assembly {
13225 #if !defined(__loongarch_asx)
13226 #error "LASX not defined"
13231 proc check_effective_target_loongarch_asx_hw { } {
13232 return [check_runtime loongarch_asx_hw {
13233 #include <lasxintrin.h>
13237 c = __lasx_xvand_v (a, b);
13243 # Check whether LoongArch binutils supports call36 relocation.
13244 proc check_effective_target_loongarch_call36_support { } {
13245 return [check_no_compiler_messages loongarch_call36_support object {
13246 /* Assembly code */
13247 pcaddu18i $r1,%call36(a)
13252 # Returns 1 if binutils supports TLS le Relax, 0 otherwise.
13253 proc check_effective_target_tls_le_relax { } {
13254 if [check_effective_target_tls_native] {
13255 return [check_no_compiler_messages loongarch_tls_le_relax object {
13256 /* Assembly code */
13257 lu12i.w $r12, %le_hi20_r(a)
13264 # Appends necessary Python flags to extra-tool-flags if Python.h is supported.
13265 # Otherwise, modifies dg-do-what.
13266 proc dg-require-python-h { args } {
13267 upvar dg-extra-tool-flags extra-tool-flags
13269 verbose "ENTER dg-require-python-h" 2
13272 set result [remote_exec host "python3-config --includes"]
13273 set status [lindex $result 0]
13274 if { $status == 0 } {
13275 # Remove trailing newline from python3-config output.
13276 set python_flags [string trim [lindex $result 1]]
13277 if [check_no_compiler_messages python_h assembly {
13278 #include <Python.h>
13279 int main (void) { return 0; }
13285 if { $supported == 0 } {
13286 verbose "Python.h not supported" 2
13287 upvar dg-do-what dg-do-what
13288 set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
13292 verbose "Python flags are: $python_flags" 2
13294 verbose "Before appending, extra-tool-flags: ${extra-tool-flags}" 3
13295 eval lappend extra-tool-flags $python_flags
13296 verbose "After appending, extra-tool-flags: ${extra-tool-flags}" 3