1 # Copyright (C) 1999-2024 Free Software Foundation, Inc.
3 # This program is free software; you can redistribute it and/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation; either version 3 of the License, or
6 # (at your option) any later version.
8 # This program is distributed in the hope that it will be useful,
9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with GCC; see the file COPYING3. If not see
15 # <http://www.gnu.org/licenses/>.
17 # Please email any bugs, comments, and/or additions to this file to:
18 # gcc-patches@gcc.gnu.org
20 # This file defines procs for determining features supported by the target.
22 # Try to compile the code given by CONTENTS into an output file of
23 # type TYPE, where TYPE is as for target_compile. Return a list
24 # whose first element contains the compiler messages and whose
25 # second element is the name of the output file.
27 # BASENAME is a prefix to use for source and output files.
28 # If ARGS is not empty, its first element is a string that
29 # should be added to the command line.
31 # Assume by default that CONTENTS is C code.
32 # Otherwise, code should contain:
33 # "/* Assembly" for assembly code,
36 # "! Fortran" for Fortran code,
38 # "// ObjC++" for ObjC++
41 # and "(* Modula-2" for Modula-2
42 # If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
43 # allow for ObjC/ObjC++ specific flags.
45 proc check_compile {basename type contents args} {
47 verbose "check_compile tool: $tool for $basename"
49 # Save additional_sources to avoid compiling testsuite's sources
50 # against check_compile's source.
51 global additional_sources
52 if [info exists additional_sources] {
53 set tmp_additional_sources "$additional_sources"
54 set additional_sources ""
57 if { [llength $args] > 0 } {
58 set options [list "additional_flags=[lindex $args 0]"]
62 # Silence "command-line option [...] is valid for [...] but not for [...]"
63 # that we may easily run into here, if more than one language is involved.
64 lappend options additional_flags=-Wno-complain-wrong-lang
66 switch -glob -- $contents {
67 "*/\\* Assembly*" { set src ${basename}[pid].S }
68 "*! Fortran*" { set src ${basename}[pid].f90 }
69 "*// C++*" { set src ${basename}[pid].cc }
70 "*// D*" { set src ${basename}[pid].d }
71 "*// ObjC++*" { set src ${basename}[pid].mm }
72 "*/\\* ObjC*" { set src ${basename}[pid].m }
73 "*// Go*" { set src ${basename}[pid].go }
74 "*// Rust*" { set src ${basename}[pid].rs }
75 "*(\\* Modula-2*" { set src ${basename}[pid].mod }
78 "objc" { set src ${basename}[pid].m }
79 "obj-c++" { set src ${basename}[pid].mm }
80 default { set src ${basename}[pid].c }
85 set compile_type $type
87 assembly { set output ${basename}[pid].s }
88 object { set output ${basename}[pid].o }
89 executable { set output ${basename}[pid].exe }
92 set output ${basename}[pid].s
93 lappend options "additional_flags=-fdump-$type"
94 set compile_type assembly
100 global compiler_flags
101 set save_compiler_flags $compiler_flags
102 set lines [${tool}_target_compile $src $output $compile_type "$options"]
103 set compiler_flags $save_compiler_flags
106 set scan_output $output
107 # Don't try folding this into the switch above; calling "glob" before the
108 # file is created won't work.
109 if [regexp "rtl-(.*)" $type dummy rtl_type] {
110 set scan_output "[glob $src.\[0-9\]\[0-9\]\[0-9\]r.$rtl_type]"
112 } elseif [regexp "tree-(.*)" $type dummy tree_type] {
113 set scan_output "[glob $src.\[0-9\]\[0-9\]\[0-9\]t.$tree_type]"
117 # Restore additional_sources.
118 if [info exists additional_sources] {
119 set additional_sources "$tmp_additional_sources"
122 return [list $lines $scan_output]
125 proc current_target_name { } {
127 if [info exists target_info(target,name)] {
128 set answer $target_info(target,name)
135 # Implement an effective-target check for property PROP by invoking
136 # the Tcl command ARGS and seeing if it returns true.
138 proc check_cached_effective_target { prop args } {
141 set target [current_target_name]
142 if {![info exists et_cache($prop,$target)]} {
143 verbose "check_cached_effective_target $prop: checking $target" 2
144 if {[string is true -strict $args] || [string is false -strict $args]} {
145 error {check_cached_effective_target condition already evaluated; did you pass [...] instead of the expected {...}?}
147 set code [catch {uplevel eval $args} result]
148 if {$code != 0 && $code != 2} {
149 return -code $code $result
151 set et_cache($prop,$target) $result
154 set value $et_cache($prop,$target)
155 verbose "check_cached_effective_target $prop: returning $value for $target" 2
159 # Implements a version of check_cached_effective_target that also takes et_index
160 # into account when creating the key for the cache.
161 proc check_cached_effective_target_indexed { prop args } {
163 set key "$et_index $prop"
164 verbose "check_cached_effective_target_index $prop: returning $key" 2
166 return [check_cached_effective_target $key [list uplevel eval $args]]
169 # Clear effective-target cache. This is useful after testing
170 # effective-target features and overriding TEST_ALWAYS_FLAGS and/or
172 # If one changes ALWAYS_CXXFLAGS or TEST_ALWAYS_FLAGS then they should
173 # do a clear_effective_target_cache at the end as the target cache can
174 # make decisions based upon the flags, and those decisions need to be
175 # redone when the flags change. An example of this is the
176 # asan_init/asan_finish pair.
178 proc clear_effective_target_cache { } {
183 # Like check_compile, but delete the output file and return true if the
184 # compiler printed no messages.
185 proc check_no_compiler_messages_nocache {args} {
186 set result [eval check_compile $args]
187 set lines [lindex $result 0]
188 set output [lindex $result 1]
189 remote_file build delete $output
190 return [string match "" $lines]
193 # Like check_no_compiler_messages_nocache, but cache the result.
194 # PROP is the property we're checking, and doubles as a prefix for
195 # temporary filenames.
196 proc check_no_compiler_messages {prop args} {
197 return [check_cached_effective_target $prop {
198 eval [list check_no_compiler_messages_nocache $prop] $args
202 # Like check_compile, but return true if the compiler printed no
203 # messages and if the contents of the output file satisfy PATTERN.
204 # If PATTERN has the form "!REGEXP", the contents satisfy it if they
205 # don't match regular expression REGEXP, otherwise they satisfy it
206 # if they do match regular expression PATTERN. (PATTERN can start
207 # with something like "[!]" if the regular expression needs to match
208 # "!" as the first character.)
210 # Delete the output file before returning. The other arguments are
211 # as for check_compile.
212 proc check_no_messages_and_pattern_nocache {basename pattern args} {
215 set result [eval [list check_compile $basename] $args]
216 set lines [lindex $result 0]
217 set output [lindex $result 1]
220 if { [string match "" $lines] } {
221 set chan [open "$output"]
222 set invert [regexp {^!(.*)} $pattern dummy pattern]
223 set ok [expr { [regexp $pattern [read $chan]] != $invert }]
227 remote_file build delete $output
231 # Like check_no_messages_and_pattern_nocache, but cache the result.
232 # PROP is the property we're checking, and doubles as a prefix for
233 # temporary filenames.
234 proc check_no_messages_and_pattern {prop pattern args} {
235 return [check_cached_effective_target $prop {
236 eval [list check_no_messages_and_pattern_nocache $prop $pattern] $args
240 # Try to compile and run an executable from code CONTENTS. Return true
241 # if the compiler reports no messages and if execution "passes" in the
242 # usual DejaGNU sense. The arguments are as for check_compile, with
243 # TYPE implicitly being "executable".
244 proc check_runtime_nocache {basename contents args} {
247 set result [eval [list check_compile $basename executable $contents] $args]
248 set lines [lindex $result 0]
249 set output [lindex $result 1]
252 if { [string match "" $lines] } {
253 # No error messages, everything is OK.
254 set result [remote_load target "./$output" "" ""]
255 set status [lindex $result 0]
256 verbose "check_runtime_nocache $basename: status is <$status>" 2
257 if { $status == "pass" } {
261 remote_file build delete $output
265 # Like check_runtime_nocache, but cache the result. PROP is the
266 # property we're checking, and doubles as a prefix for temporary
268 proc check_runtime {prop args} {
271 return [check_cached_effective_target $prop {
272 eval [list check_runtime_nocache $prop] $args
276 # Return 1 if GCC was configured with $pattern.
277 proc check_configured_with { pattern } {
280 set options [list "additional_flags=-v"]
281 set gcc_output [${tool}_target_compile "" "" "none" $options]
282 if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
283 verbose "Matched: $pattern" 2
287 verbose "Failed to match: $pattern" 2
291 ###############################
292 # proc check_weak_available { }
293 ###############################
295 # weak symbols are only supported in some configs/object formats
296 # this proc returns 1 if they're supported, 0 if they're not, or -1 if unsure
298 proc check_weak_available { } {
301 # All mips targets should support it
303 if { [ string first "mips" $target_cpu ] >= 0 } {
307 # All AIX targets should support it
309 if { [istarget *-*-aix*] } {
313 # All solaris2 targets should support it
315 if { [istarget *-*-solaris2*] } {
319 # Windows targets Cygwin and MingW32 support it
321 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
325 # nvptx (nearly) supports it
327 if { [istarget nvptx-*-*] } {
331 # pdp11 doesn't support it
333 if { [istarget pdp11*-*-*] } {
337 # VxWorks hardly supports it (vx7 RTPs only)
339 if { [istarget *-*-vxworks*] } {
343 # ELF and ECOFF support it. a.out does with gas/gld but may also with
344 # other linkers, so we should try it
346 set objformat [gcc_target_object_format]
354 unknown { return -1 }
359 # return options to add to enable weak undefined symbols.
361 proc add_options_for_weak_undefined { flags } {
362 if { [istarget *-*-darwin*] } {
363 lappend flags "-Wl,-undefined,dynamic_lookup"
364 if { [istarget *-*-darwin\[89\]*] } {
365 lappend flags "-Wl,-flat_namespace"
371 # return 1 if weak undefined symbols are supported.
373 proc check_effective_target_weak_undefined { } {
374 if { [istarget hppa*-*-hpux*] } {
377 return [check_runtime weak_undefined {
378 extern void foo () __attribute__((weak));
379 int main (void) { if (foo) return 1; return 0; }
380 } [add_options_for_weak_undefined ""]]
383 ###############################
384 # proc check_weak_override_available { }
385 ###############################
387 # Like check_weak_available, but return 0 if weak symbol definitions
388 # cannot be overridden.
390 proc check_weak_override_available { } {
391 if { [istarget *-*-mingw*] } {
394 return [check_weak_available]
397 # Return 1 if VMA is equal to LMA for the .data section, 0
398 # otherwise. Cache the result.
400 proc check_effective_target_vma_equals_lma { } {
403 return [check_cached_effective_target vma_equals_lma {
404 set src vma_equals_lma[pid].c
405 set exe vma_equals_lma[pid].exe
406 verbose "check_effective_target_vma_equals_lma compiling testfile $src" 2
407 set f [open $src "w"]
408 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
409 puts $f "int foo = 42; void main() {}"
411 set lines [${tool}_target_compile $src $exe executable ""]
414 if [string match "" $lines] then {
417 set objdump_name [find_binutils_prog objdump]
418 set output [remote_exec host "$objdump_name" "--section-headers --section=.data $exe"]
419 set output [lindex $output 1]
421 remote_file build delete $exe
423 # Example output of objdump:
424 #vma_equals_lma9059.exe: file format elf32-littlearm
427 #Idx Name Size VMA LMA File off Algn
428 # 6 .data 00000558 20000000 08002658 00020000 2**3
429 # CONTENTS, ALLOC, LOAD, DATA
431 # Capture LMA and VMA columns for .data section
432 if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy vma lma ] {
433 verbose "Could not parse objdump output" 2
436 return [string equal $vma $lma]
439 remote_file build delete $exe
440 verbose "Could not determine if VMA is equal to LMA. Assuming not equal." 2
446 # The "noinit" attribute is only supported by some targets.
447 # This proc returns 1 if it's supported, 0 if it's not.
449 proc check_effective_target_noinit { } {
450 if { [istarget arm*-*-eabi]
451 || [istarget msp430-*-*] } {
458 # The "persistent" attribute is only supported by some targets.
459 # This proc returns 1 if it's supported, 0 if it's not.
461 proc check_effective_target_persistent { } {
462 if { [istarget arm*-*-eabi]
463 || [istarget msp430-*-*] } {
470 ###############################
471 # proc check_visibility_available { what_kind }
472 ###############################
474 # The visibility attribute is only support in some object formats
475 # This proc returns 1 if it is supported, 0 if not.
476 # The argument is the kind of visibility, default/protected/hidden/internal.
478 proc check_visibility_available { what_kind } {
479 if [string match "" $what_kind] { set what_kind "hidden" }
481 return [check_no_compiler_messages visibility_available_$what_kind object "
482 void f() __attribute__((visibility(\"$what_kind\")));
487 ###############################
488 # proc check_alias_available { }
489 ###############################
491 # Determine if the target toolchain supports the alias attribute.
493 # Returns 2 if the target supports aliases. Returns 1 if the target
494 # only supports weak aliased. Returns 0 if the target does not
495 # support aliases at all. Returns -1 if support for aliases could not
498 proc check_alias_available { } {
501 return [check_cached_effective_target alias_available {
504 verbose "check_alias_available compiling testfile $src" 2
505 set f [open $src "w"]
506 # Compile a small test program. The definition of "g" is
507 # necessary to keep the Solaris assembler from complaining
509 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
510 puts $f "void g() {} void f() __attribute__((alias(\"g\")));"
512 set lines [${tool}_target_compile $src $obj object ""]
514 remote_file build delete $obj
516 if [string match "" $lines] then {
517 # No error messages, everything is OK.
520 if [regexp "alias definitions not supported" $lines] {
521 verbose "check_alias_available target does not support aliases" 2
523 set objformat [gcc_target_object_format]
525 if { $objformat == "elf" } {
526 verbose "check_alias_available but target uses ELF format, so it ought to" 2
532 if [regexp "only weak aliases are supported" $lines] {
533 verbose "check_alias_available target supports only weak aliases" 2
543 # Returns 1 if the target toolchain supports strong aliases, 0 otherwise.
545 proc check_effective_target_alias { } {
546 if { [check_alias_available] < 2 } {
553 # Returns 1 if the target uses the ELF object format, 0 otherwise.
555 proc check_effective_target_elf { } {
556 if { [gcc_target_object_format] == "elf" } {
563 # Returns 1 if the target toolchain supports ifunc, 0 otherwise.
565 proc check_ifunc_available { } {
566 return [check_no_compiler_messages ifunc_available object {
571 typedef void F (void);
572 F* g (void) { return &f_; }
573 void f () __attribute__ ((ifunc ("g")));
580 # Returns true if --gc-sections is supported on the target.
582 proc check_gc_sections_available { } {
585 return [check_cached_effective_target gc_sections_available {
586 # Some targets don't support gc-sections despite whatever's
587 # advertised by ld's options.
588 if { [istarget alpha*-*-*]
589 || [istarget ia64-*-*] } {
593 # elf2flt uses -q (--emit-relocs), which is incompatible with
595 if { [board_info target exists ldflags]
596 && [regexp " -elf2flt\[ =\]" " [board_info target ldflags] "] } {
600 # VxWorks kernel modules are relocatable objects linked with -r,
601 # while RTP executables are linked with -q (--emit-relocs).
602 # Both of these options are incompatible with --gc-sections.
603 if { [istarget *-*-vxworks*] } {
607 # Check if the ld used by gcc supports --gc-sections.
608 set options [list "additional_flags=-print-prog-name=ld"]
609 set gcc_ld [lindex [${tool}_target_compile "" "" "none" $options] 0]
610 set ld_output [remote_exec host "$gcc_ld" "--help"]
611 if { [ string first "--gc-sections" $ld_output ] >= 0 } {
619 # Returns 1 if "dot" is supported on the host.
621 proc check_dot_available { } {
622 verbose "check_dot_available" 2
624 set status [remote_exec host "dot" "-V"]
625 verbose " status: $status" 2
626 if { [lindex $status 0] != 0 } {
632 # Return 1 if according to target_info struct and explicit target list
633 # target is supposed to support trampolines.
635 proc check_effective_target_trampolines { } {
636 if [target_info exists gcc,no_trampolines] {
639 if { [istarget avr-*-*]
640 || [istarget msp430-*-*]
641 || [istarget nvptx-*-*]
642 || [istarget pru-*-*]
643 || [istarget bpf-*-*] } {
649 # Return 1 if target has limited stack size.
651 proc check_effective_target_stack_size { } {
652 # For nvptx target, stack size limits are relevant for execution only.
653 if { [istarget nvptx-*-*] } {
654 # Find 'dg-do-what' in an outer frame.
657 upvar $level dg-do-what dg-do-what
658 if [info exists dg-do-what] then break
661 verbose "check_effective_target_stack_size: found dg-do-what at level $level" 2
663 if { ![string equal [lindex ${dg-do-what} 0] run] } {
668 if [target_info exists gcc,stack_size] {
674 # Return the value attribute of an effective target, otherwise return 0.
676 proc dg-effective-target-value { effective_target } {
677 if { "$effective_target" == "stack_size" } {
678 if [check_effective_target_stack_size] {
679 return [target_info gcc,stack_size]
686 # Return 1 if signal.h is supported.
688 proc check_effective_target_signal { } {
689 if [target_info exists gcc,signal_suppress] {
695 # Return 1 if according to target_info struct and explicit target list
696 # target disables -fdelete-null-pointer-checks. Targets should return 0
697 # if they simply default to -fno-delete-null-pointer-checks but obey
698 # -fdelete-null-pointer-checks when passed explicitly (and tests that
699 # depend on this option should do that).
701 proc check_effective_target_keeps_null_pointer_checks { } {
702 if [target_info exists keeps_null_pointer_checks] {
705 if { [istarget msp430-*-*]
706 || [istarget avr-*-*] } {
712 # Return the autofdo profile wrapper
714 # Linux by default allows 516KB of perf event buffers
715 # in /proc/sys/kernel/perf_event_mlock_kb
716 # Each individual perf tries to grab it
717 # This causes problems with parallel test suite runs. Instead
718 # limit us to 8 pages (32K), which should be good enough
719 # for the small test programs. With the default settings
720 # this allows parallelism of 16 and higher of parallel gcc-auto-profile
721 proc profopt-perf-wrapper { } {
723 return "$srcdir/../config/i386/gcc-auto-profile --all -m8 "
726 # Return true if profiling is supported on the target.
728 proc check_profiling_available { test_what } {
729 verbose "Profiling argument is <$test_what>" 1
731 # These conditions depend on the argument so examine them before
732 # looking at the cache variable.
734 # Tree profiling requires TLS runtime support.
735 if { $test_what == "-fprofile-generate" } {
736 if { ![check_effective_target_tls_runtime] } {
741 if { $test_what == "-fauto-profile" } {
742 if { !([istarget i?86-*-linux*] || [istarget x86_64-*-linux*]) } {
743 verbose "autofdo only supported on linux"
746 # not cross compiling?
748 verbose "autofdo not supported for non native builds"
751 set event [profopt-perf-wrapper]
753 verbose "autofdo not supported"
757 set status [remote_exec host "$srcdir/../config/i386/gcc-auto-profile" "-m8 true -v >/dev/null"]
758 if { [lindex $status 0] != 0 } {
759 verbose "autofdo not supported because perf does not work"
763 # no good way to check this in advance -- check later instead.
764 #set status [remote_exec host "create_gcov" "2>/dev/null"]
765 #if { [lindex $status 0] != 255 } {
766 # verbose "autofdo not supported due to missing create_gcov"
771 # Support for -p on solaris2 relies on mcrt1.o which comes with the
772 # vendor compiler. We cannot reliably predict the directory where the
773 # vendor compiler (and thus mcrt1.o) is installed so we can't
774 # necessarily find mcrt1.o even if we have it.
775 if { [istarget *-*-solaris2*] && $test_what == "-p" } {
779 # We don't yet support profiling for MIPS16.
780 if { [istarget mips*-*-*]
781 && ![check_effective_target_nomips16]
782 && ($test_what == "-p" || $test_what == "-pg") } {
786 # MinGW does not support -p.
787 if { [istarget *-*-mingw*] && $test_what == "-p" } {
791 # cygwin does not support -p.
792 if { [istarget *-*-cygwin*] && $test_what == "-p" } {
796 # uClibc does not have gcrt1.o.
797 if { [check_effective_target_uclibc]
798 && ($test_what == "-p" || $test_what == "-pg") } {
802 # Now examine the cache variable.
803 set profiling_working \
804 [check_cached_effective_target profiling_available {
805 # Some targets don't have any implementation of __bb_init_func or are
806 # missing other needed machinery.
807 if {[istarget aarch64*-*-elf]
808 || [istarget am3*-*-linux*]
809 || [istarget amdgcn-*-*]
810 || [istarget arm*-*-eabi*]
811 || [istarget arm*-*-elf]
812 || [istarget arm*-*-symbianelf*]
813 || [istarget avr-*-*]
814 || [istarget bfin-*-*]
815 || [istarget cris-*-*]
816 || [istarget csky-*-elf*]
817 || [istarget fido-*-elf]
818 || [istarget h8300-*-*]
819 || [istarget lm32-*-*]
820 || [istarget m32c-*-elf]
821 || [istarget m68k-*-elf]
822 || [istarget m68k-*-uclinux*]
823 || [istarget mips*-*-elf*]
824 || [istarget mmix-*-*]
825 || [istarget mn10300-*-elf*]
826 || [istarget moxie-*-elf*]
827 || [istarget msp430-*-*]
828 || [istarget nds32*-*-elf]
829 || [istarget nios2-*-elf]
830 || [istarget nvptx-*-*]
831 || [istarget powerpc-*-eabi*]
832 || [istarget powerpc-*-elf]
833 || [istarget pru-*-*]
835 || [istarget tic6x-*-elf]
836 || [istarget visium-*-*]
837 || [istarget xstormy16-*]
838 || [istarget xtensa*-*-elf]
839 || [istarget *-*-rtems*]
840 || [istarget *-*-vxworks*] } {
847 # -pg link test result can't be cached since it may change between
849 if { $profiling_working == 1
850 && ![check_no_compiler_messages_nocache profiling executable {
851 int main() { return 0; } } "-pg"] } {
852 set profiling_working 0
855 return $profiling_working
858 # Check to see if a target is "freestanding". This is as per the definition
859 # in Section 4 of C99 standard. Effectively, it is a target which supports no
860 # extra headers or libraries other than what is considered essential.
861 proc check_effective_target_freestanding { } {
862 if { [istarget nvptx-*-*] } {
868 # Check to see that file I/O functions are available.
869 proc check_effective_target_fileio { } {
870 return [check_no_compiler_messages fileio_available executable {
873 char *n = tmpnam (NULL);
874 FILE *f = fopen (n, "w");
881 # Return 1 if target has packed layout of structure members by
882 # default, 0 otherwise. Note that this is slightly different than
883 # whether the target has "natural alignment": both attributes may be
886 proc check_effective_target_default_packed { } {
887 return [check_no_compiler_messages default_packed assembly {
888 struct x { char a; long b; } c;
889 int s[sizeof (c) == sizeof (char) + sizeof (long) ? 1 : -1];
893 # Return 1 if target has PCC_BITFIELD_TYPE_MATTERS defined. See
894 # documentation, where the test also comes from.
896 proc check_effective_target_pcc_bitfield_type_matters { } {
897 # PCC_BITFIELD_TYPE_MATTERS isn't just about unnamed or empty
898 # bitfields, but let's stick to the example code from the docs.
899 return [check_no_compiler_messages pcc_bitfield_type_matters assembly {
900 struct foo1 { char x; char :0; char y; };
901 struct foo2 { char x; int :0; char y; };
902 int s[sizeof (struct foo1) != sizeof (struct foo2) ? 1 : -1];
906 # Add to FLAGS all the target-specific flags needed to use thread-local storage.
908 proc add_options_for_tls { flags } {
909 # On AIX, __tls_get_addr/___tls_get_addr only lives in
910 # libthread, so always pass -pthread for native TLS.
911 # Need to duplicate native TLS check from
912 # check_effective_target_tls_native to avoid recursion.
913 if { ([istarget powerpc-ibm-aix*]) &&
914 [check_no_messages_and_pattern tls_native "!emutls" assembly {
916 int f (void) { return i; }
917 void g (int j) { i = j; }
919 return "-pthread [g++_link_flags [get_multilibs "-pthread"] ] $flags "
924 # Return 1 if indirect jumps are supported, 0 otherwise.
926 proc check_effective_target_indirect_jumps {} {
927 if { [istarget nvptx-*-*] || [istarget bpf-*-*] } {
933 # Return 1 if nonlocal goto is supported, 0 otherwise.
935 proc check_effective_target_nonlocal_goto {} {
936 if { [istarget nvptx-*-*] || [istarget bpf-*-*] } {
942 # Return 1 if global constructors are supported, 0 otherwise.
944 proc check_effective_target_global_constructor {} {
945 if { [istarget nvptx-*-*]
946 || [istarget bpf-*-*] } {
952 # Return 1 if taking label values is supported, 0 otherwise.
954 proc check_effective_target_label_values {} {
955 if { [istarget nvptx-*-*] || [target_info exists gcc,no_label_values] } {
962 # Return 1 if builtin_return_address and builtin_frame_address are
963 # supported, 0 otherwise.
965 proc check_effective_target_return_address {} {
966 if { [istarget nvptx-*-*] } {
969 # No notion of return address in eBPF.
970 if { [istarget bpf-*-*] } {
973 # It could be supported on amdgcn, but isn't yet.
974 if { [istarget amdgcn*-*-*] } {
980 # Return 1 if the assembler does not verify function types against
981 # calls, 0 otherwise. Such verification will typically show up problems
982 # with K&R C function declarations.
984 proc check_effective_target_untyped_assembly {} {
985 if { [istarget nvptx-*-*] } {
991 # Return 1 if alloca is supported, 0 otherwise.
993 proc check_effective_target_alloca {} {
994 if { [istarget bpf-*-*] } {
997 if { [istarget nvptx-*-*] } {
998 return [check_no_compiler_messages alloca assembly {
1000 void g (int n) { f (__builtin_alloca (n)); }
1006 # Return 1 if thread local storage (TLS) is supported, 0 otherwise.
1008 proc check_effective_target_tls {} {
1009 return [check_no_compiler_messages tls assembly {
1011 int f (void) { return i; }
1012 void g (int j) { i = j; }
1016 # Return 1 if *native* thread local storage (TLS) is supported, 0 otherwise.
1018 proc check_effective_target_tls_native {} {
1019 # VxWorks uses emulated TLS machinery, but with non-standard helper
1020 # functions, so we fail to automatically detect it.
1021 if { [istarget *-*-vxworks*] } {
1025 return [check_no_messages_and_pattern tls_native "!emutls" assembly {
1027 int f (void) { return i; }
1028 void g (int j) { i = j; }
1032 # Return 1 if *emulated* thread local storage (TLS) is supported, 0 otherwise.
1034 proc check_effective_target_tls_emulated {} {
1035 # VxWorks uses emulated TLS machinery, but with non-standard helper
1036 # functions, so we fail to automatically detect it.
1037 if { [istarget *-*-vxworks*] } {
1041 return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
1043 int f (void) { return i; }
1044 void g (int j) { i = j; }
1048 # Return 1 if TLS executables can run correctly, 0 otherwise.
1050 proc check_effective_target_tls_runtime {} {
1051 return [check_runtime tls_runtime {
1052 __thread int thr __attribute__((tls_model("global-dynamic"))) = 0;
1053 int main (void) { return thr; }
1054 } [add_options_for_tls ""]]
1057 # Return 1 if atomic compare-and-swap is supported on 'int'
1059 proc check_effective_target_cas_char {} {
1060 return [check_no_compiler_messages cas_char assembly {
1061 #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
1067 proc check_effective_target_cas_int {} {
1068 return [check_no_compiler_messages cas_int assembly {
1069 #if __INT_MAX__ == 0x7fff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
1071 #elif __INT_MAX__ == 0x7fffffff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
1079 # Return 1 if -ffunction-sections is supported, 0 otherwise.
1081 proc check_effective_target_function_sections {} {
1082 # Darwin has its own scheme and silently accepts -ffunction-sections.
1083 if { [istarget *-*-darwin*] } {
1087 return [check_no_compiler_messages functionsections assembly {
1089 } "-ffunction-sections"]
1092 # Return 1 if instruction scheduling is available, 0 otherwise.
1094 proc check_effective_target_scheduling {} {
1095 return [check_no_compiler_messages scheduling object {
1097 } "-fschedule-insns"]
1100 # Return 1 if trapping arithmetic is available, 0 otherwise.
1102 proc check_effective_target_trapping {} {
1103 return [check_no_compiler_messages trapping object {
1104 int add (int a, int b) { return a + b; }
1108 # Return 1 if compilation with -fgraphite is error-free for trivial
1109 # code, 0 otherwise.
1111 proc check_effective_target_fgraphite {} {
1112 return [check_no_compiler_messages fgraphite object {
1117 # Return 1 if compiled with --enable-offload-targets=
1118 # This affects host compilation as ENABLE_OFFLOAD then evaluates to true.
1119 proc check_effective_target_offloading_enabled {} {
1120 return [check_configured_with "--enable-offload-targets"]
1123 # Return 1 if compilation with -fopenacc is error-free for trivial
1124 # code, 0 otherwise.
1126 proc check_effective_target_fopenacc {} {
1127 # nvptx/amdgcn can be built with the device-side bits of openacc, but it
1128 # does not make sense to test it as an openacc host.
1129 if [istarget nvptx-*-*] { return 0 }
1130 if [istarget amdgcn-*-*] { return 0 }
1132 return [check_no_compiler_messages fopenacc object {
1137 # Return 1 if compilation with -fopenmp is error-free for trivial
1138 # code, 0 otherwise.
1140 proc check_effective_target_fopenmp {} {
1141 # nvptx/amdgcn can be built with the device-side bits of libgomp, but it
1142 # does not make sense to test it as an openmp host.
1143 if [istarget nvptx-*-*] { return 0 }
1144 if [istarget amdgcn-*-*] { return 0 }
1146 return [check_no_compiler_messages fopenmp object {
1151 # Return 1 if compilation with -fgnu-tm is error-free for trivial
1152 # code, 0 otherwise.
1154 proc check_effective_target_fgnu_tm {} {
1155 return [check_no_compiler_messages fgnu_tm object {
1160 # Return 1 if the target supports mmap, 0 otherwise.
1162 proc check_effective_target_mmap {} {
1163 return [check_function_available "mmap"]
1166 # Return 1 if the target supports sysconf, 0 otherwise.
1168 proc check_effective_target_sysconf {} {
1169 # VxWorks has sysconf in rtp mode only, but our way to test can't
1170 # tell kernel mode doesn't, as we're doing partial links for
1171 # kernel modules. We can tell by checking for a declaration, or
1172 # for some sysconf parm, because configurations that don't offer
1173 # sysconf don't have either.
1174 if { [istarget *-*-vxworks*] } {
1175 return [check_no_compiler_messages sysconfdecl assembly {
1177 int f() { return sysconf(_SC_PAGESIZE); }
1180 return [check_function_available "sysconf"]
1183 # Return 1 if the target supports dlopen, 0 otherwise.
1184 proc check_effective_target_dlopen {} {
1185 return [check_no_compiler_messages dlopen executable {
1187 int main(void) { dlopen ("dummy.so", RTLD_NOW); }
1188 } [add_options_for_dlopen ""]]
1191 proc add_options_for_dlopen { flags } {
1192 return "$flags -ldl"
1195 # Return 1 if the target supports clone, 0 otherwise.
1196 proc check_effective_target_clone {} {
1197 return [check_function_available "clone"]
1200 # Return 1 if the target supports posix_memalign, 0 otherwise.
1201 proc check_effective_target_posix_memalign {} {
1202 if { [istarget *-*-vxworks*] } {
1203 # VxWorks doesn't have posix_memalign but our way to test
1204 # can't tell as we're doing partial links for kernel modules.
1207 return [check_function_available "posix_memalign"]
1210 # Return 1 if the target supports setrlimit, 0 otherwise.
1211 proc check_effective_target_setrlimit {} {
1212 # Darwin has non-posix compliant RLIMIT_AS
1213 if { [istarget *-*-darwin*] } {
1216 return [check_function_available "setrlimit"]
1219 # Return 1 if the target supports gettimeofday, 0 otherwise.
1220 proc check_effective_target_gettimeofday {} {
1221 return [check_function_available "gettimeofday"]
1224 # Return 1 if the target supports swapcontext, 0 otherwise.
1225 proc check_effective_target_swapcontext {} {
1226 return [check_no_compiler_messages swapcontext executable {
1227 #include <ucontext.h>
1230 ucontext_t orig_context,child_context;
1231 if (swapcontext(&child_context, &orig_context) < 0) { }
1236 # Return 1 if the target supports POSIX threads, 0 otherwise.
1237 proc check_effective_target_pthread {} {
1238 return [check_no_compiler_messages pthread object {
1239 #include <pthread.h>
1244 # Return 1 if the target supports both Unix and internet sockets, 0 otherwise.
1245 proc check_effective_target_sockets {} {
1246 return [check_no_compiler_messages socket executable {
1247 #include <sys/socket.h>
1249 #include <netinet/in.h>
1251 socket(AF_UNIX, SOCK_STREAM, 0);
1252 socket(AF_INET, SOCK_DGRAM, 0);
1258 # Return 1 if compilation with -mpe-aligned-commons is error-free
1259 # for trivial code, 0 otherwise.
1261 proc check_effective_target_pe_aligned_commons {} {
1262 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
1263 return [check_no_compiler_messages pe_aligned_commons object {
1265 } "-mpe-aligned-commons"]
1270 # Return 1 if the target supports -static
1271 proc check_effective_target_static {} {
1272 if { [istarget arm*-*-uclinuxfdpiceabi] } {
1275 return [check_no_compiler_messages static executable {
1276 int main (void) { return 0; }
1280 # Return 1 if the target supports -fstack-protector
1281 proc check_effective_target_fstack_protector {} {
1282 if { [istarget hppa*-*-*] } {
1285 return [check_runtime fstack_protector {
1287 int main (int argc, char *argv[]) {
1289 return !strcpy (buf, strrchr (argv[0], '/'));
1291 } "-fstack-protector"]
1294 # Return 1 if the target supports -fstack-check or -fstack-check=$stack_kind
1295 proc check_stack_check_available { stack_kind } {
1296 if [string match "" $stack_kind] then {
1297 set stack_opt "-fstack-check"
1298 } else { set stack_opt "-fstack-check=$stack_kind" }
1300 return [check_no_compiler_messages stack_check_$stack_kind executable {
1301 int main (void) { return 0; }
1305 # Return 1 if the target supports stack scrubbing.
1306 proc check_effective_target_strub {} {
1307 return [check_no_compiler_messages strub assembly {
1308 void __attribute__ ((__strub__)) fn (void) {}
1312 # Return 1 if compilation with -freorder-blocks-and-partition is error-free
1313 # for trivial code, 0 otherwise. As some targets (ARM for example) only
1314 # warn when -fprofile-use is also supplied we test that combination too.
1316 proc check_effective_target_freorder {} {
1317 if { [check_no_compiler_messages freorder object {
1319 } "-freorder-blocks-and-partition"]
1320 && [check_no_compiler_messages fprofile_use_freorder object {
1322 } "-fprofile-use -freorder-blocks-and-partition -Wno-missing-profile"] } {
1328 # Return 1 if -fpic and -fPIC are supported, as in no warnings or errors
1329 # emitted, 0 otherwise. Whether a shared library can actually be built is
1330 # out of scope for this test.
1332 proc check_effective_target_fpic { } {
1333 # Note that M68K has a multilib that supports -fpic but not
1334 # -fPIC, so we need to check both. We test with a program that
1335 # requires GOT references.
1336 foreach arg {fpic fPIC} {
1337 if [check_no_compiler_messages $arg object {
1338 extern int foo (void); extern int bar;
1339 int baz (void) { return foo () + bar; }
1347 # On AArch64, if -fpic is not supported, then we will fall back to -fPIC
1348 # silently. So, we can't rely on above "check_effective_target_fpic" as it
1349 # assumes compiler will give warning if -fpic not supported. Here we check
1350 # whether binutils supports those new -fpic relocation modifiers, and assume
1351 # -fpic is supported if there is binutils support. GCC configuration will
1352 # enable -fpic for AArch64 in this case.
1354 # "check_effective_target_aarch64_small_fpic" is dedicated for checking small
1355 # memory model -fpic relocation types.
1357 proc check_effective_target_aarch64_small_fpic { } {
1358 if { [istarget aarch64*-*-*] } {
1359 return [check_no_compiler_messages aarch64_small_fpic object {
1360 void foo (void) { asm ("ldr x0, [x2, #:gotpage_lo15:globalsym]"); }
1367 # On AArch64, instruction sequence for TLS LE under -mtls-size=32 will utilize
1368 # the relocation modifier "tprel_g0_nc" together with MOVK, it's only supported
1369 # in binutils since 2015-03-04 as PR gas/17843.
1371 # This test directive make sure binutils support all features needed by TLS LE
1372 # under -mtls-size=32 on AArch64.
1374 proc check_effective_target_aarch64_tlsle32 { } {
1375 if { [istarget aarch64*-*-*] } {
1376 return [check_no_compiler_messages aarch64_tlsle32 object {
1377 void foo (void) { asm ("movk x1,#:tprel_g0_nc:t1"); }
1384 # Return 1 if -shared is supported, as in no warnings or errors
1385 # emitted, 0 otherwise.
1387 proc check_effective_target_shared { } {
1388 # Note that M68K has a multilib that supports -fpic but not
1389 # -fPIC, so we need to check both. We test with a program that
1390 # requires GOT references, and with a libc symbol that would
1391 # bring in significant parts of a static-only libc. Absent a
1392 # shared libc, this would make -shared tests fail, so we don't
1393 # want to enable the shared effective target then.
1394 return [check_no_compiler_messages shared executable {
1396 extern int foo (void); extern int bar;
1398 return foo () + (char*) malloc (bar);
1403 # Return 1 if -pie, -fpie and -fPIE are supported, 0 otherwise.
1405 proc check_effective_target_pie { } {
1406 if { [istarget *-*-darwin\[912\]*]
1407 || [istarget *-*-dragonfly*]
1408 || [istarget *-*-freebsd*]
1409 || [istarget *-*-linux*]
1410 || [istarget arm*-*-uclinuxfdpiceabi]
1411 || [istarget *-*-gnu*]
1412 || [istarget *-*-amdhsa]} {
1415 if { [istarget *-*-solaris2.1\[1-9\]*] } {
1416 # Full PIE support was added in Solaris 11.3, but gcc errors out
1417 # if missing, so check for that.
1418 return [check_no_compiler_messages pie executable {
1419 int main (void) { return 0; }
1425 # Return true if the target supports -mpaired-single (as used on MIPS).
1427 proc check_effective_target_mpaired_single { args } {
1428 return [check_no_compiler_messages mpaired_single object {
1433 # Return true if the target has access to FPU instructions.
1435 proc check_effective_target_hard_float { } {
1436 # This should work on cores that only have single-precision,
1437 # and should also correctly handle legacy cores that had thumb1 and
1438 # lacked FP support for that, but had it in Arm state.
1439 if { [istarget arm*-*-*] } {
1440 return [check_no_compiler_messages hard_float assembly {
1442 #error __arm_soft_float
1447 if { [istarget loongarch*-*-*] } {
1448 return [check_no_compiler_messages hard_float assembly {
1449 #if (defined __loongarch_soft_float)
1450 #error __loongarch_soft_float
1455 if { [istarget mips*-*-*] } {
1456 return [check_no_compiler_messages hard_float assembly {
1457 #if (defined __mips_soft_float || defined __mips16)
1458 #error __mips_soft_float || __mips16
1463 # This proc is actually checking the availabilty of FPU
1464 # support for doubles, so on the RX we must fail if the
1465 # 64-bit double multilib has been selected.
1466 if { [istarget rx-*-*] } {
1468 # return [check_no_compiler_messages hard_float assembly {
1469 #if defined __RX_64_BIT_DOUBLES__
1470 #error __RX_64_BIT_DOUBLES__
1475 # The generic test doesn't work for C-SKY because some cores have
1476 # hard float for single precision only.
1477 if { [istarget csky*-*-*] } {
1478 return [check_no_compiler_messages hard_float assembly {
1479 #if defined __csky_soft_float__
1480 #error __csky_soft_float__
1485 # The generic test equates hard_float with "no call for adding doubles".
1486 return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
1487 double a (double b, double c) { return b + c; }
1491 # Return true if the target is a 64-bit MIPS target.
1493 proc check_effective_target_mips64 { } {
1494 return [check_no_compiler_messages mips64 assembly {
1501 # Return true if the target is a MIPS target that does not produce
1504 proc check_effective_target_nomips16 { } {
1505 return [check_no_compiler_messages nomips16 object {
1509 /* A cheap way of testing for -mflip-mips16. */
1510 void foo (void) { asm ("addiu $20,$20,1"); }
1511 void bar (void) { asm ("addiu $20,$20,1"); }
1516 # Add the options needed for MIPS16 function attributes. At the moment,
1517 # we don't support MIPS16 PIC.
1519 proc add_options_for_mips16_attribute { flags } {
1520 return "$flags -mno-abicalls -fno-pic -DMIPS16=__attribute__((mips16))"
1523 # Return true if we can force a mode that allows MIPS16 code generation.
1524 # We don't support MIPS16 PIC, and only support MIPS16 -mhard-float
1527 proc check_effective_target_mips16_attribute { } {
1528 return [check_no_compiler_messages mips16_attribute assembly {
1532 #if defined __mips_hard_float \
1533 && (!defined _ABIO32 || _MIPS_SIM != _ABIO32) \
1534 && (!defined _ABIO64 || _MIPS_SIM != _ABIO64)
1535 #error __mips_hard_float && (!_ABIO32 || !_ABIO64)
1537 } [add_options_for_mips16_attribute ""]]
1540 # Return 1 if the target supports long double larger than double when
1541 # using the new ABI, 0 otherwise.
1543 proc check_effective_target_mips_newabi_large_long_double { } {
1544 return [check_no_compiler_messages mips_newabi_large_long_double object {
1545 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
1549 # Return true if the target is a MIPS target that has access
1550 # to the LL and SC instructions.
1552 proc check_effective_target_mips_llsc { } {
1553 if { ![istarget mips*-*-*] } {
1556 # Assume that these instructions are always implemented for
1557 # non-elf* targets, via emulation if necessary.
1558 if { ![istarget *-*-elf*] } {
1561 # Otherwise assume LL/SC support for everything but MIPS I.
1562 return [check_no_compiler_messages mips_llsc assembly {
1569 # Return true if the target is a MIPS target that uses in-place relocations.
1571 proc check_effective_target_mips_rel { } {
1572 if { ![istarget mips*-*-*] } {
1575 return [check_no_compiler_messages mips_rel object {
1576 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1577 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1578 #error _ABIN32 && (_ABIN32 || _ABI64)
1583 # Return true if the target is a MIPS target that uses the EABI.
1585 proc check_effective_target_mips_eabi { } {
1586 if { ![istarget mips*-*-*] } {
1589 return [check_no_compiler_messages mips_eabi object {
1596 # Return 1 if the current multilib does not generate PIC by default.
1598 proc check_effective_target_nonpic { } {
1599 return [check_no_compiler_messages nonpic assembly {
1606 # Return 1 if the current multilib generates PIE by default.
1608 proc check_effective_target_pie_enabled { } {
1609 return [check_no_compiler_messages pie_enabled assembly {
1616 # Return 1 if the target generates -fstack-protector by default.
1618 proc check_effective_target_fstack_protector_enabled {} {
1619 return [ check_no_compiler_messages fstack_protector_enabled assembly {
1620 #if !defined(__SSP__) && !defined(__SSP_ALL__) && \
1621 !defined(__SSP_STRONG__) && !defined(__SSP_EXPICIT__)
1627 # Return 1 if the target does not use a status wrapper.
1629 proc check_effective_target_unwrapped { } {
1630 if { [target_info needs_status_wrapper] != "" \
1631 && [target_info needs_status_wrapper] != "0" } {
1637 # Return true if iconv is supported on the target. In particular IBM1047.
1639 proc check_iconv_available { test_what } {
1642 # If the tool configuration file has not set libiconv, try "-liconv"
1643 if { ![info exists libiconv] } {
1644 set libiconv "-liconv"
1646 set test_what [lindex $test_what 1]
1647 return [check_runtime_nocache $test_what [subst {
1653 cd = iconv_open ("$test_what", "UTF-8");
1654 if (cd == (iconv_t) -1)
1661 # Return true if the atomic library is supported on the target.
1662 proc check_effective_target_libatomic_available { } {
1663 return [check_no_compiler_messages libatomic_available executable {
1664 int main (void) { return 0; }
1668 # Return 1 if an ASCII locale is supported on this host, 0 otherwise.
1670 proc check_ascii_locale_available { } {
1674 # Return true if named sections are supported on this target.
1676 proc check_named_sections_available { } {
1677 return [check_no_compiler_messages named_sections assembly {
1678 int __attribute__ ((section("whatever"))) foo;
1682 # Return true if the "naked" function attribute is supported on this target.
1684 proc check_effective_target_naked_functions { } {
1685 return [check_no_compiler_messages naked_functions assembly {
1686 void f() __attribute__((naked));
1690 # Return 1 if the target supports Fortran real kinds larger than real(8),
1693 # When the target name changes, replace the cached result.
1695 proc check_effective_target_fortran_large_real { } {
1696 return [check_no_compiler_messages fortran_large_real executable {
1698 integer,parameter :: k = selected_real_kind (precision (0.0_8) + 1)
1705 # Return 1 if the target supports Fortran real kind real(16),
1706 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1707 # this checks for Real(16) only; the other returned real(10) if
1708 # both real(10) and real(16) are available.
1710 # When the target name changes, replace the cached result.
1712 proc check_effective_target_fortran_real_16 { } {
1713 return [check_no_compiler_messages fortran_real_16 executable {
1721 # Return 1 if the target supports Fortran real kind 10,
1722 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1723 # this checks for real(10) only.
1725 # When the target name changes, replace the cached result.
1727 proc check_effective_target_fortran_real_10 { } {
1728 return [check_no_compiler_messages fortran_real_10 executable {
1736 # Return 1 if the target supports Fortran real kind C_FLOAT128,
1737 # 0 otherwise. This differs from check_effective_target_fortran_real_16
1738 # because _Float128 has the additional requirement that it be the
1739 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
1740 # have a corresponding Fortran kind on targets (PowerPC) that use some
1741 # other encoding for long double/TFmode/real(16).
1742 proc check_effective_target_fortran_real_c_float128 { } {
1743 return [check_no_compiler_messages fortran_real_c_float128 executable {
1746 real(kind=c_float128) :: x
1752 # Return 1 if the target supports Fortran's IEEE modules,
1755 # When the target name changes, replace the cached result.
1757 proc check_effective_target_fortran_ieee { flags } {
1758 return [check_no_compiler_messages fortran_ieee executable {
1760 use, intrinsic :: ieee_features
1766 # Return 1 if the target supports SQRT for the largest floating-point
1767 # type. (Some targets lack the libm support for this FP type.)
1768 # On most targets, this check effectively checks either whether sqrtl is
1769 # available or on __float128 systems whether libquadmath is installed,
1770 # which provides sqrtq.
1772 # When the target name changes, replace the cached result.
1774 proc check_effective_target_fortran_largest_fp_has_sqrt { } {
1775 return [check_no_compiler_messages fortran_largest_fp_has_sqrt executable {
1777 use iso_fortran_env, only: real_kinds
1778 integer,parameter:: maxFP = real_kinds(ubound(real_kinds,dim=1))
1779 real(kind=maxFP), volatile :: x
1787 # Return 1 if the target supports Fortran integer kinds larger than
1788 # integer(8), 0 otherwise.
1790 # When the target name changes, replace the cached result.
1792 proc check_effective_target_fortran_large_int { } {
1793 return [check_no_compiler_messages fortran_large_int executable {
1795 integer,parameter :: k = selected_int_kind (range (0_8) + 1)
1796 integer(kind=k) :: i
1801 # Return 1 if the target supports Fortran integer(16), 0 otherwise.
1803 # When the target name changes, replace the cached result.
1805 proc check_effective_target_fortran_integer_16 { } {
1806 return [check_no_compiler_messages fortran_integer_16 executable {
1813 # Return 1 if we can statically link libgfortran, 0 otherwise.
1815 # When the target name changes, replace the cached result.
1817 proc check_effective_target_static_libgfortran { } {
1818 return [check_no_compiler_messages static_libgfortran executable {
1825 # Return 1 if we can use the -rdynamic option, 0 otherwise.
1827 proc check_effective_target_rdynamic { } {
1828 return [check_no_compiler_messages rdynamic executable {
1829 int main() { return 0; }
1833 proc check_linker_plugin_available { } {
1834 return [check_no_compiler_messages_nocache linker_plugin executable {
1835 int main() { return 0; }
1836 } "-flto -fuse-linker-plugin"]
1839 # Return 1 if the target is RV32, 0 otherwise. Cache the result.
1841 proc check_effective_target_rv32 { } {
1842 # Check that we are compiling for RV32 by checking the xlen size.
1843 return [check_no_compiler_messages riscv_rv32 assembly {
1844 #if !defined(__riscv_xlen)
1845 #error "__riscv_xlen not defined!"
1847 #if __riscv_xlen != 32
1854 # Return 1 if the target is RV64, 0 otherwise. Cache the result.
1856 proc check_effective_target_rv64 { } {
1857 # Check that we are compiling for RV64 by checking the xlen size.
1858 return [check_no_compiler_messages riscv_rv64 assembly {
1859 #if !defined(__riscv_xlen)
1860 #error "__riscv_xlen not defined!"
1862 #if __riscv_xlen != 64
1869 # Return 1 if the target abi is __riscv_float_abi_soft, 0 otherwise.
1872 proc check_effective_target_rv_float_abi_soft { } {
1873 # Check that we are compiling for RV64 by checking the xlen size.
1874 return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly {
1875 #ifndef __riscv_float_abi_soft
1876 #error "Not __riscv_float_abi_soft"
1881 # Return 1 if the target arch supports the atomic extension, 0 otherwise.
1884 proc check_effective_target_riscv_a { } {
1885 return [check_no_compiler_messages riscv_ext_a assembly {
1887 #error "Not __riscv_a"
1892 # Return 1 if the target arch supports the double precision floating point
1893 # extension, 0 otherwise. Cache the result.
1895 proc check_effective_target_riscv_d { } {
1896 return [check_no_compiler_messages riscv_ext_d assembly {
1898 #error "Not __riscv_d"
1903 # Return 1 if the target arch supports the vector extension, 0 otherwise.
1906 proc check_effective_target_riscv_v { } {
1907 return [check_no_compiler_messages riscv_ext_v assembly {
1909 #error "Not __riscv_v"
1914 # Return 1 if the target arch supports the Zvfh extension, 0 otherwise.
1917 proc check_effective_target_riscv_zvfh { } {
1918 return [check_no_compiler_messages riscv_ext_zvfh assembly {
1919 #ifndef __riscv_zvfh
1920 #error "Not __riscv_zvfh"
1925 # Return 1 if the target arch supports half float, 0 otherwise.
1926 # Note, this differs from the test performed by
1927 # /* dg-skip-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */
1928 # in that it takes default behaviour into account.
1931 proc check_effective_target_riscv_zfh { } {
1932 return [check_no_compiler_messages riscv_ext_zfh assembly {
1934 #error "Not __riscv_zfh"
1939 # Return 1 if the target arch supports the TSO memory ordering extension,
1940 # 0 otherwise. Cache the result.
1942 proc check_effective_target_riscv_ztso { } {
1943 return [check_no_compiler_messages riscv_ext_ztso assembly {
1944 #ifndef __riscv_ztso
1945 #error "Not __riscv_ztso"
1950 # Return 1 if the target arch supports the Zbb extension, 0 otherwise.
1953 proc check_effective_target_riscv_zbb { } {
1954 return [check_no_compiler_messages riscv_ext_zbb assembly {
1956 #error "Not __riscv_zbb"
1961 # Return 1 if the target arch supports the XTheadVector extension, 0 otherwise.
1964 proc check_effective_target_riscv_xtheadvector { } {
1965 return [check_no_compiler_messages riscv_ext_xtheadvector assembly {
1966 #ifndef __riscv_xtheadvector
1967 #error "Not __riscv_xtheadvector"
1973 # Return 1 if we can execute code when using dg-add-options riscv_v
1975 proc check_effective_target_riscv_v_ok { } {
1976 # If the target already supports v without any added options,
1977 # we may assume we can execute just fine.
1978 if { [check_effective_target_riscv_v] } {
1982 # check if we can execute vector insns with the given hardware or
1984 set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
1985 if { [check_runtime ${gcc_march}_exec {
1986 int main() { asm("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } {
1990 # Possible future extensions: If the target is a simulator, dg-add-options
1991 # might change its config to make it allow vector insns, or we might use
1992 # options to set special elf flags / sections to effect that.
1997 # Return 1 if we can execute code when using dg-add-options riscv_zfh
1999 proc check_effective_target_riscv_zfh_ok { } {
2000 # If the target already supports zfh without any added options,
2001 # we may assume we can execute just fine.
2002 # ??? Other cases we should consider:
2003 # - target / simulator already supports zfh extension - test for that.
2004 # - target is a simulator, and dg-add-options knows how to enable zfh support in that simulator
2005 if { [check_effective_target_riscv_zfh] } {
2009 # check if we can execute zfh insns with the given hardware or
2011 set gcc_march [riscv_get_arch]
2012 if { [check_runtime ${gcc_march}_zfh_exec {
2013 int main() { asm("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } {
2017 # Possible future extensions: If the target is a simulator, dg-add-options
2018 # might change its config to make it allow half float insns, or we might
2019 # use options to set special elf flags / sections to effect that.
2024 # Return 1 if we can execute code when using dg-add-options riscv_zvfh
2026 proc check_effective_target_riscv_zvfh_ok { } {
2027 # If the target already supports v without any added options,
2028 # we may assume we can execute just fine.
2029 if { [check_effective_target_riscv_zvfh] } {
2033 # check if we can execute vector insns with the given hardware or
2035 set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
2036 if { [check_runtime ${gcc_march}_exec {
2039 asm ("vsetivli zero,8,e16,m1,ta,ma");
2040 asm ("vfadd.vv v8,v8,v16" : : : "v8");
2042 } } "-march=${gcc_march}"] } {
2049 proc riscv_get_arch { } {
2051 # ??? do we neeed to add more extensions to the list below?
2052 foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso } {
2053 if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
2058 if { [string length $ext] > 1 } {
2061 set gcc_march $gcc_march$ext
2063 if { [string equal $gcc_march "imafd"] } {
2067 if { [check_effective_target_rv32] } {
2068 set gcc_march rv32$gcc_march
2069 } elseif { [check_effective_target_rv64] } {
2070 set gcc_march rv64$gcc_march
2077 proc add_options_for_riscv_a { flags } {
2078 if { [lsearch $flags -march=*] >= 0 } {
2079 # If there are multiple -march flags, we have to adjust all of them.
2080 set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ]
2081 return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1a ]
2083 if { [check_effective_target_riscv_a] } {
2086 return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]"
2089 proc add_options_for_riscv_d { flags } {
2090 if { [lsearch $flags -march=*] >= 0 } {
2091 # If there are multiple -march flags, we have to adjust all of them.
2092 return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ]
2094 if { [check_effective_target_riscv_d] } {
2097 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]"
2100 proc add_options_for_riscv_v { flags } {
2101 if { [lsearch $flags -march=*] >= 0 } {
2102 # If there are multiple -march flags, we have to adjust all of them.
2103 return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1v ]
2105 if { [check_effective_target_riscv_v] } {
2108 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
2111 proc add_options_for_riscv_zfh { flags } {
2112 if { [lsearch $flags -march=*] >= 0 } {
2113 # If there are multiple -march flags, we have to adjust all of them.
2114 set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zfh ]
2115 return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zfh[[:alnum:]_.]*)_zfh} $flags \\1 ]
2117 if { [check_effective_target_riscv_zfh] } {
2120 return "$flags -march=[riscv_get_arch]_zfh"
2123 proc add_options_for_riscv_ztso { flags } {
2124 if { [lsearch $flags -march=*] >= 0 } {
2125 # If there are multiple -march flags, we have to adjust all of them.
2126 set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_ztso ]
2127 return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_ztso[[:alnum:]_.]*)_ztso} $flags \\1 ]
2129 if { [check_effective_target_riscv_ztso] } {
2132 return "$flags -march=[riscv_get_arch]_ztso"
2135 proc add_options_for_riscv_zvfh { flags } {
2136 if { [lsearch $flags -march=*] >= 0 } {
2137 # If there are multiple -march flags, we have to adjust all of them.
2138 set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvfh ]
2139 return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvfh[[:alnum:]_.]*)_zvfh} $flags \\1 ]
2141 if { [check_effective_target_riscv_zvfh] } {
2144 return "$flags -march=[riscv_get_arch]_zvfh"
2147 # Return 1 if the target OS supports running SSE executables, 0
2148 # otherwise. Cache the result.
2150 proc check_sse_os_support_available { } {
2151 return [check_cached_effective_target sse_os_support_available {
2152 # If this is not the right target then we can skip the test.
2153 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2161 # Return 1 if the target OS supports running AVX executables, 0
2162 # otherwise. Cache the result.
2164 proc check_avx_os_support_available { } {
2165 return [check_cached_effective_target avx_os_support_available {
2166 # If this is not the right target then we can skip the test.
2167 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2170 # Check that OS has AVX and SSE saving enabled.
2171 check_runtime_nocache avx_os_support_available {
2174 unsigned int eax, edx;
2176 asm ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2177 return (eax & 0x06) != 0x06;
2184 # Return 1 if the target OS supports running AVX executables, 0
2185 # otherwise. Cache the result.
2187 proc check_avx512_os_support_available { } {
2188 return [check_cached_effective_target avx512_os_support_available {
2189 # If this is not the right target then we can skip the test.
2190 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2193 # Check that OS has AVX512, AVX and SSE saving enabled.
2194 check_runtime_nocache avx512_os_support_available {
2197 unsigned int eax, edx;
2199 asm ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2200 return (eax & 0xe6) != 0xe6;
2207 # Return 1 if the target supports executing SSE instructions, 0
2208 # otherwise. Cache the result.
2210 proc check_sse_hw_available { } {
2211 return [check_cached_effective_target sse_hw_available {
2212 # If this is not the right target then we can skip the test.
2213 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2216 check_runtime_nocache sse_hw_available {
2220 unsigned int eax, ebx, ecx, edx;
2221 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2224 return !(edx & bit_SSE);
2231 # Return 1 if the target supports executing SSE2 instructions, 0
2232 # otherwise. Cache the result.
2234 proc check_sse2_hw_available { } {
2235 return [check_cached_effective_target sse2_hw_available {
2236 # If this is not the right target then we can skip the test.
2237 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2240 check_runtime_nocache sse2_hw_available {
2244 unsigned int eax, ebx, ecx, edx;
2245 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2248 return !(edx & bit_SSE2);
2255 # Return 1 if the target supports executing SSE4 instructions, 0
2256 # otherwise. Cache the result.
2258 proc check_sse4_hw_available { } {
2259 return [check_cached_effective_target sse4_hw_available {
2260 # If this is not the right target then we can skip the test.
2261 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2264 check_runtime_nocache sse4_hw_available {
2268 unsigned int eax, ebx, ecx, edx;
2269 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2272 return !(ecx & bit_SSE4_2);
2279 # Return 1 if the target supports executing AVX instructions, 0
2280 # otherwise. Cache the result.
2282 proc check_avx_hw_available { } {
2283 return [check_cached_effective_target avx_hw_available {
2284 # If this is not the right target then we can skip the test.
2285 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2288 check_runtime_nocache avx_hw_available {
2292 unsigned int eax, ebx, ecx, edx;
2293 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2296 return ((ecx & (bit_AVX | bit_OSXSAVE))
2297 != (bit_AVX | bit_OSXSAVE));
2304 # Return 1 if the target supports executing AVX2 instructions, 0
2305 # otherwise. Cache the result.
2307 proc check_avx2_hw_available { } {
2308 return [check_cached_effective_target avx2_hw_available {
2309 # If this is not the right target then we can skip the test.
2310 if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
2313 check_runtime_nocache avx2_hw_available {
2318 unsigned int eax, ebx, ecx, edx;
2320 if (__get_cpuid_max (0, NULL) < 7)
2323 __cpuid (1, eax, ebx, ecx, edx);
2325 if (!(ecx & bit_OSXSAVE))
2328 __cpuid_count (7, 0, eax, ebx, ecx, edx);
2330 return !(ebx & bit_AVX2);
2337 # Return 1 if the target supports executing AVX512 foundation instructions, 0
2338 # otherwise. Cache the result.
2340 proc check_avx512f_hw_available { } {
2341 return [check_cached_effective_target avx512f_hw_available {
2342 # If this is not the right target then we can skip the test.
2343 if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
2346 check_runtime_nocache avx512f_hw_available {
2351 unsigned int eax, ebx, ecx, edx;
2353 if (__get_cpuid_max (0, NULL) < 7)
2356 __cpuid (1, eax, ebx, ecx, edx);
2358 if (!(ecx & bit_OSXSAVE))
2361 __cpuid_count (7, 0, eax, ebx, ecx, edx);
2363 return !(ebx & bit_AVX512F);
2370 # Return 1 if the target supports running SSE executables, 0 otherwise.
2372 proc check_effective_target_sse_runtime { } {
2373 if { [check_effective_target_sse]
2374 && [check_sse_hw_available]
2375 && [check_sse_os_support_available] } {
2381 # Return 1 if the target supports running SSE2 executables, 0 otherwise.
2383 proc check_effective_target_sse2_runtime { } {
2384 if { [check_effective_target_sse2]
2385 && [check_sse2_hw_available]
2386 && [check_sse_os_support_available] } {
2392 # Return 1 if the target supports running SSE4 executables, 0 otherwise.
2394 proc check_effective_target_sse4_runtime { } {
2395 if { [check_effective_target_sse4]
2396 && [check_sse4_hw_available]
2397 && [check_sse_os_support_available] } {
2403 # Return 1 if the target supports running AVX executables, 0 otherwise.
2405 proc check_effective_target_avx_runtime { } {
2406 if { [check_effective_target_avx]
2407 && [check_avx_hw_available]
2408 && [check_avx_os_support_available] } {
2414 # Return 1 if the target supports running AVX2 executables, 0 otherwise.
2416 proc check_effective_target_avx2_runtime { } {
2417 if { [check_effective_target_avx2]
2418 && [check_avx2_hw_available]
2419 && [check_avx_os_support_available] } {
2425 # Return 1 if the target supports running AVX512f executables, 0 otherwise.
2427 proc check_effective_target_avx512f_runtime { } {
2428 if { [check_effective_target_avx512f]
2429 && [check_avx512f_hw_available]
2430 && [check_avx512_os_support_available] } {
2436 # Return 1 if bmi2 instructions can be compiled.
2437 proc check_effective_target_bmi2 { } {
2438 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
2441 return [check_no_compiler_messages bmi2 object {
2443 _bzhi_u32 (unsigned int __X, unsigned int __Y)
2445 return __builtin_ia32_bzhi_si (__X, __Y);
2450 # Return 1 if the target supports executing MIPS Paired-Single instructions,
2451 # 0 otherwise. Cache the result.
2453 proc check_mpaired_single_hw_available { } {
2454 return [check_cached_effective_target mpaired_single_hw_available {
2455 # If this is not the right target then we can skip the test.
2456 if { !([istarget mips*-*-*]) } {
2459 check_runtime_nocache mpaired_single_hw_available {
2462 asm volatile ("pll.ps $f2,$f4,$f6");
2470 # Return 1 if the target supports executing Loongson vector instructions,
2471 # 0 otherwise. Cache the result.
2473 proc check_mips_loongson_mmi_hw_available { } {
2474 return [check_cached_effective_target mips_loongson_mmi_hw_available {
2475 # If this is not the right target then we can skip the test.
2476 if { !([istarget mips*-*-*]) } {
2479 check_runtime_nocache mips_loongson_mmi_hw_available {
2480 #include <loongson-mmiintrin.h>
2483 asm volatile ("paddw $f2,$f4,$f6");
2491 # Return 1 if the target supports executing MIPS MSA instructions, 0
2492 # otherwise. Cache the result.
2494 proc check_mips_msa_hw_available { } {
2495 return [check_cached_effective_target mips_msa_hw_available {
2496 # If this is not the right target then we can skip the test.
2497 if { !([istarget mips*-*-*]) } {
2500 check_runtime_nocache mips_msa_hw_available {
2501 #if !defined(__mips_msa)
2502 #error "MSA NOT AVAIL"
2504 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
2505 #error "MSA NOT AVAIL FOR ISA REV < 2"
2507 #if !defined(__mips_hard_float)
2508 #error "MSA HARD_FLOAT REQUIRED"
2510 #if __mips_fpr != 64
2511 #error "MSA 64-bit FPR REQUIRED"
2517 v8i16 v = __builtin_msa_ldi_h (0);
2527 # Return 1 if the target supports running MIPS Paired-Single
2528 # executables, 0 otherwise.
2530 proc check_effective_target_mpaired_single_runtime { } {
2531 if { [check_effective_target_mpaired_single "-mpaired-single"]
2532 && [check_mpaired_single_hw_available] } {
2538 # Return 1 if the target supports running Loongson executables, 0 otherwise.
2540 proc check_effective_target_mips_loongson_mmi_runtime { } {
2541 if { [check_effective_target_mips_loongson_mmi "-mloongson-mmi"]
2542 && [check_mips_loongson_mmi_hw_available] } {
2548 # Return 1 if the target supports running MIPS MSA executables, 0 otherwise.
2550 proc check_effective_target_mips_msa_runtime { } {
2551 if { [check_effective_target_mips_msa "-mmsa"]
2552 && [check_mips_msa_hw_available] } {
2558 # Return 1 if we are compiling for 64-bit PowerPC but we do not use direct
2559 # move instructions for moves from GPR to FPR.
2561 proc check_effective_target_powerpc64_no_dm { } {
2562 # The "mulld" checks if we are generating PowerPC64 code. The "lfd"
2563 # checks if we do not use direct moves, but use the old-fashioned
2564 # slower move-via-the-stack.
2565 return [check_no_messages_and_pattern powerpc64_no_dm \
2566 {\mmulld\M.*\mlfd} assembly {
2567 double f(long long x) { return x*x; }
2571 # Return 1 if the target supports the __builtin_cpu_supports built-in,
2572 # including having a new enough library to support the test. Cache the result.
2573 # Require at least a power7 to run on.
2575 proc check_ppc_cpu_supports_hw_available { } {
2576 return [check_cached_effective_target ppc_cpu_supports_hw_available {
2577 # Some simulators are known to not support VSX/power8 instructions.
2578 # For now, disable on Darwin
2579 if { [istarget powerpc-*-eabi]
2580 || [istarget powerpc*-*-eabispe]
2581 || [istarget *-*-darwin*]} {
2585 check_runtime_nocache ppc_cpu_supports_hw_available {
2589 asm volatile ("xxlor vs0,vs0,vs0");
2591 asm volatile ("xxlor 0,0,0");
2593 if (!__builtin_cpu_supports ("vsx"))
2602 # Return 1 if the target supports executing 750CL paired-single instructions, 0
2603 # otherwise. Cache the result.
2605 proc check_750cl_hw_available { } {
2606 return [check_cached_effective_target 750cl_hw_available {
2607 # If this is not the right target then we can skip the test.
2608 if { ![istarget powerpc-*paired*] } {
2611 check_runtime_nocache 750cl_hw_available {
2615 asm volatile ("ps_mul v0,v0,v0");
2617 asm volatile ("ps_mul 0,0,0");
2626 # Return 1 if the target supports executing power8 vector instructions, 0
2627 # otherwise. Cache the result.
2629 proc check_p8vector_hw_available { } {
2630 return [check_cached_effective_target p8vector_hw_available {
2631 # Some simulators are known to not support VSX/power8 instructions.
2632 # For now, disable on Darwin
2633 if { [istarget powerpc-*-eabi]
2634 || [istarget powerpc*-*-eabispe]
2635 || [istarget *-*-darwin*]} {
2638 set options "-mpower8-vector"
2639 check_runtime_nocache p8vector_hw_available {
2643 asm volatile ("xxlorc vs0,vs0,vs0");
2645 asm volatile ("xxlorc 0,0,0");
2654 # Return 1 if the target supports executing power9 vector instructions, 0
2655 # otherwise. Cache the result.
2657 proc check_p9vector_hw_available { } {
2658 return [check_cached_effective_target p9vector_hw_available {
2659 # Some simulators are known to not support VSX/power8/power9
2660 # instructions. For now, disable on Darwin.
2661 if { [istarget powerpc-*-eabi]
2662 || [istarget powerpc*-*-eabispe]
2663 || [istarget *-*-darwin*]} {
2666 set options "-mpower9-vector"
2667 check_runtime_nocache p9vector_hw_available {
2671 vector double v = (vector double) { 0.0, 0.0 };
2672 asm ("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
2680 # Return 1 if the PowerPC target generates PC-relative instructions
2681 # automatically for targets that support PC-relative instructions.
2682 proc check_effective_target_powerpc_pcrel { } {
2683 return [check_no_messages_and_pattern powerpc_pcrel \
2684 {\mpla\M} assembly {
2685 static unsigned short s;
2686 unsigned short *p_foo (void) { return &s; }
2687 } {-O2 -mcpu=power10}]
2690 # Return 1 if the PowerPC target generates prefixed instructions automatically
2691 # for targets that support prefixed instructions.
2692 proc check_effective_target_powerpc_prefixed_addr { } {
2693 return [check_no_messages_and_pattern powerpc_prefixed_addr \
2694 {\mplwz\M} assembly {
2695 unsigned int foo (unsigned int *p) { return p[0x12345]; }
2696 } {-O2 -mcpu=power10}]
2699 # Return 1 if the target supports executing power9 modulo instructions, 0
2700 # otherwise. Cache the result.
2702 proc check_p9modulo_hw_available { } {
2703 return [check_cached_effective_target p9modulo_hw_available {
2704 # Some simulators are known to not support VSX/power8/power9
2705 # instructions. For now, disable on Darwin.
2706 if { [istarget powerpc-*-eabi]
2707 || [istarget powerpc*-*-eabispe]
2708 || [istarget *-*-darwin*]} {
2711 set options "-mmodulo"
2712 check_runtime_nocache p9modulo_hw_available {
2715 int i = 5, j = 3, r = -1;
2716 asm ("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
2725 # Return 1 if the target supports executing power10 instructions, 0 otherwise.
2726 # Cache the result. It is assumed that if a simulator does not support the
2727 # power10 instructions, that it will generate an error and this test will fail.
2729 proc check_power10_hw_available { } {
2730 return [check_cached_effective_target power10_hw_available {
2731 check_runtime_nocache power10_hw_available {
2734 /* Set e first and use +r to check if pli actually works. */
2736 asm ("pli %0,%1" : "+r" (e) : "n" (0x12345));
2745 # Return 1 if the target supports executing MMA instructions, 0 otherwise.
2746 # Cache the result. It is assumed that if a simulator does not support the
2747 # MMA instructions, that it will generate an error and this test will fail.
2749 proc check_ppc_mma_hw_available { } {
2750 return [check_cached_effective_target ppc_mma_hw_available {
2751 check_runtime_nocache ppc_mma_hw_available {
2752 #include <altivec.h>
2753 typedef double v4sf_t __attribute__ ((vector_size (16)));
2760 __builtin_mma_xxsetaccz (&acc0);
2761 __builtin_mma_disassemble_acc (result, &acc0);
2762 if (result[0][0] != 0.0)
2770 # Return 1 if the target supports executing __float128 on PowerPC via software
2771 # emulation, 0 otherwise. Cache the result.
2773 proc check_ppc_float128_sw_available { } {
2774 return [check_cached_effective_target ppc_float128_sw_available {
2775 # Some simulators are known to not support VSX/power8/power9
2776 # instructions. For now, disable on Darwin and VxWorks.
2777 if { [istarget *-*-vxworks*]
2778 || [istarget powerpc-*-eabi]
2779 || [istarget powerpc*-*-eabispe]
2780 || [istarget *-*-darwin*]} {
2783 set options "-mfloat128 -mvsx"
2784 check_runtime_nocache ppc_float128_sw_available {
2785 volatile __float128 x = 1.0q;
2786 volatile __float128 y = 2.0q;
2789 __float128 z = x + y;
2797 # Return 1 if the target supports executing __float128 on PowerPC via power9
2798 # hardware instructions, 0 otherwise. Cache the result.
2800 proc check_ppc_float128_hw_available { } {
2801 return [check_cached_effective_target ppc_float128_hw_available {
2802 # Some simulators are known to not support VSX/power8/power9
2803 # instructions. For now, disable on Darwin.
2804 if { [istarget *-*-vxworks*]
2805 || [istarget powerpc-*-eabi]
2806 || [istarget powerpc*-*-eabispe]
2807 || [istarget *-*-darwin*]} {
2810 set options "-mfloat128 -mvsx -mfloat128-hardware -mpower9-vector"
2811 check_runtime_nocache ppc_float128_hw_available {
2812 volatile __float128 x = 1.0q;
2813 volatile __float128 y = 2.0q;
2816 __float128 z = x + y;
2817 __float128 w = -1.0q;
2819 __asm__ ("xsaddqp %0,%1,%2" : "+v" (w) : "v" (x), "v" (y));
2820 return ((z != 3.0q) || (z != w));
2827 # See if the __ieee128 keyword is understood.
2828 proc check_effective_target_ppc_ieee128_ok { } {
2829 return [check_cached_effective_target ppc_ieee128_ok {
2830 # disable on AIX and VxWorks.
2831 if { [istarget *-*-aix*]
2832 || [istarget *-*-vxworks*]} {
2835 set options "-mfloat128"
2836 check_runtime_nocache ppc_ieee128_ok {
2847 # Check if GCC and GLIBC supports explicitly specifying that the long double
2848 # format uses the IBM 128-bit extended double format. Under little endian
2849 # PowerPC Linux, you need GLIBC 2.32 or later to be able to use a different
2850 # long double format for running a program than the system default.
2852 proc check_effective_target_long_double_ibm128 { } {
2853 return [check_runtime_nocache long_double_ibm128 {
2856 /* use volatile to prevent optimization. */
2857 volatile __ibm128 a = (__ibm128) 3.0;
2858 volatile long double one = 1.0L;
2859 volatile long double two = 2.0L;
2860 volatile long double b;
2866 if (sizeof (long double) != 16)
2869 /* eliminate removing volatile cast warning. */
2872 if (memcmp (&a2, &b2, 16) != 0)
2874 sprintf (buffer, "%lg", b);
2875 return strcmp (buffer, "3") != 0;
2877 } [add_options_for_long_double_ibm128 ""]]
2880 # Return the appropriate options to specify that long double uses the IBM
2881 # 128-bit format on PowerPC.
2883 proc add_options_for_long_double_ibm128 { flags } {
2884 if { [istarget powerpc*-*-*] } {
2885 return "$flags -mlong-double-128 -Wno-psabi -mabi=ibmlongdouble"
2890 # Check if GCC and GLIBC supports explicitly specifying that the long double
2891 # format uses the IEEE 128-bit format. Under little endian PowerPC Linux, you
2892 # need GLIBC 2.32 or later to be able to use a different long double format for
2893 # running a program than the system default.
2895 proc check_effective_target_long_double_ieee128 { } {
2896 return [check_runtime_nocache long_double_ieee128 {
2899 /* use volatile to prevent optimization. */
2900 volatile _Float128 a = 3.0f128;
2901 volatile long double one = 1.0L;
2902 volatile long double two = 2.0L;
2903 volatile long double b;
2909 if (sizeof (long double) != 16)
2912 /* eliminate removing volatile cast warning. */
2915 if (memcmp (&a2, &b2, 16) != 0)
2917 sprintf (buffer, "%lg", b);
2918 return strcmp (buffer, "3") != 0;
2920 } [add_options_for_long_double_ieee128 ""]]
2923 # Return the appropriate options to specify that long double uses the IBM
2924 # 128-bit format on PowerPC.
2925 proc add_options_for_long_double_ieee128 { flags } {
2926 if { [istarget powerpc*-*-*] } {
2927 return "$flags -mlong-double-128 -Wno-psabi -mabi=ieeelongdouble"
2932 # Check if GCC and GLIBC supports explicitly specifying that the long double
2933 # format uses the IEEE 64-bit. Under little endian PowerPC Linux, you need
2934 # GLIBC 2.32 or later to be able to use a different long double format for
2935 # running a program than the system default.
2937 proc check_effective_target_long_double_64bit { } {
2938 return [check_runtime_nocache long_double_64bit {
2941 /* use volatile to prevent optimization. */
2942 volatile double a = 3.0;
2943 volatile long double one = 1.0L;
2944 volatile long double two = 2.0L;
2945 volatile long double b;
2951 if (sizeof (long double) != 8)
2954 /* eliminate removing volatile cast warning. */
2957 if (memcmp (&a2, &b2, 16) != 0)
2959 sprintf (buffer, "%lg", b);
2960 return strcmp (buffer, "3") != 0;
2962 } [add_options_for_ppc_long_double_override_64bit ""]]
2965 # Return the appropriate options to specify that long double uses the IEEE
2966 # 64-bit format on PowerPC.
2968 proc add_options_for_long_double_64bit { flags } {
2969 if { [istarget powerpc*-*-*] } {
2970 return "$flags -mlong-double-64"
2975 # Return 1 if the target supports executing VSX instructions, 0
2976 # otherwise. Cache the result.
2978 proc check_vsx_hw_available { } {
2979 return [check_cached_effective_target vsx_hw_available {
2980 # Some simulators are known to not support VSX instructions.
2981 # For now, disable on Darwin
2982 if { [istarget powerpc-*-eabi]
2983 || [istarget powerpc*-*-eabispe]
2984 || [istarget *-*-darwin*]} {
2988 check_runtime_nocache vsx_hw_available {
2992 asm volatile ("xxlor vs0,vs0,vs0");
2994 asm volatile ("xxlor 0,0,0");
3003 # Return 1 if the target supports executing AltiVec instructions, 0
3004 # otherwise. Cache the result.
3006 proc check_vmx_hw_available { } {
3007 return [check_cached_effective_target vmx_hw_available {
3008 # Some simulators are known to not support VMX instructions.
3009 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] } {
3012 # Most targets don't require special flags for this test case, but
3013 # Darwin does. Just to be sure, make sure VSX is not enabled for
3014 # the altivec tests.
3015 if { [istarget *-*-darwin*]
3016 || [istarget *-*-aix*] } {
3017 set options "-maltivec -mno-vsx"
3019 set options "-mno-vsx"
3021 check_runtime_nocache vmx_hw_available {
3025 asm volatile ("vor v0,v0,v0");
3027 asm volatile ("vor 0,0,0");
3036 proc check_ppc_recip_hw_available { } {
3037 return [check_cached_effective_target ppc_recip_hw_available {
3038 # Some simulators may not support FRE/FRES/FRSQRTE/FRSQRTES
3039 # For now, disable on Darwin
3040 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3043 set options "-mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb"
3044 check_runtime_nocache ppc_recip_hw_available {
3045 volatile double d_recip, d_rsqrt, d_four = 4.0;
3046 volatile float f_recip, f_rsqrt, f_four = 4.0f;
3049 asm volatile ("fres %0,%1" : "=f" (f_recip) : "f" (f_four));
3050 asm volatile ("fre %0,%1" : "=d" (d_recip) : "d" (d_four));
3051 asm volatile ("frsqrtes %0,%1" : "=f" (f_rsqrt) : "f" (f_four));
3052 asm volatile ("frsqrte %0,%1" : "=f" (d_rsqrt) : "d" (d_four));
3060 # Return 1 if the target supports executing AltiVec and Cell PPU
3061 # instructions, 0 otherwise. Cache the result.
3063 proc check_effective_target_cell_hw { } {
3064 return [check_cached_effective_target cell_hw_available {
3065 # Some simulators are known to not support VMX and PPU instructions.
3066 if { [istarget powerpc-*-eabi*] } {
3069 # Most targets don't require special flags for this test
3070 # case, but Darwin and AIX do.
3071 if { [istarget *-*-darwin*]
3072 || [istarget *-*-aix*] } {
3073 set options "-maltivec -mcpu=cell"
3075 set options "-mcpu=cell"
3077 check_runtime_nocache cell_hw_available {
3081 asm volatile ("vor v0,v0,v0");
3082 asm volatile ("lvlx v0,r0,r0");
3084 asm volatile ("vor 0,0,0");
3085 asm volatile ("lvlx 0,0,0");
3094 # Return 1 if the target supports executing 64-bit instructions, 0
3095 # otherwise. Cache the result.
3097 proc check_effective_target_powerpc64 { } {
3098 global powerpc64_available_saved
3101 if [info exists powerpc64_available_saved] {
3102 verbose "check_effective_target_powerpc64 returning saved $powerpc64_available_saved" 2
3104 set powerpc64_available_saved 0
3106 # Some simulators are known to not support powerpc64 instructions.
3107 if { [istarget powerpc-*-eabi*] || [istarget powerpc-ibm-aix*] } {
3108 verbose "check_effective_target_powerpc64 returning 0" 2
3109 return $powerpc64_available_saved
3112 # Set up, compile, and execute a test program containing a 64-bit
3113 # instruction. Include the current process ID in the file
3114 # names to prevent conflicts with invocations for multiple
3119 set f [open $src "w"]
3120 puts $f "int main() {"
3121 puts $f "#ifdef __MACH__"
3122 puts $f " asm volatile (\"extsw r0,r0\");"
3124 puts $f " asm volatile (\"extsw 0,0\");"
3126 puts $f " return 0; }"
3129 set opts "additional_flags=-mcpu=G5"
3131 verbose "check_effective_target_powerpc64 compiling testfile $src" 2
3132 set lines [${tool}_target_compile $src $exe executable "$opts"]
3135 if [string match "" $lines] then {
3136 # No error message, compilation succeeded.
3137 set result [${tool}_load "./$exe" "" ""]
3138 set status [lindex $result 0]
3139 remote_file build delete $exe
3140 verbose "check_effective_target_powerpc64 testfile status is <$status>" 2
3142 if { $status == "pass" } then {
3143 set powerpc64_available_saved 1
3146 verbose "check_effective_target_powerpc64 testfile compilation failed" 2
3150 return $powerpc64_available_saved
3153 # GCC 3.4.0 for powerpc64-*-linux* included an ABI fix for passing
3154 # complex float arguments. This affects gfortran tests that call cabsf
3155 # in libm built by an earlier compiler. Return 0 if libm uses the same
3156 # argument passing as the compiler under test, 1 otherwise.
3158 proc check_effective_target_broken_cplxf_arg { } {
3159 # Skip the work for targets known not to be affected.
3160 if { ![istarget powerpc*-*-linux*] || ![is-effective-target lp64] } {
3164 return [check_cached_effective_target broken_cplxf_arg {
3165 check_runtime_nocache broken_cplxf_arg {
3166 #include <complex.h>
3167 extern void abort (void);
3168 float fabsf (float);
3169 float cabsf (_Complex float);
3176 if (fabsf (f - 5.0) > 0.0001)
3177 /* Yes, it's broken. */
3179 /* All fine, not broken. */
3186 # Return 1 is this is a TI C6X target supporting C67X instructions
3187 proc check_effective_target_ti_c67x { } {
3188 return [check_no_compiler_messages ti_c67x assembly {
3189 #if !defined(_TMS320C6700)
3190 #error !_TMS320C6700
3195 # Return 1 is this is a TI C6X target supporting C64X+ instructions
3196 proc check_effective_target_ti_c64xp { } {
3197 return [check_no_compiler_messages ti_c64xp assembly {
3198 #if !defined(_TMS320C6400_PLUS)
3199 #error !_TMS320C6400_PLUS
3204 # Check if a -march=... option is given, as part of (earlier) options.
3205 proc check_effective_target_march_option { } {
3206 return [check-flags [list "" { *-*-* } { "-march=*" } { "" } ]]
3209 proc check_alpha_max_hw_available { } {
3210 return [check_runtime alpha_max_hw_available {
3211 int main() { return __builtin_alpha_amask(1<<8) != 0; }
3215 # Returns true iff the FUNCTION is available on the target system.
3216 # (This is essentially a Tcl implementation of Autoconf's
3219 proc check_function_available { function } {
3220 return [check_no_compiler_messages ${function}_available \
3226 int main () { $function (); }
3230 # Returns true iff "fork" is available on the target system.
3232 proc check_fork_available {} {
3233 if { [istarget *-*-vxworks*] } {
3234 # VxWorks doesn't have fork but our way to test can't
3235 # tell as we're doing partial links for kernel modules.
3238 if { [istarget cris-*-*] } {
3239 # Compiling and linking works, and an executable running e.g.
3240 # gcc.dg/torture/ftrapv-1.c works on now-historical hardware,
3241 # but the GNU simulator emits an error for the fork syscall.
3242 return [check_effective_target_hw]
3244 return [check_function_available "fork"]
3247 # Returns true iff "mkfifo" is available on the target system.
3249 proc check_mkfifo_available {} {
3250 if { [istarget *-*-cygwin*] } {
3251 # Cygwin has mkfifo, but support is incomplete.
3255 return [check_function_available "mkfifo"]
3258 # Returns true iff "__cxa_atexit" is used on the target system.
3260 proc check_cxa_atexit_available { } {
3261 return [check_cached_effective_target cxa_atexit_available {
3262 if { [istarget *-*-vxworks] } {
3263 # vxworks doesn't have __cxa_atexit but subsequent test passes.
3266 check_runtime_nocache cxa_atexit_available {
3269 static unsigned int count;
3286 Y() { f(); count = 2; }
3295 int main() { return 0; }
3301 proc check_effective_target_objc2 { } {
3302 return [check_no_compiler_messages objc2 object {
3311 proc check_effective_target_next_runtime { } {
3312 return [check_no_compiler_messages objc2 object {
3313 #ifdef __NEXT_RUNTIME__
3316 #error !__NEXT_RUNTIME__
3321 # Return 1 if we're generating code for big-endian memory order.
3323 proc check_effective_target_be { } {
3324 return [check_no_compiler_messages be object {
3325 int dummy[__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ? 1 : -1];
3329 # Return 1 if we're generating code for little-endian memory order.
3331 proc check_effective_target_le { } {
3332 return [check_no_compiler_messages le object {
3333 int dummy[__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ? 1 : -1];
3337 # Return 1 if we can link a program with 2+GB of data.
3339 proc check_effective_target_two_plus_gigs { } {
3340 return [check_no_compiler_messages two_plus_gigs executable {
3341 char dummy[0x80000000];
3342 int main () { return 0; }
3346 # Return 1 if we're generating 32-bit code using default options, 0
3349 proc check_effective_target_ilp32 { } {
3350 return [check_no_compiler_messages ilp32 object {
3351 int dummy[sizeof (int) == 4
3352 && sizeof (void *) == 4
3353 && sizeof (long) == 4 ? 1 : -1];
3357 # Return 1 if we're generating ia32 code using default options, 0
3360 proc check_effective_target_ia32 { } {
3361 return [check_no_compiler_messages ia32 object {
3362 int dummy[sizeof (int) == 4
3363 && sizeof (void *) == 4
3364 && sizeof (long) == 4 ? 1 : -1] = { __i386__ };
3368 # Return 1 if we're generating x32 code using default options, 0
3371 proc check_effective_target_x32 { } {
3372 return [check_no_compiler_messages x32 object {
3373 int dummy[sizeof (int) == 4
3374 && sizeof (void *) == 4
3375 && sizeof (long) == 4 ? 1 : -1] = { __x86_64__ };
3379 # Return 1 if we're generating 32-bit integers using default
3380 # options, 0 otherwise.
3382 proc check_effective_target_int32 { } {
3383 return [check_no_compiler_messages int32 object {
3384 int dummy[sizeof (int) == 4 ? 1 : -1];
3388 # Return 1 if we're generating 32-bit or larger integers using default
3389 # options, 0 otherwise.
3391 proc check_effective_target_int32plus { } {
3392 return [check_no_compiler_messages int32plus object {
3393 int dummy[sizeof (int) >= 4 ? 1 : -1];
3397 # Return 1 if we're generating 64-bit long long using default options,
3400 proc check_effective_target_longlong64 { } {
3401 return [check_no_compiler_messages longlong64 object {
3402 int dummy[sizeof (long long) == 8 ? 1 : -1];
3406 # Return 1 if we're generating 32-bit or larger pointers using default
3407 # options, 0 otherwise.
3409 proc check_effective_target_ptr32plus { } {
3410 # The msp430 has 16-bit or 20-bit pointers. The 20-bit pointer is stored
3411 # in a 32-bit slot when in memory, so sizeof(void *) returns 4, but it
3412 # cannot really hold a 32-bit address, so we always return false here.
3413 if { [istarget msp430-*-*] } {
3417 return [check_no_compiler_messages ptr32plus object {
3418 int dummy[sizeof (void *) >= 4 ? 1 : -1];
3422 # Return 1 if we support 16-bit or larger array and structure sizes
3423 # using default options, 0 otherwise.
3424 # This implies at least a 20-bit address space, as no targets have an address
3425 # space between 16 and 20 bits.
3427 proc check_effective_target_size20plus { } {
3428 return [check_no_compiler_messages size20plus object {
3433 # Return 1 if target supports function pointers, 0 otherwise.
3435 proc check_effective_target_function_pointers { } {
3436 if { [istarget pru-*-*] } {
3437 return [check_no_compiler_messages func_ptr_avail assembly {
3438 #ifdef __PRU_EABI_GNU__
3446 # Return 1 if target supports arbitrarily large return values, 0 otherwise.
3448 proc check_effective_target_large_return_values { } {
3449 if { [istarget pru-*-*] } {
3450 return [check_no_compiler_messages large_return_values assembly {
3451 #ifdef __PRU_EABI_GNU__
3458 # Return 1 if we support 20-bit or larger array and structure sizes
3459 # using default options, 0 otherwise.
3460 # This implies at least a 24-bit address space, as no targets have an address
3461 # space between 20 and 24 bits.
3463 proc check_effective_target_size24plus { } {
3464 return [check_no_compiler_messages size24plus object {
3465 char dummy[524289L];
3469 # Return 1 if we support 24-bit or larger array and structure sizes
3470 # using default options, 0 otherwise.
3471 # This implies at least a 32-bit address space, as no targets have an address
3472 # space between 24 and 32 bits.
3474 proc check_effective_target_size32plus { } {
3475 return [check_no_compiler_messages size32plus object {
3476 char dummy[16777217L];
3480 # Returns 1 if we're generating 16-bit or smaller integers with the
3481 # default options, 0 otherwise.
3483 proc check_effective_target_int16 { } {
3484 return [check_no_compiler_messages int16 object {
3485 int dummy[sizeof (int) < 4 ? 1 : -1];
3489 # Return 1 if we're generating 64-bit code using default options, 0
3492 proc check_effective_target_lp64 { } {
3493 return [check_no_compiler_messages lp64 object {
3494 int dummy[sizeof (int) == 4
3495 && sizeof (void *) == 8
3496 && sizeof (long) == 8 ? 1 : -1];
3500 # Return 1 if we're generating 64-bit code using default llp64 options,
3503 proc check_effective_target_llp64 { } {
3504 return [check_no_compiler_messages llp64 object {
3505 int dummy[sizeof (int) == 4
3506 && sizeof (void *) == 8
3507 && sizeof (long long) == 8
3508 && sizeof (long) == 4 ? 1 : -1];
3512 # Return 1 if long and int have different sizes,
3515 proc check_effective_target_long_neq_int { } {
3516 return [check_no_compiler_messages long_ne_int object {
3517 int dummy[sizeof (int) != sizeof (long) ? 1 : -1];
3521 # Return 1 if int size is equal to float size,
3524 proc check_effective_target_int_eq_float { } {
3525 return [check_no_compiler_messages int_eq_float object {
3526 int dummy[sizeof (int) >= sizeof (float) ? 1 : -1];
3530 # Return 1 if short size is equal to int size,
3533 proc check_effective_target_short_eq_int { } {
3534 return [check_no_compiler_messages short_eq_int object {
3535 int dummy[sizeof (short) == sizeof (int) ? 1 : -1];
3539 # Return 1 if pointer size is equal to short size,
3542 proc check_effective_target_ptr_eq_short { } {
3543 return [check_no_compiler_messages ptr_eq_short object {
3544 int dummy[sizeof (void *) == sizeof (short) ? 1 : -1];
3548 # Return 1 if pointer size is equal to long size,
3551 proc check_effective_target_ptr_eq_long { } {
3552 # sizeof (void *) == 4 for msp430-elf -mlarge which is equal to
3553 # sizeof (long). Avoid false positive.
3554 if { [istarget msp430-*-*] } {
3557 return [check_no_compiler_messages ptr_eq_long object {
3558 int dummy[sizeof (void *) == sizeof (long) ? 1 : -1];
3562 # Return 1 if the target supports long double larger than double,
3565 proc check_effective_target_large_long_double { } {
3566 return [check_no_compiler_messages large_long_double object {
3567 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
3571 # Return 1 if the target supports double larger than float,
3574 proc check_effective_target_large_double { } {
3575 return [check_no_compiler_messages large_double object {
3576 int dummy[sizeof(double) > sizeof(float) ? 1 : -1];
3580 # Return 1 if the target supports long double of 128 bits,
3583 proc check_effective_target_longdouble128 { } {
3584 return [check_no_compiler_messages longdouble128 object {
3585 int dummy[sizeof(long double) == 16 ? 1 : -1];
3589 # Return 1 if the target supports long double of 64 bits,
3592 proc check_effective_target_longdouble64 { } {
3593 return [check_no_compiler_messages longdouble64 object {
3594 int dummy[sizeof(long double) == 8 ? 1 : -1];
3598 # Return 1 if the target supports double of 64 bits,
3601 proc check_effective_target_double64 { } {
3602 return [check_no_compiler_messages double64 object {
3603 int dummy[sizeof(double) == 8 ? 1 : -1];
3607 # Return 1 if the target supports double of at least 64 bits,
3610 proc check_effective_target_double64plus { } {
3611 return [check_no_compiler_messages double64plus object {
3612 int dummy[sizeof(double) >= 8 ? 1 : -1];
3616 # Return 1 if the target supports 'w' suffix on floating constant
3619 proc check_effective_target_has_w_floating_suffix { } {
3621 if [check_effective_target_c++] {
3622 append opts "-std=gnu++03"
3624 return [check_no_compiler_messages w_fp_suffix object {
3629 # Return 1 if the target supports 'q' suffix on floating constant
3632 proc check_effective_target_has_q_floating_suffix { } {
3634 if [check_effective_target_c++] {
3635 append opts "-std=gnu++03"
3637 return [check_no_compiler_messages q_fp_suffix object {
3642 # Return 1 if the target supports the _FloatN / _FloatNx type
3643 # indicated in the function name, 0 otherwise.
3645 proc check_effective_target_float16 {} {
3646 return [check_no_compiler_messages_nocache float16 object {
3647 _Float16 foo (_Float16 x) { return x; }
3648 } [add_options_for_float16 ""]]
3651 proc check_effective_target_float32 {} {
3652 return [check_no_compiler_messages_nocache float32 object {
3654 } [add_options_for_float32 ""]]
3657 proc check_effective_target_float64 {} {
3658 return [check_no_compiler_messages_nocache float64 object {
3660 } [add_options_for_float64 ""]]
3663 proc check_effective_target_float128 {} {
3664 return [check_no_compiler_messages_nocache float128 object {
3666 } [add_options_for_float128 ""]]
3669 proc check_effective_target_float32x {} {
3670 return [check_no_compiler_messages_nocache float32x object {
3672 } [add_options_for_float32x ""]]
3675 proc check_effective_target_float64x {} {
3676 return [check_no_compiler_messages_nocache float64x object {
3678 } [add_options_for_float64x ""]]
3681 proc check_effective_target_float128x {} {
3682 return [check_no_compiler_messages_nocache float128x object {
3684 } [add_options_for_float128x ""]]
3687 # Likewise, but runtime support for any special options used as well
3688 # as compile-time support is required.
3690 proc check_effective_target_float16_runtime {} {
3691 return [check_effective_target_float16]
3694 proc check_effective_target_float32_runtime {} {
3695 return [check_effective_target_float32]
3698 proc check_effective_target_float64_runtime {} {
3699 return [check_effective_target_float64]
3702 proc check_effective_target_float128_runtime {} {
3703 if { ![check_effective_target_float128] } {
3706 if { [istarget powerpc*-*-*] } {
3707 return [check_effective_target_base_quadfloat_support]
3712 proc check_effective_target_float32x_runtime {} {
3713 return [check_effective_target_float32x]
3716 proc check_effective_target_float64x_runtime {} {
3717 if { ![check_effective_target_float64x] } {
3720 if { [istarget powerpc*-*-*] } {
3721 return [check_effective_target_base_quadfloat_support]
3726 proc check_effective_target_float128x_runtime {} {
3727 return [check_effective_target_float128x]
3730 # Return 1 if the target hardware supports any options added for
3731 # _FloatN and _FloatNx types, 0 otherwise.
3733 proc check_effective_target_floatn_nx_runtime {} {
3734 if { [istarget powerpc*-*-aix*] } {
3737 if { [istarget powerpc*-*-*] } {
3738 return [check_effective_target_base_quadfloat_support]
3743 # Add options needed to use the _FloatN / _FloatNx type indicated in
3744 # the function name.
3746 proc add_options_for_float16 { flags } {
3747 if { [istarget arm*-*-*] } {
3748 return "$flags -mfp16-format=ieee"
3750 if { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
3751 return "$flags -msse2"
3756 proc add_options_for_float32 { flags } {
3760 proc add_options_for_float64 { flags } {
3764 proc add_options_for_float128 { flags } {
3765 return [add_options_for___float128 "$flags"]
3768 proc add_options_for_float32x { flags } {
3772 proc add_options_for_float64x { flags } {
3773 return [add_options_for___float128 "$flags"]
3776 proc add_options_for_float128x { flags } {
3780 # Return 1 if the target supports __float128,
3783 proc check_effective_target___float128 { } {
3784 if { [istarget powerpc*-*-*] } {
3785 return [check_ppc_float128_sw_available]
3787 if { [istarget ia64-*-*]
3788 || [istarget i?86-*-*] || [istarget x86_64-*-*] } {
3794 proc add_options_for___float128 { flags } {
3795 if { [istarget powerpc*-*-linux*] } {
3796 return "$flags -mfloat128 -mvsx"
3801 # Return 1 if the target supports any special run-time requirements
3802 # for __float128 or _Float128,
3805 proc check_effective_target_base_quadfloat_support { } {
3806 if { [istarget powerpc*-*-*] } {
3807 return [check_vsx_hw_available]
3812 # Return 1 if the target supports the __bf16 type, 0 otherwise.
3814 proc check_effective_target_bfloat16 {} {
3815 return [check_no_compiler_messages_nocache bfloat16 object {
3816 __bf16 foo (__bf16 x) { return x + x; }
3817 } [add_options_for_bfloat16 ""]]
3820 proc check_effective_target_bfloat16_runtime {} {
3821 return [check_effective_target_bfloat16]
3824 proc add_options_for_bfloat16 { flags } {
3828 # Return 1 if the target supports all four forms of fused multiply-add
3829 # (fma, fms, fnma, and fnms) for both float and double.
3831 proc check_effective_target_scalar_all_fma { } {
3832 if { [istarget aarch64*-*-*]
3833 || [istarget loongarch*-*-*]} {
3839 # Return 1 if the target supports compiling fixed-point,
3842 proc check_effective_target_fixed_point { } {
3843 return [check_no_compiler_messages fixed_point object {
3844 _Sat _Fract x; _Sat _Accum y;
3848 # Return 1 if the target supports _BitInt(N), 0 otherwise.
3850 proc check_effective_target_bitint { } {
3851 return [check_no_compiler_messages bitint object {
3852 _BitInt (2) a = 1wb;
3853 unsigned _BitInt (__BITINT_MAXWIDTH__) b = 0uwb;
3857 # Return 1 if the target supports _BitInt(128), 0 otherwise.
3859 proc check_effective_target_bitint128 { } {
3860 return [check_no_compiler_messages bitint128 object {
3861 _BitInt (2) a = 1wb;
3862 unsigned _BitInt (128) b = 0uwb;
3866 # Return 1 if the target supports _BitInt(575), 0 otherwise.
3868 proc check_effective_target_bitint575 { } {
3869 return [check_no_compiler_messages bitint575 object {
3870 _BitInt (2) a = 1wb;
3871 unsigned _BitInt (575) b = 0uwb;
3875 # Return 1 if the target supports _BitInt(65535), 0 otherwise.
3877 proc check_effective_target_bitint65535 { } {
3878 return [check_no_compiler_messages bitint65535 object {
3879 _BitInt (2) a = 1wb;
3880 unsigned _BitInt (65535) b = 0uwb;
3884 # Return 1 if the target supports compiling decimal floating point,
3887 proc check_effective_target_dfp_nocache { } {
3888 verbose "check_effective_target_dfp_nocache: compiling source" 2
3889 set ret [check_no_compiler_messages_nocache dfp object {
3890 float x __attribute__((mode(DD)));
3892 verbose "check_effective_target_dfp_nocache: returning $ret" 2
3896 proc check_effective_target_dfprt_nocache { } {
3897 return [check_runtime_nocache dfprt {
3898 typedef float d64 __attribute__((mode(DD)));
3899 d64 x = 1.2df, y = 2.3dd, z;
3900 int main () { z = x + y; return 0; }
3904 # Return 1 if the target supports compiling Decimal Floating Point,
3907 # This won't change for different subtargets so cache the result.
3909 proc check_effective_target_dfp { } {
3910 return [check_cached_effective_target dfp {
3911 check_effective_target_dfp_nocache
3915 # Return 1 if the target supports linking and executing Decimal Floating
3916 # Point, 0 otherwise.
3918 # This won't change for different subtargets so cache the result.
3920 proc check_effective_target_dfprt { } {
3921 return [check_cached_effective_target dfprt {
3922 check_effective_target_dfprt_nocache
3926 # Return 1 if the target uses the BID format for Decimal Floating
3927 # Point, 0 otherwise.
3929 proc check_effective_target_dfp_bid { } {
3930 if { [istarget aarch64*-*-*]
3931 || [istarget i?86-*-*] || [istarget x86_64-*-*]} {
3937 # Return 1 iff target has unsigned plain 'char' by default.
3939 proc check_effective_target_unsigned_char {} {
3940 return [check_no_compiler_messages unsigned_char assembly {
3945 proc check_effective_target_powerpc_popcntb_ok { } {
3946 return [check_cached_effective_target powerpc_popcntb_ok {
3948 # Disable on Darwin.
3949 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3952 check_runtime_nocache powerpc_popcntb_ok {
3954 volatile int a = 0x12345678;
3957 asm volatile ("popcntb %0,%1" : "=r" (r) : "r" (a));
3965 # Return 1 if the target supports executing DFP hardware instructions,
3966 # 0 otherwise. Cache the result.
3968 proc check_dfp_hw_available { } {
3969 return [check_cached_effective_target dfp_hw_available {
3970 # For now, disable on Darwin
3971 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3974 check_runtime_nocache dfp_hw_available {
3975 volatile _Decimal64 r;
3976 volatile _Decimal64 a = 4.0DD;
3977 volatile _Decimal64 b = 2.0DD;
3980 asm volatile ("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3981 asm volatile ("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3982 asm volatile ("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3983 asm volatile ("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3986 } "-mcpu=power6 -mhard-float"
3991 # Return 1 if the target supports compiling and assembling UCN, 0 otherwise.
3993 proc check_effective_target_ucn_nocache { } {
3994 # -std=c99 is only valid for C
3995 if [check_effective_target_c] {
3996 set ucnopts "-std=c99"
4000 verbose "check_effective_target_ucn_nocache: compiling source" 2
4001 set ret [check_no_compiler_messages_nocache ucn object {
4004 verbose "check_effective_target_ucn_nocache: returning $ret" 2
4008 # Return 1 if the target supports compiling and assembling UCN, 0 otherwise.
4010 # This won't change for different subtargets, so cache the result.
4012 proc check_effective_target_ucn { } {
4013 return [check_cached_effective_target ucn {
4014 check_effective_target_ucn_nocache
4018 # Return 1 if the target needs a command line argument to enable a SIMD
4021 proc check_effective_target_vect_cmdline_needed { } {
4022 global et_vect_cmdline_needed_target_name
4024 if { ![info exists et_vect_cmdline_needed_target_name] } {
4025 set et_vect_cmdline_needed_target_name ""
4028 # If the target has changed since we set the cached value, clear it.
4029 set current_target [current_target_name]
4030 if { $current_target != $et_vect_cmdline_needed_target_name } {
4031 verbose "check_effective_target_vect_cmdline_needed: `$et_vect_cmdline_needed_target_name' `$current_target'" 2
4032 set et_vect_cmdline_needed_target_name $current_target
4033 if { [info exists et_vect_cmdline_needed_saved] } {
4034 verbose "check_effective_target_vect_cmdline_needed: removing cached result" 2
4035 unset et_vect_cmdline_needed_saved
4039 return [check_cached_effective_target vect_cmdline_needed {
4040 if { [istarget alpha*-*-*]
4041 || [istarget ia64-*-*]
4042 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
4043 && ![is-effective-target ia32])
4044 || ([istarget powerpc*-*-*]
4045 && ([check_effective_target_powerpc_spe]
4046 || [check_effective_target_powerpc_altivec]))
4047 || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
4048 || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
4049 || [istarget aarch64*-*-*]
4050 || [istarget amdgcn*-*-*]
4051 || [istarget riscv*-*-*]} {
4058 # Return 1 if the target supports hardware vectors of int, 0 otherwise.
4060 # This won't change for different subtargets so cache the result.
4062 proc check_effective_target_vect_int { } {
4063 return [check_cached_effective_target_indexed vect_int {
4065 [istarget i?86-*-*] || [istarget x86_64-*-*]
4066 || ([istarget powerpc*-*-*]
4067 && ![istarget powerpc-*-linux*paired*])
4068 || [istarget amdgcn-*-*]
4069 || [istarget sparc*-*-*]
4070 || [istarget alpha*-*-*]
4071 || [istarget ia64-*-*]
4072 || [istarget aarch64*-*-*]
4073 || [is-effective-target arm_neon]
4074 || ([istarget mips*-*-*]
4075 && ([et-is-effective-target mips_loongson_mmi]
4076 || [et-is-effective-target mips_msa]))
4077 || ([istarget s390*-*-*]
4078 && [check_effective_target_s390_vx])
4079 || ([istarget riscv*-*-*]
4080 && [check_effective_target_riscv_v])
4081 || ([istarget loongarch*-*-*]
4082 && [check_effective_target_loongarch_sx])
4086 # Return 1 if the target supports vectorization of early breaks,
4089 # This won't change for different subtargets so cache the result.
4091 proc check_effective_target_vect_early_break { } {
4092 return [check_cached_effective_target_indexed vect_early_break {
4094 [istarget aarch64*-*-*]
4095 || [check_effective_target_arm_v8_neon_ok]
4096 || [check_effective_target_sse4]
4100 # Return 1 if the target supports hardware execution of early breaks,
4103 # This won't change for different subtargets so cache the result.
4105 proc check_effective_target_vect_early_break_hw { } {
4106 return [check_cached_effective_target_indexed vect_early_break_hw {
4108 [istarget aarch64*-*-*]
4109 || [check_effective_target_arm_v8_neon_hw]
4110 || [check_sse4_hw_available]
4114 proc add_options_for_vect_early_break { flags } {
4115 if { ! [check_effective_target_vect_early_break] } {
4119 if { [check_effective_target_arm_v8_neon_ok] } {
4120 global et_arm_v8_neon_flags
4121 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4124 if { [check_effective_target_sse4] } {
4125 return "$flags -msse4.1"
4131 # Return 1 if the target supports hardware vectorization of complex additions of
4132 # byte, 0 otherwise.
4134 # This won't change for different subtargets so cache the result.
4136 proc check_effective_target_vect_complex_add_byte { } {
4137 return [check_cached_effective_target_indexed vect_complex_add_byte {
4139 ([check_effective_target_aarch64_sve2]
4140 && [check_effective_target_aarch64_little_endian])
4141 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4142 && [check_effective_target_arm_little_endian])
4146 # Return 1 if the target supports hardware vectorization of complex additions of
4147 # short, 0 otherwise.
4149 # This won't change for different subtargets so cache the result.
4151 proc check_effective_target_vect_complex_add_short { } {
4152 return [check_cached_effective_target_indexed vect_complex_add_short {
4154 ([check_effective_target_aarch64_sve2]
4155 && [check_effective_target_aarch64_little_endian])
4156 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4157 && [check_effective_target_arm_little_endian])
4161 # Return 1 if the target supports hardware vectorization of complex additions of
4164 # This won't change for different subtargets so cache the result.
4166 proc check_effective_target_vect_complex_add_int { } {
4167 return [check_cached_effective_target_indexed vect_complex_add_int {
4169 ([check_effective_target_aarch64_sve2]
4170 && [check_effective_target_aarch64_little_endian])
4171 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4172 && [check_effective_target_arm_little_endian])
4176 # Return 1 if the target supports hardware vectorization of complex additions of
4177 # long, 0 otherwise.
4179 # This won't change for different subtargets so cache the result.
4181 proc check_effective_target_vect_complex_add_long { } {
4182 return [check_cached_effective_target_indexed vect_complex_add_long {
4184 ([check_effective_target_aarch64_sve2]
4185 && [check_effective_target_aarch64_little_endian])
4186 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4187 && [check_effective_target_arm_little_endian])
4191 # Return 1 if the target supports hardware vectorization of complex additions of
4192 # half, 0 otherwise.
4194 # This won't change for different subtargets so cache the result.
4196 proc check_effective_target_vect_complex_add_half { } {
4197 return [check_cached_effective_target_indexed vect_complex_add_half {
4199 ([check_effective_target_arm_v8_3a_fp16_complex_neon_ok]
4200 && ([check_effective_target_aarch64_little_endian]
4201 || [check_effective_target_arm_little_endian]))
4202 || ([check_effective_target_aarch64_sve2]
4203 && [check_effective_target_aarch64_little_endian])
4204 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4205 && [check_effective_target_arm_little_endian])
4209 # Return 1 if the target supports hardware vectorization of complex additions of
4210 # float, 0 otherwise.
4212 # This won't change for different subtargets so cache the result.
4214 proc check_effective_target_vect_complex_add_float { } {
4215 return [check_cached_effective_target_indexed vect_complex_add_float {
4217 ([check_effective_target_arm_v8_3a_complex_neon_ok]
4218 && ([check_effective_target_aarch64_little_endian]
4219 || [check_effective_target_arm_little_endian]))
4220 || ([check_effective_target_aarch64_sve2]
4221 && [check_effective_target_aarch64_little_endian])
4222 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4223 && [check_effective_target_arm_little_endian])
4227 # Return 1 if the target supports hardware vectorization of complex additions of
4228 # double, 0 otherwise.
4230 # This won't change for different subtargets so cache the result.
4232 proc check_effective_target_vect_complex_add_double { } {
4233 return [check_cached_effective_target_indexed vect_complex_add_double {
4235 (([check_effective_target_arm_v8_3a_complex_neon_ok]
4236 && [check_effective_target_aarch64_little_endian])
4237 || ([check_effective_target_aarch64_sve2]
4238 && [check_effective_target_aarch64_little_endian]))
4242 # Return 1 if the target supports signed int->float conversion
4245 proc check_effective_target_vect_intfloat_cvt { } {
4246 return [check_cached_effective_target_indexed vect_intfloat_cvt {
4247 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4248 || ([istarget powerpc*-*-*]
4249 && ![istarget powerpc-*-linux*paired*])
4250 || [is-effective-target arm_neon]
4251 || ([istarget mips*-*-*]
4252 && [et-is-effective-target mips_msa])
4253 || [istarget amdgcn-*-*]
4254 || ([istarget s390*-*-*]
4255 && [check_effective_target_s390_vxe2])
4256 || ([istarget riscv*-*-*]
4257 && [check_effective_target_riscv_v])
4258 || ([istarget loongarch*-*-*]
4259 && [check_effective_target_loongarch_sx]) }}]
4262 # Return 1 if the target supports signed double->int conversion
4265 proc check_effective_target_vect_doubleint_cvt { } {
4266 return [check_cached_effective_target_indexed vect_doubleint_cvt {
4267 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4268 && [check_no_compiler_messages vect_doubleint_cvt assembly {
4269 #ifdef __tune_atom__
4270 # error No double vectorizer support.
4273 || [istarget aarch64*-*-*]
4274 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4275 || ([istarget mips*-*-*]
4276 && [et-is-effective-target mips_msa])
4277 || ([istarget s390*-*-*]
4278 && [check_effective_target_s390_vx])
4279 || ([istarget riscv*-*-*]
4280 && [check_effective_target_riscv_v])
4281 || ([istarget loongarch*-*-*]
4282 && [check_effective_target_loongarch_sx]) }}]
4285 # Return 1 if the target supports signed int->double conversion
4288 proc check_effective_target_vect_intdouble_cvt { } {
4289 return [check_cached_effective_target_indexed vect_intdouble_cvt {
4290 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4291 && [check_no_compiler_messages vect_intdouble_cvt assembly {
4292 #ifdef __tune_atom__
4293 # error No double vectorizer support.
4296 || [istarget aarch64*-*-*]
4297 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4298 || ([istarget mips*-*-*]
4299 && [et-is-effective-target mips_msa])
4300 || ([istarget s390*-*-*]
4301 && [check_effective_target_s390_vx])
4302 || ([istarget riscv*-*-*]
4303 && [check_effective_target_riscv_v])
4304 || ([istarget loongarch*-*-*]
4305 && [check_effective_target_loongarch_sx]) }}]
4308 #Return 1 if we're supporting __int128 for target, 0 otherwise.
4310 proc check_effective_target_int128 { } {
4311 return [check_no_compiler_messages int128 object {
4313 #ifndef __SIZEOF_INT128__
4322 # Return 1 if the target supports unsigned int->float conversion
4325 proc check_effective_target_vect_uintfloat_cvt { } {
4326 return [check_cached_effective_target_indexed vect_uintfloat_cvt {
4327 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4328 || ([istarget powerpc*-*-*]
4329 && ![istarget powerpc-*-linux*paired*])
4330 || [istarget aarch64*-*-*]
4331 || [is-effective-target arm_neon]
4332 || ([istarget mips*-*-*]
4333 && [et-is-effective-target mips_msa])
4334 || [istarget amdgcn-*-*]
4335 || ([istarget s390*-*-*]
4336 && [check_effective_target_s390_vxe2])
4337 || ([istarget riscv*-*-*]
4338 && [check_effective_target_riscv_v])
4339 || ([istarget loongarch*-*-*]
4340 && [check_effective_target_loongarch_sx]) }}]
4344 # Return 1 if the target supports signed float->int conversion
4347 proc check_effective_target_vect_floatint_cvt { } {
4348 return [check_cached_effective_target_indexed vect_floatint_cvt {
4349 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4350 || ([istarget powerpc*-*-*]
4351 && ![istarget powerpc-*-linux*paired*])
4352 || [is-effective-target arm_neon]
4353 || ([istarget mips*-*-*]
4354 && [et-is-effective-target mips_msa])
4355 || [istarget amdgcn-*-*]
4356 || ([istarget s390*-*-*]
4357 && [check_effective_target_s390_vxe2])
4358 || ([istarget riscv*-*-*]
4359 && [check_effective_target_riscv_v])
4360 || ([istarget loongarch*-*-*]
4361 && [check_effective_target_loongarch_sx]) }}]
4364 # Return 1 if the target supports unsigned float->int conversion
4367 proc check_effective_target_vect_floatuint_cvt { } {
4368 return [check_cached_effective_target_indexed vect_floatuint_cvt {
4369 expr { ([istarget powerpc*-*-*]
4370 && ![istarget powerpc-*-linux*paired*])
4371 || [is-effective-target arm_neon]
4372 || ([istarget mips*-*-*]
4373 && [et-is-effective-target mips_msa])
4374 || [istarget amdgcn-*-*]
4375 || ([istarget s390*-*-*]
4376 && [check_effective_target_s390_vxe2])
4377 || ([istarget riscv*-*-*]
4378 && [check_effective_target_riscv_v])
4379 || ([istarget loongarch*-*-*]
4380 && [check_effective_target_loongarch_sx]) }}]
4383 # Return 1 if the target supports vector integer char -> long long extend optab
4386 proc check_effective_target_vect_ext_char_longlong { } {
4387 return [check_cached_effective_target_indexed vect_ext_char_longlong {
4388 expr { ([istarget riscv*-*-*]
4389 && [check_effective_target_riscv_v])
4390 || ([istarget loongarch*-*-*]
4391 && [check_effective_target_loongarch_sx]) }}]
4394 # Return 1 if peeling for alignment might be profitable on the target
4397 proc check_effective_target_vect_peeling_profitable { } {
4398 return [check_cached_effective_target_indexed vect_peeling_profitable {
4399 expr { ([istarget s390*-*-*]
4400 && [check_effective_target_s390_vx])
4401 || [check_effective_target_vect_element_align_preferred] }}]
4404 # Return 1 if the target supports #pragma omp declare simd, 0 otherwise.
4406 # This won't change for different subtargets so cache the result.
4408 proc check_effective_target_vect_simd_clones { } {
4409 # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx,
4410 # avx2 and avx512f clone. Only the right clone for the
4411 # specified arch will be chosen, but still we need to at least
4412 # be able to assemble avx512f.
4413 return [check_cached_effective_target_indexed vect_simd_clones {
4414 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4415 && [check_effective_target_avx512f])
4416 || [istarget amdgcn-*-*]
4417 || [istarget aarch64*-*-*] }}]
4420 # Return 1 if this is a AArch64 target supporting big endian
4421 proc check_effective_target_aarch64_big_endian { } {
4422 return [check_no_compiler_messages aarch64_big_endian assembly {
4423 #if !defined(__aarch64__) || !defined(__AARCH64EB__)
4424 #error !__aarch64__ || !__AARCH64EB__
4429 # Return 1 if this is a AArch64 target supporting little endian
4430 proc check_effective_target_aarch64_little_endian { } {
4431 if { ![istarget aarch64*-*-*] } {
4435 return [check_no_compiler_messages aarch64_little_endian assembly {
4436 #if !defined(__aarch64__) || defined(__AARCH64EB__)
4442 # Return 1 if this is an AArch64 target supporting SVE.
4443 proc check_effective_target_aarch64_sve { } {
4444 if { ![istarget aarch64*-*-*] } {
4447 return [check_no_compiler_messages aarch64_sve assembly {
4448 #if !defined (__ARM_FEATURE_SVE)
4454 # Return 1 if this is an AArch64 target supporting SVE2.
4455 proc check_effective_target_aarch64_sve2 { } {
4456 if { ![istarget aarch64*-*-*] } {
4459 return [check_no_compiler_messages aarch64_sve2 assembly {
4460 #if !defined (__ARM_FEATURE_SVE2)
4466 # Return 1 if this is an AArch64 target only supporting SVE (not SVE2).
4467 proc check_effective_target_aarch64_sve1_only { } {
4468 return [expr { [check_effective_target_aarch64_sve]
4469 && ![check_effective_target_aarch64_sve2] }]
4472 # Return the size in bits of an SVE vector, or 0 if the size is variable.
4473 proc aarch64_sve_bits { } {
4474 return [check_cached_effective_target aarch64_sve_bits {
4477 set src dummy[pid].c
4478 set f [open $src "w"]
4479 puts $f "int bits = __ARM_FEATURE_SVE_BITS;"
4481 set output [${tool}_target_compile $src "" preprocess ""]
4484 regsub {.*bits = ([^;]*);.*} $output {\1} bits
4489 # Return 1 if this is an AArch64 target that generates instructions for SME.
4490 proc check_effective_target_aarch64_sme { } {
4491 if { ![istarget aarch64*-*-*] } {
4494 return [check_no_compiler_messages aarch64_sme assembly {
4495 #if !defined (__ARM_FEATURE_SME)
4501 # Return 1 if this is an AArch64 target that generates instructions for SME.
4502 proc check_effective_target_aarch64_sme2 { } {
4503 if { ![istarget aarch64*-*-*] } {
4506 return [check_no_compiler_messages aarch64_sme2 assembly {
4507 #if !defined (__ARM_FEATURE_SME2)
4513 # Return 1 if this is a compiler supporting ARC atomic operations
4514 proc check_effective_target_arc_atomic { } {
4515 return [check_no_compiler_messages arc_atomic assembly {
4516 #if !defined(__ARC_ATOMIC__)
4522 # Return 1 if this is an arm target using 32-bit instructions
4523 proc check_effective_target_arm32 { } {
4524 if { ![istarget arm*-*-*] } {
4528 return [check_no_compiler_messages arm32 assembly {
4529 #if !defined(__arm__) || (defined(__thumb__) && !defined(__thumb2__))
4530 #error !__arm || __thumb__ && !__thumb2__
4535 # Return 1 if this is an arm target not using Thumb
4536 proc check_effective_target_arm_nothumb { } {
4537 if { ![istarget arm*-*-*] } {
4541 return [check_no_compiler_messages arm_nothumb assembly {
4542 #if !defined(__arm__) || (defined(__thumb__) || defined(__thumb2__))
4543 #error !__arm__ || __thumb || __thumb2__
4548 # Return 1 if this is a little-endian ARM target
4549 proc check_effective_target_arm_little_endian { } {
4550 if { ![istarget arm*-*-*] } {
4554 return [check_no_compiler_messages arm_little_endian assembly {
4555 #if !defined(__arm__) || !defined(__ARMEL__)
4556 #error !__arm__ || !__ARMEL__
4561 # Return 1 if this is an ARM target that only supports aligned vector accesses
4562 proc check_effective_target_arm_vect_no_misalign { } {
4563 if { ![istarget arm*-*-*] } {
4567 return [check_no_compiler_messages arm_vect_no_misalign assembly {
4568 #if !defined(__arm__) \
4569 || (defined(__ARM_FEATURE_UNALIGNED) \
4570 && defined(__ARMEL__))
4571 #error !__arm__ || (__ARMEL__ && __ARM_FEATURE_UNALIGNED)
4577 # Return 1 if this is an ARM target supporting -mfloat-abi=soft. Some
4578 # multilibs may be incompatible with this option.
4580 proc check_effective_target_arm_soft_ok { } {
4581 return [check_no_compiler_messages arm_soft_ok object {
4584 int main (void) { return 0; }
4585 } "-mfloat-abi=soft"]
4588 # Return 1 if this is an ARM target supporting -mfloat-abi=soft even
4589 # for linking. Some multilibs may be incompatible with this option,
4590 # and some linkers may reject incompatible options.
4592 proc check_effective_target_arm_soft_ok_link { } {
4593 return [check_no_compiler_messages arm_soft_ok_link executable {
4596 int main (void) { return 0; }
4597 } "-mfloat-abi=soft"]
4600 # Return 1 if this is an ARM target supporting -mfpu=vfp with an
4603 proc check_effective_target_arm_vfp_ok_nocache { } {
4604 global et_arm_vfp_flags
4605 set et_arm_vfp_flags ""
4606 if { [check_effective_target_arm32] } {
4607 foreach flags {"-mfpu=vfp" "-mfpu=vfp -mfloat-abi=softfp" "-mfpu=vfp -mfloat-abi=hard"} {
4608 if { [check_no_compiler_messages_nocache arm_vfp_ok object {
4610 #error __ARM_FP not defined
4613 set et_arm_vfp_flags $flags
4622 proc check_effective_target_arm_vfp_ok { } {
4623 return [check_cached_effective_target arm_vfp_ok \
4624 check_effective_target_arm_vfp_ok_nocache]
4627 # Add the options needed to compile code with -mfpu=vfp. We need either
4628 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4629 # specified by the multilib, use it.
4631 proc add_options_for_arm_vfp { flags } {
4632 if { ! [check_effective_target_arm_vfp_ok] } {
4635 global et_arm_vfp_flags
4636 return "$flags $et_arm_vfp_flags"
4639 # Return 1 if this is an ARM target supporting -mfpu=vfp3
4640 # -mfloat-abi=softfp.
4642 proc check_effective_target_arm_vfp3_ok { } {
4643 if { [check_effective_target_arm32] } {
4644 return [check_no_compiler_messages arm_vfp3_ok object {
4646 } "-mfpu=vfp3 -mfloat-abi=softfp"]
4652 # Return 1 if this is an ARM target supporting -mfpu=fp-armv8
4653 # -mfloat-abi=softfp.
4654 proc check_effective_target_arm_v8_vfp_ok {} {
4655 if { [check_effective_target_arm32] } {
4656 return [check_no_compiler_messages arm_v8_vfp_ok object {
4659 __asm__ volatile ("vrinta.f32.f32 s0, s0");
4662 } "-mfpu=fp-armv8 -mfloat-abi=softfp"]
4668 # Return 1 if this is an ARM target supporting -mfpu=vfp
4669 # -mfloat-abi=hard. Some multilibs may be incompatible with these
4672 proc check_effective_target_arm_hard_vfp_ok { } {
4673 if { [check_effective_target_arm32]
4674 && ! [check-flags [list "" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" }]] } {
4675 return [check_no_compiler_messages arm_hard_vfp_ok executable {
4676 int main() { return 0;}
4677 } "-mfpu=vfp -mfloat-abi=hard"]
4683 # Return 1 if this is an ARM target defining __ARM_FP. We may need
4684 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4685 # incompatible with these options. Also set et_arm_fp_flags to the
4686 # best options to add.
4688 proc check_effective_target_arm_fp_ok_nocache { } {
4689 global et_arm_fp_flags
4690 set et_arm_fp_flags ""
4691 if { [check_effective_target_arm32] } {
4692 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4693 if { [check_no_compiler_messages_nocache arm_fp_ok object {
4695 #error __ARM_FP not defined
4698 set et_arm_fp_flags $flags
4707 proc check_effective_target_arm_fp_ok { } {
4708 return [check_cached_effective_target arm_fp_ok \
4709 check_effective_target_arm_fp_ok_nocache]
4712 # Add the options needed to define __ARM_FP. We need either
4713 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4714 # specified by the multilib, use it.
4716 proc add_options_for_arm_fp { flags } {
4717 if { ! [check_effective_target_arm_fp_ok] } {
4720 global et_arm_fp_flags
4721 return "$flags $et_arm_fp_flags"
4724 # Return 1 if this is an ARM target defining __ARM_FP with
4725 # double-precision support. We may need -mfloat-abi=softfp or
4726 # equivalent options. Some multilibs may be incompatible with these
4727 # options. Also set et_arm_fp_dp_flags to the best options to add.
4729 proc check_effective_target_arm_fp_dp_ok_nocache { } {
4730 global et_arm_fp_dp_flags
4731 set et_arm_fp_dp_flags ""
4732 if { [check_effective_target_arm32] } {
4733 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4734 if { [check_no_compiler_messages_nocache arm_fp_dp_ok object {
4736 #error __ARM_FP not defined
4738 #if ((__ARM_FP & 8) == 0)
4739 #error __ARM_FP indicates that double-precision is not supported
4742 set et_arm_fp_dp_flags $flags
4751 proc check_effective_target_arm_fp_dp_ok { } {
4752 return [check_cached_effective_target arm_fp_dp_ok \
4753 check_effective_target_arm_fp_dp_ok_nocache]
4756 # Add the options needed to define __ARM_FP with double-precision
4757 # support. We need either -mfloat-abi=softfp or -mfloat-abi=hard, but
4758 # if one is already specified by the multilib, use it.
4760 proc add_options_for_arm_fp_dp { flags } {
4761 if { ! [check_effective_target_arm_fp_dp_ok] } {
4764 global et_arm_fp_dp_flags
4765 return "$flags $et_arm_fp_dp_flags"
4768 # Return 1 if this is an ARM target that supports DSP multiply with
4769 # current multilib flags.
4771 proc check_effective_target_arm_dsp { } {
4772 return [check_no_compiler_messages arm_dsp assembly {
4773 #ifndef __ARM_FEATURE_DSP
4776 #include <arm_acle.h>
4781 # Return 1 if this is an ARM target that supports unaligned word/halfword
4782 # load/store instructions.
4784 proc check_effective_target_arm_unaligned { } {
4785 return [check_no_compiler_messages arm_unaligned assembly {
4786 #ifndef __ARM_FEATURE_UNALIGNED
4787 #error no unaligned support
4793 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4794 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4795 # incompatible with these options. Also set et_arm_crypto_flags to the
4796 # best options to add.
4798 proc check_effective_target_arm_crypto_ok_nocache { } {
4799 global et_arm_crypto_flags
4800 set et_arm_crypto_flags ""
4801 if { [check_effective_target_arm_v8_neon_ok] } {
4802 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=crypto-neon-fp-armv8" "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"} {
4803 if { [check_no_compiler_messages_nocache arm_crypto_ok object {
4804 #include "arm_neon.h"
4806 foo (uint8x16_t a, uint8x16_t b)
4808 return vaeseq_u8 (a, b);
4811 set et_arm_crypto_flags $flags
4820 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4822 proc check_effective_target_arm_crypto_ok { } {
4823 return [check_cached_effective_target arm_crypto_ok \
4824 check_effective_target_arm_crypto_ok_nocache]
4827 # Add options for crypto extensions.
4828 proc add_options_for_arm_crypto { flags } {
4829 if { ! [check_effective_target_arm_crypto_ok] } {
4832 global et_arm_crypto_flags
4833 return "$flags $et_arm_crypto_flags"
4836 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4837 # or -mfloat-abi=hard, but if one is already specified by the
4838 # multilib, use it. Similarly, if a -mfpu option already enables
4839 # NEON, do not add -mfpu=neon.
4841 proc add_options_for_arm_neon { flags } {
4842 if { ! [check_effective_target_arm_neon_ok] } {
4845 global et_arm_neon_flags
4846 return "$flags $et_arm_neon_flags"
4849 proc add_options_for_arm_v8_vfp { flags } {
4850 if { ! [check_effective_target_arm_v8_vfp_ok] } {
4853 return "$flags -mfpu=fp-armv8 -mfloat-abi=softfp"
4856 proc add_options_for_arm_v8_neon { flags } {
4857 if { ! [check_effective_target_arm_v8_neon_ok] } {
4860 global et_arm_v8_neon_flags
4861 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4864 # Add the options needed for ARMv8.1 Adv.SIMD. Also adds the ARMv8 NEON
4865 # options for AArch64 and for ARM.
4867 proc add_options_for_arm_v8_1a_neon { flags } {
4868 if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
4871 global et_arm_v8_1a_neon_flags
4872 return "$flags $et_arm_v8_1a_neon_flags"
4875 # Add the options needed for ARMv8.2 with the scalar FP16 extension.
4876 # Also adds the ARMv8 FP options for ARM and for AArch64.
4878 proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
4879 if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
4882 global et_arm_v8_2a_fp16_scalar_flags
4883 return "$flags $et_arm_v8_2a_fp16_scalar_flags"
4886 # Add the options needed for ARMv8.2 with the FP16 extension. Also adds
4887 # the ARMv8 NEON options for ARM and for AArch64.
4889 proc add_options_for_arm_v8_2a_fp16_neon { flags } {
4890 if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
4893 global et_arm_v8_2a_fp16_neon_flags
4894 return "$flags $et_arm_v8_2a_fp16_neon_flags"
4897 proc add_options_for_arm_crc { flags } {
4898 if { ! [check_effective_target_arm_crc_ok] } {
4901 global et_arm_crc_flags
4902 return "$flags $et_arm_crc_flags"
4905 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4906 # or -mfloat-abi=hard, but if one is already specified by the
4907 # multilib, use it. Similarly, if a -mfpu option already enables
4908 # NEON, do not add -mfpu=neon.
4910 proc add_options_for_arm_neonv2 { flags } {
4911 if { ! [check_effective_target_arm_neonv2_ok] } {
4914 global et_arm_neonv2_flags
4915 return "$flags $et_arm_neonv2_flags"
4918 # Add the options needed for vfp3.
4919 proc add_options_for_arm_vfp3 { flags } {
4920 if { ! [check_effective_target_arm_vfp3_ok] } {
4923 return "$flags -mfpu=vfp3 -mfloat-abi=softfp"
4926 # Return 1 if this is an ARM target supporting -mfpu=neon
4927 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4928 # incompatible with these options. Also set et_arm_neon_flags to the
4929 # best options to add.
4931 proc check_effective_target_arm_neon_ok_nocache { } {
4932 global et_arm_neon_flags
4933 set et_arm_neon_flags ""
4934 if { [check_effective_target_arm32] } {
4935 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -march=armv7-a"} {
4936 if { [check_no_compiler_messages_nocache arm_neon_ok object {
4937 #include <arm_neon.h>
4939 #ifndef __ARM_NEON__
4942 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
4943 configured for -mcpu=arm926ej-s, for example. */
4944 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M'
4945 #error Architecture does not support NEON.
4948 set et_arm_neon_flags $flags
4957 proc check_effective_target_arm_neon_ok { } {
4958 return [check_cached_effective_target arm_neon_ok \
4959 check_effective_target_arm_neon_ok_nocache]
4963 # Return 1 if this is an ARM target supporting the SIMD32 intrinsics
4964 # from arm_acle.h. Some multilibs may be incompatible with these options.
4965 # Also set et_arm_simd32_flags to the best options to add.
4966 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4967 # -mfloat-abi= options.
4969 proc check_effective_target_arm_simd32_ok_nocache { } {
4970 global et_arm_simd32_flags
4971 set et_arm_simd32_flags ""
4972 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard"} {
4973 if { [check_no_compiler_messages_nocache arm_simd32_ok object {
4974 #include <arm_acle.h>
4976 #ifndef __ARM_FEATURE_SIMD32
4980 set et_arm_simd32_flags $flags
4988 proc check_effective_target_arm_simd32_ok { } {
4989 return [check_cached_effective_target arm_simd32_ok \
4990 check_effective_target_arm_simd32_ok_nocache]
4993 proc add_options_for_arm_simd32 { flags } {
4994 if { ! [check_effective_target_arm_simd32_ok] } {
4997 global et_arm_simd32_flags
4998 return "$flags $et_arm_simd32_flags"
5001 # Return 1 if this is an ARM target supporting the __ssat and __usat
5002 # saturation intrinsics from arm_acle.h. Some multilibs may be
5003 # incompatible with these options. Also set et_arm_sat_flags to the
5004 # best options to add. arm_acle.h includes stdint.h which can cause
5005 # trouble with incompatible -mfloat-abi= options.
5007 proc check_effective_target_arm_sat_ok_nocache { } {
5008 global et_arm_sat_flags
5009 set et_arm_sat_flags ""
5010 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard -mfpu=vfp"} {
5011 if { [check_no_compiler_messages_nocache et_arm_sat_flags object {
5012 #include <arm_acle.h>
5014 #ifndef __ARM_FEATURE_SAT
5018 set et_arm_sat_flags $flags
5026 proc check_effective_target_arm_sat_ok { } {
5027 return [check_cached_effective_target et_arm_sat_flags \
5028 check_effective_target_arm_sat_ok_nocache]
5031 proc add_options_for_arm_sat { flags } {
5032 if { ! [check_effective_target_arm_sat_ok] } {
5035 global et_arm_sat_flags
5036 return "$flags $et_arm_sat_flags"
5039 # Return 1 if this is an ARM target supporting the DSP intrinsics from
5040 # arm_acle.h. Some multilibs may be incompatible with these options.
5041 # Also set et_arm_dsp_flags to the best options to add.
5042 # arm_acle.h includes stdint.h which can cause trouble with incompatible
5043 # -mfloat-abi= options.
5044 # check_effective_target_arm_dsp also exists, which checks the current
5045 # multilib, without trying other options.
5047 proc check_effective_target_arm_dsp_ok_nocache { } {
5048 global et_arm_dsp_flags
5049 set et_arm_dsp_flags ""
5050 foreach flags {"" "-march=armv5te" "-march=armv5te -mfloat-abi=softfp" "-march=armv5te -mfloat-abi=hard"} {
5051 if { [check_no_compiler_messages_nocache et_arm_dsp_ok object {
5052 #include <arm_acle.h>
5054 #ifndef __ARM_FEATURE_DSP
5058 set et_arm_dsp_flags $flags
5066 proc check_effective_target_arm_dsp_ok { } {
5067 return [check_cached_effective_target et_arm_dsp_flags \
5068 check_effective_target_arm_dsp_ok_nocache]
5071 proc add_options_for_arm_dsp { flags } {
5072 if { ! [check_effective_target_arm_dsp_ok] } {
5075 global et_arm_dsp_flags
5076 return "$flags $et_arm_dsp_flags"
5079 # Return 1 if this is an ARM target supporting -mfpu=neon without any
5080 # -mfloat-abi= option. Useful in tests where add_options is not
5081 # supported (such as lto tests).
5083 proc check_effective_target_arm_neon_ok_no_float_abi_nocache { } {
5084 if { [check_effective_target_arm32] } {
5085 foreach flags {"-mfpu=neon"} {
5086 if { [check_no_compiler_messages_nocache arm_neon_ok_no_float_abi object {
5087 #include <arm_neon.h>
5089 #ifndef __ARM_NEON__
5092 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
5093 configured for -mcpu=arm926ej-s, for example. */
5094 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M'
5095 #error Architecture does not support NEON.
5106 proc check_effective_target_arm_neon_ok_no_float_abi { } {
5107 return [check_cached_effective_target arm_neon_ok_no_float_abi \
5108 check_effective_target_arm_neon_ok_no_float_abi_nocache]
5111 proc check_effective_target_arm_crc_ok_nocache { } {
5112 global et_arm_crc_flags
5113 set et_arm_crc_flags "-march=armv8-a+crc"
5114 return [check_no_compiler_messages_nocache arm_crc_ok object {
5115 #if !defined (__ARM_FEATURE_CRC32)
5118 #include <arm_acle.h>
5119 } "$et_arm_crc_flags"]
5122 proc check_effective_target_arm_crc_ok { } {
5123 return [check_cached_effective_target arm_crc_ok \
5124 check_effective_target_arm_crc_ok_nocache]
5127 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5128 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5129 # incompatible with these options. Also set et_arm_neon_fp16_flags to
5130 # the best options to add.
5132 proc check_effective_target_arm_neon_fp16_ok_nocache { } {
5133 global et_arm_neon_fp16_flags
5134 global et_arm_neon_flags
5135 set et_arm_neon_fp16_flags ""
5136 if { [check_effective_target_arm32]
5137 && [check_effective_target_arm_neon_ok] } {
5138 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5139 "-mfpu=neon-fp16 -mfloat-abi=softfp"
5140 "-mfp16-format=ieee"
5141 "-mfloat-abi=softfp -mfp16-format=ieee"
5142 "-mfpu=neon-fp16 -mfp16-format=ieee"
5143 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5144 if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
5145 #include "arm_neon.h"
5147 foo (float32x4_t arg)
5149 return vcvt_f16_f32 (arg);
5151 } "$et_arm_neon_flags $flags"] } {
5152 set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
5161 proc check_effective_target_arm_neon_fp16_ok { } {
5162 return [check_cached_effective_target arm_neon_fp16_ok \
5163 check_effective_target_arm_neon_fp16_ok_nocache]
5166 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5167 # and -mfloat-abi=softfp together. Some multilibs may be
5168 # incompatible with these options. Also set et_arm_neon_softfp_fp16_flags to
5169 # the best options to add.
5171 proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } {
5172 global et_arm_neon_softfp_fp16_flags
5173 global et_arm_neon_flags
5174 set et_arm_neon_softfp_fp16_flags ""
5175 if { [check_effective_target_arm32]
5176 && [check_effective_target_arm_neon_ok] } {
5177 foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp"
5178 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5179 if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object {
5180 #include "arm_neon.h"
5182 foo (float32x4_t arg)
5184 return vcvt_f16_f32 (arg);
5186 } "$et_arm_neon_flags $flags"] } {
5187 set et_arm_neon_softfp_fp16_flags [concat $et_arm_neon_flags $flags]
5196 proc check_effective_target_arm_neon_softfp_fp16_ok { } {
5197 return [check_cached_effective_target arm_neon_softfp_fp16_ok \
5198 check_effective_target_arm_neon_softfp_fp16_ok_nocache]
5203 proc check_effective_target_arm_neon_fp16_hw { } {
5204 if {! [check_effective_target_arm_neon_fp16_ok] } {
5207 global et_arm_neon_fp16_flags
5208 check_runtime arm_neon_fp16_hw {
5210 main (int argc, char **argv)
5212 asm ("vcvt.f32.f16 q1, d0");
5215 } $et_arm_neon_fp16_flags
5218 proc add_options_for_arm_neon_fp16 { flags } {
5219 if { ! [check_effective_target_arm_neon_fp16_ok] } {
5222 global et_arm_neon_fp16_flags
5223 return "$flags $et_arm_neon_fp16_flags"
5226 proc add_options_for_arm_neon_softfp_fp16 { flags } {
5227 if { ! [check_effective_target_arm_neon_softfp_fp16_ok] } {
5230 global et_arm_neon_softfp_fp16_flags
5231 return "$flags $et_arm_neon_softfp_fp16_flags"
5234 proc add_options_for_aarch64_sve { flags } {
5235 if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
5238 return "$flags -march=armv8.2-a+sve"
5241 # Return 1 if this is an ARM target supporting the FP16 alternative
5242 # format. Some multilibs may be incompatible with the options needed. Also
5243 # set et_arm_neon_fp16_flags to the best options to add.
5245 proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
5246 if { [istarget *-*-vxworks7*] } {
5247 # Not supported by the target system.
5250 global et_arm_neon_fp16_flags
5251 set et_arm_neon_fp16_flags ""
5252 if { [check_effective_target_arm32] } {
5253 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5254 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5255 if { [check_no_compiler_messages_nocache \
5256 arm_fp16_alternative_ok object {
5257 #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5258 #error __ARM_FP16_FORMAT_ALTERNATIVE not defined
5260 } "$flags -mfp16-format=alternative"] } {
5261 set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative"
5270 proc check_effective_target_arm_fp16_alternative_ok { } {
5271 return [check_cached_effective_target arm_fp16_alternative_ok \
5272 check_effective_target_arm_fp16_alternative_ok_nocache]
5275 # Return 1 if this is an ARM target supports specifying the FP16 none
5276 # format. Some multilibs may be incompatible with the options needed.
5278 proc check_effective_target_arm_fp16_none_ok_nocache { } {
5279 if { [check_effective_target_arm32] } {
5280 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5281 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5282 if { [check_no_compiler_messages_nocache \
5283 arm_fp16_none_ok object {
5284 #if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5285 #error __ARM_FP16_FORMAT_ALTERNATIVE defined
5287 #if defined (__ARM_FP16_FORMAT_IEEE)
5288 #error __ARM_FP16_FORMAT_IEEE defined
5290 } "$flags -mfp16-format=none"] } {
5299 proc check_effective_target_arm_fp16_none_ok { } {
5300 return [check_cached_effective_target arm_fp16_none_ok \
5301 check_effective_target_arm_fp16_none_ok_nocache]
5304 # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
5305 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5306 # incompatible with these options. Also set et_arm_v8_neon_flags to the
5307 # best options to add.
5309 proc check_effective_target_arm_v8_neon_ok_nocache { } {
5310 global et_arm_v8_neon_flags
5311 set et_arm_v8_neon_flags ""
5312 if { [check_effective_target_arm32] } {
5313 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5314 if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {
5316 #error not armv8 or later
5318 #include "arm_neon.h"
5322 __asm__ volatile ("vrintn.f32 q0, q0");
5324 } "$flags -march=armv8-a"] } {
5325 set et_arm_v8_neon_flags $flags
5334 proc check_effective_target_arm_v8_neon_ok { } {
5335 return [check_cached_effective_target arm_v8_neon_ok \
5336 check_effective_target_arm_v8_neon_ok_nocache]
5339 # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4
5340 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5341 # incompatible with these options. Also set et_arm_neonv2_flags to the
5342 # best options to add.
5344 proc check_effective_target_arm_neonv2_ok_nocache { } {
5345 global et_arm_neonv2_flags
5346 global et_arm_neon_flags
5347 set et_arm_neonv2_flags ""
5348 if { [check_effective_target_arm32]
5349 && [check_effective_target_arm_neon_ok] } {
5350 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
5351 if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
5352 #include "arm_neon.h"
5354 foo (float32x2_t a, float32x2_t b, float32x2_t c)
5356 return vfma_f32 (a, b, c);
5358 } "$et_arm_neon_flags $flags"] } {
5359 set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
5368 proc check_effective_target_arm_neonv2_ok { } {
5369 return [check_cached_effective_target arm_neonv2_ok \
5370 check_effective_target_arm_neonv2_ok_nocache]
5373 # Add the options needed for VFP FP16 support. We need either
5374 # -mfloat-abi=softfp or -mfloat-abi=hard. If one is already specified by
5375 # the multilib, use it.
5377 proc add_options_for_arm_fp16 { flags } {
5378 if { ! [check_effective_target_arm_fp16_ok] } {
5381 global et_arm_fp16_flags
5382 return "$flags $et_arm_fp16_flags"
5385 # Add the options needed to enable support for IEEE format
5386 # half-precision support. This is valid for ARM targets.
5388 proc add_options_for_arm_fp16_ieee { flags } {
5389 if { ! [check_effective_target_arm_fp16_ok] } {
5392 global et_arm_fp16_flags
5393 return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
5396 # Add the options needed to enable support for ARM Alternative format
5397 # half-precision support. This is valid for ARM targets.
5399 proc add_options_for_arm_fp16_alternative { flags } {
5400 if { ! [check_effective_target_arm_fp16_ok] } {
5403 global et_arm_fp16_flags
5404 return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
5407 # Return 1 if this is an ARM target that can support a VFP fp16 variant.
5408 # Skip multilibs that are incompatible with these options and set
5409 # et_arm_fp16_flags to the best options to add. This test is valid for
5412 proc check_effective_target_arm_fp16_ok_nocache { } {
5413 global et_arm_fp16_flags
5414 set et_arm_fp16_flags ""
5415 if { ! [check_effective_target_arm32] } {
5419 [list "" { *-*-* } { "-mfpu=*" } \
5420 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
5421 "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
5422 # Multilib flags would override -mfpu.
5425 if [check-flags [list "" { *-*-* } { "-mfloat-abi=soft" } { "" } ]] {
5426 # Must generate floating-point instructions.
5429 if [check_effective_target_arm_hf_eabi] {
5430 # Use existing float-abi and force an fpu which supports fp16
5431 set et_arm_fp16_flags "-mfpu=vfpv4"
5434 if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "" } ]] {
5435 # The existing -mfpu value is OK; use it, but add softfp.
5436 set et_arm_fp16_flags "-mfloat-abi=softfp"
5439 # Add -mfpu for a VFP fp16 variant since there is no preprocessor
5440 # macro to check for this support.
5441 set flags "-mfpu=vfpv4 -mfloat-abi=softfp"
5442 if { [check_no_compiler_messages_nocache arm_fp16_ok assembly {
5445 set et_arm_fp16_flags "$flags"
5452 proc check_effective_target_arm_fp16_ok { } {
5453 return [check_cached_effective_target arm_fp16_ok \
5454 check_effective_target_arm_fp16_ok_nocache]
5457 # Return 1 if the target supports executing VFP FP16 instructions, 0
5458 # otherwise. This test is valid for ARM only.
5460 proc check_effective_target_arm_fp16_hw { } {
5461 if {! [check_effective_target_arm_fp16_ok] } {
5464 global et_arm_fp16_flags
5465 check_runtime arm_fp16_hw {
5467 main (int argc, char **argv)
5471 asm ("vcvtb.f32.f16 %0, %1"
5472 : "=w" (r) : "w" (a)
5473 : /* No clobbers. */);
5474 return (r == 1.0) ? 0 : 1;
5476 } "$et_arm_fp16_flags -mfp16-format=ieee"
5479 # Creates a series of routines that return 1 if the given architecture
5480 # can be selected and a routine to give the flags to select that architecture
5481 # Note: Extra flags may be added to disable options from newer compilers
5482 # (Thumb in particular - but others may be added in the future).
5483 # Warning: Do not use check_effective_target_arm_arch_*_ok for architecture
5484 # extension (eg. ARMv8.1-A) since there is no macro defined for them. See
5485 # how only __ARM_ARCH_8A__ is checked for ARMv8.1-A.
5486 # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
5487 # /* { dg-add-options arm_arch_v5t } */
5488 # /* { dg-require-effective-target arm_arch_v5t_multilib } */
5489 foreach { armfunc armflag armdefs } {
5490 v4 "-march=armv4 -marm" __ARM_ARCH_4__
5491 v4t "-march=armv4t -mfloat-abi=softfp" __ARM_ARCH_4T__
5492 v4t_arm "-march=armv4t -marm" "__ARM_ARCH_4T__ && !__thumb__"
5493 v4t_thumb "-march=armv4t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_4T__ && __thumb__"
5494 v5t "-march=armv5t -mfloat-abi=softfp" __ARM_ARCH_5T__
5495 v5t_arm "-march=armv5t -marm" "__ARM_ARCH_5T__ && !__thumb__"
5496 v5t_thumb "-march=armv5t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5T__ && __thumb__"
5497 v5te "-march=armv5te+fp -mfloat-abi=softfp" __ARM_ARCH_5TE__
5498 v5te_arm "-march=armv5te+fp -marm" "__ARM_ARCH_5TE__ && !__thumb__"
5499 v5te_thumb "-march=armv5te+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5TE__ && __thumb__"
5500 xscale_arm "-mcpu=xscale -mfloat-abi=soft -marm" "__XSCALE__ && !__thumb__"
5501 v6 "-march=armv6+fp -mfloat-abi=softfp" __ARM_ARCH_6__
5502 v6_arm "-march=armv6+fp -marm" "__ARM_ARCH_6__ && !__thumb__"
5503 v6_thumb "-march=armv6+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6__ && __thumb__"
5504 v6k "-march=armv6k+fp -mfloat-abi=softfp" __ARM_ARCH_6K__
5505 v6k_arm "-march=armv6k+fp -marm" "__ARM_ARCH_6K__ && !__thumb__"
5506 v6k_thumb "-march=armv6k+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6K__ && __thumb__"
5507 v6t2 "-march=armv6t2+fp" __ARM_ARCH_6T2__
5508 v6z "-march=armv6z+fp -mfloat-abi=softfp" __ARM_ARCH_6Z__
5509 v6z_arm "-march=armv6z+fp -marm" "__ARM_ARCH_6Z__ && !__thumb__"
5510 v6z_thumb "-march=armv6z+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6Z__ && __thumb__"
5511 v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
5512 v7a "-march=armv7-a+fp" __ARM_ARCH_7A__
5513 v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__"
5514 v7a_neon "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp" "__ARM_ARCH_7A__ && __ARM_NEON__"
5515 v7r "-march=armv7-r+fp" __ARM_ARCH_7R__
5516 v7m "-march=armv7-m -mthumb -mfloat-abi=soft" __ARM_ARCH_7M__
5517 v7em "-march=armv7e-m+fp -mthumb" __ARM_ARCH_7EM__
5518 v7ve "-march=armv7ve+fp -marm"
5519 "__ARM_ARCH_7A__ && __ARM_FEATURE_IDIV"
5520 v8a "-march=armv8-a+simd" __ARM_ARCH_8A__
5521 v8a_hard "-march=armv8-a+simd -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_8A__
5522 v8_1a "-march=armv8.1-a+simd" __ARM_ARCH_8A__
5523 v8_2a "-march=armv8.2-a+simd" __ARM_ARCH_8A__
5524 v8r "-march=armv8-r+fp.sp" __ARM_ARCH_8R__
5525 v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
5526 __ARM_ARCH_8M_BASE__
5527 v8m_main "-march=armv8-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5528 v8_1m_main "-march=armv8.1-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5529 v9a "-march=armv9-a+simd" __ARM_ARCH_9A__ } {
5530 eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
5531 proc check_effective_target_arm_arch_FUNC_ok { } {
5532 return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
5544 proc add_options_for_arm_arch_FUNC { flags } {
5545 return "$flags FLAG"
5548 proc check_effective_target_arm_arch_FUNC_link { } {
5549 return [check_no_compiler_messages arm_arch_FUNC_link executable {
5552 int main (void) { return 0; }
5553 } [add_options_for_arm_arch_FUNC ""]]
5556 proc check_effective_target_arm_arch_FUNC_multilib { } {
5557 return [check_runtime arm_arch_FUNC_multilib {
5563 } [add_options_for_arm_arch_FUNC ""]]
5568 # Return 1 if GCC was configured with --with-mode=
5569 proc check_effective_target_default_mode { } {
5571 return [check_configured_with "with-mode="]
5574 # Return 1 if this is an ARM target where -marm causes ARM to be
5577 proc check_effective_target_arm_arm_ok { } {
5578 return [check_no_compiler_messages arm_arm_ok assembly {
5579 #if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
5580 #error !__arm__ || __thumb__ || __thumb2__
5586 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
5589 proc check_effective_target_arm_thumb1_ok { } {
5590 return [check_no_compiler_messages arm_thumb1_ok assembly {
5591 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5592 #error !__arm__ || !__thumb__ || __thumb2__
5594 int foo (int i) { return i; }
5598 # Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be
5601 proc check_effective_target_arm_thumb2_ok { } {
5602 return [check_no_compiler_messages arm_thumb2_ok assembly {
5603 #if !defined(__thumb2__)
5606 int foo (int i) { return i; }
5610 # Return 1 if this is an ARM target where Thumb-1 is used without options
5611 # added by the test.
5613 proc check_effective_target_arm_thumb1 { } {
5614 return [check_no_compiler_messages arm_thumb1 assembly {
5615 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5616 #error !__arm__ || !__thumb__ || __thumb2__
5622 # Return 1 if this is an ARM target where Thumb-2 is used without options
5623 # added by the test.
5625 proc check_effective_target_arm_thumb2 { } {
5626 return [check_no_compiler_messages arm_thumb2 assembly {
5627 #if !defined(__thumb2__)
5634 # Return 1 if this is an ARM target where conditional execution is available.
5636 proc check_effective_target_arm_cond_exec { } {
5637 return [check_no_compiler_messages arm_cond_exec assembly {
5638 #if defined(__arm__) && defined(__thumb__) && !defined(__thumb2__)
5645 # Return 1 if this is an ARM cortex-M profile cpu
5647 proc check_effective_target_arm_cortex_m { } {
5648 if { ![istarget arm*-*-*] } {
5651 return [check_no_compiler_messages arm_cortex_m assembly {
5652 #if defined(__ARM_ARCH_ISA_ARM)
5653 #error __ARM_ARCH_ISA_ARM is defined
5659 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5660 # used and MOVT/MOVW instructions to be available.
5662 proc check_effective_target_arm_thumb1_movt_ok {} {
5663 if [check_effective_target_arm_thumb1_ok] {
5664 return [check_no_compiler_messages arm_movt object {
5668 asm ("movt r0, #42");
5676 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5677 # used and CBZ and CBNZ instructions are available.
5679 proc check_effective_target_arm_thumb1_cbz_ok {} {
5680 if [check_effective_target_arm_thumb1_ok] {
5681 return [check_no_compiler_messages arm_cbz object {
5685 asm ("cbz r0, 2f\n2:");
5693 # Return 1 if this is an Arm target which supports the Armv6t2 extensions.
5694 # This can be either in Arm state or in Thumb state.
5696 proc check_effective_target_arm_arch_v6t2_hw {} {
5697 if [check_effective_target_arm_arch_v6t2_ok] {
5698 return [check_runtime arm_arch_v6t2 {
5702 asm ("bfc r0, #1, #2");
5705 } [add_options_for_arm_arch_v6t2 ""]]
5711 # Return 1 if this is an ARM target where ARMv8-M Security Extensions is
5714 proc check_effective_target_arm_cmse_ok {} {
5715 return [check_no_compiler_messages arm_cmse object {
5724 # Return 1 if the target supports executing CMSE instructions, 0
5725 # otherwise. Cache the result.
5727 proc check_effective_target_arm_cmse_hw { } {
5728 return [check_runtime arm_cmse_hw_available {
5732 asm ("ldr\t%0, =0xe000ed44\n" \
5734 "sg" : "=l" (id_pfr1));
5735 /* Exit with code 0 iff security extension is available. */
5736 return !(id_pfr1 & 0xf0);
5741 # Return 1 if the target supports executing MVE instructions, 0
5744 proc check_effective_target_arm_mve_hw {} {
5745 return [check_runtime arm_mve_hw_available {
5751 asm ("sqrshrl %Q1, %R1, #64, %2"
5753 : "0" (a), "r" (b));
5756 } [add_options_for_arm_v8_1m_mve_fp ""]]
5759 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
5760 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.
5762 proc check_effective_target_arm_cmse_clear_ok {} {
5763 return [check_no_compiler_messages arm_cmse_clear object {
5767 asm ("clrm {r1, r2}");
5772 # Return 1 if this is an ARM target supporting
5773 # -mbranch-protection=standard, 0 otherwise.
5775 proc check_effective_target_mbranch_protection_ok {} {
5777 return [check_no_compiler_messages mbranch_protection_ok object {
5778 int main (void) { return 0; }
5779 } "-mbranch-protection=standard"]
5782 # Return 1 if the target supports executing PACBTI instructions, 0
5785 proc check_effective_target_arm_pacbti_hw {} {
5786 return [check_runtime arm_pacbti_hw_available {
5787 __attribute__ ((naked)) int
5790 asm ("pac r12, lr, sp");
5792 asm ("autg r12, lr, sp");
5795 } "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mthumb -mfloat-abi=hard"]
5798 # Return 1 if this compilation turns on string_ops_prefer_neon on.
5800 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
5801 return [check_no_messages_and_pattern arm_tune_string_ops_prefer_neon "@string_ops_prefer_neon:\t1" assembly {
5802 int foo (void) { return 0; }
5803 } "-O2 -mprint-tune-info" ]
5806 # Return 1 if the target supports executing NEON instructions, 0
5807 # otherwise. Cache the result.
5809 proc check_effective_target_arm_neon_hw { } {
5810 return [check_runtime arm_neon_hw_available {
5814 long long a = 0, b = 1;
5815 asm ("vorr %P0, %P1, %P2"
5817 : "0" (a), "w" (b));
5820 } [add_options_for_arm_neon ""]]
5823 # Return true if this is an AArch64 target that can run SVE code.
5825 proc check_effective_target_aarch64_sve_hw { } {
5826 if { ![istarget aarch64*-*-*] } {
5829 return [check_runtime aarch64_sve_hw_available {
5833 asm volatile ("ptrue p0.b");
5836 } [add_options_for_aarch64_sve ""]]
5839 # Return true if this is an AArch64 target that can run SVE2 code.
5841 proc check_effective_target_aarch64_sve2_hw { } {
5842 if { ![istarget aarch64*-*-*] } {
5845 return [check_runtime aarch64_sve2_hw_available {
5849 asm volatile ("addp z0.b, p0/m, z0.b, z1.b");
5855 # Return true if this is an AArch64 target that can run SVE code and
5856 # if its SVE vectors have exactly BITS bits.
5858 proc aarch64_sve_hw_bits { bits } {
5859 if { ![check_effective_target_aarch64_sve_hw] } {
5862 return [check_runtime aarch64_sve${bits}_hw [subst {
5867 asm volatile ("cntd %0" : "=r" (res));
5868 if (res * 64 != $bits)
5872 }] [add_options_for_aarch64_sve ""]]
5875 # Return true if this is an AArch64 target that can run SVE code and
5876 # if its SVE vectors have exactly 256 bits.
5878 foreach N { 128 256 512 1024 2048 } {
5879 eval [string map [list N $N] {
5880 proc check_effective_target_aarch64_sveN_hw { } {
5881 return [aarch64_sve_hw_bits N]
5886 proc check_effective_target_arm_neonv2_hw { } {
5887 return [check_runtime arm_neon_hwv2_available {
5888 #include "arm_neon.h"
5892 float32x2_t a, b, c;
5893 asm ("vfma.f32 %P0, %P1, %P2"
5895 : "w" (b), "w" (c));
5898 } [add_options_for_arm_neonv2 ""]]
5901 # ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented.
5902 proc check_effective_target_aarch64_bti_hw { } {
5903 if { ![istarget aarch64*-*-*] } {
5906 return [check_runtime aarch64_bti_hw_available {
5911 asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a));
5912 return !((a & 0xf) == 1);
5917 # Return 1 if the target supports executing the armv8.3-a FJCVTZS
5919 proc check_effective_target_aarch64_fjcvtzs_hw { } {
5920 if { ![istarget aarch64*-*-*] } {
5923 return [check_runtime aarch64_fjcvtzs_hw_available {
5929 asm volatile ("fjcvtzs %w0, %d1"
5932 : /* No clobbers. */);
5935 } "-march=armv8.3-a" ]
5938 # Return 1 if GCC was configured with --enable-standard-branch-protection
5939 proc check_effective_target_default_branch_protection { } {
5940 return [check_configured_with "enable-standard-branch-protection"]
5943 # Return 1 if this is an ARM target supporting -mfloat-abi=softfp.
5945 proc check_effective_target_arm_softfp_ok { } {
5946 return [check_no_compiler_messages arm_softfp_ok object {
5949 int main (void) { return 0; }
5950 } "-mfloat-abi=softfp"]
5953 # Return 1 if this is an ARM target supporting -mfloat-abi=hard.
5955 proc check_effective_target_arm_hard_ok { } {
5956 return [check_no_compiler_messages arm_hard_ok object {
5959 int main (void) { return 0; }
5960 } "-mfloat-abi=hard"]
5963 # Return 1 if this is an ARM target supporting MVE.
5964 proc check_effective_target_arm_mve { } {
5965 if { ![istarget arm*-*-*] } {
5968 return [check_no_compiler_messages arm_mve assembly {
5969 #if !defined (__ARM_FEATURE_MVE)
5975 # Return 1 if the target supports ARMv8.1-M MVE with floating point
5976 # instructions, 0 otherwise. The test is valid for ARM.
5977 # Record the command line options needed.
5979 proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } {
5980 global et_arm_v8_1m_mve_fp_flags
5981 set et_arm_v8_1m_mve_fp_flags ""
5983 if { ![istarget arm*-*-*] } {
5987 # Iterate through sets of options to find the compiler flags that
5988 # need to be added to the -march option.
5989 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp"} {
5990 if { [check_no_compiler_messages_nocache \
5991 arm_v8_1m_mve_fp_ok object {
5992 #include <arm_mve.h>
5993 #if !(__ARM_FEATURE_MVE & 2)
5994 #error "__ARM_FEATURE_MVE for floating point not defined"
5996 #if __ARM_BIG_ENDIAN
5997 #error "MVE intrinsics are not supported in Big-Endian mode."
5999 } "$flags -mthumb"] } {
6000 set et_arm_v8_1m_mve_fp_flags "$flags -mthumb --save-temps"
6008 proc check_effective_target_arm_v8_1m_mve_fp_ok { } {
6009 return [check_cached_effective_target arm_v8_1m_mve_fp_ok \
6010 check_effective_target_arm_v8_1m_mve_fp_ok_nocache]
6013 proc add_options_for_arm_v8_1m_mve_fp { flags } {
6014 if { ! [check_effective_target_arm_v8_1m_mve_fp_ok] } {
6017 global et_arm_v8_1m_mve_fp_flags
6018 return "$flags $et_arm_v8_1m_mve_fp_flags"
6021 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
6022 # otherwise. The test is valid for AArch64 and ARM. Record the command
6023 # line options needed.
6025 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
6026 global et_arm_v8_1a_neon_flags
6027 set et_arm_v8_1a_neon_flags ""
6029 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6033 # Iterate through sets of options to find the compiler flags that
6034 # need to be added to the -march option. Start with the empty set
6035 # since AArch64 only needs the -march setting.
6036 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6037 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6038 foreach arches { "-march=armv8-a+rdma" "-march=armv8.1-a" } {
6039 if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
6040 #if !defined (__ARM_FEATURE_QRDMX)
6041 #error "__ARM_FEATURE_QRDMX not defined"
6043 } "$flags $arches"] } {
6044 set et_arm_v8_1a_neon_flags "$flags $arches"
6053 proc check_effective_target_arm_v8_1a_neon_ok { } {
6054 return [check_cached_effective_target arm_v8_1a_neon_ok \
6055 check_effective_target_arm_v8_1a_neon_ok_nocache]
6058 # Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
6059 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6060 # Record the command line options needed.
6062 proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
6063 global et_arm_v8_2a_fp16_scalar_flags
6064 set et_arm_v8_2a_fp16_scalar_flags ""
6066 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6070 # Iterate through sets of options to find the compiler flags that
6071 # need to be added to the -march option.
6072 foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
6073 "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
6074 if { [check_no_compiler_messages_nocache \
6075 arm_v8_2a_fp16_scalar_ok object {
6076 #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
6077 #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
6079 } "$flags -march=armv8.2-a+fp16"] } {
6080 set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
6088 proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
6089 return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
6090 check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
6093 # Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
6094 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6095 # Record the command line options needed.
6097 proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
6098 global et_arm_v8_2a_fp16_neon_flags
6099 set et_arm_v8_2a_fp16_neon_flags ""
6101 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6105 # Iterate through sets of options to find the compiler flags that
6106 # need to be added to the -march option.
6107 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6108 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6109 if { [check_no_compiler_messages_nocache \
6110 arm_v8_2a_fp16_neon_ok object {
6111 #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
6112 #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
6114 } "$flags -march=armv8.2-a+fp16"] } {
6115 set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
6123 proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
6124 return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
6125 check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
6128 # Return 1 if the target supports ARMv8.2 Adv.SIMD Dot Product
6129 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6130 # Record the command line options needed.
6132 proc check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {
6133 global et_arm_v8_2a_dotprod_neon_flags
6134 set et_arm_v8_2a_dotprod_neon_flags ""
6136 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6140 # Iterate through sets of options to find the compiler flags that
6141 # need to be added to the -march option.
6142 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6143 if { [check_no_compiler_messages_nocache \
6144 arm_v8_2a_dotprod_neon_ok object {
6146 #if !defined (__ARM_FEATURE_DOTPROD)
6147 #error "__ARM_FEATURE_DOTPROD not defined"
6149 } "$flags -march=armv8.2-a+dotprod"] } {
6150 set et_arm_v8_2a_dotprod_neon_flags "$flags -march=armv8.2-a+dotprod"
6158 # Return 1 if the target supports ARMv8.1-M MVE
6159 # instructions, 0 otherwise. The test is valid for ARM.
6160 # Record the command line options needed.
6162 proc check_effective_target_arm_v8_1m_mve_ok_nocache { } {
6163 global et_arm_v8_1m_mve_flags
6164 set et_arm_v8_1m_mve_flags ""
6166 if { ![istarget arm*-*-*] } {
6170 # Iterate through sets of options to find the compiler flags that
6171 # need to be added to the -march option.
6172 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve"} {
6173 if { [check_no_compiler_messages_nocache \
6174 arm_v8_1m_mve_ok object {
6175 #if !defined (__ARM_FEATURE_MVE)
6176 #error "__ARM_FEATURE_MVE not defined"
6178 #if __ARM_BIG_ENDIAN
6179 #error "MVE intrinsics are not supported in Big-Endian mode."
6181 #include <arm_mve.h>
6182 } "$flags -mthumb"] } {
6183 set et_arm_v8_1m_mve_flags "$flags -mthumb --save-temps"
6191 proc check_effective_target_arm_v8_1m_mve_ok { } {
6192 return [check_cached_effective_target arm_v8_1m_mve_ok \
6193 check_effective_target_arm_v8_1m_mve_ok_nocache]
6196 proc add_options_for_arm_v8_1m_mve { flags } {
6197 if { ! [check_effective_target_arm_v8_1m_mve_ok] } {
6200 global et_arm_v8_1m_mve_flags
6201 return "$flags $et_arm_v8_1m_mve_flags"
6204 proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {
6205 return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \
6206 check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]
6209 proc add_options_for_arm_v8_2a_dotprod_neon { flags } {
6210 if { ! [check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6213 global et_arm_v8_2a_dotprod_neon_flags
6214 return "$flags $et_arm_v8_2a_dotprod_neon_flags"
6217 # Return 1 if the target supports ARMv8.2+i8mm Adv.SIMD Dot Product
6218 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6219 # Record the command line options needed.
6221 proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } {
6222 global et_arm_v8_2a_i8mm_flags
6223 set et_arm_v8_2a_i8mm_flags ""
6225 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6229 # Iterate through sets of options to find the compiler flags that
6230 # need to be added to the -march option.
6231 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6232 if { [check_no_compiler_messages_nocache \
6233 arm_v8_2a_i8mm_ok object {
6234 #include <arm_neon.h>
6235 #if !defined (__ARM_FEATURE_MATMUL_INT8)
6236 #error "__ARM_FEATURE_MATMUL_INT8 not defined"
6238 } "$flags -march=armv8.2-a+i8mm"] } {
6239 set et_arm_v8_2a_i8mm_flags "$flags -march=armv8.2-a+i8mm"
6247 proc check_effective_target_arm_v8_2a_i8mm_ok { } {
6248 return [check_cached_effective_target arm_v8_2a_i8mm_ok \
6249 check_effective_target_arm_v8_2a_i8mm_ok_nocache]
6252 proc add_options_for_arm_v8_2a_i8mm { flags } {
6253 if { ! [check_effective_target_arm_v8_2a_i8mm_ok] } {
6256 global et_arm_v8_2a_i8mm_flags
6257 return "$flags $et_arm_v8_2a_i8mm_flags"
6260 # Return 1 if the target supports FP16 VFMAL and VFMSL
6261 # instructions, 0 otherwise.
6262 # Record the command line options needed.
6264 proc check_effective_target_arm_fp16fml_neon_ok_nocache { } {
6265 global et_arm_fp16fml_neon_flags
6266 set et_arm_fp16fml_neon_flags ""
6268 if { ![istarget arm*-*-*] } {
6272 # Iterate through sets of options to find the compiler flags that
6273 # need to be added to the -march option.
6274 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6275 if { [check_no_compiler_messages_nocache \
6276 arm_fp16fml_neon_ok assembly {
6277 #include <arm_neon.h>
6279 foo (float32x2_t r, float16x4_t a, float16x4_t b)
6281 return vfmlal_high_f16 (r, a, b);
6283 } "$flags -march=armv8.2-a+fp16fml"] } {
6284 set et_arm_fp16fml_neon_flags "$flags -march=armv8.2-a+fp16fml"
6292 proc check_effective_target_arm_fp16fml_neon_ok { } {
6293 return [check_cached_effective_target arm_fp16fml_neon_ok \
6294 check_effective_target_arm_fp16fml_neon_ok_nocache]
6297 proc add_options_for_arm_fp16fml_neon { flags } {
6298 if { ! [check_effective_target_arm_fp16fml_neon_ok] } {
6301 global et_arm_fp16fml_neon_flags
6302 return "$flags $et_arm_fp16fml_neon_flags"
6305 # Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise.
6306 # The test is valid for ARM and for AArch64.
6308 proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
6309 global et_arm_v8_2a_bf16_neon_flags
6310 set et_arm_v8_2a_bf16_neon_flags ""
6312 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6316 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6317 if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
6318 #include <arm_neon.h>
6319 #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)
6320 #error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC not defined"
6322 } "$flags -march=armv8.2-a+bf16"] } {
6323 set et_arm_v8_2a_bf16_neon_flags "$flags -march=armv8.2-a+bf16"
6331 proc check_effective_target_arm_v8_2a_bf16_neon_ok { } {
6332 return [check_cached_effective_target arm_v8_2a_bf16_neon_ok \
6333 check_effective_target_arm_v8_2a_bf16_neon_ok_nocache]
6336 proc add_options_for_arm_v8_2a_bf16_neon { flags } {
6337 if { ! [check_effective_target_arm_v8_2a_bf16_neon_ok] } {
6340 global et_arm_v8_2a_bf16_neon_flags
6341 return "$flags $et_arm_v8_2a_bf16_neon_flags"
6344 # A series of routines are created to 1) check if a given architecture is
6345 # effective (check_effective_target_*_ok) and then 2) give the corresponding
6346 # flags that enable the architecture (add_options_for_*).
6347 # The series includes:
6348 # arm_v8m_main_cde: Armv8-m CDE (Custom Datapath Extension).
6349 # arm_v8m_main_cde_fp: Armv8-m CDE with FP registers.
6350 # arm_v8_1m_main_cde_mve: Armv8.1-m CDE with MVE.
6351 # arm_v8_1m_main_cde_mve_fp: Armv8.1-m CDE with MVE with FP support.
6353 # /* { dg-require-effective-target arm_v8m_main_cde_ok } */
6354 # /* { dg-add-options arm_v8m_main_cde } */
6355 # The tests are valid for Arm.
6357 foreach { armfunc armflag armdef arminc } {
6359 "-march=armv8-m.main+cdecp0+cdecp6 -mthumb"
6360 "defined (__ARM_FEATURE_CDE)"
6363 "-march=armv8-m.main+fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6364 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FP)"
6366 arm_v8_1m_main_cde_mve
6367 "-march=armv8.1-m.main+mve+cdecp0+cdecp6 -mthumb -mfpu=auto"
6368 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FEATURE_MVE)"
6369 "#include <arm_mve.h>"
6370 arm_v8_1m_main_cde_mve_fp
6371 "-march=armv8.1-m.main+mve.fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6372 "defined (__ARM_FEATURE_CDE) || __ARM_FEATURE_MVE == 3"
6373 "#include <arm_mve.h>"
6375 eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef INC $arminc ] {
6376 proc check_effective_target_FUNC_ok_nocache { } {
6377 global et_FUNC_flags
6378 set et_FUNC_flags ""
6380 if { ![istarget arm*-*-*] } {
6384 if { [check_no_compiler_messages_nocache FUNC_ok assembly {
6388 #include <arm_cde.h>
6391 set et_FUNC_flags "FLAG"
6398 proc check_effective_target_FUNC_ok { } {
6399 return [check_cached_effective_target FUNC_ok \
6400 check_effective_target_FUNC_ok_nocache]
6403 proc add_options_for_FUNC { flags } {
6404 if { ! [check_effective_target_FUNC_ok] } {
6407 global et_FUNC_flags
6408 return "$flags $et_FUNC_flags"
6411 proc check_effective_target_FUNC_link { } {
6412 if { ! [check_effective_target_FUNC_ok] } {
6415 return [check_no_compiler_messages FUNC_link executable {
6419 #include <arm_cde.h>
6426 } [add_options_for_FUNC ""]]
6429 proc check_effective_target_FUNC_multilib { } {
6430 if { ! [check_effective_target_FUNC_ok] } {
6433 return [check_runtime FUNC_multilib {
6437 #include <arm_cde.h>
6444 } [add_options_for_FUNC ""]]
6449 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
6452 proc check_effective_target_arm_v8_neon_hw { } {
6453 return [check_runtime arm_v8_neon_hw_available {
6454 #include "arm_neon.h"
6458 float32x2_t a = { 1.0f, 2.0f };
6459 #ifdef __ARM_ARCH_ISA_A64
6460 asm ("frinta %0.2s, %1.2s"
6464 asm ("vrinta.f32 %P0, %P1"
6468 return a[0] == 2.0f;
6470 } [add_options_for_arm_v8_neon ""]]
6473 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
6474 # otherwise. The test is valid for AArch64 and ARM.
6476 proc check_effective_target_arm_v8_1a_neon_hw { } {
6477 if { ![check_effective_target_arm_v8_1a_neon_ok] } {
6480 return [check_runtime arm_v8_1a_neon_hw_available {
6484 #ifdef __ARM_ARCH_ISA_A64
6485 __Int32x2_t a = {0, 1};
6486 __Int32x2_t b = {0, 2};
6489 asm ("sqrdmlah %0.2s, %1.2s, %2.2s"
6492 : /* No clobbers. */);
6496 __simd64_int32_t a = {0, 1};
6497 __simd64_int32_t b = {0, 2};
6498 __simd64_int32_t result;
6500 asm ("vqrdmlah.s32 %P0, %P1, %P2"
6503 : /* No clobbers. */);
6508 } [add_options_for_arm_v8_1a_neon ""]]
6511 # Return 1 if the target supports executing floating point instructions from
6512 # ARMv8.2 with the FP16 extension, 0 otherwise. The test is valid for ARM and
6515 proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
6516 if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
6519 return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
6526 #ifdef __ARM_ARCH_ISA_A64
6528 asm ("fabs %h0, %h1"
6531 : /* No clobbers. */);
6535 asm ("vabs.f16 %0, %1"
6538 : /* No clobbers. */);
6542 return (result == 1.0) ? 0 : 1;
6544 } [add_options_for_arm_v8_2a_fp16_scalar ""]]
6547 # Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
6548 # with the FP16 extension, 0 otherwise. The test is valid for ARM and for
6551 proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
6552 if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
6555 return [check_runtime arm_v8_2a_fp16_neon_hw_available {
6559 #ifdef __ARM_ARCH_ISA_A64
6561 __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
6562 __Float16x4_t result;
6564 asm ("fabs %0.4h, %1.4h"
6567 : /* No clobbers. */);
6571 __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
6572 __simd64_float16_t result;
6574 asm ("vabs.f16 %P0, %P1"
6577 : /* No clobbers. */);
6581 return (result[0] == 1.0) ? 0 : 1;
6583 } [add_options_for_arm_v8_2a_fp16_neon ""]]
6586 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6587 # with the Dot Product extension, 0 otherwise. The test is valid for ARM and for
6590 proc check_effective_target_arm_v8_2a_dotprod_neon_hw { } {
6591 if { ![check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6594 return [check_runtime arm_v8_2a_dotprod_neon_hw_available {
6595 #include "arm_neon.h"
6600 uint32x2_t results = {0,0};
6601 uint8x8_t a = {1,1,1,1,2,2,2,2};
6602 uint8x8_t b = {2,2,2,2,3,3,3,3};
6604 #ifdef __ARM_ARCH_ISA_A64
6605 asm ("udot %0.2s, %1.8b, %2.8b"
6608 : /* No clobbers. */);
6611 asm ("vudot.u8 %P0, %P1, %P2"
6614 : /* No clobbers. */);
6617 return (results[0] == 8 && results[1] == 24) ? 1 : 0;
6619 } [add_options_for_arm_v8_2a_dotprod_neon ""]]
6622 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6623 # with the i8mm extension, 0 otherwise. The test is valid for ARM and for
6626 proc check_effective_target_arm_v8_2a_i8mm_neon_hw { } {
6627 if { ![check_effective_target_arm_v8_2a_i8mm_ok] } {
6630 return [check_runtime arm_v8_2a_i8mm_neon_hw_available {
6631 #include "arm_neon.h"
6636 uint32x2_t results = {0,0};
6637 uint8x8_t a = {1,1,1,1,2,2,2,2};
6638 int8x8_t b = {2,2,2,2,3,3,3,3};
6640 #ifdef __ARM_ARCH_ISA_A64
6641 asm ("usdot %0.2s, %1.8b, %2.8b"
6644 : /* No clobbers. */);
6647 asm ("vusdot.u8 %P0, %P1, %P2"
6650 : /* No clobbers. */);
6653 return (vget_lane_u32 (results, 0) == 8
6654 && vget_lane_u32 (results, 1) == 24) ? 1 : 0;
6656 } [add_options_for_arm_v8_2a_i8mm ""]]
6659 # Return 1 if this is a ARM target with NEON enabled.
6661 proc check_effective_target_arm_neon { } {
6662 if { [check_effective_target_arm32] } {
6663 return [check_no_compiler_messages arm_neon object {
6664 #ifndef __ARM_NEON__
6675 proc check_effective_target_arm_neonv2 { } {
6676 if { [check_effective_target_arm32] } {
6677 return [check_no_compiler_messages arm_neon object {
6678 #ifndef __ARM_NEON__
6681 #ifndef __ARM_FEATURE_FMA
6693 # Return 1 if this is an ARM target with load acquire and store release
6694 # instructions for 8-, 16- and 32-bit types.
6696 proc check_effective_target_arm_acq_rel { } {
6697 return [check_no_compiler_messages arm_acq_rel object {
6699 load_acquire_store_release (void)
6701 asm ("lda r0, [r1]\n\t"
6707 : : : "r0", "memory");
6712 # Add the options needed for MIPS Paired-Single.
6714 proc add_options_for_mpaired_single { flags } {
6715 if { ! [check_effective_target_mpaired_single "-mpaired-single"] } {
6718 return "$flags -mpaired-single"
6721 # Add the options needed for MIPS SIMD Architecture.
6723 proc add_options_for_mips_msa { flags } {
6724 if { ! [check_effective_target_mips_msa "-mmsa"] } {
6727 return "$flags -mmsa"
6730 # Add the options needed for MIPS Loongson MMI Architecture.
6732 proc add_options_for_mips_loongson_mmi { flags } {
6733 if { ! [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
6736 return "$flags -mloongson-mmi"
6740 # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
6741 # the Loongson vector modes.
6743 proc check_effective_target_mips_loongson_mmi { args } {
6744 return [check_no_compiler_messages loongson assembly {
6745 #if !defined(__mips_loongson_mmi)
6746 #error !__mips_loongson_mmi
6748 #if !defined(__mips_loongson_vector_rev)
6749 #error !__mips_loongson_vector_rev
6754 # Return 1 if this is a MIPS target that supports the legacy NAN.
6756 proc check_effective_target_mips_nanlegacy { } {
6757 return [check_no_compiler_messages nanlegacy assembly {
6759 int main () { return 0; }
6763 # Return 1 if an MSA program can be compiled to object
6765 proc check_effective_target_mips_msa { args } {
6766 if ![check_effective_target_nomips16] {
6769 return [check_no_compiler_messages msa object {
6770 #if !defined(__mips_msa)
6771 #error "MSA NOT AVAIL"
6773 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
6774 #error "MSA NOT AVAIL FOR ISA REV < 2"
6776 #if !defined(__mips_hard_float)
6777 #error "MSA HARD_FLOAT REQUIRED"
6779 #if __mips_fpr != 64
6780 #error "MSA 64-bit FPR REQUIRED"
6786 v8i16 v = __builtin_msa_ldi_h (1);
6794 # Return 1 if this is an ARM target that adheres to the ABI for the ARM
6797 proc check_effective_target_arm_eabi { } {
6798 return [check_no_compiler_messages arm_eabi object {
6799 #ifndef __ARM_EABI__
6807 # Return 1 if this is an ARM target that adheres to the hard-float variant of
6808 # the ABI for the ARM Architecture (e.g. -mfloat-abi=hard).
6810 proc check_effective_target_arm_hf_eabi { } {
6811 return [check_no_compiler_messages arm_hf_eabi object {
6812 #if !defined(__ARM_EABI__) || !defined(__ARM_PCS_VFP)
6813 #error not hard-float EABI
6820 # Return 1 if this is an ARM target uses emulated floating point
6823 proc check_effective_target_arm_softfloat { } {
6824 return [check_no_compiler_messages arm_softfloat object {
6825 #if !defined(__SOFTFP__)
6826 #error not soft-float EABI
6833 # Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
6834 # Some multilibs may be incompatible with this option.
6836 proc check_effective_target_arm_iwmmxt_ok { } {
6837 if { [check_effective_target_arm32] } {
6838 return [check_no_compiler_messages arm_iwmmxt_ok object {
6846 # Return true if LDRD/STRD instructions are prefered over LDM/STM instructions
6847 # for an ARM target.
6848 proc check_effective_target_arm_prefer_ldrd_strd { } {
6849 if { ![check_effective_target_arm32] } {
6853 return [check_no_messages_and_pattern arm_prefer_ldrd_strd "strd\tr" assembly {
6854 void foo (void) { __asm__ ("" ::: "r4", "r5"); }
6858 # Return true if LDRD/STRD instructions are available on this target.
6859 proc check_effective_target_arm_ldrd_strd_ok { } {
6860 if { ![check_effective_target_arm32] } {
6864 return [check_no_compiler_messages arm_ldrd_strd_ok object {
6867 __UINT64_TYPE__ a = 1, b = 10;
6868 __UINT64_TYPE__ *c = &b;
6869 // `a` will be in a valid register since it's a DImode quantity.
6878 # Return 1 if this is a PowerPC target supporting -meabi.
6880 proc check_effective_target_powerpc_eabi_ok { } {
6881 if { [istarget powerpc*-*-*] } {
6882 return [check_no_compiler_messages powerpc_eabi_ok object {
6890 # Return 1 if this is a PowerPC target with floating-point registers.
6892 proc check_effective_target_powerpc_fprs { } {
6893 if { [istarget powerpc*-*-*]
6894 || [istarget rs6000-*-*] } {
6895 return [check_no_compiler_messages powerpc_fprs object {
6907 # Return 1 if this is a PowerPC target with hardware double-precision
6910 proc check_effective_target_powerpc_hard_double { } {
6911 if { [istarget powerpc*-*-*]
6912 || [istarget rs6000-*-*] } {
6913 return [check_no_compiler_messages powerpc_hard_double object {
6925 # Return 1 if this is a PowerPC target with hardware floating point sqrt.
6927 proc check_effective_target_powerpc_sqrt { } {
6928 # We need to be PowerPC, and we need to have hardware fp enabled.
6929 if {![check_effective_target_powerpc_fprs]} {
6933 return [check_no_compiler_messages powerpc_sqrt object {
6937 #error _ARCH_PPCSQ is not defined
6943 # Return 1 if this is a PowerPC target supporting -maltivec.
6945 proc check_effective_target_powerpc_altivec_ok { } {
6946 # Not PowerPC, then not ok
6947 if { !([istarget powerpc*-*-*] || [istarget rs6000-*-*]) } { return 0 }
6949 # Paired Single, then not ok
6950 if { [istarget powerpc-*-linux*paired*] } { return 0 }
6952 # AltiVec is not supported on AIX before 5.3.
6953 if { [istarget powerpc*-*-aix4*]
6954 || [istarget powerpc*-*-aix5.1*]
6955 || [istarget powerpc*-*-aix5.2*] } { return 0 }
6957 # Return true iff compiling with -maltivec does not error.
6958 return [check_no_compiler_messages powerpc_altivec_ok object {
6963 # Return 1 if this is a PowerPC target supporting -mpower8-vector
6965 proc check_effective_target_powerpc_p8vector_ok { } {
6966 if { ([istarget powerpc*-*-*]
6967 && ![istarget powerpc-*-linux*paired*])
6968 || [istarget rs6000-*-*] } {
6969 # AltiVec is not supported on AIX before 5.3.
6970 if { [istarget powerpc*-*-aix4*]
6971 || [istarget powerpc*-*-aix5.1*]
6972 || [istarget powerpc*-*-aix5.2*] } {
6975 # Darwin doesn't run on power8, so far.
6976 if { [istarget *-*-darwin*] } {
6979 return [check_no_compiler_messages powerpc_p8vector_ok object {
6981 asm volatile ("xxlorc 0,0,0");
6984 } "-mpower8-vector"]
6990 # Return 1 if this is a PowerPC target supporting -mpower9-vector
6992 proc check_effective_target_powerpc_p9vector_ok { } {
6993 if { ([istarget powerpc*-*-*]
6994 && ![istarget powerpc-*-linux*paired*])
6995 || [istarget rs6000-*-*] } {
6996 # AltiVec is not supported on AIX before 5.3.
6997 if { [istarget powerpc*-*-aix4*]
6998 || [istarget powerpc*-*-aix5.1*]
6999 || [istarget powerpc*-*-aix5.2*] } {
7002 # Darwin doesn't run on power9, so far.
7003 if { [istarget *-*-darwin*] } {
7006 return [check_no_compiler_messages powerpc_p9vector_ok object {
7009 vector double v = (vector double) { 0.0, 0.0 };
7010 asm ("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
7013 } "-mpower9-vector"]
7019 # Return 1 if this is a PowerPC target supporting -mmodulo
7021 proc check_effective_target_powerpc_p9modulo_ok { } {
7022 if { ([istarget powerpc*-*-*]
7023 && ![istarget powerpc-*-linux*paired*])
7024 || [istarget rs6000-*-*] } {
7025 # AltiVec is not supported on AIX before 5.3.
7026 if { [istarget powerpc*-*-aix4*]
7027 || [istarget powerpc*-*-aix5.1*]
7028 || [istarget powerpc*-*-aix5.2*] } {
7031 return [check_no_compiler_messages powerpc_p9modulo_ok object {
7033 int i = 5, j = 3, r = -1;
7034 asm ("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
7043 # return 1 if our compiler returns the ARCH_PWR defines with the options
7044 # as provided by the test.
7045 proc check_effective_target_has_arch_pwr5 { } {
7046 return [check_no_compiler_messages_nocache arch_pwr5 assembly {
7050 #error does not have power5 support.
7052 /* "has power5 support" */
7055 } [current_compiler_flags]]
7058 proc check_effective_target_has_arch_pwr6 { } {
7059 return [check_no_compiler_messages_nocache arch_pwr6 assembly {
7063 #error does not have power6 support.
7065 /* "has power6 support" */
7068 } [current_compiler_flags]]
7071 proc check_effective_target_has_arch_pwr7 { } {
7072 return [check_no_compiler_messages_nocache arch_pwr7 assembly {
7076 #error does not have power7 support.
7078 /* "has power7 support" */
7081 } [current_compiler_flags]]
7084 proc check_effective_target_has_arch_pwr8 { } {
7085 return [check_no_compiler_messages_nocache arch_pwr8 assembly {
7089 #error does not have power8 support.
7091 /* "has power8 support" */
7094 } [current_compiler_flags]]
7097 proc check_effective_target_has_arch_pwr9 { } {
7098 return [check_no_compiler_messages_nocache arch_pwr9 assembly {
7102 #error does not have power9 support.
7104 /* "has power9 support" */
7107 } [current_compiler_flags]]
7110 proc check_effective_target_has_arch_pwr10 { } {
7111 return [check_no_compiler_messages_nocache arch_pwr10 assembly {
7115 #error does not have power10 support.
7117 /* "has power10 support" */
7120 } [current_compiler_flags]]
7123 proc check_effective_target_has_arch_ppc64 { } {
7124 return [check_no_compiler_messages_nocache arch_ppc64 assembly {
7128 #error does not have ppc64 support.
7130 /* "has ppc64 support" */
7133 } [current_compiler_flags]]
7136 # Return 1 if this is a PowerPC target supporting -mcpu=power10.
7137 # Limit this to 64-bit linux systems for now until other targets support
7140 proc check_effective_target_power10_ok { } {
7141 if { ([istarget powerpc64*-*-linux*]) } {
7142 return [check_no_compiler_messages power10_ok object {
7145 asm ("pli %0,%1" : "=r" (e) : "n" (0x12345));
7154 # Return 1 if this is a PowerPC target supporting -mfloat128 via either
7155 # software emulation on power7/power8 systems or hardware support on power9.
7157 proc check_effective_target_powerpc_float128_sw_ok { } {
7158 if { ([istarget powerpc*-*-*]
7159 && ![istarget powerpc-*-linux*paired*])
7160 || [istarget rs6000-*-*] } {
7161 # AltiVec is not supported on AIX before 5.3.
7162 if { [istarget powerpc*-*-aix4*]
7163 || [istarget powerpc*-*-aix5.1*]
7164 || [istarget powerpc*-*-aix5.2*] } {
7167 # Darwin doesn't have VSX, so no soft support for float128.
7168 if { [istarget *-*-darwin*] } {
7171 return [check_no_compiler_messages powerpc_float128_sw_ok object {
7172 volatile __float128 x = 1.0q;
7173 volatile __float128 y = 2.0q;
7175 __float128 z = x + y;
7178 } "-mfloat128 -mvsx"]
7184 # Return 1 if this is a PowerPC target supporting -mfloat128 via hardware
7185 # support on power9.
7187 proc check_effective_target_powerpc_float128_hw_ok { } {
7188 if { ([istarget powerpc*-*-*]
7189 && ![istarget powerpc-*-linux*paired*])
7190 || [istarget rs6000-*-*] } {
7191 # AltiVec is not supported on AIX before 5.3.
7192 if { [istarget powerpc*-*-aix4*]
7193 || [istarget powerpc*-*-aix5.1*]
7194 || [istarget powerpc*-*-aix5.2*] } {
7197 # Darwin doesn't run on any machine with float128 h/w so far.
7198 if { [istarget *-*-darwin*] } {
7201 return [check_no_compiler_messages powerpc_float128_hw_ok object {
7202 volatile __float128 x = 1.0q;
7203 volatile __float128 y = 2.0q;
7206 __asm__ ("xsaddqp %0,%1,%2" : "=v" (z) : "v" (x), "v" (y));
7209 } "-mfloat128-hardware"]
7215 # Return 1 if current options define float128, 0 otherwise.
7217 proc check_effective_target_ppc_float128 { } {
7218 return [check_no_compiler_messages_nocache ppc_float128 object {
7221 #ifndef __FLOAT128__
7228 # Return 1 if current options generate float128 insns, 0 otherwise.
7230 proc check_effective_target_ppc_float128_insns { } {
7231 return [check_no_compiler_messages_nocache ppc_float128 object {
7234 #ifndef __FLOAT128_HARDWARE__
7241 # Return 1 if current options generate VSX instructions, 0 otherwise.
7243 proc check_effective_target_powerpc_vsx { } {
7244 return [check_no_compiler_messages_nocache powerpc_vsx object {
7254 # Return 1 if this is a PowerPC target supporting -mvsx
7256 proc check_effective_target_powerpc_vsx_ok { } {
7257 if { ([istarget powerpc*-*-*]
7258 && ![istarget powerpc-*-linux*paired*])
7259 || [istarget rs6000-*-*] } {
7260 # VSX is not supported on AIX before 7.1.
7261 if { [istarget powerpc*-*-aix4*]
7262 || [istarget powerpc*-*-aix5*]
7263 || [istarget powerpc*-*-aix6*] } {
7266 # Darwin doesn't have VSX, even if it's used with an assembler
7267 # which recognises the insns.
7268 if { [istarget *-*-darwin*] } {
7271 return [check_no_compiler_messages powerpc_vsx_ok object {
7273 asm volatile ("xxlor 0,0,0");
7282 # Return 1 if this is a PowerPC target supporting -mhtm
7284 proc check_effective_target_powerpc_htm_ok { } {
7285 if { ([istarget powerpc*-*-*]
7286 && ![istarget powerpc-*-linux*paired*])
7287 || [istarget rs6000-*-*] } {
7288 # HTM is not supported on AIX yet.
7289 if { [istarget powerpc*-*-aix*] } {
7292 return [check_no_compiler_messages powerpc_htm_ok object {
7294 asm volatile ("tbegin. 0");
7303 # Return 1 if the target supports executing HTM hardware instructions,
7304 # 0 otherwise. Cache the result.
7306 proc check_htm_hw_available { } {
7307 return [check_cached_effective_target htm_hw_available {
7308 # For now, disable on Darwin
7309 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
7312 check_runtime_nocache htm_hw_available {
7322 # Return 1 if this is a PowerPC target supporting -mcpu=cell.
7324 proc check_effective_target_powerpc_ppu_ok { } {
7325 if [check_effective_target_powerpc_altivec_ok] {
7326 return [check_no_compiler_messages cell_asm_available object {
7329 asm volatile ("lvlx v0,v0,v0");
7331 asm volatile ("lvlx 0,0,0");
7341 # Return 1 if this is a PowerPC target that supports SPU.
7343 proc check_effective_target_powerpc_spu { } {
7344 if { [istarget powerpc*-*-linux*] } {
7345 return [check_effective_target_powerpc_altivec_ok]
7351 # Return 1 if this is a PowerPC SPE target. The check includes options
7352 # specified by dg-options for this test, so don't cache the result.
7354 proc check_effective_target_powerpc_spe_nocache { } {
7355 if { [istarget powerpc*-*-*] } {
7356 return [check_no_compiler_messages_nocache powerpc_spe object {
7362 } [current_compiler_flags]]
7368 # Return 1 if this is a PowerPC target with SPE enabled.
7370 proc check_effective_target_powerpc_spe { } {
7371 if { [istarget powerpc*-*-*] } {
7372 return [check_no_compiler_messages powerpc_spe object {
7384 # Return 1 if this is a PowerPC target with Altivec enabled.
7386 proc check_effective_target_powerpc_altivec { } {
7387 if { [istarget powerpc*-*-*] } {
7388 return [check_no_compiler_messages powerpc_altivec object {
7400 # Return 1 if this is a PowerPC 405 target. The check includes options
7401 # specified by dg-options for this test, so don't cache the result.
7403 proc check_effective_target_powerpc_405_nocache { } {
7404 if { [istarget powerpc*-*-*] || [istarget rs6000-*-*] } {
7405 return [check_no_compiler_messages_nocache powerpc_405 object {
7411 } [current_compiler_flags]]
7417 # Return 1 if this is a PowerPC target using the ELFv2 ABI.
7419 proc check_effective_target_powerpc_elfv2 { } {
7420 if { [istarget powerpc*-*-*] } {
7421 return [check_no_compiler_messages powerpc_elfv2 object {
7423 #error not ELF v2 ABI
7433 # Return 1 if this is a PowerPC target supporting -mrop-protect
7435 proc check_effective_target_rop_ok { } {
7436 return [check_effective_target_power10_ok] && [check_effective_target_powerpc_elfv2]
7439 # The VxWorks SPARC simulator accepts only EM_SPARC executables and
7440 # chokes on EM_SPARC32PLUS or EM_SPARCV9 executables. Return 1 if the
7441 # test environment appears to run executables on such a simulator.
7443 proc check_effective_target_ultrasparc_hw { } {
7444 return [check_runtime ultrasparc_hw {
7445 int main() { return 0; }
7446 } "-mcpu=ultrasparc"]
7449 # Return 1 if the test environment supports executing UltraSPARC VIS2
7450 # instructions. We check this by attempting: "bmask %g0, %g0, %g0"
7452 proc check_effective_target_ultrasparc_vis2_hw { } {
7453 return [check_runtime ultrasparc_vis2_hw {
7454 int main() { __asm__(".word 0x81b00320"); return 0; }
7455 } "-mcpu=ultrasparc3"]
7458 # Return 1 if the test environment supports executing UltraSPARC VIS3
7459 # instructions. We check this by attempting: "addxc %g0, %g0, %g0"
7461 proc check_effective_target_ultrasparc_vis3_hw { } {
7462 return [check_runtime ultrasparc_vis3_hw {
7463 int main() { __asm__(".word 0x81b00220"); return 0; }
7467 # Return 1 if this is a SPARC-V9 target.
7469 proc check_effective_target_sparc_v9 { } {
7470 if { [istarget sparc*-*-*] } {
7471 return [check_no_compiler_messages sparc_v9 object {
7473 asm volatile ("return %i7+8");
7482 # Return 1 if this is a SPARC target with VIS enabled.
7484 proc check_effective_target_sparc_vis { } {
7485 if { [istarget sparc*-*-*] } {
7486 return [check_no_compiler_messages sparc_vis object {
7498 # Return 1 if the target supports hardware vector shift operation.
7500 proc check_effective_target_vect_shift { } {
7501 return [check_cached_effective_target_indexed vect_shift {
7502 expr {([istarget powerpc*-*-*]
7503 && ![istarget powerpc-*-linux*paired*])
7504 || [istarget ia64-*-*]
7505 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7506 || [istarget aarch64*-*-*]
7507 || [is-effective-target arm_neon]
7508 || ([istarget mips*-*-*]
7509 && ([et-is-effective-target mips_msa]
7510 || [et-is-effective-target mips_loongson_mmi]))
7511 || ([istarget s390*-*-*]
7512 && [check_effective_target_s390_vx])
7513 || [istarget amdgcn-*-*]
7514 || ([istarget riscv*-*-*]
7515 && [check_effective_target_riscv_v])
7516 || ([istarget loongarch*-*-*]
7517 && [check_effective_target_loongarch_sx]) }}]
7520 # Return 1 if the target supports hardware vector shift by register operation.
7522 proc check_effective_target_vect_var_shift { } {
7523 return [check_cached_effective_target_indexed vect_var_shift {
7524 expr {(([istarget i?86-*-*] || [istarget x86_64-*-*])
7525 && [check_avx2_available])
7526 || [istarget aarch64*-*-*]
7527 || ([istarget riscv*-*-*]
7528 && [check_effective_target_riscv_v])
7529 || ([istarget loongarch*-*-*]
7530 && [check_effective_target_loongarch_sx])
7534 proc check_effective_target_whole_vector_shift { } {
7535 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
7536 || [istarget ia64-*-*]
7537 || [istarget aarch64*-*-*]
7538 || [istarget powerpc64*-*-*]
7539 || ([is-effective-target arm_neon]
7540 && [check_effective_target_arm_little_endian])
7541 || ([istarget mips*-*-*]
7542 && [et-is-effective-target mips_loongson_mmi])
7543 || ([istarget s390*-*-*]
7544 && [check_effective_target_s390_vx])
7545 || [istarget amdgcn-*-*]
7546 || ([istarget riscv*-*-*]
7547 && [check_effective_target_riscv_v])
7548 || ([istarget loongarch*-*-*]
7549 && [check_effective_target_loongarch_sx]) } {
7555 verbose "check_effective_target_vect_long: returning $answer" 2
7559 # Return 1 if the target supports vector bswap operations.
7561 proc check_effective_target_vect_bswap { } {
7562 return [check_cached_effective_target_indexed vect_bswap {
7563 expr { ([istarget aarch64*-*-*]
7564 || [is-effective-target arm_neon]
7565 || [istarget amdgcn-*-*])
7566 || [istarget loongarch*-*-*]
7567 || ([istarget s390*-*-*]
7568 && [check_effective_target_s390_vx]) }}]
7571 # Return 1 if the target supports comparison of bool vectors for at
7572 # least one vector length.
7574 proc check_effective_target_vect_bool_cmp { } {
7575 return [check_cached_effective_target_indexed vect_bool_cmp {
7576 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7577 || [istarget aarch64*-*-*]
7578 || [is-effective-target arm_neon]
7579 || ([istarget riscv*-*-*]
7580 && [check_effective_target_riscv_v])
7581 || ([istarget loongarch*-*-*]
7582 && [check_effective_target_loongarch_sx]) }}]
7585 # Return 1 if the target supports addition of char vectors for at least
7586 # one vector length.
7588 proc check_effective_target_vect_char_add { } {
7589 return [check_cached_effective_target_indexed vect_char_add {
7591 [istarget i?86-*-*] || [istarget x86_64-*-*]
7592 || ([istarget powerpc*-*-*]
7593 && ![istarget powerpc-*-linux*paired*])
7594 || [istarget amdgcn-*-*]
7595 || [istarget ia64-*-*]
7596 || [istarget aarch64*-*-*]
7597 || [is-effective-target arm_neon]
7598 || ([istarget mips*-*-*]
7599 && ([et-is-effective-target mips_loongson_mmi]
7600 || [et-is-effective-target mips_msa]))
7601 || ([istarget s390*-*-*]
7602 && [check_effective_target_s390_vx])
7603 || ([istarget riscv*-*-*]
7604 && [check_effective_target_riscv_v])
7605 || ([istarget loongarch*-*-*]
7606 && [check_effective_target_loongarch_sx])
7610 # Return 1 if the target supports hardware vector shift operation for char.
7612 proc check_effective_target_vect_shift_char { } {
7613 return [check_cached_effective_target_indexed vect_shift_char {
7614 expr { ([istarget powerpc*-*-*]
7615 && ![istarget powerpc-*-linux*paired*])
7616 || [is-effective-target arm_neon]
7617 || ([istarget mips*-*-*]
7618 && [et-is-effective-target mips_msa])
7619 || ([istarget s390*-*-*]
7620 && [check_effective_target_s390_vx])
7621 || [istarget amdgcn-*-*]
7622 || ([istarget riscv*-*-*]
7623 && [check_effective_target_riscv_v])
7624 || ([istarget loongarch*-*-*]
7625 && [check_effective_target_loongarch_sx]) }}]
7628 # Return 1 if the target supports hardware vectors of long, 0 otherwise.
7630 # This can change for different subtargets so do not cache the result.
7632 proc check_effective_target_vect_long { } {
7633 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
7634 || (([istarget powerpc*-*-*]
7635 && ![istarget powerpc-*-linux*paired*])
7636 && [check_effective_target_ilp32])
7637 || [is-effective-target arm_neon]
7638 || ([istarget sparc*-*-*] && [check_effective_target_ilp32])
7639 || [istarget aarch64*-*-*]
7640 || ([istarget mips*-*-*]
7641 && [et-is-effective-target mips_msa])
7642 || ([istarget s390*-*-*]
7643 && [check_effective_target_s390_vx])
7644 || [istarget amdgcn-*-*]
7645 || ([istarget riscv*-*-*]
7646 && [check_effective_target_riscv_v])
7647 || ([istarget loongarch*-*-*]
7648 && [check_effective_target_loongarch_sx]) } {
7654 verbose "check_effective_target_vect_long: returning $answer" 2
7658 # Return 1 if the target supports hardware vectors of float when
7659 # -funsafe-math-optimizations is enabled, 0 otherwise.
7661 # This won't change for different subtargets so cache the result.
7663 proc check_effective_target_vect_float { } {
7664 return [check_cached_effective_target_indexed vect_float {
7665 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7666 || [istarget powerpc*-*-*]
7667 || [istarget mips-sde-elf]
7668 || [istarget mipsisa64*-*-*]
7669 || [istarget ia64-*-*]
7670 || [istarget aarch64*-*-*]
7671 || ([istarget mips*-*-*]
7672 && [et-is-effective-target mips_msa])
7673 || [is-effective-target arm_neon]
7674 || ([istarget s390*-*-*]
7675 && [check_effective_target_s390_vxe])
7676 || [istarget amdgcn-*-*]
7677 || ([istarget riscv*-*-*]
7678 && [check_effective_target_riscv_v])
7679 || ([istarget loongarch*-*-*]
7680 && [check_effective_target_loongarch_sx]) }}]
7683 # Return 1 if the target supports hardware vectors of float without
7684 # -funsafe-math-optimizations being enabled, 0 otherwise.
7686 proc check_effective_target_vect_float_strict { } {
7687 return [expr { [check_effective_target_vect_float]
7688 && ![istarget arm*-*-*] }]
7691 # Return 1 if the target supports hardware vectors of double, 0 otherwise.
7693 # This won't change for different subtargets so cache the result.
7695 proc check_effective_target_vect_double { } {
7696 return [check_cached_effective_target_indexed vect_double {
7697 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
7698 && [check_no_compiler_messages vect_double assembly {
7699 #ifdef __tune_atom__
7700 # error No double vectorizer support.
7703 || [istarget aarch64*-*-*]
7704 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
7705 || ([istarget mips*-*-*]
7706 && [et-is-effective-target mips_msa])
7707 || ([istarget s390*-*-*]
7708 && [check_effective_target_s390_vx])
7709 || [istarget amdgcn-*-*]
7710 || ([istarget riscv*-*-*]
7711 && [check_effective_target_riscv_v])
7712 || ([istarget loongarch*-*-*]
7713 && [check_effective_target_loongarch_sx]) }}]
7716 # Return 1 if the target supports conditional addition, subtraction,
7717 # multiplication, division, minimum and maximum on vectors of double,
7718 # via the cond_ optabs. Return 0 otherwise.
7720 proc check_effective_target_vect_double_cond_arith { } {
7721 return [expr { [check_effective_target_aarch64_sve]
7722 || [check_effective_target_riscv_v] }]
7725 # Return 1 if the target supports hardware vectors of long long, 0 otherwise.
7727 # This won't change for different subtargets so cache the result.
7729 proc check_effective_target_vect_long_long { } {
7730 return [check_cached_effective_target_indexed vect_long_long {
7731 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7732 || ([istarget mips*-*-*]
7733 && [et-is-effective-target mips_msa])
7734 || ([istarget s390*-*-*]
7735 && [check_effective_target_s390_vx])
7736 || ([istarget powerpc*-*-*]
7737 && ![istarget powerpc-*-linux*paired*]
7738 && [check_effective_target_has_arch_pwr8])
7739 || [istarget aarch64*-*-*]
7740 || ([istarget riscv*-*-*]
7741 && [check_effective_target_riscv_v])
7742 || ([istarget loongarch*-*-*]
7743 && [check_effective_target_loongarch_sx])}}]
7747 # Return 1 if the target plus current options does not support a vector
7748 # max instruction on "int", 0 otherwise.
7750 # This won't change for different subtargets so cache the result.
7752 proc check_effective_target_vect_no_int_min_max { } {
7753 return [check_cached_effective_target_indexed vect_no_int_min_max {
7754 expr { [istarget sparc*-*-*]
7755 || [istarget alpha*-*-*]
7756 || ([istarget mips*-*-*]
7757 && [et-is-effective-target mips_loongson_mmi]) }}]
7760 # Return 1 if the target plus current options does not support a vector
7761 # add instruction on "int", 0 otherwise.
7763 # This won't change for different subtargets so cache the result.
7765 proc check_effective_target_vect_no_int_add { } {
7766 # Alpha only supports vector add on V8QI and V4HI.
7767 return [check_cached_effective_target_indexed vect_no_int_add {
7768 expr { [istarget alpha*-*-*] }}]
7771 # Return 1 if the target plus current options does not support vector
7772 # bitwise instructions, 0 otherwise.
7774 # This won't change for different subtargets so cache the result.
7776 proc check_effective_target_vect_no_bitwise { } {
7777 return [check_cached_effective_target_indexed vect_no_bitwise { return 0 }]
7780 # Return 1 if the target plus current options supports vector permutation,
7783 # This won't change for different subtargets so cache the result.
7785 proc check_effective_target_vect_perm { } {
7786 return [check_cached_effective_target_indexed vect_perm {
7787 expr { [is-effective-target arm_neon]
7788 || [istarget aarch64*-*-*]
7789 || [istarget powerpc*-*-*]
7790 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7791 || ([istarget mips*-*-*]
7792 && ([et-is-effective-target mpaired_single]
7793 || [et-is-effective-target mips_msa]))
7794 || ([istarget s390*-*-*]
7795 && [check_effective_target_s390_vx])
7796 || [istarget amdgcn-*-*]
7797 || ([istarget riscv*-*-*]
7798 && [check_effective_target_riscv_v])
7799 || ([istarget loongarch*-*-*]
7800 && [check_effective_target_loongarch_sx]) }}]
7803 # Return 1 if, for some VF:
7805 # - the target's default vector size is VF * ELEMENT_BITS bits
7807 # - it is possible to implement the equivalent of:
7809 # int<ELEMENT_BITS>_t s1[COUNT][COUNT * VF], s2[COUNT * VF];
7810 # for (int i = 0; i < COUNT; ++i)
7811 # for (int j = 0; j < COUNT * VF; ++j)
7812 # s1[i][j] = s2[j - j % COUNT + i]
7814 # using only a single 2-vector permute for each vector in s1.
7816 # E.g. for COUNT == 3 and vector length 4, the two arrays would be:
7818 # s2 | a0 a1 a2 a3 | b0 b1 b2 b3 | c0 c1 c2 c3
7819 # ------+-------------+-------------+------------
7820 # s1[0] | a0 a0 a0 a3 | a3 a3 b2 b2 | b2 c1 c1 c1
7821 # s1[1] | a1 a1 a1 b0 | b0 b0 b3 b3 | b3 c2 c2 c2
7822 # s1[2] | a2 a2 a2 b1 | b1 b1 c0 c0 | c0 c3 c3 c3
7824 # Each s1 permute requires only two of a, b and c.
7826 # The distance between the start of vector n in s1[0] and the start
7827 # of vector n in s2 is:
7829 # A = (n * VF) % COUNT
7831 # The corresponding value for the end of vector n is:
7833 # B = (n * VF + VF - 1) % COUNT
7835 # Subtracting i from each value gives the corresponding difference
7836 # for s1[i]. The condition being tested by this function is false
7837 # iff A - i > 0 and B - i < 0 for some i and n, such that the first
7838 # element for s1[i] comes from vector n - 1 of s2 and the last element
7839 # comes from vector n + 1 of s2. The condition is therefore true iff
7840 # A <= B for all n. This is turn means the condition is true iff:
7842 # (n * VF) % COUNT + (VF - 1) % COUNT < COUNT
7844 # for all n. COUNT - (n * VF) % COUNT is bounded by gcd (VF, COUNT),
7845 # and will be that value for at least one n in [0, COUNT), so we want:
7847 # (VF - 1) % COUNT < gcd (VF, COUNT)
7849 proc vect_perm_supported { count element_bits } {
7850 set vector_bits [lindex [available_vector_sizes] 0]
7851 # The number of vectors has to be a power of 2 when permuting
7852 # variable-length vectors.
7853 if { $vector_bits <= 0 && ($count & -$count) != $count } {
7856 set vf [expr { $vector_bits / $element_bits }]
7858 # Compute gcd (VF, COUNT).
7861 while { $temp1 > 0 } {
7862 set temp2 [expr { $gcd % $temp1 }]
7866 return [expr { ($vf - 1) % $count < $gcd }]
7869 # Return 1 if the target supports SLP permutation of 3 vectors when each
7870 # element has 32 bits.
7872 proc check_effective_target_vect_perm3_int { } {
7873 return [expr { [check_effective_target_vect_perm]
7874 && [vect_perm_supported 3 32] }]
7877 # Return 1 if the target plus current options supports vector permutation
7878 # on byte-sized elements, 0 otherwise.
7880 # This won't change for different subtargets so cache the result.
7882 proc check_effective_target_vect_perm_byte { } {
7883 return [check_cached_effective_target_indexed vect_perm_byte {
7884 expr { ([is-effective-target arm_neon]
7885 && [is-effective-target arm_little_endian])
7886 || ([istarget aarch64*-*-*]
7887 && [is-effective-target aarch64_little_endian])
7888 || [istarget powerpc*-*-*]
7889 || ([istarget mips-*.*]
7890 && [et-is-effective-target mips_msa])
7891 || ([istarget s390*-*-*]
7892 && [check_effective_target_s390_vx])
7893 || [istarget amdgcn-*-*]
7894 || ([istarget riscv*-*-*]
7895 && [check_effective_target_riscv_v])
7896 || ([istarget loongarch*-*-*]
7897 && [check_effective_target_loongarch_sx]) }}]
7900 # Return 1 if the target supports SLP permutation of 3 vectors when each
7901 # element has 8 bits.
7903 proc check_effective_target_vect_perm3_byte { } {
7904 return [expr { [check_effective_target_vect_perm_byte]
7905 && [vect_perm_supported 3 8] }]
7908 # Return 1 if the target plus current options supports vector permutation
7909 # on short-sized elements, 0 otherwise.
7911 # This won't change for different subtargets so cache the result.
7913 proc check_effective_target_vect_perm_short { } {
7914 return [check_cached_effective_target_indexed vect_perm_short {
7915 expr { ([is-effective-target arm_neon]
7916 && [is-effective-target arm_little_endian])
7917 || ([istarget aarch64*-*-*]
7918 && [is-effective-target aarch64_little_endian])
7919 || [istarget powerpc*-*-*]
7920 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
7921 && [check_ssse3_available])
7922 || ([istarget mips*-*-*]
7923 && [et-is-effective-target mips_msa])
7924 || ([istarget s390*-*-*]
7925 && [check_effective_target_s390_vx])
7926 || [istarget amdgcn-*-*]
7927 || ([istarget riscv*-*-*]
7928 && [check_effective_target_riscv_v])
7929 || ([istarget loongarch*-*-*]
7930 && [check_effective_target_loongarch_sx]) }}]
7933 # Return 1 if the target supports SLP permutation of 3 vectors when each
7934 # element has 16 bits.
7936 proc check_effective_target_vect_perm3_short { } {
7937 return [expr { [check_effective_target_vect_perm_short]
7938 && [vect_perm_supported 3 16] }]
7941 # Return 1 if the target plus current options supports folding of
7942 # copysign into XORSIGN.
7944 # This won't change for different subtargets so cache the result.
7946 proc check_effective_target_xorsign { } {
7947 return [check_cached_effective_target_indexed xorsign {
7948 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7949 || [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
7952 # Return 1 if the target plus current options supports folding of
7953 # copysign into IFN_COPYSIGN.
7955 # This won't change for different subtargets so cache the result.
7957 proc check_effective_target_ifn_copysign { } {
7958 return [check_cached_effective_target_indexed ifn_copysign {
7960 (([istarget i?86-*-*] || [istarget x86_64-*-*])
7961 && [is-effective-target sse])
7962 || ([istarget loongarch*-*-*]
7963 && [check_effective_target_hard_float])
7964 || ([istarget powerpc*-*-*]
7965 && ![istarget powerpc-*-linux*paired*])
7966 || [istarget alpha*-*-*]
7967 || [istarget aarch64*-*-*]
7968 || [is-effective-target arm_neon]
7969 || ([istarget s390*-*-*]
7970 && [check_effective_target_s390_vx])
7971 || ([istarget riscv*-*-*]
7972 && [check_effective_target_hard_float])
7976 # Return 1 if the target plus current options supports a vector
7977 # widening summation of *short* args into *int* result, 0 otherwise.
7979 # This won't change for different subtargets so cache the result.
7981 proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
7982 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si_pattern {
7983 expr { [istarget powerpc*-*-*]
7984 || ([istarget aarch64*-*-*]
7985 && ![check_effective_target_aarch64_sve])
7986 || [is-effective-target arm_neon]
7987 || [istarget ia64-*-*] }}]
7990 # Return 1 if the target plus current options supports a vector
7991 # widening summation of *short* args into *int* result, 0 otherwise.
7992 # A target can also support this widening summation if it can support
7993 # promotion (unpacking) from shorts to ints.
7995 # This won't change for different subtargets so cache the result.
7997 proc check_effective_target_vect_widen_sum_hi_to_si { } {
7998 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si {
7999 expr { [check_effective_target_vect_unpack]
8000 || [istarget powerpc*-*-*]
8001 || [istarget ia64-*-*]
8002 || [istarget loongarch*-*-*]
8003 || [istarget riscv*-*-*] }}]
8006 # Return 1 if the target plus current options supports a vector
8007 # widening summation of *char* args into *short* result, 0 otherwise.
8008 # A target can also support this widening summation if it can support
8009 # promotion (unpacking) from chars to shorts.
8011 # This won't change for different subtargets so cache the result.
8013 proc check_effective_target_vect_widen_sum_qi_to_hi { } {
8014 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi {
8015 expr { [check_effective_target_vect_unpack]
8016 || [is-effective-target arm_neon]
8017 || [istarget ia64-*-*]
8018 || [istarget riscv*-*-*]
8019 || [istarget loongarch*-*-*] }}]
8022 # Return 1 if the target plus current options supports a vector
8023 # widening summation of *char* args into *int* result, 0 otherwise.
8025 # This won't change for different subtargets so cache the result.
8027 proc check_effective_target_vect_widen_sum_qi_to_si { } {
8028 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
8029 expr { [istarget powerpc*-*-*]
8030 || [istarget loongarch*-*-*]
8031 || [istarget riscv*-*-*] }}]
8034 # Return 1 if the target plus current options supports a vector
8035 # widening multiplication of *char* args into *short* result, 0 otherwise.
8036 # A target can also support this widening multplication if it can support
8037 # promotion (unpacking) from chars to shorts, and vect_short_mult (non-widening
8038 # multiplication of shorts).
8040 # This won't change for different subtargets so cache the result.
8043 proc check_effective_target_vect_widen_mult_qi_to_hi { } {
8044 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi {
8045 expr { ([check_effective_target_vect_unpack]
8046 && [check_effective_target_vect_short_mult])
8047 || ([istarget powerpc*-*-*]
8048 || ([istarget aarch64*-*-*]
8049 && ![check_effective_target_aarch64_sve])
8050 || [is-effective-target arm_neon]
8051 || ([istarget s390*-*-*]
8052 && [check_effective_target_s390_vx]))
8053 || [istarget amdgcn-*-*] }}]
8056 # Return 1 if the target plus current options supports a vector
8057 # widening multiplication of *short* args into *int* result, 0 otherwise.
8058 # A target can also support this widening multplication if it can support
8059 # promotion (unpacking) from shorts to ints, and vect_int_mult (non-widening
8060 # multiplication of ints).
8062 # This won't change for different subtargets so cache the result.
8065 proc check_effective_target_vect_widen_mult_hi_to_si { } {
8066 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si {
8067 expr { ([check_effective_target_vect_unpack]
8068 && [check_effective_target_vect_int_mult])
8069 || ([istarget powerpc*-*-*]
8070 || [istarget ia64-*-*]
8071 || ([istarget aarch64*-*-*]
8072 && ![check_effective_target_aarch64_sve])
8073 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8074 || [is-effective-target arm_neon]
8075 || ([istarget s390*-*-*]
8076 && [check_effective_target_s390_vx]))
8077 || [istarget amdgcn-*-*] }}]
8080 # Return 1 if the target plus current options supports a vector
8081 # widening multiplication of *char* args into *short* result, 0 otherwise.
8083 # This won't change for different subtargets so cache the result.
8085 proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
8086 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi_pattern {
8087 expr { [istarget powerpc*-*-*]
8088 || ([is-effective-target arm_neon]
8089 && [check_effective_target_arm_little_endian])
8090 || ([istarget s390*-*-*]
8091 && [check_effective_target_s390_vx])
8092 || [istarget loongarch*-*-*]
8093 || [istarget amdgcn-*-*] }}]
8096 # Return 1 if the target plus current options supports a vector
8097 # widening multiplication of *short* args into *int* result, 0 otherwise.
8099 # This won't change for different subtargets so cache the result.
8101 proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
8102 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern {
8103 expr { [istarget powerpc*-*-*]
8104 || [istarget ia64-*-*]
8105 || [istarget loongarch*-*-*]
8106 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8107 || ([is-effective-target arm_neon]
8108 && [check_effective_target_arm_little_endian])
8109 || ([istarget s390*-*-*]
8110 && [check_effective_target_s390_vx])
8111 || [istarget amdgcn-*-*] }}]
8114 # Return 1 if the target plus current options supports a vector
8115 # widening multiplication of *int* args into *long* result, 0 otherwise.
8117 # This won't change for different subtargets so cache the result.
8119 proc check_effective_target_vect_widen_mult_si_to_di_pattern { } {
8120 return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern {
8121 expr { [istarget ia64-*-*]
8122 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8123 || [istarget loongarch*-*-*]
8124 || ([istarget s390*-*-*]
8125 && [check_effective_target_s390_vx]) }}]
8128 # Return 1 if the target plus current options supports a vector
8129 # widening shift, 0 otherwise.
8131 # This won't change for different subtargets so cache the result.
8133 proc check_effective_target_vect_widen_shift { } {
8134 return [check_cached_effective_target_indexed vect_widen_shift {
8135 expr { [is-effective-target arm_neon] }}]
8138 # Return 1 if the target plus current options supports a vector
8139 # dot-product of signed chars, 0 otherwise.
8141 # This won't change for different subtargets so cache the result.
8143 proc check_effective_target_vect_sdot_qi { } {
8144 return [check_cached_effective_target_indexed vect_sdot_qi {
8145 expr { [istarget ia64-*-*]
8146 || [istarget aarch64*-*-*]
8147 || [istarget arm*-*-*]
8148 || ([istarget mips*-*-*]
8149 && [et-is-effective-target mips_msa])
8150 || ([istarget riscv*-*-*]
8151 && [check_effective_target_riscv_v])
8152 || ([istarget loongarch*-*-*]
8153 && [check_effective_target_loongarch_sx]) }}]
8156 # Return 1 if the target plus current options supports a vector
8157 # dot-product of unsigned chars, 0 otherwise.
8159 # This won't change for different subtargets so cache the result.
8161 proc check_effective_target_vect_udot_qi { } {
8162 return [check_cached_effective_target_indexed vect_udot_qi {
8163 expr { [istarget powerpc*-*-*]
8164 || [istarget aarch64*-*-*]
8165 || [istarget arm*-*-*]
8166 || [istarget ia64-*-*]
8167 || ([istarget mips*-*-*]
8168 && [et-is-effective-target mips_msa])
8169 || ([istarget riscv*-*-*]
8170 && [check_effective_target_riscv_v])
8171 || ([istarget loongarch*-*-*]
8172 && [check_effective_target_loongarch_sx]) }}]
8175 # Return 1 if the target plus current options supports a vector
8176 # dot-product where one operand of the multiply is signed char
8177 # and the other unsigned chars, 0 otherwise.
8179 # This won't change for different subtargets so cache the result.
8181 proc check_effective_target_vect_usdot_qi { } {
8182 return [check_cached_effective_target_indexed vect_usdot_qi {
8183 expr { [istarget aarch64*-*-*]
8184 || [istarget arm*-*-*] }}]
8188 # Return 1 if the target plus current options supports a vector
8189 # dot-product of signed shorts, 0 otherwise.
8191 # This won't change for different subtargets so cache the result.
8193 proc check_effective_target_vect_sdot_hi { } {
8194 return [check_cached_effective_target_indexed vect_sdot_hi {
8195 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8196 || [istarget ia64-*-*]
8197 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8198 || ([istarget mips*-*-*]
8199 && [et-is-effective-target mips_msa])
8200 || ([istarget riscv*-*-*]
8201 && [check_effective_target_riscv_v])
8202 || ([istarget loongarch*-*-*]
8203 && [check_effective_target_loongarch_sx]) }}]
8206 # Return 1 if the target plus current options supports a vector
8207 # dot-product of unsigned shorts, 0 otherwise.
8209 # This won't change for different subtargets so cache the result.
8211 proc check_effective_target_vect_udot_hi { } {
8212 return [check_cached_effective_target_indexed vect_udot_hi {
8213 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8214 || ([istarget mips*-*-*]
8215 && [et-is-effective-target mips_msa])
8216 || ([istarget riscv*-*-*]
8217 && [check_effective_target_riscv_v])
8218 || ([istarget loongarch*-*-*]
8219 && [check_effective_target_loongarch_sx]) }}]
8222 # Return 1 if the target plus current options supports a vector
8223 # sad operation of unsigned chars, 0 otherwise.
8225 # This won't change for different subtargets so cache the result.
8227 proc check_effective_target_vect_usad_char { } {
8228 return [check_cached_effective_target_indexed vect_usad_char {
8229 expr { [istarget i?86-*-*]
8230 || [istarget x86_64-*-*]
8231 || ([istarget aarch64*-*-*]
8232 && ![check_effective_target_aarch64_sve])
8233 || ([istarget powerpc*-*-*]
8234 && [check_p9vector_hw_available])
8235 || ([istarget riscv*-*-*]
8236 && [check_effective_target_riscv_v])
8237 || ([istarget loongarch*-*-*]
8238 && [check_effective_target_loongarch_sx]) }}]
8241 # Return 1 if the target plus current options supports both signed
8242 # and unsigned average operations on vectors of bytes.
8244 proc check_effective_target_vect_avg_qi {} {
8245 return [expr { ([istarget aarch64*-*-*]
8246 && ![check_effective_target_aarch64_sve1_only])
8247 || ([istarget riscv*-*-*]
8248 && [check_effective_target_riscv_v])
8249 || ([istarget loongarch*-*-*]
8250 && [check_effective_target_loongarch_sx]) }]
8253 # Return 1 if the target plus current options supports both signed
8254 # and unsigned multiply-high-with-round-and-scale operations
8255 # on vectors of half-words.
8257 proc check_effective_target_vect_mulhrs_hi {} {
8258 return [expr { [istarget aarch64*-*-*]
8259 && [check_effective_target_aarch64_sve2] }]
8262 # Return 1 if the target plus current options supports signed division
8263 # by power-of-2 operations on vectors of 4-byte integers.
8265 proc check_effective_target_vect_sdiv_pow2_si {} {
8266 return [expr { ([istarget aarch64*-*-*]
8267 && [check_effective_target_aarch64_sve]) }]
8270 # Return 1 if the target plus current options supports a vector
8271 # demotion (packing) of shorts (to chars) and ints (to shorts)
8272 # using modulo arithmetic, 0 otherwise.
8274 # This won't change for different subtargets so cache the result.
8276 proc check_effective_target_vect_pack_trunc { } {
8277 return [check_cached_effective_target_indexed vect_pack_trunc {
8278 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8279 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8280 || [istarget aarch64*-*-*]
8281 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8282 && [check_effective_target_arm_little_endian])
8283 || ([istarget mips*-*-*]
8284 && [et-is-effective-target mips_msa])
8285 || ([istarget s390*-*-*]
8286 && [check_effective_target_s390_vx])
8287 || [istarget amdgcn*-*-*]
8288 || ([istarget riscv*-*-*]
8289 && [check_effective_target_riscv_v])
8290 || ([istarget loongarch*-*-*]
8291 && [check_effective_target_loongarch_sx]) }}]
8294 # Return 1 if the target plus current options supports a vector
8295 # promotion (unpacking) of chars (to shorts) and shorts (to ints), 0 otherwise.
8297 # This won't change for different subtargets so cache the result.
8299 proc check_effective_target_vect_unpack { } {
8300 return [check_cached_effective_target_indexed vect_unpack {
8301 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
8302 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8303 || [istarget ia64-*-*]
8304 || [istarget aarch64*-*-*]
8305 || ([istarget mips*-*-*]
8306 && [et-is-effective-target mips_msa])
8307 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8308 && [check_effective_target_arm_little_endian])
8309 || ([istarget s390*-*-*]
8310 && [check_effective_target_s390_vx])
8311 || [istarget amdgcn*-*-*]
8312 || ([istarget riscv*-*-*]
8313 && [check_effective_target_riscv_v])
8314 || ([istarget loongarch*-*-*]
8315 && [check_effective_target_loongarch_sx]) }}]
8318 # Return 1 if the target plus current options does not guarantee
8319 # that its STACK_BOUNDARY is >= the reguired vector alignment.
8321 # This won't change for different subtargets so cache the result.
8323 proc check_effective_target_unaligned_stack { } {
8324 return [check_cached_effective_target_indexed unaligned_stack { expr 0 }]
8327 # Return 1 if the target plus current options does not support a vector
8328 # alignment mechanism, 0 otherwise.
8330 # This won't change for different subtargets so cache the result.
8332 proc check_effective_target_vect_no_align { } {
8333 return [check_cached_effective_target_indexed vect_no_align {
8334 expr { [istarget mipsisa64*-*-*]
8335 || [istarget mips-sde-elf]
8336 || [istarget sparc*-*-*]
8337 || [istarget ia64-*-*]
8338 || [check_effective_target_arm_vect_no_misalign]
8339 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8340 || ([istarget mips*-*-*]
8341 && [et-is-effective-target mips_loongson_mmi]) }}]
8344 # Return 1 if the target supports a vector misalign access, 0 otherwise.
8346 # This won't change for different subtargets so cache the result.
8348 proc check_effective_target_vect_hw_misalign { } {
8349 return [check_cached_effective_target_indexed vect_hw_misalign {
8350 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
8351 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8352 || [istarget aarch64*-*-*]
8353 || ([istarget mips*-*-*] && [et-is-effective-target mips_msa])
8354 || ([istarget s390*-*-*]
8355 && [check_effective_target_s390_vx])
8356 || ([istarget riscv*-*-*])
8357 || ([istarget loongarch*-*-*]) } {
8360 if { [istarget arm*-*-*]
8361 && ![check_effective_target_arm_vect_no_misalign] } {
8369 # Return 1 if arrays are aligned to the vector alignment
8370 # boundary, 0 otherwise.
8372 proc check_effective_target_vect_aligned_arrays { } {
8373 set et_vect_aligned_arrays 0
8374 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
8375 && !([is-effective-target ia32]
8376 || ([check_avx_available] && ![check_prefer_avx128]))) } {
8377 set et_vect_aligned_arrays 1
8380 verbose "check_effective_target_vect_aligned_arrays:\
8381 returning $et_vect_aligned_arrays" 2
8382 return $et_vect_aligned_arrays
8385 # Return 1 if the biggest alignment required by target is 1 * BITS_PER_UNIT.
8386 # In such case the target does not impose any alignment constraints.
8388 proc check_effective_target_no_alignment_constraints { } {
8389 return [check_runtime_nocache no_alignment_constraints {
8393 return __BIGGEST_ALIGNMENT__ == 1 ? 0 : 1;
8398 # Return 1 if types of size 32 bit or less are naturally aligned
8399 # (aligned to their type-size), 0 otherwise.
8401 # This won't change for different subtargets so cache the result.
8403 proc check_effective_target_natural_alignment_32 { } {
8404 # FIXME: 32bit powerpc: guaranteed only if MASK_ALIGN_NATURAL/POWER.
8405 # FIXME: m68k has -malign-int
8406 return [check_cached_effective_target_indexed natural_alignment_32 {
8407 if { ([istarget *-*-darwin*] && [is-effective-target lp64])
8408 || [istarget avr-*-*]
8409 || [istarget m68k-*-linux*]
8410 || [istarget pru-*-*]
8411 || [istarget stormy16-*-*]
8412 || [istarget rl78-*-*]
8413 || [istarget pdp11-*-*]
8414 || [istarget msp430-*-*]
8415 || [istarget m32c-*-*]
8416 || [istarget cris-*-*] } {
8424 # Return 1 if types of size 64 bit or less are naturally aligned (aligned to their
8425 # type-size), 0 otherwise.
8427 # This won't change for different subtargets so cache the result.
8429 proc check_effective_target_natural_alignment_64 { } {
8430 return [check_cached_effective_target_indexed natural_alignment_64 {
8431 expr { [is-effective-target natural_alignment_32]
8432 && [is-effective-target lp64] && ![istarget *-*-darwin*] }
8436 # Return 1 if all vector types are naturally aligned (aligned to their
8437 # type-size), 0 otherwise.
8439 proc check_effective_target_vect_natural_alignment { } {
8440 set et_vect_natural_alignment 1
8441 if { [check_effective_target_arm_eabi]
8442 || [istarget nvptx-*-*]
8443 || [istarget s390*-*-*]
8444 || [istarget amdgcn-*-*] } {
8445 set et_vect_natural_alignment 0
8447 verbose "check_effective_target_vect_natural_alignment:\
8448 returning $et_vect_natural_alignment" 2
8449 return $et_vect_natural_alignment
8452 # Return true if the target supports the check_raw_ptrs and check_war_ptrs
8453 # optabs on vectors.
8455 proc check_effective_target_vect_check_ptrs { } {
8456 return [check_effective_target_aarch64_sve2]
8459 # Return true if fully-masked loops are supported.
8461 proc check_effective_target_vect_fully_masked { } {
8462 return [expr { [check_effective_target_aarch64_sve]
8463 || [istarget amdgcn*-*-*]
8464 || [check_effective_target_riscv_v] }]
8467 # Return true if the target supports the @code{len_load} and
8468 # @code{len_store} optabs.
8470 proc check_effective_target_vect_len_load_store { } {
8471 return [expr { [check_effective_target_has_arch_pwr9]
8472 || [check_effective_target_s390_vx]
8473 || [check_effective_target_riscv_v] }]
8476 # Return the value of parameter vect-partial-vector-usage specified for
8477 # target by checking the output of "-Q --help=params". Return zero if
8478 # the desirable pattern isn't found.
8480 proc check_vect_partial_vector_usage { } {
8483 return [check_cached_effective_target vect_partial_vector_usage {
8484 set result [check_compile vect_partial_vector_usage assembly {
8486 } "-Q --help=params" ]
8488 # Get compiler emitted messages and delete generated file.
8489 set lines [lindex $result 0]
8490 set output [lindex $result 1]
8491 remote_file build delete $output
8493 set pattern {=vect-partial-vector-usage=<0,2>\s+([0-2])}
8494 # Capture the usage value to val, set it to zero if not found.
8495 if { ![regexp $pattern $lines whole val] } then {
8503 # Return true if the target supports loop vectorization with partial vectors
8504 # and @code{vect-partial-vector-usage} is set to 1.
8506 proc check_effective_target_vect_partial_vectors_usage_1 { } {
8507 return [expr { ([check_effective_target_vect_fully_masked]
8508 || [check_effective_target_vect_len_load_store])
8509 && [check_vect_partial_vector_usage] == 1 }]
8512 # Return true if the target supports loop vectorization with partial vectors
8513 # and @code{vect-partial-vector-usage} is set to 2.
8515 proc check_effective_target_vect_partial_vectors_usage_2 { } {
8516 return [expr { ([check_effective_target_vect_fully_masked]
8517 || [check_effective_target_vect_len_load_store])
8518 && [check_vect_partial_vector_usage] == 2 }]
8521 # Return true if the target supports loop vectorization with partial vectors
8522 # and @code{vect-partial-vector-usage} is nonzero.
8524 proc check_effective_target_vect_partial_vectors { } {
8525 return [expr { ([check_effective_target_vect_fully_masked]
8526 || [check_effective_target_vect_len_load_store])
8527 && [check_vect_partial_vector_usage] != 0 }]
8530 # Return 1 if the target doesn't prefer any alignment beyond element
8531 # alignment during vectorization.
8533 proc check_effective_target_vect_element_align_preferred { } {
8534 return [expr { ([check_effective_target_aarch64_sve]
8535 && [check_effective_target_vect_variable_length])
8536 || [check_effective_target_riscv_v] }]
8539 # Return true if vectorization of v2qi/v4qi/v8qi/v16qi/v2hi store is enabed.
8540 # Return zero if the desirable pattern isn't found.
8541 # It's used by Warray-bounds/Wstringop-overflow testcases which are
8542 # regressed by O2 vectorization, refer to PR102697/PR102462/PR102706
8543 proc check_vect_slp_store_usage { pattern macro } {
8546 set result [check_compile slp_aligned_store_usage assembly {
8547 extern void sink (void* );
8548 #define Ac8 (AC8){ 0, 1, 2, 3, 4, 5, 6, 7 }
8549 #define Ac16 (AC16){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
8551 typedef struct AC16 { char a[16]; } AC16;
8552 extern char a16[16];
8559 typedef struct AC8 { char a[8]; } AC8;
8573 extern void sink (void*);
8577 struct A1 a = { 0, { } };
8594 #define Ac4 (AC4){ 0, 1, 2, 3 }
8595 typedef struct AC4 { char a[4]; } AC4;
8643 *(short*) (b + 2) = 1;
8652 foo4_2 (struct Ax *p)
8658 struct A { int i; };
8659 struct B { int j; struct A a[4]; };
8666 char cbuf2[2 * sizeof (struct C)] = { };
8670 struct C *p = (struct C*)&cbuf2;
8677 struct A { int i; };
8678 struct B { int j; struct A a[2]; };
8685 char cbuf2[2 * sizeof (struct C)] = { };
8689 struct C *p = (struct C*)&cbuf2;
8695 } "-O2 -fopt-info-all -D$macro" ]
8697 # Get compiler emitted messages and delete generated file.
8698 set lines [lindex $result 0]
8699 set output [lindex $result 1]
8700 remote_file build delete $output
8702 # Check pattern exits in lines, set it to zero if not found.
8703 if { [regexp $pattern $lines] } then {
8710 # Return the true if target support vectorization of 2-byte char stores
8711 # with 2-byte aligned address at plain O2.
8712 # NB: This target should be removed after real issues are fixed for
8713 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8714 # this target since tests in check_vect_slp_store_usage
8715 # is the exact match of relative testcases
8716 proc check_effective_target_vect_slp_v2qi_store_align { } {
8717 set pattern {add new stmt: MEM <vector\(2\) char>}
8718 set macro "TEST_V2QI"
8719 return [check_cached_effective_target vect_slp_v2qi_store_align {
8720 expr [check_vect_slp_store_usage $pattern $macro] }]
8723 # Return the true if target support vectorization of 2-byte char stores
8724 # with unaligned address at plain O2.
8725 proc check_effective_target_vect_slp_v2qi_store_unalign { } {
8726 set pattern {add new stmt: MEM <vector\(2\) char>}
8727 set macro "TEST_V2QI_2"
8728 return [check_cached_effective_target vect_slp_v2qi_store_unalign {
8729 expr [check_vect_slp_store_usage $pattern $macro ] }]
8732 # Return the true if target support vectorization of 4-byte char stores
8733 # with 4-byte aligned address at plain O2.
8734 # NB: This target should be removed after real issues are fixed for
8735 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8736 # this target since tests in check_vect_slp_store_usage
8737 # is the exact match of relative testcases
8738 proc check_effective_target_vect_slp_v4qi_store_align { } {
8739 set pattern {add new stmt: MEM <vector\(4\) char>}
8740 set macro "TEST_V4QI"
8741 return [check_cached_effective_target vect_slp_v4qi_store_align {
8742 expr [check_vect_slp_store_usage $pattern $macro ] }]
8745 # Return the true if target support vectorization of 4-byte char stores
8746 # with unaligned address at plain O2.
8747 proc check_effective_target_vect_slp_v4qi_store_unalign { } {
8748 set pattern {add new stmt: MEM <vector\(4\) char>}
8749 set macro "TEST_V4QI_2"
8750 return [check_cached_effective_target vect_slp_v4qi_store_unalign {
8751 expr [check_vect_slp_store_usage $pattern $macro ] }]
8754 # Return the true if target support block move for
8755 # 8-byte aligned 4-byte size struct initialization.
8756 proc check_effective_target_struct_4char_block_move { } {
8757 set pattern {not vectorized: more than one data ref in stmt:}
8758 set macro "TEST_V4QI_3"
8759 return [check_cached_effective_target struct_4char_block_move {
8760 expr [check_vect_slp_store_usage $pattern $macro ] }]
8763 # Return the true if target support vectorization of 4-byte char stores
8764 # with unaligned address or store them with a constant pool at plain O2.
8765 proc check_effective_target_vect_slp_v4qi_store_unalign_1 { } {
8766 set pattern {add new stmt: MEM <vector\(4\) char>}
8767 set macro "TEST_V4QI_3"
8768 return [check_cached_effective_target vect_slp_v4qi_store_unalign_1 {
8769 expr { [check_vect_slp_store_usage $pattern $macro ]
8770 || [check_effective_target_struct_4char_block_move] } }]
8773 # Return the true if target support block move for
8774 # 8-byte aligned 8-byte size struct initialization.
8775 proc check_effective_target_struct_8char_block_move { } {
8776 set pattern {not vectorized: more than one data ref in stmt:}
8777 set macro "TEST_V8QI"
8778 return [check_cached_effective_target struct_8char_block_move {
8779 expr [check_vect_slp_store_usage $pattern $macro ] }]
8782 # Return the true if target support vectorization of 8-byte char stores
8783 # with unaligned address or store them with a constant pool at plain O2.
8784 # NB: This target should be removed after real issues are fixed for
8785 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8786 # this target since tests in check_vect_slp_store_usage
8787 # is the exact match of relative testcases
8788 proc check_effective_target_vect_slp_v8qi_store_unalign_1 { } {
8789 set pattern {add new stmt: MEM <vector\(8\) char>}
8790 set macro "TEST_V8QI"
8791 return [check_cached_effective_target vect_slp_v8qi_store_unalign_1 {
8792 expr { [check_vect_slp_store_usage $pattern $macro ]
8793 || [check_effective_target_struct_8char_block_move] } }]
8796 # Return the true if target support block move for
8797 # 8-byte aligned 16-byte size struct initialization.
8798 proc check_effective_target_struct_16char_block_move { } {
8799 set pattern {not vectorized: more than one data ref in stmt:}
8800 set macro "TEST_V16QI"
8801 return [check_cached_effective_target struct_16char_block_move {
8802 expr [check_vect_slp_store_usage $pattern $macro ] }]
8805 # Return the true if target support vectorization of 16-byte char stores
8806 # with unaligned address or store them with a constant pool at plain O2.
8807 # NB: This target should be removed after real issues are fixed for
8808 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8809 # this target since tests in check_vect_slp_store_usage
8810 # is the exact match of relative testcases
8811 proc check_effective_target_vect_slp_v16qi_store_unalign_1 { } {
8812 set pattern {add new stmt: MEM <vector\(16\) char>}
8813 set macro "TEST_V16QI"
8814 return [check_cached_effective_target vect_slp_v16qi_store_unalign_1 {
8815 expr { [check_vect_slp_store_usage $pattern $macro ]
8816 || [check_effective_target_struct_16char_block_move] } }]
8819 # Return the true if target support vectorization of 4-byte short stores
8820 # with unaligned address at plain O2.
8821 # NB: This target should be removed after real issues are fixed for
8822 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8823 # this target since tests in check_vect_slp_store_usage
8824 # is the exact match of relative testcases
8825 proc check_effective_target_vect_slp_v2hi_store_unalign { } {
8826 set pattern {add new stmt: MEM <vector\(2\) short int>}
8827 set macro "TEST_V2HI"
8828 return [check_cached_effective_target vect_slp_v2hi_store_unalign {
8829 expr [check_vect_slp_store_usage $pattern $macro ] }]
8832 # Return the true if target support vectorization of 4-byte short stores
8833 # with 4-byte aligned address at plain O2.
8834 proc check_effective_target_vect_slp_v2hi_store_align { } {
8835 set pattern {add new stmt: MEM <vector\(2\) short int>}
8836 set macro "TEST_V2HI_2"
8837 return [check_cached_effective_target vect_slp_v2hi_store_align {
8838 expr [check_vect_slp_store_usage $pattern $macro ] }]
8841 # Return the true if target support vectorization of 8-byte short stores
8842 # with unaligned address at plain O2.
8843 # NB: This target should be removed after real issues are fixed for
8844 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8845 # this target since tests in check_vect_slp_store_usage
8846 # is the exact match of relative testcases
8847 proc check_effective_target_vect_slp_v4hi_store_unalign { } {
8848 set pattern {add new stmt: MEM <vector\(4\) short int>}
8849 set macro "TEST_V4HI"
8850 return [check_cached_effective_target vect_slp_v4hi_store_unalign {
8851 expr [check_vect_slp_store_usage $pattern $macro ] }]
8854 # Return the true if target support vectorization of 8-byte int stores
8855 # with 8-byte aligned address at plain O2.
8856 # NB: This target should be removed after real issues are fixed for
8857 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8858 # this target since tests in check_vect_slp_store_usage
8859 # is the exact match of relative testcases
8860 proc check_effective_target_vect_slp_v2si_store_align { } {
8861 set pattern {add new stmt: MEM <vector\(2\) int>}
8862 set macro "TEST_V2SI"
8863 return [check_cached_effective_target vect_slp_v2si_store_align {
8864 expr [check_vect_slp_store_usage $pattern $macro ] }]
8867 # Return the true if target support vectorization of 16-byte int stores
8868 # with unaligned address at plain O2.
8869 # NB: This target should be removed after real issues are fixed for
8870 # -Wstringop-overflow with O2 vect. Be careful if you want to reuse
8871 # this target since tests in check_vect_slp_store_usage
8872 # is the exact match of relative testcases
8873 proc check_effective_target_vect_slp_v4si_store_unalign { } {
8874 set pattern {add new stmt: MEM <vector\(4\) int>}
8875 set macro "TEST_V4SI"
8876 return [check_cached_effective_target vect_slp_v4si_store_unalign {
8877 expr [check_vect_slp_store_usage $pattern $macro ] }]
8880 # Return 1 if we can align stack data to the preferred vector alignment.
8882 proc check_effective_target_vect_align_stack_vars { } {
8883 if { [check_effective_target_aarch64_sve] } {
8884 return [check_effective_target_vect_variable_length]
8889 # Return 1 if vector alignment (for types of size 32 bit or less) is reachable, 0 otherwise.
8891 proc check_effective_target_vector_alignment_reachable { } {
8892 set et_vector_alignment_reachable 0
8893 if { [check_effective_target_vect_aligned_arrays]
8894 || [check_effective_target_natural_alignment_32] } {
8895 set et_vector_alignment_reachable 1
8897 verbose "check_effective_target_vector_alignment_reachable:\
8898 returning $et_vector_alignment_reachable" 2
8899 return $et_vector_alignment_reachable
8902 # Return 1 if vector alignment for 64 bit is reachable, 0 otherwise.
8904 proc check_effective_target_vector_alignment_reachable_for_64bit { } {
8905 set et_vector_alignment_reachable_for_64bit 0
8906 if { [check_effective_target_vect_aligned_arrays]
8907 || [check_effective_target_natural_alignment_64] } {
8908 set et_vector_alignment_reachable_for_64bit 1
8910 verbose "check_effective_target_vector_alignment_reachable_for_64bit:\
8911 returning $et_vector_alignment_reachable_for_64bit" 2
8912 return $et_vector_alignment_reachable_for_64bit
8915 # Return 1 if the target only requires element alignment for vector accesses
8917 proc check_effective_target_vect_element_align { } {
8918 return [check_cached_effective_target_indexed vect_element_align {
8919 expr { ([istarget arm*-*-*]
8920 && ![check_effective_target_arm_vect_no_misalign])
8921 || [check_effective_target_vect_hw_misalign]
8922 || [istarget amdgcn-*-*] }}]
8925 # Return 1 if we expect to see unaligned accesses in at least some
8928 proc check_effective_target_vect_unaligned_possible { } {
8929 return [expr { ![check_effective_target_vect_element_align_preferred]
8930 && (![check_effective_target_vect_no_align]
8931 || [check_effective_target_vect_hw_misalign]) }]
8934 # Return 1 if the target supports vector LOAD_LANES operations, 0 otherwise.
8936 proc check_effective_target_vect_load_lanes { } {
8937 # We don't support load_lanes correctly on big-endian arm.
8938 return [check_cached_effective_target vect_load_lanes {
8939 expr { ([check_effective_target_arm_little_endian]
8940 && [check_effective_target_arm_neon_ok])
8941 || [istarget aarch64*-*-*]
8942 || [istarget riscv*-*-*] }}]
8945 # Return 1 if the target supports vector masked loads.
8947 proc check_effective_target_vect_masked_load { } {
8948 return [expr { [check_avx_available]
8949 || [check_effective_target_aarch64_sve]
8950 || [istarget amdgcn*-*-*]
8951 || [check_effective_target_riscv_v] } ]
8954 # Return 1 if the target supports vector masked stores.
8956 proc check_effective_target_vect_masked_store { } {
8957 return [expr { [check_avx_available]
8958 || [check_effective_target_aarch64_sve]
8959 || [istarget amdgcn*-*-*]
8960 || [check_effective_target_riscv_v] }]
8963 # Return 1 if the target supports vector gather loads via internal functions.
8965 proc check_effective_target_vect_gather_load_ifn { } {
8966 return [expr { [check_effective_target_aarch64_sve]
8967 || [istarget amdgcn*-*-*]
8968 || [check_effective_target_riscv_v] }]
8971 # Return 1 if the target supports vector scatter stores.
8973 proc check_effective_target_vect_scatter_store { } {
8974 return [expr { [check_effective_target_aarch64_sve]
8975 || [istarget amdgcn*-*-*]
8976 || [check_effective_target_riscv_v]
8977 || [check_effective_target_loongarch_sx] }]
8980 # Return 1 if the target supports vector conditional operations, 0 otherwise.
8982 proc check_effective_target_vect_condition { } {
8983 return [check_cached_effective_target_indexed vect_condition {
8984 expr { [istarget aarch64*-*-*]
8985 || [istarget powerpc*-*-*]
8986 || [istarget ia64-*-*]
8987 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8988 || ([istarget mips*-*-*]
8989 && [et-is-effective-target mips_msa])
8990 || ([istarget arm*-*-*]
8991 && [check_effective_target_arm_neon_ok])
8992 || ([istarget s390*-*-*]
8993 && [check_effective_target_s390_vx])
8994 || [istarget amdgcn-*-*]
8995 || ([istarget riscv*-*-*]
8996 && [check_effective_target_riscv_v])
8997 || ([istarget loongarch*-*-*]
8998 && [check_effective_target_loongarch_sx]) }}]
9001 # Return 1 if the target supports vector conditional operations where
9002 # the comparison has different type from the lhs, 0 otherwise.
9004 proc check_effective_target_vect_cond_mixed { } {
9005 return [check_cached_effective_target_indexed vect_cond_mixed {
9006 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9007 || [istarget aarch64*-*-*]
9008 || [istarget powerpc*-*-*]
9009 || ([istarget arm*-*-*]
9010 && [check_effective_target_arm_neon_ok])
9011 || ([istarget mips*-*-*]
9012 && [et-is-effective-target mips_msa])
9013 || ([istarget s390*-*-*]
9014 && [check_effective_target_s390_vx])
9015 || [istarget amdgcn-*-*]
9016 || ([istarget riscv*-*-*]
9017 && [check_effective_target_riscv_v])
9018 || ([istarget loongarch*-*-*]
9019 && [check_effective_target_loongarch_sx]) }}]
9022 # Return 1 if the target supports vector char multiplication, 0 otherwise.
9024 proc check_effective_target_vect_char_mult { } {
9025 return [check_cached_effective_target_indexed vect_char_mult {
9026 expr { [istarget aarch64*-*-*]
9027 || [istarget ia64-*-*]
9028 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9029 || [check_effective_target_arm32]
9030 || [check_effective_target_powerpc_altivec]
9031 || ([istarget mips*-*-*]
9032 && [et-is-effective-target mips_msa])
9033 || ([istarget s390*-*-*]
9034 && [check_effective_target_s390_vx])
9035 || [istarget amdgcn-*-*]
9036 || ([istarget riscv*-*-*]
9037 && [check_effective_target_riscv_v])
9038 || ([istarget loongarch*-*-*]
9039 && [check_effective_target_loongarch_sx]) }}]
9042 # Return 1 if the target supports vector short multiplication, 0 otherwise.
9044 proc check_effective_target_vect_short_mult { } {
9045 return [check_cached_effective_target_indexed vect_short_mult {
9046 expr { [istarget ia64-*-*]
9047 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9048 || [istarget powerpc*-*-*]
9049 || [istarget aarch64*-*-*]
9050 || [check_effective_target_arm32]
9051 || ([istarget mips*-*-*]
9052 && ([et-is-effective-target mips_msa]
9053 || [et-is-effective-target mips_loongson_mmi]))
9054 || ([istarget s390*-*-*]
9055 && [check_effective_target_s390_vx])
9056 || [istarget amdgcn-*-*]
9057 || ([istarget riscv*-*-*]
9058 && [check_effective_target_riscv_v])
9059 || ([istarget loongarch*-*-*]
9060 && [check_effective_target_loongarch_sx]) }}]
9063 # Return 1 if the target supports vector int multiplication, 0 otherwise.
9065 proc check_effective_target_vect_int_mult { } {
9066 return [check_cached_effective_target_indexed vect_int_mult {
9067 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
9068 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9069 || [istarget ia64-*-*]
9070 || [istarget aarch64*-*-*]
9071 || ([istarget mips*-*-*]
9072 && [et-is-effective-target mips_msa])
9073 || [check_effective_target_arm32]
9074 || ([istarget s390*-*-*]
9075 && [check_effective_target_s390_vx])
9076 || [istarget amdgcn-*-*]
9077 || ([istarget riscv*-*-*]
9078 && [check_effective_target_riscv_v])
9079 || ([istarget loongarch*-*-*]
9080 && [check_effective_target_loongarch_sx]) }}]
9083 # Return 1 if the target supports 64 bit hardware vector
9084 # multiplication of long operands with a long result, 0 otherwise.
9086 # This can change for different subtargets so do not cache the result.
9088 proc check_effective_target_vect_long_mult { } {
9089 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
9090 || ([istarget powerpc*-*-*]
9091 && ([check_effective_target_ilp32]
9092 || ([check_effective_target_powerpc_vsx_ok]
9093 && [check_effective_target_has_arch_pwr10])))
9094 || [is-effective-target arm_neon]
9095 || ([istarget sparc*-*-*] && [check_effective_target_ilp32])
9096 || ([istarget aarch64*-*-*]
9097 && ([check_effective_target_ilp32]
9098 || [check_effective_target_aarch64_sve]))
9099 || ([istarget mips*-*-*]
9100 && [et-is-effective-target mips_msa])
9101 || ([istarget riscv*-*-*]
9102 && [check_effective_target_riscv_v])
9103 || ([istarget loongarch*-*-*]
9104 && [check_effective_target_loongarch_sx]) } {
9110 verbose "check_effective_target_vect_long_mult: returning $answer" 2
9114 # Return 1 if the target supports vector int modulus, 0 otherwise.
9116 proc check_effective_target_vect_int_mod { } {
9117 return [check_cached_effective_target_indexed vect_int_mod {
9118 expr { ([istarget powerpc*-*-*]
9119 && [check_effective_target_has_arch_pwr10])
9120 || [istarget amdgcn-*-*]
9121 || ([istarget loongarch*-*-*]
9122 && [check_effective_target_loongarch_sx])
9123 || ([istarget riscv*-*-*]
9124 && [check_effective_target_riscv_v]) }}]
9127 # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise.
9129 proc check_effective_target_vect_extract_even_odd { } {
9130 return [check_cached_effective_target_indexed extract_even_odd {
9131 expr { [istarget aarch64*-*-*]
9132 || [istarget powerpc*-*-*]
9133 || [is-effective-target arm_neon]
9134 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9135 || [istarget ia64-*-*]
9136 || ([istarget mips*-*-*]
9137 && ([et-is-effective-target mips_msa]
9138 || [et-is-effective-target mpaired_single]))
9139 || ([istarget s390*-*-*]
9140 && [check_effective_target_s390_vx])
9141 || ([istarget riscv*-*-*]
9142 && [check_effective_target_riscv_v])
9143 || ([istarget loongarch*-*-*]
9144 && [check_effective_target_loongarch_sx]) }}]
9147 # Return 1 if the target supports vector interleaving, 0 otherwise.
9149 proc check_effective_target_vect_interleave { } {
9150 return [check_cached_effective_target_indexed vect_interleave {
9151 expr { [istarget aarch64*-*-*]
9152 || [istarget powerpc*-*-*]
9153 || [is-effective-target arm_neon]
9154 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9155 || [istarget ia64-*-*]
9156 || ([istarget mips*-*-*]
9157 && ([et-is-effective-target mpaired_single]
9158 || [et-is-effective-target mips_msa]))
9159 || ([istarget s390*-*-*]
9160 && [check_effective_target_s390_vx])
9161 || ([istarget riscv*-*-*]
9162 && [check_effective_target_riscv_v])
9163 || ([istarget loongarch*-*-*]
9164 && [check_effective_target_loongarch_sx]) }}]
9167 foreach N {2 3 4 5 6 7 8} {
9168 eval [string map [list N $N] {
9169 # Return 1 if the target supports 2-vector interleaving
9170 proc check_effective_target_vect_stridedN { } {
9171 return [check_cached_effective_target_indexed vect_stridedN {
9173 && [check_effective_target_vect_interleave]
9174 && [check_effective_target_vect_extract_even_odd] } {
9177 if { ([istarget arm*-*-*]
9178 || [istarget aarch64*-*-*]) && N >= 2 && N <= 4 } {
9181 if { ([istarget riscv*-*-*]) && N >= 2 && N <= 8 } {
9184 if [check_effective_target_vect_fully_masked] {
9193 # Return the list of vector sizes (in bits) that each target supports.
9194 # A vector length of "0" indicates variable-length vectors.
9196 proc available_vector_sizes { } {
9198 if { [istarget aarch64*-*-*] } {
9199 if { [check_effective_target_aarch64_sve] } {
9200 lappend result [aarch64_sve_bits]
9202 lappend result 128 64
9203 } elseif { [istarget arm*-*-*]
9204 && [check_effective_target_arm_neon_ok] } {
9205 lappend result 128 64
9206 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
9207 if { [check_avx_available] && ![check_prefer_avx128] } {
9211 if { ![is-effective-target ia32] } {
9215 } elseif { [istarget sparc*-*-*] } {
9217 } elseif { [istarget amdgcn*-*-*] } {
9218 # 6 different lane counts, and 4 element sizes
9219 lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
9220 } elseif { [istarget riscv*-*-*] } {
9221 if { [check_effective_target_riscv_v] } {
9222 lappend result 0 32 64 128
9226 # The traditional default asumption.
9232 # Return 1 if the target supports multiple vector sizes
9234 proc check_effective_target_vect_multiple_sizes { } {
9235 return [expr { [llength [available_vector_sizes]] > 1 }]
9238 # Return true if variable-length vectors are supported.
9240 proc check_effective_target_vect_variable_length { } {
9241 return [expr { [lindex [available_vector_sizes] 0] == 0 }]
9244 # Return 1 if the target supports vectors of 1024 bits.
9246 proc check_effective_target_vect1024 { } {
9247 return [expr { [lsearch -exact [available_vector_sizes] 1024] >= 0 }]
9250 # Return 1 if the target supports vectors of 512 bits.
9252 proc check_effective_target_vect512 { } {
9253 return [expr { [lsearch -exact [available_vector_sizes] 512] >= 0 }]
9256 # Return 1 if the target supports vectors of 256 bits.
9258 proc check_effective_target_vect256 { } {
9259 return [expr { [lsearch -exact [available_vector_sizes] 256] >= 0 }]
9262 # Return 1 if the target supports vectors of 128 bits.
9264 proc check_effective_target_vect128 { } {
9265 return [expr { [lsearch -exact [available_vector_sizes] 128] >= 0 }]
9268 # Return 1 if the target supports vectors of 64 bits.
9270 proc check_effective_target_vect64 { } {
9271 return [expr { [lsearch -exact [available_vector_sizes] 64] >= 0 }]
9274 # Return 1 if the target supports vectors of 32 bits.
9276 proc check_effective_target_vect32 { } {
9277 return [expr { [lsearch -exact [available_vector_sizes] 32] >= 0 }]
9280 # Return 1 if the target supports vector copysignf calls.
9282 proc check_effective_target_vect_call_copysignf { } {
9283 return [check_cached_effective_target_indexed vect_call_copysignf {
9284 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9285 || [istarget powerpc*-*-*]
9286 || [istarget aarch64*-*-*]
9287 || [istarget amdgcn-*-*]
9288 || ([istarget riscv*-*-*]
9289 && [check_effective_target_riscv_v])
9290 || ([istarget loongarch*-*-*]
9291 && [check_effective_target_loongarch_sx]) }}]
9294 # Return 1 if the target supports hardware square root instructions.
9296 proc check_effective_target_sqrt_insn { } {
9297 return [check_cached_effective_target sqrt_insn {
9298 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9299 || [check_effective_target_powerpc_sqrt]
9300 || [istarget aarch64*-*-*]
9301 || ([istarget arm*-*-*] && [check_effective_target_arm_vfp_ok])
9302 || ([istarget s390*-*-*]
9303 && [check_effective_target_s390_vx])
9304 || [istarget amdgcn-*-*] }}]
9307 # Return any additional options to enable square root intructions.
9309 proc add_options_for_sqrt_insn { flags } {
9310 if { [istarget amdgcn*-*-*] } {
9311 return "$flags -ffast-math"
9313 if { [istarget arm*-*-*] } {
9314 return [add_options_for_arm_vfp "$flags"]
9319 # Return 1 if the target supports vector sqrtf calls.
9321 proc check_effective_target_vect_call_sqrtf { } {
9322 return [check_cached_effective_target_indexed vect_call_sqrtf {
9323 expr { [istarget aarch64*-*-*]
9324 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9325 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
9326 || ([istarget s390*-*-*]
9327 && [check_effective_target_s390_vx])
9328 || [istarget amdgcn-*-*]
9329 || ([istarget riscv*-*-*]
9330 && [check_effective_target_riscv_v])
9331 || ([istarget loongarch*-*-*]
9332 && [check_effective_target_loongarch_sx]) }}]
9335 # Return 1 if the target supports vector lrint calls.
9337 proc check_effective_target_vect_call_lrint { } {
9338 set et_vect_call_lrint 0
9339 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
9340 && [check_effective_target_ilp32])
9341 || [istarget amdgcn-*-*]
9342 || [istarget loongarch*-*-*] } {
9343 set et_vect_call_lrint 1
9346 verbose "check_effective_target_vect_call_lrint: returning $et_vect_call_lrint" 2
9347 return $et_vect_call_lrint
9350 # Return 1 if the target supports vector btrunc calls.
9352 proc check_effective_target_vect_call_btrunc { } {
9353 return [check_cached_effective_target_indexed vect_call_btrunc {
9354 expr { [istarget aarch64*-*-*]
9355 || [istarget amdgcn-*-*]
9356 || [istarget loongarch*-*-*] }}]
9359 # Return 1 if the target supports vector btruncf calls.
9361 proc check_effective_target_vect_call_btruncf { } {
9362 return [check_cached_effective_target_indexed vect_call_btruncf {
9363 expr { [istarget aarch64*-*-*]
9364 || [istarget amdgcn-*-*]
9365 || [istarget loongarch*-*-*] }}]
9368 # Return 1 if the target supports vector ceil calls.
9370 proc check_effective_target_vect_call_ceil { } {
9371 return [check_cached_effective_target_indexed vect_call_ceil {
9372 expr { [istarget aarch64*-*-*]
9373 || [istarget amdgcn-*-*]
9374 || [istarget loongarch*-*-*] }}]
9377 # Return 1 if the target supports vector ceilf calls.
9379 proc check_effective_target_vect_call_ceilf { } {
9380 return [check_cached_effective_target_indexed vect_call_ceilf {
9381 expr { [istarget aarch64*-*-*]
9382 || [istarget amdgcn-*-*]
9383 || [istarget loongarch*-*-*] }}]
9386 # Return 1 if the target supports vector floor calls.
9388 proc check_effective_target_vect_call_floor { } {
9389 return [check_cached_effective_target_indexed vect_call_floor {
9390 expr { [istarget aarch64*-*-*]
9391 || [istarget amdgcn-*-*]
9392 || [istarget loongarch*-*-*] }}]
9395 # Return 1 if the target supports vector floorf calls.
9397 proc check_effective_target_vect_call_floorf { } {
9398 return [check_cached_effective_target_indexed vect_call_floorf {
9399 expr { [istarget aarch64*-*-*]
9400 || [istarget amdgcn-*-*]
9401 || [istarget loongarch*-*-*] }}]
9404 # Return 1 if the target supports vector lceil calls.
9406 proc check_effective_target_vect_call_lceil { } {
9407 return [check_cached_effective_target_indexed vect_call_lceil {
9408 expr { [istarget aarch64*-*-*]
9409 || [istarget loongarch*-*-*] }}]
9412 # Return 1 if the target supports vector lfloor calls.
9414 proc check_effective_target_vect_call_lfloor { } {
9415 return [check_cached_effective_target_indexed vect_call_lfloor {
9416 expr { [istarget aarch64*-*-*]
9417 || [istarget loongarch*-*-*] }}]
9420 # Return 1 if the target supports vector nearbyint calls.
9422 proc check_effective_target_vect_call_nearbyint { } {
9423 return [check_cached_effective_target_indexed vect_call_nearbyint {
9424 expr { [istarget aarch64*-*-*] }}]
9427 # Return 1 if the target supports vector nearbyintf calls.
9429 proc check_effective_target_vect_call_nearbyintf { } {
9430 return [check_cached_effective_target_indexed vect_call_nearbyintf {
9431 expr { [istarget aarch64*-*-*] }}]
9434 # Return 1 if the target supports vector round calls.
9436 proc check_effective_target_vect_call_round { } {
9437 return [check_cached_effective_target_indexed vect_call_round {
9438 expr { [istarget aarch64*-*-*] }}]
9441 # Return 1 if the target supports vector roundf calls.
9443 proc check_effective_target_vect_call_roundf { } {
9444 return [check_cached_effective_target_indexed vect_call_roundf {
9445 expr { [istarget aarch64*-*-*] }}]
9448 # Return 1 if the target supports AND, OR and XOR reduction.
9450 proc check_effective_target_vect_logical_reduc { } {
9451 return [expr { [check_effective_target_aarch64_sve]
9452 || [istarget amdgcn-*-*]
9453 || [check_effective_target_riscv_v]
9454 || [check_effective_target_loongarch_sx]
9455 || [istarget i?86-*-*] || [istarget x86_64-*-*]}]
9458 # Return 1 if the target supports the fold_extract_last optab.
9460 proc check_effective_target_vect_fold_extract_last { } {
9461 return [expr { [check_effective_target_aarch64_sve]
9462 || [istarget amdgcn*-*-*]
9463 || [check_effective_target_riscv_v] }]
9466 # Return 1 if the target supports section-anchors
9468 proc check_effective_target_section_anchors { } {
9469 return [check_cached_effective_target section_anchors {
9470 expr { [istarget powerpc*-*-*]
9471 || [istarget arm*-*-*]
9472 || [istarget aarch64*-*-*]
9473 || [istarget loongarch*-*-*] }}]
9476 # Return 1 if the target supports atomic operations on "int_128" values.
9478 proc check_effective_target_sync_int_128 { } {
9482 # Return 1 if the target supports atomic operations on "int_128" values
9483 # and can execute them.
9484 # This requires support for both compare-and-swap and true atomic loads.
9486 proc check_effective_target_sync_int_128_runtime { } {
9490 # Return 1 if the target supports atomic operations on "long long".
9492 # Note: 32bit x86 targets require -march=pentium in dg-options.
9493 # Note: 32bit s390 targets require -mzarch in dg-options.
9495 proc check_effective_target_sync_long_long { } {
9496 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
9497 || [istarget aarch64*-*-*]
9498 || [istarget arm*-*-*]
9499 || [istarget alpha*-*-*]
9500 || ([istarget sparc*-*-*] && [check_effective_target_lp64])
9501 || [istarget s390*-*-*] } {
9508 # Return 1 if the target supports popcount on long.
9510 proc check_effective_target_popcountl { } {
9511 return [check_no_messages_and_pattern popcountl "!\\(call" rtl-expand {
9514 return __builtin_popcountl (b);
9519 # Return 1 if the target supports popcount on long long.
9521 proc check_effective_target_popcountll { } {
9522 return [check_no_messages_and_pattern popcountll "!\\(call" rtl-expand {
9523 int foo (long long b)
9525 return __builtin_popcountll (b);
9531 # Return 1 if the target supports popcount on int.
9533 proc check_effective_target_popcount { } {
9534 return [check_no_messages_and_pattern popcount "!\\(call" rtl-expand {
9537 return __builtin_popcount (b);
9542 # Return 1 if the target supports clz on int.
9544 proc check_effective_target_clz { } {
9545 return [check_no_messages_and_pattern clz "!\\(call" rtl-expand {
9548 return __builtin_clz (b);
9553 # Return 1 if the target supports clz on long.
9555 proc check_effective_target_clzl { } {
9556 return [check_no_messages_and_pattern clzl "!\\(call" rtl-expand {
9559 return __builtin_clzl (b);
9564 # Return 1 if the target supports clz on long long.
9566 proc check_effective_target_clzll { } {
9567 return [check_no_messages_and_pattern clzll "!\\(call" rtl-expand {
9568 int foo (long long b)
9570 return __builtin_clzll (b);
9575 # Return 1 if the target supports ctz on int.
9577 proc check_effective_target_ctz { } {
9578 return [check_no_messages_and_pattern ctz "!\\(call" rtl-expand {
9581 return __builtin_ctz (b);
9586 # Return 1 if the target supports ctz on long.
9588 proc check_effective_target_ctzl { } {
9589 return [check_no_messages_and_pattern ctzl "!\\(call" rtl-expand {
9592 return __builtin_ctzl (b);
9597 # Return 1 if the target supports ctz on long long.
9599 proc check_effective_target_ctzll { } {
9600 return [check_no_messages_and_pattern ctzll "!\\(call" rtl-expand {
9601 int foo (long long b)
9603 return __builtin_ctzll (b);
9608 # Return 1 if the target supports atomic operations on "long long"
9609 # and can execute them.
9611 # Note: 32bit x86 targets require -march=pentium in dg-options.
9613 proc check_effective_target_sync_long_long_runtime { } {
9614 if { (([istarget x86_64-*-*] || [istarget i?86-*-*])
9615 && [check_cached_effective_target sync_long_long_available {
9616 check_runtime_nocache sync_long_long_available {
9620 unsigned int eax, ebx, ecx, edx;
9621 if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
9622 return !(edx & bit_CMPXCHG8B);
9627 || [istarget aarch64*-*-*]
9628 || [istarget arm*-*-uclinuxfdpiceabi]
9629 || ([istarget arm*-*-linux-*]
9630 && [check_runtime sync_longlong_runtime {
9636 if (sizeof (long long) != 8)
9639 /* Just check for native;
9640 checking for kernel fallback is tricky. */
9641 asm volatile ("ldrexd r0,r1, [%0]"
9642 : : "r" (&l1) : "r0", "r1");
9646 || [istarget alpha*-*-*]
9647 || ([istarget sparc*-*-*]
9648 && [check_effective_target_lp64]
9649 && [check_effective_target_ultrasparc_hw])
9650 || ([istarget powerpc*-*-*] && [check_effective_target_lp64]) } {
9657 # Return 1 if the target supports byte swap instructions.
9659 proc check_effective_target_bswap { } {
9660 return [check_cached_effective_target bswap {
9661 expr { [istarget aarch64*-*-*]
9662 || [istarget alpha*-*-*]
9663 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9664 || [istarget m68k-*-*]
9665 || [istarget powerpc*-*-*]
9666 || [istarget rs6000-*-*]
9667 || [istarget s390*-*-*]
9668 || ([istarget riscv*-*-*]
9669 && [check_no_compiler_messages_nocache riscv_zbb object {
9670 #if __riscv_zbb <= 0
9671 #error ZBB is not enabled
9675 || ([istarget arm*-*-*]
9676 && [check_no_compiler_messages_nocache arm_v6_or_later object {
9678 #error not armv6 or later
9684 # Return 1 if the target supports atomic operations on "int" and "long".
9686 proc check_effective_target_sync_int_long { } {
9687 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9688 # load-reserved/store-conditional instructions.
9689 return [check_cached_effective_target sync_int_long {
9690 expr { [istarget ia64-*-*]
9691 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9692 || [istarget aarch64*-*-*]
9693 || [istarget alpha*-*-*]
9694 || [istarget arm*-*-linux-*]
9695 || [istarget arm*-*-uclinuxfdpiceabi]
9696 || ([istarget arm*-*-*]
9697 && [check_effective_target_arm_acq_rel])
9698 || [istarget bfin*-*linux*]
9699 || [istarget hppa*-*linux*]
9700 || [istarget s390*-*-*]
9701 || [istarget powerpc*-*-*]
9702 || [istarget cris-*-*]
9703 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9704 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9705 || [check_effective_target_mips_llsc]
9706 || [istarget nvptx*-*-*]
9710 # Return 1 if the target supports atomic operations on "int" and "long" on
9713 proc check_effective_target_sync_int_long_stack { } {
9714 return [check_cached_effective_target sync_int_long_stack {
9715 expr { ![istarget nvptx*-*-*]
9716 && [check_effective_target_sync_int_long]
9720 # Return 1 if the target supports atomic operations on "char" and "short".
9722 proc check_effective_target_sync_char_short { } {
9723 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9724 # load-reserved/store-conditional instructions.
9725 return [check_cached_effective_target sync_char_short {
9726 expr { [istarget aarch64*-*-*]
9727 || [istarget ia64-*-*]
9728 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9729 || [istarget alpha*-*-*]
9730 || [istarget arm*-*-linux-*]
9731 || [istarget arm*-*-uclinuxfdpiceabi]
9732 || ([istarget arm*-*-*]
9733 && [check_effective_target_arm_acq_rel])
9734 || [istarget hppa*-*linux*]
9735 || [istarget s390*-*-*]
9736 || [istarget powerpc*-*-*]
9737 || [istarget cris-*-*]
9738 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9739 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9740 || [istarget loongarch*-*-*]
9741 || [check_effective_target_mips_llsc] }}]
9744 # Return 1 if thread_fence does not rely on __sync_synchronize
9747 proc check_effective_target_thread_fence {} {
9748 return [check_no_compiler_messages thread_fence executable {
9750 __atomic_thread_fence (__ATOMIC_SEQ_CST);
9756 # Return 1 if the target uses a ColdFire FPU.
9758 proc check_effective_target_coldfire_fpu { } {
9759 return [check_no_compiler_messages coldfire_fpu assembly {
9766 # Return true if this is a uClibc target.
9768 proc check_effective_target_uclibc {} {
9769 return [check_no_compiler_messages uclibc object {
9770 #include <features.h>
9771 #if !defined (__UCLIBC__)
9777 # Return true if this is a uclibc target and if the uclibc feature
9778 # described by __$feature__ is not present.
9780 proc check_missing_uclibc_feature {feature} {
9781 return [check_no_compiler_messages $feature object "
9782 #include <features.h>
9783 #if !defined (__UCLIBC) || defined (__${feature}__)
9789 # Return true if this is a Newlib target.
9791 proc check_effective_target_newlib {} {
9792 return [check_no_compiler_messages newlib object {
9797 # Return true if GCC was configured with --enable-newlib-nano-formatted-io
9798 proc check_effective_target_newlib_nano_io { } {
9799 return [check_configured_with "--enable-newlib-nano-formatted-io"]
9802 # Some newlib versions don't provide a frexpl and instead depend
9803 # on frexp to implement long double conversions in their printf-like
9804 # functions. This leads to broken results. Detect such versions here.
9806 proc check_effective_target_newlib_broken_long_double_io {} {
9807 if { [is-effective-target newlib] && ![is-effective-target frexpl] } {
9813 # Return true if this is NOT a Bionic target.
9815 proc check_effective_target_non_bionic {} {
9816 return [check_no_compiler_messages non_bionic object {
9818 #if defined (__BIONIC__)
9824 # Return true if this target has error.h header.
9826 proc check_effective_target_error_h {} {
9827 return [check_no_compiler_messages error_h object {
9832 # Return true if this target has tgmath.h header.
9834 proc check_effective_target_tgmath_h {} {
9835 return [check_no_compiler_messages tgmath_h object {
9840 # Return true if target's libc supports complex functions.
9842 proc check_effective_target_libc_has_complex_functions {} {
9843 return [check_no_compiler_messages libc_has_complex_functions object {
9844 #include <complex.h>
9849 # (a) an error of a few ULP is expected in string to floating-point
9850 # conversion functions; and
9851 # (b) overflow is not always detected correctly by those functions.
9853 proc check_effective_target_lax_strtofp {} {
9854 # By default, assume that all uClibc targets suffer from this.
9855 return [check_effective_target_uclibc]
9858 # Return 1 if this is a target for which wcsftime is a dummy
9859 # function that always returns 0.
9861 proc check_effective_target_dummy_wcsftime {} {
9862 # By default, assume that all uClibc targets suffer from this.
9863 return [check_effective_target_uclibc]
9866 # Return 1 if constructors with initialization priority arguments are
9867 # supposed on this target.
9869 proc check_effective_target_init_priority {} {
9870 return [check_no_compiler_messages init_priority assembly "
9871 void f() __attribute__((constructor (1000)));
9876 # Return 1 if the target matches the effective target 'arg', 0 otherwise.
9877 # This can be used with any check_* proc that takes no argument and
9878 # returns only 1 or 0. It could be used with check_* procs that take
9879 # arguments with keywords that pass particular arguments.
9881 proc is-effective-target { arg } {
9884 if { ![info exists et_index] } {
9885 # Initialize the effective target index that is used in some
9886 # check_effective_target_* procs.
9889 if { [info procs check_effective_target_${arg}] != [list] } {
9890 set selected [check_effective_target_${arg}]
9893 "vmx_hw" { set selected [check_vmx_hw_available] }
9894 "vsx_hw" { set selected [check_vsx_hw_available] }
9895 "p8vector_hw" { set selected [check_p8vector_hw_available] }
9896 "p9vector_hw" { set selected [check_p9vector_hw_available] }
9897 "p9modulo_hw" { set selected [check_p9modulo_hw_available] }
9898 "power10_hw" { set selected [check_power10_hw_available] }
9899 "ppc_float128_sw" { set selected [check_ppc_float128_sw_available] }
9900 "ppc_float128_hw" { set selected [check_ppc_float128_hw_available] }
9901 "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }
9902 "ppc_cpu_supports_hw" { set selected [check_ppc_cpu_supports_hw_available] }
9903 "ppc_mma_hw" { set selected [check_ppc_mma_hw_available] }
9904 "dfp_hw" { set selected [check_dfp_hw_available] }
9905 "htm_hw" { set selected [check_htm_hw_available] }
9906 "named_sections" { set selected [check_named_sections_available] }
9907 "gc_sections" { set selected [check_gc_sections_available] }
9908 "cxa_atexit" { set selected [check_cxa_atexit_available] }
9909 default { error "unknown effective target keyword `$arg'" }
9913 verbose "is-effective-target: $arg $selected" 2
9917 # Return 1 if the argument is an effective-target keyword, 0 otherwise.
9919 proc is-effective-target-keyword { arg } {
9920 if { [info procs check_effective_target_${arg}] != [list] } {
9923 # These have different names for their check_* procs.
9925 "vmx_hw" { return 1 }
9926 "vsx_hw" { return 1 }
9927 "p8vector_hw" { return 1 }
9928 "p9vector_hw" { return 1 }
9929 "p9modulo_hw" { return 1 }
9930 "power10_hw" { return 1 }
9931 "ppc_float128_sw" { return 1 }
9932 "ppc_float128_hw" { return 1 }
9933 "ppc_recip_hw" { return 1 }
9934 "ppc_mma_hw" { return 1 }
9935 "dfp_hw" { return 1 }
9936 "htm_hw" { return 1 }
9937 "named_sections" { return 1 }
9938 "gc_sections" { return 1 }
9939 "cxa_atexit" { return 1 }
9940 "ppc_cpu_supports_hw" { return 1 }
9941 default { return 0 }
9946 # Execute tests for all targets in EFFECTIVE_TARGETS list. Set et_index to
9947 # indicate what target is currently being processed. This is for
9948 # the vectorizer tests, e.g. vect_int, to keep track what target supports
9951 proc et-dg-runtest { runtest testcases flags default-extra-flags } {
9952 global dg-do-what-default
9953 global EFFECTIVE_TARGETS
9956 if { [llength $EFFECTIVE_TARGETS] > 0 } {
9957 foreach target $EFFECTIVE_TARGETS {
9958 set target_flags $flags
9959 set dg-do-what-default compile
9960 set et_index [lsearch -exact $EFFECTIVE_TARGETS $target]
9961 if { [info procs add_options_for_${target}] != [list] } {
9962 set target_flags [add_options_for_${target} "$flags"]
9964 if { [info procs check_effective_target_${target}_runtime]
9965 != [list] && [check_effective_target_${target}_runtime] } {
9966 set dg-do-what-default run
9968 $runtest $testcases $target_flags ${default-extra-flags}
9972 $runtest $testcases $flags ${default-extra-flags}
9976 # Return 1 if a target matches the target in EFFECTIVE_TARGETS at index
9977 # et_index, 0 otherwise.
9979 proc et-is-effective-target { target } {
9980 global EFFECTIVE_TARGETS
9983 if { [info exists EFFECTIVE_TARGETS] } {
9984 if { [llength $EFFECTIVE_TARGETS] > $et_index
9985 && [lindex $EFFECTIVE_TARGETS $et_index] == $target } {
9991 return [check_effective_target_${target}]
9995 # Return 1 if target default to short enums
9997 proc check_effective_target_short_enums { } {
9998 return [check_no_compiler_messages short_enums assembly {
10000 int s[sizeof (enum foo) == 1 ? 1 : -1];
10004 # Return 1 if target supports merging string constants at link time.
10006 proc check_effective_target_string_merging { } {
10007 return [check_no_messages_and_pattern string_merging \
10008 "rodata\\.str" assembly {
10009 const char *var = "String";
10013 # Return 1 if target has the basic signed and unsigned types in
10014 # <stdint.h>, 0 otherwise. This will be obsolete when GCC ensures a
10015 # working <stdint.h> for all targets.
10017 proc check_effective_target_stdint_types { } {
10018 return [check_no_compiler_messages stdint_types assembly {
10019 #include <stdint.h>
10020 int8_t a; int16_t b; int32_t c; int64_t d;
10021 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
10025 # Like check_effective_target_stdint_types, but test what happens when
10026 # -mbig-endian is passed. This test only makes sense on targets that
10027 # support -mbig-endian; it will fail elsewhere.
10029 proc check_effective_target_stdint_types_mbig_endian { } {
10030 return [check_no_compiler_messages stdint_types_mbig_endian assembly {
10031 #include <stdint.h>
10032 int8_t a; int16_t b; int32_t c; int64_t d;
10033 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
10037 # Return 1 if target has the basic signed and unsigned types in
10038 # <inttypes.h>, 0 otherwise. This is for tests that GCC's notions of
10039 # these types agree with those in the header, as some systems have
10040 # only <inttypes.h>.
10042 proc check_effective_target_inttypes_types { } {
10043 return [check_no_compiler_messages inttypes_types assembly {
10044 #include <inttypes.h>
10045 int8_t a; int16_t b; int32_t c; int64_t d;
10046 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
10050 # Return 1 if programs are intended to be run on a simulator
10051 # (i.e. slowly) rather than hardware (i.e. fast).
10053 proc check_effective_target_simulator { } {
10055 # All "src/sim" simulators set this one.
10056 if [board_info target exists is_simulator] {
10057 return [board_info target is_simulator]
10060 # The "sid" simulators don't set that one, but at least they set
10062 if [board_info target exists slow_simulator] {
10063 return [board_info target slow_simulator]
10069 # Return 1 if programs are intended to be run on hardware rather than
10072 proc check_effective_target_hw { } {
10074 # All "src/sim" simulators set this one.
10075 if [board_info target exists is_simulator] {
10076 if [board_info target is_simulator] {
10083 # The "sid" simulators don't set that one, but at least they set
10085 if [board_info target exists slow_simulator] {
10086 if [board_info target slow_simulator] {
10096 # Return 1 if the target is a VxWorks kernel.
10098 proc check_effective_target_vxworks_kernel { } {
10099 return [check_no_compiler_messages vxworks_kernel assembly {
10100 #if !defined __vxworks || defined __RTP__
10106 # Return 1 if the target is a VxWorks RTP.
10108 proc check_effective_target_vxworks_rtp { } {
10109 return [check_no_compiler_messages vxworks_rtp assembly {
10110 #if !defined __vxworks || !defined __RTP__
10116 # Return 1 if the target is expected to provide wide character support.
10118 proc check_effective_target_wchar { } {
10119 if {[check_missing_uclibc_feature UCLIBC_HAS_WCHAR]} {
10122 return [check_no_compiler_messages wchar assembly {
10127 # Return 1 if the target has <pthread.h>.
10129 proc check_effective_target_pthread_h { } {
10130 return [check_no_compiler_messages pthread_h assembly {
10131 #include <pthread.h>
10135 # Return 1 if the target can truncate a file from a file-descriptor,
10136 # as used by libgfortran/io/unix.c:fd_truncate; i.e. ftruncate or
10137 # chsize. We test for a trivially functional truncation; no stubs.
10138 # As libgfortran uses _FILE_OFFSET_BITS 64, we do too; it'll cause a
10139 # different function to be used.
10141 proc check_effective_target_fd_truncate { } {
10143 #define _FILE_OFFSET_BITS 64
10144 #include <unistd.h>
10146 #include <stdlib.h>
10147 #include <string.h>
10150 FILE *f = fopen ("tst.tmp", "wb");
10152 const char t[] = "test writing more than ten characters";
10156 write (fd, t, sizeof (t) - 1);
10158 if (ftruncate (fd, 10) != 0)
10164 unlink ("tst.tmp");
10167 f = fopen ("tst.tmp", "rb");
10168 if (fread (s, 1, sizeof (s), f) != 10 || strncmp (s, t, 10) != 0)
10171 unlink ("tst.tmp");
10176 if { [check_runtime ftruncate $prog] } {
10180 regsub "ftruncate" $prog "chsize" prog
10181 return [check_runtime chsize $prog]
10184 # Add to FLAGS all the target-specific flags needed to enable
10185 # full IEEE compliance mode.
10187 proc add_options_for_ieee { flags } {
10188 if { [istarget alpha*-*-*]
10189 || [istarget sh*-*-*] } {
10190 return "$flags -mieee"
10192 if { [istarget rx-*-*] } {
10193 return "$flags -mnofpu"
10198 if {![info exists flags_to_postpone]} {
10199 set flags_to_postpone ""
10202 # Add to FLAGS the flags needed to enable functions to bind locally
10203 # when using pic/PIC passes in the testsuite.
10204 proc add_options_for_bind_pic_locally { flags } {
10205 global flags_to_postpone
10207 # Instead of returning 'flags' with the -fPIE or -fpie appended, we save it
10208 # in 'flags_to_postpone' and append it later in gcc_target_compile procedure in
10209 # order to make sure that the multilib_flags doesn't override this.
10211 if {[check_no_compiler_messages using_pic2 assembly {
10213 #error __PIC__ != 2
10216 set flags_to_postpone "-fPIE"
10219 if {[check_no_compiler_messages using_pic1 assembly {
10221 #error __PIC__ != 1
10224 set flags_to_postpone "-fpie"
10230 # Add to FLAGS the flags needed to enable 64-bit vectors.
10232 proc add_options_for_double_vectors { flags } {
10233 if [is-effective-target arm_neon_ok] {
10234 return "$flags -mvectorize-with-neon-double"
10240 # Add to FLAGS the flags needed to define the STACK_SIZE macro.
10242 proc add_options_for_stack_size { flags } {
10243 if [is-effective-target stack_size] {
10244 set stack_size [dg-effective-target-value stack_size]
10245 return "$flags -DSTACK_SIZE=$stack_size"
10251 # Return 1 if the target provides a full C99 runtime.
10253 proc check_effective_target_c99_runtime { } {
10254 return [check_cached_effective_target c99_runtime {
10257 set file [open "$srcdir/gcc.dg/builtins-config.h"]
10258 set contents [read $file]
10261 #ifndef HAVE_C99_RUNTIME
10262 #error !HAVE_C99_RUNTIME
10265 check_no_compiler_messages_nocache c99_runtime assembly $contents
10269 # Return 1 if the target supports DWARF CFI directives.
10271 proc check_effective_target_cfi { } {
10272 return [check_no_compiler_messages cfi assembly {
10273 #ifdef __GCC_HAVE_DWARF2_CFI_ASM
10281 # Return 1 if the target provides the D runtime.
10283 proc check_effective_target_d_runtime { } {
10284 return [check_no_compiler_messages d_runtime executable {
10288 extern(C) int main() {
10294 # Return 1 if the target provides the D standard library.
10296 proc check_effective_target_d_runtime_has_std_library { } {
10297 return [check_no_compiler_messages d_runtime_has_std_library executable {
10301 extern(C) int main() {
10303 real function(real) pcos = &cos;
10309 # Return 1 if target wchar_t is at least 4 bytes.
10311 proc check_effective_target_4byte_wchar_t { } {
10312 return [check_no_compiler_messages 4byte_wchar_t object {
10313 int dummy[sizeof (__WCHAR_TYPE__) >= 4 ? 1 : -1];
10317 # Return 1 if the target supports automatic stack alignment.
10319 proc check_effective_target_automatic_stack_alignment { } {
10320 # Ordinarily x86 supports automatic stack alignment ...
10321 if { [istarget i?86*-*-*] || [istarget x86_64-*-*] } then {
10322 if { [istarget *-*-mingw*] || [istarget *-*-cygwin*] } {
10323 # ... except Win64 SEH doesn't. Succeed for Win32 though.
10324 return [check_effective_target_ilp32];
10331 # Return true if we are compiling for AVX target.
10333 proc check_avx_available { } {
10334 if { [check_no_compiler_messages avx_available assembly {
10344 # Return true if we are compiling for AVX2 target.
10346 proc check_avx2_available { } {
10347 if { [check_no_compiler_messages avx2_available assembly {
10357 # Return true if we are compiling for SSSE3 target.
10359 proc check_ssse3_available { } {
10360 if { [check_no_compiler_messages sse3a_available assembly {
10370 # Return true if 32- and 16-bytes vectors are available.
10372 proc check_effective_target_vect_sizes_32B_16B { } {
10373 return [expr { [available_vector_sizes] == [list 256 128] }]
10376 # Return true if 16- and 8-bytes vectors are available.
10378 proc check_effective_target_vect_sizes_16B_8B { } {
10379 if { [check_avx_available]
10380 || [is-effective-target arm_neon]
10381 || [istarget aarch64*-*-*]
10382 || [check_effective_target_riscv_v] } {
10390 # Return true if 128-bits vectors are preferred even if 256-bits vectors
10393 proc check_prefer_avx128 { } {
10394 if ![check_avx_available] {
10397 return [check_no_messages_and_pattern avx_explicit "xmm" assembly {
10398 float a[1024],b[1024],c[1024];
10399 void foo (void) { int i; for (i = 0; i < 1024; i++) a[i]=b[i]+c[i];}
10400 } "-O2 -ftree-vectorize"]
10404 # Return 1 if avx512fp16 instructions can be compiled.
10406 proc check_effective_target_avx512fp16 { } {
10407 return [check_no_compiler_messages avx512fp16 object {
10410 asm volatile ("vmovw %edi, %xmm0");
10411 asm volatile ("vfcmulcph %xmm1, %xmm2, %xmm3{%k1}");
10413 } "-O2 -mavx512fp16" ]
10416 # Return 1 if avx512f instructions can be compiled.
10418 proc check_effective_target_avx512f { } {
10419 return [check_no_compiler_messages avx512f object {
10420 typedef double __m512d __attribute__ ((__vector_size__ (64)));
10421 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10423 __m512d _mm512_add (__m512d a)
10425 return __builtin_ia32_addpd512_mask (a, a, a, 1, 4);
10428 __m128d _mm128_add (__m128d a)
10430 return __builtin_ia32_addsd_round (a, a, 8);
10433 __m128d _mm128_getmant (__m128d a)
10435 return __builtin_ia32_getmantsd_round (a, a, 0, 8);
10437 } "-O2 -mavx512f" ]
10440 # Return 1 if avx instructions can be compiled.
10442 proc check_effective_target_avx { } {
10443 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
10446 return [check_no_compiler_messages avx object {
10447 void _mm256_zeroall (void)
10449 __builtin_ia32_vzeroall ();
10454 # Return 1 if avx2 instructions can be compiled.
10455 proc check_effective_target_avx2 { } {
10456 return [check_no_compiler_messages avx2 object {
10457 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10459 mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
10461 return __builtin_ia32_andnotsi256 (__X, __Y);
10466 # Return 1 if avxvnni instructions can be compiled.
10467 proc check_effective_target_avxvnni { } {
10468 return [check_no_compiler_messages avxvnni object {
10469 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10471 _mm256_dpbusd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10473 return __builtin_ia32_vpdpbusd_v8si (__A, __B, __C);
10478 # Return 1 if avxifma instructions can be compiled.
10479 proc check_effective_target_avxifma { } {
10480 return [check_no_compiler_messages avxifma object {
10481 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10483 _mm256_maddlo_epu64 (__v4di __A, __v4di __B, __v4di __C)
10485 return __builtin_ia32_vpmadd52luq256 (__A, __B, __C);
10487 } "-O0 -mavxifma" ]
10490 # Return 1 if avxvnniint8 instructions can be compiled.
10491 proc check_effective_target_avxvnniint8 { } {
10492 return [check_no_compiler_messages avxvnniint8 object {
10493 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10495 _mm256_dpbssd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10497 return __builtin_ia32_vpdpbssd256 (__A, __B, __C);
10499 } "-O0 -mavxvnniint8" ]
10502 # Return 1 if avxneconvert instructions can be compiled.
10503 proc check_effective_target_avxneconvert { } {
10504 return [check_no_compiler_messages avxneconvert object {
10505 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
10507 _mm_bcstnebf16_ps (const void *__P)
10509 return (__m128) __builtin_ia32_vbcstnebf162ps128 ((const __bf16 *) __P);
10511 } "-O0 -mavxneconvert" ]
10514 # Return 1 if cmpccxadd instructions can be compiled.
10515 proc check_effective_target_cmpccxadd { } {
10516 return [check_no_compiler_messages cmpccxadd object {
10517 int _cmpccxadd_epi32 (int *__A, int __B, int __C, const int __D)
10519 return (int)__builtin_ia32_cmpccxadd (__A, __B, __C, 1);
10524 # Return 1 if raoint instructions can be compiled.
10525 proc check_effective_target_raoint { } {
10526 return [check_no_compiler_messages raoint object {
10528 _aadd_si32 (int *__A, int __B)
10530 return __builtin_ia32_aadd32((int *)__A, __B);
10535 # Return 1 if amx-complex instructions can be compiled.
10536 proc check_effective_target_amx_complex { } {
10537 return [check_no_compiler_messages amx_complex object {
10541 __asm__ volatile ("tcmmimfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10543 } "-mamx-complex" ]
10546 # Return 1 if avxvnniint16 instructions can be compiled.
10547 proc check_effective_target_avxvnniint16 { } {
10548 return [check_no_compiler_messages avxvnniint16 object {
10549 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10551 _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C)
10553 return __builtin_ia32_vpdpwsud256 (__A, __B, __C);
10555 } "-O0 -mavxvnniint16" ]
10558 # Return 1 if sm3 instructions can be compiled.
10559 proc check_effective_target_sm3 { } {
10560 return [check_no_compiler_messages sm3 object {
10561 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10562 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10564 _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
10566 return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A,
10573 # Return 1 if sha512 instructions can be compiled.
10574 proc check_effective_target_sha512 { } {
10575 return [check_no_compiler_messages sha512 object {
10576 typedef long long __m256i __attribute__ ((__vector_size__ (32)));
10577 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10579 _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
10581 return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A,
10587 # Return 1 if sm4 instructions can be compiled.
10588 proc check_effective_target_sm4 { } {
10589 return [check_no_compiler_messages sm4 object {
10590 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10591 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10593 _mm_sm4key4_epi32 (__m128i __A, __m128i __B)
10595 return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A,
10601 proc check_effective_target_apxf { } {
10602 return [check_no_compiler_messages apxf object {
10606 __asm__ volatile ("add\t%%r16, %%r31" ::);
10611 # Return 1 if sse instructions can be compiled.
10612 proc check_effective_target_sse { } {
10613 return [check_no_compiler_messages sse object {
10616 __builtin_ia32_stmxcsr ();
10622 # Return 1 if sse2 instructions can be compiled.
10623 proc check_effective_target_sse2 { } {
10624 return [check_no_compiler_messages sse2 object {
10625 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10627 __m128i _mm_srli_si128 (__m128i __A, int __N)
10629 return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
10634 # Return 1 if sse4.1 instructions can be compiled.
10635 proc check_effective_target_sse4 { } {
10636 return [check_no_compiler_messages sse4.1 object {
10637 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10638 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10640 __m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
10642 return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
10648 # Return 1 if F16C instructions can be compiled.
10650 proc check_effective_target_f16c { } {
10651 return [check_no_compiler_messages f16c object {
10652 #include "immintrin.h"
10654 foo (unsigned short val)
10656 return _cvtsh_ss (val);
10661 proc check_effective_target_ms_hook_prologue { } {
10662 if { [check_no_compiler_messages ms_hook_prologue object {
10663 void __attribute__ ((__ms_hook_prologue__)) foo ();
10671 # Return 1 if 3dnow instructions can be compiled.
10672 proc check_effective_target_3dnow { } {
10673 return [check_no_compiler_messages 3dnow object {
10674 typedef int __m64 __attribute__ ((__vector_size__ (8)));
10675 typedef float __v2sf __attribute__ ((__vector_size__ (8)));
10677 __m64 _m_pfadd (__m64 __A, __m64 __B)
10679 return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B);
10684 # Return 1 if sse3 instructions can be compiled.
10685 proc check_effective_target_sse3 { } {
10686 return [check_no_compiler_messages sse3 object {
10687 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10688 typedef double __v2df __attribute__ ((__vector_size__ (16)));
10690 __m128d _mm_addsub_pd (__m128d __X, __m128d __Y)
10692 return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
10697 # Return 1 if ssse3 instructions can be compiled.
10698 proc check_effective_target_ssse3 { } {
10699 return [check_no_compiler_messages ssse3 object {
10700 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10701 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10703 __m128i _mm_abs_epi32 (__m128i __X)
10705 return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
10710 # Return 1 if aes instructions can be compiled.
10711 proc check_effective_target_aes { } {
10712 return [check_no_compiler_messages aes object {
10713 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10714 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10716 __m128i _mm_aesimc_si128 (__m128i __X)
10718 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10723 # Return 1 if vaes instructions can be compiled.
10724 proc check_effective_target_vaes { } {
10725 return [check_no_compiler_messages vaes object {
10726 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10727 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10729 __m128i _mm_aesimc_si128 (__m128i __X)
10731 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10733 } "-O2 -maes -mavx" ]
10736 # Return 1 if pclmul instructions can be compiled.
10737 proc check_effective_target_pclmul { } {
10738 return [check_no_compiler_messages pclmul object {
10739 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10740 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10742 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10744 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10751 # Return 1 if vpclmul instructions can be compiled.
10752 proc check_effective_target_vpclmul { } {
10753 return [check_no_compiler_messages vpclmul object {
10754 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10755 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10757 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10759 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10763 } "-O2 -mpclmul -mavx" ]
10766 # Return 1 if sse4a instructions can be compiled.
10767 proc check_effective_target_sse4a { } {
10768 return [check_no_compiler_messages sse4a object {
10769 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10770 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10772 __m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
10774 return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
10779 # Return 1 if fma4 instructions can be compiled.
10780 proc check_effective_target_fma4 { } {
10781 return [check_no_compiler_messages fma4 object {
10782 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10783 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10784 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10786 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10793 # Return 1 if fma instructions can be compiled.
10794 proc check_effective_target_fma { } {
10795 return [check_no_compiler_messages fma object {
10796 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10797 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10798 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10800 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10807 # Return 1 if xop instructions can be compiled.
10808 proc check_effective_target_xop { } {
10809 return [check_no_compiler_messages xop object {
10810 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10811 typedef short __v8hi __attribute__ ((__vector_size__ (16)));
10812 __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
10814 return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A,
10821 # Return 1 if lzcnt instruction can be compiled.
10822 proc check_effective_target_lzcnt { } {
10823 return [check_no_compiler_messages lzcnt object {
10824 unsigned short _lzcnt (unsigned short __X)
10826 return __builtin_clzs (__X);
10831 # Return 1 if bmi instructions can be compiled.
10832 proc check_effective_target_bmi { } {
10833 return [check_no_compiler_messages bmi object {
10834 unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y)
10836 return __builtin_ia32_bextr_u32 (__X, __Y);
10841 # Return 1 if ADX instructions can be compiled.
10842 proc check_effective_target_adx { } {
10843 return [check_no_compiler_messages adx object {
10845 _adxcarry_u32 (unsigned char __CF, unsigned int __X,
10846 unsigned int __Y, unsigned int *__P)
10848 return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P);
10853 # Return 1 if rtm instructions can be compiled.
10854 proc check_effective_target_rtm { } {
10855 return [check_no_compiler_messages rtm object {
10859 return __builtin_ia32_xend ();
10864 # Return 1 if avx512vl instructions can be compiled.
10865 proc check_effective_target_avx512vl { } {
10866 return [check_no_compiler_messages avx512vl object {
10867 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10869 mm256_and_epi64 (__v4di __X, __v4di __Y)
10872 return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1);
10877 # Return 1 if avx512cd instructions can be compiled.
10878 proc check_effective_target_avx512cd { } {
10879 return [check_no_compiler_messages avx512cd_trans object {
10880 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10882 _mm512_conflict_epi64 (__v8di __W, __v8di __A)
10884 return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
10888 } "-Wno-psabi -mavx512cd" ]
10891 # Return 1 if avx512er instructions can be compiled.
10892 proc check_effective_target_avx512er { } {
10893 return [check_no_compiler_messages avx512er_trans object {
10894 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10896 mm512_exp2a23_ps (__v16sf __X)
10898 return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4);
10900 } "-Wno-psabi -mavx512er" ]
10903 # Return 1 if sha instructions can be compiled.
10904 proc check_effective_target_sha { } {
10905 return [check_no_compiler_messages sha object {
10906 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10907 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10909 __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y)
10911 return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X,
10917 # Return 1 if avx512dq instructions can be compiled.
10918 proc check_effective_target_avx512dq { } {
10919 return [check_no_compiler_messages avx512dq object {
10920 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10922 _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B)
10924 return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A,
10932 # Return 1 if avx512bw instructions can be compiled.
10933 proc check_effective_target_avx512bw { } {
10934 return [check_no_compiler_messages avx512bw object {
10935 typedef short __v32hi __attribute__ ((__vector_size__ (64)));
10937 _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B)
10939 return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
10947 # Return 1 if -Wa,-march=+noavx512bw is supported.
10948 proc check_effective_target_assembler_march_noavx512bw {} {
10949 if { [istarget i?86*-*-*] || [istarget x86_64*-*-*] } {
10950 return [check_no_compiler_messages assembler_march_noavx512bw object {
10952 } "-mno-avx512bw -Wa,-march=+noavx512bw"]
10957 # Return 1 if avx512vp2intersect instructions can be compiled.
10958 proc check_effective_target_avx512vp2intersect { } {
10959 return [check_no_compiler_messages avx512vp2intersect object {
10960 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10961 typedef short __mmask16;
10963 _mm512_2intersect_epi32 (__v16si __A, __v16si __B, __mmask16 *__U,
10966 __builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B);
10968 } "-mavx512vp2intersect" ]
10971 # Return 1 if avx512ifma instructions can be compiled.
10972 proc check_effective_target_avx512ifma { } {
10973 return [check_no_compiler_messages avx512ifma object {
10974 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10976 _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z)
10978 return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X,
10986 # Return 1 if avx512vbmi instructions can be compiled.
10987 proc check_effective_target_avx512vbmi { } {
10988 return [check_no_compiler_messages avx512vbmi object {
10989 typedef char __v64qi __attribute__ ((__vector_size__ (64)));
10991 _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y)
10993 return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X,
11001 # Return 1 if avx512_4fmaps instructions can be compiled.
11002 proc check_effective_target_avx5124fmaps { } {
11003 return [check_no_compiler_messages avx5124fmaps object {
11004 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
11005 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
11008 _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C,
11009 __v16sf __D, __v16sf __E, __v4sf *__F)
11011 return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A,
11016 (const __v4sf *) __F,
11020 } "-mavx5124fmaps" ]
11023 # Return 1 if avx512_4vnniw instructions can be compiled.
11024 proc check_effective_target_avx5124vnniw { } {
11025 return [check_no_compiler_messages avx5124vnniw object {
11026 typedef int __v16si __attribute__ ((__vector_size__ (64)));
11027 typedef int __v4si __attribute__ ((__vector_size__ (16)));
11030 _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C,
11031 __v16si __D, __v16si __E, __v4si *__F)
11033 return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B,
11038 (const __v4si *) __F);
11040 } "-mavx5124vnniw" ]
11043 # Return 1 if avx512_vpopcntdq instructions can be compiled.
11044 proc check_effective_target_avx512vpopcntdq { } {
11045 return [check_no_compiler_messages avx512vpopcntdq object {
11046 typedef int __v16si __attribute__ ((__vector_size__ (64)));
11049 _mm512_popcnt_epi32 (__v16si __A)
11051 return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A);
11053 } "-mavx512vpopcntdq" ]
11056 # Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled.
11057 proc check_effective_target_avx512vpopcntdqvl { } {
11058 return [check_no_compiler_messages avx512vpopcntdqvl object {
11059 typedef int __v8si __attribute__ ((__vector_size__ (32)));
11062 _mm256_popcnt_epi32 (__v8si __A)
11064 return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A);
11066 } "-mavx512vpopcntdq -mavx512vl" ]
11069 # Return 1 if gfni instructions can be compiled.
11070 proc check_effective_target_gfni { } {
11071 return [check_no_compiler_messages gfni object {
11072 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
11075 _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C)
11077 return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A,
11084 # Return 1 if avx512vbmi2 instructions can be compiled.
11085 proc check_effective_target_avx512vbmi2 { } {
11086 return [check_no_compiler_messages avx512vbmi2 object {
11087 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
11088 typedef unsigned long long __mmask16;
11091 _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C)
11093 return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C,
11097 } "-mavx512vbmi2 -mavx512vl" ]
11100 # Return 1 if avx512vbmi2 instructions can be compiled.
11101 proc check_effective_target_avx512vnni { } {
11102 return [check_no_compiler_messages avx512vnni object {
11103 typedef int __v16si __attribute__ ((__vector_size__ (64)));
11106 _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C)
11108 return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A,
11112 } "-mavx512vnni -mavx512f" ]
11115 # Return 1 if vaes instructions can be compiled.
11116 proc check_effective_target_avx512vaes { } {
11117 return [check_no_compiler_messages avx512vaes object {
11119 typedef int __v16si __attribute__ ((__vector_size__ (64)));
11122 _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
11124 return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
11129 # Return 1 if amx-tile instructions can be compiled.
11130 proc check_effective_target_amx_tile { } {
11131 return [check_no_compiler_messages amx_tile object {
11135 __asm__ volatile ("tilerelease" ::);
11140 # Return 1 if amx-int8 instructions can be compiled.
11141 proc check_effective_target_amx_int8 { } {
11142 return [check_no_compiler_messages amx_int8 object {
11146 __asm__ volatile ("tdpbssd\t%%tmm1, %%tmm2, %%tmm3" ::);
11151 # Return 1 if amx-bf16 instructions can be compiled.
11152 proc check_effective_target_amx_bf16 { } {
11153 return [check_no_compiler_messages amx_bf16 object {
11157 __asm__ volatile ("tdpbf16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
11162 # Return 1 if amx-fp16 instructions can be compiled.
11163 proc check_effective_target_amx_fp16 { } {
11164 return [check_no_compiler_messages amx_fp16 object {
11168 __asm__ volatile ("tdpfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
11173 # Return 1 if vpclmulqdq instructions can be compiled.
11174 proc check_effective_target_vpclmulqdq { } {
11175 return [check_no_compiler_messages vpclmulqdq object {
11176 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
11179 _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B)
11181 return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0);
11183 } "-mvpclmulqdq -mavx512vl" ]
11186 # Return 1 if avx512_bitalg instructions can be compiled.
11187 proc check_effective_target_avx512bitalg { } {
11188 return [check_no_compiler_messages avx512bitalg object {
11189 typedef short int __v32hi __attribute__ ((__vector_size__ (64)));
11192 _mm512_popcnt_epi16 (__v32hi __A)
11194 return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
11196 } "-mavx512bitalg" ]
11199 # Return 1 if C wchar_t type is compatible with char16_t.
11201 proc check_effective_target_wchar_t_char16_t_compatible { } {
11202 return [check_no_compiler_messages wchar_t_char16_t object {
11204 __CHAR16_TYPE__ *p16 = &wc;
11205 char t[(((__CHAR16_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11209 # Return 1 if C wchar_t type is compatible with char32_t.
11211 proc check_effective_target_wchar_t_char32_t_compatible { } {
11212 return [check_no_compiler_messages wchar_t_char32_t object {
11214 __CHAR32_TYPE__ *p32 = &wc;
11215 char t[(((__CHAR32_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11219 # Return 1 if pow10 function exists.
11221 proc check_effective_target_pow10 { } {
11222 return [check_runtime pow10 {
11232 # Return 1 if frexpl function exists.
11234 proc check_effective_target_frexpl { } {
11235 return [check_runtime frexpl {
11240 x = frexpl (5.0, &y);
11247 # Return 1 if issignaling function exists.
11248 proc check_effective_target_issignaling {} {
11249 return [check_runtime issignaling {
11250 #define _GNU_SOURCE
11254 return issignaling (0.0);
11259 # Return 1 if current options generate DFP instructions, 0 otherwise.
11260 proc check_effective_target_hard_dfp {} {
11261 return [check_no_messages_and_pattern hard_dfp "!adddd3" assembly {
11262 typedef float d64 __attribute__((mode(DD)));
11264 void foo (void) { z = x + y; }
11268 # Return 1 if string.h and wchar.h headers provide C++ requires overloads
11269 # for strchr etc. functions.
11271 proc check_effective_target_correct_iso_cpp_string_wchar_protos { } {
11272 return [check_no_compiler_messages correct_iso_cpp_string_wchar_protos assembly {
11273 #include <string.h>
11275 #if !defined(__cplusplus) \
11276 || !defined(__CORRECT_ISO_CPP_STRING_H_PROTO) \
11277 || !defined(__CORRECT_ISO_CPP_WCHAR_H_PROTO)
11278 ISO C++ correct string.h and wchar.h protos not supported.
11285 # Return 1 if GNU as is used.
11287 proc check_effective_target_gas { } {
11288 global use_gas_saved
11291 if {![info exists use_gas_saved]} {
11292 # Check if the as used by gcc is GNU as.
11293 set options [list "additional_flags=-print-prog-name=as"]
11294 set gcc_as [lindex [${tool}_target_compile "" "" "none" $options] 0]
11295 # Provide /dev/null as input, otherwise gas times out reading from
11297 set status [remote_exec host "$gcc_as" "-v /dev/null"]
11298 set as_output [lindex $status 1]
11299 if { [ string first "GNU" $as_output ] >= 0 } {
11300 # Some Darwin versions have an assembler which is based on an old
11301 # version of GAS (and reports GNU assembler in its -v output) but
11302 # but doesn't support many of the modern GAS features.
11303 if { [ string first "cctools" $as_output ] >= 0 } {
11304 set use_gas_saved 0
11306 set use_gas_saved 1
11309 set use_gas_saved 0
11312 return $use_gas_saved
11315 # Return 1 if GNU ld is used.
11317 proc check_effective_target_gld { } {
11318 global use_gld_saved
11321 if {![info exists use_gld_saved]} {
11322 # Check if the ld used by gcc is GNU ld.
11323 set options [list "additional_flags=-print-prog-name=ld"]
11324 set gcc_ld [lindex [${tool}_target_compile "" "" "none" $options] 0]
11325 set status [remote_exec host "$gcc_ld" "--version"]
11326 set ld_output [lindex $status 1]
11327 if { [ string first "GNU" $ld_output ] >= 0 } {
11328 set use_gld_saved 1
11330 set use_gld_saved 0
11333 return $use_gld_saved
11336 # Return 1 if the compiler has been configure with link-time optimization
11339 proc check_effective_target_lto { } {
11340 if { [istarget *-*-vxworks*] } {
11341 # No LTO on VxWorks, with kernel modules
11342 # built with partial links
11345 if { [istarget nvptx-*-*]
11346 || [istarget amdgcn-*-*] } {
11349 return [check_no_compiler_messages lto object {
11350 void foo (void) { }
11354 # Return 1 if the compiler and linker support incremental link-time
11357 proc check_effective_target_lto_incremental { } {
11358 if ![check_effective_target_lto] {
11361 return [check_no_compiler_messages lto_incremental executable {
11362 int main () { return 0; }
11363 } "-flto -r -nostdlib"]
11366 # Return 1 if the compiler has been configured with analyzer support.
11368 proc check_effective_target_analyzer { } {
11369 return [check_no_compiler_messages analyzer object {
11370 void foo (void) { }
11374 # Return 1 if -mx32 -maddress-mode=short can compile, 0 otherwise.
11376 proc check_effective_target_maybe_x32 { } {
11377 return [check_no_compiler_messages maybe_x32 object {
11379 } "-mx32 -maddress-mode=short"]
11382 # Return 1 if this target supports the -fsplit-stack option, 0
11385 proc check_effective_target_split_stack {} {
11386 return [check_no_compiler_messages split_stack object {
11387 void foo (void) { }
11391 # Return 1 if this target supports the -masm=intel option, 0
11394 proc check_effective_target_masm_intel {} {
11395 return [check_no_compiler_messages masm_intel object {
11396 extern void abort (void);
11400 # Return 1 if the language for the compiler under test is C.
11402 proc check_effective_target_c { } {
11404 if [string match $tool "gcc"] {
11410 # Return 1 if the language for the compiler under test is C++.
11412 proc check_effective_target_c++ { } {
11414 if { [string match $tool "g++"] || [string match $tool "libstdc++"] } {
11420 set cxx_default "c++17"
11421 # Check whether the current active language standard supports the features
11422 # of C++11/C++14 by checking for the presence of one of the -std flags.
11423 # This assumes that the default for the compiler is $cxx_default, and that
11424 # there will never be multiple -std= arguments on the command line.
11425 proc check_effective_target_c++11_only { } {
11427 if ![check_effective_target_c++] {
11430 if [check-flags { { } { } { -std=c++0x -std=gnu++0x -std=c++11 -std=gnu++11 } }] {
11433 if { $cxx_default == "c++11" && [check-flags { { } { } { } { -std=* } }] } {
11438 proc check_effective_target_c++11 { } {
11439 if [check_effective_target_c++11_only] {
11442 return [check_effective_target_c++14]
11444 proc check_effective_target_c++11_down { } {
11445 if ![check_effective_target_c++] {
11448 return [expr ![check_effective_target_c++14] ]
11451 proc check_effective_target_c++14_only { } {
11453 if ![check_effective_target_c++] {
11456 if [check-flags { { } { } { -std=c++14 -std=gnu++14 -std=c++14 -std=gnu++14 } }] {
11459 if { $cxx_default == "c++14" && [check-flags { { } { } { } { -std=* } }] } {
11465 proc check_effective_target_c++14 { } {
11466 if [check_effective_target_c++14_only] {
11469 return [check_effective_target_c++17]
11471 proc check_effective_target_c++14_down { } {
11472 if ![check_effective_target_c++] {
11475 return [expr ![check_effective_target_c++17] ]
11478 proc check_effective_target_c++98_only { } {
11480 if ![check_effective_target_c++] {
11483 if [check-flags { { } { } { -std=c++98 -std=gnu++98 -std=c++03 -std=gnu++03 } }] {
11486 if { $cxx_default == "c++98" && [check-flags { { } { } { } { -std=* } }] } {
11492 proc check_effective_target_c++17_only { } {
11494 if ![check_effective_target_c++] {
11497 if [check-flags { { } { } { -std=c++17 -std=gnu++17 -std=c++1z -std=gnu++1z } }] {
11500 if { $cxx_default == "c++17" && [check-flags { { } { } { } { -std=* } }] } {
11506 proc check_effective_target_c++17 { } {
11507 if [check_effective_target_c++17_only] {
11510 return [check_effective_target_c++2a]
11512 proc check_effective_target_c++17_down { } {
11513 if ![check_effective_target_c++] {
11516 return [expr ![check_effective_target_c++2a] ]
11519 proc check_effective_target_c++2a_only { } {
11521 if ![check_effective_target_c++] {
11524 if [check-flags { { } { } { -std=c++2a -std=gnu++2a -std=c++20 -std=gnu++20 } }] {
11527 if { $cxx_default == "c++20" && [check-flags { { } { } { } { -std=* } }] } {
11532 proc check_effective_target_c++2a { } {
11533 if [check_effective_target_c++2a_only] {
11536 return [check_effective_target_c++23]
11539 proc check_effective_target_c++20_only { } {
11540 return [check_effective_target_c++2a_only]
11543 proc check_effective_target_c++20 { } {
11544 return [check_effective_target_c++2a]
11546 proc check_effective_target_c++20_down { } {
11547 if ![check_effective_target_c++] {
11550 return [expr ![check_effective_target_c++23] ]
11553 proc check_effective_target_c++23_only { } {
11555 if ![check_effective_target_c++] {
11558 if [check-flags { { } { } { -std=c++23 -std=gnu++23 -std=c++2b -std=gnu++2b } }] {
11561 if { $cxx_default == "c++23" && [check-flags { { } { } { } { -std=* } }] } {
11566 proc check_effective_target_c++23 { } {
11567 if [check_effective_target_c++23_only] {
11570 return [check_effective_target_c++26]
11573 proc check_effective_target_c++23_down { } {
11574 if ![check_effective_target_c++] {
11577 return [expr ![check_effective_target_c++26] ]
11580 proc check_effective_target_c++26_only { } {
11582 if ![check_effective_target_c++] {
11585 if [check-flags { { } { } { -std=c++26 -std=gnu++26 -std=c++2c -std=gnu++2c } }] {
11588 if { $cxx_default == "c++26" && [check-flags { { } { } { } { -std=* } }] } {
11594 proc check_effective_target_c++26 { } {
11595 return [check_effective_target_c++26_only]
11598 # Check for C++ Concepts support, i.e. -fconcepts flag.
11599 proc check_effective_target_concepts { } {
11600 if [check_effective_target_c++2a] {
11603 return [check-flags { "" { } { -fconcepts } }]
11606 proc check_effective_target_implicit_constexpr { } {
11607 return [check-flags { "" { } { -fimplicit-constexpr } }]
11610 # Return 1 if expensive testcases should be run.
11612 proc check_effective_target_run_expensive_tests { } {
11613 if { [getenv GCC_TEST_RUN_EXPENSIVE] != "" } {
11619 # Returns 1 if "mempcpy" is available on the target system.
11621 proc check_effective_target_mempcpy {} {
11622 if { [istarget *-*-vxworks*] } {
11623 # VxWorks doesn't have mempcpy but our way to test fails
11624 # to detect as we're doing partial links for kernel modules.
11627 return [check_function_available "mempcpy"]
11630 # Returns 1 if "stpcpy" is available on the target system.
11632 proc check_effective_target_stpcpy {} {
11633 return [check_function_available "stpcpy"]
11636 # Returns 1 if "sigsetjmp" is available on the target system.
11637 # Also check if "__sigsetjmp" is defined since that's what glibc
11640 proc check_effective_target_sigsetjmp {} {
11641 if { [check_function_available "sigsetjmp"]
11642 || [check_function_available "__sigsetjmp"] } {
11648 # Check whether the vectorizer tests are supported by the target and
11649 # append additional target-dependent compile flags to DEFAULT_VECTCFLAGS.
11650 # If a port wants to execute the tests more than once it should append
11651 # the supported target to EFFECTIVE_TARGETS instead, and the compile flags
11652 # will be added by a call to add_options_for_<target>.
11653 # Set dg-do-what-default to either compile or run, depending on target
11654 # capabilities. Do not set this if the supported target is appended to
11655 # EFFECTIVE_TARGETS. Flags and this variable will be set by et-dg-runtest
11656 # automatically. Return the number of effective targets if vectorizer tests
11657 # are supported, 0 otherwise.
11659 proc check_vect_support_and_set_flags { } {
11660 global DEFAULT_VECTCFLAGS
11661 global dg-do-what-default
11662 global EFFECTIVE_TARGETS
11664 if [istarget powerpc-*paired*] {
11665 lappend DEFAULT_VECTCFLAGS "-mpaired"
11666 if [check_750cl_hw_available] {
11667 set dg-do-what-default run
11669 set dg-do-what-default compile
11671 } elseif [istarget powerpc*-*-*] {
11672 # Skip targets not supporting -maltivec.
11673 if ![is-effective-target powerpc_altivec_ok] {
11677 lappend DEFAULT_VECTCFLAGS "-maltivec"
11678 if [check_p9vector_hw_available] {
11679 lappend DEFAULT_VECTCFLAGS "-mpower9-vector"
11680 } elseif [check_p8vector_hw_available] {
11681 lappend DEFAULT_VECTCFLAGS "-mpower8-vector"
11682 } elseif [check_vsx_hw_available] {
11683 lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
11686 if [check_vmx_hw_available] {
11687 set dg-do-what-default run
11689 if [is-effective-target ilp32] {
11690 # Specify a cpu that supports VMX for compile-only tests.
11691 lappend DEFAULT_VECTCFLAGS "-mcpu=970"
11693 set dg-do-what-default compile
11695 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
11696 lappend DEFAULT_VECTCFLAGS "-msse2"
11697 if { [check_effective_target_sse2_runtime] } {
11698 set dg-do-what-default run
11700 set dg-do-what-default compile
11702 } elseif { [istarget mips*-*-*]
11703 && [check_effective_target_nomips16] } {
11704 if { [check_effective_target_mpaired_single "-mpaired-single"] } {
11705 lappend EFFECTIVE_TARGETS mpaired_single
11707 if { [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
11708 lappend EFFECTIVE_TARGETS mips_loongson_mmi
11710 if { [check_effective_target_mips_msa "-mmsa"] } {
11711 lappend EFFECTIVE_TARGETS mips_msa
11713 return [llength $EFFECTIVE_TARGETS]
11714 } elseif [istarget sparc*-*-*] {
11715 lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
11716 if [check_effective_target_ultrasparc_hw] {
11717 set dg-do-what-default run
11719 set dg-do-what-default compile
11721 } elseif [istarget alpha*-*-*] {
11722 # Alpha's vectorization capabilities are extremely limited.
11723 # It's more effort than its worth disabling all of the tests
11724 # that it cannot pass. But if you actually want to see what
11725 # does work, command out the return.
11728 lappend DEFAULT_VECTCFLAGS "-mmax"
11729 if [check_alpha_max_hw_available] {
11730 set dg-do-what-default run
11732 set dg-do-what-default compile
11734 } elseif [istarget ia64-*-*] {
11735 set dg-do-what-default run
11736 } elseif [is-effective-target arm_neon_ok] {
11737 eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
11738 # NEON does not support denormals, so is not used for vectorization by
11739 # default to avoid loss of precision. We must pass -ffast-math to test
11740 # vectorization of float operations.
11741 lappend DEFAULT_VECTCFLAGS "-ffast-math"
11742 if [is-effective-target arm_neon_hw] {
11743 set dg-do-what-default run
11745 set dg-do-what-default compile
11747 } elseif [istarget aarch64*-*-*] {
11748 set dg-do-what-default run
11749 } elseif [istarget s390*-*-*] {
11750 # The S/390 backend set a default of 2 for that value.
11751 # Override it to have the same situation as with other
11753 lappend DEFAULT_VECTCFLAGS "--param" "min-vect-loop-bound=1"
11754 lappend DEFAULT_VECTCFLAGS "--param" "max-unrolled-insns=200"
11755 lappend DEFAULT_VECTCFLAGS "--param" "max-unroll-times=8"
11756 lappend DEFAULT_VECTCFLAGS "--param" "max-completely-peeled-insns=200"
11757 lappend DEFAULT_VECTCFLAGS "--param" "max-completely-peel-times=16"
11758 if [check_effective_target_s390_vxe2] {
11759 lappend DEFAULT_VECTCFLAGS "-march=z15" "-mzarch"
11760 set dg-do-what-default run
11761 } elseif [check_effective_target_s390_vxe] {
11762 lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
11763 set dg-do-what-default run
11764 } elseif [check_effective_target_s390_vx] {
11765 lappend DEFAULT_VECTCFLAGS "-march=z13" "-mzarch"
11766 set dg-do-what-default run
11768 lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
11769 set dg-do-what-default compile
11771 } elseif [istarget amdgcn-*-*] {
11772 set dg-do-what-default run
11773 } elseif [istarget riscv*-*-*] {
11774 if [check_effective_target_riscv_v] {
11775 set dg-do-what-default run
11777 foreach item [add_options_for_riscv_v ""] {
11778 lappend DEFAULT_VECTCFLAGS $item
11780 set dg-do-what-default compile
11782 } elseif [istarget loongarch*-*-*] {
11783 # Set the default vectorization option to "-mlsx" due to the problem
11784 # of non-aligned memory access when using 256-bit vectorization.
11785 lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx"
11786 if [check_effective_target_loongarch_sx_hw] {
11787 set dg-do-what-default run
11789 set dg-do-what-default compile
11798 # Return 1 if the target does *not* require strict alignment.
11800 proc check_effective_target_non_strict_align {} {
11802 # On ARM, the default is to use STRICT_ALIGNMENT, but there
11803 # are interfaces defined for misaligned access and thus
11804 # depending on the architecture levels unaligned access is
11806 if [istarget "arm*-*-*"] {
11807 return [check_effective_target_arm_unaligned]
11810 return [check_no_compiler_messages non_strict_align assembly {
11812 typedef char __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))) c;
11814 void foo(void) { z = (c *) y; }
11818 # Return 1 if the target supports -mstrict-align (and -mno-strict-align).
11820 proc check_effective_target_opt_mstrict_align {} {
11821 return [check_no_compiler_messages opt_mstrict_align assembly {
11823 } "-mstrict-align -mno-strict-align"]
11826 # Return 1 if the target has <ucontext.h>.
11828 proc check_effective_target_ucontext_h { } {
11829 return [check_no_compiler_messages ucontext_h assembly {
11830 #include <ucontext.h>
11834 proc check_effective_target_aarch64_tiny { } {
11835 if { [istarget aarch64*-*-*] } {
11836 return [check_no_compiler_messages aarch64_tiny object {
11837 #ifdef __AARCH64_CMODEL_TINY__
11840 #error target not AArch64 tiny code model
11848 # Create functions to check that the AArch64 assembler supports the
11849 # various architecture extensions via the .arch_extension pseudo-op.
11851 foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
11852 "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64"
11853 "sme" "sme-i16i64" "sme2" } {
11854 eval [string map [list FUNC $aarch64_ext] {
11855 proc check_effective_target_aarch64_asm_FUNC_ok { } {
11856 if { [istarget aarch64*-*-*] } {
11857 return [check_no_compiler_messages aarch64_FUNC_assembler object {
11858 __asm__ (".arch_extension FUNC");
11859 } "-march=armv8-a+FUNC"]
11867 proc check_effective_target_aarch64_small { } {
11868 if { [istarget aarch64*-*-*] } {
11869 return [check_no_compiler_messages aarch64_small object {
11870 #ifdef __AARCH64_CMODEL_SMALL__
11873 #error target not AArch64 small code model
11881 proc check_effective_target_aarch64_large { } {
11882 if { [istarget aarch64*-*-*] } {
11883 return [check_no_compiler_messages aarch64_large object {
11884 #ifdef __AARCH64_CMODEL_LARGE__
11887 #error target not AArch64 large code model
11895 # Return 1 if the assembler accepts the aarch64 .variant_pcs directive.
11897 proc check_effective_target_aarch64_variant_pcs { } {
11898 if { [istarget aarch64*-*-*] } {
11899 return [check_no_compiler_messages aarch64_variant_pcs object {
11900 __asm__ (".variant_pcs foo");
11907 # Return 1 if this is a reduced AVR Tiny core. Such cores have different
11908 # register set, instruction set, addressing capabilities and ABI.
11910 proc check_effective_target_avr_tiny { } {
11911 if { [istarget avr*-*-*] } {
11912 return [check_no_compiler_messages avr_tiny object {
11913 #ifdef __AVR_TINY__
11916 #error target not a reduced AVR Tiny core
11924 # Return 1 if <fenv.h> is available.
11926 proc check_effective_target_fenv {} {
11927 return [check_no_compiler_messages fenv object {
11929 } [add_options_for_ieee "-std=gnu99"]]
11932 # Return 1 if <fenv.h> is available with all the standard IEEE
11933 # exceptions and floating-point exceptions are raised by arithmetic
11934 # operations. (If the target requires special options for "inexact"
11935 # exceptions, those need to be specified in the testcases.)
11937 proc check_effective_target_fenv_exceptions {} {
11938 return [check_runtime fenv_exceptions {
11940 #include <stdlib.h>
11941 #ifndef FE_DIVBYZERO
11942 # error Missing FE_DIVBYZERO
11945 # error Missing FE_INEXACT
11948 # error Missing FE_INVALID
11950 #ifndef FE_OVERFLOW
11951 # error Missing FE_OVERFLOW
11953 #ifndef FE_UNDERFLOW
11954 # error Missing FE_UNDERFLOW
11956 volatile float a = 0.0f, r;
11961 if (fetestexcept (FE_INVALID))
11966 } [add_options_for_ieee "-std=gnu99"]]
11969 # Return 1 if <fenv.h> is available with all the standard IEEE
11970 # exceptions and floating-point exceptions are raised by arithmetic
11971 # operations for decimal floating point. (If the target requires
11972 # special options for "inexact" exceptions, those need to be specified
11973 # in the testcases.)
11975 proc check_effective_target_fenv_exceptions_dfp {} {
11976 return [check_runtime fenv_exceptions_dfp {
11978 #include <stdlib.h>
11979 #ifndef FE_DIVBYZERO
11980 # error Missing FE_DIVBYZERO
11983 # error Missing FE_INEXACT
11986 # error Missing FE_INVALID
11988 #ifndef FE_OVERFLOW
11989 # error Missing FE_OVERFLOW
11991 #ifndef FE_UNDERFLOW
11992 # error Missing FE_UNDERFLOW
11994 volatile _Decimal64 a = 0.0DD, r;
11999 if (fetestexcept (FE_INVALID))
12004 } [add_options_for_ieee "-std=gnu99"]]
12007 # Return 1 if <fenv.h> is available with all the standard IEEE
12008 # exceptions and floating-point exceptions are raised by arithmetic
12009 # operations. (If the target requires special options for "inexact"
12010 # exceptions, those need to be specified in the testcases.)
12012 proc check_effective_target_fenv_exceptions_double {} {
12013 return [check_runtime fenv_exceptions_double {
12015 #include <stdlib.h>
12016 #ifndef FE_DIVBYZERO
12017 # error Missing FE_DIVBYZERO
12020 # error Missing FE_INEXACT
12023 # error Missing FE_INVALID
12025 #ifndef FE_OVERFLOW
12026 # error Missing FE_OVERFLOW
12028 #ifndef FE_UNDERFLOW
12029 # error Missing FE_UNDERFLOW
12031 volatile double a = 0.0f, r;
12036 if (fetestexcept (FE_INVALID))
12041 } [add_options_for_ieee "-std=gnu99"]]
12044 # Return 1 if <fenv.h> is available with all the standard IEEE
12045 # exceptions and floating-point exceptions are raised by arithmetic
12046 # operations. (If the target requires special options for "inexact"
12047 # exceptions, those need to be specified in the testcases.)
12049 proc check_effective_target_fenv_exceptions_long_double {} {
12050 return [check_runtime fenv_exceptions_long_double {
12052 #include <stdlib.h>
12053 #ifndef FE_DIVBYZERO
12054 # error Missing FE_DIVBYZERO
12057 # error Missing FE_INEXACT
12060 # error Missing FE_INVALID
12062 #ifndef FE_OVERFLOW
12063 # error Missing FE_OVERFLOW
12065 #ifndef FE_UNDERFLOW
12066 # error Missing FE_UNDERFLOW
12068 volatile long double a = 0.0f, r;
12073 if (fetestexcept (FE_INVALID))
12078 } [add_options_for_ieee "-std=gnu99"]]
12081 # Return 1 if -fexceptions is supported.
12083 proc check_effective_target_exceptions {} {
12084 if { [istarget amdgcn*-*-*] } {
12090 # Used to check if the testing configuration supports exceptions.
12091 # Returns 0 if exceptions are unsupported or disabled (e.g. by passing
12092 # -fno-exceptions). Returns 1 if exceptions are enabled.
12093 proc check_effective_target_exceptions_enabled {} {
12094 return [check_cached_effective_target exceptions_enabled {
12095 if { [check_effective_target_exceptions] } {
12096 return [check_no_compiler_messages exceptions_enabled assembly {
12104 # If exceptions aren't supported, then they're not enabled.
12110 proc check_effective_target_tiny {} {
12111 return [check_cached_effective_target tiny {
12112 if { [istarget aarch64*-*-*]
12113 && [check_effective_target_aarch64_tiny] } {
12116 if { [istarget avr-*-*]
12117 && [check_effective_target_avr_tiny] } {
12120 # PRU Program Counter is 16-bits, and trampolines are not supported.
12121 # Hence directly declare as a tiny target.
12122 if [istarget pru-*-*] {
12129 # Return 1 if the target supports -mbranch-cost=N option.
12131 proc check_effective_target_branch_cost {} {
12132 if { [ istarget arm*-*-*]
12133 || [istarget avr*-*-*]
12134 || [istarget csky*-*-*]
12135 || [istarget epiphany*-*-*]
12136 || [istarget frv*-*-*]
12137 || [istarget i?86-*-*] || [istarget x86_64-*-*]
12138 || [istarget loongarch*-*-*]
12139 || [istarget mips*-*-*]
12140 || [istarget s390*-*-*]
12141 || [istarget riscv*-*-*]
12142 || [istarget sh*-*-*] } {
12148 # Record that dg-final test TEST requires convential compilation.
12150 proc set_required_options_for { test } {
12151 if { [info proc $test] == "" } {
12152 perror "$test does not exist"
12155 proc ${test}_required_options {} {
12156 global gcc_set_required_options
12157 upvar 1 extra_tool_flags extra_tool_flags
12158 if {[regexp -- "^scan-assembler" [info level 0]]
12159 && ![string match "*-fident*" $extra_tool_flags]} {
12160 # Do not let .ident confuse assembler scan tests
12161 return [list $gcc_set_required_options "-fno-ident"]
12163 return $gcc_set_required_options
12167 # Record that dg-final test scan-ltrans-tree-dump* requires -flto-partition=one
12168 # in order to force a single partition, allowing scan-ltrans-tree-dump* to scan
12169 # a dump file *.exe.ltrans0.*.
12171 proc scan-ltrans-tree-dump_required_options {} {
12172 return "-flto-partition=one"
12174 proc scan-ltrans-tree-dump-times_required_options {} {
12175 return "-flto-partition=one"
12177 proc scan-ltrans-tree-dump-not_required_options {} {
12178 return "-flto-partition=one"
12180 proc scan-ltrans-tree-dump-dem_required_options {} {
12181 return "-flto-partition=one"
12183 proc scan-ltrans-tree-dump-dem-not_required_options {} {
12184 return "-flto-partition=one"
12187 # Return 1 if the x86-64 target supports PIE with copy reloc, 0
12188 # otherwise. Cache the result.
12190 proc check_effective_target_pie_copyreloc { } {
12192 global GCC_UNDER_TEST
12194 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12198 # Need auto-host.h to check linker support.
12199 if { ![file exists ../../auto-host.h ] } {
12203 return [check_cached_effective_target pie_copyreloc {
12204 # Set up and compile to see if linker supports PIE with copy
12205 # reloc. Include the current process ID in the file names to
12206 # prevent conflicts with invocations for multiple testsuites.
12211 set f [open $src "w"]
12212 puts $f "#include \"../../auto-host.h\""
12213 puts $f "#if HAVE_LD_PIE_COPYRELOC == 0"
12214 puts $f "# error Linker does not support PIE with copy reloc."
12218 verbose "check_effective_target_pie_copyreloc compiling testfile $src" 2
12219 set lines [${tool}_target_compile $src $obj object ""]
12224 if [string match "" $lines] then {
12225 verbose "check_effective_target_pie_copyreloc testfile compilation passed" 2
12228 verbose "check_effective_target_pie_copyreloc testfile compilation failed" 2
12234 # Return 1 if the x86 target supports R_386_GOT32X relocation, 0
12235 # otherwise. Cache the result.
12237 proc check_effective_target_got32x_reloc { } {
12239 global GCC_UNDER_TEST
12241 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12245 # Need auto-host.h to check linker support.
12246 if { ![file exists ../../auto-host.h ] } {
12250 return [check_cached_effective_target got32x_reloc {
12251 # Include the current process ID in the file names to prevent
12252 # conflicts with invocations for multiple testsuites.
12254 set src got32x[pid].c
12255 set obj got32x[pid].o
12257 set f [open $src "w"]
12258 puts $f "#include \"../../auto-host.h\""
12259 puts $f "#if HAVE_AS_IX86_GOT32X == 0"
12260 puts $f "# error Assembler does not support R_386_GOT32X."
12264 verbose "check_effective_target_got32x_reloc compiling testfile $src" 2
12265 set lines [${tool}_target_compile $src $obj object ""]
12270 if [string match "" $lines] then {
12271 verbose "check_effective_target_got32x_reloc testfile compilation passed" 2
12274 verbose "check_effective_target_got32x_reloc testfile compilation failed" 2
12279 return $got32x_reloc_available_saved
12282 # Return 1 if the x86 target supports calling ___tls_get_addr via GOT,
12283 # 0 otherwise. Cache the result.
12285 proc check_effective_target_tls_get_addr_via_got { } {
12287 global GCC_UNDER_TEST
12289 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12293 # Need auto-host.h to check linker support.
12294 if { ![file exists ../../auto-host.h ] } {
12298 return [check_cached_effective_target tls_get_addr_via_got {
12299 # Include the current process ID in the file names to prevent
12300 # conflicts with invocations for multiple testsuites.
12302 set src tls_get_addr_via_got[pid].c
12303 set obj tls_get_addr_via_got[pid].o
12305 set f [open $src "w"]
12306 puts $f "#include \"../../auto-host.h\""
12307 puts $f "#if HAVE_AS_IX86_TLS_GET_ADDR_GOT == 0"
12308 puts $f "# error Assembler/linker do not support calling ___tls_get_addr via GOT."
12312 verbose "check_effective_target_tls_get_addr_via_got compiling testfile $src" 2
12313 set lines [${tool}_target_compile $src $obj object ""]
12318 if [string match "" $lines] then {
12319 verbose "check_effective_target_tls_get_addr_via_got testfile compilation passed" 2
12322 verbose "check_effective_target_tls_get_addr_via_got testfile compilation failed" 2
12328 # Return 1 if the target uses comdat groups.
12330 proc check_effective_target_comdat_group {} {
12331 return [check_no_messages_and_pattern comdat_group "\.section\[^\n\r]*,comdat|\.group\[^\n\r]*,#comdat" assembly {
12333 inline int foo () { return 1; }
12334 int (*fn) () = foo;
12338 # Return 1 if target supports __builtin_eh_return
12339 proc check_effective_target_builtin_eh_return { } {
12340 return [check_no_compiler_messages builtin_eh_return object {
12341 void test (long l, void *p)
12343 __builtin_eh_return (l, p);
12348 # Return 1 if the target supports max reduction for vectors.
12350 proc check_effective_target_vect_max_reduc { } {
12351 if { [istarget aarch64*-*-*] || [is-effective-target arm_neon]
12352 || [check_effective_target_riscv_v]
12353 || [check_effective_target_loongarch_sx] } {
12359 # Return 1 if the compiler has been configured with nvptx offloading.
12361 proc check_effective_target_offload_nvptx { } {
12362 return [check_no_compiler_messages offload_nvptx assembly {
12363 int main () {return 0;}
12364 } "-foffload=nvptx-none" ]
12367 # Return 1 if the compiler has been configured with gcn offloading.
12369 proc check_effective_target_offload_gcn { } {
12370 return [check_no_compiler_messages offload_gcn assembly {
12371 int main () {return 0;}
12372 } "-foffload=amdgcn-amdhsa" ]
12375 # Return 1 if the target support -fprofile-update=atomic
12376 proc check_effective_target_profile_update_atomic {} {
12377 return [check_no_compiler_messages profile_update_atomic assembly {
12378 int main (void) { return 0; }
12379 } "-fprofile-update=atomic -fprofile-generate"]
12382 # Return 1 if vector (va - vector add) instructions are understood by
12383 # the assembler and can be executed. This also covers checking for
12384 # the VX kernel feature. A kernel without that feature does not
12385 # enable the vector facility and the following check will die with a
12387 proc check_effective_target_s390_vx { } {
12388 if ![istarget s390*-*-*] then {
12392 return [check_runtime s390_check_vx {
12395 asm ("va %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12398 } "-march=z13 -mzarch" ]
12401 # Same as above but for the z14 vector enhancement facility. Test
12402 # is performed with the vector nand instruction.
12403 proc check_effective_target_s390_vxe { } {
12404 if ![istarget s390*-*-*] then {
12408 return [check_runtime s390_check_vxe {
12411 asm ("vnn %%v24, %%v26, %%v28" : : : "v24", "v26", "v28");
12414 } "-march=z14 -mzarch" ]
12417 # Same as above but for the arch13 vector enhancement facility. Test
12418 # is performed with the vector shift left double by bit instruction.
12419 proc check_effective_target_s390_vxe2 { } {
12420 if ![istarget s390*-*-*] then {
12424 return [check_runtime s390_check_vxe2 {
12427 asm ("vsld %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12430 } "-march=arch13 -mzarch" ]
12433 # Same as above but for the arch14 NNPA facility.
12434 proc check_effective_target_s390_nnpa { } {
12435 if ![istarget s390*-*-*] then {
12439 return [check_runtime s390_check_nnpa {
12442 asm ("vzero %%v24\n\t"
12443 "vcrnf %%v24,%%v24,%%v24,0,2" : : : "v24");
12446 } "-march=arch14 -mzarch" ]
12449 #For versions of ARM architectures that have hardware div insn,
12450 #disable the divmod transform
12452 proc check_effective_target_arm_divmod_simode { } {
12453 return [check_no_compiler_messages arm_divmod assembly {
12454 #ifdef __ARM_ARCH_EXT_IDIV__
12455 #error has div insn
12461 # Return 1 if target supports divmod hardware insn or divmod libcall.
12463 proc check_effective_target_divmod { } {
12464 #TODO: Add checks for all targets that have either hardware divmod insn
12465 # or define libfunc for divmod.
12466 if { [istarget arm*-*-*]
12467 || [istarget i?86-*-*] || [istarget x86_64-*-*]
12468 || [istarget amdgcn-*-*] } {
12474 # Return 1 if target supports divmod for SImode. The reason for
12475 # separating this from check_effective_target_divmod is that
12476 # some versions of ARM architecture define div instruction
12477 # only for simode, and for these archs, we do not want to enable
12478 # divmod transform for simode.
12480 proc check_effective_target_divmod_simode { } {
12481 if { [istarget arm*-*-*] } {
12482 return [check_effective_target_arm_divmod_simode]
12485 return [check_effective_target_divmod]
12488 # Return 1 if store merging optimization is applicable for target.
12489 # Store merging is not profitable for targets like the avr which
12490 # can load/store only one byte at a time. Use int size as a proxy
12491 # for the number of bytes the target can write, and skip for targets
12492 # with a smallish (< 32) size.
12494 proc check_effective_target_store_merge { } {
12495 if { [is-effective-target non_strict_align ] && [is-effective-target int32plus] } {
12502 # Return 1 if we're able to assemble rdrand
12504 proc check_effective_target_rdrand { } {
12505 return [check_no_compiler_messages_nocache rdrand object {
12510 __builtin_ia32_rdrand32_step(&val);
12516 # Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl,
12517 # stc, stcl, mcr and mrc.
12518 proc check_effective_target_arm_coproc1_ok_nocache { } {
12519 if { ![istarget arm*-*-*] } {
12522 return [check_no_compiler_messages_nocache arm_coproc1_ok assembly {
12523 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 4
12526 #include <arm_acle.h>
12530 proc check_effective_target_arm_coproc1_ok { } {
12531 return [check_cached_effective_target arm_coproc1_ok \
12532 check_effective_target_arm_coproc1_ok_nocache]
12535 # Return 1 if the target supports all coprocessor instructions checked by
12536 # check_effective_target_arm_coproc1_ok in addition to the following: cdp2,
12537 # ldc2, ldc2l, stc2, stc2l, mcr2 and mrc2.
12538 proc check_effective_target_arm_coproc2_ok_nocache { } {
12539 if { ![check_effective_target_arm_coproc1_ok] } {
12542 return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
12543 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5
12546 #include <arm_acle.h>
12550 proc check_effective_target_arm_coproc2_ok { } {
12551 return [check_cached_effective_target arm_coproc2_ok \
12552 check_effective_target_arm_coproc2_ok_nocache]
12555 # Return 1 if the target supports all coprocessor instructions checked by
12556 # check_effective_target_arm_coproc2_ok in addition the following: mcrr and
12558 proc check_effective_target_arm_coproc3_ok_nocache { } {
12559 if { ![check_effective_target_arm_coproc2_ok] } {
12562 return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
12563 #if (__thumb__ && !__thumb2__) \
12564 || (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__))
12567 #include <arm_acle.h>
12571 proc check_effective_target_arm_coproc3_ok { } {
12572 return [check_cached_effective_target arm_coproc3_ok \
12573 check_effective_target_arm_coproc3_ok_nocache]
12576 # Return 1 if the target supports all coprocessor instructions checked by
12577 # check_effective_target_arm_coproc3_ok in addition the following: mcrr2 and
12579 proc check_effective_target_arm_coproc4_ok_nocache { } {
12580 if { ![check_effective_target_arm_coproc3_ok] } {
12583 return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
12584 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6
12587 #include <arm_acle.h>
12591 proc check_effective_target_arm_coproc4_ok { } {
12592 return [check_cached_effective_target arm_coproc4_ok \
12593 check_effective_target_arm_coproc4_ok_nocache]
12596 # Return 1 if the target supports the auto_inc_dec optimization pass.
12597 proc check_effective_target_autoincdec { } {
12598 if { ![check_no_compiler_messages auto_incdec assembly { void f () { }
12599 } "-O2 -fdump-rtl-auto_inc_dec" ] } {
12603 set dumpfile [glob -nocomplain "auto_incdec[pid].c.\[0-9\]\[0-9\]\[0-9\]r.auto_inc_dec"]
12604 if { [file exists $dumpfile ] } {
12605 file delete $dumpfile
12611 # Return 1 if the target has support for stack probing designed
12612 # to avoid stack-clash style attacks.
12614 # This is used to restrict the stack-clash mitigation tests to
12615 # just those targets that have been explicitly supported.
12617 # In addition to the prologue work on those targets, each target's
12618 # properties should be described in the functions below so that
12619 # tests do not become a mess of unreadable target conditions.
12621 proc check_effective_target_supports_stack_clash_protection { } {
12623 if { [istarget x86_64-*-*] || [istarget i?86-*-*]
12624 || [istarget powerpc*-*-*] || [istarget rs6000*-*-*]
12625 || [istarget aarch64*-**] || [istarget s390*-*-*]
12626 || [istarget loongarch64*-**] } {
12632 # Return 1 if the target creates a frame pointer for non-leaf functions
12633 # Note we ignore cases where we apply tail call optimization here.
12634 proc check_effective_target_frame_pointer_for_non_leaf { } {
12635 # Solaris/x86 defaults to -fno-omit-frame-pointer.
12636 if { [istarget i?86-*-solaris*] || [istarget x86_64-*-solaris*] } {
12643 # Return 1 if the target can perform tail-call optimizations of the
12644 # most trivial type.
12645 proc check_effective_target_tail_call { } {
12646 return [check_no_messages_and_pattern tail_call ",SIBCALL" rtl-expand {
12647 __attribute__((__noipa__)) void foo (void) { }
12648 __attribute__((__noipa__)) void bar (void) { foo(); }
12649 } {-O2 -fdump-rtl-expand-all}] ;# The "SIBCALL" note requires a detailed dump.
12652 # Return 1 if the target's calling sequence or its ABI
12653 # create implicit stack probes at or prior to function entry.
12654 proc check_effective_target_caller_implicit_probes { } {
12656 # On x86/x86_64 the call instruction itself pushes the return
12657 # address onto the stack. That is an implicit probe of *sp.
12658 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12662 # On PPC, the ABI mandates that the address of the outer
12663 # frame be stored at *sp. Thus each allocation of stack
12664 # space is itself an implicit probe of *sp.
12665 if { [istarget powerpc*-*-*] || [istarget rs6000*-*-*] } {
12669 # s390's ABI has a register save area allocated by the
12670 # caller for use by the callee. The mere existence does
12671 # not constitute a probe by the caller, but when the slots
12672 # used by the callee those stores are implicit probes.
12673 if { [istarget s390*-*-*] } {
12677 # Not strictly true on aarch64, but we have agreed that we will
12678 # consider any function that pushes SP more than 3kbytes into
12679 # the guard page as broken. This essentially means that we can
12680 # consider the aarch64 as having a caller implicit probe at
12682 if { [istarget aarch64*-*-*] } {
12686 if { [istarget loongarch64*-*-*] } {
12693 # Targets that potentially realign the stack pointer often cause residual
12694 # stack allocations and make it difficult to elimination loops or residual
12695 # allocations for dynamic stack allocations
12696 proc check_effective_target_callee_realigns_stack { } {
12697 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12703 # Return 1 if CET instructions can be compiled.
12704 proc check_effective_target_cet { } {
12705 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12708 return [check_no_compiler_messages cet object {
12713 } "-O2 -fcf-protection" ]
12716 # Return 1 if target supports floating point "infinite"
12717 proc check_effective_target_inf { } {
12718 return [check_no_compiler_messages supports_inf assembly {
12719 const double pinf = __builtin_inf ();
12723 # Return 1 if target supports floating point "infinite" for float.
12724 proc check_effective_target_inff { } {
12725 return [check_no_compiler_messages supports_inff assembly {
12726 const float pinf = __builtin_inff ();
12730 # Return 1 if the target supports ARMv8.3 Adv.SIMD Complex instructions
12731 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
12732 # Record the command line options needed.
12734 proc check_effective_target_arm_v8_3a_complex_neon_ok_nocache { } {
12735 global et_arm_v8_3a_complex_neon_flags
12736 set et_arm_v8_3a_complex_neon_flags ""
12738 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
12742 # Iterate through sets of options to find the compiler flags that
12743 # need to be added to the -march option.
12744 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12745 if { [check_no_compiler_messages_nocache \
12746 arm_v8_3a_complex_neon_ok assembly {
12747 #if !defined (__ARM_FEATURE_COMPLEX)
12748 #error "__ARM_FEATURE_COMPLEX not defined"
12750 } "$flags -march=armv8.3-a"] } {
12751 set et_arm_v8_3a_complex_neon_flags "$flags -march=armv8.3-a"
12759 proc check_effective_target_arm_v8_3a_complex_neon_ok { } {
12760 return [check_cached_effective_target arm_v8_3a_complex_neon_ok \
12761 check_effective_target_arm_v8_3a_complex_neon_ok_nocache]
12764 proc add_options_for_arm_v8_3a_complex_neon { flags } {
12765 if { ! [check_effective_target_arm_v8_3a_complex_neon_ok] } {
12768 global et_arm_v8_3a_complex_neon_flags
12769 return "$flags $et_arm_v8_3a_complex_neon_flags"
12772 # Return 1 if the target supports ARMv8.3 Adv.SIMD + FP16 Complex instructions
12773 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
12774 # Record the command line options needed.
12776 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache { } {
12777 global et_arm_v8_3a_fp16_complex_neon_flags
12778 set et_arm_v8_3a_fp16_complex_neon_flags ""
12780 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
12784 # Iterate through sets of options to find the compiler flags that
12785 # need to be added to the -march option.
12786 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12787 if { [check_no_compiler_messages_nocache \
12788 arm_v8_3a_fp16_complex_neon_ok assembly {
12789 #if !defined (__ARM_FEATURE_COMPLEX)
12790 #error "__ARM_FEATURE_COMPLEX not defined"
12792 } "$flags -march=armv8.3-a+fp16"] } {
12793 set et_arm_v8_3a_fp16_complex_neon_flags \
12794 "$flags -march=armv8.3-a+fp16"
12802 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok { } {
12803 return [check_cached_effective_target arm_v8_3a_fp16_complex_neon_ok \
12804 check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache]
12807 proc add_options_for_arm_v8_3a_fp16_complex_neon { flags } {
12808 if { ! [check_effective_target_arm_v8_3a_fp16_complex_neon_ok] } {
12811 global et_arm_v8_3a_fp16_complex_neon_flags
12812 return "$flags $et_arm_v8_3a_fp16_complex_neon_flags"
12816 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.3
12817 # with the complex instruction extension, 0 otherwise. The test is valid for
12818 # ARM and for AArch64.
12820 proc check_effective_target_arm_v8_3a_complex_neon_hw { } {
12821 if { ![check_effective_target_arm_v8_3a_complex_neon_ok] } {
12824 return [check_runtime arm_v8_3a_complex_neon_hw_available {
12825 #include "arm_neon.h"
12830 float32x2_t results = {-4.0,5.0};
12831 float32x2_t a = {1.0,3.0};
12832 float32x2_t b = {2.0,5.0};
12834 #ifdef __ARM_ARCH_ISA_A64
12835 asm ("fcadd %0.2s, %1.2s, %2.2s, #90"
12838 : /* No clobbers. */);
12841 asm ("vcadd.f32 %P0, %P1, %P2, #90"
12844 : /* No clobbers. */);
12847 return (results[0] == 8 && results[1] == 24) ? 0 : 1;
12849 } [add_options_for_arm_v8_3a_complex_neon ""]]
12852 # Return 1 if the assembler supports assembling the Armv8.3 pointer authentication B key directive
12853 proc check_effective_target_arm_v8_3a_bkey_directive { } {
12854 return [check_no_compiler_messages cet object {
12856 asm (".cfi_b_key_frame");
12862 # Return 1 if the target supports executing the Armv8.1-M Mainline Low
12863 # Overhead Loop, 0 otherwise. The test is valid for ARM.
12865 proc check_effective_target_arm_v8_1_lob_ok { } {
12866 if { ![check_effective_target_arm_cortex_m] } {
12869 return [check_runtime arm_v8_1_lob_hw_available {
12873 asm ("movw r3, #10\n\t" /* movs? */
12874 "dls lr, r3" : : : "r3", "lr");
12877 asm goto ("le lr, %l0" : : : "lr" : loop);
12880 } "-march=armv8.1-m.main -mthumb" ]
12884 # Return 1 if this is an ARM target where Thumb-2 is used without
12885 # options added by the test and the target does not support executing
12886 # the Armv8.1-M Mainline Low Overhead Loop, 0 otherwise. The test is
12889 proc check_effective_target_arm_thumb2_no_arm_v8_1_lob { } {
12890 if { [check_effective_target_arm_thumb2]
12891 && ![check_effective_target_arm_v8_1_lob_ok] } {
12897 # Return 1 if this is an ARM target where -mthumb causes Thumb-2 to be
12898 # used and the target does not support executing the Armv8.1-M
12899 # Mainline Low Overhead Loop, 0 otherwise. The test is valid for ARM.
12901 proc check_effective_target_arm_thumb2_ok_no_arm_v8_1_lob { } {
12902 if { [check_effective_target_arm_thumb2_ok]
12903 && ![check_effective_target_arm_v8_1_lob_ok] } {
12909 # Returns 1 if the target is using glibc, 0 otherwise.
12911 proc check_effective_target_glibc { } {
12912 return [check_no_compiler_messages glibc_object assembly {
12913 #include <stdlib.h>
12914 #if !defined(__GLIBC__)
12920 # Return 1 if the target plus current options supports a vector
12921 # complex addition with rotate of half and single float modes, 0 otherwise.
12923 # This won't change for different subtargets so cache the result.
12925 foreach N {hf sf} {
12926 eval [string map [list N $N] {
12927 proc check_effective_target_vect_complex_rot_N { } {
12928 return [check_cached_effective_target_indexed vect_complex_rot_N {
12929 expr { [istarget aarch64*-*-*]
12930 || [istarget arm*-*-*] }}]
12935 # Return 1 if the target plus current options supports a vector
12936 # complex addition with rotate of double float modes, 0 otherwise.
12938 # This won't change for different subtargets so cache the result.
12941 eval [string map [list N $N] {
12942 proc check_effective_target_vect_complex_rot_N { } {
12943 return [check_cached_effective_target_indexed vect_complex_rot_N {
12944 expr { [istarget aarch64*-*-*] }}]
12949 # Return 1 if this target uses an LLVM assembler and/or linker
12950 proc check_effective_target_llvm_binutils { } {
12951 return [check_cached_effective_target llvm_binutils {
12952 expr { [istarget amdgcn*-*-*]
12953 || [check_effective_target_offload_gcn] }}]
12956 # Return 1 if the compiler supports '-mfentry'.
12958 proc check_effective_target_mfentry { } {
12959 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
12962 return [check_no_compiler_messages mfentry object {
12963 void foo (void) { }
12967 # Return 1 if this target supports indirect calls
12968 proc check_effective_target_indirect_calls { } {
12969 if { [istarget bpf-*-*] } {
12975 # Return 1 if we can use the -lgccjit option, 0 otherwise.
12977 proc check_effective_target_lgccjit { } {
12978 if { [info procs jit_target_compile] == "" } then {
12979 global GCC_UNDER_TEST
12980 if ![info exists GCC_UNDER_TEST] {
12981 set GCC_UNDER_TEST "[find_gcc]"
12983 proc jit_target_compile { source dest type options } [info body gcc_target_compile]
12985 return [check_no_compiler_messages lgccjit executable {
12986 int main() { return 0; }
12990 # Return 1 if the MSP430 small memory model is in use.
12991 proc check_effective_target_msp430_small {} {
12992 return [check_no_compiler_messages msp430_small assembly {
12993 #if (!defined __MSP430__ || defined __MSP430X_LARGE__)
12994 #error !msp430 || __MSP430X_LARGE__
12999 # Return 1 if the MSP430 large memory model is in use.
13000 proc check_effective_target_msp430_large {} {
13001 return [check_no_compiler_messages msp430_large assembly {
13002 #ifndef __MSP430X_LARGE__
13003 #error __MSP430X_LARGE__
13008 # Return 1 if GCC was configured with --with-tune=cortex-a76
13009 proc check_effective_target_tune_cortex_a76 { } {
13010 return [check_configured_with "with-tune=cortex-a76"]
13013 # Return 1 if the target has an efficient means to encode large initializers
13016 proc check_effective_target_large_initializer { } {
13017 if { [istarget nvptx*-*-*] } {
13024 # Return 1 if the target allows function prototype mismatches
13027 proc check_effective_target_non_strict_prototype { } {
13028 if { [istarget nvptx*-*-*] } {
13035 # Returns 1 if the target toolchain supports extended
13036 # syntax of .symver directive, 0 otherwise.
13038 proc check_symver_available { } {
13039 return [check_no_compiler_messages symver_available object {
13040 int foo(void) { return 0; }
13042 asm volatile (".symver foo,foo@VER_1, local");
13048 # Return 1 if emitted assembly contains .ident directive.
13050 proc check_effective_target_ident_directive {} {
13051 return [check_no_messages_and_pattern ident_directive \
13052 "(?n)^\[\t\]+\\.ident" assembly {
13057 # Return 1 if we're able to assemble movdiri and movdir64b
13059 proc check_effective_target_movdir { } {
13060 return [check_no_compiler_messages movdir object {
13062 foo (unsigned int *d, unsigned int s)
13064 __builtin_ia32_directstoreu_u32 (d, s);
13067 bar (void *d, const void *s)
13069 __builtin_ia32_movdir64b (d, s);
13071 } "-mmovdiri -mmovdir64b" ]
13074 # Return 1 if the target does not support address sanitizer, 0 otherwise
13076 proc check_effective_target_no_fsanitize_address {} {
13077 if ![check_no_compiler_messages fsanitize_address executable {
13078 int main (void) { return 0; }
13079 } "-fsanitize=address" ] {
13086 # Return 1 if this target supports 'R' flag in .section directive, 0
13087 # otherwise. Cache the result.
13089 proc check_effective_target_R_flag_in_section { } {
13091 global GCC_UNDER_TEST
13093 # Need auto-host.h to check linker support.
13094 if { ![file exists ../../auto-host.h ] } {
13098 return [check_cached_effective_target R_flag_in_section {
13103 set f [open $src "w"]
13104 puts $f "#include \"../../auto-host.h\""
13105 puts $f "#if HAVE_GAS_SHF_GNU_RETAIN == 0 || HAVE_INITFINI_ARRAY_SUPPORT == 0"
13106 puts $f "# error Assembler does not support 'R' flag in .section directive."
13110 verbose "check_effective_target_R_flag_in_section compiling testfile $src" 2
13111 set lines [${tool}_target_compile $src $obj assembly ""]
13116 if [string match "" $lines] then {
13117 verbose "check_effective_target_R_flag_in_section testfile compilation passed" 2
13120 verbose "check_effective_target_R_flag_in_section testfile compilation failed" 2
13126 # Return 1 if this target supports 'o' flag in .section directive, 0
13127 # otherwise. Cache the result.
13129 proc check_effective_target_o_flag_in_section { } {
13131 global GCC_UNDER_TEST
13133 # Need auto-host.h to check linker support.
13134 if { ![file exists ../../auto-host.h ] } {
13138 return [check_cached_effective_target o_flag_in_section {
13143 set f [open $src "w"]
13144 puts $f "#include \"../../auto-host.h\""
13145 puts $f "#if HAVE_GAS_SECTION_LINK_ORDER == 0"
13146 puts $f "# error Assembler does not support 'o' flag in .section directive."
13150 verbose "check_effective_target_o_flag_in_section compiling testfile $src" 2
13151 set lines [${tool}_target_compile $src $obj object ""]
13156 if [string match "" $lines] then {
13157 verbose "check_effective_target_o_flag_in_section testfile compilation passed" 2
13160 verbose "check_effective_target_o_flag_in_section testfile compilation failed" 2
13166 # Return 1 if the given assembler supports hardware transactional memory
13167 # instructions with machine type Power10, 0 otherwise. Cache the result.
13169 proc check_effective_target_powerpc_as_p10_htm { } {
13171 global GCC_UNDER_TEST
13173 # Need auto-host.h to check linker support.
13174 if { ![file exists ../../auto-host.h ] } {
13178 return [check_cached_effective_target powerpc_as_p10_htm {
13183 set f [open $src "w"]
13184 puts $f "#include \"../../auto-host.h\""
13185 puts $f "#if HAVE_AS_POWER10_HTM == 0"
13186 puts $f "# error Assembler does not support htm insns with power10."
13190 verbose "check_effective_target_powerpc_as_p10_htm compiling testfile $src" 2
13191 set lines [${tool}_target_compile $src $obj object ""]
13196 if [string match "" $lines] then {
13197 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation passed" 2
13200 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation failed" 2
13206 # return 1 if LRA is supported.
13208 proc check_effective_target_lra { } {
13209 if { [istarget hppa*-*-*] || [istarget avr-*-*] } {
13215 # Test whether optimizations are enabled ('__OPTIMIZE__') per the
13216 # 'current_compiler_flags' (thus don't cache).
13218 proc check_effective_target___OPTIMIZE__ {} {
13219 return [check_no_compiler_messages_nocache __OPTIMIZE__ assembly {
13220 #ifndef __OPTIMIZE__
13223 /* Avoid pedwarn about empty TU. */
13225 } [current_compiler_flags]]
13228 # Return 1 if python3 (>= 3.6) is available.
13230 proc check_effective_target_recent_python3 { } {
13231 set result [remote_exec host "python3 -c \"import sys; assert sys.version_info >= (3, 6)\""]
13232 set status [lindex $result 0]
13233 if { $status == 0 } then {
13240 # Return 1 if python3 contains a module
13242 proc check_effective_target_python3_module { module } {
13243 set result [remote_exec host "python3 -c \"import $module\""]
13244 set status [lindex $result 0]
13245 if { $status == 0 } then {
13252 # Return 1 if pytest module is available for python3.
13254 proc check_effective_target_pytest3 { } {
13255 set result [remote_exec host "python3 -m pytest --color=no -rap -s --tb=no --version"]
13256 set status [lindex $result 0]
13257 if { $status == 0 } then {
13264 proc check_effective_target_property_1_needed { } {
13265 return [check_no_compiler_messages property_1_needed executable {
13266 /* Assembly code */
13268 # define __PROPERTY_ALIGN 3
13270 # define __PROPERTY_ALIGN 2
13273 .section ".note.gnu.property", "a"
13274 .p2align __PROPERTY_ALIGN
13275 .long 1f - 0f /* name length. */
13276 .long 4f - 1f /* data length. */
13277 /* NT_GNU_PROPERTY_TYPE_0. */
13278 .long 5 /* note type. */
13280 .asciz "GNU" /* vendor name. */
13282 .p2align __PROPERTY_ALIGN
13283 /* GNU_PROPERTY_1_NEEDED. */
13284 .long 0xb0008000 /* pr_type. */
13285 .long 3f - 2f /* pr_datasz. */
13287 /* GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. */
13290 .p2align __PROPERTY_ALIGN
13299 # Return 1 if this target has prog named "$prog", 0 otherwise.
13301 proc check_is_prog_name_available { prog } {
13304 set options [list "additional_flags=-print-prog-name=$prog"]
13305 set output [lindex [${tool}_target_compile "" "" "none" $options] 0]
13307 if { $output == $prog } {
13314 # returns 1 if target does selects a readonly section for const volatile variables.
13315 proc check_effective_target_const_volatile_readonly_section { } {
13317 if { [istarget powerpc-*-*]
13318 || [check-flags { "" { powerpc64-*-* } { -m32 } }] } {
13324 # Return 1 if the CORE-V MAC extension is available.
13325 proc check_effective_target_cv_mac { } {
13326 if { !([istarget riscv*-*-*]) } {
13329 return [check_no_compiler_messages cv_mac object {
13332 asm ("cv.mac t0, t1, t2");
13334 } "-march=rv32i_xcvmac" ]
13337 # Return 1 if the CORE-V ALU extension is available.
13338 proc check_effective_target_cv_alu { } {
13339 if { !([istarget riscv*-*-*]) } {
13342 return [check_no_compiler_messages cv_alu object {
13345 asm ("cv.addn t0, t1, t2, 0");
13347 } "-march=rv32i_xcvalu" ]
13350 # Return 1 if the CORE-V ELW extension is available.
13351 proc check_effective_target_cv_elw { } {
13352 if { !([istarget riscv*-*-*]) } {
13355 return [check_no_compiler_messages cv_elw object {
13358 asm ("cv.elw x0, 0(x0)");
13360 } "-march=rv32i_xcvelw" ]
13363 # Return 1 if the CORE-V SIMD extension is available.
13364 proc check_effective_target_cv_simd { } {
13365 if { !([istarget riscv*-*-*]) } {
13368 return [check_no_compiler_messages cv_simd object {
13371 asm ("cv.add.sc.b x0, x0, x0");
13373 } "-march=rv32i_xcvsimd" ]
13376 proc check_effective_target_loongarch_sx { } {
13377 return [check_no_compiler_messages loongarch_lsx assembly {
13378 #if !defined(__loongarch_sx)
13379 #error "LSX not defined"
13384 proc check_effective_target_loongarch_sx_hw { } {
13385 return [check_runtime loongarch_sx_hw {
13386 #include <lsxintrin.h>
13390 c = __lsx_vand_v (a, b);
13396 proc check_effective_target_loongarch_asx { } {
13397 return [check_no_compiler_messages loongarch_asx assembly {
13398 #if !defined(__loongarch_asx)
13399 #error "LASX not defined"
13404 proc check_effective_target_loongarch_asx_hw { } {
13405 return [check_runtime loongarch_asx_hw {
13406 #include <lasxintrin.h>
13410 c = __lasx_xvand_v (a, b);
13416 # Check whether LoongArch binutils supports call36 relocation.
13417 proc check_effective_target_loongarch_call36_support { } {
13418 return [check_no_compiler_messages loongarch_call36_support object {
13419 /* Assembly code */
13420 pcaddu18i $r1,%call36(a)
13425 # Returns 1 if binutils supports TLS le Relax, 0 otherwise.
13426 proc check_effective_target_tls_le_relax { } {
13427 if [check_effective_target_tls_native] {
13428 return [check_no_compiler_messages loongarch_tls_le_relax object {
13429 /* Assembly code */
13430 lu12i.w $r12, %le_hi20_r(a)
13437 # Appends necessary Python flags to extra-tool-flags if Python.h is supported.
13438 # Otherwise, modifies dg-do-what.
13439 proc dg-require-python-h { args } {
13440 upvar dg-extra-tool-flags extra-tool-flags
13442 verbose "ENTER dg-require-python-h" 2
13445 set result [remote_exec host "python3-config --includes"]
13446 set status [lindex $result 0]
13447 if { $status == 0 } {
13448 # Remove trailing newline from python3-config output.
13449 set python_flags [string trim [lindex $result 1]]
13450 if [check_no_compiler_messages python_h assembly {
13451 #include <Python.h>
13452 int main (void) { return 0; }
13458 if { $supported == 0 } {
13459 verbose "Python.h not supported" 2
13460 upvar dg-do-what dg-do-what
13461 set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
13465 verbose "Python flags are: $python_flags" 2
13467 verbose "Before appending, extra-tool-flags: ${extra-tool-flags}" 3
13468 eval lappend extra-tool-flags $python_flags
13469 verbose "After appending, extra-tool-flags: ${extra-tool-flags}" 3