gdb/arch/aarch64-insn.h

   1 /* Copyright (C) 2009-2021 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARCH_AARCH64_INSN_H
  20 #define ARCH_AARCH64_INSN_H
  21
  22 extern bool aarch64_debug;
  23
  24 /* Support routines for instruction parsing.  */
  25
  26 /* Create a mask of X bits.  */
  27 #define submask(x) ((1L << ((x) + 1)) - 1)
  28
  29 /* Extract the bitfield from OBJ starting at bit ST and ending at bit FN.  */
  30 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
  31
  32 /* Extract bit ST from OBJ.  */
  33 #define bit(obj,st) (((obj) >> (st)) & 1)
  34
  35 /* Extract the signed bitfield from OBJ starting at bit ST and ending at
  36    bit FN.  The result is sign-extended.  */
  37 #define sbits(obj,st,fn) \
  38   ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
  39
  40 /* List of opcodes that we need for building the jump pad and relocating
  41    an instruction.  */
  42
  43 enum aarch64_opcodes
  44 {
  45   /* B              0001 01ii iiii iiii iiii iiii iiii iiii */
  46   /* BL             1001 01ii iiii iiii iiii iiii iiii iiii */
  47   /* B.COND         0101 0100 iiii iiii iiii iiii iii0 cccc */
  48   /* CBZ            s011 0100 iiii iiii iiii iiii iiir rrrr */
  49   /* CBNZ           s011 0101 iiii iiii iiii iiii iiir rrrr */
  50   /* TBZ            b011 0110 bbbb biii iiii iiii iiir rrrr */
  51   /* TBNZ           b011 0111 bbbb biii iiii iiii iiir rrrr */
  52   B               = 0x14000000,
  53   BL              = 0x80000000 | B,
  54   BCOND           = 0x40000000 | B,
  55   CBZ             = 0x20000000 | B,
  56   CBNZ            = 0x21000000 | B,
  57   TBZ             = 0x36000000 | B,
  58   TBNZ            = 0x37000000 | B,
  59   /* BLR            1101 0110 0011 1111 0000 00rr rrr0 0000 */
  60   BLR             = 0xd63f0000,
  61   /* RET            1101 0110 0101 1111 0000 00rr rrr0 0000 */
  62   RET             = 0xd65f0000,
  63   /* STP            s010 100o o0ii iiii irrr rrrr rrrr rrrr */
  64   /* LDP            s010 100o o1ii iiii irrr rrrr rrrr rrrr */
  65   /* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
  66   /* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
  67   STP             = 0x28000000,
  68   LDP             = 0x28400000,
  69   STP_SIMD_VFP    = 0x04000000 | STP,
  70   LDP_SIMD_VFP    = 0x04000000 | LDP,
  71   /* STR            ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
  72   /* LDR            ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
  73   /* LDRSW          1011 100o 10xi iiii iiii xxrr rrrr rrrr */
  74   STR             = 0x38000000,
  75   LDR             = 0x00400000 | STR,
  76   LDRSW           = 0x80800000 | STR,
  77   /* LDAXR          ss00 1000 0101 1111 1111 11rr rrrr rrrr */
  78   LDAXR           = 0x085ffc00,
  79   /* STXR           ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
  80   STXR            = 0x08007c00,
  81   /* STLR           ss00 1000 1001 1111 1111 11rr rrrr rrrr */
  82   STLR            = 0x089ffc00,
  83   /* MOV            s101 0010 1xxi iiii iiii iiii iiir rrrr */
  84   /* MOVK           s111 0010 1xxi iiii iiii iiii iiir rrrr */
  85   MOV             = 0x52800000,
  86   MOVK            = 0x20000000 | MOV,
  87   /* ADD            s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
  88   /* SUB            s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
  89   /* SUBS           s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
  90   ADD             = 0x01000000,
  91   SUB             = 0x40000000 | ADD,
  92   SUBS            = 0x20000000 | SUB,
  93   /* AND            s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
  94   /* ORR            s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
  95   /* ORN            s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
  96   /* EOR            s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
  97   AND             = 0x0a000000,
  98   ORR             = 0x20000000 | AND,
  99   ORN             = 0x00200000 | ORR,
 100   EOR             = 0x40000000 | AND,
 101   /* LSLV           s001 1010 110r rrrr 0010 00rr rrrr rrrr */
 102   /* LSRV           s001 1010 110r rrrr 0010 01rr rrrr rrrr */
 103   /* ASRV           s001 1010 110r rrrr 0010 10rr rrrr rrrr */
 104   LSLV             = 0x1ac02000,
 105   LSRV             = 0x00000400 | LSLV,
 106   ASRV             = 0x00000800 | LSLV,
 107   /* SBFM           s001 0011 0nii iiii iiii iirr rrrr rrrr */
 108   SBFM            = 0x13000000,
 109   /* UBFM           s101 0011 0nii iiii iiii iirr rrrr rrrr */
 110   UBFM            = 0x40000000 | SBFM,
 111   /* CSINC          s001 1010 100r rrrr cccc 01rr rrrr rrrr */
 112   CSINC           = 0x9a800400,
 113   /* MUL            s001 1011 000r rrrr 0111 11rr rrrr rrrr */
 114   MUL             = 0x1b007c00,
 115   /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
 116   /* MRS            1101 0101 0011 oooo oooo oooo ooor rrrr */
 117   MSR             = 0xd5100000,
 118   MRS             = 0x00200000 | MSR,
 119   /* HINT           1101 0101 0000 0011 0010 oooo ooo1 1111 */
 120   HINT            = 0xd503201f,
 121   SEVL            = (5 << 5) | HINT,
 122   WFE             = (2 << 5) | HINT,
 123   NOP             = (0 << 5) | HINT,
 124 };
 125
 126 /* Representation of a general purpose register of the form xN or wN.
 127
 128    This type is used by emitting functions that take registers as operands.  */
 129
 130 struct aarch64_register
 131 {
 132   unsigned num;
 133   int is64;
 134 };
 135
 136 enum aarch64_memory_operand_type
 137 {
 138   MEMORY_OPERAND_OFFSET,
 139   MEMORY_OPERAND_PREINDEX,
 140   MEMORY_OPERAND_POSTINDEX,
 141 };
 142
 143 /* Representation of a memory operand, used for load and store
 144    instructions.
 145
 146    The types correspond to the following variants:
 147
 148    MEMORY_OPERAND_OFFSET:    LDR rt, [rn, #offset]
 149    MEMORY_OPERAND_PREINDEX:  LDR rt, [rn, #index]!
 150    MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index  */
 151
 152 struct aarch64_memory_operand
 153 {
 154   /* Type of the operand.  */
 155   enum aarch64_memory_operand_type type;
 156
 157   /* Index from the base register.  */
 158   int32_t index;
 159 };
 160
 161 /* Helper macro to mask and shift a value into a bitfield.  */
 162
 163 #define ENCODE(val, size, offset) \
 164   ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
 165
 166 int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
 167                         unsigned *rd, int32_t *offset);
 168
 169 int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
 170                       int32_t *offset);
 171
 172 int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
 173                           int32_t *offset);
 174
 175 int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
 176                        int *is_cbnz, unsigned *rn, int32_t *offset);
 177
 178 int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
 179                        unsigned *bit, unsigned *rt, int32_t *imm);
 180
 181 int aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
 182                                 int *is64, unsigned *rt, int32_t *offset);
 183
 184 /* Data passed to each method of aarch64_insn_visitor.  */
 185
 186 struct aarch64_insn_data
 187 {
 188   /* The instruction address.  */
 189   CORE_ADDR insn_addr;
 190 };
 191
 192 /* Visit different instructions by different methods.  */
 193
 194 struct aarch64_insn_visitor
 195 {
 196   /* Visit instruction B/BL OFFSET.  */
 197   void (*b) (const int is_bl, const int32_t offset,
 198              struct aarch64_insn_data *data);
 199
 200   /* Visit instruction B.COND OFFSET.  */
 201   void (*b_cond) (const unsigned cond, const int32_t offset,
 202                   struct aarch64_insn_data *data);
 203
 204   /* Visit instruction CBZ/CBNZ Rn, OFFSET.  */
 205   void (*cb) (const int32_t offset, const int is_cbnz,
 206               const unsigned rn, int is64,
 207               struct aarch64_insn_data *data);
 208
 209   /* Visit instruction TBZ/TBNZ Rt, #BIT, OFFSET.  */
 210   void (*tb) (const int32_t offset, int is_tbnz,
 211               const unsigned rt, unsigned bit,
 212               struct aarch64_insn_data *data);
 213
 214   /* Visit instruction ADR/ADRP Rd, OFFSET.  */
 215   void (*adr) (const int32_t offset, const unsigned rd,
 216                const int is_adrp, struct aarch64_insn_data *data);
 217
 218   /* Visit instruction LDR/LDRSW Rt, OFFSET.  */
 219   void (*ldr_literal) (const int32_t offset, const int is_sw,
 220                        const unsigned rt, const int is64,
 221                        struct aarch64_insn_data *data);
 222
 223   /* Visit instruction INSN of other kinds.  */
 224   void (*others) (const uint32_t insn, struct aarch64_insn_data *data);
 225 };
 226
 227 void aarch64_relocate_instruction (uint32_t insn,
 228                                    const struct aarch64_insn_visitor *visitor,
 229                                    struct aarch64_insn_data *data);
 230
 231 #define can_encode_int32(val, bits)                     \
 232   (((val) >> (bits)) == 0 || ((val) >> (bits)) == -1)
 233
 234 /* Write a B or BL instruction into *BUF.
 235
 236      B  #offset
 237      BL #offset
 238
 239    IS_BL specifies if the link register should be updated.
 240    OFFSET is the immediate offset from the current PC.  It is
 241    byte-addressed but should be 4 bytes aligned.  It has a limited range of
 242    +/- 128MB (26 bits << 2).  */
 243
 244 #define emit_b(buf, is_bl, offset) \
 245   aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0)))
 246
 247 /* Write a BCOND instruction into *BUF.
 248
 249      B.COND #offset
 250
 251    COND specifies the condition field.
 252    OFFSET is the immediate offset from the current PC.  It is
 253    byte-addressed but should be 4 bytes aligned.  It has a limited range of
 254    +/- 1MB (19 bits << 2).  */
 255
 256 #define emit_bcond(buf, cond, offset)                           \
 257   aarch64_emit_insn (buf,                                       \
 258                      BCOND | ENCODE ((offset) >> 2, 19, 5)      \
 259                      | ENCODE ((cond), 4, 0))
 260
 261 /* Write a CBZ or CBNZ instruction into *BUF.
 262
 263      CBZ  rt, #offset
 264      CBNZ rt, #offset
 265
 266    IS_CBNZ distinguishes between CBZ and CBNZ instructions.
 267    RN is the register to test.
 268    OFFSET is the immediate offset from the current PC.  It is
 269    byte-addressed but should be 4 bytes aligned.  It has a limited range of
 270    +/- 1MB (19 bits << 2).  */
 271
 272 #define emit_cb(buf, is_cbnz, rt, offset)                       \
 273   aarch64_emit_insn (buf,                                       \
 274                      ((is_cbnz) ? CBNZ : CBZ)                   \
 275                      | ENCODE (rt.is64, 1, 31)  /* sf */        \
 276                      | ENCODE (offset >> 2, 19, 5) /* imm19 */  \
 277                      | ENCODE (rt.num, 5, 0))
 278
 279 /* Write a LDR instruction into *BUF.
 280
 281      LDR rt, [rn, #offset]
 282      LDR rt, [rn, #index]!
 283      LDR rt, [rn], #index
 284
 285    RT is the register to store.
 286    RN is the base address register.
 287    OFFSET is the immediate to add to the base address.  It is limited to
 288    0 .. 32760 range (12 bits << 3).  */
 289
 290 #define emit_ldr(buf, rt, rn, operand) \
 291   aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
 292
 293 /* Write a LDRSW instruction into *BUF.  The register size is 64-bit.
 294
 295      LDRSW xt, [rn, #offset]
 296      LDRSW xt, [rn, #index]!
 297      LDRSW xt, [rn], #index
 298
 299    RT is the register to store.
 300    RN is the base address register.
 301    OFFSET is the immediate to add to the base address.  It is limited to
 302    0 .. 16380 range (12 bits << 2).  */
 303
 304 #define emit_ldrsw(buf, rt, rn, operand)                \
 305   aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)
 306
 307
 308 /* Write a TBZ or TBNZ instruction into *BUF.
 309
 310    TBZ  rt, #bit, #offset
 311    TBNZ rt, #bit, #offset
 312
 313    IS_TBNZ distinguishes between TBZ and TBNZ instructions.
 314    RT is the register to test.
 315    BIT is the index of the bit to test in register RT.
 316    OFFSET is the immediate offset from the current PC.  It is
 317    byte-addressed but should be 4 bytes aligned.  It has a limited range of
 318    +/- 32KB (14 bits << 2).  */
 319
 320 #define emit_tb(buf, is_tbnz, bit, rt, offset)                 \
 321   aarch64_emit_insn (buf,                                      \
 322                      ((is_tbnz) ? TBNZ: TBZ)                   \
 323                      | ENCODE (bit >> 5, 1, 31) /* b5 */       \
 324                      | ENCODE (bit, 5, 19) /* b40 */           \
 325                      | ENCODE (offset >> 2, 14, 5) /* imm14 */ \
 326                      | ENCODE (rt.num, 5, 0))
 327
 328 /* Write a NOP instruction into *BUF.  */
 329
 330 #define emit_nop(buf) aarch64_emit_insn (buf, NOP)
 331
 332 int aarch64_emit_insn (uint32_t *buf, uint32_t insn);
 333
 334 int aarch64_emit_load_store (uint32_t *buf, uint32_t size,
 335                              enum aarch64_opcodes opcode,
 336                              struct aarch64_register rt,
 337                              struct aarch64_register rn,
 338                              struct aarch64_memory_operand operand);
 339
 340 #endif /* ARCH_AARCH64_INSN_H */