1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 #include "solib-svr4.h"
37 /* Each OS has a different mechanism for accessing the various
38 registers stored in the sigcontext structure.
40 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
41 function pointer) which may be used to determine the addresses
42 of the various saved registers in the sigcontext structure.
44 For the ARM target, there are three parameters to this function.
45 The first is the pc value of the frame under consideration, the
46 second the stack pointer of this frame, and the last is the
47 register number to fetch.
49 If the tm.h file does not define this macro, then it's assumed that
50 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
53 When it comes time to multi-arching this code, see the identically
54 named machinery in ia64-tdep.c for an example of how it could be
55 done. It should not be necessary to modify the code below where
56 this macro is used. */
58 #ifdef SIGCONTEXT_REGISTER_ADDRESS
59 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
60 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
63 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
64 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
67 extern void _initialize_arm_tdep (void);
69 /* Number of different reg name sets (options). */
70 static int num_flavor_options
;
72 /* We have more registers than the disassembler as gdb can print the value
73 of special registers as well.
74 The general register names are overwritten by whatever is being used by
75 the disassembler at the moment. We also adjust the case of cpsr and fps. */
77 /* Initial value: Register names used in ARM's ISA documentation. */
78 static char * arm_register_name_strings
[] =
79 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
80 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
81 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
82 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
83 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
84 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
85 "fps", "cpsr" }; /* 24 25 */
86 static char **arm_register_names
= arm_register_name_strings
;
88 /* Valid register name flavors. */
89 static const char **valid_flavors
;
91 /* Disassembly flavor to use. Default to "std" register names. */
92 static const char *disassembly_flavor
;
93 static int current_option
; /* Index to that option in the opcodes table. */
95 /* This is used to keep the bfd arch_info in sync with the disassembly
97 static void set_disassembly_flavor_sfunc(char *, int,
98 struct cmd_list_element
*);
99 static void set_disassembly_flavor (void);
101 static void convert_from_extended (void *ptr
, void *dbl
);
103 /* Define other aspects of the stack frame. We keep the offsets of
104 all saved registers, 'cause we need 'em a lot! We also keep the
105 current size of the stack frame, and the offset of the frame
106 pointer from the stack pointer (for frameless functions, and when
107 we're still in the prologue of a function with a frame) */
109 struct frame_extra_info
116 /* Addresses for calling Thumb functions have the bit 0 set.
117 Here are some macros to test, set, or clear bit 0 of addresses. */
118 #define IS_THUMB_ADDR(addr) ((addr) & 1)
119 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
120 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
122 /* Will a function return an aggregate type in memory or in a
123 register? Return 0 if an aggregate type can be returned in a
124 register, 1 if it must be returned in memory. */
127 arm_use_struct_convention (int gcc_p
, struct type
*type
)
130 register enum type_code code
;
132 /* In the ARM ABI, "integer" like aggregate types are returned in
133 registers. For an aggregate type to be integer like, its size
134 must be less than or equal to REGISTER_SIZE and the offset of
135 each addressable subfield must be zero. Note that bit fields are
136 not addressable, and all addressable subfields of unions always
137 start at offset zero.
139 This function is based on the behaviour of GCC 2.95.1.
140 See: gcc/arm.c: arm_return_in_memory() for details.
142 Note: All versions of GCC before GCC 2.95.2 do not set up the
143 parameters correctly for a function returning the following
144 structure: struct { float f;}; This should be returned in memory,
145 not a register. Richard Earnshaw sent me a patch, but I do not
146 know of any way to detect if a function like the above has been
147 compiled with the correct calling convention. */
149 /* All aggregate types that won't fit in a register must be returned
151 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
156 /* The only aggregate types that can be returned in a register are
157 structs and unions. Arrays must be returned in memory. */
158 code
= TYPE_CODE (type
);
159 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
164 /* Assume all other aggregate types can be returned in a register.
165 Run a check for structures, unions and arrays. */
168 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
171 /* Need to check if this struct/union is "integer" like. For
172 this to be true, its size must be less than or equal to
173 REGISTER_SIZE and the offset of each addressable subfield
174 must be zero. Note that bit fields are not addressable, and
175 unions always start at offset zero. If any of the subfields
176 is a floating point type, the struct/union cannot be an
179 /* For each field in the object, check:
180 1) Is it FP? --> yes, nRc = 1;
181 2) Is it addressable (bitpos != 0) and
182 not packed (bitsize == 0)?
186 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
188 enum type_code field_type_code
;
189 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
191 /* Is it a floating point type field? */
192 if (field_type_code
== TYPE_CODE_FLT
)
198 /* If bitpos != 0, then we have to care about it. */
199 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
201 /* Bitfields are not addressable. If the field bitsize is
202 zero, then the field is not packed. Hence it cannot be
203 a bitfield or any other packed type. */
204 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
217 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
219 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
222 /* Set to true if the 32-bit mode is in use. */
226 /* Flag set by arm_fix_call_dummy that tells whether the target
227 function is a Thumb function. This flag is checked by
228 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
229 its use in valops.c) to pass the function address as an additional
232 static int target_is_thumb
;
234 /* Flag set by arm_fix_call_dummy that tells whether the calling
235 function is a Thumb function. This flag is checked by
236 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
238 static int caller_is_thumb
;
240 /* Determine if the program counter specified in MEMADDR is in a Thumb
244 arm_pc_is_thumb (CORE_ADDR memaddr
)
246 struct minimal_symbol
*sym
;
248 /* If bit 0 of the address is set, assume this is a Thumb address. */
249 if (IS_THUMB_ADDR (memaddr
))
252 /* Thumb functions have a "special" bit set in minimal symbols. */
253 sym
= lookup_minimal_symbol_by_pc (memaddr
);
256 return (MSYMBOL_IS_SPECIAL (sym
));
264 /* Determine if the program counter specified in MEMADDR is in a call
265 dummy being called from a Thumb function. */
268 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
270 CORE_ADDR sp
= read_sp ();
272 /* FIXME: Until we switch for the new call dummy macros, this heuristic
273 is the best we can do. We are trying to determine if the pc is on
274 the stack, which (hopefully) will only happen in a call dummy.
275 We hope the current stack pointer is not so far alway from the dummy
276 frame location (true if we have not pushed large data structures or
277 gone too many levels deep) and that our 1024 is not enough to consider
278 code regions as part of the stack (true for most practical purposes) */
279 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
280 return caller_is_thumb
;
285 /* Remove useless bits from addresses in a running program. */
287 arm_addr_bits_remove (CORE_ADDR val
)
289 if (arm_pc_is_thumb (val
))
290 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
292 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
295 /* When reading symbols, we need to zap the low bit of the address,
296 which may be set to 1 for Thumb functions. */
298 arm_smash_text_address (CORE_ADDR val
)
304 arm_saved_pc_after_call (struct frame_info
*frame
)
306 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
309 /* Determine whether the function invocation represented by FI has a
310 frame on the stack associated with it. If it does return zero,
311 otherwise return 1. */
314 arm_frameless_function_invocation (struct frame_info
*fi
)
316 CORE_ADDR func_start
, after_prologue
;
319 /* Sometimes we have functions that do a little setup (like saving the
320 vN registers with the stmdb instruction, but DO NOT set up a frame.
321 The symbol table will report this as a prologue. However, it is
322 important not to try to parse these partial frames as frames, or we
323 will get really confused.
325 So I will demand 3 instructions between the start & end of the
326 prologue before I call it a real prologue, i.e. at least
331 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
332 after_prologue
= SKIP_PROLOGUE (func_start
);
334 /* There are some frameless functions whose first two instructions
335 follow the standard APCS form, in which case after_prologue will
336 be func_start + 8. */
338 frameless
= (after_prologue
< func_start
+ 12);
342 /* The address of the arguments in the frame. */
344 arm_frame_args_address (struct frame_info
*fi
)
349 /* The address of the local variables in the frame. */
351 arm_frame_locals_address (struct frame_info
*fi
)
356 /* The number of arguments being passed in the frame. */
358 arm_frame_num_args (struct frame_info
*fi
)
360 /* We have no way of knowing. */
364 /* A typical Thumb prologue looks like this:
368 Sometimes the latter instruction may be replaced by:
376 or, on tpcs, like this:
383 There is always one instruction of three classes:
388 When we have found at least one of each class we are done with the prolog.
389 Note that the "sub sp, #NN" before the push does not count.
393 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
395 CORE_ADDR current_pc
;
396 int findmask
= 0; /* findmask:
397 bit 0 - push { rlist }
398 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
399 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
402 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
404 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
406 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
408 findmask
|= 1; /* push found */
410 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
412 if ((findmask
& 1) == 0) /* before push ? */
415 findmask
|= 4; /* add/sub sp found */
417 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
419 findmask
|= 2; /* setting of r7 found */
421 else if (insn
== 0x466f) /* mov r7, sp */
423 findmask
|= 2; /* setting of r7 found */
425 else if (findmask
== (4+2+1))
427 break; /* We have found one of each type of prologue instruction */
430 continue; /* something in the prolog that we don't care about or some
431 instruction from outside the prolog scheduled here for optimization */
437 /* The APCS (ARM Procedure Call Standard) defines the following
441 [stmfd sp!, {a1,a2,a3,a4}]
442 stmfd sp!, {...,fp,ip,lr,pc}
443 [stfe f7, [sp, #-12]!]
444 [stfe f6, [sp, #-12]!]
445 [stfe f5, [sp, #-12]!]
446 [stfe f4, [sp, #-12]!]
447 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
450 arm_skip_prologue (CORE_ADDR pc
)
454 CORE_ADDR func_addr
, func_end
;
456 struct symtab_and_line sal
;
458 /* See what the symbol table says. */
460 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
464 /* Found a function. */
465 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
466 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
468 /* Don't use this trick for assembly source files. */
469 sal
= find_pc_line (func_addr
, 0);
470 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
475 /* Check if this is Thumb code. */
476 if (arm_pc_is_thumb (pc
))
477 return thumb_skip_prologue (pc
, func_end
);
479 /* Can't find the prologue end in the symbol table, try it the hard way
480 by disassembling the instructions. */
482 inst
= read_memory_integer (skip_pc
, 4);
483 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
487 inst
= read_memory_integer (skip_pc
, 4);
488 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
491 inst
= read_memory_integer (skip_pc
, 4);
494 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
498 inst
= read_memory_integer (skip_pc
, 4);
500 /* Any insns after this point may float into the code, if it makes
501 for better instruction scheduling, so we skip them only if we
502 find them, but still consdier the function to be frame-ful. */
504 /* We may have either one sfmfd instruction here, or several stfe
505 insns, depending on the version of floating point code we
507 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
510 inst
= read_memory_integer (skip_pc
, 4);
514 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
517 inst
= read_memory_integer (skip_pc
, 4);
521 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
527 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
528 This function decodes a Thumb function prologue to determine:
529 1) the size of the stack frame
530 2) which registers are saved on it
531 3) the offsets of saved regs
532 4) the offset from the stack pointer to the frame pointer
533 This information is stored in the "extra" fields of the frame_info.
535 A typical Thumb function prologue would create this stack frame
536 (offsets relative to FP)
537 old SP -> 24 stack parameters
540 R7 -> 0 local variables (16 bytes)
541 SP -> -12 additional stack space (12 bytes)
542 The frame size would thus be 36 bytes, and the frame offset would be
543 12 bytes. The frame register is R7.
545 The comments for thumb_skip_prolog() describe the algorithm we use to detect
546 the end of the prolog */
550 thumb_scan_prologue (struct frame_info
*fi
)
552 CORE_ADDR prologue_start
;
553 CORE_ADDR prologue_end
;
554 CORE_ADDR current_pc
;
555 int saved_reg
[16]; /* which register has been copied to register n? */
556 int findmask
= 0; /* findmask:
557 bit 0 - push { rlist }
558 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
559 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
563 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
565 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
567 if (sal
.line
== 0) /* no line info, use current PC */
568 prologue_end
= fi
->pc
;
569 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
570 prologue_end
= sal
.end
; /* (probably means no prologue) */
573 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
574 /* 16 pushes, an add, and "mv fp,sp" */
576 prologue_end
= min (prologue_end
, fi
->pc
);
578 /* Initialize the saved register map. When register H is copied to
579 register L, we will put H in saved_reg[L]. */
580 for (i
= 0; i
< 16; i
++)
583 /* Search the prologue looking for instructions that set up the
584 frame pointer, adjust the stack pointer, and save registers.
585 Do this until all basic prolog instructions are found. */
587 fi
->extra_info
->framesize
= 0;
588 for (current_pc
= prologue_start
;
589 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
596 insn
= read_memory_unsigned_integer (current_pc
, 2);
598 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
601 findmask
|= 1; /* push found */
602 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
603 whether to save LR (R14). */
604 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
606 /* Calculate offsets of saved R0-R7 and LR. */
607 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
608 if (mask
& (1 << regno
))
610 fi
->extra_info
->framesize
+= 4;
611 fi
->saved_regs
[saved_reg
[regno
]] =
612 -(fi
->extra_info
->framesize
);
613 saved_reg
[regno
] = regno
; /* reset saved register map */
616 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
618 if ((findmask
& 1) == 0) /* before push ? */
621 findmask
|= 4; /* add/sub sp found */
623 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
624 if (insn
& 0x80) /* is it signed? (==subtracting) */
626 fi
->extra_info
->frameoffset
+= offset
;
629 fi
->extra_info
->framesize
-= offset
;
631 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
633 findmask
|= 2; /* setting of r7 found */
634 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
635 /* get scaled offset */
636 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
638 else if (insn
== 0x466f) /* mov r7, sp */
640 findmask
|= 2; /* setting of r7 found */
641 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
642 fi
->extra_info
->frameoffset
= 0;
643 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
645 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
647 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
648 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
649 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
652 continue; /* something in the prolog that we don't care about or some
653 instruction from outside the prolog scheduled here for optimization */
657 /* Check if prologue for this frame's PC has already been scanned. If
658 it has, copy the relevant information about that prologue and
659 return non-zero. Otherwise do not copy anything and return zero.
661 The information saved in the cache includes:
662 * the frame register number;
663 * the size of the stack frame;
664 * the offsets of saved regs (relative to the old SP); and
665 * the offset from the stack pointer to the frame pointer
667 The cache contains only one entry, since this is adequate for the
668 typical sequence of prologue scan requests we get. When performing
669 a backtrace, GDB will usually ask to scan the same function twice
670 in a row (once to get the frame chain, and once to fill in the
671 extra frame information). */
673 static struct frame_info prologue_cache
;
676 check_prologue_cache (struct frame_info
*fi
)
680 if (fi
->pc
== prologue_cache
.pc
)
682 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
683 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
684 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
685 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
686 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
694 /* Copy the prologue information from fi to the prologue cache. */
697 save_prologue_cache (struct frame_info
*fi
)
701 prologue_cache
.pc
= fi
->pc
;
702 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
703 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
704 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
706 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
707 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
711 /* This function decodes an ARM function prologue to determine:
712 1) the size of the stack frame
713 2) which registers are saved on it
714 3) the offsets of saved regs
715 4) the offset from the stack pointer to the frame pointer
716 This information is stored in the "extra" fields of the frame_info.
718 There are two basic forms for the ARM prologue. The fixed argument
719 function call will look like:
722 stmfd sp!, {fp, ip, lr, pc}
726 Which would create this stack frame (offsets relative to FP):
727 IP -> 4 (caller's stack)
728 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
729 -4 LR (return address in caller)
730 -8 IP (copy of caller's SP)
732 SP -> -28 Local variables
734 The frame size would thus be 32 bytes, and the frame offset would be
735 28 bytes. The stmfd call can also save any of the vN registers it
736 plans to use, which increases the frame size accordingly.
738 Note: The stored PC is 8 off of the STMFD instruction that stored it
739 because the ARM Store instructions always store PC + 8 when you read
742 A variable argument function call will look like:
745 stmfd sp!, {a1, a2, a3, a4}
746 stmfd sp!, {fp, ip, lr, pc}
749 Which would create this stack frame (offsets relative to FP):
750 IP -> 20 (caller's stack)
755 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
756 -4 LR (return address in caller)
757 -8 IP (copy of caller's SP)
759 SP -> -28 Local variables
761 The frame size would thus be 48 bytes, and the frame offset would be
764 There is another potential complication, which is that the optimizer
765 will try to separate the store of fp in the "stmfd" instruction from
766 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
767 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
769 Also, note, the original version of the ARM toolchain claimed that there
772 instruction at the end of the prologue. I have never seen GCC produce
773 this, and the ARM docs don't mention it. We still test for it below in
779 arm_scan_prologue (struct frame_info
*fi
)
781 int regno
, sp_offset
, fp_offset
;
782 LONGEST return_value
;
783 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
785 /* Check if this function is already in the cache of frame information. */
786 if (check_prologue_cache (fi
))
789 /* Assume there is no frame until proven otherwise. */
790 fi
->extra_info
->framereg
= SP_REGNUM
;
791 fi
->extra_info
->framesize
= 0;
792 fi
->extra_info
->frameoffset
= 0;
794 /* Check for Thumb prologue. */
795 if (arm_pc_is_thumb (fi
->pc
))
797 thumb_scan_prologue (fi
);
798 save_prologue_cache (fi
);
802 /* Find the function prologue. If we can't find the function in
803 the symbol table, peek in the stack frame to find the PC. */
804 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
806 /* One way to find the end of the prologue (which works well
807 for unoptimized code) is to do the following:
809 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
812 prologue_end = fi->pc;
813 else if (sal.end < prologue_end)
814 prologue_end = sal.end;
816 This mechanism is very accurate so long as the optimizer
817 doesn't move any instructions from the function body into the
818 prologue. If this happens, sal.end will be the last
819 instruction in the first hunk of prologue code just before
820 the first instruction that the scheduler has moved from
821 the body to the prologue.
823 In order to make sure that we scan all of the prologue
824 instructions, we use a slightly less accurate mechanism which
825 may scan more than necessary. To help compensate for this
826 lack of accuracy, the prologue scanning loop below contains
827 several clauses which'll cause the loop to terminate early if
828 an implausible prologue instruction is encountered.
834 is a suitable endpoint since it accounts for the largest
835 possible prologue plus up to five instructions inserted by
838 if (prologue_end
> prologue_start
+ 64)
840 prologue_end
= prologue_start
+ 64; /* See above. */
845 /* Get address of the stmfd in the prologue of the callee; the saved
846 PC is the address of the stmfd + 8. */
847 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
851 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
852 prologue_end
= prologue_start
+ 64; /* See above. */
856 /* Now search the prologue looking for instructions that set up the
857 frame pointer, adjust the stack pointer, and save registers.
859 Be careful, however, and if it doesn't look like a prologue,
860 don't try to scan it. If, for instance, a frameless function
861 begins with stmfd sp!, then we will tell ourselves there is
862 a frame, which will confuse stack traceback, as well ad"finish"
863 and other operations that rely on a knowledge of the stack
866 In the APCS, the prologue should start with "mov ip, sp" so
867 if we don't see this as the first insn, we will stop. [Note:
868 This doesn't seem to be true any longer, so it's now an optional
869 part of the prologue. - Kevin Buettner, 2001-11-20] */
871 sp_offset
= fp_offset
= 0;
873 if (read_memory_unsigned_integer (prologue_start
, 4)
874 == 0xe1a0c00d) /* mov ip, sp */
875 current_pc
= prologue_start
+ 4;
877 current_pc
= prologue_start
;
879 for (; current_pc
< prologue_end
; current_pc
+= 4)
881 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
883 if ((insn
& 0xffff0000) == 0xe92d0000)
884 /* stmfd sp!, {..., fp, ip, lr, pc}
886 stmfd sp!, {a1, a2, a3, a4} */
888 int mask
= insn
& 0xffff;
890 /* Calculate offsets of saved registers. */
891 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
892 if (mask
& (1 << regno
))
895 fi
->saved_regs
[regno
] = sp_offset
;
898 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
900 unsigned imm
= insn
& 0xff; /* immediate value */
901 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
902 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
904 fi
->extra_info
->framereg
= FP_REGNUM
;
906 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
908 unsigned imm
= insn
& 0xff; /* immediate value */
909 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
910 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
913 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
916 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
917 fi
->saved_regs
[regno
] = sp_offset
;
919 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
922 unsigned int fp_start_reg
, fp_bound_reg
;
924 if ((insn
& 0x800) == 0x800) /* N0 is set */
926 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
933 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
939 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
940 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
941 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
944 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
947 else if ((insn
& 0xf0000000) != 0xe0000000)
948 break; /* Condition not true, exit early */
949 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
950 break; /* Don't scan past a block load */
952 /* The optimizer might shove anything into the prologue,
953 so we just skip what we don't recognize. */
957 /* The frame size is just the negative of the offset (from the original SP)
958 of the last thing thing we pushed on the stack. The frame offset is
959 [new FP] - [new SP]. */
960 fi
->extra_info
->framesize
= -sp_offset
;
961 if (fi
->extra_info
->framereg
== FP_REGNUM
)
962 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
964 fi
->extra_info
->frameoffset
= 0;
966 save_prologue_cache (fi
);
969 /* Find REGNUM on the stack. Otherwise, it's in an active register.
970 One thing we might want to do here is to check REGNUM against the
971 clobber mask, and somehow flag it as invalid if it isn't saved on
972 the stack somewhere. This would provide a graceful failure mode
973 when trying to get the value of caller-saves registers for an inner
977 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
979 for (; fi
; fi
= fi
->next
)
981 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
982 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
983 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
986 if (fi
->saved_regs
[regnum
] != 0)
987 return read_memory_integer (fi
->saved_regs
[regnum
],
988 REGISTER_RAW_SIZE (regnum
));
989 return read_register (regnum
);
992 /* Function: frame_chain
993 Given a GDB frame, determine the address of the calling function's frame.
994 This will be used to create a new GDB frame struct, and then
995 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
996 For ARM, we save the frame size when we initialize the frame_info.
998 The original definition of this function was a macro in tm-arm.h:
999 { In the case of the ARM, the frame's nominal address is the FP value,
1000 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
1002 #define FRAME_CHAIN(thisframe) \
1003 ((thisframe)->pc >= LOWEST_PC ? \
1004 read_memory_integer ((thisframe)->frame - 12, 4) :\
1010 arm_frame_chain (struct frame_info
*fi
)
1012 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1013 CORE_ADDR fn_start
, callers_pc
, fp
;
1015 /* is this a dummy frame? */
1016 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1017 return fi
->frame
; /* dummy frame same as caller's frame */
1019 /* is caller-of-this a dummy frame? */
1020 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
1021 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
1022 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
1023 return fp
; /* dummy frame's frame may bear no relation to ours */
1025 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
1026 if (fn_start
== entry_point_address ())
1027 return 0; /* in _start fn, don't chain further */
1029 CORE_ADDR caller_pc
, fn_start
;
1030 int framereg
= fi
->extra_info
->framereg
;
1032 if (fi
->pc
< LOWEST_PC
)
1035 /* If the caller is the startup code, we're at the end of the chain. */
1036 caller_pc
= FRAME_SAVED_PC (fi
);
1037 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
1038 if (fn_start
== entry_point_address ())
1041 /* If the caller is Thumb and the caller is ARM, or vice versa,
1042 the frame register of the caller is different from ours.
1043 So we must scan the prologue of the caller to determine its
1044 frame register number. */
1045 /* XXX Fixme, we should try to do this without creating a temporary
1047 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1049 struct frame_info caller_fi
;
1050 struct cleanup
*old_chain
;
1052 /* Create a temporary frame suitable for scanning the caller's
1054 memset (&caller_fi
, 0, sizeof (caller_fi
));
1055 caller_fi
.extra_info
= (struct frame_extra_info
*)
1056 xcalloc (1, sizeof (struct frame_extra_info
));
1057 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1058 caller_fi
.saved_regs
= (CORE_ADDR
*)
1059 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1060 make_cleanup (xfree
, caller_fi
.saved_regs
);
1062 /* Now, scan the prologue and obtain the frame register. */
1063 caller_fi
.pc
= caller_pc
;
1064 arm_scan_prologue (&caller_fi
);
1065 framereg
= caller_fi
.extra_info
->framereg
;
1067 /* Deallocate the storage associated with the temporary frame
1069 do_cleanups (old_chain
);
1072 /* If the caller used a frame register, return its value.
1073 Otherwise, return the caller's stack pointer. */
1074 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1075 return arm_find_callers_reg (fi
, framereg
);
1077 return fi
->frame
+ fi
->extra_info
->framesize
;
1080 /* This function actually figures out the frame address for a given pc
1081 and sp. This is tricky because we sometimes don't use an explicit
1082 frame pointer, and the previous stack pointer isn't necessarily
1083 recorded on the stack. The only reliable way to get this info is
1084 to examine the prologue. FROMLEAF is a little confusing, it means
1085 this is the next frame up the chain AFTER a frameless function. If
1086 this is true, then the frame value for this frame is still in the
1090 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1095 if (fi
->saved_regs
== NULL
)
1096 frame_saved_regs_zalloc (fi
);
1098 fi
->extra_info
= (struct frame_extra_info
*)
1099 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1101 fi
->extra_info
->framesize
= 0;
1102 fi
->extra_info
->frameoffset
= 0;
1103 fi
->extra_info
->framereg
= 0;
1106 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1108 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1110 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1111 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1113 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1114 by assuming it's always FP. */
1115 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1116 fi
->extra_info
->framesize
= 0;
1117 fi
->extra_info
->frameoffset
= 0;
1123 /* Compute stack pointer for this frame. We use this value for both the
1124 sigtramp and call dummy cases. */
1128 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1129 + fi
->next
->extra_info
->framesize
);
1131 /* Determine whether or not we're in a sigtramp frame.
1132 Unfortunately, it isn't sufficient to test
1133 fi->signal_handler_caller because this value is sometimes set
1134 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1135 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1136 to use the sigcontext addresses for the saved registers.
1138 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1139 the name of the function, the code below will have to be changed
1140 to first fetch the name of the function and then pass this name
1143 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1144 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, (char *)0)))
1146 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1147 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1149 /* FIXME: What about thumb mode? */
1150 fi
->extra_info
->framereg
= SP_REGNUM
;
1152 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1153 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1154 fi
->extra_info
->framesize
= 0;
1155 fi
->extra_info
->frameoffset
= 0;
1158 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1161 CORE_ADDR callers_sp
;
1163 /* Set rp point at the high end of the saved registers. */
1164 rp
= fi
->frame
- REGISTER_SIZE
;
1166 /* Fill in addresses of saved registers. */
1167 fi
->saved_regs
[PS_REGNUM
] = rp
;
1168 rp
-= REGISTER_RAW_SIZE (PS_REGNUM
);
1169 for (reg
= PC_REGNUM
; reg
>= 0; reg
--)
1171 fi
->saved_regs
[reg
] = rp
;
1172 rp
-= REGISTER_RAW_SIZE (reg
);
1175 callers_sp
= read_memory_integer (fi
->saved_regs
[SP_REGNUM
],
1176 REGISTER_RAW_SIZE (SP_REGNUM
));
1177 fi
->extra_info
->framereg
= FP_REGNUM
;
1178 fi
->extra_info
->framesize
= callers_sp
- sp
;
1179 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1183 arm_scan_prologue (fi
);
1186 /* this is the innermost frame? */
1187 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1188 else if (fi
->extra_info
->framereg
== FP_REGNUM
1189 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1191 /* not the innermost frame */
1192 /* If we have an FP, the callee saved it. */
1193 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1195 read_memory_integer (fi
->next
1196 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1198 /* If we were called by a frameless fn. then our frame is
1199 still in the frame pointer register on the board... */
1200 fi
->frame
= read_fp ();
1203 /* Calculate actual addresses of saved registers using offsets
1204 determined by arm_scan_prologue. */
1205 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1206 if (fi
->saved_regs
[reg
] != 0)
1207 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1208 - fi
->extra_info
->frameoffset
);
1213 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1214 is saved in the stack anywhere, otherwise we get it from the
1217 The old definition of this function was a macro:
1218 #define FRAME_SAVED_PC(FRAME) \
1219 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1222 arm_frame_saved_pc (struct frame_info
*fi
)
1224 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1225 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1226 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1229 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1232 return read_memory_integer (fi
->saved_regs
[PC_REGNUM
],
1233 REGISTER_RAW_SIZE (PC_REGNUM
));
1237 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1238 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1242 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1243 Examine the Program Status Register to decide which state we're in. */
1246 arm_target_read_fp (void)
1248 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1249 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1251 return read_register (FP_REGNUM
); /* R11 if ARM */
1254 /* Calculate the frame offsets of the saved registers (ARM version). */
1257 arm_frame_init_saved_regs (struct frame_info
*fip
)
1260 if (fip
->saved_regs
)
1263 arm_init_extra_frame_info (0, fip
);
1267 arm_push_dummy_frame (void)
1269 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1270 CORE_ADDR sp
= old_sp
;
1271 CORE_ADDR fp
, prologue_start
;
1274 /* Push the two dummy prologue instructions in reverse order,
1275 so that they'll be in the correct low-to-high order in memory. */
1276 /* sub fp, ip, #4 */
1277 sp
= push_word (sp
, 0xe24cb004);
1278 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1279 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1281 /* Push a pointer to the dummy prologue + 12, because when stm
1282 instruction stores the PC, it stores the address of the stm
1283 instruction itself plus 12. */
1284 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1286 /* Push the processor status. */
1287 sp
= push_word (sp
, read_register (PS_REGNUM
));
1289 /* Push all 16 registers starting with r15. */
1290 for (regnum
= PC_REGNUM
; regnum
>= 0; regnum
--)
1291 sp
= push_word (sp
, read_register (regnum
));
1293 /* Update fp (for both Thumb and ARM) and sp. */
1294 write_register (FP_REGNUM
, fp
);
1295 write_register (THUMB_FP_REGNUM
, fp
);
1296 write_register (SP_REGNUM
, sp
);
1299 /* CALL_DUMMY_WORDS:
1300 This sequence of words is the instructions
1306 Note this is 12 bytes. */
1308 LONGEST arm_call_dummy_words
[] =
1310 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1313 /* Fix up the call dummy, based on whether the processor is currently
1314 in Thumb or ARM mode, and whether the target function is Thumb or
1315 ARM. There are three different situations requiring three
1318 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1319 been copied into the dummy parameter to this function.
1320 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1321 "mov pc,r4" instruction patched to be a "bx r4" instead.
1322 * Thumb calling anything: uses the Thumb dummy defined below, which
1323 works for calling both ARM and Thumb functions.
1325 All three call dummies expect to receive the target function
1326 address in R4, with the low bit set if it's a Thumb function. */
1329 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1330 struct value
**args
, struct type
*type
, int gcc_p
)
1332 static short thumb_dummy
[4] =
1334 0xf000, 0xf801, /* bl label */
1335 0xdf18, /* swi 24 */
1336 0x4720, /* label: bx r4 */
1338 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1340 /* Set flag indicating whether the current PC is in a Thumb function. */
1341 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1343 /* If the target function is Thumb, set the low bit of the function
1344 address. And if the CPU is currently in ARM mode, patch the
1345 second instruction of call dummy to use a BX instruction to
1346 switch to Thumb mode. */
1347 target_is_thumb
= arm_pc_is_thumb (fun
);
1348 if (target_is_thumb
)
1351 if (!caller_is_thumb
)
1352 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1355 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1356 instead of the ARM one that's already been copied. This will
1357 work for both Thumb and ARM target functions. */
1358 if (caller_is_thumb
)
1362 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1364 for (i
= 0; i
< len
; i
++)
1366 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1367 p
+= sizeof (thumb_dummy
[0]);
1371 /* Put the target address in r4; the call dummy will copy this to
1373 write_register (4, fun
);
1376 /* Return the offset in the call dummy of the instruction that needs
1377 to have a breakpoint placed on it. This is the offset of the 'swi
1378 24' instruction, which is no longer actually used, but simply acts
1379 as a place-holder now.
1381 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1384 arm_call_dummy_breakpoint_offset (void)
1386 if (caller_is_thumb
)
1394 This function does not support passing parameters using the FPA
1395 variant of the APCS. It passes any floating point arguments in the
1396 general registers and/or on the stack. */
1399 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1400 int struct_return
, CORE_ADDR struct_addr
)
1403 int argnum
, argreg
, nstack_size
;
1405 /* Walk through the list of args and determine how large a temporary
1406 stack is required. Need to take care here as structs may be
1407 passed on the stack, and we have to to push them. */
1408 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1409 if (struct_return
) /* The struct address goes in A1. */
1410 nstack_size
+= REGISTER_SIZE
;
1412 /* Walk through the arguments and add their size to nstack_size. */
1413 for (argnum
= 0; argnum
< nargs
; argnum
++)
1416 struct type
*arg_type
;
1418 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1419 len
= TYPE_LENGTH (arg_type
);
1421 /* ANSI C code passes float arguments as integers, K&R code
1422 passes float arguments as doubles. Correct for this here. */
1423 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1424 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1429 /* Allocate room on the stack, and initialize our stack frame
1432 if (nstack_size
> 0)
1438 /* Initialize the integer argument register pointer. */
1441 /* The struct_return pointer occupies the first parameter passing
1444 write_register (argreg
++, struct_addr
);
1446 /* Process arguments from left to right. Store as many as allowed
1447 in the parameter passing registers (A1-A4), and save the rest on
1448 the temporary stack. */
1449 for (argnum
= 0; argnum
< nargs
; argnum
++)
1454 enum type_code typecode
;
1455 struct type
*arg_type
, *target_type
;
1457 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1458 target_type
= TYPE_TARGET_TYPE (arg_type
);
1459 len
= TYPE_LENGTH (arg_type
);
1460 typecode
= TYPE_CODE (arg_type
);
1461 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1463 /* ANSI C code passes float arguments as integers, K&R code
1464 passes float arguments as doubles. The .stabs record for
1465 for ANSI prototype floating point arguments records the
1466 type as FP_INTEGER, while a K&R style (no prototype)
1467 .stabs records the type as FP_FLOAT. In this latter case
1468 the compiler converts the float arguments to double before
1469 calling the function. */
1470 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1473 dblval
= extract_floating (val
, len
);
1474 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1476 store_floating (val
, len
, dblval
);
1479 /* I don't know why this code was disable. The only logical use
1480 for a function pointer is to call that function, so setting
1481 the mode bit is perfectly fine. FN */
1482 /* If the argument is a pointer to a function, and it is a Thumb
1483 function, set the low bit of the pointer. */
1484 if (TYPE_CODE_PTR
== typecode
1485 && NULL
!= target_type
1486 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1488 CORE_ADDR regval
= extract_address (val
, len
);
1489 if (arm_pc_is_thumb (regval
))
1490 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1493 /* Copy the argument to general registers or the stack in
1494 register-sized pieces. Large arguments are split between
1495 registers and stack. */
1498 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1500 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1502 /* It's an argument being passed in a general register. */
1503 regval
= extract_address (val
, partial_len
);
1504 write_register (argreg
++, regval
);
1508 /* Push the arguments onto the stack. */
1509 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1510 fp
+= REGISTER_SIZE
;
1518 /* Return adjusted stack pointer. */
1522 /* Pop the current frame. So long as the frame info has been initialized
1523 properly (see arm_init_extra_frame_info), this code works for dummy frames
1524 as well as regular frames. I.e, there's no need to have a special case
1525 for dummy frames. */
1527 arm_pop_frame (void)
1530 struct frame_info
*frame
= get_current_frame ();
1531 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1532 + frame
->extra_info
->framesize
);
1534 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1535 if (frame
->saved_regs
[regnum
] != 0)
1536 write_register (regnum
,
1537 read_memory_integer (frame
->saved_regs
[regnum
],
1538 REGISTER_RAW_SIZE (regnum
)));
1540 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1541 write_register (SP_REGNUM
, old_SP
);
1543 flush_cached_frames ();
1547 print_fpu_flags (int flags
)
1549 if (flags
& (1 << 0))
1550 fputs ("IVO ", stdout
);
1551 if (flags
& (1 << 1))
1552 fputs ("DVZ ", stdout
);
1553 if (flags
& (1 << 2))
1554 fputs ("OFL ", stdout
);
1555 if (flags
& (1 << 3))
1556 fputs ("UFL ", stdout
);
1557 if (flags
& (1 << 4))
1558 fputs ("INX ", stdout
);
1563 arm_float_info (void)
1565 register unsigned long status
= read_register (FPS_REGNUM
);
1568 type
= (status
>> 24) & 127;
1569 printf ("%s FPU type %d\n",
1570 (status
& (1 << 31)) ? "Hardware" : "Software",
1572 fputs ("mask: ", stdout
);
1573 print_fpu_flags (status
>> 16);
1574 fputs ("flags: ", stdout
);
1575 print_fpu_flags (status
);
1579 arm_register_type (int regnum
)
1581 if (regnum
>= F0_REGNUM
&& regnum
< F0_REGNUM
+ NUM_FREGS
)
1583 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1584 return builtin_type_arm_ext_big
;
1586 return builtin_type_arm_ext_littlebyte_bigword
;
1589 return builtin_type_int32
;
1592 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1593 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1594 It is thought that this is is the floating-point register format on
1595 little-endian systems. */
1598 convert_from_extended (void *ptr
, void *dbl
)
1601 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1602 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1604 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1606 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1610 convert_to_extended (void *dbl
, void *ptr
)
1613 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1614 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1615 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1617 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1622 condition_true (unsigned long cond
, unsigned long status_reg
)
1624 if (cond
== INST_AL
|| cond
== INST_NV
)
1630 return ((status_reg
& FLAG_Z
) != 0);
1632 return ((status_reg
& FLAG_Z
) == 0);
1634 return ((status_reg
& FLAG_C
) != 0);
1636 return ((status_reg
& FLAG_C
) == 0);
1638 return ((status_reg
& FLAG_N
) != 0);
1640 return ((status_reg
& FLAG_N
) == 0);
1642 return ((status_reg
& FLAG_V
) != 0);
1644 return ((status_reg
& FLAG_V
) == 0);
1646 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1648 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1650 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1652 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1654 return (((status_reg
& FLAG_Z
) == 0) &&
1655 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1657 return (((status_reg
& FLAG_Z
) != 0) ||
1658 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1663 /* Support routines for single stepping. Calculate the next PC value. */
1664 #define submask(x) ((1L << ((x) + 1)) - 1)
1665 #define bit(obj,st) (((obj) >> (st)) & 1)
1666 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1667 #define sbits(obj,st,fn) \
1668 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1669 #define BranchDest(addr,instr) \
1670 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1673 static unsigned long
1674 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1675 unsigned long status_reg
)
1677 unsigned long res
, shift
;
1678 int rm
= bits (inst
, 0, 3);
1679 unsigned long shifttype
= bits (inst
, 5, 6);
1683 int rs
= bits (inst
, 8, 11);
1684 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1687 shift
= bits (inst
, 7, 11);
1690 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1691 + (bit (inst
, 4) ? 12 : 8))
1692 : read_register (rm
));
1697 res
= shift
>= 32 ? 0 : res
<< shift
;
1701 res
= shift
>= 32 ? 0 : res
>> shift
;
1707 res
= ((res
& 0x80000000L
)
1708 ? ~((~res
) >> shift
) : res
>> shift
);
1711 case 3: /* ROR/RRX */
1714 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1716 res
= (res
>> shift
) | (res
<< (32 - shift
));
1720 return res
& 0xffffffff;
1723 /* Return number of 1-bits in VAL. */
1726 bitcount (unsigned long val
)
1729 for (nbits
= 0; val
!= 0; nbits
++)
1730 val
&= val
- 1; /* delete rightmost 1-bit in val */
1735 thumb_get_next_pc (CORE_ADDR pc
)
1737 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1738 unsigned short inst1
= read_memory_integer (pc
, 2);
1739 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1740 unsigned long offset
;
1742 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1746 /* Fetch the saved PC from the stack. It's stored above
1747 all of the other registers. */
1748 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1749 sp
= read_register (SP_REGNUM
);
1750 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1751 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1753 error ("Infinite loop detected");
1755 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1757 unsigned long status
= read_register (PS_REGNUM
);
1758 unsigned long cond
= bits (inst1
, 8, 11);
1759 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1760 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1762 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1764 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1766 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1768 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1769 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1770 nextpc
= pc_val
+ offset
;
1777 arm_get_next_pc (CORE_ADDR pc
)
1779 unsigned long pc_val
;
1780 unsigned long this_instr
;
1781 unsigned long status
;
1784 if (arm_pc_is_thumb (pc
))
1785 return thumb_get_next_pc (pc
);
1787 pc_val
= (unsigned long) pc
;
1788 this_instr
= read_memory_integer (pc
, 4);
1789 status
= read_register (PS_REGNUM
);
1790 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1792 if (condition_true (bits (this_instr
, 28, 31), status
))
1794 switch (bits (this_instr
, 24, 27))
1797 case 0x1: /* data processing */
1801 unsigned long operand1
, operand2
, result
= 0;
1805 if (bits (this_instr
, 12, 15) != 15)
1808 if (bits (this_instr
, 22, 25) == 0
1809 && bits (this_instr
, 4, 7) == 9) /* multiply */
1810 error ("Illegal update to pc in instruction");
1812 /* Multiply into PC */
1813 c
= (status
& FLAG_C
) ? 1 : 0;
1814 rn
= bits (this_instr
, 16, 19);
1815 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1817 if (bit (this_instr
, 25))
1819 unsigned long immval
= bits (this_instr
, 0, 7);
1820 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1821 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1824 else /* operand 2 is a shifted register */
1825 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1827 switch (bits (this_instr
, 21, 24))
1830 result
= operand1
& operand2
;
1834 result
= operand1
^ operand2
;
1838 result
= operand1
- operand2
;
1842 result
= operand2
- operand1
;
1846 result
= operand1
+ operand2
;
1850 result
= operand1
+ operand2
+ c
;
1854 result
= operand1
- operand2
+ c
;
1858 result
= operand2
- operand1
+ c
;
1864 case 0xb: /* tst, teq, cmp, cmn */
1865 result
= (unsigned long) nextpc
;
1869 result
= operand1
| operand2
;
1873 /* Always step into a function. */
1878 result
= operand1
& ~operand2
;
1885 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1888 error ("Infinite loop detected");
1893 case 0x5: /* data transfer */
1896 if (bit (this_instr
, 20))
1899 if (bits (this_instr
, 12, 15) == 15)
1905 if (bit (this_instr
, 22))
1906 error ("Illegal update to pc in instruction");
1908 /* byte write to PC */
1909 rn
= bits (this_instr
, 16, 19);
1910 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1911 if (bit (this_instr
, 24))
1914 int c
= (status
& FLAG_C
) ? 1 : 0;
1915 unsigned long offset
=
1916 (bit (this_instr
, 25)
1917 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1918 : bits (this_instr
, 0, 11));
1920 if (bit (this_instr
, 23))
1925 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1928 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1931 error ("Infinite loop detected");
1937 case 0x9: /* block transfer */
1938 if (bit (this_instr
, 20))
1941 if (bit (this_instr
, 15))
1946 if (bit (this_instr
, 23))
1949 unsigned long reglist
= bits (this_instr
, 0, 14);
1950 offset
= bitcount (reglist
) * 4;
1951 if (bit (this_instr
, 24)) /* pre */
1954 else if (bit (this_instr
, 24))
1958 unsigned long rn_val
=
1959 read_register (bits (this_instr
, 16, 19));
1961 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1965 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1967 error ("Infinite loop detected");
1972 case 0xb: /* branch & link */
1973 case 0xa: /* branch */
1975 nextpc
= BranchDest (pc
, this_instr
);
1977 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1979 error ("Infinite loop detected");
1985 case 0xe: /* coproc ops */
1990 fprintf (stderr
, "Bad bit-field extraction\n");
1998 /* single_step() is called just before we want to resume the inferior,
1999 if we want to single-step it but there is no hardware or kernel
2000 single-step support. We find the target of the coming instruction
2003 single_step is also called just after the inferior stops. If we had
2004 set up a simulated single-step, we undo our damage. */
2007 arm_software_single_step (ignore
, insert_bpt
)
2008 int ignore
; /* Signal, not needed */
2011 static int next_pc
; /* State between setting and unsetting. */
2012 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2016 next_pc
= arm_get_next_pc (read_register (PC_REGNUM
));
2017 target_insert_breakpoint (next_pc
, break_mem
);
2020 target_remove_breakpoint (next_pc
, break_mem
);
2023 #include "bfd-in2.h"
2024 #include "libcoff.h"
2027 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2029 if (arm_pc_is_thumb (memaddr
))
2031 static asymbol
*asym
;
2032 static combined_entry_type ce
;
2033 static struct coff_symbol_struct csym
;
2034 static struct _bfd fake_bfd
;
2035 static bfd_target fake_target
;
2037 if (csym
.native
== NULL
)
2039 /* Create a fake symbol vector containing a Thumb symbol. This is
2040 solely so that the code in print_insn_little_arm() and
2041 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
2042 of a Thumb symbol and switch to decoding Thumb instructions. */
2044 fake_target
.flavour
= bfd_target_coff_flavour
;
2045 fake_bfd
.xvec
= &fake_target
;
2046 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2048 csym
.symbol
.the_bfd
= &fake_bfd
;
2049 csym
.symbol
.name
= "fake";
2050 asym
= (asymbol
*) & csym
;
2053 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2054 info
->symbols
= &asym
;
2057 info
->symbols
= NULL
;
2059 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2060 return print_insn_big_arm (memaddr
, info
);
2062 return print_insn_little_arm (memaddr
, info
);
2065 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
2066 program counter value to determine whether a 16-bit or 32-bit
2067 breakpoint should be used. It returns a pointer to a string of
2068 bytes that encode a breakpoint instruction, stores the length of
2069 the string to *lenptr, and adjusts the program counter (if
2070 necessary) to point to the actual memory location where the
2071 breakpoint should be inserted. */
2074 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2076 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2078 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2080 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2081 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2082 *lenptr
= sizeof (thumb_breakpoint
);
2083 return thumb_breakpoint
;
2087 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2088 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2089 *lenptr
= sizeof (thumb_breakpoint
);
2090 return thumb_breakpoint
;
2095 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2097 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
2098 *lenptr
= sizeof (arm_breakpoint
);
2099 return arm_breakpoint
;
2103 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
2104 *lenptr
= sizeof (arm_breakpoint
);
2105 return arm_breakpoint
;
2110 /* Extract from an array REGBUF containing the (raw) register state a
2111 function return value of type TYPE, and copy that, in virtual
2112 format, into VALBUF. */
2115 arm_extract_return_value (struct type
*type
,
2116 char regbuf
[REGISTER_BYTES
],
2119 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2120 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
2122 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
2125 /* Return non-zero if the PC is inside a thumb call thunk. */
2128 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2130 CORE_ADDR start_addr
;
2132 /* Find the starting address of the function containing the PC. If
2133 the caller didn't give us a name, look it up at the same time. */
2134 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2137 return strncmp (name
, "_call_via_r", 11) == 0;
2140 /* If PC is in a Thumb call or return stub, return the address of the
2141 target PC, which is in a register. The thunk functions are called
2142 _called_via_xx, where x is the register name. The possible names
2143 are r0-r9, sl, fp, ip, sp, and lr. */
2146 arm_skip_stub (CORE_ADDR pc
)
2149 CORE_ADDR start_addr
;
2151 /* Find the starting address and name of the function containing the PC. */
2152 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2155 /* Call thunks always start with "_call_via_". */
2156 if (strncmp (name
, "_call_via_", 10) == 0)
2158 /* Use the name suffix to determine which register contains the
2160 static char *table
[15] =
2161 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2162 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2166 for (regno
= 0; regno
<= 14; regno
++)
2167 if (strcmp (&name
[10], table
[regno
]) == 0)
2168 return read_register (regno
);
2171 return 0; /* not a stub */
2174 /* If the user changes the register disassembly flavor used for info register
2175 and other commands, we have to also switch the flavor used in opcodes
2176 for disassembly output.
2177 This function is run in the set disassembly_flavor command, and does that. */
2180 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2181 struct cmd_list_element
*c
)
2183 set_disassembly_flavor ();
2186 /* Return the ARM register name corresponding to register I. */
2188 arm_register_name(int i
)
2190 return arm_register_names
[i
];
2194 set_disassembly_flavor (void)
2196 const char *setname
, *setdesc
, **regnames
;
2199 /* Find the flavor that the user wants in the opcodes table. */
2201 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2202 while ((disassembly_flavor
!= setname
)
2203 && (current
< num_flavor_options
))
2204 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2205 current_option
= current
;
2207 /* Fill our copy. */
2208 for (j
= 0; j
< numregs
; j
++)
2209 arm_register_names
[j
] = (char *) regnames
[j
];
2212 if (isupper (*regnames
[PC_REGNUM
]))
2214 arm_register_names
[FPS_REGNUM
] = "FPS";
2215 arm_register_names
[PS_REGNUM
] = "CPSR";
2219 arm_register_names
[FPS_REGNUM
] = "fps";
2220 arm_register_names
[PS_REGNUM
] = "cpsr";
2223 /* Synchronize the disassembler. */
2224 set_arm_regname_option (current
);
2227 /* arm_othernames implements the "othernames" command. This is kind
2228 of hacky, and I prefer the set-show disassembly-flavor which is
2229 also used for the x86 gdb. I will keep this around, however, in
2230 case anyone is actually using it. */
2233 arm_othernames (char *names
, int n
)
2235 /* Circle through the various flavors. */
2236 current_option
= (current_option
+ 1) % num_flavor_options
;
2238 disassembly_flavor
= valid_flavors
[current_option
];
2239 set_disassembly_flavor ();
2242 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2243 for ARM linux targets using the struct offsets defined in <link.h>.
2244 Note, however, that link.h is not actually referred to in this file.
2245 Instead, the relevant structs offsets were obtained from examining
2246 link.h. (We can't refer to link.h from this file because the host
2247 system won't necessarily have it, or if it does, the structs which
2248 it defines will refer to the host system, not the target.) */
2250 struct link_map_offsets
*
2251 arm_linux_svr4_fetch_link_map_offsets (void)
2253 static struct link_map_offsets lmo
;
2254 static struct link_map_offsets
*lmp
= 0;
2260 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2263 lmo
.r_map_offset
= 4;
2266 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2269 lmo
.l_addr_offset
= 0;
2270 lmo
.l_addr_size
= 4;
2272 lmo
.l_name_offset
= 4;
2273 lmo
.l_name_size
= 4;
2275 lmo
.l_next_offset
= 12;
2276 lmo
.l_next_size
= 4;
2278 lmo
.l_prev_offset
= 16;
2279 lmo
.l_prev_size
= 4;
2286 _initialize_arm_tdep (void)
2288 struct ui_file
*stb
;
2290 struct cmd_list_element
*new_cmd
;
2291 const char *setname
;
2292 const char *setdesc
;
2293 const char **regnames
;
2295 static char *helptext
;
2297 tm_print_insn
= gdb_print_insn_arm
;
2299 /* Get the number of possible sets of register names defined in opcodes. */
2300 num_flavor_options
= get_arm_regname_num_options ();
2302 /* Sync the opcode insn printer with our register viewer: */
2303 parse_arm_disassembler_option ("reg-names-std");
2305 /* Begin creating the help text. */
2306 stb
= mem_fileopen ();
2307 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2308 The valid values are:\n");
2310 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2311 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2312 for (i
= 0; i
< num_flavor_options
; i
++)
2314 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2315 valid_flavors
[i
] = setname
;
2316 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2318 /* Copy the default names (if found) and synchronize disassembler. */
2319 if (!strcmp (setname
, "std"))
2321 disassembly_flavor
= setname
;
2323 for (j
= 0; j
< numregs
; j
++)
2324 arm_register_names
[j
] = (char *) regnames
[j
];
2325 set_arm_regname_option (i
);
2328 /* Mark the end of valid options. */
2329 valid_flavors
[num_flavor_options
] = NULL
;
2331 /* Finish the creation of the help text. */
2332 fprintf_unfiltered (stb
, "The default is \"std\".");
2333 helptext
= ui_file_xstrdup (stb
, &length
);
2334 ui_file_delete (stb
);
2336 /* Add the disassembly-flavor command */
2337 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2339 &disassembly_flavor
,
2342 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
2343 add_show_from_set (new_cmd
, &showlist
);
2345 /* ??? Maybe this should be a boolean. */
2346 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2347 var_zinteger
, (char *) &arm_apcs_32
,
2348 "Set usage of ARM 32-bit mode.\n", &setlist
),
2351 /* Add the deprecated "othernames" command */
2353 add_com ("othernames", class_obscure
, arm_othernames
,
2354 "Switch to the next set of register names.");
2356 /* Fill in the prologue_cache fields. */
2357 prologue_cache
.extra_info
= (struct frame_extra_info
*)
2358 xcalloc (1, sizeof (struct frame_extra_info
));
2359 prologue_cache
.saved_regs
= (CORE_ADDR
*)
2360 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
2363 /* Test whether the coff symbol specific value corresponds to a Thumb
2367 coff_sym_is_thumb (int val
)
2369 return (val
== C_THUMBEXT
||
2370 val
== C_THUMBSTAT
||
2371 val
== C_THUMBEXTFUNC
||
2372 val
== C_THUMBSTATFUNC
||
2373 val
== C_THUMBLABEL
);