1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
58 #include "record-full.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data
*arm_objfile_data_key
;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
92 DEF_VEC_O(arm_mapping_symbol_s
);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s
) **section_maps
;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element
*setarmcmdlist
= NULL
;
101 static struct cmd_list_element
*showarmcmdlist
= NULL
;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings
[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
117 static const char *current_fp_model
= "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
130 static const char *arm_abi_string
= "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode
= -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options
;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases
[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names
[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles
;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style
;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element
*);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat
*, const void *,
228 static void convert_to_extended (const struct floatformat
*, void *,
231 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
232 struct regcache
*regcache
,
233 int regnum
, gdb_byte
*buf
);
234 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, const gdb_byte
*buf
);
238 static int thumb_insn_size (unsigned short inst1
);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg
*saved_regs
;
260 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
261 CORE_ADDR prologue_start
,
262 CORE_ADDR prologue_end
,
263 struct arm_prologue_cache
*cache
);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
285 if (gdbarch_tdep (gdbarch
)->is_m
)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info
*frame
)
297 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
312 const struct arm_mapping_symbol
*rhs
)
314 return lhs
->value
< rhs
->value
;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
324 struct obj_section
*sec
;
326 /* If there are mapping symbols, consult them. */
327 sec
= find_pc_section (memaddr
);
330 struct arm_per_objfile
*data
;
331 VEC(arm_mapping_symbol_s
) *map
;
332 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
336 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
339 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
340 if (!VEC_empty (arm_mapping_symbol_s
, map
))
342 struct arm_mapping_symbol
*map_sym
;
344 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
345 arm_compare_mapping_symbols
);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
353 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
354 if (map_sym
->value
== map_key
.value
)
357 *start
= map_sym
->value
+ obj_section_addr (sec
);
358 return map_sym
->type
;
364 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
366 *start
= map_sym
->value
+ obj_section_addr (sec
);
367 return map_sym
->type
;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
383 struct bound_minimal_symbol sym
;
385 struct displaced_step_closure
* dsc
386 = get_displaced_step_closure_by_addr(memaddr
);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog
,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc
->insn_addr
,
396 (unsigned long) memaddr
);
397 memaddr
= dsc
->insn_addr
;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr
))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode
!= -1)
406 return arm_override_mode
;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string
, "arm") == 0)
411 if (strcmp (arm_force_mode_string
, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch
)->is_m
)
418 /* If there are mapping symbols, consult them. */
419 type
= arm_find_mapping_symbol (memaddr
, NULL
);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym
= lookup_minimal_symbol_by_pc (memaddr
);
426 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers
)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* On M-profile devices, do not strip the low bit from EXC_RETURN
451 (the magic exception return address). */
452 if (gdbarch_tdep (gdbarch
)->is_m
453 && (val
& 0xfffffff0) == 0xfffffff0)
457 return UNMAKE_THUMB_ADDR (val
);
459 return (val
& 0x03fffffc);
462 /* Return 1 if PC is the start of a compiler helper function which
463 can be safely ignored during prologue skipping. IS_THUMB is true
464 if the function is known to be a Thumb function due to the way it
467 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
469 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
470 struct bound_minimal_symbol msym
;
472 msym
= lookup_minimal_symbol_by_pc (pc
);
473 if (msym
.minsym
!= NULL
474 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
475 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
477 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
479 /* The GNU linker's Thumb call stub to foo is named
481 if (strstr (name
, "_from_thumb") != NULL
)
484 /* On soft-float targets, __truncdfsf2 is called to convert promoted
485 arguments to their argument types in non-prototyped
487 if (startswith (name
, "__truncdfsf2"))
489 if (startswith (name
, "__aeabi_d2f"))
492 /* Internal functions related to thread-local storage. */
493 if (startswith (name
, "__tls_get_addr"))
495 if (startswith (name
, "__aeabi_read_tp"))
500 /* If we run against a stripped glibc, we may be unable to identify
501 special functions by name. Check for one important case,
502 __aeabi_read_tp, by comparing the *code* against the default
503 implementation (this is hand-written ARM assembler in glibc). */
506 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
507 == 0xe3e00a0f /* mov r0, #0xffff0fff */
508 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
509 == 0xe240f01f) /* sub pc, r0, #31 */
516 /* Support routines for instruction parsing. */
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
525 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
526 the first 16-bit of instruction, and INSN2 is the second 16-bit of
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
534 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
535 the 32-bit instruction. */
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
540 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
543 thumb_expand_immediate (unsigned int imm
)
545 unsigned int count
= imm
>> 7;
553 return (imm
& 0xff) | ((imm
& 0xff) << 16);
555 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
557 return (imm
& 0xff) | ((imm
& 0xff) << 8)
558 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
561 return (0x80 | (imm
& 0x7f)) << (32 - count
);
564 /* Return 1 if the 16-bit Thumb instruction INST might change
565 control flow, 0 otherwise. */
568 thumb_instruction_changes_pc (unsigned short inst
)
570 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
573 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
576 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
579 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
582 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
585 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
591 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
592 might change control flow, 0 otherwise. */
595 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
597 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
599 /* Branches and miscellaneous control instructions. */
601 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
606 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
608 /* SUBS PC, LR, #imm8. */
611 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
613 /* Conditional branch. */
620 if ((inst1
& 0xfe50) == 0xe810)
622 /* Load multiple or RFE. */
624 if (bit (inst1
, 7) && !bit (inst1
, 8))
630 else if (!bit (inst1
, 7) && bit (inst1
, 8))
636 else if (bit (inst1
, 7) && bit (inst1
, 8))
641 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
650 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
652 /* MOV PC or MOVS PC. */
656 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
659 if (bits (inst1
, 0, 3) == 15)
665 if ((inst2
& 0x0fc0) == 0x0000)
671 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
677 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
686 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
687 epilogue, 0 otherwise. */
690 thumb_instruction_restores_sp (unsigned short insn
)
692 return (insn
== 0x46bd /* mov sp, r7 */
693 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
694 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
697 /* Analyze a Thumb prologue, looking for a recognizable stack frame
698 and frame pointer. Scan until we encounter a store that could
699 clobber the stack frame unexpectedly, or an unknown instruction.
700 Return the last address which is definitely safe to skip for an
701 initial breakpoint. */
704 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
705 CORE_ADDR start
, CORE_ADDR limit
,
706 struct arm_prologue_cache
*cache
)
708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
709 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
712 struct pv_area
*stack
;
713 struct cleanup
*back_to
;
715 CORE_ADDR unrecognized_pc
= 0;
717 for (i
= 0; i
< 16; i
++)
718 regs
[i
] = pv_register (i
, 0);
719 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
720 back_to
= make_cleanup_free_pv_area (stack
);
722 while (start
< limit
)
726 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
728 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
733 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
736 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
737 whether to save LR (R14). */
738 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
740 /* Calculate offsets of saved R0-R7 and LR. */
741 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
742 if (mask
& (1 << regno
))
744 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
746 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
749 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
751 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
752 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
755 else if (thumb_instruction_restores_sp (insn
))
757 /* Don't scan past the epilogue. */
760 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
761 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
763 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
764 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
765 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
767 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
768 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
769 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
771 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
772 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
773 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
774 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
775 regs
[bits (insn
, 6, 8)]);
776 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
777 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
779 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
780 int rm
= bits (insn
, 3, 6);
781 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
783 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
785 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
786 int src_reg
= (insn
& 0x78) >> 3;
787 regs
[dst_reg
] = regs
[src_reg
];
789 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
791 /* Handle stores to the stack. Normally pushes are used,
792 but with GCC -mtpcs-frame, there may be other stores
793 in the prologue to create the frame. */
794 int regno
= (insn
>> 8) & 0x7;
797 offset
= (insn
& 0xff) << 2;
798 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
800 if (pv_area_store_would_trash (stack
, addr
))
803 pv_area_store (stack
, addr
, 4, regs
[regno
]);
805 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
807 int rd
= bits (insn
, 0, 2);
808 int rn
= bits (insn
, 3, 5);
811 offset
= bits (insn
, 6, 10) << 2;
812 addr
= pv_add_constant (regs
[rn
], offset
);
814 if (pv_area_store_would_trash (stack
, addr
))
817 pv_area_store (stack
, addr
, 4, regs
[rd
]);
819 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
820 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
821 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
822 /* Ignore stores of argument registers to the stack. */
824 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
825 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
826 /* Ignore block loads from the stack, potentially copying
827 parameters from memory. */
829 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
830 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
831 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
832 /* Similarly ignore single loads from the stack. */
834 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
835 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
836 /* Skip register copies, i.e. saves to another register
837 instead of the stack. */
839 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
840 /* Recognize constant loads; even with small stacks these are necessary
842 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
843 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
845 /* Constant pool loads, for the same reason. */
846 unsigned int constant
;
849 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
850 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
851 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
853 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
855 unsigned short inst2
;
857 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
858 byte_order_for_code
);
860 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
862 /* BL, BLX. Allow some special function calls when
863 skipping the prologue; GCC generates these before
864 storing arguments to the stack. */
866 int j1
, j2
, imm1
, imm2
;
868 imm1
= sbits (insn
, 0, 10);
869 imm2
= bits (inst2
, 0, 10);
870 j1
= bit (inst2
, 13);
871 j2
= bit (inst2
, 11);
873 offset
= ((imm1
<< 12) + (imm2
<< 1));
874 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
876 nextpc
= start
+ 4 + offset
;
877 /* For BLX make sure to clear the low bits. */
878 if (bit (inst2
, 12) == 0)
879 nextpc
= nextpc
& 0xfffffffc;
881 if (!skip_prologue_function (gdbarch
, nextpc
,
882 bit (inst2
, 12) != 0))
886 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
888 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
890 pv_t addr
= regs
[bits (insn
, 0, 3)];
893 if (pv_area_store_would_trash (stack
, addr
))
896 /* Calculate offsets of saved registers. */
897 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
898 if (inst2
& (1 << regno
))
900 addr
= pv_add_constant (addr
, -4);
901 pv_area_store (stack
, addr
, 4, regs
[regno
]);
905 regs
[bits (insn
, 0, 3)] = addr
;
908 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
910 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
912 int regno1
= bits (inst2
, 12, 15);
913 int regno2
= bits (inst2
, 8, 11);
914 pv_t addr
= regs
[bits (insn
, 0, 3)];
916 offset
= inst2
& 0xff;
918 addr
= pv_add_constant (addr
, offset
);
920 addr
= pv_add_constant (addr
, -offset
);
922 if (pv_area_store_would_trash (stack
, addr
))
925 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
926 pv_area_store (stack
, pv_add_constant (addr
, 4),
930 regs
[bits (insn
, 0, 3)] = addr
;
933 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
934 && (inst2
& 0x0c00) == 0x0c00
935 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
937 int regno
= bits (inst2
, 12, 15);
938 pv_t addr
= regs
[bits (insn
, 0, 3)];
940 offset
= inst2
& 0xff;
942 addr
= pv_add_constant (addr
, offset
);
944 addr
= pv_add_constant (addr
, -offset
);
946 if (pv_area_store_would_trash (stack
, addr
))
949 pv_area_store (stack
, addr
, 4, regs
[regno
]);
952 regs
[bits (insn
, 0, 3)] = addr
;
955 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
956 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
958 int regno
= bits (inst2
, 12, 15);
961 offset
= inst2
& 0xfff;
962 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
964 if (pv_area_store_would_trash (stack
, addr
))
967 pv_area_store (stack
, addr
, 4, regs
[regno
]);
970 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
971 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
972 /* Ignore stores of argument registers to the stack. */
975 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
976 && (inst2
& 0x0d00) == 0x0c00
977 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
978 /* Ignore stores of argument registers to the stack. */
981 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
983 && (inst2
& 0x8000) == 0x0000
984 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
985 /* Ignore block loads from the stack, potentially copying
986 parameters from memory. */
989 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
991 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
992 /* Similarly ignore dual loads from the stack. */
995 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
996 && (inst2
& 0x0d00) == 0x0c00
997 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
998 /* Similarly ignore single loads from the stack. */
1001 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1002 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1003 /* Similarly ignore single loads from the stack. */
1006 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1007 && (inst2
& 0x8000) == 0x0000)
1009 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1010 | (bits (inst2
, 12, 14) << 8)
1011 | bits (inst2
, 0, 7));
1013 regs
[bits (inst2
, 8, 11)]
1014 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1015 thumb_expand_immediate (imm
));
1018 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1019 && (inst2
& 0x8000) == 0x0000)
1021 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1022 | (bits (inst2
, 12, 14) << 8)
1023 | bits (inst2
, 0, 7));
1025 regs
[bits (inst2
, 8, 11)]
1026 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1029 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1030 && (inst2
& 0x8000) == 0x0000)
1032 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1033 | (bits (inst2
, 12, 14) << 8)
1034 | bits (inst2
, 0, 7));
1036 regs
[bits (inst2
, 8, 11)]
1037 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1038 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1041 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1042 && (inst2
& 0x8000) == 0x0000)
1044 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1045 | (bits (inst2
, 12, 14) << 8)
1046 | bits (inst2
, 0, 7));
1048 regs
[bits (inst2
, 8, 11)]
1049 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1052 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1054 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1055 | (bits (inst2
, 12, 14) << 8)
1056 | bits (inst2
, 0, 7));
1058 regs
[bits (inst2
, 8, 11)]
1059 = pv_constant (thumb_expand_immediate (imm
));
1062 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1065 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1067 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1070 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1071 && (inst2
& 0xf0f0) == 0)
1073 int dst_reg
= (inst2
& 0x0f00) >> 8;
1074 int src_reg
= inst2
& 0xf;
1075 regs
[dst_reg
] = regs
[src_reg
];
1078 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1080 /* Constant pool loads. */
1081 unsigned int constant
;
1084 offset
= bits (inst2
, 0, 11);
1086 loc
= start
+ 4 + offset
;
1088 loc
= start
+ 4 - offset
;
1090 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1091 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1094 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1096 /* Constant pool loads. */
1097 unsigned int constant
;
1100 offset
= bits (inst2
, 0, 7) << 2;
1102 loc
= start
+ 4 + offset
;
1104 loc
= start
+ 4 - offset
;
1106 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1107 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1109 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1110 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1113 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1115 /* Don't scan past anything that might change control flow. */
1120 /* The optimizer might shove anything into the prologue,
1121 so we just skip what we don't recognize. */
1122 unrecognized_pc
= start
;
1127 else if (thumb_instruction_changes_pc (insn
))
1129 /* Don't scan past anything that might change control flow. */
1134 /* The optimizer might shove anything into the prologue,
1135 so we just skip what we don't recognize. */
1136 unrecognized_pc
= start
;
1143 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1144 paddress (gdbarch
, start
));
1146 if (unrecognized_pc
== 0)
1147 unrecognized_pc
= start
;
1151 do_cleanups (back_to
);
1152 return unrecognized_pc
;
1155 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1157 /* Frame pointer is fp. Frame size is constant. */
1158 cache
->framereg
= ARM_FP_REGNUM
;
1159 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1161 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1163 /* Frame pointer is r7. Frame size is constant. */
1164 cache
->framereg
= THUMB_FP_REGNUM
;
1165 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1169 /* Try the stack pointer... this is a bit desperate. */
1170 cache
->framereg
= ARM_SP_REGNUM
;
1171 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1174 for (i
= 0; i
< 16; i
++)
1175 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1176 cache
->saved_regs
[i
].addr
= offset
;
1178 do_cleanups (back_to
);
1179 return unrecognized_pc
;
1183 /* Try to analyze the instructions starting from PC, which load symbol
1184 __stack_chk_guard. Return the address of instruction after loading this
1185 symbol, set the dest register number to *BASEREG, and set the size of
1186 instructions for loading symbol in OFFSET. Return 0 if instructions are
1190 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1191 unsigned int *destreg
, int *offset
)
1193 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1195 unsigned int low
, high
, address
;
1200 unsigned short insn1
1201 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1203 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1205 *destreg
= bits (insn1
, 8, 10);
1207 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1208 address
= read_memory_unsigned_integer (address
, 4,
1209 byte_order_for_code
);
1211 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1213 unsigned short insn2
1214 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1216 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1219 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1221 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1223 /* movt Rd, #const */
1224 if ((insn1
& 0xfbc0) == 0xf2c0)
1226 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1227 *destreg
= bits (insn2
, 8, 11);
1229 address
= (high
<< 16 | low
);
1236 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1238 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1240 address
= bits (insn
, 0, 11) + pc
+ 8;
1241 address
= read_memory_unsigned_integer (address
, 4,
1242 byte_order_for_code
);
1244 *destreg
= bits (insn
, 12, 15);
1247 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1249 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1252 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1254 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1256 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1257 *destreg
= bits (insn
, 12, 15);
1259 address
= (high
<< 16 | low
);
1267 /* Try to skip a sequence of instructions used for stack protector. If PC
1268 points to the first instruction of this sequence, return the address of
1269 first instruction after this sequence, otherwise, return original PC.
1271 On arm, this sequence of instructions is composed of mainly three steps,
1272 Step 1: load symbol __stack_chk_guard,
1273 Step 2: load from address of __stack_chk_guard,
1274 Step 3: store it to somewhere else.
1276 Usually, instructions on step 2 and step 3 are the same on various ARM
1277 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1278 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1279 instructions in step 1 vary from different ARM architectures. On ARMv7,
1282 movw Rn, #:lower16:__stack_chk_guard
1283 movt Rn, #:upper16:__stack_chk_guard
1290 .word __stack_chk_guard
1292 Since ldr/str is a very popular instruction, we can't use them as
1293 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1294 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1295 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1298 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1300 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1301 unsigned int basereg
;
1302 struct bound_minimal_symbol stack_chk_guard
;
1304 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1307 /* Try to parse the instructions in Step 1. */
1308 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1313 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1314 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1315 Otherwise, this sequence cannot be for stack protector. */
1316 if (stack_chk_guard
.minsym
== NULL
1317 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1322 unsigned int destreg
;
1324 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1326 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1327 if ((insn
& 0xf800) != 0x6800)
1329 if (bits (insn
, 3, 5) != basereg
)
1331 destreg
= bits (insn
, 0, 2);
1333 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1334 byte_order_for_code
);
1335 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1336 if ((insn
& 0xf800) != 0x6000)
1338 if (destreg
!= bits (insn
, 0, 2))
1343 unsigned int destreg
;
1345 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1347 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1348 if ((insn
& 0x0e500000) != 0x04100000)
1350 if (bits (insn
, 16, 19) != basereg
)
1352 destreg
= bits (insn
, 12, 15);
1353 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1354 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1355 4, byte_order_for_code
);
1356 if ((insn
& 0x0e500000) != 0x04000000)
1358 if (bits (insn
, 12, 15) != destreg
)
1361 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1364 return pc
+ offset
+ 4;
1366 return pc
+ offset
+ 8;
1369 /* Advance the PC across any function entry prologue instructions to
1370 reach some "real" code.
1372 The APCS (ARM Procedure Call Standard) defines the following
1376 [stmfd sp!, {a1,a2,a3,a4}]
1377 stmfd sp!, {...,fp,ip,lr,pc}
1378 [stfe f7, [sp, #-12]!]
1379 [stfe f6, [sp, #-12]!]
1380 [stfe f5, [sp, #-12]!]
1381 [stfe f4, [sp, #-12]!]
1382 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1385 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1387 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1389 CORE_ADDR func_addr
, limit_pc
;
1391 /* See if we can determine the end of the prologue via the symbol table.
1392 If so, then return either PC, or the PC after the prologue, whichever
1394 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1396 CORE_ADDR post_prologue_pc
1397 = skip_prologue_using_sal (gdbarch
, func_addr
);
1398 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1400 if (post_prologue_pc
)
1402 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1405 /* GCC always emits a line note before the prologue and another
1406 one after, even if the two are at the same address or on the
1407 same line. Take advantage of this so that we do not need to
1408 know every instruction that might appear in the prologue. We
1409 will have producer information for most binaries; if it is
1410 missing (e.g. for -gstabs), assuming the GNU tools. */
1411 if (post_prologue_pc
1413 || COMPUNIT_PRODUCER (cust
) == NULL
1414 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1415 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1416 return post_prologue_pc
;
1418 if (post_prologue_pc
!= 0)
1420 CORE_ADDR analyzed_limit
;
1422 /* For non-GCC compilers, make sure the entire line is an
1423 acceptable prologue; GDB will round this function's
1424 return value up to the end of the following line so we
1425 can not skip just part of a line (and we do not want to).
1427 RealView does not treat the prologue specially, but does
1428 associate prologue code with the opening brace; so this
1429 lets us skip the first line if we think it is the opening
1431 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1432 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1433 post_prologue_pc
, NULL
);
1435 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1436 post_prologue_pc
, NULL
);
1438 if (analyzed_limit
!= post_prologue_pc
)
1441 return post_prologue_pc
;
1445 /* Can't determine prologue from the symbol table, need to examine
1448 /* Find an upper limit on the function prologue using the debug
1449 information. If the debug information could not be used to provide
1450 that bound, then use an arbitrary large number as the upper bound. */
1451 /* Like arm_scan_prologue, stop no later than pc + 64. */
1452 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1454 limit_pc
= pc
+ 64; /* Magic. */
1457 /* Check if this is Thumb code. */
1458 if (arm_pc_is_thumb (gdbarch
, pc
))
1459 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1461 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1465 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1466 This function decodes a Thumb function prologue to determine:
1467 1) the size of the stack frame
1468 2) which registers are saved on it
1469 3) the offsets of saved regs
1470 4) the offset from the stack pointer to the frame pointer
1472 A typical Thumb function prologue would create this stack frame
1473 (offsets relative to FP)
1474 old SP -> 24 stack parameters
1477 R7 -> 0 local variables (16 bytes)
1478 SP -> -12 additional stack space (12 bytes)
1479 The frame size would thus be 36 bytes, and the frame offset would be
1480 12 bytes. The frame register is R7.
1482 The comments for thumb_skip_prolog() describe the algorithm we use
1483 to detect the end of the prolog. */
1487 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1488 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1490 CORE_ADDR prologue_start
;
1491 CORE_ADDR prologue_end
;
1493 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1496 /* See comment in arm_scan_prologue for an explanation of
1498 if (prologue_end
> prologue_start
+ 64)
1500 prologue_end
= prologue_start
+ 64;
1504 /* We're in the boondocks: we have no idea where the start of the
1508 prologue_end
= min (prologue_end
, prev_pc
);
1510 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1513 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1516 arm_instruction_changes_pc (uint32_t this_instr
)
1518 if (bits (this_instr
, 28, 31) == INST_NV
)
1519 /* Unconditional instructions. */
1520 switch (bits (this_instr
, 24, 27))
1524 /* Branch with Link and change to Thumb. */
1529 /* Coprocessor register transfer. */
1530 if (bits (this_instr
, 12, 15) == 15)
1531 error (_("Invalid update to pc in instruction"));
1537 switch (bits (this_instr
, 25, 27))
1540 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1542 /* Multiplies and extra load/stores. */
1543 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1544 /* Neither multiplies nor extension load/stores are allowed
1548 /* Otherwise, miscellaneous instructions. */
1550 /* BX <reg>, BXJ <reg>, BLX <reg> */
1551 if (bits (this_instr
, 4, 27) == 0x12fff1
1552 || bits (this_instr
, 4, 27) == 0x12fff2
1553 || bits (this_instr
, 4, 27) == 0x12fff3)
1556 /* Other miscellaneous instructions are unpredictable if they
1560 /* Data processing instruction. Fall through. */
1563 if (bits (this_instr
, 12, 15) == 15)
1570 /* Media instructions and architecturally undefined instructions. */
1571 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1575 if (bit (this_instr
, 20) == 0)
1579 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1585 /* Load/store multiple. */
1586 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1592 /* Branch and branch with link. */
1597 /* Coprocessor transfers or SWIs can not affect PC. */
1601 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1605 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1609 arm_instruction_restores_sp (unsigned int insn
)
1611 if (bits (insn
, 28, 31) != INST_NV
)
1613 if ((insn
& 0x0df0f000) == 0x0080d000
1614 /* ADD SP (register or immediate). */
1615 || (insn
& 0x0df0f000) == 0x0040d000
1616 /* SUB SP (register or immediate). */
1617 || (insn
& 0x0ffffff0) == 0x01a0d000
1619 || (insn
& 0x0fff0000) == 0x08bd0000
1621 || (insn
& 0x0fff0000) == 0x049d0000)
1622 /* POP of a single register. */
1629 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1630 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1631 fill it in. Return the first address not recognized as a prologue
1634 We recognize all the instructions typically found in ARM prologues,
1635 plus harmless instructions which can be skipped (either for analysis
1636 purposes, or a more restrictive set that can be skipped when finding
1637 the end of the prologue). */
1640 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1641 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1642 struct arm_prologue_cache
*cache
)
1644 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1645 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1647 CORE_ADDR offset
, current_pc
;
1648 pv_t regs
[ARM_FPS_REGNUM
];
1649 struct pv_area
*stack
;
1650 struct cleanup
*back_to
;
1651 CORE_ADDR unrecognized_pc
= 0;
1653 /* Search the prologue looking for instructions that set up the
1654 frame pointer, adjust the stack pointer, and save registers.
1656 Be careful, however, and if it doesn't look like a prologue,
1657 don't try to scan it. If, for instance, a frameless function
1658 begins with stmfd sp!, then we will tell ourselves there is
1659 a frame, which will confuse stack traceback, as well as "finish"
1660 and other operations that rely on a knowledge of the stack
1663 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1664 regs
[regno
] = pv_register (regno
, 0);
1665 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1666 back_to
= make_cleanup_free_pv_area (stack
);
1668 for (current_pc
= prologue_start
;
1669 current_pc
< prologue_end
;
1673 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1675 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1677 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1680 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1681 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1683 unsigned imm
= insn
& 0xff; /* immediate value */
1684 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1685 int rd
= bits (insn
, 12, 15);
1686 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1687 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1690 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1691 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1693 unsigned imm
= insn
& 0xff; /* immediate value */
1694 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1695 int rd
= bits (insn
, 12, 15);
1696 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1697 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1700 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1703 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1705 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1706 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1707 regs
[bits (insn
, 12, 15)]);
1710 else if ((insn
& 0xffff0000) == 0xe92d0000)
1711 /* stmfd sp!, {..., fp, ip, lr, pc}
1713 stmfd sp!, {a1, a2, a3, a4} */
1715 int mask
= insn
& 0xffff;
1717 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1720 /* Calculate offsets of saved registers. */
1721 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1722 if (mask
& (1 << regno
))
1725 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1726 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1729 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1730 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1731 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1733 /* No need to add this to saved_regs -- it's just an arg reg. */
1736 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1737 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1738 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1740 /* No need to add this to saved_regs -- it's just an arg reg. */
1743 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1745 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1747 /* No need to add this to saved_regs -- it's just arg regs. */
1750 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1752 unsigned imm
= insn
& 0xff; /* immediate value */
1753 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1754 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1755 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1757 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1759 unsigned imm
= insn
& 0xff; /* immediate value */
1760 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1761 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1762 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1764 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1766 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1768 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1771 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1772 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1773 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1775 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1777 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1779 int n_saved_fp_regs
;
1780 unsigned int fp_start_reg
, fp_bound_reg
;
1782 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1785 if ((insn
& 0x800) == 0x800) /* N0 is set */
1787 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1788 n_saved_fp_regs
= 3;
1790 n_saved_fp_regs
= 1;
1794 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1795 n_saved_fp_regs
= 2;
1797 n_saved_fp_regs
= 4;
1800 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1801 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1802 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1804 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1805 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1806 regs
[fp_start_reg
++]);
1809 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1811 /* Allow some special function calls when skipping the
1812 prologue; GCC generates these before storing arguments to
1814 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1816 if (skip_prologue_function (gdbarch
, dest
, 0))
1821 else if ((insn
& 0xf0000000) != 0xe0000000)
1822 break; /* Condition not true, exit early. */
1823 else if (arm_instruction_changes_pc (insn
))
1824 /* Don't scan past anything that might change control flow. */
1826 else if (arm_instruction_restores_sp (insn
))
1828 /* Don't scan past the epilogue. */
1831 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1832 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1833 /* Ignore block loads from the stack, potentially copying
1834 parameters from memory. */
1836 else if ((insn
& 0xfc500000) == 0xe4100000
1837 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1838 /* Similarly ignore single loads from the stack. */
1840 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1841 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1842 register instead of the stack. */
1846 /* The optimizer might shove anything into the prologue, if
1847 we build up cache (cache != NULL) from scanning prologue,
1848 we just skip what we don't recognize and scan further to
1849 make cache as complete as possible. However, if we skip
1850 prologue, we'll stop immediately on unrecognized
1852 unrecognized_pc
= current_pc
;
1860 if (unrecognized_pc
== 0)
1861 unrecognized_pc
= current_pc
;
1865 int framereg
, framesize
;
1867 /* The frame size is just the distance from the frame register
1868 to the original stack pointer. */
1869 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1871 /* Frame pointer is fp. */
1872 framereg
= ARM_FP_REGNUM
;
1873 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1877 /* Try the stack pointer... this is a bit desperate. */
1878 framereg
= ARM_SP_REGNUM
;
1879 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1882 cache
->framereg
= framereg
;
1883 cache
->framesize
= framesize
;
1885 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1886 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1887 cache
->saved_regs
[regno
].addr
= offset
;
1891 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1892 paddress (gdbarch
, unrecognized_pc
));
1894 do_cleanups (back_to
);
1895 return unrecognized_pc
;
1899 arm_scan_prologue (struct frame_info
*this_frame
,
1900 struct arm_prologue_cache
*cache
)
1902 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1903 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1905 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1906 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1907 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1908 pv_t regs
[ARM_FPS_REGNUM
];
1909 struct pv_area
*stack
;
1910 struct cleanup
*back_to
;
1913 /* Assume there is no frame until proven otherwise. */
1914 cache
->framereg
= ARM_SP_REGNUM
;
1915 cache
->framesize
= 0;
1917 /* Check for Thumb prologue. */
1918 if (arm_frame_is_thumb (this_frame
))
1920 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1924 /* Find the function prologue. If we can't find the function in
1925 the symbol table, peek in the stack frame to find the PC. */
1926 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1929 /* One way to find the end of the prologue (which works well
1930 for unoptimized code) is to do the following:
1932 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1935 prologue_end = prev_pc;
1936 else if (sal.end < prologue_end)
1937 prologue_end = sal.end;
1939 This mechanism is very accurate so long as the optimizer
1940 doesn't move any instructions from the function body into the
1941 prologue. If this happens, sal.end will be the last
1942 instruction in the first hunk of prologue code just before
1943 the first instruction that the scheduler has moved from
1944 the body to the prologue.
1946 In order to make sure that we scan all of the prologue
1947 instructions, we use a slightly less accurate mechanism which
1948 may scan more than necessary. To help compensate for this
1949 lack of accuracy, the prologue scanning loop below contains
1950 several clauses which'll cause the loop to terminate early if
1951 an implausible prologue instruction is encountered.
1957 is a suitable endpoint since it accounts for the largest
1958 possible prologue plus up to five instructions inserted by
1961 if (prologue_end
> prologue_start
+ 64)
1963 prologue_end
= prologue_start
+ 64; /* See above. */
1968 /* We have no symbol information. Our only option is to assume this
1969 function has a standard stack frame and the normal frame register.
1970 Then, we can find the value of our frame pointer on entrance to
1971 the callee (or at the present moment if this is the innermost frame).
1972 The value stored there should be the address of the stmfd + 8. */
1973 CORE_ADDR frame_loc
;
1974 LONGEST return_value
;
1976 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1977 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1981 prologue_start
= gdbarch_addr_bits_remove
1982 (gdbarch
, return_value
) - 8;
1983 prologue_end
= prologue_start
+ 64; /* See above. */
1987 if (prev_pc
< prologue_end
)
1988 prologue_end
= prev_pc
;
1990 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1993 static struct arm_prologue_cache
*
1994 arm_make_prologue_cache (struct frame_info
*this_frame
)
1997 struct arm_prologue_cache
*cache
;
1998 CORE_ADDR unwound_fp
;
2000 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2001 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2003 arm_scan_prologue (this_frame
, cache
);
2005 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2006 if (unwound_fp
== 0)
2009 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2011 /* Calculate actual addresses of saved registers using offsets
2012 determined by arm_scan_prologue. */
2013 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2014 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2015 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2020 /* Implementation of the stop_reason hook for arm_prologue frames. */
2022 static enum unwind_stop_reason
2023 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
2026 struct arm_prologue_cache
*cache
;
2029 if (*this_cache
== NULL
)
2030 *this_cache
= arm_make_prologue_cache (this_frame
);
2031 cache
= *this_cache
;
2033 /* This is meant to halt the backtrace at "_start". */
2034 pc
= get_frame_pc (this_frame
);
2035 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2036 return UNWIND_OUTERMOST
;
2038 /* If we've hit a wall, stop. */
2039 if (cache
->prev_sp
== 0)
2040 return UNWIND_OUTERMOST
;
2042 return UNWIND_NO_REASON
;
2045 /* Our frame ID for a normal frame is the current function's starting PC
2046 and the caller's SP when we were called. */
2049 arm_prologue_this_id (struct frame_info
*this_frame
,
2051 struct frame_id
*this_id
)
2053 struct arm_prologue_cache
*cache
;
2057 if (*this_cache
== NULL
)
2058 *this_cache
= arm_make_prologue_cache (this_frame
);
2059 cache
= *this_cache
;
2061 /* Use function start address as part of the frame ID. If we cannot
2062 identify the start address (due to missing symbol information),
2063 fall back to just using the current PC. */
2064 pc
= get_frame_pc (this_frame
);
2065 func
= get_frame_func (this_frame
);
2069 id
= frame_id_build (cache
->prev_sp
, func
);
2073 static struct value
*
2074 arm_prologue_prev_register (struct frame_info
*this_frame
,
2078 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2079 struct arm_prologue_cache
*cache
;
2081 if (*this_cache
== NULL
)
2082 *this_cache
= arm_make_prologue_cache (this_frame
);
2083 cache
= *this_cache
;
2085 /* If we are asked to unwind the PC, then we need to return the LR
2086 instead. The prologue may save PC, but it will point into this
2087 frame's prologue, not the next frame's resume location. Also
2088 strip the saved T bit. A valid LR may have the low bit set, but
2089 a valid PC never does. */
2090 if (prev_regnum
== ARM_PC_REGNUM
)
2094 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2095 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2096 arm_addr_bits_remove (gdbarch
, lr
));
2099 /* SP is generally not saved to the stack, but this frame is
2100 identified by the next frame's stack pointer at the time of the call.
2101 The value was already reconstructed into PREV_SP. */
2102 if (prev_regnum
== ARM_SP_REGNUM
)
2103 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2105 /* The CPSR may have been changed by the call instruction and by the
2106 called function. The only bit we can reconstruct is the T bit,
2107 by checking the low bit of LR as of the call. This is a reliable
2108 indicator of Thumb-ness except for some ARM v4T pre-interworking
2109 Thumb code, which could get away with a clear low bit as long as
2110 the called function did not use bx. Guess that all other
2111 bits are unchanged; the condition flags are presumably lost,
2112 but the processor status is likely valid. */
2113 if (prev_regnum
== ARM_PS_REGNUM
)
2116 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2118 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2119 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2120 if (IS_THUMB_ADDR (lr
))
2124 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2127 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2131 struct frame_unwind arm_prologue_unwind
= {
2133 arm_prologue_unwind_stop_reason
,
2134 arm_prologue_this_id
,
2135 arm_prologue_prev_register
,
2137 default_frame_sniffer
2140 /* Maintain a list of ARM exception table entries per objfile, similar to the
2141 list of mapping symbols. We only cache entries for standard ARM-defined
2142 personality routines; the cache will contain only the frame unwinding
2143 instructions associated with the entry (not the descriptors). */
2145 static const struct objfile_data
*arm_exidx_data_key
;
2147 struct arm_exidx_entry
2152 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2153 DEF_VEC_O(arm_exidx_entry_s
);
2155 struct arm_exidx_data
2157 VEC(arm_exidx_entry_s
) **section_maps
;
2161 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2163 struct arm_exidx_data
*data
= arg
;
2166 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2167 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2171 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2172 const struct arm_exidx_entry
*rhs
)
2174 return lhs
->addr
< rhs
->addr
;
2177 static struct obj_section
*
2178 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2180 struct obj_section
*osect
;
2182 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2183 if (bfd_get_section_flags (objfile
->obfd
,
2184 osect
->the_bfd_section
) & SEC_ALLOC
)
2186 bfd_vma start
, size
;
2187 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2188 size
= bfd_get_section_size (osect
->the_bfd_section
);
2190 if (start
<= vma
&& vma
< start
+ size
)
2197 /* Parse contents of exception table and exception index sections
2198 of OBJFILE, and fill in the exception table entry cache.
2200 For each entry that refers to a standard ARM-defined personality
2201 routine, extract the frame unwinding instructions (from either
2202 the index or the table section). The unwinding instructions
2204 - extracting them from the rest of the table data
2205 - converting to host endianness
2206 - appending the implicit 0xb0 ("Finish") code
2208 The extracted and normalized instructions are stored for later
2209 retrieval by the arm_find_exidx_entry routine. */
2212 arm_exidx_new_objfile (struct objfile
*objfile
)
2214 struct cleanup
*cleanups
;
2215 struct arm_exidx_data
*data
;
2216 asection
*exidx
, *extab
;
2217 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2218 bfd_size_type exidx_size
= 0, extab_size
= 0;
2219 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2222 /* If we've already touched this file, do nothing. */
2223 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2225 cleanups
= make_cleanup (null_cleanup
, NULL
);
2227 /* Read contents of exception table and index. */
2228 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2231 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2232 exidx_size
= bfd_get_section_size (exidx
);
2233 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2234 make_cleanup (xfree
, exidx_data
);
2236 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2237 exidx_data
, 0, exidx_size
))
2239 do_cleanups (cleanups
);
2244 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2247 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2248 extab_size
= bfd_get_section_size (extab
);
2249 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2250 make_cleanup (xfree
, extab_data
);
2252 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2253 extab_data
, 0, extab_size
))
2255 do_cleanups (cleanups
);
2260 /* Allocate exception table data structure. */
2261 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2262 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2263 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2264 objfile
->obfd
->section_count
,
2265 VEC(arm_exidx_entry_s
) *);
2267 /* Fill in exception table. */
2268 for (i
= 0; i
< exidx_size
/ 8; i
++)
2270 struct arm_exidx_entry new_exidx_entry
;
2271 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2272 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2273 bfd_vma addr
= 0, word
= 0;
2274 int n_bytes
= 0, n_words
= 0;
2275 struct obj_section
*sec
;
2276 gdb_byte
*entry
= NULL
;
2278 /* Extract address of start of function. */
2279 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2280 idx
+= exidx_vma
+ i
* 8;
2282 /* Find section containing function and compute section offset. */
2283 sec
= arm_obj_section_from_vma (objfile
, idx
);
2286 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2288 /* Determine address of exception table entry. */
2291 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2293 else if ((val
& 0xff000000) == 0x80000000)
2295 /* Exception table entry embedded in .ARM.exidx
2296 -- must be short form. */
2300 else if (!(val
& 0x80000000))
2302 /* Exception table entry in .ARM.extab. */
2303 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2304 addr
+= exidx_vma
+ i
* 8 + 4;
2306 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2308 word
= bfd_h_get_32 (objfile
->obfd
,
2309 extab_data
+ addr
- extab_vma
);
2312 if ((word
& 0xff000000) == 0x80000000)
2317 else if ((word
& 0xff000000) == 0x81000000
2318 || (word
& 0xff000000) == 0x82000000)
2322 n_words
= ((word
>> 16) & 0xff);
2324 else if (!(word
& 0x80000000))
2327 struct obj_section
*pers_sec
;
2328 int gnu_personality
= 0;
2330 /* Custom personality routine. */
2331 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2332 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2334 /* Check whether we've got one of the variants of the
2335 GNU personality routines. */
2336 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2339 static const char *personality
[] =
2341 "__gcc_personality_v0",
2342 "__gxx_personality_v0",
2343 "__gcj_personality_v0",
2344 "__gnu_objc_personality_v0",
2348 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2351 for (k
= 0; personality
[k
]; k
++)
2352 if (lookup_minimal_symbol_by_pc_name
2353 (pc
, personality
[k
], objfile
))
2355 gnu_personality
= 1;
2360 /* If so, the next word contains a word count in the high
2361 byte, followed by the same unwind instructions as the
2362 pre-defined forms. */
2364 && addr
+ 4 <= extab_vma
+ extab_size
)
2366 word
= bfd_h_get_32 (objfile
->obfd
,
2367 extab_data
+ addr
- extab_vma
);
2370 n_words
= ((word
>> 24) & 0xff);
2376 /* Sanity check address. */
2378 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2379 n_words
= n_bytes
= 0;
2381 /* The unwind instructions reside in WORD (only the N_BYTES least
2382 significant bytes are valid), followed by N_WORDS words in the
2383 extab section starting at ADDR. */
2384 if (n_bytes
|| n_words
)
2387 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2388 n_bytes
+ n_words
* 4 + 1);
2391 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2395 word
= bfd_h_get_32 (objfile
->obfd
,
2396 extab_data
+ addr
- extab_vma
);
2399 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2400 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2401 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2402 *p
++ = (gdb_byte
) (word
& 0xff);
2405 /* Implied "Finish" to terminate the list. */
2409 /* Push entry onto vector. They are guaranteed to always
2410 appear in order of increasing addresses. */
2411 new_exidx_entry
.addr
= idx
;
2412 new_exidx_entry
.entry
= entry
;
2413 VEC_safe_push (arm_exidx_entry_s
,
2414 data
->section_maps
[sec
->the_bfd_section
->index
],
2418 do_cleanups (cleanups
);
2421 /* Search for the exception table entry covering MEMADDR. If one is found,
2422 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2423 set *START to the start of the region covered by this entry. */
2426 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2428 struct obj_section
*sec
;
2430 sec
= find_pc_section (memaddr
);
2433 struct arm_exidx_data
*data
;
2434 VEC(arm_exidx_entry_s
) *map
;
2435 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2438 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2441 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2442 if (!VEC_empty (arm_exidx_entry_s
, map
))
2444 struct arm_exidx_entry
*map_sym
;
2446 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2447 arm_compare_exidx_entries
);
2449 /* VEC_lower_bound finds the earliest ordered insertion
2450 point. If the following symbol starts at this exact
2451 address, we use that; otherwise, the preceding
2452 exception table entry covers this address. */
2453 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2455 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2456 if (map_sym
->addr
== map_key
.addr
)
2459 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2460 return map_sym
->entry
;
2466 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2468 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2469 return map_sym
->entry
;
2478 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2479 instruction list from the ARM exception table entry ENTRY, allocate and
2480 return a prologue cache structure describing how to unwind this frame.
2482 Return NULL if the unwinding instruction list contains a "spare",
2483 "reserved" or "refuse to unwind" instruction as defined in section
2484 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2485 for the ARM Architecture" document. */
2487 static struct arm_prologue_cache
*
2488 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2493 struct arm_prologue_cache
*cache
;
2494 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2495 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2501 /* Whenever we reload SP, we actually have to retrieve its
2502 actual value in the current frame. */
2505 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2507 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2508 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2512 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2513 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2519 /* Decode next unwind instruction. */
2522 if ((insn
& 0xc0) == 0)
2524 int offset
= insn
& 0x3f;
2525 vsp
+= (offset
<< 2) + 4;
2527 else if ((insn
& 0xc0) == 0x40)
2529 int offset
= insn
& 0x3f;
2530 vsp
-= (offset
<< 2) + 4;
2532 else if ((insn
& 0xf0) == 0x80)
2534 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2537 /* The special case of an all-zero mask identifies
2538 "Refuse to unwind". We return NULL to fall back
2539 to the prologue analyzer. */
2543 /* Pop registers r4..r15 under mask. */
2544 for (i
= 0; i
< 12; i
++)
2545 if (mask
& (1 << i
))
2547 cache
->saved_regs
[4 + i
].addr
= vsp
;
2551 /* Special-case popping SP -- we need to reload vsp. */
2552 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2555 else if ((insn
& 0xf0) == 0x90)
2557 int reg
= insn
& 0xf;
2559 /* Reserved cases. */
2560 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2563 /* Set SP from another register and mark VSP for reload. */
2564 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2567 else if ((insn
& 0xf0) == 0xa0)
2569 int count
= insn
& 0x7;
2570 int pop_lr
= (insn
& 0x8) != 0;
2573 /* Pop r4..r[4+count]. */
2574 for (i
= 0; i
<= count
; i
++)
2576 cache
->saved_regs
[4 + i
].addr
= vsp
;
2580 /* If indicated by flag, pop LR as well. */
2583 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2587 else if (insn
== 0xb0)
2589 /* We could only have updated PC by popping into it; if so, it
2590 will show up as address. Otherwise, copy LR into PC. */
2591 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2592 cache
->saved_regs
[ARM_PC_REGNUM
]
2593 = cache
->saved_regs
[ARM_LR_REGNUM
];
2598 else if (insn
== 0xb1)
2600 int mask
= *entry
++;
2603 /* All-zero mask and mask >= 16 is "spare". */
2604 if (mask
== 0 || mask
>= 16)
2607 /* Pop r0..r3 under mask. */
2608 for (i
= 0; i
< 4; i
++)
2609 if (mask
& (1 << i
))
2611 cache
->saved_regs
[i
].addr
= vsp
;
2615 else if (insn
== 0xb2)
2617 ULONGEST offset
= 0;
2622 offset
|= (*entry
& 0x7f) << shift
;
2625 while (*entry
++ & 0x80);
2627 vsp
+= 0x204 + (offset
<< 2);
2629 else if (insn
== 0xb3)
2631 int start
= *entry
>> 4;
2632 int count
= (*entry
++) & 0xf;
2635 /* Only registers D0..D15 are valid here. */
2636 if (start
+ count
>= 16)
2639 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2640 for (i
= 0; i
<= count
; i
++)
2642 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2646 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2649 else if ((insn
& 0xf8) == 0xb8)
2651 int count
= insn
& 0x7;
2654 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2655 for (i
= 0; i
<= count
; i
++)
2657 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2661 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2664 else if (insn
== 0xc6)
2666 int start
= *entry
>> 4;
2667 int count
= (*entry
++) & 0xf;
2670 /* Only registers WR0..WR15 are valid. */
2671 if (start
+ count
>= 16)
2674 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2675 for (i
= 0; i
<= count
; i
++)
2677 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2681 else if (insn
== 0xc7)
2683 int mask
= *entry
++;
2686 /* All-zero mask and mask >= 16 is "spare". */
2687 if (mask
== 0 || mask
>= 16)
2690 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2691 for (i
= 0; i
< 4; i
++)
2692 if (mask
& (1 << i
))
2694 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2698 else if ((insn
& 0xf8) == 0xc0)
2700 int count
= insn
& 0x7;
2703 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2704 for (i
= 0; i
<= count
; i
++)
2706 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2710 else if (insn
== 0xc8)
2712 int start
= *entry
>> 4;
2713 int count
= (*entry
++) & 0xf;
2716 /* Only registers D0..D31 are valid. */
2717 if (start
+ count
>= 16)
2720 /* Pop VFP double-precision registers
2721 D[16+start]..D[16+start+count]. */
2722 for (i
= 0; i
<= count
; i
++)
2724 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2728 else if (insn
== 0xc9)
2730 int start
= *entry
>> 4;
2731 int count
= (*entry
++) & 0xf;
2734 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2735 for (i
= 0; i
<= count
; i
++)
2737 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2741 else if ((insn
& 0xf8) == 0xd0)
2743 int count
= insn
& 0x7;
2746 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2747 for (i
= 0; i
<= count
; i
++)
2749 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2755 /* Everything else is "spare". */
2760 /* If we restore SP from a register, assume this was the frame register.
2761 Otherwise just fall back to SP as frame register. */
2762 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2763 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2765 cache
->framereg
= ARM_SP_REGNUM
;
2767 /* Determine offset to previous frame. */
2769 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2771 /* We already got the previous SP. */
2772 cache
->prev_sp
= vsp
;
2777 /* Unwinding via ARM exception table entries. Note that the sniffer
2778 already computes a filled-in prologue cache, which is then used
2779 with the same arm_prologue_this_id and arm_prologue_prev_register
2780 routines also used for prologue-parsing based unwinding. */
2783 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2784 struct frame_info
*this_frame
,
2785 void **this_prologue_cache
)
2787 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2788 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2789 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2790 struct arm_prologue_cache
*cache
;
2793 /* See if we have an ARM exception table entry covering this address. */
2794 addr_in_block
= get_frame_address_in_block (this_frame
);
2795 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2799 /* The ARM exception table does not describe unwind information
2800 for arbitrary PC values, but is guaranteed to be correct only
2801 at call sites. We have to decide here whether we want to use
2802 ARM exception table information for this frame, or fall back
2803 to using prologue parsing. (Note that if we have DWARF CFI,
2804 this sniffer isn't even called -- CFI is always preferred.)
2806 Before we make this decision, however, we check whether we
2807 actually have *symbol* information for the current frame.
2808 If not, prologue parsing would not work anyway, so we might
2809 as well use the exception table and hope for the best. */
2810 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2814 /* If the next frame is "normal", we are at a call site in this
2815 frame, so exception information is guaranteed to be valid. */
2816 if (get_next_frame (this_frame
)
2817 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2820 /* We also assume exception information is valid if we're currently
2821 blocked in a system call. The system library is supposed to
2822 ensure this, so that e.g. pthread cancellation works. */
2823 if (arm_frame_is_thumb (this_frame
))
2827 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2828 byte_order_for_code
, &insn
)
2829 && (insn
& 0xff00) == 0xdf00 /* svc */)
2836 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2837 byte_order_for_code
, &insn
)
2838 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2842 /* Bail out if we don't know that exception information is valid. */
2846 /* The ARM exception index does not mark the *end* of the region
2847 covered by the entry, and some functions will not have any entry.
2848 To correctly recognize the end of the covered region, the linker
2849 should have inserted dummy records with a CANTUNWIND marker.
2851 Unfortunately, current versions of GNU ld do not reliably do
2852 this, and thus we may have found an incorrect entry above.
2853 As a (temporary) sanity check, we only use the entry if it
2854 lies *within* the bounds of the function. Note that this check
2855 might reject perfectly valid entries that just happen to cover
2856 multiple functions; therefore this check ought to be removed
2857 once the linker is fixed. */
2858 if (func_start
> exidx_region
)
2862 /* Decode the list of unwinding instructions into a prologue cache.
2863 Note that this may fail due to e.g. a "refuse to unwind" code. */
2864 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2868 *this_prologue_cache
= cache
;
2872 struct frame_unwind arm_exidx_unwind
= {
2874 default_frame_unwind_stop_reason
,
2875 arm_prologue_this_id
,
2876 arm_prologue_prev_register
,
2878 arm_exidx_unwind_sniffer
2881 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2882 trampoline, return the target PC. Otherwise return 0.
2884 void call0a (char c, short s, int i, long l) {}
2888 (*pointer_to_call0a) (c, s, i, l);
2891 Instead of calling a stub library function _call_via_xx (xx is
2892 the register name), GCC may inline the trampoline in the object
2893 file as below (register r2 has the address of call0a).
2896 .type main, %function
2905 The trampoline 'bx r2' doesn't belong to main. */
2908 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2910 /* The heuristics of recognizing such trampoline is that FRAME is
2911 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2912 if (arm_frame_is_thumb (frame
))
2916 if (target_read_memory (pc
, buf
, 2) == 0)
2918 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2919 enum bfd_endian byte_order_for_code
2920 = gdbarch_byte_order_for_code (gdbarch
);
2922 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2924 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2927 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2929 /* Clear the LSB so that gdb core sets step-resume
2930 breakpoint at the right address. */
2931 return UNMAKE_THUMB_ADDR (dest
);
2939 static struct arm_prologue_cache
*
2940 arm_make_stub_cache (struct frame_info
*this_frame
)
2942 struct arm_prologue_cache
*cache
;
2944 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2945 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2947 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2952 /* Our frame ID for a stub frame is the current SP and LR. */
2955 arm_stub_this_id (struct frame_info
*this_frame
,
2957 struct frame_id
*this_id
)
2959 struct arm_prologue_cache
*cache
;
2961 if (*this_cache
== NULL
)
2962 *this_cache
= arm_make_stub_cache (this_frame
);
2963 cache
= *this_cache
;
2965 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2969 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2970 struct frame_info
*this_frame
,
2971 void **this_prologue_cache
)
2973 CORE_ADDR addr_in_block
;
2975 CORE_ADDR pc
, start_addr
;
2978 addr_in_block
= get_frame_address_in_block (this_frame
);
2979 pc
= get_frame_pc (this_frame
);
2980 if (in_plt_section (addr_in_block
)
2981 /* We also use the stub winder if the target memory is unreadable
2982 to avoid having the prologue unwinder trying to read it. */
2983 || target_read_memory (pc
, dummy
, 4) != 0)
2986 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2987 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2993 struct frame_unwind arm_stub_unwind
= {
2995 default_frame_unwind_stop_reason
,
2997 arm_prologue_prev_register
,
2999 arm_stub_unwind_sniffer
3002 /* Put here the code to store, into CACHE->saved_regs, the addresses
3003 of the saved registers of frame described by THIS_FRAME. CACHE is
3006 static struct arm_prologue_cache
*
3007 arm_m_exception_cache (struct frame_info
*this_frame
)
3009 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3010 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3011 struct arm_prologue_cache
*cache
;
3012 CORE_ADDR unwound_sp
;
3015 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3016 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3018 unwound_sp
= get_frame_register_unsigned (this_frame
,
3021 /* The hardware saves eight 32-bit words, comprising xPSR,
3022 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3023 "B1.5.6 Exception entry behavior" in
3024 "ARMv7-M Architecture Reference Manual". */
3025 cache
->saved_regs
[0].addr
= unwound_sp
;
3026 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
3027 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
3028 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
3029 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
3030 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
3031 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
3032 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
3034 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3035 aligner between the top of the 32-byte stack frame and the
3036 previous context's stack pointer. */
3037 cache
->prev_sp
= unwound_sp
+ 32;
3038 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
3039 && (xpsr
& (1 << 9)) != 0)
3040 cache
->prev_sp
+= 4;
3045 /* Implementation of function hook 'this_id' in
3046 'struct frame_uwnind'. */
3049 arm_m_exception_this_id (struct frame_info
*this_frame
,
3051 struct frame_id
*this_id
)
3053 struct arm_prologue_cache
*cache
;
3055 if (*this_cache
== NULL
)
3056 *this_cache
= arm_m_exception_cache (this_frame
);
3057 cache
= *this_cache
;
3059 /* Our frame ID for a stub frame is the current SP and LR. */
3060 *this_id
= frame_id_build (cache
->prev_sp
,
3061 get_frame_pc (this_frame
));
3064 /* Implementation of function hook 'prev_register' in
3065 'struct frame_uwnind'. */
3067 static struct value
*
3068 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3072 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3073 struct arm_prologue_cache
*cache
;
3075 if (*this_cache
== NULL
)
3076 *this_cache
= arm_m_exception_cache (this_frame
);
3077 cache
= *this_cache
;
3079 /* The value was already reconstructed into PREV_SP. */
3080 if (prev_regnum
== ARM_SP_REGNUM
)
3081 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3084 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3088 /* Implementation of function hook 'sniffer' in
3089 'struct frame_uwnind'. */
3092 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3093 struct frame_info
*this_frame
,
3094 void **this_prologue_cache
)
3096 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3098 /* No need to check is_m; this sniffer is only registered for
3099 M-profile architectures. */
3101 /* Exception frames return to one of these magic PCs. Other values
3102 are not defined as of v7-M. See details in "B1.5.8 Exception
3103 return behavior" in "ARMv7-M Architecture Reference Manual". */
3104 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3105 || this_pc
== 0xfffffffd)
3111 /* Frame unwinder for M-profile exceptions. */
3113 struct frame_unwind arm_m_exception_unwind
=
3116 default_frame_unwind_stop_reason
,
3117 arm_m_exception_this_id
,
3118 arm_m_exception_prev_register
,
3120 arm_m_exception_unwind_sniffer
3124 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3126 struct arm_prologue_cache
*cache
;
3128 if (*this_cache
== NULL
)
3129 *this_cache
= arm_make_prologue_cache (this_frame
);
3130 cache
= *this_cache
;
3132 return cache
->prev_sp
- cache
->framesize
;
3135 struct frame_base arm_normal_base
= {
3136 &arm_prologue_unwind
,
3137 arm_normal_frame_base
,
3138 arm_normal_frame_base
,
3139 arm_normal_frame_base
3142 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3143 dummy frame. The frame ID's base needs to match the TOS value
3144 saved by save_dummy_frame_tos() and returned from
3145 arm_push_dummy_call, and the PC needs to match the dummy frame's
3148 static struct frame_id
3149 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3151 return frame_id_build (get_frame_register_unsigned (this_frame
,
3153 get_frame_pc (this_frame
));
3156 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3157 be used to construct the previous frame's ID, after looking up the
3158 containing function). */
3161 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3164 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3165 return arm_addr_bits_remove (gdbarch
, pc
);
3169 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3171 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3174 static struct value
*
3175 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3178 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3180 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3185 /* The PC is normally copied from the return column, which
3186 describes saves of LR. However, that version may have an
3187 extra bit set to indicate Thumb state. The bit is not
3189 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3190 return frame_unwind_got_constant (this_frame
, regnum
,
3191 arm_addr_bits_remove (gdbarch
, lr
));
3194 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3195 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3196 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3197 if (IS_THUMB_ADDR (lr
))
3201 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3204 internal_error (__FILE__
, __LINE__
,
3205 _("Unexpected register %d"), regnum
);
3210 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3211 struct dwarf2_frame_state_reg
*reg
,
3212 struct frame_info
*this_frame
)
3218 reg
->how
= DWARF2_FRAME_REG_FN
;
3219 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3222 reg
->how
= DWARF2_FRAME_REG_CFA
;
3227 /* Implement the stack_frame_destroyed_p gdbarch method. */
3230 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3232 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3233 unsigned int insn
, insn2
;
3234 int found_return
= 0, found_stack_adjust
= 0;
3235 CORE_ADDR func_start
, func_end
;
3239 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3242 /* The epilogue is a sequence of instructions along the following lines:
3244 - add stack frame size to SP or FP
3245 - [if frame pointer used] restore SP from FP
3246 - restore registers from SP [may include PC]
3247 - a return-type instruction [if PC wasn't already restored]
3249 In a first pass, we scan forward from the current PC and verify the
3250 instructions we find as compatible with this sequence, ending in a
3253 However, this is not sufficient to distinguish indirect function calls
3254 within a function from indirect tail calls in the epilogue in some cases.
3255 Therefore, if we didn't already find any SP-changing instruction during
3256 forward scan, we add a backward scanning heuristic to ensure we actually
3257 are in the epilogue. */
3260 while (scan_pc
< func_end
&& !found_return
)
3262 if (target_read_memory (scan_pc
, buf
, 2))
3266 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3268 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3270 else if (insn
== 0x46f7) /* mov pc, lr */
3272 else if (thumb_instruction_restores_sp (insn
))
3274 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3277 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3279 if (target_read_memory (scan_pc
, buf
, 2))
3283 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3285 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3287 if (insn2
& 0x8000) /* <registers> include PC. */
3290 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3291 && (insn2
& 0x0fff) == 0x0b04)
3293 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3296 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3297 && (insn2
& 0x0e00) == 0x0a00)
3309 /* Since any instruction in the epilogue sequence, with the possible
3310 exception of return itself, updates the stack pointer, we need to
3311 scan backwards for at most one instruction. Try either a 16-bit or
3312 a 32-bit instruction. This is just a heuristic, so we do not worry
3313 too much about false positives. */
3315 if (pc
- 4 < func_start
)
3317 if (target_read_memory (pc
- 4, buf
, 4))
3320 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3321 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3323 if (thumb_instruction_restores_sp (insn2
))
3324 found_stack_adjust
= 1;
3325 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3326 found_stack_adjust
= 1;
3327 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3328 && (insn2
& 0x0fff) == 0x0b04)
3329 found_stack_adjust
= 1;
3330 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3331 && (insn2
& 0x0e00) == 0x0a00)
3332 found_stack_adjust
= 1;
3334 return found_stack_adjust
;
3337 /* Implement the stack_frame_destroyed_p gdbarch method. */
3340 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3342 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3345 CORE_ADDR func_start
, func_end
;
3347 if (arm_pc_is_thumb (gdbarch
, pc
))
3348 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3350 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3353 /* We are in the epilogue if the previous instruction was a stack
3354 adjustment and the next instruction is a possible return (bx, mov
3355 pc, or pop). We could have to scan backwards to find the stack
3356 adjustment, or forwards to find the return, but this is a decent
3357 approximation. First scan forwards. */
3360 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3361 if (bits (insn
, 28, 31) != INST_NV
)
3363 if ((insn
& 0x0ffffff0) == 0x012fff10)
3366 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3369 else if ((insn
& 0x0fff0000) == 0x08bd0000
3370 && (insn
& 0x0000c000) != 0)
3371 /* POP (LDMIA), including PC or LR. */
3378 /* Scan backwards. This is just a heuristic, so do not worry about
3379 false positives from mode changes. */
3381 if (pc
< func_start
+ 4)
3384 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3385 if (arm_instruction_restores_sp (insn
))
3392 /* When arguments must be pushed onto the stack, they go on in reverse
3393 order. The code below implements a FILO (stack) to do this. */
3398 struct stack_item
*prev
;
3402 static struct stack_item
*
3403 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3405 struct stack_item
*si
;
3406 si
= XNEW (struct stack_item
);
3407 si
->data
= xmalloc (len
);
3410 memcpy (si
->data
, contents
, len
);
3414 static struct stack_item
*
3415 pop_stack_item (struct stack_item
*si
)
3417 struct stack_item
*dead
= si
;
3425 /* Return the alignment (in bytes) of the given type. */
3428 arm_type_align (struct type
*t
)
3434 t
= check_typedef (t
);
3435 switch (TYPE_CODE (t
))
3438 /* Should never happen. */
3439 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3443 case TYPE_CODE_ENUM
:
3447 case TYPE_CODE_RANGE
:
3449 case TYPE_CODE_CHAR
:
3450 case TYPE_CODE_BOOL
:
3451 return TYPE_LENGTH (t
);
3453 case TYPE_CODE_ARRAY
:
3454 case TYPE_CODE_COMPLEX
:
3455 /* TODO: What about vector types? */
3456 return arm_type_align (TYPE_TARGET_TYPE (t
));
3458 case TYPE_CODE_STRUCT
:
3459 case TYPE_CODE_UNION
:
3461 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3463 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3471 /* Possible base types for a candidate for passing and returning in
3474 enum arm_vfp_cprc_base_type
3483 /* The length of one element of base type B. */
3486 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3490 case VFP_CPRC_SINGLE
:
3492 case VFP_CPRC_DOUBLE
:
3494 case VFP_CPRC_VEC64
:
3496 case VFP_CPRC_VEC128
:
3499 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3504 /* The character ('s', 'd' or 'q') for the type of VFP register used
3505 for passing base type B. */
3508 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3512 case VFP_CPRC_SINGLE
:
3514 case VFP_CPRC_DOUBLE
:
3516 case VFP_CPRC_VEC64
:
3518 case VFP_CPRC_VEC128
:
3521 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3526 /* Determine whether T may be part of a candidate for passing and
3527 returning in VFP registers, ignoring the limit on the total number
3528 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3529 classification of the first valid component found; if it is not
3530 VFP_CPRC_UNKNOWN, all components must have the same classification
3531 as *BASE_TYPE. If it is found that T contains a type not permitted
3532 for passing and returning in VFP registers, a type differently
3533 classified from *BASE_TYPE, or two types differently classified
3534 from each other, return -1, otherwise return the total number of
3535 base-type elements found (possibly 0 in an empty structure or
3536 array). Vector types are not currently supported, matching the
3537 generic AAPCS support. */
3540 arm_vfp_cprc_sub_candidate (struct type
*t
,
3541 enum arm_vfp_cprc_base_type
*base_type
)
3543 t
= check_typedef (t
);
3544 switch (TYPE_CODE (t
))
3547 switch (TYPE_LENGTH (t
))
3550 if (*base_type
== VFP_CPRC_UNKNOWN
)
3551 *base_type
= VFP_CPRC_SINGLE
;
3552 else if (*base_type
!= VFP_CPRC_SINGLE
)
3557 if (*base_type
== VFP_CPRC_UNKNOWN
)
3558 *base_type
= VFP_CPRC_DOUBLE
;
3559 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3568 case TYPE_CODE_COMPLEX
:
3569 /* Arguments of complex T where T is one of the types float or
3570 double get treated as if they are implemented as:
3579 switch (TYPE_LENGTH (t
))
3582 if (*base_type
== VFP_CPRC_UNKNOWN
)
3583 *base_type
= VFP_CPRC_SINGLE
;
3584 else if (*base_type
!= VFP_CPRC_SINGLE
)
3589 if (*base_type
== VFP_CPRC_UNKNOWN
)
3590 *base_type
= VFP_CPRC_DOUBLE
;
3591 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3600 case TYPE_CODE_ARRAY
:
3604 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3607 if (TYPE_LENGTH (t
) == 0)
3609 gdb_assert (count
== 0);
3612 else if (count
== 0)
3614 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3615 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3616 return TYPE_LENGTH (t
) / unitlen
;
3620 case TYPE_CODE_STRUCT
:
3625 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3627 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3629 if (sub_count
== -1)
3633 if (TYPE_LENGTH (t
) == 0)
3635 gdb_assert (count
== 0);
3638 else if (count
== 0)
3640 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3641 if (TYPE_LENGTH (t
) != unitlen
* count
)
3646 case TYPE_CODE_UNION
:
3651 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3653 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3655 if (sub_count
== -1)
3657 count
= (count
> sub_count
? count
: sub_count
);
3659 if (TYPE_LENGTH (t
) == 0)
3661 gdb_assert (count
== 0);
3664 else if (count
== 0)
3666 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3667 if (TYPE_LENGTH (t
) != unitlen
* count
)
3679 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3680 if passed to or returned from a non-variadic function with the VFP
3681 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3682 *BASE_TYPE to the base type for T and *COUNT to the number of
3683 elements of that base type before returning. */
3686 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3689 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3690 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3691 if (c
<= 0 || c
> 4)
3698 /* Return 1 if the VFP ABI should be used for passing arguments to and
3699 returning values from a function of type FUNC_TYPE, 0
3703 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3705 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3706 /* Variadic functions always use the base ABI. Assume that functions
3707 without debug info are not variadic. */
3708 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3710 /* The VFP ABI is only supported as a variant of AAPCS. */
3711 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3713 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3716 /* We currently only support passing parameters in integer registers, which
3717 conforms with GCC's default model, and VFP argument passing following
3718 the VFP variant of AAPCS. Several other variants exist and
3719 we should probably support some of them based on the selected ABI. */
3722 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3723 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3724 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3725 CORE_ADDR struct_addr
)
3727 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3731 struct stack_item
*si
= NULL
;
3734 unsigned vfp_regs_free
= (1 << 16) - 1;
3736 /* Determine the type of this function and whether the VFP ABI
3738 ftype
= check_typedef (value_type (function
));
3739 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3740 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3741 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3743 /* Set the return address. For the ARM, the return breakpoint is
3744 always at BP_ADDR. */
3745 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3747 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3749 /* Walk through the list of args and determine how large a temporary
3750 stack is required. Need to take care here as structs may be
3751 passed on the stack, and we have to push them. */
3754 argreg
= ARM_A1_REGNUM
;
3757 /* The struct_return pointer occupies the first parameter
3758 passing register. */
3762 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3763 gdbarch_register_name (gdbarch
, argreg
),
3764 paddress (gdbarch
, struct_addr
));
3765 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3769 for (argnum
= 0; argnum
< nargs
; argnum
++)
3772 struct type
*arg_type
;
3773 struct type
*target_type
;
3774 enum type_code typecode
;
3775 const bfd_byte
*val
;
3777 enum arm_vfp_cprc_base_type vfp_base_type
;
3779 int may_use_core_reg
= 1;
3781 arg_type
= check_typedef (value_type (args
[argnum
]));
3782 len
= TYPE_LENGTH (arg_type
);
3783 target_type
= TYPE_TARGET_TYPE (arg_type
);
3784 typecode
= TYPE_CODE (arg_type
);
3785 val
= value_contents (args
[argnum
]);
3787 align
= arm_type_align (arg_type
);
3788 /* Round alignment up to a whole number of words. */
3789 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3790 /* Different ABIs have different maximum alignments. */
3791 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3793 /* The APCS ABI only requires word alignment. */
3794 align
= INT_REGISTER_SIZE
;
3798 /* The AAPCS requires at most doubleword alignment. */
3799 if (align
> INT_REGISTER_SIZE
* 2)
3800 align
= INT_REGISTER_SIZE
* 2;
3804 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3812 /* Because this is a CPRC it cannot go in a core register or
3813 cause a core register to be skipped for alignment.
3814 Either it goes in VFP registers and the rest of this loop
3815 iteration is skipped for this argument, or it goes on the
3816 stack (and the stack alignment code is correct for this
3818 may_use_core_reg
= 0;
3820 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3821 shift
= unit_length
/ 4;
3822 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3823 for (regno
= 0; regno
< 16; regno
+= shift
)
3824 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3833 vfp_regs_free
&= ~(mask
<< regno
);
3834 reg_scaled
= regno
/ shift
;
3835 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3836 for (i
= 0; i
< vfp_base_count
; i
++)
3840 if (reg_char
== 'q')
3841 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3842 val
+ i
* unit_length
);
3845 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3846 reg_char
, reg_scaled
+ i
);
3847 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3849 regcache_cooked_write (regcache
, regnum
,
3850 val
+ i
* unit_length
);
3857 /* This CPRC could not go in VFP registers, so all VFP
3858 registers are now marked as used. */
3863 /* Push stack padding for dowubleword alignment. */
3864 if (nstack
& (align
- 1))
3866 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3867 nstack
+= INT_REGISTER_SIZE
;
3870 /* Doubleword aligned quantities must go in even register pairs. */
3871 if (may_use_core_reg
3872 && argreg
<= ARM_LAST_ARG_REGNUM
3873 && align
> INT_REGISTER_SIZE
3877 /* If the argument is a pointer to a function, and it is a
3878 Thumb function, create a LOCAL copy of the value and set
3879 the THUMB bit in it. */
3880 if (TYPE_CODE_PTR
== typecode
3881 && target_type
!= NULL
3882 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3884 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3885 if (arm_pc_is_thumb (gdbarch
, regval
))
3887 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3888 store_unsigned_integer (copy
, len
, byte_order
,
3889 MAKE_THUMB_ADDR (regval
));
3894 /* Copy the argument to general registers or the stack in
3895 register-sized pieces. Large arguments are split between
3896 registers and stack. */
3899 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3901 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3903 /* The argument is being passed in a general purpose
3906 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3907 if (byte_order
== BFD_ENDIAN_BIG
)
3908 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3910 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3912 gdbarch_register_name
3914 phex (regval
, INT_REGISTER_SIZE
));
3915 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3920 /* Push the arguments onto the stack. */
3922 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3924 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3925 nstack
+= INT_REGISTER_SIZE
;
3932 /* If we have an odd number of words to push, then decrement the stack
3933 by one word now, so first stack argument will be dword aligned. */
3940 write_memory (sp
, si
->data
, si
->len
);
3941 si
= pop_stack_item (si
);
3944 /* Finally, update teh SP register. */
3945 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3951 /* Always align the frame to an 8-byte boundary. This is required on
3952 some platforms and harmless on the rest. */
3955 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3957 /* Align the stack to eight bytes. */
3958 return sp
& ~ (CORE_ADDR
) 7;
3962 print_fpu_flags (struct ui_file
*file
, int flags
)
3964 if (flags
& (1 << 0))
3965 fputs_filtered ("IVO ", file
);
3966 if (flags
& (1 << 1))
3967 fputs_filtered ("DVZ ", file
);
3968 if (flags
& (1 << 2))
3969 fputs_filtered ("OFL ", file
);
3970 if (flags
& (1 << 3))
3971 fputs_filtered ("UFL ", file
);
3972 if (flags
& (1 << 4))
3973 fputs_filtered ("INX ", file
);
3974 fputc_filtered ('\n', file
);
3977 /* Print interesting information about the floating point processor
3978 (if present) or emulator. */
3980 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3981 struct frame_info
*frame
, const char *args
)
3983 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3986 type
= (status
>> 24) & 127;
3987 if (status
& (1 << 31))
3988 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3990 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3991 /* i18n: [floating point unit] mask */
3992 fputs_filtered (_("mask: "), file
);
3993 print_fpu_flags (file
, status
>> 16);
3994 /* i18n: [floating point unit] flags */
3995 fputs_filtered (_("flags: "), file
);
3996 print_fpu_flags (file
, status
);
3999 /* Construct the ARM extended floating point type. */
4000 static struct type
*
4001 arm_ext_type (struct gdbarch
*gdbarch
)
4003 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4005 if (!tdep
->arm_ext_type
)
4007 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
4008 floatformats_arm_ext
);
4010 return tdep
->arm_ext_type
;
4013 static struct type
*
4014 arm_neon_double_type (struct gdbarch
*gdbarch
)
4016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4018 if (tdep
->neon_double_type
== NULL
)
4020 struct type
*t
, *elem
;
4022 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4024 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4025 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4026 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4027 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4028 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4029 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4030 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4031 append_composite_type_field (t
, "u64", elem
);
4032 elem
= builtin_type (gdbarch
)->builtin_float
;
4033 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4034 elem
= builtin_type (gdbarch
)->builtin_double
;
4035 append_composite_type_field (t
, "f64", elem
);
4037 TYPE_VECTOR (t
) = 1;
4038 TYPE_NAME (t
) = "neon_d";
4039 tdep
->neon_double_type
= t
;
4042 return tdep
->neon_double_type
;
4045 /* FIXME: The vector types are not correctly ordered on big-endian
4046 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4047 bits of d0 - regardless of what unit size is being held in d0. So
4048 the offset of the first uint8 in d0 is 7, but the offset of the
4049 first float is 4. This code works as-is for little-endian
4052 static struct type
*
4053 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4057 if (tdep
->neon_quad_type
== NULL
)
4059 struct type
*t
, *elem
;
4061 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4063 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4064 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4065 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4066 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4067 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4068 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4069 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4070 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4071 elem
= builtin_type (gdbarch
)->builtin_float
;
4072 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4073 elem
= builtin_type (gdbarch
)->builtin_double
;
4074 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4076 TYPE_VECTOR (t
) = 1;
4077 TYPE_NAME (t
) = "neon_q";
4078 tdep
->neon_quad_type
= t
;
4081 return tdep
->neon_quad_type
;
4084 /* Return the GDB type object for the "standard" data type of data in
4087 static struct type
*
4088 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4090 int num_regs
= gdbarch_num_regs (gdbarch
);
4092 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4093 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4094 return builtin_type (gdbarch
)->builtin_float
;
4096 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4097 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4098 return arm_neon_quad_type (gdbarch
);
4100 /* If the target description has register information, we are only
4101 in this function so that we can override the types of
4102 double-precision registers for NEON. */
4103 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4105 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4107 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4108 && TYPE_CODE (t
) == TYPE_CODE_FLT
4109 && gdbarch_tdep (gdbarch
)->have_neon
)
4110 return arm_neon_double_type (gdbarch
);
4115 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4117 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4118 return builtin_type (gdbarch
)->builtin_void
;
4120 return arm_ext_type (gdbarch
);
4122 else if (regnum
== ARM_SP_REGNUM
)
4123 return builtin_type (gdbarch
)->builtin_data_ptr
;
4124 else if (regnum
== ARM_PC_REGNUM
)
4125 return builtin_type (gdbarch
)->builtin_func_ptr
;
4126 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4127 /* These registers are only supported on targets which supply
4128 an XML description. */
4129 return builtin_type (gdbarch
)->builtin_int0
;
4131 return builtin_type (gdbarch
)->builtin_uint32
;
4134 /* Map a DWARF register REGNUM onto the appropriate GDB register
4138 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4140 /* Core integer regs. */
4141 if (reg
>= 0 && reg
<= 15)
4144 /* Legacy FPA encoding. These were once used in a way which
4145 overlapped with VFP register numbering, so their use is
4146 discouraged, but GDB doesn't support the ARM toolchain
4147 which used them for VFP. */
4148 if (reg
>= 16 && reg
<= 23)
4149 return ARM_F0_REGNUM
+ reg
- 16;
4151 /* New assignments for the FPA registers. */
4152 if (reg
>= 96 && reg
<= 103)
4153 return ARM_F0_REGNUM
+ reg
- 96;
4155 /* WMMX register assignments. */
4156 if (reg
>= 104 && reg
<= 111)
4157 return ARM_WCGR0_REGNUM
+ reg
- 104;
4159 if (reg
>= 112 && reg
<= 127)
4160 return ARM_WR0_REGNUM
+ reg
- 112;
4162 if (reg
>= 192 && reg
<= 199)
4163 return ARM_WC0_REGNUM
+ reg
- 192;
4165 /* VFP v2 registers. A double precision value is actually
4166 in d1 rather than s2, but the ABI only defines numbering
4167 for the single precision registers. This will "just work"
4168 in GDB for little endian targets (we'll read eight bytes,
4169 starting in s0 and then progressing to s1), but will be
4170 reversed on big endian targets with VFP. This won't
4171 be a problem for the new Neon quad registers; you're supposed
4172 to use DW_OP_piece for those. */
4173 if (reg
>= 64 && reg
<= 95)
4177 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4178 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4182 /* VFP v3 / Neon registers. This range is also used for VFP v2
4183 registers, except that it now describes d0 instead of s0. */
4184 if (reg
>= 256 && reg
<= 287)
4188 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4189 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4196 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4198 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4201 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4203 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4204 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4206 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4207 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4209 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4210 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4212 if (reg
< NUM_GREGS
)
4213 return SIM_ARM_R0_REGNUM
+ reg
;
4216 if (reg
< NUM_FREGS
)
4217 return SIM_ARM_FP0_REGNUM
+ reg
;
4220 if (reg
< NUM_SREGS
)
4221 return SIM_ARM_FPS_REGNUM
+ reg
;
4224 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4227 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4228 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4229 It is thought that this is is the floating-point register format on
4230 little-endian systems. */
4233 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4234 void *dbl
, int endianess
)
4238 if (endianess
== BFD_ENDIAN_BIG
)
4239 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4241 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4243 floatformat_from_doublest (fmt
, &d
, dbl
);
4247 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4252 floatformat_to_doublest (fmt
, ptr
, &d
);
4253 if (endianess
== BFD_ENDIAN_BIG
)
4254 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4256 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4261 condition_true (unsigned long cond
, unsigned long status_reg
)
4263 if (cond
== INST_AL
|| cond
== INST_NV
)
4269 return ((status_reg
& FLAG_Z
) != 0);
4271 return ((status_reg
& FLAG_Z
) == 0);
4273 return ((status_reg
& FLAG_C
) != 0);
4275 return ((status_reg
& FLAG_C
) == 0);
4277 return ((status_reg
& FLAG_N
) != 0);
4279 return ((status_reg
& FLAG_N
) == 0);
4281 return ((status_reg
& FLAG_V
) != 0);
4283 return ((status_reg
& FLAG_V
) == 0);
4285 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4287 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4289 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4291 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4293 return (((status_reg
& FLAG_Z
) == 0)
4294 && (((status_reg
& FLAG_N
) == 0)
4295 == ((status_reg
& FLAG_V
) == 0)));
4297 return (((status_reg
& FLAG_Z
) != 0)
4298 || (((status_reg
& FLAG_N
) == 0)
4299 != ((status_reg
& FLAG_V
) == 0)));
4304 static unsigned long
4305 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4306 unsigned long pc_val
, unsigned long status_reg
)
4308 unsigned long res
, shift
;
4309 int rm
= bits (inst
, 0, 3);
4310 unsigned long shifttype
= bits (inst
, 5, 6);
4314 int rs
= bits (inst
, 8, 11);
4315 shift
= (rs
== 15 ? pc_val
+ 8
4316 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4319 shift
= bits (inst
, 7, 11);
4321 res
= (rm
== ARM_PC_REGNUM
4322 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4323 : get_frame_register_unsigned (frame
, rm
));
4328 res
= shift
>= 32 ? 0 : res
<< shift
;
4332 res
= shift
>= 32 ? 0 : res
>> shift
;
4338 res
= ((res
& 0x80000000L
)
4339 ? ~((~res
) >> shift
) : res
>> shift
);
4342 case 3: /* ROR/RRX */
4345 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4347 res
= (res
>> shift
) | (res
<< (32 - shift
));
4351 return res
& 0xffffffff;
4354 /* Return number of 1-bits in VAL. */
4357 bitcount (unsigned long val
)
4360 for (nbits
= 0; val
!= 0; nbits
++)
4361 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4365 /* Return the size in bytes of the complete Thumb instruction whose
4366 first halfword is INST1. */
4369 thumb_insn_size (unsigned short inst1
)
4371 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4378 thumb_advance_itstate (unsigned int itstate
)
4380 /* Preserve IT[7:5], the first three bits of the condition. Shift
4381 the upcoming condition flags left by one bit. */
4382 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4384 /* If we have finished the IT block, clear the state. */
4385 if ((itstate
& 0x0f) == 0)
4391 /* Find the next PC after the current instruction executes. In some
4392 cases we can not statically determine the answer (see the IT state
4393 handling in this function); in that case, a breakpoint may be
4394 inserted in addition to the returned PC, which will be used to set
4395 another breakpoint by our caller. */
4398 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4400 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4401 struct address_space
*aspace
= get_frame_address_space (frame
);
4402 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4403 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4404 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4405 unsigned short inst1
;
4406 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4407 unsigned long offset
;
4408 ULONGEST status
, itstate
;
4410 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4411 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4413 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4415 /* Thumb-2 conditional execution support. There are eight bits in
4416 the CPSR which describe conditional execution state. Once
4417 reconstructed (they're in a funny order), the low five bits
4418 describe the low bit of the condition for each instruction and
4419 how many instructions remain. The high three bits describe the
4420 base condition. One of the low four bits will be set if an IT
4421 block is active. These bits read as zero on earlier
4423 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4424 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4426 /* If-Then handling. On GNU/Linux, where this routine is used, we
4427 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4428 can disable execution of the undefined instruction. So we might
4429 miss the breakpoint if we set it on a skipped conditional
4430 instruction. Because conditional instructions can change the
4431 flags, affecting the execution of further instructions, we may
4432 need to set two breakpoints. */
4434 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4436 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4438 /* An IT instruction. Because this instruction does not
4439 modify the flags, we can accurately predict the next
4440 executed instruction. */
4441 itstate
= inst1
& 0x00ff;
4442 pc
+= thumb_insn_size (inst1
);
4444 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4446 inst1
= read_memory_unsigned_integer (pc
, 2,
4447 byte_order_for_code
);
4448 pc
+= thumb_insn_size (inst1
);
4449 itstate
= thumb_advance_itstate (itstate
);
4452 return MAKE_THUMB_ADDR (pc
);
4454 else if (itstate
!= 0)
4456 /* We are in a conditional block. Check the condition. */
4457 if (! condition_true (itstate
>> 4, status
))
4459 /* Advance to the next executed instruction. */
4460 pc
+= thumb_insn_size (inst1
);
4461 itstate
= thumb_advance_itstate (itstate
);
4463 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4465 inst1
= read_memory_unsigned_integer (pc
, 2,
4466 byte_order_for_code
);
4467 pc
+= thumb_insn_size (inst1
);
4468 itstate
= thumb_advance_itstate (itstate
);
4471 return MAKE_THUMB_ADDR (pc
);
4473 else if ((itstate
& 0x0f) == 0x08)
4475 /* This is the last instruction of the conditional
4476 block, and it is executed. We can handle it normally
4477 because the following instruction is not conditional,
4478 and we must handle it normally because it is
4479 permitted to branch. Fall through. */
4485 /* There are conditional instructions after this one.
4486 If this instruction modifies the flags, then we can
4487 not predict what the next executed instruction will
4488 be. Fortunately, this instruction is architecturally
4489 forbidden to branch; we know it will fall through.
4490 Start by skipping past it. */
4491 pc
+= thumb_insn_size (inst1
);
4492 itstate
= thumb_advance_itstate (itstate
);
4494 /* Set a breakpoint on the following instruction. */
4495 gdb_assert ((itstate
& 0x0f) != 0);
4496 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4497 MAKE_THUMB_ADDR (pc
));
4498 cond_negated
= (itstate
>> 4) & 1;
4500 /* Skip all following instructions with the same
4501 condition. If there is a later instruction in the IT
4502 block with the opposite condition, set the other
4503 breakpoint there. If not, then set a breakpoint on
4504 the instruction after the IT block. */
4507 inst1
= read_memory_unsigned_integer (pc
, 2,
4508 byte_order_for_code
);
4509 pc
+= thumb_insn_size (inst1
);
4510 itstate
= thumb_advance_itstate (itstate
);
4512 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4514 return MAKE_THUMB_ADDR (pc
);
4518 else if (itstate
& 0x0f)
4520 /* We are in a conditional block. Check the condition. */
4521 int cond
= itstate
>> 4;
4523 if (! condition_true (cond
, status
))
4524 /* Advance to the next instruction. All the 32-bit
4525 instructions share a common prefix. */
4526 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4528 /* Otherwise, handle the instruction normally. */
4531 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4535 /* Fetch the saved PC from the stack. It's stored above
4536 all of the other registers. */
4537 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4538 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4539 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4541 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4543 unsigned long cond
= bits (inst1
, 8, 11);
4544 if (cond
== 0x0f) /* 0x0f = SWI */
4546 struct gdbarch_tdep
*tdep
;
4547 tdep
= gdbarch_tdep (gdbarch
);
4549 if (tdep
->syscall_next_pc
!= NULL
)
4550 nextpc
= tdep
->syscall_next_pc (frame
);
4553 else if (cond
!= 0x0f && condition_true (cond
, status
))
4554 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4556 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4558 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4560 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4562 unsigned short inst2
;
4563 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4565 /* Default to the next instruction. */
4567 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4569 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4571 /* Branches and miscellaneous control instructions. */
4573 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4576 int j1
, j2
, imm1
, imm2
;
4578 imm1
= sbits (inst1
, 0, 10);
4579 imm2
= bits (inst2
, 0, 10);
4580 j1
= bit (inst2
, 13);
4581 j2
= bit (inst2
, 11);
4583 offset
= ((imm1
<< 12) + (imm2
<< 1));
4584 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4586 nextpc
= pc_val
+ offset
;
4587 /* For BLX make sure to clear the low bits. */
4588 if (bit (inst2
, 12) == 0)
4589 nextpc
= nextpc
& 0xfffffffc;
4591 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4593 /* SUBS PC, LR, #imm8. */
4594 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4595 nextpc
-= inst2
& 0x00ff;
4597 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4599 /* Conditional branch. */
4600 if (condition_true (bits (inst1
, 6, 9), status
))
4602 int sign
, j1
, j2
, imm1
, imm2
;
4604 sign
= sbits (inst1
, 10, 10);
4605 imm1
= bits (inst1
, 0, 5);
4606 imm2
= bits (inst2
, 0, 10);
4607 j1
= bit (inst2
, 13);
4608 j2
= bit (inst2
, 11);
4610 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4611 offset
+= (imm1
<< 12) + (imm2
<< 1);
4613 nextpc
= pc_val
+ offset
;
4617 else if ((inst1
& 0xfe50) == 0xe810)
4619 /* Load multiple or RFE. */
4620 int rn
, offset
, load_pc
= 1;
4622 rn
= bits (inst1
, 0, 3);
4623 if (bit (inst1
, 7) && !bit (inst1
, 8))
4626 if (!bit (inst2
, 15))
4628 offset
= bitcount (inst2
) * 4 - 4;
4630 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4633 if (!bit (inst2
, 15))
4637 else if (bit (inst1
, 7) && bit (inst1
, 8))
4642 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4652 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4653 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4656 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4658 /* MOV PC or MOVS PC. */
4659 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4660 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4662 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4666 int rn
, load_pc
= 1;
4668 rn
= bits (inst1
, 0, 3);
4669 base
= get_frame_register_unsigned (frame
, rn
);
4670 if (rn
== ARM_PC_REGNUM
)
4672 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4674 base
+= bits (inst2
, 0, 11);
4676 base
-= bits (inst2
, 0, 11);
4678 else if (bit (inst1
, 7))
4679 base
+= bits (inst2
, 0, 11);
4680 else if (bit (inst2
, 11))
4682 if (bit (inst2
, 10))
4685 base
+= bits (inst2
, 0, 7);
4687 base
-= bits (inst2
, 0, 7);
4690 else if ((inst2
& 0x0fc0) == 0x0000)
4692 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4693 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4700 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4702 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4705 CORE_ADDR tbl_reg
, table
, offset
, length
;
4707 tbl_reg
= bits (inst1
, 0, 3);
4708 if (tbl_reg
== 0x0f)
4709 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4711 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4713 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4714 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4715 nextpc
= pc_val
+ length
;
4717 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4720 CORE_ADDR tbl_reg
, table
, offset
, length
;
4722 tbl_reg
= bits (inst1
, 0, 3);
4723 if (tbl_reg
== 0x0f)
4724 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4726 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4728 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4729 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4730 nextpc
= pc_val
+ length
;
4733 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4735 if (bits (inst1
, 3, 6) == 0x0f)
4736 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4738 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4740 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4742 if (bits (inst1
, 3, 6) == 0x0f)
4745 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4747 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4749 else if ((inst1
& 0xf500) == 0xb100)
4752 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4753 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4755 if (bit (inst1
, 11) && reg
!= 0)
4756 nextpc
= pc_val
+ imm
;
4757 else if (!bit (inst1
, 11) && reg
== 0)
4758 nextpc
= pc_val
+ imm
;
4763 /* Get the raw next address. PC is the current program counter, in
4764 FRAME, which is assumed to be executing in ARM mode.
4766 The value returned has the execution state of the next instruction
4767 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4768 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4772 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4774 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4775 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4776 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4777 unsigned long pc_val
;
4778 unsigned long this_instr
;
4779 unsigned long status
;
4782 pc_val
= (unsigned long) pc
;
4783 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4785 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4786 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4788 if (bits (this_instr
, 28, 31) == INST_NV
)
4789 switch (bits (this_instr
, 24, 27))
4794 /* Branch with Link and change to Thumb. */
4795 nextpc
= BranchDest (pc
, this_instr
);
4796 nextpc
|= bit (this_instr
, 24) << 1;
4797 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4803 /* Coprocessor register transfer. */
4804 if (bits (this_instr
, 12, 15) == 15)
4805 error (_("Invalid update to pc in instruction"));
4808 else if (condition_true (bits (this_instr
, 28, 31), status
))
4810 switch (bits (this_instr
, 24, 27))
4813 case 0x1: /* data processing */
4817 unsigned long operand1
, operand2
, result
= 0;
4821 if (bits (this_instr
, 12, 15) != 15)
4824 if (bits (this_instr
, 22, 25) == 0
4825 && bits (this_instr
, 4, 7) == 9) /* multiply */
4826 error (_("Invalid update to pc in instruction"));
4828 /* BX <reg>, BLX <reg> */
4829 if (bits (this_instr
, 4, 27) == 0x12fff1
4830 || bits (this_instr
, 4, 27) == 0x12fff3)
4832 rn
= bits (this_instr
, 0, 3);
4833 nextpc
= ((rn
== ARM_PC_REGNUM
)
4835 : get_frame_register_unsigned (frame
, rn
));
4840 /* Multiply into PC. */
4841 c
= (status
& FLAG_C
) ? 1 : 0;
4842 rn
= bits (this_instr
, 16, 19);
4843 operand1
= ((rn
== ARM_PC_REGNUM
)
4845 : get_frame_register_unsigned (frame
, rn
));
4847 if (bit (this_instr
, 25))
4849 unsigned long immval
= bits (this_instr
, 0, 7);
4850 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4851 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4854 else /* operand 2 is a shifted register. */
4855 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4858 switch (bits (this_instr
, 21, 24))
4861 result
= operand1
& operand2
;
4865 result
= operand1
^ operand2
;
4869 result
= operand1
- operand2
;
4873 result
= operand2
- operand1
;
4877 result
= operand1
+ operand2
;
4881 result
= operand1
+ operand2
+ c
;
4885 result
= operand1
- operand2
+ c
;
4889 result
= operand2
- operand1
+ c
;
4895 case 0xb: /* tst, teq, cmp, cmn */
4896 result
= (unsigned long) nextpc
;
4900 result
= operand1
| operand2
;
4904 /* Always step into a function. */
4909 result
= operand1
& ~operand2
;
4917 /* In 26-bit APCS the bottom two bits of the result are
4918 ignored, and we always end up in ARM state. */
4920 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4928 case 0x5: /* data transfer */
4931 if (bits (this_instr
, 25, 27) == 0x3 && bit (this_instr
, 4) == 1)
4933 /* Media instructions and architecturally undefined
4938 if (bit (this_instr
, 20))
4941 if (bits (this_instr
, 12, 15) == 15)
4947 if (bit (this_instr
, 22))
4948 error (_("Invalid update to pc in instruction"));
4950 /* byte write to PC */
4951 rn
= bits (this_instr
, 16, 19);
4952 base
= ((rn
== ARM_PC_REGNUM
)
4954 : get_frame_register_unsigned (frame
, rn
));
4956 if (bit (this_instr
, 24))
4959 int c
= (status
& FLAG_C
) ? 1 : 0;
4960 unsigned long offset
=
4961 (bit (this_instr
, 25)
4962 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4963 : bits (this_instr
, 0, 11));
4965 if (bit (this_instr
, 23))
4971 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4978 case 0x9: /* block transfer */
4979 if (bit (this_instr
, 20))
4982 if (bit (this_instr
, 15))
4986 unsigned long rn_val
4987 = get_frame_register_unsigned (frame
,
4988 bits (this_instr
, 16, 19));
4990 if (bit (this_instr
, 23))
4993 unsigned long reglist
= bits (this_instr
, 0, 14);
4994 offset
= bitcount (reglist
) * 4;
4995 if (bit (this_instr
, 24)) /* pre */
4998 else if (bit (this_instr
, 24))
5002 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
5009 case 0xb: /* branch & link */
5010 case 0xa: /* branch */
5012 nextpc
= BranchDest (pc
, this_instr
);
5018 case 0xe: /* coproc ops */
5022 struct gdbarch_tdep
*tdep
;
5023 tdep
= gdbarch_tdep (gdbarch
);
5025 if (tdep
->syscall_next_pc
!= NULL
)
5026 nextpc
= tdep
->syscall_next_pc (frame
);
5032 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
5040 /* Determine next PC after current instruction executes. Will call either
5041 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5042 loop is detected. */
5045 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5049 if (arm_frame_is_thumb (frame
))
5050 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
5052 nextpc
= arm_get_next_pc_raw (frame
, pc
);
5057 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5058 of the appropriate mode (as encoded in the PC value), even if this
5059 differs from what would be expected according to the symbol tables. */
5062 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
5063 struct address_space
*aspace
,
5066 struct cleanup
*old_chain
5067 = make_cleanup_restore_integer (&arm_override_mode
);
5069 arm_override_mode
= IS_THUMB_ADDR (pc
);
5070 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
5072 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
5074 do_cleanups (old_chain
);
5077 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5078 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5079 is found, attempt to step through it. A breakpoint is placed at the end of
5083 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5085 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5086 struct address_space
*aspace
= get_frame_address_space (frame
);
5087 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5088 CORE_ADDR pc
= get_frame_pc (frame
);
5089 CORE_ADDR breaks
[2] = {-1, -1};
5091 unsigned short insn1
, insn2
;
5094 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5095 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5096 ULONGEST status
, itstate
;
5098 /* We currently do not support atomic sequences within an IT block. */
5099 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
5100 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
5104 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5105 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5107 if (thumb_insn_size (insn1
) != 4)
5110 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5112 if (!((insn1
& 0xfff0) == 0xe850
5113 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
5116 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5118 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5120 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5123 if (thumb_insn_size (insn1
) != 4)
5125 /* Assume that there is at most one conditional branch in the
5126 atomic sequence. If a conditional branch is found, put a
5127 breakpoint in its destination address. */
5128 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
5130 if (last_breakpoint
> 0)
5131 return 0; /* More than one conditional branch found,
5132 fallback to the standard code. */
5134 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
5138 /* We do not support atomic sequences that use any *other*
5139 instructions but conditional branches to change the PC.
5140 Fall back to standard code to avoid losing control of
5142 else if (thumb_instruction_changes_pc (insn1
))
5147 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5150 /* Assume that there is at most one conditional branch in the
5151 atomic sequence. If a conditional branch is found, put a
5152 breakpoint in its destination address. */
5153 if ((insn1
& 0xf800) == 0xf000
5154 && (insn2
& 0xd000) == 0x8000
5155 && (insn1
& 0x0380) != 0x0380)
5157 int sign
, j1
, j2
, imm1
, imm2
;
5158 unsigned int offset
;
5160 sign
= sbits (insn1
, 10, 10);
5161 imm1
= bits (insn1
, 0, 5);
5162 imm2
= bits (insn2
, 0, 10);
5163 j1
= bit (insn2
, 13);
5164 j2
= bit (insn2
, 11);
5166 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
5167 offset
+= (imm1
<< 12) + (imm2
<< 1);
5169 if (last_breakpoint
> 0)
5170 return 0; /* More than one conditional branch found,
5171 fallback to the standard code. */
5173 breaks
[1] = loc
+ offset
;
5177 /* We do not support atomic sequences that use any *other*
5178 instructions but conditional branches to change the PC.
5179 Fall back to standard code to avoid losing control of
5181 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
5184 /* If we find a strex{,b,h,d}, we're done. */
5185 if ((insn1
& 0xfff0) == 0xe840
5186 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5191 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5192 if (insn_count
== atomic_sequence_length
)
5195 /* Insert a breakpoint right after the end of the atomic sequence. */
5198 /* Check for duplicated breakpoints. Check also for a breakpoint
5199 placed (branch instruction's destination) anywhere in sequence. */
5201 && (breaks
[1] == breaks
[0]
5202 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5203 last_breakpoint
= 0;
5205 /* Effectively inserts the breakpoints. */
5206 for (index
= 0; index
<= last_breakpoint
; index
++)
5207 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5208 MAKE_THUMB_ADDR (breaks
[index
]));
5214 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5216 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5217 struct address_space
*aspace
= get_frame_address_space (frame
);
5218 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5219 CORE_ADDR pc
= get_frame_pc (frame
);
5220 CORE_ADDR breaks
[2] = {-1, -1};
5225 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5226 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5228 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5229 Note that we do not currently support conditionally executed atomic
5231 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5233 if ((insn
& 0xff9000f0) != 0xe1900090)
5236 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5238 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5240 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5243 /* Assume that there is at most one conditional branch in the atomic
5244 sequence. If a conditional branch is found, put a breakpoint in
5245 its destination address. */
5246 if (bits (insn
, 24, 27) == 0xa)
5248 if (last_breakpoint
> 0)
5249 return 0; /* More than one conditional branch found, fallback
5250 to the standard single-step code. */
5252 breaks
[1] = BranchDest (loc
- 4, insn
);
5256 /* We do not support atomic sequences that use any *other* instructions
5257 but conditional branches to change the PC. Fall back to standard
5258 code to avoid losing control of execution. */
5259 else if (arm_instruction_changes_pc (insn
))
5262 /* If we find a strex{,b,h,d}, we're done. */
5263 if ((insn
& 0xff9000f0) == 0xe1800090)
5267 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5268 if (insn_count
== atomic_sequence_length
)
5271 /* Insert a breakpoint right after the end of the atomic sequence. */
5274 /* Check for duplicated breakpoints. Check also for a breakpoint
5275 placed (branch instruction's destination) anywhere in sequence. */
5277 && (breaks
[1] == breaks
[0]
5278 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5279 last_breakpoint
= 0;
5281 /* Effectively inserts the breakpoints. */
5282 for (index
= 0; index
<= last_breakpoint
; index
++)
5283 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5289 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5291 if (arm_frame_is_thumb (frame
))
5292 return thumb_deal_with_atomic_sequence_raw (frame
);
5294 return arm_deal_with_atomic_sequence_raw (frame
);
5297 /* single_step() is called just before we want to resume the inferior,
5298 if we want to single-step it but there is no hardware or kernel
5299 single-step support. We find the target of the coming instruction
5300 and breakpoint it. */
5303 arm_software_single_step (struct frame_info
*frame
)
5305 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5306 struct address_space
*aspace
= get_frame_address_space (frame
);
5309 if (arm_deal_with_atomic_sequence (frame
))
5312 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5313 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5318 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5319 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5320 NULL if an error occurs. BUF is freed. */
5323 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5324 int old_len
, int new_len
)
5327 int bytes_to_read
= new_len
- old_len
;
5329 new_buf
= (gdb_byte
*) xmalloc (new_len
);
5330 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5332 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5340 /* An IT block is at most the 2-byte IT instruction followed by
5341 four 4-byte instructions. The furthest back we must search to
5342 find an IT block that affects the current instruction is thus
5343 2 + 3 * 4 == 14 bytes. */
5344 #define MAX_IT_BLOCK_PREFIX 14
5346 /* Use a quick scan if there are more than this many bytes of
5348 #define IT_SCAN_THRESHOLD 32
5350 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5351 A breakpoint in an IT block may not be hit, depending on the
5354 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5358 CORE_ADDR boundary
, func_start
;
5360 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5361 int i
, any
, last_it
, last_it_count
;
5363 /* If we are using BKPT breakpoints, none of this is necessary. */
5364 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5367 /* ARM mode does not have this problem. */
5368 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5371 /* We are setting a breakpoint in Thumb code that could potentially
5372 contain an IT block. The first step is to find how much Thumb
5373 code there is; we do not need to read outside of known Thumb
5375 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5377 /* Thumb-2 code must have mapping symbols to have a chance. */
5380 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5382 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5383 && func_start
> boundary
)
5384 boundary
= func_start
;
5386 /* Search for a candidate IT instruction. We have to do some fancy
5387 footwork to distinguish a real IT instruction from the second
5388 half of a 32-bit instruction, but there is no need for that if
5389 there's no candidate. */
5390 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5392 /* No room for an IT instruction. */
5395 buf
= (gdb_byte
*) xmalloc (buf_len
);
5396 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5399 for (i
= 0; i
< buf_len
; i
+= 2)
5401 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5402 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5414 /* OK, the code bytes before this instruction contain at least one
5415 halfword which resembles an IT instruction. We know that it's
5416 Thumb code, but there are still two possibilities. Either the
5417 halfword really is an IT instruction, or it is the second half of
5418 a 32-bit Thumb instruction. The only way we can tell is to
5419 scan forwards from a known instruction boundary. */
5420 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5424 /* There's a lot of code before this instruction. Start with an
5425 optimistic search; it's easy to recognize halfwords that can
5426 not be the start of a 32-bit instruction, and use that to
5427 lock on to the instruction boundaries. */
5428 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5431 buf_len
= IT_SCAN_THRESHOLD
;
5434 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5436 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5437 if (thumb_insn_size (inst1
) == 2)
5444 /* At this point, if DEFINITE, BUF[I] is the first place we
5445 are sure that we know the instruction boundaries, and it is far
5446 enough from BPADDR that we could not miss an IT instruction
5447 affecting BPADDR. If ! DEFINITE, give up - start from a
5451 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5455 buf_len
= bpaddr
- boundary
;
5461 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5464 buf_len
= bpaddr
- boundary
;
5468 /* Scan forwards. Find the last IT instruction before BPADDR. */
5473 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5475 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5480 else if (inst1
& 0x0002)
5482 else if (inst1
& 0x0004)
5487 i
+= thumb_insn_size (inst1
);
5493 /* There wasn't really an IT instruction after all. */
5496 if (last_it_count
< 1)
5497 /* It was too far away. */
5500 /* This really is a trouble spot. Move the breakpoint to the IT
5502 return bpaddr
- buf_len
+ last_it
;
5505 /* ARM displaced stepping support.
5507 Generally ARM displaced stepping works as follows:
5509 1. When an instruction is to be single-stepped, it is first decoded by
5510 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5511 Depending on the type of instruction, it is then copied to a scratch
5512 location, possibly in a modified form. The copy_* set of functions
5513 performs such modification, as necessary. A breakpoint is placed after
5514 the modified instruction in the scratch space to return control to GDB.
5515 Note in particular that instructions which modify the PC will no longer
5516 do so after modification.
5518 2. The instruction is single-stepped, by setting the PC to the scratch
5519 location address, and resuming. Control returns to GDB when the
5522 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5523 function used for the current instruction. This function's job is to
5524 put the CPU/memory state back to what it would have been if the
5525 instruction had been executed unmodified in its original location. */
5527 /* NOP instruction (mov r0, r0). */
5528 #define ARM_NOP 0xe1a00000
5529 #define THUMB_NOP 0x4600
5531 /* Helper for register reads for displaced stepping. In particular, this
5532 returns the PC as it would be seen by the instruction at its original
5536 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5540 CORE_ADDR from
= dsc
->insn_addr
;
5542 if (regno
== ARM_PC_REGNUM
)
5544 /* Compute pipeline offset:
5545 - When executing an ARM instruction, PC reads as the address of the
5546 current instruction plus 8.
5547 - When executing a Thumb instruction, PC reads as the address of the
5548 current instruction plus 4. */
5555 if (debug_displaced
)
5556 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5557 (unsigned long) from
);
5558 return (ULONGEST
) from
;
5562 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5563 if (debug_displaced
)
5564 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5565 regno
, (unsigned long) ret
);
5571 displaced_in_arm_mode (struct regcache
*regs
)
5574 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5576 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5578 return (ps
& t_bit
) == 0;
5581 /* Write to the PC as from a branch instruction. */
5584 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5588 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5589 architecture versions < 6. */
5590 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5591 val
& ~(ULONGEST
) 0x3);
5593 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5594 val
& ~(ULONGEST
) 0x1);
5597 /* Write to the PC as from a branch-exchange instruction. */
5600 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5603 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5605 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5609 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5610 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5612 else if ((val
& 2) == 0)
5614 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5615 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5619 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5620 mode, align dest to 4 bytes). */
5621 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5622 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5623 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5627 /* Write to the PC as if from a load instruction. */
5630 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5633 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5634 bx_write_pc (regs
, val
);
5636 branch_write_pc (regs
, dsc
, val
);
5639 /* Write to the PC as if from an ALU instruction. */
5642 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5645 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5646 bx_write_pc (regs
, val
);
5648 branch_write_pc (regs
, dsc
, val
);
5651 /* Helper for writing to registers for displaced stepping. Writing to the PC
5652 has a varying effects depending on the instruction which does the write:
5653 this is controlled by the WRITE_PC argument. */
5656 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5657 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5659 if (regno
== ARM_PC_REGNUM
)
5661 if (debug_displaced
)
5662 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5663 (unsigned long) val
);
5666 case BRANCH_WRITE_PC
:
5667 branch_write_pc (regs
, dsc
, val
);
5671 bx_write_pc (regs
, val
);
5675 load_write_pc (regs
, dsc
, val
);
5679 alu_write_pc (regs
, dsc
, val
);
5682 case CANNOT_WRITE_PC
:
5683 warning (_("Instruction wrote to PC in an unexpected way when "
5684 "single-stepping"));
5688 internal_error (__FILE__
, __LINE__
,
5689 _("Invalid argument to displaced_write_reg"));
5692 dsc
->wrote_to_pc
= 1;
5696 if (debug_displaced
)
5697 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5698 regno
, (unsigned long) val
);
5699 regcache_cooked_write_unsigned (regs
, regno
, val
);
5703 /* This function is used to concisely determine if an instruction INSN
5704 references PC. Register fields of interest in INSN should have the
5705 corresponding fields of BITMASK set to 0b1111. The function
5706 returns return 1 if any of these fields in INSN reference the PC
5707 (also 0b1111, r15), else it returns 0. */
5710 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5712 uint32_t lowbit
= 1;
5714 while (bitmask
!= 0)
5718 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5724 mask
= lowbit
* 0xf;
5726 if ((insn
& mask
) == mask
)
5735 /* The simplest copy function. Many instructions have the same effect no
5736 matter what address they are executed at: in those cases, use this. */
5739 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5740 const char *iname
, struct displaced_step_closure
*dsc
)
5742 if (debug_displaced
)
5743 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5744 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5747 dsc
->modinsn
[0] = insn
;
5753 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5754 uint16_t insn2
, const char *iname
,
5755 struct displaced_step_closure
*dsc
)
5757 if (debug_displaced
)
5758 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5759 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5762 dsc
->modinsn
[0] = insn1
;
5763 dsc
->modinsn
[1] = insn2
;
5769 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5772 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5774 struct displaced_step_closure
*dsc
)
5776 if (debug_displaced
)
5777 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5778 "opcode/class '%s' unmodified\n", insn
,
5781 dsc
->modinsn
[0] = insn
;
5786 /* Preload instructions with immediate offset. */
5789 cleanup_preload (struct gdbarch
*gdbarch
,
5790 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5792 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5793 if (!dsc
->u
.preload
.immed
)
5794 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5798 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5799 struct displaced_step_closure
*dsc
, unsigned int rn
)
5802 /* Preload instructions:
5804 {pli/pld} [rn, #+/-imm]
5806 {pli/pld} [r0, #+/-imm]. */
5808 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5809 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5810 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5811 dsc
->u
.preload
.immed
= 1;
5813 dsc
->cleanup
= &cleanup_preload
;
5817 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5818 struct displaced_step_closure
*dsc
)
5820 unsigned int rn
= bits (insn
, 16, 19);
5822 if (!insn_references_pc (insn
, 0x000f0000ul
))
5823 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5825 if (debug_displaced
)
5826 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5827 (unsigned long) insn
);
5829 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5831 install_preload (gdbarch
, regs
, dsc
, rn
);
5837 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5838 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5840 unsigned int rn
= bits (insn1
, 0, 3);
5841 unsigned int u_bit
= bit (insn1
, 7);
5842 int imm12
= bits (insn2
, 0, 11);
5845 if (rn
!= ARM_PC_REGNUM
)
5846 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5848 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5849 PLD (literal) Encoding T1. */
5850 if (debug_displaced
)
5851 fprintf_unfiltered (gdb_stdlog
,
5852 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5853 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5859 /* Rewrite instruction {pli/pld} PC imm12 into:
5860 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5864 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5866 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5867 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5869 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5871 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5872 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5873 dsc
->u
.preload
.immed
= 0;
5875 /* {pli/pld} [r0, r1] */
5876 dsc
->modinsn
[0] = insn1
& 0xfff0;
5877 dsc
->modinsn
[1] = 0xf001;
5880 dsc
->cleanup
= &cleanup_preload
;
5884 /* Preload instructions with register offset. */
5887 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5888 struct displaced_step_closure
*dsc
, unsigned int rn
,
5891 ULONGEST rn_val
, rm_val
;
5893 /* Preload register-offset instructions:
5895 {pli/pld} [rn, rm {, shift}]
5897 {pli/pld} [r0, r1 {, shift}]. */
5899 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5900 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5901 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5902 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5903 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5904 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5905 dsc
->u
.preload
.immed
= 0;
5907 dsc
->cleanup
= &cleanup_preload
;
5911 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5912 struct regcache
*regs
,
5913 struct displaced_step_closure
*dsc
)
5915 unsigned int rn
= bits (insn
, 16, 19);
5916 unsigned int rm
= bits (insn
, 0, 3);
5919 if (!insn_references_pc (insn
, 0x000f000ful
))
5920 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5922 if (debug_displaced
)
5923 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5924 (unsigned long) insn
);
5926 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5928 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5932 /* Copy/cleanup coprocessor load and store instructions. */
5935 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5936 struct regcache
*regs
,
5937 struct displaced_step_closure
*dsc
)
5939 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5941 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5943 if (dsc
->u
.ldst
.writeback
)
5944 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5948 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5949 struct displaced_step_closure
*dsc
,
5950 int writeback
, unsigned int rn
)
5954 /* Coprocessor load/store instructions:
5956 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5958 {stc/stc2} [r0, #+/-imm].
5960 ldc/ldc2 are handled identically. */
5962 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5963 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5964 /* PC should be 4-byte aligned. */
5965 rn_val
= rn_val
& 0xfffffffc;
5966 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5968 dsc
->u
.ldst
.writeback
= writeback
;
5969 dsc
->u
.ldst
.rn
= rn
;
5971 dsc
->cleanup
= &cleanup_copro_load_store
;
5975 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5976 struct regcache
*regs
,
5977 struct displaced_step_closure
*dsc
)
5979 unsigned int rn
= bits (insn
, 16, 19);
5981 if (!insn_references_pc (insn
, 0x000f0000ul
))
5982 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5984 if (debug_displaced
)
5985 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5986 "load/store insn %.8lx\n", (unsigned long) insn
);
5988 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5990 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5996 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5997 uint16_t insn2
, struct regcache
*regs
,
5998 struct displaced_step_closure
*dsc
)
6000 unsigned int rn
= bits (insn1
, 0, 3);
6002 if (rn
!= ARM_PC_REGNUM
)
6003 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6004 "copro load/store", dsc
);
6006 if (debug_displaced
)
6007 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
6008 "load/store insn %.4x%.4x\n", insn1
, insn2
);
6010 dsc
->modinsn
[0] = insn1
& 0xfff0;
6011 dsc
->modinsn
[1] = insn2
;
6014 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6015 doesn't support writeback, so pass 0. */
6016 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
6021 /* Clean up branch instructions (actually perform the branch, by setting
6025 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6026 struct displaced_step_closure
*dsc
)
6028 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6029 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
6030 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
6031 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
6036 if (dsc
->u
.branch
.link
)
6038 /* The value of LR should be the next insn of current one. In order
6039 not to confuse logic hanlding later insn `bx lr', if current insn mode
6040 is Thumb, the bit 0 of LR value should be set to 1. */
6041 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6044 next_insn_addr
|= 0x1;
6046 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
6050 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
6053 /* Copy B/BL/BLX instructions with immediate destinations. */
6056 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6057 struct displaced_step_closure
*dsc
,
6058 unsigned int cond
, int exchange
, int link
, long offset
)
6060 /* Implement "BL<cond> <label>" as:
6062 Preparation: cond <- instruction condition
6063 Insn: mov r0, r0 (nop)
6064 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6066 B<cond> similar, but don't set r14 in cleanup. */
6068 dsc
->u
.branch
.cond
= cond
;
6069 dsc
->u
.branch
.link
= link
;
6070 dsc
->u
.branch
.exchange
= exchange
;
6072 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
6073 if (link
&& exchange
)
6074 /* For BLX, offset is computed from the Align (PC, 4). */
6075 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
6078 dsc
->u
.branch
.dest
+= 4 + offset
;
6080 dsc
->u
.branch
.dest
+= 8 + offset
;
6082 dsc
->cleanup
= &cleanup_branch
;
6085 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
6086 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6088 unsigned int cond
= bits (insn
, 28, 31);
6089 int exchange
= (cond
== 0xf);
6090 int link
= exchange
|| bit (insn
, 24);
6093 if (debug_displaced
)
6094 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
6095 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
6096 (unsigned long) insn
);
6098 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6099 then arrange the switch into Thumb mode. */
6100 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
6102 offset
= bits (insn
, 0, 23) << 2;
6104 if (bit (offset
, 25))
6105 offset
= offset
| ~0x3ffffff;
6107 dsc
->modinsn
[0] = ARM_NOP
;
6109 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6114 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
6115 uint16_t insn2
, struct regcache
*regs
,
6116 struct displaced_step_closure
*dsc
)
6118 int link
= bit (insn2
, 14);
6119 int exchange
= link
&& !bit (insn2
, 12);
6122 int j1
= bit (insn2
, 13);
6123 int j2
= bit (insn2
, 11);
6124 int s
= sbits (insn1
, 10, 10);
6125 int i1
= !(j1
^ bit (insn1
, 10));
6126 int i2
= !(j2
^ bit (insn1
, 10));
6128 if (!link
&& !exchange
) /* B */
6130 offset
= (bits (insn2
, 0, 10) << 1);
6131 if (bit (insn2
, 12)) /* Encoding T4 */
6133 offset
|= (bits (insn1
, 0, 9) << 12)
6139 else /* Encoding T3 */
6141 offset
|= (bits (insn1
, 0, 5) << 12)
6145 cond
= bits (insn1
, 6, 9);
6150 offset
= (bits (insn1
, 0, 9) << 12);
6151 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
6152 offset
|= exchange
?
6153 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
6156 if (debug_displaced
)
6157 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
6158 "%.4x %.4x with offset %.8lx\n",
6159 link
? (exchange
) ? "blx" : "bl" : "b",
6160 insn1
, insn2
, offset
);
6162 dsc
->modinsn
[0] = THUMB_NOP
;
6164 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6168 /* Copy B Thumb instructions. */
6170 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
6171 struct displaced_step_closure
*dsc
)
6173 unsigned int cond
= 0;
6175 unsigned short bit_12_15
= bits (insn
, 12, 15);
6176 CORE_ADDR from
= dsc
->insn_addr
;
6178 if (bit_12_15
== 0xd)
6180 /* offset = SignExtend (imm8:0, 32) */
6181 offset
= sbits ((insn
<< 1), 0, 8);
6182 cond
= bits (insn
, 8, 11);
6184 else if (bit_12_15
== 0xe) /* Encoding T2 */
6186 offset
= sbits ((insn
<< 1), 0, 11);
6190 if (debug_displaced
)
6191 fprintf_unfiltered (gdb_stdlog
,
6192 "displaced: copying b immediate insn %.4x "
6193 "with offset %d\n", insn
, offset
);
6195 dsc
->u
.branch
.cond
= cond
;
6196 dsc
->u
.branch
.link
= 0;
6197 dsc
->u
.branch
.exchange
= 0;
6198 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6200 dsc
->modinsn
[0] = THUMB_NOP
;
6202 dsc
->cleanup
= &cleanup_branch
;
6207 /* Copy BX/BLX with register-specified destinations. */
6210 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6211 struct displaced_step_closure
*dsc
, int link
,
6212 unsigned int cond
, unsigned int rm
)
6214 /* Implement {BX,BLX}<cond> <reg>" as:
6216 Preparation: cond <- instruction condition
6217 Insn: mov r0, r0 (nop)
6218 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6220 Don't set r14 in cleanup for BX. */
6222 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6224 dsc
->u
.branch
.cond
= cond
;
6225 dsc
->u
.branch
.link
= link
;
6227 dsc
->u
.branch
.exchange
= 1;
6229 dsc
->cleanup
= &cleanup_branch
;
6233 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6234 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6236 unsigned int cond
= bits (insn
, 28, 31);
6239 int link
= bit (insn
, 5);
6240 unsigned int rm
= bits (insn
, 0, 3);
6242 if (debug_displaced
)
6243 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6244 (unsigned long) insn
);
6246 dsc
->modinsn
[0] = ARM_NOP
;
6248 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6253 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6254 struct regcache
*regs
,
6255 struct displaced_step_closure
*dsc
)
6257 int link
= bit (insn
, 7);
6258 unsigned int rm
= bits (insn
, 3, 6);
6260 if (debug_displaced
)
6261 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6262 (unsigned short) insn
);
6264 dsc
->modinsn
[0] = THUMB_NOP
;
6266 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6272 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6275 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6276 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6278 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6279 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6280 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6281 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6285 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6286 struct displaced_step_closure
*dsc
)
6288 unsigned int rn
= bits (insn
, 16, 19);
6289 unsigned int rd
= bits (insn
, 12, 15);
6290 unsigned int op
= bits (insn
, 21, 24);
6291 int is_mov
= (op
== 0xd);
6292 ULONGEST rd_val
, rn_val
;
6294 if (!insn_references_pc (insn
, 0x000ff000ul
))
6295 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6297 if (debug_displaced
)
6298 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6299 "%.8lx\n", is_mov
? "move" : "ALU",
6300 (unsigned long) insn
);
6302 /* Instruction is of form:
6304 <op><cond> rd, [rn,] #imm
6308 Preparation: tmp1, tmp2 <- r0, r1;
6310 Insn: <op><cond> r0, r1, #imm
6311 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6314 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6315 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6316 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6317 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6318 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6319 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6323 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6325 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6327 dsc
->cleanup
= &cleanup_alu_imm
;
6333 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6334 uint16_t insn2
, struct regcache
*regs
,
6335 struct displaced_step_closure
*dsc
)
6337 unsigned int op
= bits (insn1
, 5, 8);
6338 unsigned int rn
, rm
, rd
;
6339 ULONGEST rd_val
, rn_val
;
6341 rn
= bits (insn1
, 0, 3); /* Rn */
6342 rm
= bits (insn2
, 0, 3); /* Rm */
6343 rd
= bits (insn2
, 8, 11); /* Rd */
6345 /* This routine is only called for instruction MOV. */
6346 gdb_assert (op
== 0x2 && rn
== 0xf);
6348 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6349 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6351 if (debug_displaced
)
6352 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6353 "ALU", insn1
, insn2
);
6355 /* Instruction is of form:
6357 <op><cond> rd, [rn,] #imm
6361 Preparation: tmp1, tmp2 <- r0, r1;
6363 Insn: <op><cond> r0, r1, #imm
6364 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6367 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6368 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6369 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6370 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6371 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6372 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6375 dsc
->modinsn
[0] = insn1
;
6376 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6379 dsc
->cleanup
= &cleanup_alu_imm
;
6384 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6387 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6388 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6393 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6395 for (i
= 0; i
< 3; i
++)
6396 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6398 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6402 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6403 struct displaced_step_closure
*dsc
,
6404 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6406 ULONGEST rd_val
, rn_val
, rm_val
;
6408 /* Instruction is of form:
6410 <op><cond> rd, [rn,] rm [, <shift>]
6414 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6415 r0, r1, r2 <- rd, rn, rm
6416 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
6417 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6420 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6421 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6422 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6423 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6424 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6425 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6426 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6427 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6428 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6431 dsc
->cleanup
= &cleanup_alu_reg
;
6435 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6436 struct displaced_step_closure
*dsc
)
6438 unsigned int op
= bits (insn
, 21, 24);
6439 int is_mov
= (op
== 0xd);
6441 if (!insn_references_pc (insn
, 0x000ff00ful
))
6442 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6444 if (debug_displaced
)
6445 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6446 is_mov
? "move" : "ALU", (unsigned long) insn
);
6449 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6451 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6453 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6459 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6460 struct regcache
*regs
,
6461 struct displaced_step_closure
*dsc
)
6465 rm
= bits (insn
, 3, 6);
6466 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6468 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
6469 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6471 if (debug_displaced
)
6472 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
6473 (unsigned short) insn
);
6475 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
6477 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
6482 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6485 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6486 struct regcache
*regs
,
6487 struct displaced_step_closure
*dsc
)
6489 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6492 for (i
= 0; i
< 4; i
++)
6493 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6495 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6499 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6500 struct displaced_step_closure
*dsc
,
6501 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6505 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6507 /* Instruction is of form:
6509 <op><cond> rd, [rn,] rm, <shift> rs
6513 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6514 r0, r1, r2, r3 <- rd, rn, rm, rs
6515 Insn: <op><cond> r0, r1, r2, <shift> r3
6517 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6521 for (i
= 0; i
< 4; i
++)
6522 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6524 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6525 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6526 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6527 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6528 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6529 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6530 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6531 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6533 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6537 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6538 struct regcache
*regs
,
6539 struct displaced_step_closure
*dsc
)
6541 unsigned int op
= bits (insn
, 21, 24);
6542 int is_mov
= (op
== 0xd);
6543 unsigned int rd
, rn
, rm
, rs
;
6545 if (!insn_references_pc (insn
, 0x000fff0ful
))
6546 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6548 if (debug_displaced
)
6549 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6550 "%.8lx\n", is_mov
? "move" : "ALU",
6551 (unsigned long) insn
);
6553 rn
= bits (insn
, 16, 19);
6554 rm
= bits (insn
, 0, 3);
6555 rs
= bits (insn
, 8, 11);
6556 rd
= bits (insn
, 12, 15);
6559 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6561 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6563 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6568 /* Clean up load instructions. */
6571 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6572 struct displaced_step_closure
*dsc
)
6574 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6576 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6577 if (dsc
->u
.ldst
.xfersize
== 8)
6578 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6579 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6581 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6582 if (dsc
->u
.ldst
.xfersize
> 4)
6583 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6584 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6585 if (!dsc
->u
.ldst
.immed
)
6586 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6588 /* Handle register writeback. */
6589 if (dsc
->u
.ldst
.writeback
)
6590 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6591 /* Put result in right place. */
6592 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6593 if (dsc
->u
.ldst
.xfersize
== 8)
6594 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6597 /* Clean up store instructions. */
6600 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6601 struct displaced_step_closure
*dsc
)
6603 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6605 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6606 if (dsc
->u
.ldst
.xfersize
> 4)
6607 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6608 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6609 if (!dsc
->u
.ldst
.immed
)
6610 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6611 if (!dsc
->u
.ldst
.restore_r4
)
6612 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6615 if (dsc
->u
.ldst
.writeback
)
6616 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6619 /* Copy "extra" load/store instructions. These are halfword/doubleword
6620 transfers, which have a different encoding to byte/word transfers. */
6623 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6624 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6626 unsigned int op1
= bits (insn
, 20, 24);
6627 unsigned int op2
= bits (insn
, 5, 6);
6628 unsigned int rt
= bits (insn
, 12, 15);
6629 unsigned int rn
= bits (insn
, 16, 19);
6630 unsigned int rm
= bits (insn
, 0, 3);
6631 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6632 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6633 int immed
= (op1
& 0x4) != 0;
6635 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6637 if (!insn_references_pc (insn
, 0x000ff00ful
))
6638 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6640 if (debug_displaced
)
6641 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6642 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6643 (unsigned long) insn
);
6645 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6648 internal_error (__FILE__
, __LINE__
,
6649 _("copy_extra_ld_st: instruction decode error"));
6651 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6652 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6653 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6655 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6657 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6658 if (bytesize
[opcode
] == 8)
6659 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6660 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6662 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6664 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6665 if (bytesize
[opcode
] == 8)
6666 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6667 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6669 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6672 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6673 dsc
->u
.ldst
.rn
= rn
;
6674 dsc
->u
.ldst
.immed
= immed
;
6675 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6676 dsc
->u
.ldst
.restore_r4
= 0;
6679 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6681 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6682 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6684 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6686 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6687 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6689 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6694 /* Copy byte/half word/word loads and stores. */
6697 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6698 struct displaced_step_closure
*dsc
, int load
,
6699 int immed
, int writeback
, int size
, int usermode
,
6700 int rt
, int rm
, int rn
)
6702 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6704 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6705 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6707 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6709 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6711 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6712 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6714 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6716 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6717 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6719 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6721 dsc
->u
.ldst
.xfersize
= size
;
6722 dsc
->u
.ldst
.rn
= rn
;
6723 dsc
->u
.ldst
.immed
= immed
;
6724 dsc
->u
.ldst
.writeback
= writeback
;
6726 /* To write PC we can do:
6728 Before this sequence of instructions:
6729 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6730 r2 is the Rn value got from dispalced_read_reg.
6732 Insn1: push {pc} Write address of STR instruction + offset on stack
6733 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6734 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6735 = addr(Insn1) + offset - addr(Insn3) - 8
6737 Insn4: add r4, r4, #8 r4 = offset - 8
6738 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6740 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6742 Otherwise we don't know what value to write for PC, since the offset is
6743 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6744 of this can be found in Section "Saving from r15" in
6745 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6747 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6752 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6753 uint16_t insn2
, struct regcache
*regs
,
6754 struct displaced_step_closure
*dsc
, int size
)
6756 unsigned int u_bit
= bit (insn1
, 7);
6757 unsigned int rt
= bits (insn2
, 12, 15);
6758 int imm12
= bits (insn2
, 0, 11);
6761 if (debug_displaced
)
6762 fprintf_unfiltered (gdb_stdlog
,
6763 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6764 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6770 /* Rewrite instruction LDR Rt imm12 into:
6772 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6776 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6779 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6780 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6781 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6783 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6785 pc_val
= pc_val
& 0xfffffffc;
6787 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6788 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6792 dsc
->u
.ldst
.xfersize
= size
;
6793 dsc
->u
.ldst
.immed
= 0;
6794 dsc
->u
.ldst
.writeback
= 0;
6795 dsc
->u
.ldst
.restore_r4
= 0;
6797 /* LDR R0, R2, R3 */
6798 dsc
->modinsn
[0] = 0xf852;
6799 dsc
->modinsn
[1] = 0x3;
6802 dsc
->cleanup
= &cleanup_load
;
6808 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6809 uint16_t insn2
, struct regcache
*regs
,
6810 struct displaced_step_closure
*dsc
,
6811 int writeback
, int immed
)
6813 unsigned int rt
= bits (insn2
, 12, 15);
6814 unsigned int rn
= bits (insn1
, 0, 3);
6815 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6816 /* In LDR (register), there is also a register Rm, which is not allowed to
6817 be PC, so we don't have to check it. */
6819 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6820 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6823 if (debug_displaced
)
6824 fprintf_unfiltered (gdb_stdlog
,
6825 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6826 rt
, rn
, insn1
, insn2
);
6828 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6831 dsc
->u
.ldst
.restore_r4
= 0;
6834 /* ldr[b]<cond> rt, [rn, #imm], etc.
6836 ldr[b]<cond> r0, [r2, #imm]. */
6838 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6839 dsc
->modinsn
[1] = insn2
& 0x0fff;
6842 /* ldr[b]<cond> rt, [rn, rm], etc.
6844 ldr[b]<cond> r0, [r2, r3]. */
6846 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6847 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6857 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6858 struct regcache
*regs
,
6859 struct displaced_step_closure
*dsc
,
6860 int load
, int size
, int usermode
)
6862 int immed
= !bit (insn
, 25);
6863 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6864 unsigned int rt
= bits (insn
, 12, 15);
6865 unsigned int rn
= bits (insn
, 16, 19);
6866 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6868 if (!insn_references_pc (insn
, 0x000ff00ful
))
6869 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6871 if (debug_displaced
)
6872 fprintf_unfiltered (gdb_stdlog
,
6873 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6874 load
? (size
== 1 ? "ldrb" : "ldr")
6875 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6877 (unsigned long) insn
);
6879 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6880 usermode
, rt
, rm
, rn
);
6882 if (load
|| rt
!= ARM_PC_REGNUM
)
6884 dsc
->u
.ldst
.restore_r4
= 0;
6887 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6889 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6890 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6892 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6894 {ldr,str}[b]<cond> r0, [r2, r3]. */
6895 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6899 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6900 dsc
->u
.ldst
.restore_r4
= 1;
6901 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6902 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6903 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6904 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6905 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6909 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6911 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6916 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6921 /* Cleanup LDM instructions with fully-populated register list. This is an
6922 unfortunate corner case: it's impossible to implement correctly by modifying
6923 the instruction. The issue is as follows: we have an instruction,
6927 which we must rewrite to avoid loading PC. A possible solution would be to
6928 do the load in two halves, something like (with suitable cleanup
6932 ldm[id][ab] r8!, {r0-r7}
6934 ldm[id][ab] r8, {r7-r14}
6937 but at present there's no suitable place for <temp>, since the scratch space
6938 is overwritten before the cleanup routine is called. For now, we simply
6939 emulate the instruction. */
6942 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6943 struct displaced_step_closure
*dsc
)
6945 int inc
= dsc
->u
.block
.increment
;
6946 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6947 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6948 uint32_t regmask
= dsc
->u
.block
.regmask
;
6949 int regno
= inc
? 0 : 15;
6950 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6951 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6952 && (regmask
& 0x8000) != 0;
6953 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6954 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6955 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6960 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6961 sensible we can do here. Complain loudly. */
6962 if (exception_return
)
6963 error (_("Cannot single-step exception return"));
6965 /* We don't handle any stores here for now. */
6966 gdb_assert (dsc
->u
.block
.load
!= 0);
6968 if (debug_displaced
)
6969 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6970 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6971 dsc
->u
.block
.increment
? "inc" : "dec",
6972 dsc
->u
.block
.before
? "before" : "after");
6979 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6982 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6985 xfer_addr
+= bump_before
;
6987 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6988 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6990 xfer_addr
+= bump_after
;
6992 regmask
&= ~(1 << regno
);
6995 if (dsc
->u
.block
.writeback
)
6996 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
7000 /* Clean up an STM which included the PC in the register list. */
7003 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7004 struct displaced_step_closure
*dsc
)
7006 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7007 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7008 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
7009 CORE_ADDR stm_insn_addr
;
7012 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7014 /* If condition code fails, there's nothing else to do. */
7015 if (!store_executed
)
7018 if (dsc
->u
.block
.increment
)
7020 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
7022 if (dsc
->u
.block
.before
)
7027 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
7029 if (dsc
->u
.block
.before
)
7033 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
7034 stm_insn_addr
= dsc
->scratch_base
;
7035 offset
= pc_val
- stm_insn_addr
;
7037 if (debug_displaced
)
7038 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
7039 "STM instruction\n", offset
);
7041 /* Rewrite the stored PC to the proper value for the non-displaced original
7043 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
7044 dsc
->insn_addr
+ offset
);
7047 /* Clean up an LDM which includes the PC in the register list. We clumped all
7048 the registers in the transferred list into a contiguous range r0...rX (to
7049 avoid loading PC directly and losing control of the debugged program), so we
7050 must undo that here. */
7053 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
7054 struct regcache
*regs
,
7055 struct displaced_step_closure
*dsc
)
7057 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7058 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7059 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
7060 unsigned int regs_loaded
= bitcount (mask
);
7061 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
7063 /* The method employed here will fail if the register list is fully populated
7064 (we need to avoid loading PC directly). */
7065 gdb_assert (num_to_shuffle
< 16);
7070 clobbered
= (1 << num_to_shuffle
) - 1;
7072 while (num_to_shuffle
> 0)
7074 if ((mask
& (1 << write_reg
)) != 0)
7076 unsigned int read_reg
= num_to_shuffle
- 1;
7078 if (read_reg
!= write_reg
)
7080 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
7081 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
7082 if (debug_displaced
)
7083 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
7084 "loaded register r%d to r%d\n"), read_reg
,
7087 else if (debug_displaced
)
7088 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
7089 "r%d already in the right place\n"),
7092 clobbered
&= ~(1 << write_reg
);
7100 /* Restore any registers we scribbled over. */
7101 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
7103 if ((clobbered
& (1 << write_reg
)) != 0)
7105 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
7107 if (debug_displaced
)
7108 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
7109 "clobbered register r%d\n"), write_reg
);
7110 clobbered
&= ~(1 << write_reg
);
7114 /* Perform register writeback manually. */
7115 if (dsc
->u
.block
.writeback
)
7117 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
7119 if (dsc
->u
.block
.increment
)
7120 new_rn_val
+= regs_loaded
* 4;
7122 new_rn_val
-= regs_loaded
* 4;
7124 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
7129 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7130 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7133 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
7134 struct regcache
*regs
,
7135 struct displaced_step_closure
*dsc
)
7137 int load
= bit (insn
, 20);
7138 int user
= bit (insn
, 22);
7139 int increment
= bit (insn
, 23);
7140 int before
= bit (insn
, 24);
7141 int writeback
= bit (insn
, 21);
7142 int rn
= bits (insn
, 16, 19);
7144 /* Block transfers which don't mention PC can be run directly
7146 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
7147 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
7149 if (rn
== ARM_PC_REGNUM
)
7151 warning (_("displaced: Unpredictable LDM or STM with "
7152 "base register r15"));
7153 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
7156 if (debug_displaced
)
7157 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7158 "%.8lx\n", (unsigned long) insn
);
7160 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7161 dsc
->u
.block
.rn
= rn
;
7163 dsc
->u
.block
.load
= load
;
7164 dsc
->u
.block
.user
= user
;
7165 dsc
->u
.block
.increment
= increment
;
7166 dsc
->u
.block
.before
= before
;
7167 dsc
->u
.block
.writeback
= writeback
;
7168 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
7170 dsc
->u
.block
.regmask
= insn
& 0xffff;
7174 if ((insn
& 0xffff) == 0xffff)
7176 /* LDM with a fully-populated register list. This case is
7177 particularly tricky. Implement for now by fully emulating the
7178 instruction (which might not behave perfectly in all cases, but
7179 these instructions should be rare enough for that not to matter
7181 dsc
->modinsn
[0] = ARM_NOP
;
7183 dsc
->cleanup
= &cleanup_block_load_all
;
7187 /* LDM of a list of registers which includes PC. Implement by
7188 rewriting the list of registers to be transferred into a
7189 contiguous chunk r0...rX before doing the transfer, then shuffling
7190 registers into the correct places in the cleanup routine. */
7191 unsigned int regmask
= insn
& 0xffff;
7192 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7193 unsigned int to
= 0, from
= 0, i
, new_rn
;
7195 for (i
= 0; i
< num_in_list
; i
++)
7196 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7198 /* Writeback makes things complicated. We need to avoid clobbering
7199 the base register with one of the registers in our modified
7200 register list, but just using a different register can't work in
7203 ldm r14!, {r0-r13,pc}
7205 which would need to be rewritten as:
7209 but that can't work, because there's no free register for N.
7211 Solve this by turning off the writeback bit, and emulating
7212 writeback manually in the cleanup routine. */
7217 new_regmask
= (1 << num_in_list
) - 1;
7219 if (debug_displaced
)
7220 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7221 "{..., pc}: original reg list %.4x, modified "
7222 "list %.4x\n"), rn
, writeback
? "!" : "",
7223 (int) insn
& 0xffff, new_regmask
);
7225 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7227 dsc
->cleanup
= &cleanup_block_load_pc
;
7232 /* STM of a list of registers which includes PC. Run the instruction
7233 as-is, but out of line: this will store the wrong value for the PC,
7234 so we must manually fix up the memory in the cleanup routine.
7235 Doing things this way has the advantage that we can auto-detect
7236 the offset of the PC write (which is architecture-dependent) in
7237 the cleanup routine. */
7238 dsc
->modinsn
[0] = insn
;
7240 dsc
->cleanup
= &cleanup_block_store_pc
;
7247 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7248 struct regcache
*regs
,
7249 struct displaced_step_closure
*dsc
)
7251 int rn
= bits (insn1
, 0, 3);
7252 int load
= bit (insn1
, 4);
7253 int writeback
= bit (insn1
, 5);
7255 /* Block transfers which don't mention PC can be run directly
7257 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7258 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7260 if (rn
== ARM_PC_REGNUM
)
7262 warning (_("displaced: Unpredictable LDM or STM with "
7263 "base register r15"));
7264 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7265 "unpredictable ldm/stm", dsc
);
7268 if (debug_displaced
)
7269 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7270 "%.4x%.4x\n", insn1
, insn2
);
7272 /* Clear bit 13, since it should be always zero. */
7273 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7274 dsc
->u
.block
.rn
= rn
;
7276 dsc
->u
.block
.load
= load
;
7277 dsc
->u
.block
.user
= 0;
7278 dsc
->u
.block
.increment
= bit (insn1
, 7);
7279 dsc
->u
.block
.before
= bit (insn1
, 8);
7280 dsc
->u
.block
.writeback
= writeback
;
7281 dsc
->u
.block
.cond
= INST_AL
;
7282 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7286 if (dsc
->u
.block
.regmask
== 0xffff)
7288 /* This branch is impossible to happen. */
7293 unsigned int regmask
= dsc
->u
.block
.regmask
;
7294 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7295 unsigned int to
= 0, from
= 0, i
, new_rn
;
7297 for (i
= 0; i
< num_in_list
; i
++)
7298 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7303 new_regmask
= (1 << num_in_list
) - 1;
7305 if (debug_displaced
)
7306 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7307 "{..., pc}: original reg list %.4x, modified "
7308 "list %.4x\n"), rn
, writeback
? "!" : "",
7309 (int) dsc
->u
.block
.regmask
, new_regmask
);
7311 dsc
->modinsn
[0] = insn1
;
7312 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7315 dsc
->cleanup
= &cleanup_block_load_pc
;
7320 dsc
->modinsn
[0] = insn1
;
7321 dsc
->modinsn
[1] = insn2
;
7323 dsc
->cleanup
= &cleanup_block_store_pc
;
7328 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7329 for Linux, where some SVC instructions must be treated specially. */
7332 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7333 struct displaced_step_closure
*dsc
)
7335 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7337 if (debug_displaced
)
7338 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7339 "%.8lx\n", (unsigned long) resume_addr
);
7341 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7345 /* Common copy routine for svc instruciton. */
7348 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7349 struct displaced_step_closure
*dsc
)
7351 /* Preparation: none.
7352 Insn: unmodified svc.
7353 Cleanup: pc <- insn_addr + insn_size. */
7355 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7357 dsc
->wrote_to_pc
= 1;
7359 /* Allow OS-specific code to override SVC handling. */
7360 if (dsc
->u
.svc
.copy_svc_os
)
7361 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7364 dsc
->cleanup
= &cleanup_svc
;
7370 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7371 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7374 if (debug_displaced
)
7375 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7376 (unsigned long) insn
);
7378 dsc
->modinsn
[0] = insn
;
7380 return install_svc (gdbarch
, regs
, dsc
);
7384 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7385 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7388 if (debug_displaced
)
7389 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7392 dsc
->modinsn
[0] = insn
;
7394 return install_svc (gdbarch
, regs
, dsc
);
7397 /* Copy undefined instructions. */
7400 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7401 struct displaced_step_closure
*dsc
)
7403 if (debug_displaced
)
7404 fprintf_unfiltered (gdb_stdlog
,
7405 "displaced: copying undefined insn %.8lx\n",
7406 (unsigned long) insn
);
7408 dsc
->modinsn
[0] = insn
;
7414 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7415 struct displaced_step_closure
*dsc
)
7418 if (debug_displaced
)
7419 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7420 "%.4x %.4x\n", (unsigned short) insn1
,
7421 (unsigned short) insn2
);
7423 dsc
->modinsn
[0] = insn1
;
7424 dsc
->modinsn
[1] = insn2
;
7430 /* Copy unpredictable instructions. */
7433 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7434 struct displaced_step_closure
*dsc
)
7436 if (debug_displaced
)
7437 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7438 "%.8lx\n", (unsigned long) insn
);
7440 dsc
->modinsn
[0] = insn
;
7445 /* The decode_* functions are instruction decoding helpers. They mostly follow
7446 the presentation in the ARM ARM. */
7449 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7450 struct regcache
*regs
,
7451 struct displaced_step_closure
*dsc
)
7453 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7454 unsigned int rn
= bits (insn
, 16, 19);
7456 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7457 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7458 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7459 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7460 else if ((op1
& 0x60) == 0x20)
7461 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7462 else if ((op1
& 0x71) == 0x40)
7463 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7465 else if ((op1
& 0x77) == 0x41)
7466 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7467 else if ((op1
& 0x77) == 0x45)
7468 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7469 else if ((op1
& 0x77) == 0x51)
7472 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7474 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7476 else if ((op1
& 0x77) == 0x55)
7477 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7478 else if (op1
== 0x57)
7481 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7482 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7483 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7484 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7485 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7487 else if ((op1
& 0x63) == 0x43)
7488 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7489 else if ((op2
& 0x1) == 0x0)
7490 switch (op1
& ~0x80)
7493 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7495 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7496 case 0x71: case 0x75:
7498 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7499 case 0x63: case 0x67: case 0x73: case 0x77:
7500 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7502 return arm_copy_undef (gdbarch
, insn
, dsc
);
7505 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7509 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7510 struct regcache
*regs
,
7511 struct displaced_step_closure
*dsc
)
7513 if (bit (insn
, 27) == 0)
7514 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7515 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7516 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7519 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7522 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7524 case 0x4: case 0x5: case 0x6: case 0x7:
7525 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7528 switch ((insn
& 0xe00000) >> 21)
7530 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7532 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7535 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7538 return arm_copy_undef (gdbarch
, insn
, dsc
);
7543 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7544 switch ((insn
& 0xe00000) >> 21)
7547 /* ldc/ldc2 imm (undefined for rn == pc). */
7548 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7549 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7552 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7554 case 0x4: case 0x5: case 0x6: case 0x7:
7555 /* ldc/ldc2 lit (undefined for rn != pc). */
7556 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7557 : arm_copy_undef (gdbarch
, insn
, dsc
);
7560 return arm_copy_undef (gdbarch
, insn
, dsc
);
7565 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7568 if (bits (insn
, 16, 19) == 0xf)
7570 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7572 return arm_copy_undef (gdbarch
, insn
, dsc
);
7576 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7578 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7582 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7584 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7587 return arm_copy_undef (gdbarch
, insn
, dsc
);
7591 /* Decode miscellaneous instructions in dp/misc encoding space. */
7594 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7595 struct regcache
*regs
,
7596 struct displaced_step_closure
*dsc
)
7598 unsigned int op2
= bits (insn
, 4, 6);
7599 unsigned int op
= bits (insn
, 21, 22);
7600 unsigned int op1
= bits (insn
, 16, 19);
7605 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7608 if (op
== 0x1) /* bx. */
7609 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7611 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7613 return arm_copy_undef (gdbarch
, insn
, dsc
);
7617 /* Not really supported. */
7618 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7620 return arm_copy_undef (gdbarch
, insn
, dsc
);
7624 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7625 regs
, dsc
); /* blx register. */
7627 return arm_copy_undef (gdbarch
, insn
, dsc
);
7630 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7634 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7636 /* Not really supported. */
7637 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7640 return arm_copy_undef (gdbarch
, insn
, dsc
);
7645 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7646 struct regcache
*regs
,
7647 struct displaced_step_closure
*dsc
)
7650 switch (bits (insn
, 20, 24))
7653 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7656 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7658 case 0x12: case 0x16:
7659 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7662 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7666 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7668 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7669 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7670 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7671 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7672 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7673 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7674 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7675 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7676 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7677 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7678 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7679 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7680 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7681 /* 2nd arg means "unpriveleged". */
7682 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7686 /* Should be unreachable. */
7691 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7692 struct regcache
*regs
,
7693 struct displaced_step_closure
*dsc
)
7695 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7696 uint32_t op1
= bits (insn
, 20, 24);
7697 int rn_f
= bits (insn
, 16, 19) == 0xf;
7699 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7700 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7701 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7702 else if ((!a
&& (op1
& 0x17) == 0x02)
7703 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7704 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7705 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7706 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7707 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7708 else if ((!a
&& (op1
& 0x17) == 0x03)
7709 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7710 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7711 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7712 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7713 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7714 else if ((!a
&& (op1
& 0x17) == 0x06)
7715 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7716 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7717 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7718 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7719 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7720 else if ((!a
&& (op1
& 0x17) == 0x07)
7721 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7722 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7724 /* Should be unreachable. */
7729 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7730 struct displaced_step_closure
*dsc
)
7732 switch (bits (insn
, 20, 24))
7734 case 0x00: case 0x01: case 0x02: case 0x03:
7735 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7737 case 0x04: case 0x05: case 0x06: case 0x07:
7738 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7740 case 0x08: case 0x09: case 0x0a: case 0x0b:
7741 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7742 return arm_copy_unmodified (gdbarch
, insn
,
7743 "decode/pack/unpack/saturate/reverse", dsc
);
7746 if (bits (insn
, 5, 7) == 0) /* op2. */
7748 if (bits (insn
, 12, 15) == 0xf)
7749 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7751 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7754 return arm_copy_undef (gdbarch
, insn
, dsc
);
7756 case 0x1a: case 0x1b:
7757 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7758 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7760 return arm_copy_undef (gdbarch
, insn
, dsc
);
7762 case 0x1c: case 0x1d:
7763 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7765 if (bits (insn
, 0, 3) == 0xf)
7766 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7768 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7771 return arm_copy_undef (gdbarch
, insn
, dsc
);
7773 case 0x1e: case 0x1f:
7774 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7775 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7777 return arm_copy_undef (gdbarch
, insn
, dsc
);
7780 /* Should be unreachable. */
7785 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7786 struct regcache
*regs
,
7787 struct displaced_step_closure
*dsc
)
7790 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7792 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7796 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7797 struct regcache
*regs
,
7798 struct displaced_step_closure
*dsc
)
7800 unsigned int opcode
= bits (insn
, 20, 24);
7804 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7805 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7807 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7808 case 0x12: case 0x16:
7809 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7811 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7812 case 0x13: case 0x17:
7813 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7815 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7816 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7817 /* Note: no writeback for these instructions. Bit 25 will always be
7818 zero though (via caller), so the following works OK. */
7819 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7822 /* Should be unreachable. */
7826 /* Decode shifted register instructions. */
7829 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7830 uint16_t insn2
, struct regcache
*regs
,
7831 struct displaced_step_closure
*dsc
)
7833 /* PC is only allowed to be used in instruction MOV. */
7835 unsigned int op
= bits (insn1
, 5, 8);
7836 unsigned int rn
= bits (insn1
, 0, 3);
7838 if (op
== 0x2 && rn
== 0xf) /* MOV */
7839 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7841 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7842 "dp (shift reg)", dsc
);
7846 /* Decode extension register load/store. Exactly the same as
7847 arm_decode_ext_reg_ld_st. */
7850 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7851 uint16_t insn2
, struct regcache
*regs
,
7852 struct displaced_step_closure
*dsc
)
7854 unsigned int opcode
= bits (insn1
, 4, 8);
7858 case 0x04: case 0x05:
7859 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7860 "vfp/neon vmov", dsc
);
7862 case 0x08: case 0x0c: /* 01x00 */
7863 case 0x0a: case 0x0e: /* 01x10 */
7864 case 0x12: case 0x16: /* 10x10 */
7865 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7866 "vfp/neon vstm/vpush", dsc
);
7868 case 0x09: case 0x0d: /* 01x01 */
7869 case 0x0b: case 0x0f: /* 01x11 */
7870 case 0x13: case 0x17: /* 10x11 */
7871 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7872 "vfp/neon vldm/vpop", dsc
);
7874 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7875 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7877 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7878 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7881 /* Should be unreachable. */
7886 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7887 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7889 unsigned int op1
= bits (insn
, 20, 25);
7890 int op
= bit (insn
, 4);
7891 unsigned int coproc
= bits (insn
, 8, 11);
7892 unsigned int rn
= bits (insn
, 16, 19);
7894 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7895 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7896 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7897 && (coproc
& 0xe) != 0xa)
7899 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7900 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7901 && (coproc
& 0xe) != 0xa)
7902 /* ldc/ldc2 imm/lit. */
7903 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7904 else if ((op1
& 0x3e) == 0x00)
7905 return arm_copy_undef (gdbarch
, insn
, dsc
);
7906 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7907 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7908 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7909 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7910 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7911 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7912 else if ((op1
& 0x30) == 0x20 && !op
)
7914 if ((coproc
& 0xe) == 0xa)
7915 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7917 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7919 else if ((op1
& 0x30) == 0x20 && op
)
7920 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7921 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7922 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7923 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7924 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7925 else if ((op1
& 0x30) == 0x30)
7926 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7928 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7932 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7933 uint16_t insn2
, struct regcache
*regs
,
7934 struct displaced_step_closure
*dsc
)
7936 unsigned int coproc
= bits (insn2
, 8, 11);
7937 unsigned int op1
= bits (insn1
, 4, 9);
7938 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7939 unsigned int bit_9
= bit (insn1
, 9);
7940 unsigned int bit_4
= bit (insn1
, 4);
7941 unsigned int rn
= bits (insn1
, 0, 3);
7946 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7947 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7949 else if (bit_5_8
== 0) /* UNDEFINED. */
7950 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7953 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7954 if ((coproc
& 0xe) == 0xa)
7955 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7957 else /* coproc is not 101x. */
7959 if (bit_4
== 0) /* STC/STC2. */
7960 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7962 else /* LDC/LDC2 {literal, immeidate}. */
7963 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7969 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7975 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7976 struct displaced_step_closure
*dsc
, int rd
)
7982 Preparation: Rd <- PC
7988 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7989 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7993 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7994 struct displaced_step_closure
*dsc
,
7995 int rd
, unsigned int imm
)
7998 /* Encoding T2: ADDS Rd, #imm */
7999 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
8001 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8007 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
8008 struct regcache
*regs
,
8009 struct displaced_step_closure
*dsc
)
8011 unsigned int rd
= bits (insn
, 8, 10);
8012 unsigned int imm8
= bits (insn
, 0, 7);
8014 if (debug_displaced
)
8015 fprintf_unfiltered (gdb_stdlog
,
8016 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8019 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
8023 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
8024 uint16_t insn2
, struct regcache
*regs
,
8025 struct displaced_step_closure
*dsc
)
8027 unsigned int rd
= bits (insn2
, 8, 11);
8028 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8029 extract raw immediate encoding rather than computing immediate. When
8030 generating ADD or SUB instruction, we can simply perform OR operation to
8031 set immediate into ADD. */
8032 unsigned int imm_3_8
= insn2
& 0x70ff;
8033 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
8035 if (debug_displaced
)
8036 fprintf_unfiltered (gdb_stdlog
,
8037 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8038 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
8040 if (bit (insn1
, 7)) /* Encoding T2 */
8042 /* Encoding T3: SUB Rd, Rd, #imm */
8043 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
8044 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8046 else /* Encoding T3 */
8048 /* Encoding T3: ADD Rd, Rd, #imm */
8049 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
8050 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8054 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8060 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
8061 struct regcache
*regs
,
8062 struct displaced_step_closure
*dsc
)
8064 unsigned int rt
= bits (insn1
, 8, 10);
8066 int imm8
= (bits (insn1
, 0, 7) << 2);
8067 CORE_ADDR from
= dsc
->insn_addr
;
8073 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8075 Insn: LDR R0, [R2, R3];
8076 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8078 if (debug_displaced
)
8079 fprintf_unfiltered (gdb_stdlog
,
8080 "displaced: copying thumb ldr r%d [pc #%d]\n"
8083 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
8084 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
8085 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
8086 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8087 /* The assembler calculates the required value of the offset from the
8088 Align(PC,4) value of this instruction to the label. */
8089 pc
= pc
& 0xfffffffc;
8091 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
8092 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
8095 dsc
->u
.ldst
.xfersize
= 4;
8097 dsc
->u
.ldst
.immed
= 0;
8098 dsc
->u
.ldst
.writeback
= 0;
8099 dsc
->u
.ldst
.restore_r4
= 0;
8101 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8103 dsc
->cleanup
= &cleanup_load
;
8108 /* Copy Thumb cbnz/cbz insruction. */
8111 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
8112 struct regcache
*regs
,
8113 struct displaced_step_closure
*dsc
)
8115 int non_zero
= bit (insn1
, 11);
8116 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
8117 CORE_ADDR from
= dsc
->insn_addr
;
8118 int rn
= bits (insn1
, 0, 2);
8119 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
8121 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
8122 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8123 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8124 condition is false, let it be, cleanup_branch will do nothing. */
8125 if (dsc
->u
.branch
.cond
)
8127 dsc
->u
.branch
.cond
= INST_AL
;
8128 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
8131 dsc
->u
.branch
.dest
= from
+ 2;
8133 dsc
->u
.branch
.link
= 0;
8134 dsc
->u
.branch
.exchange
= 0;
8136 if (debug_displaced
)
8137 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
8138 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
8139 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
8141 dsc
->modinsn
[0] = THUMB_NOP
;
8143 dsc
->cleanup
= &cleanup_branch
;
8147 /* Copy Table Branch Byte/Halfword */
8149 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
8150 uint16_t insn2
, struct regcache
*regs
,
8151 struct displaced_step_closure
*dsc
)
8153 ULONGEST rn_val
, rm_val
;
8154 int is_tbh
= bit (insn2
, 4);
8155 CORE_ADDR halfwords
= 0;
8156 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8158 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
8159 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
8165 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
8166 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
8172 target_read_memory (rn_val
+ rm_val
, buf
, 1);
8173 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
8176 if (debug_displaced
)
8177 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
8178 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
8179 (unsigned int) rn_val
, (unsigned int) rm_val
,
8180 (unsigned int) halfwords
);
8182 dsc
->u
.branch
.cond
= INST_AL
;
8183 dsc
->u
.branch
.link
= 0;
8184 dsc
->u
.branch
.exchange
= 0;
8185 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
8187 dsc
->cleanup
= &cleanup_branch
;
8193 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8194 struct displaced_step_closure
*dsc
)
8197 int val
= displaced_read_reg (regs
, dsc
, 7);
8198 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8201 val
= displaced_read_reg (regs
, dsc
, 8);
8202 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8205 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8210 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8211 struct regcache
*regs
,
8212 struct displaced_step_closure
*dsc
)
8214 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8216 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8219 (1) register list is full, that is, r0-r7 are used.
8220 Prepare: tmp[0] <- r8
8222 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8223 MOV r8, r7; Move value of r7 to r8;
8224 POP {r7}; Store PC value into r7.
8226 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8228 (2) register list is not full, supposing there are N registers in
8229 register list (except PC, 0 <= N <= 7).
8230 Prepare: for each i, 0 - N, tmp[i] <- ri.
8232 POP {r0, r1, ...., rN};
8234 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8235 from tmp[] properly.
8237 if (debug_displaced
)
8238 fprintf_unfiltered (gdb_stdlog
,
8239 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8240 dsc
->u
.block
.regmask
, insn1
);
8242 if (dsc
->u
.block
.regmask
== 0xff)
8244 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8246 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8247 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8248 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8251 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8255 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8256 unsigned int new_regmask
, bit
= 1;
8257 unsigned int to
= 0, from
= 0, i
, new_rn
;
8259 for (i
= 0; i
< num_in_list
+ 1; i
++)
8260 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8262 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8264 if (debug_displaced
)
8265 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8266 "{..., pc}: original reg list %.4x,"
8267 " modified list %.4x\n"),
8268 (int) dsc
->u
.block
.regmask
, new_regmask
);
8270 dsc
->u
.block
.regmask
|= 0x8000;
8271 dsc
->u
.block
.writeback
= 0;
8272 dsc
->u
.block
.cond
= INST_AL
;
8274 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8276 dsc
->cleanup
= &cleanup_block_load_pc
;
8283 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8284 struct regcache
*regs
,
8285 struct displaced_step_closure
*dsc
)
8287 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8288 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8291 /* 16-bit thumb instructions. */
8292 switch (op_bit_12_15
)
8294 /* Shift (imme), add, subtract, move and compare. */
8295 case 0: case 1: case 2: case 3:
8296 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8297 "shift/add/sub/mov/cmp",
8301 switch (op_bit_10_11
)
8303 case 0: /* Data-processing */
8304 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8308 case 1: /* Special data instructions and branch and exchange. */
8310 unsigned short op
= bits (insn1
, 7, 9);
8311 if (op
== 6 || op
== 7) /* BX or BLX */
8312 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8313 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8314 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8316 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8320 default: /* LDR (literal) */
8321 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8324 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8325 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8328 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8329 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8330 else /* Generate SP-relative address */
8331 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8333 case 11: /* Misc 16-bit instructions */
8335 switch (bits (insn1
, 8, 11))
8337 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8338 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8340 case 12: case 13: /* POP */
8341 if (bit (insn1
, 8)) /* PC is in register list. */
8342 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8344 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8346 case 15: /* If-Then, and hints */
8347 if (bits (insn1
, 0, 3))
8348 /* If-Then makes up to four following instructions conditional.
8349 IT instruction itself is not conditional, so handle it as a
8350 common unmodified instruction. */
8351 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8354 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8357 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8362 if (op_bit_10_11
< 2) /* Store multiple registers */
8363 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8364 else /* Load multiple registers */
8365 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8367 case 13: /* Conditional branch and supervisor call */
8368 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8369 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8371 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8373 case 14: /* Unconditional branch */
8374 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8381 internal_error (__FILE__
, __LINE__
,
8382 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8386 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8387 uint16_t insn1
, uint16_t insn2
,
8388 struct regcache
*regs
,
8389 struct displaced_step_closure
*dsc
)
8391 int rt
= bits (insn2
, 12, 15);
8392 int rn
= bits (insn1
, 0, 3);
8393 int op1
= bits (insn1
, 7, 8);
8396 switch (bits (insn1
, 5, 6))
8398 case 0: /* Load byte and memory hints */
8399 if (rt
== 0xf) /* PLD/PLI */
8402 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8403 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8405 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8410 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8411 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8414 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8415 "ldrb{reg, immediate}/ldrbt",
8420 case 1: /* Load halfword and memory hints. */
8421 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8422 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8423 "pld/unalloc memhint", dsc
);
8427 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8430 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8434 case 2: /* Load word */
8436 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8439 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8440 else if (op1
== 0x1) /* Encoding T3 */
8441 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8443 else /* op1 == 0x0 */
8445 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8446 /* LDR (immediate) */
8447 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8448 dsc
, bit (insn2
, 8), 1);
8449 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8450 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8453 /* LDR (register) */
8454 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8460 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8467 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8468 uint16_t insn2
, struct regcache
*regs
,
8469 struct displaced_step_closure
*dsc
)
8472 unsigned short op
= bit (insn2
, 15);
8473 unsigned int op1
= bits (insn1
, 11, 12);
8479 switch (bits (insn1
, 9, 10))
8484 /* Load/store {dual, execlusive}, table branch. */
8485 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8486 && bits (insn2
, 5, 7) == 0)
8487 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8490 /* PC is not allowed to use in load/store {dual, exclusive}
8492 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8493 "load/store dual/ex", dsc
);
8495 else /* load/store multiple */
8497 switch (bits (insn1
, 7, 8))
8499 case 0: case 3: /* SRS, RFE */
8500 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8503 case 1: case 2: /* LDM/STM/PUSH/POP */
8504 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8511 /* Data-processing (shift register). */
8512 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8515 default: /* Coprocessor instructions. */
8516 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8521 case 2: /* op1 = 2 */
8522 if (op
) /* Branch and misc control. */
8524 if (bit (insn2
, 14) /* BLX/BL */
8525 || bit (insn2
, 12) /* Unconditional branch */
8526 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8527 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8529 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8534 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8536 int op
= bits (insn1
, 4, 8);
8537 int rn
= bits (insn1
, 0, 3);
8538 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8539 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8542 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8545 else /* Data processing (modified immeidate) */
8546 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8550 case 3: /* op1 = 3 */
8551 switch (bits (insn1
, 9, 10))
8555 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8557 else /* NEON Load/Store and Store single data item */
8558 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8559 "neon elt/struct load/store",
8562 case 1: /* op1 = 3, bits (9, 10) == 1 */
8563 switch (bits (insn1
, 7, 8))
8565 case 0: case 1: /* Data processing (register) */
8566 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8569 case 2: /* Multiply and absolute difference */
8570 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8571 "mul/mua/diff", dsc
);
8573 case 3: /* Long multiply and divide */
8574 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8579 default: /* Coprocessor instructions */
8580 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8589 internal_error (__FILE__
, __LINE__
,
8590 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8595 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8596 CORE_ADDR to
, struct regcache
*regs
,
8597 struct displaced_step_closure
*dsc
)
8599 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8601 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8603 if (debug_displaced
)
8604 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8605 "at %.8lx\n", insn1
, (unsigned long) from
);
8608 dsc
->insn_size
= thumb_insn_size (insn1
);
8609 if (thumb_insn_size (insn1
) == 4)
8612 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8613 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8616 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8620 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8621 CORE_ADDR to
, struct regcache
*regs
,
8622 struct displaced_step_closure
*dsc
)
8625 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8628 /* Most displaced instructions use a 1-instruction scratch space, so set this
8629 here and override below if/when necessary. */
8631 dsc
->insn_addr
= from
;
8632 dsc
->scratch_base
= to
;
8633 dsc
->cleanup
= NULL
;
8634 dsc
->wrote_to_pc
= 0;
8636 if (!displaced_in_arm_mode (regs
))
8637 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8641 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8642 if (debug_displaced
)
8643 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8644 "at %.8lx\n", (unsigned long) insn
,
8645 (unsigned long) from
);
8647 if ((insn
& 0xf0000000) == 0xf0000000)
8648 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8649 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8651 case 0x0: case 0x1: case 0x2: case 0x3:
8652 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8655 case 0x4: case 0x5: case 0x6:
8656 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8660 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8663 case 0x8: case 0x9: case 0xa: case 0xb:
8664 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8667 case 0xc: case 0xd: case 0xe: case 0xf:
8668 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8673 internal_error (__FILE__
, __LINE__
,
8674 _("arm_process_displaced_insn: Instruction decode error"));
8677 /* Actually set up the scratch space for a displaced instruction. */
8680 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8681 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8683 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8684 unsigned int i
, len
, offset
;
8685 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8686 int size
= dsc
->is_thumb
? 2 : 4;
8687 const gdb_byte
*bkp_insn
;
8690 /* Poke modified instruction(s). */
8691 for (i
= 0; i
< dsc
->numinsns
; i
++)
8693 if (debug_displaced
)
8695 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8697 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8700 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8701 (unsigned short)dsc
->modinsn
[i
]);
8703 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8704 (unsigned long) to
+ offset
);
8707 write_memory_unsigned_integer (to
+ offset
, size
,
8708 byte_order_for_code
,
8713 /* Choose the correct breakpoint instruction. */
8716 bkp_insn
= tdep
->thumb_breakpoint
;
8717 len
= tdep
->thumb_breakpoint_size
;
8721 bkp_insn
= tdep
->arm_breakpoint
;
8722 len
= tdep
->arm_breakpoint_size
;
8725 /* Put breakpoint afterwards. */
8726 write_memory (to
+ offset
, bkp_insn
, len
);
8728 if (debug_displaced
)
8729 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8730 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8733 /* Entry point for copying an instruction into scratch space for displaced
8736 struct displaced_step_closure
*
8737 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8738 CORE_ADDR from
, CORE_ADDR to
,
8739 struct regcache
*regs
)
8741 struct displaced_step_closure
*dsc
= XNEW (struct displaced_step_closure
);
8743 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8744 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8749 /* Entry point for cleaning things up after a displaced instruction has been
8753 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8754 struct displaced_step_closure
*dsc
,
8755 CORE_ADDR from
, CORE_ADDR to
,
8756 struct regcache
*regs
)
8759 dsc
->cleanup (gdbarch
, regs
, dsc
);
8761 if (!dsc
->wrote_to_pc
)
8762 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8763 dsc
->insn_addr
+ dsc
->insn_size
);
8767 #include "bfd-in2.h"
8768 #include "libcoff.h"
8771 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8773 struct gdbarch
*gdbarch
= info
->application_data
;
8775 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8777 static asymbol
*asym
;
8778 static combined_entry_type ce
;
8779 static struct coff_symbol_struct csym
;
8780 static struct bfd fake_bfd
;
8781 static bfd_target fake_target
;
8783 if (csym
.native
== NULL
)
8785 /* Create a fake symbol vector containing a Thumb symbol.
8786 This is solely so that the code in print_insn_little_arm()
8787 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8788 the presence of a Thumb symbol and switch to decoding
8789 Thumb instructions. */
8791 fake_target
.flavour
= bfd_target_coff_flavour
;
8792 fake_bfd
.xvec
= &fake_target
;
8793 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8795 csym
.symbol
.the_bfd
= &fake_bfd
;
8796 csym
.symbol
.name
= "fake";
8797 asym
= (asymbol
*) & csym
;
8800 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8801 info
->symbols
= &asym
;
8804 info
->symbols
= NULL
;
8806 if (info
->endian
== BFD_ENDIAN_BIG
)
8807 return print_insn_big_arm (memaddr
, info
);
8809 return print_insn_little_arm (memaddr
, info
);
8812 /* The following define instruction sequences that will cause ARM
8813 cpu's to take an undefined instruction trap. These are used to
8814 signal a breakpoint to GDB.
8816 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8817 modes. A different instruction is required for each mode. The ARM
8818 cpu's can also be big or little endian. Thus four different
8819 instructions are needed to support all cases.
8821 Note: ARMv4 defines several new instructions that will take the
8822 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8823 not in fact add the new instructions. The new undefined
8824 instructions in ARMv4 are all instructions that had no defined
8825 behaviour in earlier chips. There is no guarantee that they will
8826 raise an exception, but may be treated as NOP's. In practice, it
8827 may only safe to rely on instructions matching:
8829 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8830 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8831 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8833 Even this may only true if the condition predicate is true. The
8834 following use a condition predicate of ALWAYS so it is always TRUE.
8836 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8837 and NetBSD all use a software interrupt rather than an undefined
8838 instruction to force a trap. This can be handled by by the
8839 abi-specific code during establishment of the gdbarch vector. */
8841 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8842 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8843 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8844 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8846 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8847 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8848 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8849 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8851 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8852 the program counter value to determine whether a 16-bit or 32-bit
8853 breakpoint should be used. It returns a pointer to a string of
8854 bytes that encode a breakpoint instruction, stores the length of
8855 the string to *lenptr, and adjusts the program counter (if
8856 necessary) to point to the actual memory location where the
8857 breakpoint should be inserted. */
8859 static const unsigned char *
8860 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8863 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8865 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8867 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8869 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8870 check whether we are replacing a 32-bit instruction. */
8871 if (tdep
->thumb2_breakpoint
!= NULL
)
8874 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8876 unsigned short inst1
;
8877 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8878 if (thumb_insn_size (inst1
) == 4)
8880 *lenptr
= tdep
->thumb2_breakpoint_size
;
8881 return tdep
->thumb2_breakpoint
;
8886 *lenptr
= tdep
->thumb_breakpoint_size
;
8887 return tdep
->thumb_breakpoint
;
8891 *lenptr
= tdep
->arm_breakpoint_size
;
8892 return tdep
->arm_breakpoint
;
8897 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8900 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8902 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8903 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8904 that this is not confused with a 32-bit ARM breakpoint. */
8908 /* Extract from an array REGBUF containing the (raw) register state a
8909 function return value of type TYPE, and copy that, in virtual
8910 format, into VALBUF. */
8913 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8916 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8917 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8919 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8921 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8925 /* The value is in register F0 in internal format. We need to
8926 extract the raw value and then convert it to the desired
8928 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8930 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8931 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8932 valbuf
, gdbarch_byte_order (gdbarch
));
8936 case ARM_FLOAT_SOFT_FPA
:
8937 case ARM_FLOAT_SOFT_VFP
:
8938 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8939 not using the VFP ABI code. */
8941 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8942 if (TYPE_LENGTH (type
) > 4)
8943 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8944 valbuf
+ INT_REGISTER_SIZE
);
8948 internal_error (__FILE__
, __LINE__
,
8949 _("arm_extract_return_value: "
8950 "Floating point model not supported"));
8954 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8955 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8956 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8957 || TYPE_CODE (type
) == TYPE_CODE_PTR
8958 || TYPE_CODE (type
) == TYPE_CODE_REF
8959 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8961 /* If the type is a plain integer, then the access is
8962 straight-forward. Otherwise we have to play around a bit
8964 int len
= TYPE_LENGTH (type
);
8965 int regno
= ARM_A1_REGNUM
;
8970 /* By using store_unsigned_integer we avoid having to do
8971 anything special for small big-endian values. */
8972 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8973 store_unsigned_integer (valbuf
,
8974 (len
> INT_REGISTER_SIZE
8975 ? INT_REGISTER_SIZE
: len
),
8977 len
-= INT_REGISTER_SIZE
;
8978 valbuf
+= INT_REGISTER_SIZE
;
8983 /* For a structure or union the behaviour is as if the value had
8984 been stored to word-aligned memory and then loaded into
8985 registers with 32-bit load instruction(s). */
8986 int len
= TYPE_LENGTH (type
);
8987 int regno
= ARM_A1_REGNUM
;
8988 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8992 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8993 memcpy (valbuf
, tmpbuf
,
8994 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8995 len
-= INT_REGISTER_SIZE
;
8996 valbuf
+= INT_REGISTER_SIZE
;
9002 /* Will a function return an aggregate type in memory or in a
9003 register? Return 0 if an aggregate type can be returned in a
9004 register, 1 if it must be returned in memory. */
9007 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
9010 enum type_code code
;
9012 type
= check_typedef (type
);
9014 /* In the ARM ABI, "integer" like aggregate types are returned in
9015 registers. For an aggregate type to be integer like, its size
9016 must be less than or equal to INT_REGISTER_SIZE and the
9017 offset of each addressable subfield must be zero. Note that bit
9018 fields are not addressable, and all addressable subfields of
9019 unions always start at offset zero.
9021 This function is based on the behaviour of GCC 2.95.1.
9022 See: gcc/arm.c: arm_return_in_memory() for details.
9024 Note: All versions of GCC before GCC 2.95.2 do not set up the
9025 parameters correctly for a function returning the following
9026 structure: struct { float f;}; This should be returned in memory,
9027 not a register. Richard Earnshaw sent me a patch, but I do not
9028 know of any way to detect if a function like the above has been
9029 compiled with the correct calling convention. */
9031 /* All aggregate types that won't fit in a register must be returned
9033 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
9038 /* The AAPCS says all aggregates not larger than a word are returned
9040 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
9043 /* The only aggregate types that can be returned in a register are
9044 structs and unions. Arrays must be returned in memory. */
9045 code
= TYPE_CODE (type
);
9046 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
9051 /* Assume all other aggregate types can be returned in a register.
9052 Run a check for structures, unions and arrays. */
9055 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
9058 /* Need to check if this struct/union is "integer" like. For
9059 this to be true, its size must be less than or equal to
9060 INT_REGISTER_SIZE and the offset of each addressable
9061 subfield must be zero. Note that bit fields are not
9062 addressable, and unions always start at offset zero. If any
9063 of the subfields is a floating point type, the struct/union
9064 cannot be an integer type. */
9066 /* For each field in the object, check:
9067 1) Is it FP? --> yes, nRc = 1;
9068 2) Is it addressable (bitpos != 0) and
9069 not packed (bitsize == 0)?
9073 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
9075 enum type_code field_type_code
;
9076 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
9079 /* Is it a floating point type field? */
9080 if (field_type_code
== TYPE_CODE_FLT
)
9086 /* If bitpos != 0, then we have to care about it. */
9087 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
9089 /* Bitfields are not addressable. If the field bitsize is
9090 zero, then the field is not packed. Hence it cannot be
9091 a bitfield or any other packed type. */
9092 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
9104 /* Write into appropriate registers a function return value of type
9105 TYPE, given in virtual format. */
9108 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
9109 const gdb_byte
*valbuf
)
9111 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
9112 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9114 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
9116 gdb_byte buf
[MAX_REGISTER_SIZE
];
9118 switch (gdbarch_tdep (gdbarch
)->fp_model
)
9122 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
9123 gdbarch_byte_order (gdbarch
));
9124 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
9127 case ARM_FLOAT_SOFT_FPA
:
9128 case ARM_FLOAT_SOFT_VFP
:
9129 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9130 not using the VFP ABI code. */
9132 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
9133 if (TYPE_LENGTH (type
) > 4)
9134 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
9135 valbuf
+ INT_REGISTER_SIZE
);
9139 internal_error (__FILE__
, __LINE__
,
9140 _("arm_store_return_value: Floating "
9141 "point model not supported"));
9145 else if (TYPE_CODE (type
) == TYPE_CODE_INT
9146 || TYPE_CODE (type
) == TYPE_CODE_CHAR
9147 || TYPE_CODE (type
) == TYPE_CODE_BOOL
9148 || TYPE_CODE (type
) == TYPE_CODE_PTR
9149 || TYPE_CODE (type
) == TYPE_CODE_REF
9150 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
9152 if (TYPE_LENGTH (type
) <= 4)
9154 /* Values of one word or less are zero/sign-extended and
9156 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9157 LONGEST val
= unpack_long (type
, valbuf
);
9159 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
9160 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
9164 /* Integral values greater than one word are stored in consecutive
9165 registers starting with r0. This will always be a multiple of
9166 the regiser size. */
9167 int len
= TYPE_LENGTH (type
);
9168 int regno
= ARM_A1_REGNUM
;
9172 regcache_cooked_write (regs
, regno
++, valbuf
);
9173 len
-= INT_REGISTER_SIZE
;
9174 valbuf
+= INT_REGISTER_SIZE
;
9180 /* For a structure or union the behaviour is as if the value had
9181 been stored to word-aligned memory and then loaded into
9182 registers with 32-bit load instruction(s). */
9183 int len
= TYPE_LENGTH (type
);
9184 int regno
= ARM_A1_REGNUM
;
9185 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9189 memcpy (tmpbuf
, valbuf
,
9190 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9191 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9192 len
-= INT_REGISTER_SIZE
;
9193 valbuf
+= INT_REGISTER_SIZE
;
9199 /* Handle function return values. */
9201 static enum return_value_convention
9202 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9203 struct type
*valtype
, struct regcache
*regcache
,
9204 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9207 struct type
*func_type
= function
? value_type (function
) : NULL
;
9208 enum arm_vfp_cprc_base_type vfp_base_type
;
9211 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9212 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9214 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9215 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9217 for (i
= 0; i
< vfp_base_count
; i
++)
9219 if (reg_char
== 'q')
9222 arm_neon_quad_write (gdbarch
, regcache
, i
,
9223 writebuf
+ i
* unit_length
);
9226 arm_neon_quad_read (gdbarch
, regcache
, i
,
9227 readbuf
+ i
* unit_length
);
9234 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
9235 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9238 regcache_cooked_write (regcache
, regnum
,
9239 writebuf
+ i
* unit_length
);
9241 regcache_cooked_read (regcache
, regnum
,
9242 readbuf
+ i
* unit_length
);
9245 return RETURN_VALUE_REGISTER_CONVENTION
;
9248 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9249 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9250 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9252 if (tdep
->struct_return
== pcc_struct_return
9253 || arm_return_in_memory (gdbarch
, valtype
))
9254 return RETURN_VALUE_STRUCT_CONVENTION
;
9257 /* AAPCS returns complex types longer than a register in memory. */
9258 if (tdep
->arm_abi
!= ARM_ABI_APCS
9259 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9260 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9261 return RETURN_VALUE_STRUCT_CONVENTION
;
9264 arm_store_return_value (valtype
, regcache
, writebuf
);
9267 arm_extract_return_value (valtype
, regcache
, readbuf
);
9269 return RETURN_VALUE_REGISTER_CONVENTION
;
9274 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9276 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9278 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9280 gdb_byte buf
[INT_REGISTER_SIZE
];
9282 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9284 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9288 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9292 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9293 return the target PC. Otherwise return 0. */
9296 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9300 CORE_ADDR start_addr
;
9302 /* Find the starting address and name of the function containing the PC. */
9303 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9305 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9307 start_addr
= arm_skip_bx_reg (frame
, pc
);
9308 if (start_addr
!= 0)
9314 /* If PC is in a Thumb call or return stub, return the address of the
9315 target PC, which is in a register. The thunk functions are called
9316 _call_via_xx, where x is the register name. The possible names
9317 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9318 functions, named __ARM_call_via_r[0-7]. */
9319 if (startswith (name
, "_call_via_")
9320 || startswith (name
, "__ARM_call_via_"))
9322 /* Use the name suffix to determine which register contains the
9324 static char *table
[15] =
9325 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9326 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9329 int offset
= strlen (name
) - 2;
9331 for (regno
= 0; regno
<= 14; regno
++)
9332 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9333 return get_frame_register_unsigned (frame
, regno
);
9336 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9337 non-interworking calls to foo. We could decode the stubs
9338 to find the target but it's easier to use the symbol table. */
9339 namelen
= strlen (name
);
9340 if (name
[0] == '_' && name
[1] == '_'
9341 && ((namelen
> 2 + strlen ("_from_thumb")
9342 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
9343 || (namelen
> 2 + strlen ("_from_arm")
9344 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
9347 int target_len
= namelen
- 2;
9348 struct bound_minimal_symbol minsym
;
9349 struct objfile
*objfile
;
9350 struct obj_section
*sec
;
9352 if (name
[namelen
- 1] == 'b')
9353 target_len
-= strlen ("_from_thumb");
9355 target_len
-= strlen ("_from_arm");
9357 target_name
= (char *) alloca (target_len
+ 1);
9358 memcpy (target_name
, name
+ 2, target_len
);
9359 target_name
[target_len
] = '\0';
9361 sec
= find_pc_section (pc
);
9362 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9363 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9364 if (minsym
.minsym
!= NULL
)
9365 return BMSYMBOL_VALUE_ADDRESS (minsym
);
9370 return 0; /* not a stub */
9374 set_arm_command (char *args
, int from_tty
)
9376 printf_unfiltered (_("\
9377 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9378 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9382 show_arm_command (char *args
, int from_tty
)
9384 cmd_show_list (showarmcmdlist
, from_tty
, "");
9388 arm_update_current_architecture (void)
9390 struct gdbarch_info info
;
9392 /* If the current architecture is not ARM, we have nothing to do. */
9393 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9396 /* Update the architecture. */
9397 gdbarch_info_init (&info
);
9399 if (!gdbarch_update_p (info
))
9400 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9404 set_fp_model_sfunc (char *args
, int from_tty
,
9405 struct cmd_list_element
*c
)
9409 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9410 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9412 arm_fp_model
= (enum arm_float_model
) fp_model
;
9416 if (fp_model
== ARM_FLOAT_LAST
)
9417 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9420 arm_update_current_architecture ();
9424 show_fp_model (struct ui_file
*file
, int from_tty
,
9425 struct cmd_list_element
*c
, const char *value
)
9427 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9429 if (arm_fp_model
== ARM_FLOAT_AUTO
9430 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9431 fprintf_filtered (file
, _("\
9432 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9433 fp_model_strings
[tdep
->fp_model
]);
9435 fprintf_filtered (file
, _("\
9436 The current ARM floating point model is \"%s\".\n"),
9437 fp_model_strings
[arm_fp_model
]);
9441 arm_set_abi (char *args
, int from_tty
,
9442 struct cmd_list_element
*c
)
9446 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9447 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9449 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
9453 if (arm_abi
== ARM_ABI_LAST
)
9454 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9457 arm_update_current_architecture ();
9461 arm_show_abi (struct ui_file
*file
, int from_tty
,
9462 struct cmd_list_element
*c
, const char *value
)
9464 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9466 if (arm_abi_global
== ARM_ABI_AUTO
9467 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9468 fprintf_filtered (file
, _("\
9469 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9470 arm_abi_strings
[tdep
->arm_abi
]);
9472 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9477 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9478 struct cmd_list_element
*c
, const char *value
)
9480 fprintf_filtered (file
,
9481 _("The current execution mode assumed "
9482 "(when symbols are unavailable) is \"%s\".\n"),
9483 arm_fallback_mode_string
);
9487 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9488 struct cmd_list_element
*c
, const char *value
)
9490 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9492 fprintf_filtered (file
,
9493 _("The current execution mode assumed "
9494 "(even when symbols are available) is \"%s\".\n"),
9495 arm_force_mode_string
);
9498 /* If the user changes the register disassembly style used for info
9499 register and other commands, we have to also switch the style used
9500 in opcodes for disassembly output. This function is run in the "set
9501 arm disassembly" command, and does that. */
9504 set_disassembly_style_sfunc (char *args
, int from_tty
,
9505 struct cmd_list_element
*c
)
9507 set_disassembly_style ();
9510 /* Return the ARM register name corresponding to register I. */
9512 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9514 const int num_regs
= gdbarch_num_regs (gdbarch
);
9516 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9517 && i
>= num_regs
&& i
< num_regs
+ 32)
9519 static const char *const vfp_pseudo_names
[] = {
9520 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9521 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9522 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9523 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9526 return vfp_pseudo_names
[i
- num_regs
];
9529 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9530 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9532 static const char *const neon_pseudo_names
[] = {
9533 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9534 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9537 return neon_pseudo_names
[i
- num_regs
- 32];
9540 if (i
>= ARRAY_SIZE (arm_register_names
))
9541 /* These registers are only supported on targets which supply
9542 an XML description. */
9545 return arm_register_names
[i
];
9549 set_disassembly_style (void)
9553 /* Find the style that the user wants. */
9554 for (current
= 0; current
< num_disassembly_options
; current
++)
9555 if (disassembly_style
== valid_disassembly_styles
[current
])
9557 gdb_assert (current
< num_disassembly_options
);
9559 /* Synchronize the disassembler. */
9560 set_arm_regname_option (current
);
9563 /* Test whether the coff symbol specific value corresponds to a Thumb
9567 coff_sym_is_thumb (int val
)
9569 return (val
== C_THUMBEXT
9570 || val
== C_THUMBSTAT
9571 || val
== C_THUMBEXTFUNC
9572 || val
== C_THUMBSTATFUNC
9573 || val
== C_THUMBLABEL
);
9576 /* arm_coff_make_msymbol_special()
9577 arm_elf_make_msymbol_special()
9579 These functions test whether the COFF or ELF symbol corresponds to
9580 an address in thumb code, and set a "special" bit in a minimal
9581 symbol to indicate that it does. */
9584 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9586 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9587 == ST_BRANCH_TO_THUMB
)
9588 MSYMBOL_SET_SPECIAL (msym
);
9592 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9594 if (coff_sym_is_thumb (val
))
9595 MSYMBOL_SET_SPECIAL (msym
);
9599 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9601 struct arm_per_objfile
*data
= arg
;
9604 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9605 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9609 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9612 const char *name
= bfd_asymbol_name (sym
);
9613 struct arm_per_objfile
*data
;
9614 VEC(arm_mapping_symbol_s
) **map_p
;
9615 struct arm_mapping_symbol new_map_sym
;
9617 gdb_assert (name
[0] == '$');
9618 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9621 data
= objfile_data (objfile
, arm_objfile_data_key
);
9624 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9625 struct arm_per_objfile
);
9626 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9627 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9628 objfile
->obfd
->section_count
,
9629 VEC(arm_mapping_symbol_s
) *);
9631 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9633 new_map_sym
.value
= sym
->value
;
9634 new_map_sym
.type
= name
[1];
9636 /* Assume that most mapping symbols appear in order of increasing
9637 value. If they were randomly distributed, it would be faster to
9638 always push here and then sort at first use. */
9639 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9641 struct arm_mapping_symbol
*prev_map_sym
;
9643 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9644 if (prev_map_sym
->value
>= sym
->value
)
9647 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9648 arm_compare_mapping_symbols
);
9649 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9654 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9658 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9660 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9661 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9663 /* If necessary, set the T bit. */
9666 ULONGEST val
, t_bit
;
9667 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9668 t_bit
= arm_psr_thumb_bit (gdbarch
);
9669 if (arm_pc_is_thumb (gdbarch
, pc
))
9670 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9673 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9678 /* Read the contents of a NEON quad register, by reading from two
9679 double registers. This is used to implement the quad pseudo
9680 registers, and for argument passing in case the quad registers are
9681 missing; vectors are passed in quad registers when using the VFP
9682 ABI, even if a NEON unit is not present. REGNUM is the index of
9683 the quad register, in [0, 15]. */
9685 static enum register_status
9686 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9687 int regnum
, gdb_byte
*buf
)
9690 gdb_byte reg_buf
[8];
9691 int offset
, double_regnum
;
9692 enum register_status status
;
9694 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9695 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9698 /* d0 is always the least significant half of q0. */
9699 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9704 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9705 if (status
!= REG_VALID
)
9707 memcpy (buf
+ offset
, reg_buf
, 8);
9709 offset
= 8 - offset
;
9710 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9711 if (status
!= REG_VALID
)
9713 memcpy (buf
+ offset
, reg_buf
, 8);
9718 static enum register_status
9719 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9720 int regnum
, gdb_byte
*buf
)
9722 const int num_regs
= gdbarch_num_regs (gdbarch
);
9724 gdb_byte reg_buf
[8];
9725 int offset
, double_regnum
;
9727 gdb_assert (regnum
>= num_regs
);
9730 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9731 /* Quad-precision register. */
9732 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9735 enum register_status status
;
9737 /* Single-precision register. */
9738 gdb_assert (regnum
< 32);
9740 /* s0 is always the least significant half of d0. */
9741 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9742 offset
= (regnum
& 1) ? 0 : 4;
9744 offset
= (regnum
& 1) ? 4 : 0;
9746 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9747 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9750 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9751 if (status
== REG_VALID
)
9752 memcpy (buf
, reg_buf
+ offset
, 4);
9757 /* Store the contents of BUF to a NEON quad register, by writing to
9758 two double registers. This is used to implement the quad pseudo
9759 registers, and for argument passing in case the quad registers are
9760 missing; vectors are passed in quad registers when using the VFP
9761 ABI, even if a NEON unit is not present. REGNUM is the index
9762 of the quad register, in [0, 15]. */
9765 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9766 int regnum
, const gdb_byte
*buf
)
9769 int offset
, double_regnum
;
9771 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9772 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9775 /* d0 is always the least significant half of q0. */
9776 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9781 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9782 offset
= 8 - offset
;
9783 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9787 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9788 int regnum
, const gdb_byte
*buf
)
9790 const int num_regs
= gdbarch_num_regs (gdbarch
);
9792 gdb_byte reg_buf
[8];
9793 int offset
, double_regnum
;
9795 gdb_assert (regnum
>= num_regs
);
9798 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9799 /* Quad-precision register. */
9800 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9803 /* Single-precision register. */
9804 gdb_assert (regnum
< 32);
9806 /* s0 is always the least significant half of d0. */
9807 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9808 offset
= (regnum
& 1) ? 0 : 4;
9810 offset
= (regnum
& 1) ? 4 : 0;
9812 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9813 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9816 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9817 memcpy (reg_buf
+ offset
, buf
, 4);
9818 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9822 static struct value
*
9823 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9825 const int *reg_p
= baton
;
9826 return value_of_register (*reg_p
, frame
);
9829 static enum gdb_osabi
9830 arm_elf_osabi_sniffer (bfd
*abfd
)
9832 unsigned int elfosabi
;
9833 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9835 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9837 if (elfosabi
== ELFOSABI_ARM
)
9838 /* GNU tools use this value. Check note sections in this case,
9840 bfd_map_over_sections (abfd
,
9841 generic_elf_osabi_sniff_abi_tag_sections
,
9844 /* Anything else will be handled by the generic ELF sniffer. */
9849 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9850 struct reggroup
*group
)
9852 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9853 this, FPS register belongs to save_regroup, restore_reggroup, and
9854 all_reggroup, of course. */
9855 if (regnum
== ARM_FPS_REGNUM
)
9856 return (group
== float_reggroup
9857 || group
== save_reggroup
9858 || group
== restore_reggroup
9859 || group
== all_reggroup
);
9861 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9865 /* For backward-compatibility we allow two 'g' packet lengths with
9866 the remote protocol depending on whether FPA registers are
9867 supplied. M-profile targets do not have FPA registers, but some
9868 stubs already exist in the wild which use a 'g' packet which
9869 supplies them albeit with dummy values. The packet format which
9870 includes FPA registers should be considered deprecated for
9871 M-profile targets. */
9874 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9876 if (gdbarch_tdep (gdbarch
)->is_m
)
9878 /* If we know from the executable this is an M-profile target,
9879 cater for remote targets whose register set layout is the
9880 same as the FPA layout. */
9881 register_remote_g_packet_guess (gdbarch
,
9882 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9883 (16 * INT_REGISTER_SIZE
)
9884 + (8 * FP_REGISTER_SIZE
)
9885 + (2 * INT_REGISTER_SIZE
),
9886 tdesc_arm_with_m_fpa_layout
);
9888 /* The regular M-profile layout. */
9889 register_remote_g_packet_guess (gdbarch
,
9890 /* r0-r12,sp,lr,pc; xpsr */
9891 (16 * INT_REGISTER_SIZE
)
9892 + INT_REGISTER_SIZE
,
9895 /* M-profile plus M4F VFP. */
9896 register_remote_g_packet_guess (gdbarch
,
9897 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9898 (16 * INT_REGISTER_SIZE
)
9899 + (16 * VFP_REGISTER_SIZE
)
9900 + (2 * INT_REGISTER_SIZE
),
9901 tdesc_arm_with_m_vfp_d16
);
9904 /* Otherwise we don't have a useful guess. */
9908 /* Initialize the current architecture based on INFO. If possible,
9909 re-use an architecture from ARCHES, which is a list of
9910 architectures already created during this debugging session.
9912 Called e.g. at program startup, when reading a core file, and when
9913 reading a binary file. */
9915 static struct gdbarch
*
9916 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9918 struct gdbarch_tdep
*tdep
;
9919 struct gdbarch
*gdbarch
;
9920 struct gdbarch_list
*best_arch
;
9921 enum arm_abi_kind arm_abi
= arm_abi_global
;
9922 enum arm_float_model fp_model
= arm_fp_model
;
9923 struct tdesc_arch_data
*tdesc_data
= NULL
;
9925 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9926 int have_wmmx_registers
= 0;
9928 int have_fpa_registers
= 1;
9929 const struct target_desc
*tdesc
= info
.target_desc
;
9931 /* If we have an object to base this architecture on, try to determine
9934 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9936 int ei_osabi
, e_flags
;
9938 switch (bfd_get_flavour (info
.abfd
))
9940 case bfd_target_aout_flavour
:
9941 /* Assume it's an old APCS-style ABI. */
9942 arm_abi
= ARM_ABI_APCS
;
9945 case bfd_target_coff_flavour
:
9946 /* Assume it's an old APCS-style ABI. */
9948 arm_abi
= ARM_ABI_APCS
;
9951 case bfd_target_elf_flavour
:
9952 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9953 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9955 if (ei_osabi
== ELFOSABI_ARM
)
9957 /* GNU tools used to use this value, but do not for EABI
9958 objects. There's nowhere to tag an EABI version
9959 anyway, so assume APCS. */
9960 arm_abi
= ARM_ABI_APCS
;
9962 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9964 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9965 int attr_arch
, attr_profile
;
9969 case EF_ARM_EABI_UNKNOWN
:
9970 /* Assume GNU tools. */
9971 arm_abi
= ARM_ABI_APCS
;
9974 case EF_ARM_EABI_VER4
:
9975 case EF_ARM_EABI_VER5
:
9976 arm_abi
= ARM_ABI_AAPCS
;
9977 /* EABI binaries default to VFP float ordering.
9978 They may also contain build attributes that can
9979 be used to identify if the VFP argument-passing
9981 if (fp_model
== ARM_FLOAT_AUTO
)
9984 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9988 case AEABI_VFP_args_base
:
9989 /* "The user intended FP parameter/result
9990 passing to conform to AAPCS, base
9992 fp_model
= ARM_FLOAT_SOFT_VFP
;
9994 case AEABI_VFP_args_vfp
:
9995 /* "The user intended FP parameter/result
9996 passing to conform to AAPCS, VFP
9998 fp_model
= ARM_FLOAT_VFP
;
10000 case AEABI_VFP_args_toolchain
:
10001 /* "The user intended FP parameter/result
10002 passing to conform to tool chain-specific
10003 conventions" - we don't know any such
10004 conventions, so leave it as "auto". */
10006 case AEABI_VFP_args_compatible
:
10007 /* "Code is compatible with both the base
10008 and VFP variants; the user did not permit
10009 non-variadic functions to pass FP
10010 parameters/results" - leave it as
10014 /* Attribute value not mentioned in the
10015 November 2012 ABI, so leave it as
10020 fp_model
= ARM_FLOAT_SOFT_VFP
;
10026 /* Leave it as "auto". */
10027 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
10032 /* Detect M-profile programs. This only works if the
10033 executable file includes build attributes; GCC does
10034 copy them to the executable, but e.g. RealView does
10036 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
10038 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
10040 Tag_CPU_arch_profile
);
10041 /* GCC specifies the profile for v6-M; RealView only
10042 specifies the profile for architectures starting with
10043 V7 (as opposed to architectures with a tag
10044 numerically greater than TAG_CPU_ARCH_V7). */
10045 if (!tdesc_has_registers (tdesc
)
10046 && (attr_arch
== TAG_CPU_ARCH_V6_M
10047 || attr_arch
== TAG_CPU_ARCH_V6S_M
10048 || attr_profile
== 'M'))
10053 if (fp_model
== ARM_FLOAT_AUTO
)
10055 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
10057 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
10060 /* Leave it as "auto". Strictly speaking this case
10061 means FPA, but almost nobody uses that now, and
10062 many toolchains fail to set the appropriate bits
10063 for the floating-point model they use. */
10065 case EF_ARM_SOFT_FLOAT
:
10066 fp_model
= ARM_FLOAT_SOFT_FPA
;
10068 case EF_ARM_VFP_FLOAT
:
10069 fp_model
= ARM_FLOAT_VFP
;
10071 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
10072 fp_model
= ARM_FLOAT_SOFT_VFP
;
10077 if (e_flags
& EF_ARM_BE8
)
10078 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
10083 /* Leave it as "auto". */
10088 /* Check any target description for validity. */
10089 if (tdesc_has_registers (tdesc
))
10091 /* For most registers we require GDB's default names; but also allow
10092 the numeric names for sp / lr / pc, as a convenience. */
10093 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
10094 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
10095 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
10097 const struct tdesc_feature
*feature
;
10100 feature
= tdesc_find_feature (tdesc
,
10101 "org.gnu.gdb.arm.core");
10102 if (feature
== NULL
)
10104 feature
= tdesc_find_feature (tdesc
,
10105 "org.gnu.gdb.arm.m-profile");
10106 if (feature
== NULL
)
10112 tdesc_data
= tdesc_data_alloc ();
10115 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
10116 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10117 arm_register_names
[i
]);
10118 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10121 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10124 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10128 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10129 ARM_PS_REGNUM
, "xpsr");
10131 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10132 ARM_PS_REGNUM
, "cpsr");
10136 tdesc_data_cleanup (tdesc_data
);
10140 feature
= tdesc_find_feature (tdesc
,
10141 "org.gnu.gdb.arm.fpa");
10142 if (feature
!= NULL
)
10145 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
10146 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10147 arm_register_names
[i
]);
10150 tdesc_data_cleanup (tdesc_data
);
10155 have_fpa_registers
= 0;
10157 feature
= tdesc_find_feature (tdesc
,
10158 "org.gnu.gdb.xscale.iwmmxt");
10159 if (feature
!= NULL
)
10161 static const char *const iwmmxt_names
[] = {
10162 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10163 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10164 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10165 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10169 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
10171 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10172 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10174 /* Check for the control registers, but do not fail if they
10176 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
10177 tdesc_numbered_register (feature
, tdesc_data
, i
,
10178 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10180 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
10182 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10183 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10187 tdesc_data_cleanup (tdesc_data
);
10191 have_wmmx_registers
= 1;
10194 /* If we have a VFP unit, check whether the single precision registers
10195 are present. If not, then we will synthesize them as pseudo
10197 feature
= tdesc_find_feature (tdesc
,
10198 "org.gnu.gdb.arm.vfp");
10199 if (feature
!= NULL
)
10201 static const char *const vfp_double_names
[] = {
10202 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10203 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10204 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10205 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10208 /* Require the double precision registers. There must be either
10211 for (i
= 0; i
< 32; i
++)
10213 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10215 vfp_double_names
[i
]);
10219 if (!valid_p
&& i
== 16)
10222 /* Also require FPSCR. */
10223 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10224 ARM_FPSCR_REGNUM
, "fpscr");
10227 tdesc_data_cleanup (tdesc_data
);
10231 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10232 have_vfp_pseudos
= 1;
10234 vfp_register_count
= i
;
10236 /* If we have VFP, also check for NEON. The architecture allows
10237 NEON without VFP (integer vector operations only), but GDB
10238 does not support that. */
10239 feature
= tdesc_find_feature (tdesc
,
10240 "org.gnu.gdb.arm.neon");
10241 if (feature
!= NULL
)
10243 /* NEON requires 32 double-precision registers. */
10246 tdesc_data_cleanup (tdesc_data
);
10250 /* If there are quad registers defined by the stub, use
10251 their type; otherwise (normally) provide them with
10252 the default type. */
10253 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10254 have_neon_pseudos
= 1;
10261 /* If there is already a candidate, use it. */
10262 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10264 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10266 if (arm_abi
!= ARM_ABI_AUTO
10267 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10270 if (fp_model
!= ARM_FLOAT_AUTO
10271 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10274 /* There are various other properties in tdep that we do not
10275 need to check here: those derived from a target description,
10276 since gdbarches with a different target description are
10277 automatically disqualified. */
10279 /* Do check is_m, though, since it might come from the binary. */
10280 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10283 /* Found a match. */
10287 if (best_arch
!= NULL
)
10289 if (tdesc_data
!= NULL
)
10290 tdesc_data_cleanup (tdesc_data
);
10291 return best_arch
->gdbarch
;
10294 tdep
= XCNEW (struct gdbarch_tdep
);
10295 gdbarch
= gdbarch_alloc (&info
, tdep
);
10297 /* Record additional information about the architecture we are defining.
10298 These are gdbarch discriminators, like the OSABI. */
10299 tdep
->arm_abi
= arm_abi
;
10300 tdep
->fp_model
= fp_model
;
10302 tdep
->have_fpa_registers
= have_fpa_registers
;
10303 tdep
->have_wmmx_registers
= have_wmmx_registers
;
10304 gdb_assert (vfp_register_count
== 0
10305 || vfp_register_count
== 16
10306 || vfp_register_count
== 32);
10307 tdep
->vfp_register_count
= vfp_register_count
;
10308 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10309 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10310 tdep
->have_neon
= have_neon
;
10312 arm_register_g_packet_guesses (gdbarch
);
10315 switch (info
.byte_order_for_code
)
10317 case BFD_ENDIAN_BIG
:
10318 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10319 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10320 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10321 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10325 case BFD_ENDIAN_LITTLE
:
10326 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10327 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10328 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10329 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10334 internal_error (__FILE__
, __LINE__
,
10335 _("arm_gdbarch_init: bad byte order for float format"));
10338 /* On ARM targets char defaults to unsigned. */
10339 set_gdbarch_char_signed (gdbarch
, 0);
10341 /* Note: for displaced stepping, this includes the breakpoint, and one word
10342 of additional scratch space. This setting isn't used for anything beside
10343 displaced stepping at present. */
10344 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10346 /* This should be low enough for everything. */
10347 tdep
->lowest_pc
= 0x20;
10348 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10350 /* The default, for both APCS and AAPCS, is to return small
10351 structures in registers. */
10352 tdep
->struct_return
= reg_struct_return
;
10354 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10355 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10357 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10359 /* Frame handling. */
10360 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10361 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10362 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10364 frame_base_set_default (gdbarch
, &arm_normal_base
);
10366 /* Address manipulation. */
10367 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10369 /* Advance PC across function entry code. */
10370 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10372 /* Detect whether PC is at a point where the stack has been destroyed. */
10373 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
10375 /* Skip trampolines. */
10376 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10378 /* The stack grows downward. */
10379 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10381 /* Breakpoint manipulation. */
10382 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10383 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10384 arm_remote_breakpoint_from_pc
);
10386 /* Information about registers, etc. */
10387 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10388 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10389 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10390 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10391 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10393 /* This "info float" is FPA-specific. Use the generic version if we
10394 do not have FPA. */
10395 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10396 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10398 /* Internal <-> external register number maps. */
10399 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10400 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10402 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10404 /* Returning results. */
10405 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10408 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10410 /* Minsymbol frobbing. */
10411 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10412 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10413 arm_coff_make_msymbol_special
);
10414 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10416 /* Thumb-2 IT block support. */
10417 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10418 arm_adjust_breakpoint_address
);
10420 /* Virtual tables. */
10421 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10423 /* Hook in the ABI-specific overrides, if they have been registered. */
10424 gdbarch_init_osabi (info
, gdbarch
);
10426 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10428 /* Add some default predicates. */
10430 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10431 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10432 dwarf2_append_unwinders (gdbarch
);
10433 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10434 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10436 /* Now we have tuned the configuration, set a few final things,
10437 based on what the OS ABI has told us. */
10439 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10440 binaries are always marked. */
10441 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10442 tdep
->arm_abi
= ARM_ABI_APCS
;
10444 /* Watchpoints are not steppable. */
10445 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10447 /* We used to default to FPA for generic ARM, but almost nobody
10448 uses that now, and we now provide a way for the user to force
10449 the model. So default to the most useful variant. */
10450 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10451 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10453 if (tdep
->jb_pc
>= 0)
10454 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10456 /* Floating point sizes and format. */
10457 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10458 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10460 set_gdbarch_double_format
10461 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10462 set_gdbarch_long_double_format
10463 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10467 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10468 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10471 if (have_vfp_pseudos
)
10473 /* NOTE: These are the only pseudo registers used by
10474 the ARM target at the moment. If more are added, a
10475 little more care in numbering will be needed. */
10477 int num_pseudos
= 32;
10478 if (have_neon_pseudos
)
10480 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10481 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10482 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10487 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10489 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10491 /* Override tdesc_register_type to adjust the types of VFP
10492 registers for NEON. */
10493 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10496 /* Add standard register aliases. We add aliases even for those
10497 nanes which are used by the current architecture - it's simpler,
10498 and does no harm, since nothing ever lists user registers. */
10499 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10500 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10501 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10507 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10514 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10515 (unsigned long) tdep
->lowest_pc
);
10518 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10521 _initialize_arm_tdep (void)
10523 struct ui_file
*stb
;
10525 struct cmd_list_element
*new_set
, *new_show
;
10526 const char *setname
;
10527 const char *setdesc
;
10528 const char *const *regnames
;
10530 static char *helptext
;
10531 char regdesc
[1024], *rdptr
= regdesc
;
10532 size_t rest
= sizeof (regdesc
);
10534 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10536 arm_objfile_data_key
10537 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10539 /* Add ourselves to objfile event chain. */
10540 observer_attach_new_objfile (arm_exidx_new_objfile
);
10542 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10544 /* Register an ELF OS ABI sniffer for ARM binaries. */
10545 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10546 bfd_target_elf_flavour
,
10547 arm_elf_osabi_sniffer
);
10549 /* Initialize the standard target descriptions. */
10550 initialize_tdesc_arm_with_m ();
10551 initialize_tdesc_arm_with_m_fpa_layout ();
10552 initialize_tdesc_arm_with_m_vfp_d16 ();
10553 initialize_tdesc_arm_with_iwmmxt ();
10554 initialize_tdesc_arm_with_vfpv2 ();
10555 initialize_tdesc_arm_with_vfpv3 ();
10556 initialize_tdesc_arm_with_neon ();
10558 /* Get the number of possible sets of register names defined in opcodes. */
10559 num_disassembly_options
= get_arm_regname_num_options ();
10561 /* Add root prefix command for all "set arm"/"show arm" commands. */
10562 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10563 _("Various ARM-specific commands."),
10564 &setarmcmdlist
, "set arm ", 0, &setlist
);
10566 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10567 _("Various ARM-specific commands."),
10568 &showarmcmdlist
, "show arm ", 0, &showlist
);
10570 /* Sync the opcode insn printer with our register viewer. */
10571 parse_arm_disassembler_option ("reg-names-std");
10573 /* Initialize the array that will be passed to
10574 add_setshow_enum_cmd(). */
10575 valid_disassembly_styles
= XNEWVEC (const char *,
10576 num_disassembly_options
+ 1);
10577 for (i
= 0; i
< num_disassembly_options
; i
++)
10579 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10580 valid_disassembly_styles
[i
] = setname
;
10581 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10584 /* When we find the default names, tell the disassembler to use
10586 if (!strcmp (setname
, "std"))
10588 disassembly_style
= setname
;
10589 set_arm_regname_option (i
);
10592 /* Mark the end of valid options. */
10593 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10595 /* Create the help text. */
10596 stb
= mem_fileopen ();
10597 fprintf_unfiltered (stb
, "%s%s%s",
10598 _("The valid values are:\n"),
10600 _("The default is \"std\"."));
10601 helptext
= ui_file_xstrdup (stb
, NULL
);
10602 ui_file_delete (stb
);
10604 add_setshow_enum_cmd("disassembler", no_class
,
10605 valid_disassembly_styles
, &disassembly_style
,
10606 _("Set the disassembly style."),
10607 _("Show the disassembly style."),
10609 set_disassembly_style_sfunc
,
10610 NULL
, /* FIXME: i18n: The disassembly style is
10612 &setarmcmdlist
, &showarmcmdlist
);
10614 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10615 _("Set usage of ARM 32-bit mode."),
10616 _("Show usage of ARM 32-bit mode."),
10617 _("When off, a 26-bit PC will be used."),
10619 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10621 &setarmcmdlist
, &showarmcmdlist
);
10623 /* Add a command to allow the user to force the FPU model. */
10624 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10625 _("Set the floating point type."),
10626 _("Show the floating point type."),
10627 _("auto - Determine the FP typefrom the OS-ABI.\n\
10628 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10629 fpa - FPA co-processor (GCC compiled).\n\
10630 softvfp - Software FP with pure-endian doubles.\n\
10631 vfp - VFP co-processor."),
10632 set_fp_model_sfunc
, show_fp_model
,
10633 &setarmcmdlist
, &showarmcmdlist
);
10635 /* Add a command to allow the user to force the ABI. */
10636 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10638 _("Show the ABI."),
10639 NULL
, arm_set_abi
, arm_show_abi
,
10640 &setarmcmdlist
, &showarmcmdlist
);
10642 /* Add two commands to allow the user to force the assumed
10644 add_setshow_enum_cmd ("fallback-mode", class_support
,
10645 arm_mode_strings
, &arm_fallback_mode_string
,
10646 _("Set the mode assumed when symbols are unavailable."),
10647 _("Show the mode assumed when symbols are unavailable."),
10648 NULL
, NULL
, arm_show_fallback_mode
,
10649 &setarmcmdlist
, &showarmcmdlist
);
10650 add_setshow_enum_cmd ("force-mode", class_support
,
10651 arm_mode_strings
, &arm_force_mode_string
,
10652 _("Set the mode assumed even when symbols are available."),
10653 _("Show the mode assumed even when symbols are available."),
10654 NULL
, NULL
, arm_show_force_mode
,
10655 &setarmcmdlist
, &showarmcmdlist
);
10657 /* Debugging flag. */
10658 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10659 _("Set ARM debugging."),
10660 _("Show ARM debugging."),
10661 _("When on, arm-specific debugging is enabled."),
10663 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10664 &setdebuglist
, &showdebuglist
);
10667 /* ARM-reversible process record data structures. */
10669 #define ARM_INSN_SIZE_BYTES 4
10670 #define THUMB_INSN_SIZE_BYTES 2
10671 #define THUMB2_INSN_SIZE_BYTES 4
10674 /* Position of the bit within a 32-bit ARM instruction
10675 that defines whether the instruction is a load or store. */
10676 #define INSN_S_L_BIT_NUM 20
10678 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10681 unsigned int reg_len = LENGTH; \
10684 REGS = XNEWVEC (uint32_t, reg_len); \
10685 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10690 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10693 unsigned int mem_len = LENGTH; \
10696 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10697 memcpy(&MEMS->len, &RECORD_BUF[0], \
10698 sizeof(struct arm_mem_r) * LENGTH); \
10703 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10704 #define INSN_RECORDED(ARM_RECORD) \
10705 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10707 /* ARM memory record structure. */
10710 uint32_t len
; /* Record length. */
10711 uint32_t addr
; /* Memory address. */
10714 /* ARM instruction record contains opcode of current insn
10715 and execution state (before entry to decode_insn()),
10716 contains list of to-be-modified registers and
10717 memory blocks (on return from decode_insn()). */
10719 typedef struct insn_decode_record_t
10721 struct gdbarch
*gdbarch
;
10722 struct regcache
*regcache
;
10723 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10724 uint32_t arm_insn
; /* Should accommodate thumb. */
10725 uint32_t cond
; /* Condition code. */
10726 uint32_t opcode
; /* Insn opcode. */
10727 uint32_t decode
; /* Insn decode bits. */
10728 uint32_t mem_rec_count
; /* No of mem records. */
10729 uint32_t reg_rec_count
; /* No of reg records. */
10730 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10731 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10732 } insn_decode_record
;
10735 /* Checks ARM SBZ and SBO mandatory fields. */
10738 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10740 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10759 enum arm_record_result
10761 ARM_RECORD_SUCCESS
= 0,
10762 ARM_RECORD_FAILURE
= 1
10769 } arm_record_strx_t
;
10780 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10781 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10784 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10785 ULONGEST u_regval
[2]= {0};
10787 uint32_t reg_src1
= 0, reg_src2
= 0;
10788 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10789 uint32_t opcode1
= 0;
10791 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10792 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10793 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10796 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10798 /* 1) Handle misc store, immediate offset. */
10799 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10800 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10801 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10802 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10804 if (ARM_PC_REGNUM
== reg_src1
)
10806 /* If R15 was used as Rn, hence current PC+8. */
10807 u_regval
[0] = u_regval
[0] + 8;
10809 offset_8
= (immed_high
<< 4) | immed_low
;
10810 /* Calculate target store address. */
10811 if (14 == arm_insn_r
->opcode
)
10813 tgt_mem_addr
= u_regval
[0] + offset_8
;
10817 tgt_mem_addr
= u_regval
[0] - offset_8
;
10819 if (ARM_RECORD_STRH
== str_type
)
10821 record_buf_mem
[0] = 2;
10822 record_buf_mem
[1] = tgt_mem_addr
;
10823 arm_insn_r
->mem_rec_count
= 1;
10825 else if (ARM_RECORD_STRD
== str_type
)
10827 record_buf_mem
[0] = 4;
10828 record_buf_mem
[1] = tgt_mem_addr
;
10829 record_buf_mem
[2] = 4;
10830 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10831 arm_insn_r
->mem_rec_count
= 2;
10834 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10836 /* 2) Store, register offset. */
10838 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10840 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10841 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10842 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10843 if (15 == reg_src2
)
10845 /* If R15 was used as Rn, hence current PC+8. */
10846 u_regval
[0] = u_regval
[0] + 8;
10848 /* Calculate target store address, Rn +/- Rm, register offset. */
10849 if (12 == arm_insn_r
->opcode
)
10851 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10855 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10857 if (ARM_RECORD_STRH
== str_type
)
10859 record_buf_mem
[0] = 2;
10860 record_buf_mem
[1] = tgt_mem_addr
;
10861 arm_insn_r
->mem_rec_count
= 1;
10863 else if (ARM_RECORD_STRD
== str_type
)
10865 record_buf_mem
[0] = 4;
10866 record_buf_mem
[1] = tgt_mem_addr
;
10867 record_buf_mem
[2] = 4;
10868 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10869 arm_insn_r
->mem_rec_count
= 2;
10872 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10873 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10875 /* 3) Store, immediate pre-indexed. */
10876 /* 5) Store, immediate post-indexed. */
10877 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10878 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10879 offset_8
= (immed_high
<< 4) | immed_low
;
10880 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10881 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10882 /* Calculate target store address, Rn +/- Rm, register offset. */
10883 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10885 tgt_mem_addr
= u_regval
[0] + offset_8
;
10889 tgt_mem_addr
= u_regval
[0] - offset_8
;
10891 if (ARM_RECORD_STRH
== str_type
)
10893 record_buf_mem
[0] = 2;
10894 record_buf_mem
[1] = tgt_mem_addr
;
10895 arm_insn_r
->mem_rec_count
= 1;
10897 else if (ARM_RECORD_STRD
== str_type
)
10899 record_buf_mem
[0] = 4;
10900 record_buf_mem
[1] = tgt_mem_addr
;
10901 record_buf_mem
[2] = 4;
10902 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10903 arm_insn_r
->mem_rec_count
= 2;
10905 /* Record Rn also as it changes. */
10906 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10907 arm_insn_r
->reg_rec_count
= 1;
10909 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10910 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10912 /* 4) Store, register pre-indexed. */
10913 /* 6) Store, register post -indexed. */
10914 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10915 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10916 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10917 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10918 /* Calculate target store address, Rn +/- Rm, register offset. */
10919 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10921 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10925 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10927 if (ARM_RECORD_STRH
== str_type
)
10929 record_buf_mem
[0] = 2;
10930 record_buf_mem
[1] = tgt_mem_addr
;
10931 arm_insn_r
->mem_rec_count
= 1;
10933 else if (ARM_RECORD_STRD
== str_type
)
10935 record_buf_mem
[0] = 4;
10936 record_buf_mem
[1] = tgt_mem_addr
;
10937 record_buf_mem
[2] = 4;
10938 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10939 arm_insn_r
->mem_rec_count
= 2;
10941 /* Record Rn also as it changes. */
10942 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10943 arm_insn_r
->reg_rec_count
= 1;
10948 /* Handling ARM extension space insns. */
10951 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10953 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10954 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10955 uint32_t record_buf
[8], record_buf_mem
[8];
10956 uint32_t reg_src1
= 0;
10957 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10958 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10959 ULONGEST u_regval
= 0;
10961 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10962 /* Handle unconditional insn extension space. */
10964 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10965 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10966 if (arm_insn_r
->cond
)
10968 /* PLD has no affect on architectural state, it just affects
10970 if (5 == ((opcode1
& 0xE0) >> 5))
10973 record_buf
[0] = ARM_PS_REGNUM
;
10974 record_buf
[1] = ARM_LR_REGNUM
;
10975 arm_insn_r
->reg_rec_count
= 2;
10977 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10981 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10982 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10985 /* Undefined instruction on ARM V5; need to handle if later
10986 versions define it. */
10989 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10990 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10991 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10993 /* Handle arithmetic insn extension space. */
10994 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10995 && !INSN_RECORDED(arm_insn_r
))
10997 /* Handle MLA(S) and MUL(S). */
10998 if (0 <= insn_op1
&& 3 >= insn_op1
)
11000 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11001 record_buf
[1] = ARM_PS_REGNUM
;
11002 arm_insn_r
->reg_rec_count
= 2;
11004 else if (4 <= insn_op1
&& 15 >= insn_op1
)
11006 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
11007 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11008 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11009 record_buf
[2] = ARM_PS_REGNUM
;
11010 arm_insn_r
->reg_rec_count
= 3;
11014 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
11015 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
11016 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
11018 /* Handle control insn extension space. */
11020 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
11021 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
11023 if (!bit (arm_insn_r
->arm_insn
,25))
11025 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
11027 if ((0 == insn_op1
) || (2 == insn_op1
))
11030 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11031 arm_insn_r
->reg_rec_count
= 1;
11033 else if (1 == insn_op1
)
11035 /* CSPR is going to be changed. */
11036 record_buf
[0] = ARM_PS_REGNUM
;
11037 arm_insn_r
->reg_rec_count
= 1;
11039 else if (3 == insn_op1
)
11041 /* SPSR is going to be changed. */
11042 /* We need to get SPSR value, which is yet to be done. */
11043 printf_unfiltered (_("Process record does not support "
11044 "instruction 0x%0x at address %s.\n"),
11045 arm_insn_r
->arm_insn
,
11046 paddress (arm_insn_r
->gdbarch
,
11047 arm_insn_r
->this_addr
));
11051 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
11056 record_buf
[0] = ARM_PS_REGNUM
;
11057 arm_insn_r
->reg_rec_count
= 1;
11059 else if (3 == insn_op1
)
11062 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11063 arm_insn_r
->reg_rec_count
= 1;
11066 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
11069 record_buf
[0] = ARM_PS_REGNUM
;
11070 record_buf
[1] = ARM_LR_REGNUM
;
11071 arm_insn_r
->reg_rec_count
= 2;
11073 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
11075 /* QADD, QSUB, QDADD, QDSUB */
11076 record_buf
[0] = ARM_PS_REGNUM
;
11077 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11078 arm_insn_r
->reg_rec_count
= 2;
11080 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
11083 record_buf
[0] = ARM_PS_REGNUM
;
11084 record_buf
[1] = ARM_LR_REGNUM
;
11085 arm_insn_r
->reg_rec_count
= 2;
11087 /* Save SPSR also;how? */
11088 printf_unfiltered (_("Process record does not support "
11089 "instruction 0x%0x at address %s.\n"),
11090 arm_insn_r
->arm_insn
,
11091 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11094 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
11095 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
11096 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
11097 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11100 if (0 == insn_op1
|| 1 == insn_op1
)
11102 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11103 /* We dont do optimization for SMULW<y> where we
11105 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11106 record_buf
[1] = ARM_PS_REGNUM
;
11107 arm_insn_r
->reg_rec_count
= 2;
11109 else if (2 == insn_op1
)
11112 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11113 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11114 arm_insn_r
->reg_rec_count
= 2;
11116 else if (3 == insn_op1
)
11119 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11120 arm_insn_r
->reg_rec_count
= 1;
11126 /* MSR : immediate form. */
11129 /* CSPR is going to be changed. */
11130 record_buf
[0] = ARM_PS_REGNUM
;
11131 arm_insn_r
->reg_rec_count
= 1;
11133 else if (3 == insn_op1
)
11135 /* SPSR is going to be changed. */
11136 /* we need to get SPSR value, which is yet to be done */
11137 printf_unfiltered (_("Process record does not support "
11138 "instruction 0x%0x at address %s.\n"),
11139 arm_insn_r
->arm_insn
,
11140 paddress (arm_insn_r
->gdbarch
,
11141 arm_insn_r
->this_addr
));
11147 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11148 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11149 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11151 /* Handle load/store insn extension space. */
11153 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11154 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11155 && !INSN_RECORDED(arm_insn_r
))
11160 /* These insn, changes register and memory as well. */
11161 /* SWP or SWPB insn. */
11162 /* Get memory address given by Rn. */
11163 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11164 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11165 /* SWP insn ?, swaps word. */
11166 if (8 == arm_insn_r
->opcode
)
11168 record_buf_mem
[0] = 4;
11172 /* SWPB insn, swaps only byte. */
11173 record_buf_mem
[0] = 1;
11175 record_buf_mem
[1] = u_regval
;
11176 arm_insn_r
->mem_rec_count
= 1;
11177 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11178 arm_insn_r
->reg_rec_count
= 1;
11180 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11183 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11186 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11189 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11190 record_buf
[1] = record_buf
[0] + 1;
11191 arm_insn_r
->reg_rec_count
= 2;
11193 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11196 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11199 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11201 /* LDRH, LDRSB, LDRSH. */
11202 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11203 arm_insn_r
->reg_rec_count
= 1;
11208 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11209 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11210 && !INSN_RECORDED(arm_insn_r
))
11213 /* Handle coprocessor insn extension space. */
11216 /* To be done for ARMv5 and later; as of now we return -1. */
11218 printf_unfiltered (_("Process record does not support instruction x%0x "
11219 "at address %s.\n"),arm_insn_r
->arm_insn
,
11220 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11223 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11224 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11229 /* Handling opcode 000 insns. */
11232 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11234 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11235 uint32_t record_buf
[8], record_buf_mem
[8];
11236 ULONGEST u_regval
[2] = {0};
11238 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11239 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11240 uint32_t opcode1
= 0;
11242 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11243 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11244 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11246 /* Data processing insn /multiply insn. */
11247 if (9 == arm_insn_r
->decode
11248 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11249 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11251 /* Handle multiply instructions. */
11252 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11253 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11255 /* Handle MLA and MUL. */
11256 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11257 record_buf
[1] = ARM_PS_REGNUM
;
11258 arm_insn_r
->reg_rec_count
= 2;
11260 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11262 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11263 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11264 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11265 record_buf
[2] = ARM_PS_REGNUM
;
11266 arm_insn_r
->reg_rec_count
= 3;
11269 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11270 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11272 /* Handle misc load insns, as 20th bit (L = 1). */
11273 /* LDR insn has a capability to do branching, if
11274 MOV LR, PC is precceded by LDR insn having Rn as R15
11275 in that case, it emulates branch and link insn, and hence we
11276 need to save CSPR and PC as well. I am not sure this is right
11277 place; as opcode = 010 LDR insn make this happen, if R15 was
11279 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11280 if (15 != reg_dest
)
11282 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11283 arm_insn_r
->reg_rec_count
= 1;
11287 record_buf
[0] = reg_dest
;
11288 record_buf
[1] = ARM_PS_REGNUM
;
11289 arm_insn_r
->reg_rec_count
= 2;
11292 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11293 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11294 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11295 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11297 /* Handle MSR insn. */
11298 if (9 == arm_insn_r
->opcode
)
11300 /* CSPR is going to be changed. */
11301 record_buf
[0] = ARM_PS_REGNUM
;
11302 arm_insn_r
->reg_rec_count
= 1;
11306 /* SPSR is going to be changed. */
11307 /* How to read SPSR value? */
11308 printf_unfiltered (_("Process record does not support instruction "
11309 "0x%0x at address %s.\n"),
11310 arm_insn_r
->arm_insn
,
11311 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11315 else if (9 == arm_insn_r
->decode
11316 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11317 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11319 /* Handling SWP, SWPB. */
11320 /* These insn, changes register and memory as well. */
11321 /* SWP or SWPB insn. */
11323 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11324 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11325 /* SWP insn ?, swaps word. */
11326 if (8 == arm_insn_r
->opcode
)
11328 record_buf_mem
[0] = 4;
11332 /* SWPB insn, swaps only byte. */
11333 record_buf_mem
[0] = 1;
11335 record_buf_mem
[1] = u_regval
[0];
11336 arm_insn_r
->mem_rec_count
= 1;
11337 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11338 arm_insn_r
->reg_rec_count
= 1;
11340 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11341 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11343 /* Handle BLX, branch and link/exchange. */
11344 if (9 == arm_insn_r
->opcode
)
11346 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11347 and R14 stores the return address. */
11348 record_buf
[0] = ARM_PS_REGNUM
;
11349 record_buf
[1] = ARM_LR_REGNUM
;
11350 arm_insn_r
->reg_rec_count
= 2;
11353 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11355 /* Handle enhanced software breakpoint insn, BKPT. */
11356 /* CPSR is changed to be executed in ARM state, disabling normal
11357 interrupts, entering abort mode. */
11358 /* According to high vector configuration PC is set. */
11359 /* user hit breakpoint and type reverse, in
11360 that case, we need to go back with previous CPSR and
11361 Program Counter. */
11362 record_buf
[0] = ARM_PS_REGNUM
;
11363 record_buf
[1] = ARM_LR_REGNUM
;
11364 arm_insn_r
->reg_rec_count
= 2;
11366 /* Save SPSR also; how? */
11367 printf_unfiltered (_("Process record does not support instruction "
11368 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11369 paddress (arm_insn_r
->gdbarch
,
11370 arm_insn_r
->this_addr
));
11373 else if (11 == arm_insn_r
->decode
11374 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11376 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11378 /* Handle str(x) insn */
11379 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11382 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11383 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11385 /* Handle BX, branch and link/exchange. */
11386 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11387 record_buf
[0] = ARM_PS_REGNUM
;
11388 arm_insn_r
->reg_rec_count
= 1;
11390 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11391 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11392 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11394 /* Count leading zeros: CLZ. */
11395 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11396 arm_insn_r
->reg_rec_count
= 1;
11398 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11399 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11400 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11401 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11404 /* Handle MRS insn. */
11405 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11406 arm_insn_r
->reg_rec_count
= 1;
11408 else if (arm_insn_r
->opcode
<= 15)
11410 /* Normal data processing insns. */
11411 /* Out of 11 shifter operands mode, all the insn modifies destination
11412 register, which is specified by 13-16 decode. */
11413 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11414 record_buf
[1] = ARM_PS_REGNUM
;
11415 arm_insn_r
->reg_rec_count
= 2;
11422 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11423 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11427 /* Handling opcode 001 insns. */
11430 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11432 uint32_t record_buf
[8], record_buf_mem
[8];
11434 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11435 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11437 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11438 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11439 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11442 /* Handle MSR insn. */
11443 if (9 == arm_insn_r
->opcode
)
11445 /* CSPR is going to be changed. */
11446 record_buf
[0] = ARM_PS_REGNUM
;
11447 arm_insn_r
->reg_rec_count
= 1;
11451 /* SPSR is going to be changed. */
11454 else if (arm_insn_r
->opcode
<= 15)
11456 /* Normal data processing insns. */
11457 /* Out of 11 shifter operands mode, all the insn modifies destination
11458 register, which is specified by 13-16 decode. */
11459 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11460 record_buf
[1] = ARM_PS_REGNUM
;
11461 arm_insn_r
->reg_rec_count
= 2;
11468 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11469 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11473 /* Handle ARM mode instructions with opcode 010. */
11476 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11478 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11480 uint32_t reg_base
, reg_dest
;
11481 uint32_t offset_12
, tgt_mem_addr
;
11482 uint32_t record_buf
[8], record_buf_mem
[8];
11483 unsigned char wback
;
11486 /* Calculate wback. */
11487 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
11488 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
11490 arm_insn_r
->reg_rec_count
= 0;
11491 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11493 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11495 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11498 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11499 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
11501 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11502 preceeds a LDR instruction having R15 as reg_base, it
11503 emulates a branch and link instruction, and hence we need to save
11504 CPSR and PC as well. */
11505 if (ARM_PC_REGNUM
== reg_dest
)
11506 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11508 /* If wback is true, also save the base register, which is going to be
11511 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11515 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11517 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11518 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11520 /* Handle bit U. */
11521 if (bit (arm_insn_r
->arm_insn
, 23))
11523 /* U == 1: Add the offset. */
11524 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
11528 /* U == 0: subtract the offset. */
11529 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
11532 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11534 if (bit (arm_insn_r
->arm_insn
, 22))
11536 /* STRB and STRBT: 1 byte. */
11537 record_buf_mem
[0] = 1;
11541 /* STR and STRT: 4 bytes. */
11542 record_buf_mem
[0] = 4;
11545 /* Handle bit P. */
11546 if (bit (arm_insn_r
->arm_insn
, 24))
11547 record_buf_mem
[1] = tgt_mem_addr
;
11549 record_buf_mem
[1] = (uint32_t) u_regval
;
11551 arm_insn_r
->mem_rec_count
= 1;
11553 /* If wback is true, also save the base register, which is going to be
11556 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11559 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11560 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11564 /* Handling opcode 011 insns. */
11567 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11569 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11571 uint32_t shift_imm
= 0;
11572 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11573 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11574 uint32_t record_buf
[8], record_buf_mem
[8];
11577 ULONGEST u_regval
[2];
11579 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11580 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11582 /* Handle enhanced store insns and LDRD DSP insn,
11583 order begins according to addressing modes for store insns
11587 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11589 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11590 /* LDR insn has a capability to do branching, if
11591 MOV LR, PC is precedded by LDR insn having Rn as R15
11592 in that case, it emulates branch and link insn, and hence we
11593 need to save CSPR and PC as well. */
11594 if (15 != reg_dest
)
11596 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11597 arm_insn_r
->reg_rec_count
= 1;
11601 record_buf
[0] = reg_dest
;
11602 record_buf
[1] = ARM_PS_REGNUM
;
11603 arm_insn_r
->reg_rec_count
= 2;
11608 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11610 /* Store insn, register offset and register pre-indexed,
11611 register post-indexed. */
11613 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11615 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11616 regcache_raw_read_unsigned (reg_cache
, reg_src1
11618 regcache_raw_read_unsigned (reg_cache
, reg_src2
11620 if (15 == reg_src2
)
11622 /* If R15 was used as Rn, hence current PC+8. */
11623 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11624 u_regval
[0] = u_regval
[0] + 8;
11626 /* Calculate target store address, Rn +/- Rm, register offset. */
11628 if (bit (arm_insn_r
->arm_insn
, 23))
11630 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11634 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11637 switch (arm_insn_r
->opcode
)
11651 record_buf_mem
[0] = 4;
11666 record_buf_mem
[0] = 1;
11670 gdb_assert_not_reached ("no decoding pattern found");
11673 record_buf_mem
[1] = tgt_mem_addr
;
11674 arm_insn_r
->mem_rec_count
= 1;
11676 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11677 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11678 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11679 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11680 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11681 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11684 /* Rn is going to be changed in pre-indexed mode and
11685 post-indexed mode as well. */
11686 record_buf
[0] = reg_src2
;
11687 arm_insn_r
->reg_rec_count
= 1;
11692 /* Store insn, scaled register offset; scaled pre-indexed. */
11693 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11695 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11697 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11698 /* Get shift_imm. */
11699 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11700 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11701 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11702 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11703 /* Offset_12 used as shift. */
11707 /* Offset_12 used as index. */
11708 offset_12
= u_regval
[0] << shift_imm
;
11712 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11718 if (bit (u_regval
[0], 31))
11720 offset_12
= 0xFFFFFFFF;
11729 /* This is arithmetic shift. */
11730 offset_12
= s_word
>> shift_imm
;
11737 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11739 /* Get C flag value and shift it by 31. */
11740 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11741 | (u_regval
[0]) >> 1);
11745 offset_12
= (u_regval
[0] >> shift_imm
) \
11747 (sizeof(uint32_t) - shift_imm
));
11752 gdb_assert_not_reached ("no decoding pattern found");
11756 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11758 if (bit (arm_insn_r
->arm_insn
, 23))
11760 tgt_mem_addr
= u_regval
[1] + offset_12
;
11764 tgt_mem_addr
= u_regval
[1] - offset_12
;
11767 switch (arm_insn_r
->opcode
)
11781 record_buf_mem
[0] = 4;
11796 record_buf_mem
[0] = 1;
11800 gdb_assert_not_reached ("no decoding pattern found");
11803 record_buf_mem
[1] = tgt_mem_addr
;
11804 arm_insn_r
->mem_rec_count
= 1;
11806 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11807 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11808 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11809 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11810 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11811 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11814 /* Rn is going to be changed in register scaled pre-indexed
11815 mode,and scaled post indexed mode. */
11816 record_buf
[0] = reg_src2
;
11817 arm_insn_r
->reg_rec_count
= 1;
11822 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11823 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11827 /* Handle ARM mode instructions with opcode 100. */
11830 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11832 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11833 uint32_t register_count
= 0, register_bits
;
11834 uint32_t reg_base
, addr_mode
;
11835 uint32_t record_buf
[24], record_buf_mem
[48];
11839 /* Fetch the list of registers. */
11840 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11841 arm_insn_r
->reg_rec_count
= 0;
11843 /* Fetch the base register that contains the address we are loading data
11845 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11847 /* Calculate wback. */
11848 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11850 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11852 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11854 /* Find out which registers are going to be loaded from memory. */
11855 while (register_bits
)
11857 if (register_bits
& 0x00000001)
11858 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11859 register_bits
= register_bits
>> 1;
11864 /* If wback is true, also save the base register, which is going to be
11867 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11869 /* Save the CPSR register. */
11870 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11874 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11876 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11878 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11880 /* Find out how many registers are going to be stored to memory. */
11881 while (register_bits
)
11883 if (register_bits
& 0x00000001)
11885 register_bits
= register_bits
>> 1;
11890 /* STMDA (STMED): Decrement after. */
11892 record_buf_mem
[1] = (uint32_t) u_regval
11893 - register_count
* INT_REGISTER_SIZE
+ 4;
11895 /* STM (STMIA, STMEA): Increment after. */
11897 record_buf_mem
[1] = (uint32_t) u_regval
;
11899 /* STMDB (STMFD): Decrement before. */
11901 record_buf_mem
[1] = (uint32_t) u_regval
11902 - register_count
* INT_REGISTER_SIZE
;
11904 /* STMIB (STMFA): Increment before. */
11906 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11909 gdb_assert_not_reached ("no decoding pattern found");
11913 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11914 arm_insn_r
->mem_rec_count
= 1;
11916 /* If wback is true, also save the base register, which is going to be
11919 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11922 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11923 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11927 /* Handling opcode 101 insns. */
11930 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11932 uint32_t record_buf
[8];
11934 /* Handle B, BL, BLX(1) insns. */
11935 /* B simply branches so we do nothing here. */
11936 /* Note: BLX(1) doesnt fall here but instead it falls into
11937 extension space. */
11938 if (bit (arm_insn_r
->arm_insn
, 24))
11940 record_buf
[0] = ARM_LR_REGNUM
;
11941 arm_insn_r
->reg_rec_count
= 1;
11944 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11949 /* Handling opcode 110 insns. */
11952 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11954 printf_unfiltered (_("Process record does not support instruction "
11955 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11956 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11961 /* Record handler for vector data transfer instructions. */
11964 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11966 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11967 uint32_t record_buf
[4];
11969 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11970 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11971 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11972 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11973 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11974 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11976 /* Handle VMOV instruction. */
11977 if (bit_l
&& bit_c
)
11979 record_buf
[0] = reg_t
;
11980 arm_insn_r
->reg_rec_count
= 1;
11982 else if (bit_l
&& !bit_c
)
11984 /* Handle VMOV instruction. */
11985 if (bits_a
== 0x00)
11987 if (bit (arm_insn_r
->arm_insn
, 20))
11988 record_buf
[0] = reg_t
;
11990 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
11993 arm_insn_r
->reg_rec_count
= 1;
11995 /* Handle VMRS instruction. */
11996 else if (bits_a
== 0x07)
11999 reg_t
= ARM_PS_REGNUM
;
12001 record_buf
[0] = reg_t
;
12002 arm_insn_r
->reg_rec_count
= 1;
12005 else if (!bit_l
&& !bit_c
)
12007 /* Handle VMOV instruction. */
12008 if (bits_a
== 0x00)
12010 if (bit (arm_insn_r
->arm_insn
, 20))
12011 record_buf
[0] = reg_t
;
12013 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12016 arm_insn_r
->reg_rec_count
= 1;
12018 /* Handle VMSR instruction. */
12019 else if (bits_a
== 0x07)
12021 record_buf
[0] = ARM_FPSCR_REGNUM
;
12022 arm_insn_r
->reg_rec_count
= 1;
12025 else if (!bit_l
&& bit_c
)
12027 /* Handle VMOV instruction. */
12028 if (!(bits_a
& 0x04))
12030 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
12032 arm_insn_r
->reg_rec_count
= 1;
12034 /* Handle VDUP instruction. */
12037 if (bit (arm_insn_r
->arm_insn
, 21))
12039 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12040 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12041 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
12042 arm_insn_r
->reg_rec_count
= 2;
12046 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12047 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12048 arm_insn_r
->reg_rec_count
= 1;
12053 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12057 /* Record handler for extension register load/store instructions. */
12060 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
12062 uint32_t opcode
, single_reg
;
12063 uint8_t op_vldm_vstm
;
12064 uint32_t record_buf
[8], record_buf_mem
[128];
12065 ULONGEST u_regval
= 0;
12067 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12068 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
12070 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
12071 single_reg
= bit (arm_insn_r
->arm_insn
, 8);
12072 op_vldm_vstm
= opcode
& 0x1b;
12074 /* Handle VMOV instructions. */
12075 if ((opcode
& 0x1e) == 0x04)
12077 if (bit (arm_insn_r
->arm_insn
, 4))
12079 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12080 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12081 arm_insn_r
->reg_rec_count
= 2;
12085 uint8_t reg_m
= (bits (arm_insn_r
->arm_insn
, 0, 3) << 1)
12086 | bit (arm_insn_r
->arm_insn
, 5);
12090 record_buf
[0] = num_regs
+ reg_m
;
12091 record_buf
[1] = num_regs
+ reg_m
+ 1;
12092 arm_insn_r
->reg_rec_count
= 2;
12096 record_buf
[0] = reg_m
+ ARM_D0_REGNUM
;
12097 arm_insn_r
->reg_rec_count
= 1;
12101 /* Handle VSTM and VPUSH instructions. */
12102 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
12103 || op_vldm_vstm
== 0x12)
12105 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12106 uint32_t memory_index
= 0;
12108 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12109 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12110 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12111 imm_off32
= imm_off8
<< 24;
12112 memory_count
= imm_off8
;
12114 if (bit (arm_insn_r
->arm_insn
, 23))
12115 start_address
= u_regval
;
12117 start_address
= u_regval
- imm_off32
;
12119 if (bit (arm_insn_r
->arm_insn
, 21))
12121 record_buf
[0] = reg_rn
;
12122 arm_insn_r
->reg_rec_count
= 1;
12125 while (memory_count
> 0)
12129 record_buf_mem
[memory_index
] = start_address
;
12130 record_buf_mem
[memory_index
+ 1] = 4;
12131 start_address
= start_address
+ 4;
12132 memory_index
= memory_index
+ 2;
12136 record_buf_mem
[memory_index
] = start_address
;
12137 record_buf_mem
[memory_index
+ 1] = 4;
12138 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12139 record_buf_mem
[memory_index
+ 3] = 4;
12140 start_address
= start_address
+ 8;
12141 memory_index
= memory_index
+ 4;
12145 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
12147 /* Handle VLDM instructions. */
12148 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
12149 || op_vldm_vstm
== 0x13)
12151 uint32_t reg_count
, reg_vd
;
12152 uint32_t reg_index
= 0;
12154 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12155 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
12158 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12160 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12162 if (bit (arm_insn_r
->arm_insn
, 21))
12163 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
12165 while (reg_count
> 0)
12168 record_buf
[reg_index
++] = num_regs
+ reg_vd
+ reg_count
- 1;
12170 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
12174 arm_insn_r
->reg_rec_count
= reg_index
;
12176 /* VSTR Vector store register. */
12177 else if ((opcode
& 0x13) == 0x10)
12179 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12180 uint32_t memory_index
= 0;
12182 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12183 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12184 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12185 imm_off32
= imm_off8
<< 24;
12186 memory_count
= imm_off8
;
12188 if (bit (arm_insn_r
->arm_insn
, 23))
12189 start_address
= u_regval
+ imm_off32
;
12191 start_address
= u_regval
- imm_off32
;
12195 record_buf_mem
[memory_index
] = start_address
;
12196 record_buf_mem
[memory_index
+ 1] = 4;
12197 arm_insn_r
->mem_rec_count
= 1;
12201 record_buf_mem
[memory_index
] = start_address
;
12202 record_buf_mem
[memory_index
+ 1] = 4;
12203 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12204 record_buf_mem
[memory_index
+ 3] = 4;
12205 arm_insn_r
->mem_rec_count
= 2;
12208 /* VLDR Vector load register. */
12209 else if ((opcode
& 0x13) == 0x11)
12211 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12215 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12216 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
12220 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12221 record_buf
[0] = num_regs
+ reg_vd
;
12223 arm_insn_r
->reg_rec_count
= 1;
12226 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12227 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12231 /* Record handler for arm/thumb mode VFP data processing instructions. */
12234 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
12236 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
12237 uint32_t record_buf
[4];
12238 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
12239 enum insn_types curr_insn_type
= INSN_INV
;
12241 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12242 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
12243 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
12244 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
12245 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
12246 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12247 opc1
= opc1
& 0x04;
12249 /* Handle VMLA, VMLS. */
12252 if (bit (arm_insn_r
->arm_insn
, 10))
12254 if (bit (arm_insn_r
->arm_insn
, 6))
12255 curr_insn_type
= INSN_T0
;
12257 curr_insn_type
= INSN_T1
;
12262 curr_insn_type
= INSN_T1
;
12264 curr_insn_type
= INSN_T2
;
12267 /* Handle VNMLA, VNMLS, VNMUL. */
12268 else if (opc1
== 0x01)
12271 curr_insn_type
= INSN_T1
;
12273 curr_insn_type
= INSN_T2
;
12276 else if (opc1
== 0x02 && !(opc3
& 0x01))
12278 if (bit (arm_insn_r
->arm_insn
, 10))
12280 if (bit (arm_insn_r
->arm_insn
, 6))
12281 curr_insn_type
= INSN_T0
;
12283 curr_insn_type
= INSN_T1
;
12288 curr_insn_type
= INSN_T1
;
12290 curr_insn_type
= INSN_T2
;
12293 /* Handle VADD, VSUB. */
12294 else if (opc1
== 0x03)
12296 if (!bit (arm_insn_r
->arm_insn
, 9))
12298 if (bit (arm_insn_r
->arm_insn
, 6))
12299 curr_insn_type
= INSN_T0
;
12301 curr_insn_type
= INSN_T1
;
12306 curr_insn_type
= INSN_T1
;
12308 curr_insn_type
= INSN_T2
;
12312 else if (opc1
== 0x0b)
12315 curr_insn_type
= INSN_T1
;
12317 curr_insn_type
= INSN_T2
;
12319 /* Handle all other vfp data processing instructions. */
12320 else if (opc1
== 0x0b)
12323 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
12325 if (bit (arm_insn_r
->arm_insn
, 4))
12327 if (bit (arm_insn_r
->arm_insn
, 6))
12328 curr_insn_type
= INSN_T0
;
12330 curr_insn_type
= INSN_T1
;
12335 curr_insn_type
= INSN_T1
;
12337 curr_insn_type
= INSN_T2
;
12340 /* Handle VNEG and VABS. */
12341 else if ((opc2
== 0x01 && opc3
== 0x01)
12342 || (opc2
== 0x00 && opc3
== 0x03))
12344 if (!bit (arm_insn_r
->arm_insn
, 11))
12346 if (bit (arm_insn_r
->arm_insn
, 6))
12347 curr_insn_type
= INSN_T0
;
12349 curr_insn_type
= INSN_T1
;
12354 curr_insn_type
= INSN_T1
;
12356 curr_insn_type
= INSN_T2
;
12359 /* Handle VSQRT. */
12360 else if (opc2
== 0x01 && opc3
== 0x03)
12363 curr_insn_type
= INSN_T1
;
12365 curr_insn_type
= INSN_T2
;
12368 else if (opc2
== 0x07 && opc3
== 0x03)
12371 curr_insn_type
= INSN_T1
;
12373 curr_insn_type
= INSN_T2
;
12375 else if (opc3
& 0x01)
12378 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
12380 if (!bit (arm_insn_r
->arm_insn
, 18))
12381 curr_insn_type
= INSN_T2
;
12385 curr_insn_type
= INSN_T1
;
12387 curr_insn_type
= INSN_T2
;
12391 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
12394 curr_insn_type
= INSN_T1
;
12396 curr_insn_type
= INSN_T2
;
12398 /* Handle VCVTB, VCVTT. */
12399 else if ((opc2
& 0x0e) == 0x02)
12400 curr_insn_type
= INSN_T2
;
12401 /* Handle VCMP, VCMPE. */
12402 else if ((opc2
& 0x0e) == 0x04)
12403 curr_insn_type
= INSN_T3
;
12407 switch (curr_insn_type
)
12410 reg_vd
= reg_vd
| (bit_d
<< 4);
12411 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12412 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
12413 arm_insn_r
->reg_rec_count
= 2;
12417 reg_vd
= reg_vd
| (bit_d
<< 4);
12418 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12419 arm_insn_r
->reg_rec_count
= 1;
12423 reg_vd
= (reg_vd
<< 1) | bit_d
;
12424 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12425 arm_insn_r
->reg_rec_count
= 1;
12429 record_buf
[0] = ARM_FPSCR_REGNUM
;
12430 arm_insn_r
->reg_rec_count
= 1;
12434 gdb_assert_not_reached ("no decoding pattern found");
12438 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12442 /* Handling opcode 110 insns. */
12445 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
12447 uint32_t op
, op1
, op1_sbit
, op1_ebit
, coproc
;
12449 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12450 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12451 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12453 if ((coproc
& 0x0e) == 0x0a)
12455 /* Handle extension register ld/st instructions. */
12457 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12459 /* 64-bit transfers between arm core and extension registers. */
12460 if ((op1
& 0x3e) == 0x04)
12461 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12465 /* Handle coprocessor ld/st instructions. */
12470 return arm_record_unsupported_insn (arm_insn_r
);
12473 return arm_record_unsupported_insn (arm_insn_r
);
12476 /* Move to coprocessor from two arm core registers. */
12478 return arm_record_unsupported_insn (arm_insn_r
);
12480 /* Move to two arm core registers from coprocessor. */
12485 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12486 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12487 arm_insn_r
->reg_rec_count
= 2;
12489 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
12493 return arm_record_unsupported_insn (arm_insn_r
);
12496 /* Handling opcode 111 insns. */
12499 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
12501 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
12502 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
12503 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12504 ULONGEST u_regval
= 0;
12506 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
12507 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12508 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
12509 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12510 op
= bit (arm_insn_r
->arm_insn
, 4);
12512 /* Handle arm SWI/SVC system call instructions. */
12515 if (tdep
->arm_syscall_record
!= NULL
)
12517 ULONGEST svc_operand
, svc_number
;
12519 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
12521 if (svc_operand
) /* OABI. */
12522 svc_number
= svc_operand
- 0x900000;
12524 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
12526 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
12530 printf_unfiltered (_("no syscall record support\n"));
12535 if ((coproc
& 0x0e) == 0x0a)
12537 /* VFP data-processing instructions. */
12538 if (!op1_sbit
&& !op
)
12539 return arm_record_vfp_data_proc_insn (arm_insn_r
);
12541 /* Advanced SIMD, VFP instructions. */
12542 if (!op1_sbit
&& op
)
12543 return arm_record_vdata_transfer_insn (arm_insn_r
);
12547 /* Coprocessor data operations. */
12548 if (!op1_sbit
&& !op
)
12549 return arm_record_unsupported_insn (arm_insn_r
);
12551 /* Move to Coprocessor from ARM core register. */
12552 if (!op1_sbit
&& !op1_ebit
&& op
)
12553 return arm_record_unsupported_insn (arm_insn_r
);
12555 /* Move to arm core register from coprocessor. */
12556 if (!op1_sbit
&& op1_ebit
&& op
)
12558 uint32_t record_buf
[1];
12560 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12561 if (record_buf
[0] == 15)
12562 record_buf
[0] = ARM_PS_REGNUM
;
12564 arm_insn_r
->reg_rec_count
= 1;
12565 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
12571 return arm_record_unsupported_insn (arm_insn_r
);
12574 /* Handling opcode 000 insns. */
12577 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
12579 uint32_t record_buf
[8];
12580 uint32_t reg_src1
= 0;
12582 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12584 record_buf
[0] = ARM_PS_REGNUM
;
12585 record_buf
[1] = reg_src1
;
12586 thumb_insn_r
->reg_rec_count
= 2;
12588 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12594 /* Handling opcode 001 insns. */
12597 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
12599 uint32_t record_buf
[8];
12600 uint32_t reg_src1
= 0;
12602 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12604 record_buf
[0] = ARM_PS_REGNUM
;
12605 record_buf
[1] = reg_src1
;
12606 thumb_insn_r
->reg_rec_count
= 2;
12608 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12613 /* Handling opcode 010 insns. */
12616 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12618 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12619 uint32_t record_buf
[8], record_buf_mem
[8];
12621 uint32_t reg_src1
= 0, reg_src2
= 0;
12622 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12624 ULONGEST u_regval
[2] = {0};
12626 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12628 if (bit (thumb_insn_r
->arm_insn
, 12))
12630 /* Handle load/store register offset. */
12631 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
12632 if (opcode2
>= 12 && opcode2
<= 15)
12634 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12635 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12636 record_buf
[0] = reg_src1
;
12637 thumb_insn_r
->reg_rec_count
= 1;
12639 else if (opcode2
>= 8 && opcode2
<= 10)
12641 /* STR(2), STRB(2), STRH(2) . */
12642 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12643 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12644 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12645 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12647 record_buf_mem
[0] = 4; /* STR (2). */
12648 else if (10 == opcode2
)
12649 record_buf_mem
[0] = 1; /* STRB (2). */
12650 else if (9 == opcode2
)
12651 record_buf_mem
[0] = 2; /* STRH (2). */
12652 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12653 thumb_insn_r
->mem_rec_count
= 1;
12656 else if (bit (thumb_insn_r
->arm_insn
, 11))
12658 /* Handle load from literal pool. */
12660 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12661 record_buf
[0] = reg_src1
;
12662 thumb_insn_r
->reg_rec_count
= 1;
12666 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12667 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12668 if ((3 == opcode2
) && (!opcode3
))
12670 /* Branch with exchange. */
12671 record_buf
[0] = ARM_PS_REGNUM
;
12672 thumb_insn_r
->reg_rec_count
= 1;
12676 /* Format 8; special data processing insns. */
12677 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12678 record_buf
[0] = ARM_PS_REGNUM
;
12679 record_buf
[1] = reg_src1
;
12680 thumb_insn_r
->reg_rec_count
= 2;
12685 /* Format 5; data processing insns. */
12686 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12687 if (bit (thumb_insn_r
->arm_insn
, 7))
12689 reg_src1
= reg_src1
+ 8;
12691 record_buf
[0] = ARM_PS_REGNUM
;
12692 record_buf
[1] = reg_src1
;
12693 thumb_insn_r
->reg_rec_count
= 2;
12696 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12697 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12703 /* Handling opcode 001 insns. */
12706 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12708 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12709 uint32_t record_buf
[8], record_buf_mem
[8];
12711 uint32_t reg_src1
= 0;
12712 uint32_t opcode
= 0, immed_5
= 0;
12714 ULONGEST u_regval
= 0;
12716 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12721 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12722 record_buf
[0] = reg_src1
;
12723 thumb_insn_r
->reg_rec_count
= 1;
12728 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12729 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12730 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12731 record_buf_mem
[0] = 4;
12732 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12733 thumb_insn_r
->mem_rec_count
= 1;
12736 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12737 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12743 /* Handling opcode 100 insns. */
12746 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12748 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12749 uint32_t record_buf
[8], record_buf_mem
[8];
12751 uint32_t reg_src1
= 0;
12752 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12754 ULONGEST u_regval
= 0;
12756 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12761 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12762 record_buf
[0] = reg_src1
;
12763 thumb_insn_r
->reg_rec_count
= 1;
12765 else if (1 == opcode
)
12768 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12769 record_buf
[0] = reg_src1
;
12770 thumb_insn_r
->reg_rec_count
= 1;
12772 else if (2 == opcode
)
12775 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12776 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12777 record_buf_mem
[0] = 4;
12778 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12779 thumb_insn_r
->mem_rec_count
= 1;
12781 else if (0 == opcode
)
12784 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12785 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12786 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12787 record_buf_mem
[0] = 2;
12788 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12789 thumb_insn_r
->mem_rec_count
= 1;
12792 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12793 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12799 /* Handling opcode 101 insns. */
12802 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12804 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12806 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12807 uint32_t register_bits
= 0, register_count
= 0;
12808 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12809 uint32_t record_buf
[24], record_buf_mem
[48];
12812 ULONGEST u_regval
= 0;
12814 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12815 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12816 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12821 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12822 while (register_bits
)
12824 if (register_bits
& 0x00000001)
12825 record_buf
[index
++] = register_count
;
12826 register_bits
= register_bits
>> 1;
12829 record_buf
[index
++] = ARM_PS_REGNUM
;
12830 record_buf
[index
++] = ARM_SP_REGNUM
;
12831 thumb_insn_r
->reg_rec_count
= index
;
12833 else if (10 == opcode2
)
12836 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12837 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12838 while (register_bits
)
12840 if (register_bits
& 0x00000001)
12842 register_bits
= register_bits
>> 1;
12844 start_address
= u_regval
- \
12845 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12846 thumb_insn_r
->mem_rec_count
= register_count
;
12847 while (register_count
)
12849 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12850 record_buf_mem
[(register_count
* 2) - 2] = 4;
12851 start_address
= start_address
+ 4;
12854 record_buf
[0] = ARM_SP_REGNUM
;
12855 thumb_insn_r
->reg_rec_count
= 1;
12857 else if (0x1E == opcode1
)
12860 /* Handle enhanced software breakpoint insn, BKPT. */
12861 /* CPSR is changed to be executed in ARM state, disabling normal
12862 interrupts, entering abort mode. */
12863 /* According to high vector configuration PC is set. */
12864 /* User hits breakpoint and type reverse, in that case, we need to go back with
12865 previous CPSR and Program Counter. */
12866 record_buf
[0] = ARM_PS_REGNUM
;
12867 record_buf
[1] = ARM_LR_REGNUM
;
12868 thumb_insn_r
->reg_rec_count
= 2;
12869 /* We need to save SPSR value, which is not yet done. */
12870 printf_unfiltered (_("Process record does not support instruction "
12871 "0x%0x at address %s.\n"),
12872 thumb_insn_r
->arm_insn
,
12873 paddress (thumb_insn_r
->gdbarch
,
12874 thumb_insn_r
->this_addr
));
12877 else if ((0 == opcode
) || (1 == opcode
))
12879 /* ADD(5), ADD(6). */
12880 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12881 record_buf
[0] = reg_src1
;
12882 thumb_insn_r
->reg_rec_count
= 1;
12884 else if (2 == opcode
)
12886 /* ADD(7), SUB(4). */
12887 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12888 record_buf
[0] = ARM_SP_REGNUM
;
12889 thumb_insn_r
->reg_rec_count
= 1;
12892 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12893 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12899 /* Handling opcode 110 insns. */
12902 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12904 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12905 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12907 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12908 uint32_t reg_src1
= 0;
12909 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12910 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12911 uint32_t record_buf
[24], record_buf_mem
[48];
12913 ULONGEST u_regval
= 0;
12915 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12916 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12922 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12924 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12925 while (register_bits
)
12927 if (register_bits
& 0x00000001)
12928 record_buf
[index
++] = register_count
;
12929 register_bits
= register_bits
>> 1;
12932 record_buf
[index
++] = reg_src1
;
12933 thumb_insn_r
->reg_rec_count
= index
;
12935 else if (0 == opcode2
)
12937 /* It handles both STMIA. */
12938 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12940 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12941 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12942 while (register_bits
)
12944 if (register_bits
& 0x00000001)
12946 register_bits
= register_bits
>> 1;
12948 start_address
= u_regval
;
12949 thumb_insn_r
->mem_rec_count
= register_count
;
12950 while (register_count
)
12952 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12953 record_buf_mem
[(register_count
* 2) - 2] = 4;
12954 start_address
= start_address
+ 4;
12958 else if (0x1F == opcode1
)
12960 /* Handle arm syscall insn. */
12961 if (tdep
->arm_syscall_record
!= NULL
)
12963 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12964 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12968 printf_unfiltered (_("no syscall record support\n"));
12973 /* B (1), conditional branch is automatically taken care in process_record,
12974 as PC is saved there. */
12976 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12977 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12983 /* Handling opcode 111 insns. */
12986 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12988 uint32_t record_buf
[8];
12989 uint32_t bits_h
= 0;
12991 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12993 if (2 == bits_h
|| 3 == bits_h
)
12996 record_buf
[0] = ARM_LR_REGNUM
;
12997 thumb_insn_r
->reg_rec_count
= 1;
12999 else if (1 == bits_h
)
13002 record_buf
[0] = ARM_PS_REGNUM
;
13003 record_buf
[1] = ARM_LR_REGNUM
;
13004 thumb_insn_r
->reg_rec_count
= 2;
13007 /* B(2) is automatically taken care in process_record, as PC is
13010 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13015 /* Handler for thumb2 load/store multiple instructions. */
13018 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
13020 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13022 uint32_t reg_rn
, op
;
13023 uint32_t register_bits
= 0, register_count
= 0;
13024 uint32_t index
= 0, start_address
= 0;
13025 uint32_t record_buf
[24], record_buf_mem
[48];
13027 ULONGEST u_regval
= 0;
13029 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13030 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13032 if (0 == op
|| 3 == op
)
13034 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13036 /* Handle RFE instruction. */
13037 record_buf
[0] = ARM_PS_REGNUM
;
13038 thumb2_insn_r
->reg_rec_count
= 1;
13042 /* Handle SRS instruction after reading banked SP. */
13043 return arm_record_unsupported_insn (thumb2_insn_r
);
13046 else if (1 == op
|| 2 == op
)
13048 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13050 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13051 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13052 while (register_bits
)
13054 if (register_bits
& 0x00000001)
13055 record_buf
[index
++] = register_count
;
13058 register_bits
= register_bits
>> 1;
13060 record_buf
[index
++] = reg_rn
;
13061 record_buf
[index
++] = ARM_PS_REGNUM
;
13062 thumb2_insn_r
->reg_rec_count
= index
;
13066 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13067 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13068 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13069 while (register_bits
)
13071 if (register_bits
& 0x00000001)
13074 register_bits
= register_bits
>> 1;
13079 /* Start address calculation for LDMDB/LDMEA. */
13080 start_address
= u_regval
;
13084 /* Start address calculation for LDMDB/LDMEA. */
13085 start_address
= u_regval
- register_count
* 4;
13088 thumb2_insn_r
->mem_rec_count
= register_count
;
13089 while (register_count
)
13091 record_buf_mem
[register_count
* 2 - 1] = start_address
;
13092 record_buf_mem
[register_count
* 2 - 2] = 4;
13093 start_address
= start_address
+ 4;
13096 record_buf
[0] = reg_rn
;
13097 record_buf
[1] = ARM_PS_REGNUM
;
13098 thumb2_insn_r
->reg_rec_count
= 2;
13102 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13104 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13106 return ARM_RECORD_SUCCESS
;
13109 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13113 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
13115 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13117 uint32_t reg_rd
, reg_rn
, offset_imm
;
13118 uint32_t reg_dest1
, reg_dest2
;
13119 uint32_t address
, offset_addr
;
13120 uint32_t record_buf
[8], record_buf_mem
[8];
13121 uint32_t op1
, op2
, op3
;
13124 ULONGEST u_regval
[2];
13126 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13127 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
13128 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13130 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13132 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
13134 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13135 record_buf
[0] = reg_dest1
;
13136 record_buf
[1] = ARM_PS_REGNUM
;
13137 thumb2_insn_r
->reg_rec_count
= 2;
13140 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
13142 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13143 record_buf
[2] = reg_dest2
;
13144 thumb2_insn_r
->reg_rec_count
= 3;
13149 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13150 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13152 if (0 == op1
&& 0 == op2
)
13154 /* Handle STREX. */
13155 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13156 address
= u_regval
[0] + (offset_imm
* 4);
13157 record_buf_mem
[0] = 4;
13158 record_buf_mem
[1] = address
;
13159 thumb2_insn_r
->mem_rec_count
= 1;
13160 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13161 record_buf
[0] = reg_rd
;
13162 thumb2_insn_r
->reg_rec_count
= 1;
13164 else if (1 == op1
&& 0 == op2
)
13166 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13167 record_buf
[0] = reg_rd
;
13168 thumb2_insn_r
->reg_rec_count
= 1;
13169 address
= u_regval
[0];
13170 record_buf_mem
[1] = address
;
13174 /* Handle STREXB. */
13175 record_buf_mem
[0] = 1;
13176 thumb2_insn_r
->mem_rec_count
= 1;
13180 /* Handle STREXH. */
13181 record_buf_mem
[0] = 2 ;
13182 thumb2_insn_r
->mem_rec_count
= 1;
13186 /* Handle STREXD. */
13187 address
= u_regval
[0];
13188 record_buf_mem
[0] = 4;
13189 record_buf_mem
[2] = 4;
13190 record_buf_mem
[3] = address
+ 4;
13191 thumb2_insn_r
->mem_rec_count
= 2;
13196 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13198 if (bit (thumb2_insn_r
->arm_insn
, 24))
13200 if (bit (thumb2_insn_r
->arm_insn
, 23))
13201 offset_addr
= u_regval
[0] + (offset_imm
* 4);
13203 offset_addr
= u_regval
[0] - (offset_imm
* 4);
13205 address
= offset_addr
;
13208 address
= u_regval
[0];
13210 record_buf_mem
[0] = 4;
13211 record_buf_mem
[1] = address
;
13212 record_buf_mem
[2] = 4;
13213 record_buf_mem
[3] = address
+ 4;
13214 thumb2_insn_r
->mem_rec_count
= 2;
13215 record_buf
[0] = reg_rn
;
13216 thumb2_insn_r
->reg_rec_count
= 1;
13220 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13222 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13224 return ARM_RECORD_SUCCESS
;
13227 /* Handler for thumb2 data processing (shift register and modified immediate)
13231 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
13233 uint32_t reg_rd
, op
;
13234 uint32_t record_buf
[8];
13236 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
13237 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13239 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
13241 record_buf
[0] = ARM_PS_REGNUM
;
13242 thumb2_insn_r
->reg_rec_count
= 1;
13246 record_buf
[0] = reg_rd
;
13247 record_buf
[1] = ARM_PS_REGNUM
;
13248 thumb2_insn_r
->reg_rec_count
= 2;
13251 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13253 return ARM_RECORD_SUCCESS
;
13256 /* Generic handler for thumb2 instructions which effect destination and PS
13260 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
13263 uint32_t record_buf
[8];
13265 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13267 record_buf
[0] = reg_rd
;
13268 record_buf
[1] = ARM_PS_REGNUM
;
13269 thumb2_insn_r
->reg_rec_count
= 2;
13271 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13273 return ARM_RECORD_SUCCESS
;
13276 /* Handler for thumb2 branch and miscellaneous control instructions. */
13279 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
13281 uint32_t op
, op1
, op2
;
13282 uint32_t record_buf
[8];
13284 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13285 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
13286 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13288 /* Handle MSR insn. */
13289 if (!(op1
& 0x2) && 0x38 == op
)
13293 /* CPSR is going to be changed. */
13294 record_buf
[0] = ARM_PS_REGNUM
;
13295 thumb2_insn_r
->reg_rec_count
= 1;
13299 arm_record_unsupported_insn(thumb2_insn_r
);
13303 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
13306 record_buf
[0] = ARM_PS_REGNUM
;
13307 record_buf
[1] = ARM_LR_REGNUM
;
13308 thumb2_insn_r
->reg_rec_count
= 2;
13311 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13313 return ARM_RECORD_SUCCESS
;
13316 /* Handler for thumb2 store single data item instructions. */
13319 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
13321 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13323 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
13324 uint32_t address
, offset_addr
;
13325 uint32_t record_buf
[8], record_buf_mem
[8];
13328 ULONGEST u_regval
[2];
13330 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
13331 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
13332 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13333 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13335 if (bit (thumb2_insn_r
->arm_insn
, 23))
13338 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
13339 offset_addr
= u_regval
[0] + offset_imm
;
13340 address
= offset_addr
;
13345 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
13347 /* Handle STRB (register). */
13348 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13349 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
13350 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
13351 offset_addr
= u_regval
[1] << shift_imm
;
13352 address
= u_regval
[0] + offset_addr
;
13356 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13357 if (bit (thumb2_insn_r
->arm_insn
, 10))
13359 if (bit (thumb2_insn_r
->arm_insn
, 9))
13360 offset_addr
= u_regval
[0] + offset_imm
;
13362 offset_addr
= u_regval
[0] - offset_imm
;
13364 address
= offset_addr
;
13367 address
= u_regval
[0];
13373 /* Store byte instructions. */
13376 record_buf_mem
[0] = 1;
13378 /* Store half word instructions. */
13381 record_buf_mem
[0] = 2;
13383 /* Store word instructions. */
13386 record_buf_mem
[0] = 4;
13390 gdb_assert_not_reached ("no decoding pattern found");
13394 record_buf_mem
[1] = address
;
13395 thumb2_insn_r
->mem_rec_count
= 1;
13396 record_buf
[0] = reg_rn
;
13397 thumb2_insn_r
->reg_rec_count
= 1;
13399 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13401 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13403 return ARM_RECORD_SUCCESS
;
13406 /* Handler for thumb2 load memory hints instructions. */
13409 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
13411 uint32_t record_buf
[8];
13412 uint32_t reg_rt
, reg_rn
;
13414 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13415 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13417 if (ARM_PC_REGNUM
!= reg_rt
)
13419 record_buf
[0] = reg_rt
;
13420 record_buf
[1] = reg_rn
;
13421 record_buf
[2] = ARM_PS_REGNUM
;
13422 thumb2_insn_r
->reg_rec_count
= 3;
13424 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13426 return ARM_RECORD_SUCCESS
;
13429 return ARM_RECORD_FAILURE
;
13432 /* Handler for thumb2 load word instructions. */
13435 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
13437 uint32_t opcode1
= 0, opcode2
= 0;
13438 uint32_t record_buf
[8];
13440 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13441 record_buf
[1] = ARM_PS_REGNUM
;
13442 thumb2_insn_r
->reg_rec_count
= 2;
13444 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13446 return ARM_RECORD_SUCCESS
;
13449 /* Handler for thumb2 long multiply, long multiply accumulate, and
13450 divide instructions. */
13453 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
13455 uint32_t opcode1
= 0, opcode2
= 0;
13456 uint32_t record_buf
[8];
13457 uint32_t reg_src1
= 0;
13459 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
13460 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13462 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
13464 /* Handle SMULL, UMULL, SMULAL. */
13465 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13466 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13467 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13468 record_buf
[2] = ARM_PS_REGNUM
;
13469 thumb2_insn_r
->reg_rec_count
= 3;
13471 else if (1 == opcode1
|| 3 == opcode2
)
13473 /* Handle SDIV and UDIV. */
13474 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13475 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13476 record_buf
[2] = ARM_PS_REGNUM
;
13477 thumb2_insn_r
->reg_rec_count
= 3;
13480 return ARM_RECORD_FAILURE
;
13482 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13484 return ARM_RECORD_SUCCESS
;
13487 /* Record handler for thumb32 coprocessor instructions. */
13490 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
13492 if (bit (thumb2_insn_r
->arm_insn
, 25))
13493 return arm_record_coproc_data_proc (thumb2_insn_r
);
13495 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
13498 /* Record handler for advance SIMD structure load/store instructions. */
13501 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
13503 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13504 uint32_t l_bit
, a_bit
, b_bits
;
13505 uint32_t record_buf
[128], record_buf_mem
[128];
13506 uint32_t reg_rn
, reg_vd
, address
, f_esize
, f_elem
;
13507 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
13510 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
13511 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
13512 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13513 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13514 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13515 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
13516 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
13517 f_esize
= 8 * f_ebytes
;
13518 f_elem
= 8 / f_ebytes
;
13522 ULONGEST u_regval
= 0;
13523 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13524 address
= u_regval
;
13529 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13531 if (b_bits
== 0x07)
13533 else if (b_bits
== 0x0a)
13535 else if (b_bits
== 0x06)
13537 else if (b_bits
== 0x02)
13542 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13544 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13546 record_buf_mem
[index_m
++] = f_ebytes
;
13547 record_buf_mem
[index_m
++] = address
;
13548 address
= address
+ f_ebytes
;
13549 thumb2_insn_r
->mem_rec_count
+= 1;
13554 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13556 if (b_bits
== 0x09 || b_bits
== 0x08)
13558 else if (b_bits
== 0x03)
13563 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13564 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13566 for (loop_t
= 0; loop_t
< 2; loop_t
++)
13568 record_buf_mem
[index_m
++] = f_ebytes
;
13569 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13570 thumb2_insn_r
->mem_rec_count
+= 1;
13572 address
= address
+ (2 * f_ebytes
);
13576 else if ((b_bits
& 0x0e) == 0x04)
13578 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13580 for (loop_t
= 0; loop_t
< 3; loop_t
++)
13582 record_buf_mem
[index_m
++] = f_ebytes
;
13583 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13584 thumb2_insn_r
->mem_rec_count
+= 1;
13586 address
= address
+ (3 * f_ebytes
);
13590 else if (!(b_bits
& 0x0e))
13592 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13594 for (loop_t
= 0; loop_t
< 4; loop_t
++)
13596 record_buf_mem
[index_m
++] = f_ebytes
;
13597 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13598 thumb2_insn_r
->mem_rec_count
+= 1;
13600 address
= address
+ (4 * f_ebytes
);
13606 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
13608 if (bft_size
== 0x00)
13610 else if (bft_size
== 0x01)
13612 else if (bft_size
== 0x02)
13618 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
13619 thumb2_insn_r
->mem_rec_count
= 1;
13621 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
13622 thumb2_insn_r
->mem_rec_count
= 2;
13624 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
13625 thumb2_insn_r
->mem_rec_count
= 3;
13627 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
13628 thumb2_insn_r
->mem_rec_count
= 4;
13630 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
13632 record_buf_mem
[index_m
] = f_ebytes
;
13633 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
13642 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13643 thumb2_insn_r
->reg_rec_count
= 1;
13645 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13646 thumb2_insn_r
->reg_rec_count
= 2;
13648 else if ((b_bits
& 0x0e) == 0x04)
13649 thumb2_insn_r
->reg_rec_count
= 3;
13651 else if (!(b_bits
& 0x0e))
13652 thumb2_insn_r
->reg_rec_count
= 4;
13657 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
13658 thumb2_insn_r
->reg_rec_count
= 1;
13660 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
13661 thumb2_insn_r
->reg_rec_count
= 2;
13663 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
13664 thumb2_insn_r
->reg_rec_count
= 3;
13666 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
13667 thumb2_insn_r
->reg_rec_count
= 4;
13669 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
13670 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
13674 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
13676 record_buf
[index_r
] = reg_rn
;
13677 thumb2_insn_r
->reg_rec_count
+= 1;
13680 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13682 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13687 /* Decodes thumb2 instruction type and invokes its record handler. */
13689 static unsigned int
13690 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
13692 uint32_t op
, op1
, op2
;
13694 op
= bit (thumb2_insn_r
->arm_insn
, 15);
13695 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
13696 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13700 if (!(op2
& 0x64 ))
13702 /* Load/store multiple instruction. */
13703 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
13705 else if (!((op2
& 0x64) ^ 0x04))
13707 /* Load/store (dual/exclusive) and table branch instruction. */
13708 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
13710 else if (!((op2
& 0x20) ^ 0x20))
13712 /* Data-processing (shifted register). */
13713 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13715 else if (op2
& 0x40)
13717 /* Co-processor instructions. */
13718 return thumb2_record_coproc_insn (thumb2_insn_r
);
13721 else if (op1
== 0x02)
13725 /* Branches and miscellaneous control instructions. */
13726 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
13728 else if (op2
& 0x20)
13730 /* Data-processing (plain binary immediate) instruction. */
13731 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13735 /* Data-processing (modified immediate). */
13736 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13739 else if (op1
== 0x03)
13741 if (!(op2
& 0x71 ))
13743 /* Store single data item. */
13744 return thumb2_record_str_single_data (thumb2_insn_r
);
13746 else if (!((op2
& 0x71) ^ 0x10))
13748 /* Advanced SIMD or structure load/store instructions. */
13749 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13751 else if (!((op2
& 0x67) ^ 0x01))
13753 /* Load byte, memory hints instruction. */
13754 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13756 else if (!((op2
& 0x67) ^ 0x03))
13758 /* Load halfword, memory hints instruction. */
13759 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13761 else if (!((op2
& 0x67) ^ 0x05))
13763 /* Load word instruction. */
13764 return thumb2_record_ld_word (thumb2_insn_r
);
13766 else if (!((op2
& 0x70) ^ 0x20))
13768 /* Data-processing (register) instruction. */
13769 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13771 else if (!((op2
& 0x78) ^ 0x30))
13773 /* Multiply, multiply accumulate, abs diff instruction. */
13774 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13776 else if (!((op2
& 0x78) ^ 0x38))
13778 /* Long multiply, long multiply accumulate, and divide. */
13779 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13781 else if (op2
& 0x40)
13783 /* Co-processor instructions. */
13784 return thumb2_record_coproc_insn (thumb2_insn_r
);
13791 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13792 and positive val on fauilure. */
13795 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
13797 gdb_byte buf
[insn_size
];
13799 memset (&buf
[0], 0, insn_size
);
13801 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
13803 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13805 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
13809 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13811 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13815 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
13816 uint32_t insn_size
)
13819 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13820 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13822 arm_record_data_proc_misc_ld_str
, /* 000. */
13823 arm_record_data_proc_imm
, /* 001. */
13824 arm_record_ld_st_imm_offset
, /* 010. */
13825 arm_record_ld_st_reg_offset
, /* 011. */
13826 arm_record_ld_st_multiple
, /* 100. */
13827 arm_record_b_bl
, /* 101. */
13828 arm_record_asimd_vfp_coproc
, /* 110. */
13829 arm_record_coproc_data_proc
/* 111. */
13832 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13833 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13835 thumb_record_shift_add_sub
, /* 000. */
13836 thumb_record_add_sub_cmp_mov
, /* 001. */
13837 thumb_record_ld_st_reg_offset
, /* 010. */
13838 thumb_record_ld_st_imm_offset
, /* 011. */
13839 thumb_record_ld_st_stack
, /* 100. */
13840 thumb_record_misc
, /* 101. */
13841 thumb_record_ldm_stm_swi
, /* 110. */
13842 thumb_record_branch
/* 111. */
13845 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13846 uint32_t insn_id
= 0;
13848 if (extract_arm_insn (arm_record
, insn_size
))
13852 printf_unfiltered (_("Process record: error reading memory at "
13853 "addr %s len = %d.\n"),
13854 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
13858 else if (ARM_RECORD
== record_type
)
13860 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13861 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13862 ret
= arm_record_extension_space (arm_record
);
13863 /* If this insn has fallen into extension space
13864 then we need not decode it anymore. */
13865 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
13867 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13870 else if (THUMB_RECORD
== record_type
)
13872 /* As thumb does not have condition codes, we set negative. */
13873 arm_record
->cond
= -1;
13874 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13875 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13877 else if (THUMB2_RECORD
== record_type
)
13879 /* As thumb does not have condition codes, we set negative. */
13880 arm_record
->cond
= -1;
13882 /* Swap first half of 32bit thumb instruction with second half. */
13883 arm_record
->arm_insn
13884 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13886 insn_id
= thumb2_record_decode_insn_handler (arm_record
);
13888 if (insn_id
!= ARM_RECORD_SUCCESS
)
13890 arm_record_unsupported_insn (arm_record
);
13896 /* Throw assertion. */
13897 gdb_assert_not_reached ("not a valid instruction, could not decode");
13904 /* Cleans up local record registers and memory allocations. */
13907 deallocate_reg_mem (insn_decode_record
*record
)
13909 xfree (record
->arm_regs
);
13910 xfree (record
->arm_mems
);
13914 /* Parse the current instruction and record the values of the registers and
13915 memory that will be changed in current instruction to record_arch_list".
13916 Return -1 if something is wrong. */
13919 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13920 CORE_ADDR insn_addr
)
13923 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
13924 uint32_t no_of_rec
= 0;
13925 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13926 ULONGEST t_bit
= 0, insn_id
= 0;
13928 ULONGEST u_regval
= 0;
13930 insn_decode_record arm_record
;
13932 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13933 arm_record
.regcache
= regcache
;
13934 arm_record
.this_addr
= insn_addr
;
13935 arm_record
.gdbarch
= gdbarch
;
13938 if (record_debug
> 1)
13940 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13942 paddress (gdbarch
, arm_record
.this_addr
));
13945 if (extract_arm_insn (&arm_record
, 2))
13949 printf_unfiltered (_("Process record: error reading memory at "
13950 "addr %s len = %d.\n"),
13951 paddress (arm_record
.gdbarch
,
13952 arm_record
.this_addr
), 2);
13957 /* Check the insn, whether it is thumb or arm one. */
13959 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13960 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13963 if (!(u_regval
& t_bit
))
13965 /* We are decoding arm insn. */
13966 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13970 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13971 /* is it thumb2 insn? */
13972 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13974 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13975 THUMB2_INSN_SIZE_BYTES
);
13979 /* We are decoding thumb insn. */
13980 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13986 /* Record registers. */
13987 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13988 if (arm_record
.arm_regs
)
13990 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13992 if (record_full_arch_list_add_reg
13993 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13997 /* Record memories. */
13998 if (arm_record
.arm_mems
)
14000 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
14002 if (record_full_arch_list_add_mem
14003 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
14004 arm_record
.arm_mems
[no_of_rec
].len
))
14009 if (record_full_arch_list_add_end ())
14014 deallocate_reg_mem (&arm_record
);