gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  19    Boston, MA 02110-1301, USA.  */
  20
  21 #ifndef ARM_TDEP_H
  22 #define ARM_TDEP_H
  23
  24 /* Forward declarations.  */
  25 struct gdbarch;
  26 struct regset;
  27
  28 /* Register numbers of various important registers.  Note that some of
  29    these values are "real" register numbers, and correspond to the
  30    general registers of the machine, and some are "phony" register
  31    numbers which are too large to be actual register numbers as far as
  32    the user is concerned but do serve to get the desired values when
  33    passed to read_register.  */
  34
  35 enum gdb_regnum {
  36   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  37   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  38   ARM_AP_REGNUM = 11,
  39   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  40   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  41   ARM_PC_REGNUM = 15,           /* Contains program counter */
  42   ARM_F0_REGNUM = 16,           /* first floating point register */
  43   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  44   ARM_F7_REGNUM = 23,           /* last floating point register */
  45   ARM_FPS_REGNUM = 24,          /* floating point status register */
  46   ARM_PS_REGNUM = 25,           /* Contains processor status */
  47   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  48   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  49   ARM_NUM_ARG_REGS = 4,
  50   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  51   ARM_NUM_FP_ARG_REGS = 4,
  52   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  53 };
  54
  55 /* Size of integer registers.  */
  56 #define INT_REGISTER_SIZE               4
  57
  58 /* Say how long FP registers are.  Used for documentation purposes and
  59    code readability in this header.  IEEE extended doubles are 80
  60    bits.  DWORD aligned they use 96 bits.  */
  61 #define FP_REGISTER_SIZE        12
  62
  63 /* Status registers are the same size as general purpose registers.
  64    Used for documentation purposes and code readability in this
  65    header.  */
  66 #define STATUS_REGISTER_SIZE    4
  67
  68 /* Number of machine registers.  The only define actually required
  69    is NUM_REGS.  The other definitions are used for documentation
  70    purposes and code readability.  */
  71 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  72    (and called PS for processor status) so the status bits can be cleared
  73    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  74    in PS.  */
  75 #define NUM_FREGS       8       /* Number of floating point registers.  */
  76 #define NUM_SREGS       2       /* Number of status registers.  */
  77 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  78
  79
  80 /* Instruction condition field values.  */
  81 #define INST_EQ         0x0
  82 #define INST_NE         0x1
  83 #define INST_CS         0x2
  84 #define INST_CC         0x3
  85 #define INST_MI         0x4
  86 #define INST_PL         0x5
  87 #define INST_VS         0x6
  88 #define INST_VC         0x7
  89 #define INST_HI         0x8
  90 #define INST_LS         0x9
  91 #define INST_GE         0xa
  92 #define INST_LT         0xb
  93 #define INST_GT         0xc
  94 #define INST_LE         0xd
  95 #define INST_AL         0xe
  96 #define INST_NV         0xf
  97
  98 #define FLAG_N          0x80000000
  99 #define FLAG_Z          0x40000000
 100 #define FLAG_C          0x20000000
 101 #define FLAG_V          0x10000000
 102
 103 /* Type of floating-point code in use by inferior.  There are really 3 models
 104    that are traditionally supported (plus the endianness issue), but gcc can
 105    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 106    functions are passed in floating-point registers.
 107
 108    In addition to the traditional models, VFP adds two more.
 109
 110    If you update this enum, don't forget to update fp_model_strings in
 111    arm-tdep.c.  */
 112
 113 enum arm_float_model
 114 {
 115   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 116   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 117   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 118   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 119   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 120   ARM_FLOAT_LAST        /* Keep at end.  */
 121 };
 122
 123 /* ABI used by the inferior.  */
 124 enum arm_abi_kind
 125 {
 126   ARM_ABI_AUTO,
 127   ARM_ABI_APCS,
 128   ARM_ABI_AAPCS,
 129   ARM_ABI_LAST
 130 };
 131
 132 /* Convention for returning structures.  */
 133
 134 enum struct_return
 135 {
 136   pcc_struct_return,            /* Return "short" structures in memory.  */
 137   reg_struct_return             /* Return "short" structures in registers.  */
 138 };
 139
 140 /* Target-dependent structure in gdbarch.  */
 141 struct gdbarch_tdep
 142 {
 143   /* The ABI for this architecture.  It should never be set to
 144      ARM_ABI_AUTO.  */
 145   enum arm_abi_kind arm_abi;
 146
 147   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 148
 149   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 150                                    will appear.  */
 151
 152   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 153   int arm_breakpoint_size;      /* And its size.  */
 154   const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn.  */
 155   int thumb_breakpoint_size;    /* And its size.  */
 156
 157   int jb_pc;                    /* Offset to PC value in jump buffer.
 158                                    If this is negative, longjmp support
 159                                    will be disabled.  */
 160   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 161
 162   /* Convention for returning structures.  */
 163   enum struct_return struct_return;
 164
 165   /* Cached core file helpers.  */
 166   struct regset *gregset, *fpregset;
 167 };
 168
 169
 170
 171 #ifndef LOWEST_PC
 172 #define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
 173 #endif
 174
 175 /* Prototypes for internal interfaces needed by more than one MD file.  */
 176 int arm_pc_is_thumb_dummy (CORE_ADDR);
 177
 178 int arm_pc_is_thumb (CORE_ADDR);
 179
 180 CORE_ADDR thumb_get_next_pc (CORE_ADDR);
 181
 182 CORE_ADDR arm_get_next_pc (CORE_ADDR);
 183
 184 /* Functions exported from armbsd-tdep.h.  */
 185
 186 /* Return the appropriate register set for the core section identified
 187    by SECT_NAME and SECT_SIZE.  */
 188
 189 extern const struct regset *
 190   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 191                                    const char *sect_name, size_t sect_size);
 192
 193 #endif /* arm-tdep.h */