gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7 This file is part of GDB.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef TM_MIPS_H
  24 #define TM_MIPS_H 1
  25
  26 #ifdef __STDC__
  27 struct frame_info;
  28 struct symbol;
  29 struct type;
  30 struct value;
  31 #endif
  32
  33 #include <bfd.h>
  34 #include "coff/sym.h"           /* Needed for PDR below.  */
  35 #include "coff/symconst.h"
  36
  37 #if !defined (TARGET_BYTE_ORDER_DEFAULT)
  38 #define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
  39 #endif
  40
  41 #if !defined (GDB_TARGET_IS_MIPS64)
  42 #define GDB_TARGET_IS_MIPS64 0
  43 #endif
  44
  45 #if !defined (MIPS_EABI)
  46 #define MIPS_EABI 0
  47 #endif
  48
  49 #if !defined (TARGET_MONITOR_PROMPT)
  50 #define TARGET_MONITOR_PROMPT "<IDT>"
  51 #endif
  52
  53 /* PC should be masked to remove possible MIPS16 flag */
  54 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  55 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  56 #endif
  57 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  58 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  59 #endif
  60
  61 /* Floating point is IEEE compliant */
  62 #define IEEE_FLOAT
  63
  64 /* The name of the usual type of MIPS processor that is in the target
  65    system.  */
  66
  67 #define DEFAULT_MIPS_TYPE "generic"
  68
  69 /* Remove useless bits from an instruction address.  */
  70
  71 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  72 CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
  73
  74 /* Remove useless bits from the stack pointer.  */
  75
  76 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  77
  78 /* Offset from address of function to start of its code.
  79    Zero on most machines.  */
  80
  81 #define FUNCTION_START_OFFSET 0
  82
  83 /* Advance PC across any function entry prologue instructions
  84    to reach some "real" code.  */
  85
  86 #define SKIP_PROLOGUE(pc)       pc = mips_skip_prologue (pc, 0)
  87 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
  88
  89 /* Return non-zero if PC points to an instruction which will cause a step
  90    to execute both the instruction at PC and an instruction at PC+4.  */
  91 extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
  92 #define STEP_SKIPS_DELAY_P (1)
  93 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  94
  95 /* Immediately after a function call, return the saved pc.
  96    Can't always go through the frames for this because on some machines
  97    the new frame is not set up until the new function executes
  98    some instructions.  */
  99
 100 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
 101
 102 /* Are we currently handling a signal */
 103
 104 extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
 105 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
 106
 107 /* Stack grows downward.  */
 108
 109 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 110
 111 #define BIG_ENDIAN 4321
 112
 113 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 114    16- or 32-bit breakpoint should be used.  It returns a pointer
 115    to a string of bytes that encode a breakpoint instruction, stores
 116    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 117    point to the actual memory location where the breakpoint should be
 118    inserted.  */
 119
 120 extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
 121 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 122
 123 /* Amount PC must be decremented by after a breakpoint.
 124    This is often the number of bytes in BREAKPOINT
 125    but not always.  */
 126
 127 #define DECR_PC_AFTER_BREAK 0
 128
 129 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 130    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 131    real way to know how big a register is.  */
 132
 133 #define REGISTER_SIZE 4
 134
 135 /* The size of a register.  This is predefined in tm-mips64.h.  We
 136    can't use REGISTER_SIZE because that is used for various other
 137    things.  */
 138
 139 #ifndef MIPS_REGSIZE
 140 #define MIPS_REGSIZE 4
 141 #endif
 142
 143 /* The sizes of floating point registers.  */
 144
 145 #define MIPS_FPU_SINGLE_REGSIZE 4
 146 #define MIPS_FPU_DOUBLE_REGSIZE 8
 147
 148 /* Number of machine registers */
 149
 150 #ifndef NUM_REGS
 151 #define NUM_REGS 90
 152 #endif
 153
 154 /* Initializer for an array of names of registers.
 155    There should be NUM_REGS strings in this initializer.  */
 156
 157 #ifndef REGISTER_NAMES
 158 #define REGISTER_NAMES  \
 159     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 160         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 161         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 162         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 163         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 164         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 165         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 166         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 167         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 168         "fsr",  "fir",  "fp",   "", \
 169         "",     "",     "",     "",     "",     "",     "",     "", \
 170         "",     "",     "",     "",     "",     "",     "",     "", \
 171     }
 172 #endif
 173
 174 /* Register numbers of various important registers.
 175    Note that some of these values are "real" register numbers,
 176    and correspond to the general registers of the machine,
 177    and some are "phony" register numbers which are too large
 178    to be actual register numbers as far as the user is concerned
 179    but do serve to get the desired values when passed to read_register.  */
 180
 181 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 182 #define V0_REGNUM 2             /* Function integer return value */
 183 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 184 #if MIPS_EABI
 185 #  define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 186 #  define MIPS_NUM_ARG_REGS 8
 187 #else
 188 #  define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 189 #  define MIPS_NUM_ARG_REGS 4
 190 #endif
 191 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 192 #define SP_REGNUM 29            /* Contains address of top of stack */
 193 #define RA_REGNUM 31            /* Contains return address value */
 194 #define PS_REGNUM 32            /* Contains processor status */
 195 #define HI_REGNUM 34            /* Multiple/divide temp */
 196 #define LO_REGNUM 33            /* ... */
 197 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 198 #define CAUSE_REGNUM 36         /* describes last exception */
 199 #define PC_REGNUM 37            /* Contains program counter */
 200 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 201 #define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */
 202 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 203 #  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 204 #  define MIPS_NUM_FP_ARG_REGS 8
 205 #else                           /* old ABI uses F12 through F15 for args */
 206 #  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 207 #  define MIPS_NUM_FP_ARG_REGS 4
 208 #endif
 209 #define FCRCS_REGNUM 70         /* FP control/status */
 210 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 211 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 212 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 213 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 214 #define PRID_REGNUM 89          /* Processor ID */
 215 #define LAST_EMBED_REGNUM 89    /* Last one */
 216
 217 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 218    of register dumps. */
 219
 220 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 221 extern void mips_do_registers_info PARAMS ((int, int));
 222
 223 /* Total amount of space needed to store our copies of the machine's
 224    register state, the array `registers'.  */
 225
 226 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 227
 228 /* Index within `registers' of the first byte of the space for
 229    register N.  */
 230
 231 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 232
 233 /* Number of bytes of storage in the actual machine representation
 234    for register N. */
 235
 236 #define REGISTER_RAW_SIZE(N) REGISTER_VIRTUAL_SIZE(N)
 237
 238 /* Number of bytes of storage in the program's representation
 239    for register N. */
 240
 241 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 242
 243 /* Largest value REGISTER_RAW_SIZE can have.  */
 244
 245 #define MAX_REGISTER_RAW_SIZE 8
 246
 247 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 248
 249 #define MAX_REGISTER_VIRTUAL_SIZE 8
 250
 251 /* Return the GDB type object for the "standard" data type of data in
 252    register N.  */
 253
 254 #ifndef REGISTER_VIRTUAL_TYPE
 255 #define REGISTER_VIRTUAL_TYPE(N) \
 256         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 257          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 258          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 259          : builtin_type_int)
 260 #endif
 261
 262 /* All mips targets store doubles in a register pair with the least
 263    significant register in the lower numbered register.
 264    If the target is big endian, double register values need conversion
 265    between memory and register formats.  */
 266
 267 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 268   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 269           && REGISTER_RAW_SIZE (n) == 4                                 \
 270           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 271           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 272           && TYPE_LENGTH(type) == 8) {                                  \
 273         char __temp[4];                                                 \
 274         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 275         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 276         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 277
 278 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 279   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 280           && REGISTER_RAW_SIZE (n) == 4                                 \
 281           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 282           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 283           && TYPE_LENGTH(type) == 8) {                                  \
 284         char __temp[4];                                                 \
 285         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 286         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 287         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 288
 289 /* Store the address of the place in which to copy the structure the
 290    subroutine will return.  Handled by mips_push_arguments.  */
 291
 292 #define STORE_STRUCT_RETURN(addr, sp)   /**/
 293
 294 /* Extract from an array REGBUF containing the (raw) register state
 295    a function return value of type TYPE, and copy that, in virtual format,
 296    into VALBUF.  XXX floats */
 297
 298 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 299   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 300 extern void
 301 mips_extract_return_value PARAMS ((struct type *, char [], char *));
 302
 303 /* Write into appropriate registers a function return value
 304    of type TYPE, given in virtual format.  */
 305
 306 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 307   mips_store_return_value(TYPE, VALBUF)
 308 extern void mips_store_return_value PARAMS ((struct type *, char *));
 309
 310 /* Extract from an array REGBUF containing the (raw) register state
 311    the address in which a function should return its structure value,
 312    as a CORE_ADDR (or an expression that can be used as one).  */
 313 /* The address is passed in a0 upon entry to the function, but when
 314    the function exits, the compiler has copied the value to v0.  This
 315    convention is specified by the System V ABI, so I think we can rely
 316    on it.  */
 317
 318 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 319   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 320                     REGISTER_RAW_SIZE (V0_REGNUM)))
 321
 322 extern use_struct_convention_fn mips_use_struct_convention;
 323 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 324 \f
 325 /* Describe the pointer in each stack frame to the previous stack frame
 326    (its caller).  */
 327
 328 /* FRAME_CHAIN takes a frame's nominal address
 329    and produces the frame's chain-pointer. */
 330
 331 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 332 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
 333
 334 /* Define other aspects of the stack frame.  */
 335
 336
 337 /* A macro that tells us whether the function invocation represented
 338    by FI does not have a frame on the stack associated with it.  If it
 339    does not, FRAMELESS is set to 1, else 0.  */
 340 /* We handle this differently for mips, and maybe we should not */
 341
 342 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}
 343
 344 /* Saved Pc.  */
 345
 346 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 347 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
 348
 349 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 350
 351 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 352
 353 /* Return number of args passed to a frame.
 354    Can return -1, meaning no way to tell.  */
 355
 356 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
 357 extern int mips_frame_num_args PARAMS ((struct frame_info *));
 358
 359 /* Return number of bytes at start of arglist that are not really args.  */
 360
 361 #define FRAME_ARGS_SKIP 0
 362
 363 /* Put here the code to store, into a struct frame_saved_regs,
 364    the addresses of the saved registers of frame described by FRAME_INFO.
 365    This includes special registers such as pc and fp saved in special
 366    ways in the stack frame.  sp is even more special:
 367    the address we return for it IS the sp for the next frame.  */
 368
 369 #define FRAME_INIT_SAVED_REGS(frame_info) \
 370   do { \
 371     if ((frame_info)->saved_regs == NULL) \
 372       mips_find_saved_regs (frame_info); \
 373     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 374   } while (0)
 375 extern void mips_find_saved_regs PARAMS ((struct frame_info *));
 376
 377 \f
 378 /* Things needed for making the inferior call functions.  */
 379
 380 /* Stack must be aligned on 32-bit boundaries when synthesizing
 381    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 382    handle it. */
 383
 384 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 385     sp = mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))
 386 extern CORE_ADDR
 387 mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
 388
 389 /* Push an empty stack frame, to record the current PC, etc.  */
 390
 391 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 392 extern void mips_push_dummy_frame PARAMS ((void));
 393
 394 /* Discard from the stack the innermost frame, restoring all registers.  */
 395
 396 #define POP_FRAME               mips_pop_frame()
 397 extern void mips_pop_frame PARAMS ((void));
 398
 399 #define CALL_DUMMY { 0 }
 400
 401 #define CALL_DUMMY_START_OFFSET (0)
 402
 403 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 404
 405 /* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
 406    It doesn't hurt to do this on other systems; $t9 will be ignored.  */
 407 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 408     write_register(T9_REGNUM, fun)
 409
 410 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 411
 412 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 413 extern CORE_ADDR mips_call_dummy_address PARAMS ((void));
 414
 415 /* There's a mess in stack frame creation.  See comments in blockframe.c
 416    near reference to INIT_FRAME_PC_FIRST.  */
 417
 418 #define INIT_FRAME_PC(fromleaf, prev) /* nada */
 419
 420 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 421    mips_init_frame_pc_first(fromleaf, prev)
 422 extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
 423
 424 /* Special symbol found in blocks associated with routines.  We can hang
 425    mips_extra_func_info_t's off of this.  */
 426
 427 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 428 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
 429
 430 /* Specific information about a procedure.
 431    This overlays the MIPS's PDR records,
 432    mipsread.c (ab)uses this to save memory */
 433
 434 typedef struct mips_extra_func_info {
 435         long    numargs;        /* number of args to procedure (was iopt) */
 436         bfd_vma high_addr;      /* upper address bound */
 437         long    frame_adjust;   /* offset of FP from SP (used on MIPS16) */
 438         PDR     pdr;            /* Procedure descriptor record */
 439 } *mips_extra_func_info_t;
 440
 441 #define EXTRA_FRAME_INFO \
 442   mips_extra_func_info_t proc_desc; \
 443   int num_args;
 444
 445 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
 446 extern void init_extra_frame_info PARAMS ((struct frame_info *));
 447
 448 #define PRINT_EXTRA_FRAME_INFO(fi) \
 449   { \
 450     if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
 451       printf_filtered (" frame pointer is at %s+%d\n", \
 452                        REGISTER_NAME (fi->proc_desc->pdr.framereg), \
 453                                  fi->proc_desc->pdr.frameoffset); \
 454   }
 455
 456 /* It takes two values to specify a frame on the MIPS.
 457
 458    In fact, the *PC* is the primary value that sets up a frame.  The
 459    PC is looked up to see what function it's in; symbol information
 460    from that function tells us which register is the frame pointer
 461    base, and what offset from there is the "virtual frame pointer".
 462    (This is usually an offset from SP.)  On most non-MIPS machines,
 463    the primary value is the SP, and the PC, if needed, disambiguates
 464    multiple functions with the same SP.  But on the MIPS we can't do
 465    that since the PC is not stored in the same part of the frame every
 466    time.  This does not seem to be a very clever way to set up frames,
 467    but there is nothing we can do about that).  */
 468
 469 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 470 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
 471
 472 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 473
 474 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 475
 476 /* Convert a ecoff register number to a gdb REGNUM */
 477
 478 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 479
 480 /* If the current gcc for for this target does not produce correct debugging
 481    information for float parameters, both prototyped and unprototyped, then
 482    define this macro.  This forces gdb to  always assume that floats are
 483    passed as doubles and then converted in the callee.
 484
 485    For the mips chip, it appears that the debug info marks the parameters as
 486    floats regardless of whether the function is prototyped, but the actual
 487    values are passed as doubles for the non-prototyped case and floats for
 488    the prototyped case.  Thus we choose to make the non-prototyped case work
 489    for C and break the prototyped case, since the non-prototyped case is
 490    probably much more common.  (FIXME). */
 491
 492 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
 493
 494 /* Select the default mips disassembler */
 495
 496 #define TM_PRINT_INSN_MACH 0
 497
 498
 499 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 500 extern CORE_ADDR sigtramp_address, sigtramp_end;
 501 extern void fixup_sigtramp PARAMS ((void));
 502
 503 /* Defined in mips-tdep.c and used in remote-mips.c */
 504 extern char *mips_read_processor_type PARAMS ((void));
 505
 506 /* Functions for dealing with MIPS16 call and return stubs.  */
 507 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 508 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 509 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 510 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 511 extern int mips_in_call_stub PARAMS ((CORE_ADDR pc,  char *name));
 512 extern int mips_in_return_stub PARAMS ((CORE_ADDR pc,  char *name));
 513 extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
 514 extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
 515
 516 #ifndef TARGET_MIPS
 517 #define TARGET_MIPS
 518 #endif
 519
 520 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 521 #define MIPS_INSTLEN 4          /* Length of an instruction */
 522 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16*/
 523 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 524 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 525
 526 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 527    macros to test, set, or clear bit 0 of addresses.  */
 528 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 529 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 530 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 531
 532 #endif  /* TM_MIPS_H */
 533
 534 /* Macros for setting and testing a bit in a minimal symbol that
 535    marks it as 16-bit function.  The MSB of the minimal symbol's
 536    "info" field is used for this purpose. This field is already
 537    being used to store the symbol size, so the assumption is
 538    that the symbol size cannot exceed 2^31.
 539
 540    ELF_MAKE_MSYMBOL_SPECIAL
 541                         tests whether an ELF symbol is "special", i.e. refers
 542                         to a 16-bit function, and sets a "special" bit in a
 543                         minimal symbol to mark it as a 16-bit function
 544    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 545    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 546                         the "info" field with the "special" bit masked out
 547 */
 548
 549 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 550  { \
 551   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 552     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 553     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 554   } \
 555  }
 556
 557 #define MSYMBOL_IS_SPECIAL(msym) \
 558   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 559 #define MSYMBOL_SIZE(msym) \
 560   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)