gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #ifndef TM_MIPS_H
  25 #define TM_MIPS_H 1
  26
  27 #ifdef __STDC__
  28 struct frame_info;
  29 struct symbol;
  30 struct type;
  31 struct value;
  32 #endif
  33
  34 #include <bfd.h>
  35 #include "coff/sym.h"           /* Needed for PDR below.  */
  36 #include "coff/symconst.h"
  37
  38 #if !defined (TARGET_BYTE_ORDER_DEFAULT)
  39 #define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
  40 #endif
  41
  42 #if !defined (GDB_TARGET_IS_MIPS64)
  43 #define GDB_TARGET_IS_MIPS64 0
  44 #endif
  45
  46 #if !defined (MIPS_EABI)
  47 #define MIPS_EABI 0
  48 #endif
  49
  50 #if !defined (TARGET_MONITOR_PROMPT)
  51 #define TARGET_MONITOR_PROMPT "<IDT>"
  52 #endif
  53
  54 /* PC should be masked to remove possible MIPS16 flag */
  55 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  56 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  57 #endif
  58 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  59 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  60 #endif
  61
  62 /* Floating point is IEEE compliant */
  63 #define IEEE_FLOAT
  64
  65 /* The name of the usual type of MIPS processor that is in the target
  66    system.  */
  67
  68 #define DEFAULT_MIPS_TYPE "generic"
  69
  70 /* Remove useless bits from an instruction address.  */
  71
  72 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  73 CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
  74
  75 /* Remove useless bits from the stack pointer.  */
  76
  77 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  78
  79 /* Offset from address of function to start of its code.
  80    Zero on most machines.  */
  81
  82 #define FUNCTION_START_OFFSET 0
  83
  84 /* Advance PC across any function entry prologue instructions
  85    to reach some "real" code.  */
  86
  87 #define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
  88 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
  89
  90 /* Return non-zero if PC points to an instruction which will cause a step
  91    to execute both the instruction at PC and an instruction at PC+4.  */
  92 extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
  93 #define STEP_SKIPS_DELAY_P (1)
  94 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  95
  96 /* Immediately after a function call, return the saved pc.
  97    Can't always go through the frames for this because on some machines
  98    the new frame is not set up until the new function executes
  99    some instructions.  */
 100
 101 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
 102
 103 /* Are we currently handling a signal */
 104
 105 extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
 106 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
 107
 108 /* Stack grows downward.  */
 109
 110 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 111
 112 #define BIG_ENDIAN 4321
 113
 114 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 115    16- or 32-bit breakpoint should be used.  It returns a pointer
 116    to a string of bytes that encode a breakpoint instruction, stores
 117    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 118    point to the actual memory location where the breakpoint should be
 119    inserted.  */
 120
 121 extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
 122 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 123
 124 /* Amount PC must be decremented by after a breakpoint.
 125    This is often the number of bytes in BREAKPOINT
 126    but not always.  */
 127
 128 #define DECR_PC_AFTER_BREAK 0
 129
 130 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 131    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 132    real way to know how big a register is.  */
 133
 134 #define REGISTER_SIZE 4
 135
 136 /* The size of a register.  This is predefined in tm-mips64.h.  We
 137    can't use REGISTER_SIZE because that is used for various other
 138    things.  */
 139
 140 #ifndef MIPS_REGSIZE
 141 #define MIPS_REGSIZE 4
 142 #endif
 143
 144 /* The sizes of floating point registers.  */
 145
 146 #define MIPS_FPU_SINGLE_REGSIZE 4
 147 #define MIPS_FPU_DOUBLE_REGSIZE 8
 148
 149 /* Number of machine registers */
 150
 151 #ifndef NUM_REGS
 152 #define NUM_REGS 90
 153 #endif
 154
 155 /* Given the register index, return the name of the corresponding
 156    register. */
 157 extern char *mips_register_name PARAMS ((int regnr));
 158 #define REGISTER_NAME(i) mips_register_name (i)
 159
 160 /* Initializer for an array of names of registers.
 161    There should be NUM_REGS strings in this initializer.  */
 162
 163 #ifndef MIPS_REGISTER_NAMES
 164 #define MIPS_REGISTER_NAMES     \
 165     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 166         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 167         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 168         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 169         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 170         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 171         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 172         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 173         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 174         "fsr",  "fir",  "fp",   "", \
 175         "",     "",     "",     "",     "",     "",     "",     "", \
 176         "",     "",     "",     "",     "",     "",     "",     "", \
 177     }
 178 #endif
 179
 180 /* Register numbers of various important registers.
 181    Note that some of these values are "real" register numbers,
 182    and correspond to the general registers of the machine,
 183    and some are "phony" register numbers which are too large
 184    to be actual register numbers as far as the user is concerned
 185    but do serve to get the desired values when passed to read_register.  */
 186
 187 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 188 #define V0_REGNUM 2             /* Function integer return value */
 189 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 190 #if MIPS_EABI
 191 #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 192 #define MIPS_NUM_ARG_REGS 8
 193 #else
 194 #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 195 #define MIPS_NUM_ARG_REGS 4
 196 #endif
 197 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 198 #define SP_REGNUM 29            /* Contains address of top of stack */
 199 #define RA_REGNUM 31            /* Contains return address value */
 200 #define PS_REGNUM 32            /* Contains processor status */
 201 #define HI_REGNUM 34            /* Multiple/divide temp */
 202 #define LO_REGNUM 33            /* ... */
 203 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 204 #define CAUSE_REGNUM 36         /* describes last exception */
 205 #define PC_REGNUM 37            /* Contains program counter */
 206 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 207 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 208 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 209 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 210 #define MIPS_NUM_FP_ARG_REGS 8
 211 #else /* old ABI uses F12 through F15 for args */
 212 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 213 #define MIPS_NUM_FP_ARG_REGS 4
 214 #endif
 215 #define FCRCS_REGNUM 70         /* FP control/status */
 216 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 217 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 218 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 219 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 220 #define PRID_REGNUM 89          /* Processor ID */
 221 #define LAST_EMBED_REGNUM 89    /* Last one */
 222
 223 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 224    of register dumps. */
 225
 226 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 227 extern void mips_do_registers_info PARAMS ((int, int));
 228
 229 /* Total amount of space needed to store our copies of the machine's
 230    register state, the array `registers'.  */
 231
 232 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 233
 234 /* Index within `registers' of the first byte of the space for
 235    register N.  */
 236
 237 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 238
 239 /* Number of bytes of storage in the actual machine representation
 240    for register N. */
 241
 242 #define REGISTER_RAW_SIZE(N) REGISTER_VIRTUAL_SIZE(N)
 243
 244 /* Number of bytes of storage in the program's representation
 245    for register N. */
 246
 247 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 248
 249 /* Largest value REGISTER_RAW_SIZE can have.  */
 250
 251 #define MAX_REGISTER_RAW_SIZE 8
 252
 253 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 254
 255 #define MAX_REGISTER_VIRTUAL_SIZE 8
 256
 257 /* Return the GDB type object for the "standard" data type of data in
 258    register N.  */
 259
 260 #ifndef REGISTER_VIRTUAL_TYPE
 261 #define REGISTER_VIRTUAL_TYPE(N) \
 262         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 263          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 264          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 265          : builtin_type_int)
 266 #endif
 267
 268 /* All mips targets store doubles in a register pair with the least
 269    significant register in the lower numbered register.
 270    If the target is big endian, double register values need conversion
 271    between memory and register formats.  */
 272
 273 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 274   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 275           && REGISTER_RAW_SIZE (n) == 4                                 \
 276           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 277           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 278           && TYPE_LENGTH(type) == 8) {                                  \
 279         char __temp[4];                                                 \
 280         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 281         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 282         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 283
 284 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 285   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 286           && REGISTER_RAW_SIZE (n) == 4                                 \
 287           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 288           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 289           && TYPE_LENGTH(type) == 8) {                                  \
 290         char __temp[4];                                                 \
 291         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 292         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 293         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 294
 295 /* Store the address of the place in which to copy the structure the
 296    subroutine will return.  Handled by mips_push_arguments.  */
 297
 298 #define STORE_STRUCT_RETURN(addr, sp)
 299 /**/
 300
 301 /* Extract from an array REGBUF containing the (raw) register state
 302    a function return value of type TYPE, and copy that, in virtual format,
 303    into VALBUF.  XXX floats */
 304
 305 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 306   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 307 extern void
 308 mips_extract_return_value PARAMS ((struct type *, char[], char *));
 309
 310 /* Write into appropriate registers a function return value
 311    of type TYPE, given in virtual format.  */
 312
 313 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 314   mips_store_return_value(TYPE, VALBUF)
 315 extern void mips_store_return_value PARAMS ((struct type *, char *));
 316
 317 /* Extract from an array REGBUF containing the (raw) register state
 318    the address in which a function should return its structure value,
 319    as a CORE_ADDR (or an expression that can be used as one).  */
 320 /* The address is passed in a0 upon entry to the function, but when
 321    the function exits, the compiler has copied the value to v0.  This
 322    convention is specified by the System V ABI, so I think we can rely
 323    on it.  */
 324
 325 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 326   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 327                     REGISTER_RAW_SIZE (V0_REGNUM)))
 328
 329 extern use_struct_convention_fn mips_use_struct_convention;
 330 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 331 \f
 332 /* Describe the pointer in each stack frame to the previous stack frame
 333    (its caller).  */
 334
 335 /* FRAME_CHAIN takes a frame's nominal address
 336    and produces the frame's chain-pointer. */
 337
 338 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 339 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
 340
 341 /* Define other aspects of the stack frame.  */
 342
 343
 344 /* A macro that tells us whether the function invocation represented
 345    by FI does not have a frame on the stack associated with it.  If it
 346    does not, FRAMELESS is set to 1, else 0.  */
 347 /* We handle this differently for mips, and maybe we should not */
 348
 349 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 350
 351 /* Saved Pc.  */
 352
 353 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 354 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
 355
 356 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 357
 358 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 359
 360 /* Return number of args passed to a frame.
 361    Can return -1, meaning no way to tell.  */
 362
 363 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 364 extern int mips_frame_num_args PARAMS ((struct frame_info *));
 365
 366 /* Return number of bytes at start of arglist that are not really args.  */
 367
 368 #define FRAME_ARGS_SKIP 0
 369
 370 /* Put here the code to store, into a struct frame_saved_regs,
 371    the addresses of the saved registers of frame described by FRAME_INFO.
 372    This includes special registers such as pc and fp saved in special
 373    ways in the stack frame.  sp is even more special:
 374    the address we return for it IS the sp for the next frame.  */
 375
 376 #define FRAME_INIT_SAVED_REGS(frame_info) \
 377   do { \
 378     if ((frame_info)->saved_regs == NULL) \
 379       mips_find_saved_regs (frame_info); \
 380     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 381   } while (0)
 382 extern void mips_find_saved_regs PARAMS ((struct frame_info *));
 383 \f
 384
 385 /* Things needed for making the inferior call functions.  */
 386
 387 /* Stack must be aligned on 32-bit boundaries when synthesizing
 388    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 389    handle it. */
 390
 391 extern CORE_ADDR mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
 392 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 393   (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
 394
 395 extern CORE_ADDR mips_push_return_address PARAMS ((CORE_ADDR pc, CORE_ADDR sp));
 396 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 397
 398 /* Push an empty stack frame, to record the current PC, etc.  */
 399
 400 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 401 extern void mips_push_dummy_frame PARAMS ((void));
 402
 403 /* Discard from the stack the innermost frame, restoring all registers.  */
 404
 405 #define POP_FRAME               mips_pop_frame()
 406 extern void mips_pop_frame PARAMS ((void));
 407
 408 #define CALL_DUMMY { 0 }
 409
 410 #define CALL_DUMMY_START_OFFSET (0)
 411
 412 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 413
 414 /* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
 415    It doesn't hurt to do this on other systems; $t9 will be ignored.  */
 416 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 417     write_register(T9_REGNUM, fun)
 418
 419 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 420
 421 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 422 extern CORE_ADDR mips_call_dummy_address PARAMS ((void));
 423
 424 /* There's a mess in stack frame creation.  See comments in blockframe.c
 425    near reference to INIT_FRAME_PC_FIRST.  */
 426
 427 #define INIT_FRAME_PC(fromleaf, prev)   /* nada */
 428
 429 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 430    mips_init_frame_pc_first(fromleaf, prev)
 431 extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
 432
 433 /* Special symbol found in blocks associated with routines.  We can hang
 434    mips_extra_func_info_t's off of this.  */
 435
 436 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 437 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
 438
 439 /* Specific information about a procedure.
 440    This overlays the MIPS's PDR records,
 441    mipsread.c (ab)uses this to save memory */
 442
 443 typedef struct mips_extra_func_info
 444   {
 445     long numargs;               /* number of args to procedure (was iopt) */
 446     bfd_vma high_addr;          /* upper address bound */
 447     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 448     PDR pdr;                    /* Procedure descriptor record */
 449   }
 450  *mips_extra_func_info_t;
 451
 452 extern void mips_init_extra_frame_info PARAMS ((int fromleaf, struct frame_info *));
 453 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 454   mips_init_extra_frame_info(fromleaf, fci)
 455
 456 extern void mips_print_extra_frame_info PARAMS ((struct frame_info * frame));
 457 #define PRINT_EXTRA_FRAME_INFO(fi) \
 458   mips_print_extra_frame_info (fi)
 459
 460 /* It takes two values to specify a frame on the MIPS.
 461
 462    In fact, the *PC* is the primary value that sets up a frame.  The
 463    PC is looked up to see what function it's in; symbol information
 464    from that function tells us which register is the frame pointer
 465    base, and what offset from there is the "virtual frame pointer".
 466    (This is usually an offset from SP.)  On most non-MIPS machines,
 467    the primary value is the SP, and the PC, if needed, disambiguates
 468    multiple functions with the same SP.  But on the MIPS we can't do
 469    that since the PC is not stored in the same part of the frame every
 470    time.  This does not seem to be a very clever way to set up frames,
 471    but there is nothing we can do about that).  */
 472
 473 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 474 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
 475
 476 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 477
 478 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 479
 480 /* Convert a ecoff register number to a gdb REGNUM */
 481
 482 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 483
 484 /* If the current gcc for for this target does not produce correct debugging
 485    information for float parameters, both prototyped and unprototyped, then
 486    define this macro.  This forces gdb to  always assume that floats are
 487    passed as doubles and then converted in the callee.
 488
 489    For the mips chip, it appears that the debug info marks the parameters as
 490    floats regardless of whether the function is prototyped, but the actual
 491    values are passed as doubles for the non-prototyped case and floats for
 492    the prototyped case.  Thus we choose to make the non-prototyped case work
 493    for C and break the prototyped case, since the non-prototyped case is
 494    probably much more common.  (FIXME). */
 495
 496 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
 497
 498 /* Select the default mips disassembler */
 499
 500 #define TM_PRINT_INSN_MACH 0
 501
 502
 503 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 504 extern CORE_ADDR sigtramp_address, sigtramp_end;
 505 extern void fixup_sigtramp PARAMS ((void));
 506
 507 /* Defined in mips-tdep.c and used in remote-mips.c */
 508 extern char *mips_read_processor_type PARAMS ((void));
 509
 510 /* Functions for dealing with MIPS16 call and return stubs.  */
 511 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 512 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 513 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 514 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 515 extern int mips_in_call_stub PARAMS ((CORE_ADDR pc, char *name));
 516 extern int mips_in_return_stub PARAMS ((CORE_ADDR pc, char *name));
 517 extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
 518 extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
 519
 520 #ifndef TARGET_MIPS
 521 #define TARGET_MIPS
 522 #endif
 523
 524 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 525 #define MIPS_INSTLEN 4          /* Length of an instruction */
 526 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 527 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 528 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 529
 530 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 531    macros to test, set, or clear bit 0 of addresses.  */
 532 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 533 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 534 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 535
 536 #endif /* TM_MIPS_H */
 537
 538 /* Macros for setting and testing a bit in a minimal symbol that
 539    marks it as 16-bit function.  The MSB of the minimal symbol's
 540    "info" field is used for this purpose. This field is already
 541    being used to store the symbol size, so the assumption is
 542    that the symbol size cannot exceed 2^31.
 543
 544    ELF_MAKE_MSYMBOL_SPECIAL
 545    tests whether an ELF symbol is "special", i.e. refers
 546    to a 16-bit function, and sets a "special" bit in a
 547    minimal symbol to mark it as a 16-bit function
 548    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 549    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 550    the "info" field with the "special" bit masked out
 551  */
 552
 553 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 554  { \
 555   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 556     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 557     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 558   } \
 559  }
 560
 561 #define MSYMBOL_IS_SPECIAL(msym) \
 562   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 563 #define MSYMBOL_SIZE(msym) \
 564   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)