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1 /* Target-dependent code for the CSKY architecture, for GDB.
2
3 Copyright (C) 2010-2022 Free Software Foundation, Inc.
4
5 Contributed by C-SKY Microsystems and Mentor Graphics.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "defs.h"
23 #include "gdbsupport/gdb_assert.h"
24 #include "frame.h"
25 #include "inferior.h"
26 #include "symtab.h"
27 #include "value.h"
28 #include "gdbcmd.h"
29 #include "language.h"
30 #include "gdbcore.h"
31 #include "symfile.h"
32 #include "objfiles.h"
33 #include "gdbtypes.h"
34 #include "target.h"
35 #include "arch-utils.h"
36 #include "regcache.h"
37 #include "osabi.h"
38 #include "block.h"
39 #include "reggroups.h"
40 #include "elf/csky.h"
41 #include "elf-bfd.h"
42 #include "symcat.h"
43 #include "sim-regno.h"
44 #include "dis-asm.h"
45 #include "frame-unwind.h"
46 #include "frame-base.h"
47 #include "trad-frame.h"
48 #include "infcall.h"
49 #include "floatformat.h"
50 #include "remote.h"
51 #include "target-descriptions.h"
52 #include "dwarf2/frame.h"
53 #include "user-regs.h"
54 #include "valprint.h"
55 #include "csky-tdep.h"
56 #include "regset.h"
57 #include "opcode/csky.h"
58 #include <algorithm>
59 #include <vector>
60
61 /* Control debugging information emitted in this file. */
62
63 static bool csky_debug = false;
64
65 static const reggroup *cr_reggroup;
66 static const reggroup *fr_reggroup;
67 static const reggroup *vr_reggroup;
68 static const reggroup *mmu_reggroup;
69 static const reggroup *prof_reggroup;
70
71 static const char *csky_supported_tdesc_feature_names[] = {
72 (const char *)"org.gnu.csky.abiv2.gpr",
73 (const char *)"org.gnu.csky.abiv2.fpu",
74 (const char *)"org.gnu.csky.abiv2.cr",
75 (const char *)"org.gnu.csky.abiv2.fvcr",
76 (const char *)"org.gnu.csky.abiv2.mmu",
77 (const char *)"org.gnu.csky.abiv2.tee",
78 (const char *)"org.gnu.csky.abiv2.fpu2",
79 (const char *)"org.gnu.csky.abiv2.bank0",
80 (const char *)"org.gnu.csky.abiv2.bank1",
81 (const char *)"org.gnu.csky.abiv2.bank2",
82 (const char *)"org.gnu.csky.abiv2.bank3",
83 (const char *)"org.gnu.csky.abiv2.bank4",
84 (const char *)"org.gnu.csky.abiv2.bank5",
85 (const char *)"org.gnu.csky.abiv2.bank6",
86 (const char *)"org.gnu.csky.abiv2.bank7",
87 (const char *)"org.gnu.csky.abiv2.bank8",
88 (const char *)"org.gnu.csky.abiv2.bank9",
89 (const char *)"org.gnu.csky.abiv2.bank10",
90 (const char *)"org.gnu.csky.abiv2.bank11",
91 (const char *)"org.gnu.csky.abiv2.bank12",
92 (const char *)"org.gnu.csky.abiv2.bank13",
93 (const char *)"org.gnu.csky.abiv2.bank14",
94 (const char *)"org.gnu.csky.abiv2.bank15",
95 (const char *)"org.gnu.csky.abiv2.bank16",
96 (const char *)"org.gnu.csky.abiv2.bank17",
97 (const char *)"org.gnu.csky.abiv2.bank18",
98 (const char *)"org.gnu.csky.abiv2.bank19",
99 (const char *)"org.gnu.csky.abiv2.bank20",
100 (const char *)"org.gnu.csky.abiv2.bank21",
101 (const char *)"org.gnu.csky.abiv2.bank22",
102 (const char *)"org.gnu.csky.abiv2.bank23",
103 (const char *)"org.gnu.csky.abiv2.bank24",
104 (const char *)"org.gnu.csky.abiv2.bank25",
105 (const char *)"org.gnu.csky.abiv2.bank26",
106 (const char *)"org.gnu.csky.abiv2.bank27",
107 (const char *)"org.gnu.csky.abiv2.bank28",
108 (const char *)"org.gnu.csky.abiv2.bank29",
109 (const char *)"org.gnu.csky.abiv2.bank30",
110 (const char *)"org.gnu.csky.abiv2.bank31"
111 };
112
113 struct csky_supported_tdesc_register
114 {
115 char name[16];
116 int num;
117 };
118
119 static const struct csky_supported_tdesc_register csky_supported_gpr_regs[] = {
120 {"r0", 0},
121 {"r1", 1},
122 {"r2", 2},
123 {"r3", 3},
124 {"r4", 4},
125 {"r5", 5},
126 {"r6", 6},
127 {"r7", 7},
128 {"r8", 8},
129 {"r9", 9},
130 {"r10", 10},
131 {"r11", 11},
132 {"r12", 12},
133 {"r13", 13},
134 {"r14", 14},
135 {"r15", 15},
136 {"r16", 16},
137 {"r17", 17},
138 {"r18", 18},
139 {"r19", 19},
140 {"r20", 20},
141 {"r21", 21},
142 {"r22", 22},
143 {"r23", 23},
144 {"r24", 24},
145 {"r25", 25},
146 {"r26", 26},
147 {"r27", 27},
148 {"r28", 28},
149 {"r28", 28},
150 {"r29", 29},
151 {"r30", 30},
152 {"r31", 31},
153 {"hi", CSKY_HI_REGNUM},
154 {"lo", CSKY_LO_REGNUM},
155 {"pc", CSKY_PC_REGNUM}
156 };
157
158 static const struct csky_supported_tdesc_register csky_supported_fpu_regs[] = {
159 /* fr0~fr15. */
160 {"fr0", CSKY_FR0_REGNUM + 0},
161 {"fr1", CSKY_FR0_REGNUM + 1},
162 {"fr2", CSKY_FR0_REGNUM + 2},
163 {"fr3", CSKY_FR0_REGNUM + 3},
164 {"fr4", CSKY_FR0_REGNUM + 4},
165 {"fr5", CSKY_FR0_REGNUM + 5},
166 {"fr6", CSKY_FR0_REGNUM + 6},
167 {"fr7", CSKY_FR0_REGNUM + 7},
168 {"fr8", CSKY_FR0_REGNUM + 8},
169 {"fr9", CSKY_FR0_REGNUM + 9},
170 {"fr10", CSKY_FR0_REGNUM + 10},
171 {"fr11", CSKY_FR0_REGNUM + 11},
172 {"fr12", CSKY_FR0_REGNUM + 12},
173 {"fr13", CSKY_FR0_REGNUM + 13},
174 {"fr14", CSKY_FR0_REGNUM + 14},
175 {"fr15", CSKY_FR0_REGNUM + 15},
176 /* fr16~fr31. */
177 {"fr16", CSKY_FR16_REGNUM + 0},
178 {"fr17", CSKY_FR16_REGNUM + 1},
179 {"fr18", CSKY_FR16_REGNUM + 2},
180 {"fr19", CSKY_FR16_REGNUM + 3},
181 {"fr20", CSKY_FR16_REGNUM + 4},
182 {"fr21", CSKY_FR16_REGNUM + 5},
183 {"fr22", CSKY_FR16_REGNUM + 6},
184 {"fr23", CSKY_FR16_REGNUM + 7},
185 {"fr24", CSKY_FR16_REGNUM + 8},
186 {"fr25", CSKY_FR16_REGNUM + 9},
187 {"fr26", CSKY_FR16_REGNUM + 10},
188 {"fr27", CSKY_FR16_REGNUM + 11},
189 {"fr28", CSKY_FR16_REGNUM + 12},
190 {"fr29", CSKY_FR16_REGNUM + 13},
191 {"fr30", CSKY_FR16_REGNUM + 14},
192 {"fr31", CSKY_FR16_REGNUM + 15},
193 /* vr0~vr15. */
194 {"vr0", CSKY_VR0_REGNUM + 0},
195 {"vr1", CSKY_VR0_REGNUM + 1},
196 {"vr2", CSKY_VR0_REGNUM + 2},
197 {"vr3", CSKY_VR0_REGNUM + 3},
198 {"vr4", CSKY_VR0_REGNUM + 4},
199 {"vr5", CSKY_VR0_REGNUM + 5},
200 {"vr6", CSKY_VR0_REGNUM + 6},
201 {"vr7", CSKY_VR0_REGNUM + 7},
202 {"vr8", CSKY_VR0_REGNUM + 8},
203 {"vr9", CSKY_VR0_REGNUM + 9},
204 {"vr10", CSKY_VR0_REGNUM + 10},
205 {"vr11", CSKY_VR0_REGNUM + 11},
206 {"vr12", CSKY_VR0_REGNUM + 12},
207 {"vr13", CSKY_VR0_REGNUM + 13},
208 {"vr14", CSKY_VR0_REGNUM + 14},
209 {"vr15", CSKY_VR0_REGNUM + 15},
210 /* fpu control registers. */
211 {"fcr", CSKY_FCR_REGNUM + 0},
212 {"fid", CSKY_FCR_REGNUM + 1},
213 {"fesr", CSKY_FCR_REGNUM + 2},
214 };
215
216 static const struct csky_supported_tdesc_register csky_supported_ar_regs[] = {
217 {"ar0", CSKY_AR0_REGNUM + 0},
218 {"ar1", CSKY_AR0_REGNUM + 1},
219 {"ar2", CSKY_AR0_REGNUM + 2},
220 {"ar3", CSKY_AR0_REGNUM + 3},
221 {"ar4", CSKY_AR0_REGNUM + 4},
222 {"ar5", CSKY_AR0_REGNUM + 5},
223 {"ar6", CSKY_AR0_REGNUM + 6},
224 {"ar7", CSKY_AR0_REGNUM + 7},
225 {"ar8", CSKY_AR0_REGNUM + 8},
226 {"ar9", CSKY_AR0_REGNUM + 9},
227 {"ar10", CSKY_AR0_REGNUM + 10},
228 {"ar11", CSKY_AR0_REGNUM + 11},
229 {"ar12", CSKY_AR0_REGNUM + 12},
230 {"ar13", CSKY_AR0_REGNUM + 13},
231 {"ar14", CSKY_AR0_REGNUM + 14},
232 {"ar15", CSKY_AR0_REGNUM + 15},
233 };
234
235 static const struct csky_supported_tdesc_register csky_supported_bank0_regs[] = {
236 {"cr0", CSKY_CR0_REGNUM + 0},
237 {"cr1", CSKY_CR0_REGNUM + 1},
238 {"cr2", CSKY_CR0_REGNUM + 2},
239 {"cr3", CSKY_CR0_REGNUM + 3},
240 {"cr4", CSKY_CR0_REGNUM + 4},
241 {"cr5", CSKY_CR0_REGNUM + 5},
242 {"cr6", CSKY_CR0_REGNUM + 6},
243 {"cr7", CSKY_CR0_REGNUM + 7},
244 {"cr8", CSKY_CR0_REGNUM + 8},
245 {"cr9", CSKY_CR0_REGNUM + 9},
246 {"cr10", CSKY_CR0_REGNUM + 10},
247 {"cr11", CSKY_CR0_REGNUM + 11},
248 {"cr12", CSKY_CR0_REGNUM + 12},
249 {"cr13", CSKY_CR0_REGNUM + 13},
250 {"cr14", CSKY_CR0_REGNUM + 14},
251 {"cr15", CSKY_CR0_REGNUM + 15},
252 {"cr16", CSKY_CR0_REGNUM + 16},
253 {"cr17", CSKY_CR0_REGNUM + 17},
254 {"cr18", CSKY_CR0_REGNUM + 18},
255 {"cr19", CSKY_CR0_REGNUM + 19},
256 {"cr20", CSKY_CR0_REGNUM + 20},
257 {"cr21", CSKY_CR0_REGNUM + 21},
258 {"cr22", CSKY_CR0_REGNUM + 22},
259 {"cr23", CSKY_CR0_REGNUM + 23},
260 {"cr24", CSKY_CR0_REGNUM + 24},
261 {"cr25", CSKY_CR0_REGNUM + 25},
262 {"cr26", CSKY_CR0_REGNUM + 26},
263 {"cr27", CSKY_CR0_REGNUM + 27},
264 {"cr28", CSKY_CR0_REGNUM + 28},
265 {"cr29", CSKY_CR0_REGNUM + 29},
266 {"cr30", CSKY_CR0_REGNUM + 30},
267 {"cr31", CSKY_CR0_REGNUM + 31}
268 };
269
270 static const struct csky_supported_tdesc_register csky_supported_mmu_regs[] = {
271 {"mcr0", 128},
272 {"mcr2", 129},
273 {"mcr3", 130},
274 {"mcr4", 131},
275 {"mcr6", 132},
276 {"mcr8", 133},
277 {"mcr29", 134},
278 {"mcr30", 135},
279 {"mcr31", 136}
280 };
281
282 static const struct csky_supported_tdesc_register csky_supported_bank15_regs[] = {
283 {"cp15cp1", 253},
284 {"cp15cp5", 254},
285 {"cp15cp7", 255},
286 {"cp15cp9", 256},
287 {"cp15cp10", 257},
288 {"cp15cp11", 258},
289 {"cp15cp12", 259},
290 {"cp15cp13", 260},
291 {"cp15cp14", 261},
292 {"cp15cp15", 262},
293 {"cp15cp16", 263},
294 {"cp15cp17", 264},
295 {"cp15cp18", 265},
296 {"cp15cp19", 266},
297 {"cp15cp20", 267},
298 {"cp15cp21", 268},
299 {"cp15cp22", 269},
300 {"cp15cp23", 270},
301 {"cp15cp24", 271},
302 {"cp15cp25", 272},
303 {"cp15cp26", 273},
304 {"cp15cp27", 274},
305 {"cp15cp28", 275},
306 };
307
308 static const struct csky_supported_tdesc_register csky_supported_alias_regs[] = {
309 /* Alias register names for Bank0. */
310 {"psr", CSKY_CR0_REGNUM + 0},
311 {"vbr", CSKY_CR0_REGNUM + 1},
312 {"epsr", CSKY_CR0_REGNUM + 2},
313 {"fpsr", CSKY_CR0_REGNUM + 3},
314 {"epc", CSKY_CR0_REGNUM + 4},
315 {"fpc", CSKY_CR0_REGNUM + 5},
316 {"ss0", CSKY_CR0_REGNUM + 6},
317 {"ss1", CSKY_CR0_REGNUM + 7},
318 {"ss2", CSKY_CR0_REGNUM + 8},
319 {"ss3", CSKY_CR0_REGNUM + 9},
320 {"ss4", CSKY_CR0_REGNUM + 10},
321 {"gcr", CSKY_CR0_REGNUM + 11},
322 {"gsr", CSKY_CR0_REGNUM + 12},
323 {"cpuid", CSKY_CR0_REGNUM + 13},
324 {"ccr", CSKY_CR0_REGNUM + 18},
325 {"capr", CSKY_CR0_REGNUM + 19},
326 {"pacr", CSKY_CR0_REGNUM + 20},
327 {"prsr", CSKY_CR0_REGNUM + 21},
328 {"chr", CSKY_CR0_REGNUM + 31},
329 /* Alias register names for MMU. */
330 {"mir", 128},
331 {"mel0", 129},
332 {"mel1", 130},
333 {"meh", 131},
334 {"mpr", 132},
335 {"mcir", 133},
336 {"mpgd", 134},
337 {"msa0", 135},
338 {"msa1", 136},
339 /* Alias register names for Bank1. */
340 {"ebr", 190},
341 {"errlc", 195},
342 {"erraddr", 196},
343 {"errsts", 197},
344 {"errinj", 198},
345 {"usp", 203},
346 {"int_sp", 204},
347 {"itcmcr", 211},
348 {"dtcmcr", 212},
349 {"cindex", 215},
350 {"cdata0", 216},
351 {"cdata1", 217},
352 {"cdata2", 218},
353 {"cins", 220},
354 /* Alias register names for Bank3. */
355 {"sepsr", 221},
356 {"t_wssr", 221},
357 {"sevbr", 222},
358 {"t_wrcr", 222},
359 {"seepsr", 223},
360 {"seepc", 225},
361 {"nsssp", 227},
362 {"t_usp", 228},
363 {"dcr", 229},
364 {"t_pcr", 230},
365 };
366
367 /* Functions declaration. */
368
369 static const char *
370 csky_pseudo_register_name (struct gdbarch *gdbarch, int regno);
371
372 /* Get csky supported registers's count for tdesc xml. */
373
374 static int
375 csky_get_supported_tdesc_registers_count()
376 {
377 int count = 0;
378 count += ARRAY_SIZE (csky_supported_gpr_regs);
379 count += ARRAY_SIZE (csky_supported_fpu_regs);
380 count += ARRAY_SIZE (csky_supported_ar_regs);
381 count += ARRAY_SIZE (csky_supported_bank0_regs);
382 count += ARRAY_SIZE (csky_supported_mmu_regs);
383 count += ARRAY_SIZE (csky_supported_bank15_regs);
384 count += ARRAY_SIZE (csky_supported_alias_regs);
385 /* Bank1~Bank14, Bank16~Bank31. */
386 count += 32 * (14 + 16);
387 return count;
388 }
389
390 /* Return a supported register according to index. */
391
392 static const struct csky_supported_tdesc_register *
393 csky_get_supported_register_by_index (int index)
394 {
395 static struct csky_supported_tdesc_register tdesc_reg;
396 int count = 0;
397 int multi, remain;
398 int count_gpr = ARRAY_SIZE (csky_supported_gpr_regs);
399 int count_fpu = ARRAY_SIZE (csky_supported_fpu_regs);
400 int count_ar = ARRAY_SIZE (csky_supported_ar_regs);
401 int count_bank0 = ARRAY_SIZE (csky_supported_bank0_regs);
402 int count_mmu = ARRAY_SIZE (csky_supported_mmu_regs);
403 int count_bank15 = ARRAY_SIZE (csky_supported_bank15_regs);
404 int count_alias = ARRAY_SIZE (csky_supported_alias_regs);
405
406 count = count_gpr;
407 if (index < count)
408 return &csky_supported_gpr_regs[index];
409 if (index < (count + count_fpu))
410 return &csky_supported_fpu_regs[index - count];
411 count += count_fpu;
412 if (index < (count + count_ar))
413 return &csky_supported_ar_regs[index - count];
414 count += count_ar;
415 if (index < (count + count_bank0))
416 return &csky_supported_bank0_regs[index - count];
417 count += count_bank0;
418 if (index < (count + count_mmu))
419 return &csky_supported_mmu_regs[index - count];
420 count += count_mmu;
421 if (index < (count + count_bank15))
422 return &csky_supported_bank15_regs[index - count];
423 count += count_bank15;
424 if (index < (count + count_alias))
425 return &csky_supported_alias_regs[index - count];
426 count += count_alias;
427 index -= count;
428 multi = index / 32;
429 remain = index % 32;
430 switch (multi)
431 {
432 case 0: /* Bank1. */
433 {
434 sprintf (tdesc_reg.name, "cp1cr%d", remain);
435 tdesc_reg.num = 189 + remain;
436 }
437 break;
438 case 1: /* Bank2. */
439 {
440 sprintf (tdesc_reg.name, "cp2cr%d", remain);
441 tdesc_reg.num = 276 + remain;
442 }
443 break;
444 case 2: /* Bank3. */
445 {
446 sprintf (tdesc_reg.name, "cp3cr%d", remain);
447 tdesc_reg.num = 221 + remain;
448 }
449 break;
450 case 3: /* Bank4. */
451 case 4: /* Bank5. */
452 case 5: /* Bank6. */
453 case 6: /* Bank7. */
454 case 7: /* Bank8. */
455 case 8: /* Bank9. */
456 case 9: /* Bank10. */
457 case 10: /* Bank11. */
458 case 11: /* Bank12. */
459 case 12: /* Bank13. */
460 case 13: /* Bank14. */
461 {
462 /* Regitsers in Bank4~14 have continuous regno with start 308. */
463 sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 1), remain);
464 tdesc_reg.num = 308 + ((multi - 3) * 32) + remain;
465 }
466 break;
467 case 14: /* Bank16. */
468 case 15: /* Bank17. */
469 case 16: /* Bank18. */
470 case 17: /* Bank19. */
471 case 18: /* Bank20. */
472 case 19: /* Bank21. */
473 case 20: /* Bank22. */
474 case 21: /* Bank23. */
475 case 22: /* Bank24. */
476 case 23: /* Bank25. */
477 case 24: /* Bank26. */
478 case 25: /* Bank27. */
479 case 26: /* Bank28. */
480 case 27: /* Bank29. */
481 case 28: /* Bank30. */
482 case 29: /* Bank31. */
483 {
484 /* Regitsers in Bank16~31 have continuous regno with start 660. */
485 sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 2), remain);
486 tdesc_reg.num = 660 + ((multi - 14) * 32) + remain;
487 }
488 break;
489 default:
490 return NULL;
491 }
492 return &tdesc_reg;
493 }
494
495 /* Convenience function to print debug messages in prologue analysis. */
496
497 static void
498 print_savedreg_msg (int regno, int offsets[], bool print_continuing)
499 {
500 gdb_printf (gdb_stdlog, "csky: r%d saved at offset 0x%x\n",
501 regno, offsets[regno]);
502 if (print_continuing)
503 gdb_printf (gdb_stdlog, "csky: continuing\n");
504 }
505
506 /* Check whether the instruction at ADDR is 16-bit or not. */
507
508 static int
509 csky_pc_is_csky16 (struct gdbarch *gdbarch, CORE_ADDR addr)
510 {
511 gdb_byte target_mem[2];
512 int status;
513 unsigned int insn;
514 int ret = 1;
515 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
516
517 status = target_read_memory (addr, target_mem, 2);
518 /* Assume a 16-bit instruction if we can't read memory. */
519 if (status)
520 return 1;
521
522 /* Get instruction from memory. */
523 insn = extract_unsigned_integer (target_mem, 2, byte_order);
524 if ((insn & CSKY_32_INSN_MASK) == CSKY_32_INSN_MASK)
525 ret = 0;
526 else if (insn == CSKY_BKPT_INSN)
527 {
528 /* Check for 32-bit bkpt instruction which is all 0. */
529 status = target_read_memory (addr + 2, target_mem, 2);
530 if (status)
531 return 1;
532
533 insn = extract_unsigned_integer (target_mem, 2, byte_order);
534 if (insn == CSKY_BKPT_INSN)
535 ret = 0;
536 }
537 return ret;
538 }
539
540 /* Get one instruction at ADDR and store it in INSN. Return 2 for
541 a 16-bit instruction or 4 for a 32-bit instruction. */
542
543 static int
544 csky_get_insn (struct gdbarch *gdbarch, CORE_ADDR addr, unsigned int *insn)
545 {
546 gdb_byte target_mem[2];
547 unsigned int insn_type;
548 int status;
549 int insn_len = 2;
550 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
551
552 status = target_read_memory (addr, target_mem, 2);
553 if (status)
554 memory_error (TARGET_XFER_E_IO, addr);
555
556 insn_type = extract_unsigned_integer (target_mem, 2, byte_order);
557 if (CSKY_32_INSN_MASK == (insn_type & CSKY_32_INSN_MASK))
558 {
559 status = target_read_memory (addr + 2, target_mem, 2);
560 if (status)
561 memory_error (TARGET_XFER_E_IO, addr);
562 insn_type = ((insn_type << 16)
563 | extract_unsigned_integer (target_mem, 2, byte_order));
564 insn_len = 4;
565 }
566 *insn = insn_type;
567 return insn_len;
568 }
569
570 /* Implement the read_pc gdbarch method. */
571
572 static CORE_ADDR
573 csky_read_pc (readable_regcache *regcache)
574 {
575 ULONGEST pc;
576 regcache->cooked_read (CSKY_PC_REGNUM, &pc);
577 return pc;
578 }
579
580 /* Implement the write_pc gdbarch method. */
581
582 static void
583 csky_write_pc (regcache *regcache, CORE_ADDR val)
584 {
585 regcache_cooked_write_unsigned (regcache, CSKY_PC_REGNUM, val);
586 }
587
588 /* C-Sky ABI register names. */
589
590 static const char * const csky_register_names[] =
591 {
592 /* General registers 0 - 31. */
593 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
594 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
595 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
596 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
597
598 /* DSP hilo registers 36 and 37. */
599 "", "", "", "", "hi", "lo", "", "",
600
601 /* FPU/VPU general registers 40 - 71. */
602 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
603 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
604 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
605 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
606
607 /* Program counter 72. */
608 "pc",
609
610 /* Optional registers (ar) 73 - 88. */
611 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7",
612 "ar8", "ar9", "ar10", "ar11", "ar12", "ar13", "ar14", "ar15",
613
614 /* Control registers (cr) 89 - 119. */
615 "psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
616 "ss2", "ss3", "ss4", "gcr", "gsr", "cr13", "cr14", "cr15",
617 "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", "cr22", "cr23",
618 "cr24", "cr25", "cr26", "cr27", "cr28", "cr29", "cr30", "cr31",
619
620 /* FPU/VPU control registers 121 ~ 123. */
621 /* User sp 127. */
622 "fid", "fcr", "fesr", "", "", "", "usp",
623
624 /* MMU control registers: 128 - 136. */
625 "mcr0", "mcr2", "mcr3", "mcr4", "mcr6", "mcr8", "mcr29", "mcr30",
626 "mcr31", "", "", "",
627
628 /* Profiling control registers 140 - 143. */
629 /* Profiling software general registers 144 - 157. */
630 "profcr0", "profcr1", "profcr2", "profcr3", "profsgr0", "profsgr1",
631 "profsgr2", "profsgr3", "profsgr4", "profsgr5", "profsgr6", "profsgr7",
632 "profsgr8", "profsgr9", "profsgr10","profsgr11","profsgr12", "profsgr13",
633 "", "",
634
635 /* Profiling architecture general registers 160 - 174. */
636 "profagr0", "profagr1", "profagr2", "profagr3", "profagr4", "profagr5",
637 "profagr6", "profagr7", "profagr8", "profagr9", "profagr10","profagr11",
638 "profagr12","profagr13","profagr14", "",
639
640 /* Profiling extension general registers 176 - 188. */
641 "profxgr0", "profxgr1", "profxgr2", "profxgr3", "profxgr4", "profxgr5",
642 "profxgr6", "profxgr7", "profxgr8", "profxgr9", "profxgr10","profxgr11",
643 "profxgr12",
644
645 /* Control registers in bank1. */
646 "", "", "", "", "", "", "", "",
647 "", "", "", "", "", "", "", "",
648 "cp1cr16", "cp1cr17", "cp1cr18", "cp1cr19", "cp1cr20", "", "", "",
649 "", "", "", "", "", "", "", "",
650
651 /* Control registers in bank3 (ICE). */
652 "sepsr", "sevbr", "seepsr", "", "seepc", "", "nsssp", "seusp",
653 "sedcr", "", "", "", "", "", "", "",
654 "", "", "", "", "", "", "", "",
655 "", "", "", "", "", "", "", ""
656 };
657
658 /* Implement the register_name gdbarch method. */
659
660 static const char *
661 csky_register_name (struct gdbarch *gdbarch, int reg_nr)
662 {
663 int num_regs = gdbarch_num_regs (gdbarch);
664 int num_pseudo_regs = gdbarch_num_pseudo_regs (gdbarch);
665
666 if ((reg_nr >= num_regs) && (reg_nr < (num_regs + num_pseudo_regs)))
667 return csky_pseudo_register_name (gdbarch, reg_nr);
668
669 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
670 return tdesc_register_name (gdbarch, reg_nr);
671
672 if (reg_nr < 0)
673 return NULL;
674
675 if (reg_nr >= gdbarch_num_regs (gdbarch))
676 return NULL;
677
678 return csky_register_names[reg_nr];
679 }
680
681 /* Construct vector type for vrx registers. */
682
683 static struct type *
684 csky_vector_type (struct gdbarch *gdbarch)
685 {
686 const struct builtin_type *bt = builtin_type (gdbarch);
687
688 struct type *t;
689
690 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vec128i",
691 TYPE_CODE_UNION);
692
693 append_composite_type_field (t, "u32",
694 init_vector_type (bt->builtin_int32, 4));
695 append_composite_type_field (t, "u16",
696 init_vector_type (bt->builtin_int16, 8));
697 append_composite_type_field (t, "u8",
698 init_vector_type (bt->builtin_int8, 16));
699
700 t->set_is_vector (true);
701 t->set_name ("builtin_type_vec128i");
702
703 return t;
704 }
705
706 /* Return the GDB type object for the "standard" data type
707 of data in register N. */
708
709 static struct type *
710 csky_register_type (struct gdbarch *gdbarch, int reg_nr)
711 {
712 /* If type has been described in tdesc-xml, use it. */
713 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
714 {
715 struct type *tdesc_t = tdesc_register_type (gdbarch, reg_nr);
716 if (tdesc_t)
717 return tdesc_t;
718 }
719
720 /* PC, EPC, FPC is a text pointer. */
721 if ((reg_nr == CSKY_PC_REGNUM) || (reg_nr == CSKY_EPC_REGNUM)
722 || (reg_nr == CSKY_FPC_REGNUM))
723 return builtin_type (gdbarch)->builtin_func_ptr;
724
725 /* VBR is a data pointer. */
726 if (reg_nr == CSKY_VBR_REGNUM)
727 return builtin_type (gdbarch)->builtin_data_ptr;
728
729 /* Float register has 64 bits, and only in ck810. */
730 if ((reg_nr >=CSKY_FR0_REGNUM) && (reg_nr <= CSKY_FR0_REGNUM + 15))
731 return arch_float_type (gdbarch, 64, "builtin_type_csky_ext",
732 floatformats_ieee_double);
733
734 /* Vector register has 128 bits, and only in ck810. */
735 if ((reg_nr >= CSKY_VR0_REGNUM) && (reg_nr <= CSKY_VR0_REGNUM + 15))
736 return csky_vector_type (gdbarch);
737
738 /* Profiling general register has 48 bits, we use 64bit. */
739 if ((reg_nr >= CSKY_PROFGR_REGNUM) && (reg_nr <= CSKY_PROFGR_REGNUM + 44))
740 return builtin_type (gdbarch)->builtin_uint64;
741
742 if (reg_nr == CSKY_SP_REGNUM)
743 return builtin_type (gdbarch)->builtin_data_ptr;
744
745 /* Others are 32 bits. */
746 return builtin_type (gdbarch)->builtin_int32;
747 }
748
749 /* Data structure to marshall items in a dummy stack frame when
750 calling a function in the inferior. */
751
752 struct csky_stack_item
753 {
754 csky_stack_item (int len_, const gdb_byte *data_)
755 : len (len_), data (data_)
756 {}
757
758 int len;
759 const gdb_byte *data;
760 };
761
762 /* Implement the push_dummy_call gdbarch method. */
763
764 static CORE_ADDR
765 csky_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
766 struct regcache *regcache, CORE_ADDR bp_addr,
767 int nargs, struct value **args, CORE_ADDR sp,
768 function_call_return_method return_method,
769 CORE_ADDR struct_addr)
770 {
771 int argnum;
772 int argreg = CSKY_ABI_A0_REGNUM;
773 int last_arg_regnum = CSKY_ABI_LAST_ARG_REGNUM;
774 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
775 std::vector<csky_stack_item> stack_items;
776
777 /* Set the return address. For CSKY, the return breakpoint is
778 always at BP_ADDR. */
779 regcache_cooked_write_unsigned (regcache, CSKY_LR_REGNUM, bp_addr);
780
781 /* The struct_return pointer occupies the first parameter
782 passing register. */
783 if (return_method == return_method_struct)
784 {
785 if (csky_debug)
786 {
787 gdb_printf (gdb_stdlog,
788 "csky: struct return in %s = %s\n",
789 gdbarch_register_name (gdbarch, argreg),
790 paddress (gdbarch, struct_addr));
791 }
792 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
793 argreg++;
794 }
795
796 /* Put parameters into argument registers in REGCACHE.
797 In ABI argument registers are r0 through r3. */
798 for (argnum = 0; argnum < nargs; argnum++)
799 {
800 int len;
801 struct type *arg_type;
802 const gdb_byte *val;
803
804 arg_type = check_typedef (value_type (args[argnum]));
805 len = arg_type->length ();
806 val = value_contents (args[argnum]).data ();
807
808 /* Copy the argument to argument registers or the dummy stack.
809 Large arguments are split between registers and stack.
810
811 If len < 4, there is no need to worry about endianness since
812 the arguments will always be stored in the low address. */
813 if (len < 4)
814 {
815 CORE_ADDR regval
816 = extract_unsigned_integer (val, len, byte_order);
817 regcache_cooked_write_unsigned (regcache, argreg, regval);
818 argreg++;
819 }
820 else
821 {
822 while (len > 0)
823 {
824 int partial_len = len < 4 ? len : 4;
825 if (argreg <= last_arg_regnum)
826 {
827 /* The argument is passed in an argument register. */
828 CORE_ADDR regval
829 = extract_unsigned_integer (val, partial_len,
830 byte_order);
831 if (byte_order == BFD_ENDIAN_BIG)
832 regval <<= (4 - partial_len) * 8;
833
834 /* Put regval into register in REGCACHE. */
835 regcache_cooked_write_unsigned (regcache, argreg,
836 regval);
837 argreg++;
838 }
839 else
840 {
841 /* The argument should be pushed onto the dummy stack. */
842 stack_items.emplace_back (4, val);
843 }
844 len -= partial_len;
845 val += partial_len;
846 }
847 }
848 }
849
850 /* Transfer the dummy stack frame to the target. */
851 std::vector<csky_stack_item>::reverse_iterator iter;
852 for (iter = stack_items.rbegin (); iter != stack_items.rend (); ++iter)
853 {
854 sp -= iter->len;
855 write_memory (sp, iter->data, iter->len);
856 }
857
858 /* Finally, update the SP register. */
859 regcache_cooked_write_unsigned (regcache, CSKY_SP_REGNUM, sp);
860 return sp;
861 }
862
863 /* Implement the return_value gdbarch method. */
864
865 static enum return_value_convention
866 csky_return_value (struct gdbarch *gdbarch, struct value *function,
867 struct type *valtype, struct regcache *regcache,
868 gdb_byte *readbuf, const gdb_byte *writebuf)
869 {
870 CORE_ADDR regval;
871 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
872 int len = valtype->length ();
873 unsigned int ret_regnum = CSKY_RET_REGNUM;
874
875 /* Csky abi specifies that return values larger than 8 bytes
876 are put on the stack. */
877 if (len > 8)
878 return RETURN_VALUE_STRUCT_CONVENTION;
879 else
880 {
881 if (readbuf != NULL)
882 {
883 ULONGEST tmp;
884 /* By using store_unsigned_integer we avoid having to do
885 anything special for small big-endian values. */
886 regcache->cooked_read (ret_regnum, &tmp);
887 store_unsigned_integer (readbuf, (len > 4 ? 4 : len),
888 byte_order, tmp);
889 if (len > 4)
890 {
891 regcache->cooked_read (ret_regnum + 1, &tmp);
892 store_unsigned_integer (readbuf + 4, 4, byte_order, tmp);
893 }
894 }
895 if (writebuf != NULL)
896 {
897 regval = extract_unsigned_integer (writebuf, len > 4 ? 4 : len,
898 byte_order);
899 regcache_cooked_write_unsigned (regcache, ret_regnum, regval);
900 if (len > 4)
901 {
902 regval = extract_unsigned_integer ((gdb_byte *) writebuf + 4,
903 4, byte_order);
904 regcache_cooked_write_unsigned (regcache, ret_regnum + 1,
905 regval);
906 }
907
908 }
909 return RETURN_VALUE_REGISTER_CONVENTION;
910 }
911 }
912
913 /* Implement the frame_align gdbarch method.
914
915 Adjust the address downward (direction of stack growth) so that it
916 is correctly aligned for a new stack frame. */
917
918 static CORE_ADDR
919 csky_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
920 {
921 return align_down (addr, 4);
922 }
923
924 /* Unwind cache used for gdbarch fallback unwinder. */
925
926 struct csky_unwind_cache
927 {
928 /* The stack pointer at the time this frame was created; i.e. the
929 caller's stack pointer when this function was called. It is used
930 to identify this frame. */
931 CORE_ADDR prev_sp;
932
933 /* The frame base for this frame is just prev_sp - frame size.
934 FRAMESIZE is the distance from the frame pointer to the
935 initial stack pointer. */
936 int framesize;
937
938 /* The register used to hold the frame pointer for this frame. */
939 int framereg;
940
941 /* Saved register offsets. */
942 trad_frame_saved_reg *saved_regs;
943 };
944
945 /* Do prologue analysis, returning the PC of the first instruction
946 after the function prologue. */
947
948 static CORE_ADDR
949 csky_analyze_prologue (struct gdbarch *gdbarch,
950 CORE_ADDR start_pc,
951 CORE_ADDR limit_pc,
952 CORE_ADDR end_pc,
953 struct frame_info *this_frame,
954 struct csky_unwind_cache *this_cache,
955 lr_type_t lr_type)
956 {
957 CORE_ADDR addr;
958 unsigned int insn, rn;
959 int framesize = 0;
960 int stacksize = 0;
961 int register_offsets[CSKY_NUM_GREGS_SAVED_GREGS];
962 int insn_len;
963 /* For adjusting fp. */
964 int is_fp_saved = 0;
965 int adjust_fp = 0;
966
967 /* REGISTER_OFFSETS will contain offsets from the top of the frame
968 (NOT the frame pointer) for the various saved registers, or -1
969 if the register is not saved. */
970 for (rn = 0; rn < CSKY_NUM_GREGS_SAVED_GREGS; rn++)
971 register_offsets[rn] = -1;
972
973 /* Analyze the prologue. Things we determine from analyzing the
974 prologue include the size of the frame and which registers are
975 saved (and where). */
976 if (csky_debug)
977 {
978 gdb_printf (gdb_stdlog,
979 "csky: Scanning prologue: start_pc = 0x%x,"
980 "limit_pc = 0x%x\n", (unsigned int) start_pc,
981 (unsigned int) limit_pc);
982 }
983
984 /* Default to 16 bit instruction. */
985 insn_len = 2;
986 stacksize = 0;
987 for (addr = start_pc; addr < limit_pc; addr += insn_len)
988 {
989 /* Get next insn. */
990 insn_len = csky_get_insn (gdbarch, addr, &insn);
991
992 /* Check if 32 bit. */
993 if (insn_len == 4)
994 {
995 /* subi32 sp,sp oimm12. */
996 if (CSKY_32_IS_SUBI0 (insn))
997 {
998 /* Got oimm12. */
999 int offset = CSKY_32_SUBI_IMM (insn);
1000 if (csky_debug)
1001 {
1002 gdb_printf (gdb_stdlog,
1003 "csky: got subi sp,%d; continuing\n",
1004 offset);
1005 }
1006 stacksize += offset;
1007 continue;
1008 }
1009 /* stm32 ry-rz,(sp). */
1010 else if (CSKY_32_IS_STMx0 (insn))
1011 {
1012 /* Spill register(s). */
1013 int start_register;
1014 int reg_count;
1015 int offset;
1016
1017 /* BIG WARNING! The CKCore ABI does not restrict functions
1018 to taking only one stack allocation. Therefore, when
1019 we save a register, we record the offset of where it was
1020 saved relative to the current stacksize. This will
1021 then give an offset from the SP upon entry to our
1022 function. Remember, stacksize is NOT constant until
1023 we're done scanning the prologue. */
1024 start_register = CSKY_32_STM_VAL_REGNUM (insn);
1025 reg_count = CSKY_32_STM_SIZE (insn);
1026 if (csky_debug)
1027 {
1028 gdb_printf (gdb_stdlog,
1029 "csky: got stm r%d-r%d,(sp)\n",
1030 start_register,
1031 start_register + reg_count);
1032 }
1033
1034 for (rn = start_register, offset = 0;
1035 rn <= start_register + reg_count;
1036 rn++, offset += 4)
1037 {
1038 register_offsets[rn] = stacksize - offset;
1039 if (csky_debug)
1040 {
1041 gdb_printf (gdb_stdlog,
1042 "csky: r%d saved at 0x%x"
1043 " (offset %d)\n",
1044 rn, register_offsets[rn],
1045 offset);
1046 }
1047 }
1048 if (csky_debug)
1049 gdb_printf (gdb_stdlog, "csky: continuing\n");
1050 continue;
1051 }
1052 /* stw ry,(sp,disp). */
1053 else if (CSKY_32_IS_STWx0 (insn))
1054 {
1055 /* Spill register: see note for IS_STM above. */
1056 int disp;
1057
1058 rn = CSKY_32_ST_VAL_REGNUM (insn);
1059 disp = CSKY_32_ST_OFFSET (insn);
1060 register_offsets[rn] = stacksize - disp;
1061 if (csky_debug)
1062 print_savedreg_msg (rn, register_offsets, true);
1063 continue;
1064 }
1065 else if (CSKY_32_IS_MOV_FP_SP (insn))
1066 {
1067 /* SP is saved to FP reg, means code afer prologue may
1068 modify SP. */
1069 is_fp_saved = 1;
1070 adjust_fp = stacksize;
1071 continue;
1072 }
1073 else if (CSKY_32_IS_MFCR_EPSR (insn))
1074 {
1075 unsigned int insn2;
1076 addr += 4;
1077 int mfcr_regnum = insn & 0x1f;
1078 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1079 if (insn_len == 2)
1080 {
1081 int stw_regnum = (insn2 >> 5) & 0x7;
1082 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1083 {
1084 int offset;
1085
1086 /* CSKY_EPSR_REGNUM. */
1087 rn = CSKY_NUM_GREGS;
1088 offset = CSKY_16_STWx0_OFFSET (insn2);
1089 register_offsets[rn] = stacksize - offset;
1090 if (csky_debug)
1091 print_savedreg_msg (rn, register_offsets, true);
1092 continue;
1093 }
1094 break;
1095 }
1096 else
1097 {
1098 /* INSN_LEN == 4. */
1099 int stw_regnum = (insn2 >> 21) & 0x1f;
1100 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1101 {
1102 int offset;
1103
1104 /* CSKY_EPSR_REGNUM. */
1105 rn = CSKY_NUM_GREGS;
1106 offset = CSKY_32_ST_OFFSET (insn2);
1107 register_offsets[rn] = framesize - offset;
1108 if (csky_debug)
1109 print_savedreg_msg (rn, register_offsets, true);
1110 continue;
1111 }
1112 break;
1113 }
1114 }
1115 else if (CSKY_32_IS_MFCR_FPSR (insn))
1116 {
1117 unsigned int insn2;
1118 addr += 4;
1119 int mfcr_regnum = insn & 0x1f;
1120 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1121 if (insn_len == 2)
1122 {
1123 int stw_regnum = (insn2 >> 5) & 0x7;
1124 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum
1125 == stw_regnum))
1126 {
1127 int offset;
1128
1129 /* CSKY_FPSR_REGNUM. */
1130 rn = CSKY_NUM_GREGS + 1;
1131 offset = CSKY_16_STWx0_OFFSET (insn2);
1132 register_offsets[rn] = stacksize - offset;
1133 if (csky_debug)
1134 print_savedreg_msg (rn, register_offsets, true);
1135 continue;
1136 }
1137 break;
1138 }
1139 else
1140 {
1141 /* INSN_LEN == 4. */
1142 int stw_regnum = (insn2 >> 21) & 0x1f;
1143 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1144 {
1145 int offset;
1146
1147 /* CSKY_FPSR_REGNUM. */
1148 rn = CSKY_NUM_GREGS + 1;
1149 offset = CSKY_32_ST_OFFSET (insn2);
1150 register_offsets[rn] = framesize - offset;
1151 if (csky_debug)
1152 print_savedreg_msg (rn, register_offsets, true);
1153 continue;
1154 }
1155 break;
1156 }
1157 }
1158 else if (CSKY_32_IS_MFCR_EPC (insn))
1159 {
1160 unsigned int insn2;
1161 addr += 4;
1162 int mfcr_regnum = insn & 0x1f;
1163 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1164 if (insn_len == 2)
1165 {
1166 int stw_regnum = (insn2 >> 5) & 0x7;
1167 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1168 {
1169 int offset;
1170
1171 /* CSKY_EPC_REGNUM. */
1172 rn = CSKY_NUM_GREGS + 2;
1173 offset = CSKY_16_STWx0_OFFSET (insn2);
1174 register_offsets[rn] = stacksize - offset;
1175 if (csky_debug)
1176 print_savedreg_msg (rn, register_offsets, true);
1177 continue;
1178 }
1179 break;
1180 }
1181 else
1182 {
1183 /* INSN_LEN == 4. */
1184 int stw_regnum = (insn2 >> 21) & 0x1f;
1185 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1186 {
1187 int offset;
1188
1189 /* CSKY_EPC_REGNUM. */
1190 rn = CSKY_NUM_GREGS + 2;
1191 offset = CSKY_32_ST_OFFSET (insn2);
1192 register_offsets[rn] = framesize - offset;
1193 if (csky_debug)
1194 print_savedreg_msg (rn, register_offsets, true);
1195 continue;
1196 }
1197 break;
1198 }
1199 }
1200 else if (CSKY_32_IS_MFCR_FPC (insn))
1201 {
1202 unsigned int insn2;
1203 addr += 4;
1204 int mfcr_regnum = insn & 0x1f;
1205 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1206 if (insn_len == 2)
1207 {
1208 int stw_regnum = (insn2 >> 5) & 0x7;
1209 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1210 {
1211 int offset;
1212
1213 /* CSKY_FPC_REGNUM. */
1214 rn = CSKY_NUM_GREGS + 3;
1215 offset = CSKY_16_STWx0_OFFSET (insn2);
1216 register_offsets[rn] = stacksize - offset;
1217 if (csky_debug)
1218 print_savedreg_msg (rn, register_offsets, true);
1219 continue;
1220 }
1221 break;
1222 }
1223 else
1224 {
1225 /* INSN_LEN == 4. */
1226 int stw_regnum = (insn2 >> 21) & 0x1f;
1227 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1228 {
1229 int offset;
1230
1231 /* CSKY_FPC_REGNUM. */
1232 rn = CSKY_NUM_GREGS + 3;
1233 offset = CSKY_32_ST_OFFSET (insn2);
1234 register_offsets[rn] = framesize - offset;
1235 if (csky_debug)
1236 print_savedreg_msg (rn, register_offsets, true);
1237 continue;
1238 }
1239 break;
1240 }
1241 }
1242 else if (CSKY_32_IS_PUSH (insn))
1243 {
1244 /* Push for 32_bit. */
1245 if (CSKY_32_IS_PUSH_R29 (insn))
1246 {
1247 stacksize += 4;
1248 register_offsets[29] = stacksize;
1249 if (csky_debug)
1250 print_savedreg_msg (29, register_offsets, false);
1251 }
1252 if (CSKY_32_PUSH_LIST2 (insn))
1253 {
1254 int num = CSKY_32_PUSH_LIST2 (insn);
1255 int tmp = 0;
1256 stacksize += num * 4;
1257 if (csky_debug)
1258 {
1259 gdb_printf (gdb_stdlog,
1260 "csky: push regs_array: r16-r%d\n",
1261 16 + num - 1);
1262 }
1263 for (rn = 16; rn <= 16 + num - 1; rn++)
1264 {
1265 register_offsets[rn] = stacksize - tmp;
1266 if (csky_debug)
1267 {
1268 gdb_printf (gdb_stdlog,
1269 "csky: r%d saved at 0x%x"
1270 " (offset %d)\n", rn,
1271 register_offsets[rn], tmp);
1272 }
1273 tmp += 4;
1274 }
1275 }
1276 if (CSKY_32_IS_PUSH_R15 (insn))
1277 {
1278 stacksize += 4;
1279 register_offsets[15] = stacksize;
1280 if (csky_debug)
1281 print_savedreg_msg (15, register_offsets, false);
1282 }
1283 if (CSKY_32_PUSH_LIST1 (insn))
1284 {
1285 int num = CSKY_32_PUSH_LIST1 (insn);
1286 int tmp = 0;
1287 stacksize += num * 4;
1288 if (csky_debug)
1289 {
1290 gdb_printf (gdb_stdlog,
1291 "csky: push regs_array: r4-r%d\n",
1292 4 + num - 1);
1293 }
1294 for (rn = 4; rn <= 4 + num - 1; rn++)
1295 {
1296 register_offsets[rn] = stacksize - tmp;
1297 if (csky_debug)
1298 {
1299 gdb_printf (gdb_stdlog,
1300 "csky: r%d saved at 0x%x"
1301 " (offset %d)\n", rn,
1302 register_offsets[rn], tmp);
1303 }
1304 tmp += 4;
1305 }
1306 }
1307
1308 framesize = stacksize;
1309 if (csky_debug)
1310 gdb_printf (gdb_stdlog, "csky: continuing\n");
1311 continue;
1312 }
1313 else if (CSKY_32_IS_LRW4 (insn) || CSKY_32_IS_MOVI4 (insn)
1314 || CSKY_32_IS_MOVIH4 (insn) || CSKY_32_IS_BMASKI4 (insn))
1315 {
1316 int adjust = 0;
1317 int offset = 0;
1318 unsigned int insn2;
1319
1320 if (csky_debug)
1321 {
1322 gdb_printf (gdb_stdlog,
1323 "csky: looking at large frame\n");
1324 }
1325 if (CSKY_32_IS_LRW4 (insn))
1326 {
1327 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1328 int literal_addr = (addr + ((insn & 0xffff) << 2))
1329 & 0xfffffffc;
1330 adjust = read_memory_unsigned_integer (literal_addr, 4,
1331 byte_order);
1332 }
1333 else if (CSKY_32_IS_MOVI4 (insn))
1334 adjust = (insn & 0xffff);
1335 else if (CSKY_32_IS_MOVIH4 (insn))
1336 adjust = (insn & 0xffff) << 16;
1337 else
1338 {
1339 /* CSKY_32_IS_BMASKI4 (insn). */
1340 adjust = (1 << (((insn & 0x3e00000) >> 21) + 1)) - 1;
1341 }
1342
1343 if (csky_debug)
1344 {
1345 gdb_printf (gdb_stdlog,
1346 "csky: base stacksize=0x%x\n", adjust);
1347
1348 /* May have zero or more insns which modify r4. */
1349 gdb_printf (gdb_stdlog,
1350 "csky: looking for r4 adjusters...\n");
1351 }
1352
1353 offset = 4;
1354 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1355 while (CSKY_IS_R4_ADJUSTER (insn2))
1356 {
1357 if (CSKY_32_IS_ADDI4 (insn2))
1358 {
1359 int imm = (insn2 & 0xfff) + 1;
1360 adjust += imm;
1361 if (csky_debug)
1362 {
1363 gdb_printf (gdb_stdlog,
1364 "csky: addi r4,%d\n", imm);
1365 }
1366 }
1367 else if (CSKY_32_IS_SUBI4 (insn2))
1368 {
1369 int imm = (insn2 & 0xfff) + 1;
1370 adjust -= imm;
1371 if (csky_debug)
1372 {
1373 gdb_printf (gdb_stdlog,
1374 "csky: subi r4,%d\n", imm);
1375 }
1376 }
1377 else if (CSKY_32_IS_NOR4 (insn2))
1378 {
1379 adjust = ~adjust;
1380 if (csky_debug)
1381 {
1382 gdb_printf (gdb_stdlog,
1383 "csky: nor r4,r4,r4\n");
1384 }
1385 }
1386 else if (CSKY_32_IS_ROTLI4 (insn2))
1387 {
1388 int imm = ((insn2 >> 21) & 0x1f);
1389 int temp = adjust >> (32 - imm);
1390 adjust <<= imm;
1391 adjust |= temp;
1392 if (csky_debug)
1393 {
1394 gdb_printf (gdb_stdlog,
1395 "csky: rotli r4,r4,%d\n", imm);
1396 }
1397 }
1398 else if (CSKY_32_IS_LISI4 (insn2))
1399 {
1400 int imm = ((insn2 >> 21) & 0x1f);
1401 adjust <<= imm;
1402 if (csky_debug)
1403 {
1404 gdb_printf (gdb_stdlog,
1405 "csky: lsli r4,r4,%d\n", imm);
1406 }
1407 }
1408 else if (CSKY_32_IS_BSETI4 (insn2))
1409 {
1410 int imm = ((insn2 >> 21) & 0x1f);
1411 adjust |= (1 << imm);
1412 if (csky_debug)
1413 {
1414 gdb_printf (gdb_stdlog,
1415 "csky: bseti r4,r4 %d\n", imm);
1416 }
1417 }
1418 else if (CSKY_32_IS_BCLRI4 (insn2))
1419 {
1420 int imm = ((insn2 >> 21) & 0x1f);
1421 adjust &= ~(1 << imm);
1422 if (csky_debug)
1423 {
1424 gdb_printf (gdb_stdlog,
1425 "csky: bclri r4,r4 %d\n", imm);
1426 }
1427 }
1428 else if (CSKY_32_IS_IXH4 (insn2))
1429 {
1430 adjust *= 3;
1431 if (csky_debug)
1432 {
1433 gdb_printf (gdb_stdlog,
1434 "csky: ixh r4,r4,r4\n");
1435 }
1436 }
1437 else if (CSKY_32_IS_IXW4 (insn2))
1438 {
1439 adjust *= 5;
1440 if (csky_debug)
1441 {
1442 gdb_printf (gdb_stdlog,
1443 "csky: ixw r4,r4,r4\n");
1444 }
1445 }
1446 else if (CSKY_16_IS_ADDI4 (insn2))
1447 {
1448 int imm = (insn2 & 0xff) + 1;
1449 adjust += imm;
1450 if (csky_debug)
1451 {
1452 gdb_printf (gdb_stdlog,
1453 "csky: addi r4,%d\n", imm);
1454 }
1455 }
1456 else if (CSKY_16_IS_SUBI4 (insn2))
1457 {
1458 int imm = (insn2 & 0xff) + 1;
1459 adjust -= imm;
1460 if (csky_debug)
1461 {
1462 gdb_printf (gdb_stdlog,
1463 "csky: subi r4,%d\n", imm);
1464 }
1465 }
1466 else if (CSKY_16_IS_NOR4 (insn2))
1467 {
1468 adjust = ~adjust;
1469 if (csky_debug)
1470 {
1471 gdb_printf (gdb_stdlog,
1472 "csky: nor r4,r4\n");
1473 }
1474 }
1475 else if (CSKY_16_IS_BSETI4 (insn2))
1476 {
1477 int imm = (insn2 & 0x1f);
1478 adjust |= (1 << imm);
1479 if (csky_debug)
1480 {
1481 gdb_printf (gdb_stdlog,
1482 "csky: bseti r4, %d\n", imm);
1483 }
1484 }
1485 else if (CSKY_16_IS_BCLRI4 (insn2))
1486 {
1487 int imm = (insn2 & 0x1f);
1488 adjust &= ~(1 << imm);
1489 if (csky_debug)
1490 {
1491 gdb_printf (gdb_stdlog,
1492 "csky: bclri r4, %d\n", imm);
1493 }
1494 }
1495 else if (CSKY_16_IS_LSLI4 (insn2))
1496 {
1497 int imm = (insn2 & 0x1f);
1498 adjust <<= imm;
1499 if (csky_debug)
1500 {
1501 gdb_printf (gdb_stdlog,
1502 "csky: lsli r4,r4, %d\n", imm);
1503 }
1504 }
1505
1506 offset += insn_len;
1507 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1508 };
1509
1510 if (csky_debug)
1511 {
1512 gdb_printf (gdb_stdlog, "csky: done looking for"
1513 " r4 adjusters\n");
1514 }
1515
1516 /* If the next insn adjusts the stack pointer, we keep
1517 everything; if not, we scrap it and we've found the
1518 end of the prologue. */
1519 if (CSKY_IS_SUBU4 (insn2))
1520 {
1521 addr += offset;
1522 stacksize += adjust;
1523 if (csky_debug)
1524 {
1525 gdb_printf (gdb_stdlog,
1526 "csky: found stack adjustment of"
1527 " 0x%x bytes.\n", adjust);
1528 gdb_printf (gdb_stdlog,
1529 "csky: skipping to new address %s\n",
1530 core_addr_to_string_nz (addr));
1531 gdb_printf (gdb_stdlog,
1532 "csky: continuing\n");
1533 }
1534 continue;
1535 }
1536
1537 /* None of these instructions are prologue, so don't touch
1538 anything. */
1539 if (csky_debug)
1540 {
1541 gdb_printf (gdb_stdlog,
1542 "csky: no subu sp,sp,r4; NOT altering"
1543 " stacksize.\n");
1544 }
1545 break;
1546 }
1547 }
1548 else
1549 {
1550 /* insn_len != 4. */
1551
1552 /* subi.sp sp,disp. */
1553 if (CSKY_16_IS_SUBI0 (insn))
1554 {
1555 int offset = CSKY_16_SUBI_IMM (insn);
1556 if (csky_debug)
1557 {
1558 gdb_printf (gdb_stdlog,
1559 "csky: got subi r0,%d; continuing\n",
1560 offset);
1561 }
1562 stacksize += offset;
1563 continue;
1564 }
1565 /* stw.16 rz,(sp,disp). */
1566 else if (CSKY_16_IS_STWx0 (insn))
1567 {
1568 /* Spill register: see note for IS_STM above. */
1569 int disp;
1570
1571 rn = CSKY_16_ST_VAL_REGNUM (insn);
1572 disp = CSKY_16_ST_OFFSET (insn);
1573 register_offsets[rn] = stacksize - disp;
1574 if (csky_debug)
1575 print_savedreg_msg (rn, register_offsets, true);
1576 continue;
1577 }
1578 else if (CSKY_16_IS_MOV_FP_SP (insn))
1579 {
1580 /* SP is saved to FP reg, means prologue may modify SP. */
1581 is_fp_saved = 1;
1582 adjust_fp = stacksize;
1583 continue;
1584 }
1585 else if (CSKY_16_IS_PUSH (insn))
1586 {
1587 /* Push for 16_bit. */
1588 int offset = 0;
1589 if (CSKY_16_IS_PUSH_R15 (insn))
1590 {
1591 stacksize += 4;
1592 register_offsets[15] = stacksize;
1593 if (csky_debug)
1594 print_savedreg_msg (15, register_offsets, false);
1595 offset += 4;
1596 }
1597 if (CSKY_16_PUSH_LIST1 (insn))
1598 {
1599 int num = CSKY_16_PUSH_LIST1 (insn);
1600 int tmp = 0;
1601 stacksize += num * 4;
1602 offset += num * 4;
1603 if (csky_debug)
1604 {
1605 gdb_printf (gdb_stdlog,
1606 "csky: push regs_array: r4-r%d\n",
1607 4 + num - 1);
1608 }
1609 for (rn = 4; rn <= 4 + num - 1; rn++)
1610 {
1611 register_offsets[rn] = stacksize - tmp;
1612 if (csky_debug)
1613 {
1614 gdb_printf (gdb_stdlog,
1615 "csky: r%d saved at 0x%x"
1616 " (offset %d)\n", rn,
1617 register_offsets[rn], offset);
1618 }
1619 tmp += 4;
1620 }
1621 }
1622
1623 framesize = stacksize;
1624 if (csky_debug)
1625 gdb_printf (gdb_stdlog, "csky: continuing\n");
1626 continue;
1627 }
1628 else if (CSKY_16_IS_LRW4 (insn) || CSKY_16_IS_MOVI4 (insn))
1629 {
1630 int adjust = 0;
1631 unsigned int insn2;
1632
1633 if (csky_debug)
1634 {
1635 gdb_printf (gdb_stdlog,
1636 "csky: looking at large frame\n");
1637 }
1638 if (CSKY_16_IS_LRW4 (insn))
1639 {
1640 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1641 int offset = ((insn & 0x300) >> 3) | (insn & 0x1f);
1642 int literal_addr = (addr + ( offset << 2)) & 0xfffffffc;
1643 adjust = read_memory_unsigned_integer (literal_addr, 4,
1644 byte_order);
1645 }
1646 else
1647 {
1648 /* CSKY_16_IS_MOVI4 (insn). */
1649 adjust = (insn & 0xff);
1650 }
1651
1652 if (csky_debug)
1653 {
1654 gdb_printf (gdb_stdlog,
1655 "csky: base stacksize=0x%x\n", adjust);
1656 }
1657
1658 /* May have zero or more instructions which modify r4. */
1659 if (csky_debug)
1660 {
1661 gdb_printf (gdb_stdlog,
1662 "csky: looking for r4 adjusters...\n");
1663 }
1664 int offset = 2;
1665 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1666 while (CSKY_IS_R4_ADJUSTER (insn2))
1667 {
1668 if (CSKY_32_IS_ADDI4 (insn2))
1669 {
1670 int imm = (insn2 & 0xfff) + 1;
1671 adjust += imm;
1672 if (csky_debug)
1673 {
1674 gdb_printf (gdb_stdlog,
1675 "csky: addi r4,%d\n", imm);
1676 }
1677 }
1678 else if (CSKY_32_IS_SUBI4 (insn2))
1679 {
1680 int imm = (insn2 & 0xfff) + 1;
1681 adjust -= imm;
1682 if (csky_debug)
1683 {
1684 gdb_printf (gdb_stdlog,
1685 "csky: subi r4,%d\n", imm);
1686 }
1687 }
1688 else if (CSKY_32_IS_NOR4 (insn2))
1689 {
1690 adjust = ~adjust;
1691 if (csky_debug)
1692 {
1693 gdb_printf (gdb_stdlog,
1694 "csky: nor r4,r4,r4\n");
1695 }
1696 }
1697 else if (CSKY_32_IS_ROTLI4 (insn2))
1698 {
1699 int imm = ((insn2 >> 21) & 0x1f);
1700 int temp = adjust >> (32 - imm);
1701 adjust <<= imm;
1702 adjust |= temp;
1703 if (csky_debug)
1704 {
1705 gdb_printf (gdb_stdlog,
1706 "csky: rotli r4,r4,%d\n", imm);
1707 }
1708 }
1709 else if (CSKY_32_IS_LISI4 (insn2))
1710 {
1711 int imm = ((insn2 >> 21) & 0x1f);
1712 adjust <<= imm;
1713 if (csky_debug)
1714 {
1715 gdb_printf (gdb_stdlog,
1716 "csky: lsli r4,r4,%d\n", imm);
1717 }
1718 }
1719 else if (CSKY_32_IS_BSETI4 (insn2))
1720 {
1721 int imm = ((insn2 >> 21) & 0x1f);
1722 adjust |= (1 << imm);
1723 if (csky_debug)
1724 {
1725 gdb_printf (gdb_stdlog,
1726 "csky: bseti r4,r4 %d\n", imm);
1727 }
1728 }
1729 else if (CSKY_32_IS_BCLRI4 (insn2))
1730 {
1731 int imm = ((insn2 >> 21) & 0x1f);
1732 adjust &= ~(1 << imm);
1733 if (csky_debug)
1734 {
1735 gdb_printf (gdb_stdlog,
1736 "csky: bclri r4,r4 %d\n", imm);
1737 }
1738 }
1739 else if (CSKY_32_IS_IXH4 (insn2))
1740 {
1741 adjust *= 3;
1742 if (csky_debug)
1743 {
1744 gdb_printf (gdb_stdlog,
1745 "csky: ixh r4,r4,r4\n");
1746 }
1747 }
1748 else if (CSKY_32_IS_IXW4 (insn2))
1749 {
1750 adjust *= 5;
1751 if (csky_debug)
1752 {
1753 gdb_printf (gdb_stdlog,
1754 "csky: ixw r4,r4,r4\n");
1755 }
1756 }
1757 else if (CSKY_16_IS_ADDI4 (insn2))
1758 {
1759 int imm = (insn2 & 0xff) + 1;
1760 adjust += imm;
1761 if (csky_debug)
1762 {
1763 gdb_printf (gdb_stdlog,
1764 "csky: addi r4,%d\n", imm);
1765 }
1766 }
1767 else if (CSKY_16_IS_SUBI4 (insn2))
1768 {
1769 int imm = (insn2 & 0xff) + 1;
1770 adjust -= imm;
1771 if (csky_debug)
1772 {
1773 gdb_printf (gdb_stdlog,
1774 "csky: subi r4,%d\n", imm);
1775 }
1776 }
1777 else if (CSKY_16_IS_NOR4 (insn2))
1778 {
1779 adjust = ~adjust;
1780 if (csky_debug)
1781 {
1782 gdb_printf (gdb_stdlog,
1783 "csky: nor r4,r4\n");
1784 }
1785 }
1786 else if (CSKY_16_IS_BSETI4 (insn2))
1787 {
1788 int imm = (insn2 & 0x1f);
1789 adjust |= (1 << imm);
1790 if (csky_debug)
1791 {
1792 gdb_printf (gdb_stdlog,
1793 "csky: bseti r4, %d\n", imm);
1794 }
1795 }
1796 else if (CSKY_16_IS_BCLRI4 (insn2))
1797 {
1798 int imm = (insn2 & 0x1f);
1799 adjust &= ~(1 << imm);
1800 if (csky_debug)
1801 {
1802 gdb_printf (gdb_stdlog,
1803 "csky: bclri r4, %d\n", imm);
1804 }
1805 }
1806 else if (CSKY_16_IS_LSLI4 (insn2))
1807 {
1808 int imm = (insn2 & 0x1f);
1809 adjust <<= imm;
1810 if (csky_debug)
1811 {
1812 gdb_printf (gdb_stdlog,
1813 "csky: lsli r4,r4, %d\n", imm);
1814 }
1815 }
1816
1817 offset += insn_len;
1818 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1819 };
1820
1821 if (csky_debug)
1822 {
1823 gdb_printf (gdb_stdlog, "csky: "
1824 "done looking for r4 adjusters\n");
1825 }
1826
1827 /* If the next instruction adjusts the stack pointer, we keep
1828 everything; if not, we scrap it and we've found the end
1829 of the prologue. */
1830 if (CSKY_IS_SUBU4 (insn2))
1831 {
1832 addr += offset;
1833 stacksize += adjust;
1834 if (csky_debug)
1835 {
1836 gdb_printf (gdb_stdlog, "csky: "
1837 "found stack adjustment of 0x%x"
1838 " bytes.\n", adjust);
1839 gdb_printf (gdb_stdlog, "csky: "
1840 "skipping to new address %s\n",
1841 core_addr_to_string_nz (addr));
1842 gdb_printf (gdb_stdlog, "csky: continuing\n");
1843 }
1844 continue;
1845 }
1846
1847 /* None of these instructions are prologue, so don't touch
1848 anything. */
1849 if (csky_debug)
1850 {
1851 gdb_printf (gdb_stdlog, "csky: no subu sp,r4; "
1852 "NOT altering stacksize.\n");
1853 }
1854 break;
1855 }
1856 }
1857
1858 /* This is not a prologue instruction, so stop here. */
1859 if (csky_debug)
1860 {
1861 gdb_printf (gdb_stdlog, "csky: insn is not a prologue"
1862 " insn -- ending scan\n");
1863 }
1864 break;
1865 }
1866
1867 if (this_cache)
1868 {
1869 CORE_ADDR unwound_fp;
1870 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1871 this_cache->framesize = framesize;
1872
1873 if (is_fp_saved)
1874 {
1875 this_cache->framereg = CSKY_FP_REGNUM;
1876 unwound_fp = get_frame_register_unsigned (this_frame,
1877 this_cache->framereg);
1878 this_cache->prev_sp = unwound_fp + adjust_fp;
1879 }
1880 else
1881 {
1882 this_cache->framereg = CSKY_SP_REGNUM;
1883 unwound_fp = get_frame_register_unsigned (this_frame,
1884 this_cache->framereg);
1885 this_cache->prev_sp = unwound_fp + stacksize;
1886 }
1887
1888 /* Note where saved registers are stored. The offsets in
1889 REGISTER_OFFSETS are computed relative to the top of the frame. */
1890 for (rn = 0; rn < CSKY_NUM_GREGS; rn++)
1891 {
1892 if (register_offsets[rn] >= 0)
1893 {
1894 this_cache->saved_regs[rn].set_addr (this_cache->prev_sp
1895 - register_offsets[rn]);
1896 if (csky_debug)
1897 {
1898 CORE_ADDR rn_value = read_memory_unsigned_integer (
1899 this_cache->saved_regs[rn].addr (), 4, byte_order);
1900 gdb_printf (gdb_stdlog, "Saved register %s "
1901 "stored at 0x%08lx, value=0x%08lx\n",
1902 csky_register_names[rn],
1903 (unsigned long)
1904 this_cache->saved_regs[rn].addr (),
1905 (unsigned long) rn_value);
1906 }
1907 }
1908 }
1909 if (lr_type == LR_TYPE_EPC)
1910 {
1911 /* rte || epc . */
1912 this_cache->saved_regs[CSKY_PC_REGNUM]
1913 = this_cache->saved_regs[CSKY_EPC_REGNUM];
1914 }
1915 else if (lr_type == LR_TYPE_FPC)
1916 {
1917 /* rfi || fpc . */
1918 this_cache->saved_regs[CSKY_PC_REGNUM]
1919 = this_cache->saved_regs[CSKY_FPC_REGNUM];
1920 }
1921 else
1922 {
1923 this_cache->saved_regs[CSKY_PC_REGNUM]
1924 = this_cache->saved_regs[CSKY_LR_REGNUM];
1925 }
1926 }
1927
1928 return addr;
1929 }
1930
1931 /* Detect whether PC is at a point where the stack frame has been
1932 destroyed. */
1933
1934 static int
1935 csky_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1936 {
1937 unsigned int insn;
1938 CORE_ADDR addr;
1939 CORE_ADDR func_start, func_end;
1940
1941 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
1942 return 0;
1943
1944 bool fp_saved = false;
1945 int insn_len;
1946 for (addr = func_start; addr < func_end; addr += insn_len)
1947 {
1948 /* Get next insn. */
1949 insn_len = csky_get_insn (gdbarch, addr, &insn);
1950
1951 if (insn_len == 2)
1952 {
1953 /* Is sp is saved to fp. */
1954 if (CSKY_16_IS_MOV_FP_SP (insn))
1955 fp_saved = true;
1956 /* If sp was saved to fp and now being restored from
1957 fp then it indicates the start of epilog. */
1958 else if (fp_saved && CSKY_16_IS_MOV_SP_FP (insn))
1959 return pc >= addr;
1960 }
1961 }
1962 return 0;
1963 }
1964
1965 /* Implement the skip_prologue gdbarch hook. */
1966
1967 static CORE_ADDR
1968 csky_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1969 {
1970 CORE_ADDR func_addr, func_end;
1971 const int default_search_limit = 128;
1972
1973 /* See if we can find the end of the prologue using the symbol table. */
1974 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1975 {
1976 CORE_ADDR post_prologue_pc
1977 = skip_prologue_using_sal (gdbarch, func_addr);
1978
1979 if (post_prologue_pc != 0)
1980 return std::max (pc, post_prologue_pc);
1981 }
1982 else
1983 func_end = pc + default_search_limit;
1984
1985 /* Find the end of prologue. Default lr_type. */
1986 return csky_analyze_prologue (gdbarch, pc, func_end, func_end,
1987 NULL, NULL, LR_TYPE_R15);
1988 }
1989
1990 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1991
1992 static int
1993 csky_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1994 {
1995 if (csky_pc_is_csky16 (gdbarch, *pcptr))
1996 return CSKY_INSN_SIZE16;
1997 else
1998 return CSKY_INSN_SIZE32;
1999 }
2000
2001 /* Implement the sw_breakpoint_from_kind gdbarch method. */
2002
2003 static const gdb_byte *
2004 csky_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
2005 {
2006 *size = kind;
2007 if (kind == CSKY_INSN_SIZE16)
2008 {
2009 static gdb_byte csky_16_breakpoint[] = { 0, 0 };
2010 return csky_16_breakpoint;
2011 }
2012 else
2013 {
2014 static gdb_byte csky_32_breakpoint[] = { 0, 0, 0, 0 };
2015 return csky_32_breakpoint;
2016 }
2017 }
2018
2019 /* Determine link register type. */
2020
2021 static lr_type_t
2022 csky_analyze_lr_type (struct gdbarch *gdbarch,
2023 CORE_ADDR start_pc, CORE_ADDR end_pc)
2024 {
2025 CORE_ADDR addr;
2026 unsigned int insn, insn_len;
2027 insn_len = 2;
2028
2029 for (addr = start_pc; addr < end_pc; addr += insn_len)
2030 {
2031 insn_len = csky_get_insn (gdbarch, addr, &insn);
2032 if (insn_len == 4)
2033 {
2034 if (CSKY_32_IS_MFCR_EPSR (insn) || CSKY_32_IS_MFCR_EPC (insn)
2035 || CSKY_32_IS_RTE (insn))
2036 return LR_TYPE_EPC;
2037 }
2038 else if (CSKY_32_IS_MFCR_FPSR (insn) || CSKY_32_IS_MFCR_FPC (insn)
2039 || CSKY_32_IS_RFI (insn))
2040 return LR_TYPE_FPC;
2041 else if (CSKY_32_IS_JMP (insn) || CSKY_32_IS_BR (insn)
2042 || CSKY_32_IS_JMPIX (insn) || CSKY_32_IS_JMPI (insn))
2043 return LR_TYPE_R15;
2044 else
2045 {
2046 /* 16 bit instruction. */
2047 if (CSKY_16_IS_JMP (insn) || CSKY_16_IS_BR (insn)
2048 || CSKY_16_IS_JMPIX (insn))
2049 return LR_TYPE_R15;
2050 }
2051 }
2052 return LR_TYPE_R15;
2053 }
2054
2055 /* Heuristic unwinder. */
2056
2057 static struct csky_unwind_cache *
2058 csky_frame_unwind_cache (struct frame_info *this_frame)
2059 {
2060 CORE_ADDR prologue_start, prologue_end, func_end, prev_pc, block_addr;
2061 struct csky_unwind_cache *cache;
2062 const struct block *bl;
2063 unsigned long func_size = 0;
2064 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2065 unsigned int sp_regnum = CSKY_SP_REGNUM;
2066
2067 /* Default lr type is r15. */
2068 lr_type_t lr_type = LR_TYPE_R15;
2069
2070 cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
2071 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2072
2073 /* Assume there is no frame until proven otherwise. */
2074 cache->framereg = sp_regnum;
2075
2076 cache->framesize = 0;
2077
2078 prev_pc = get_frame_pc (this_frame);
2079 block_addr = get_frame_address_in_block (this_frame);
2080 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
2081 &func_end) == 0)
2082 /* We couldn't find a function containing block_addr, so bail out
2083 and hope for the best. */
2084 return cache;
2085
2086 /* Get the (function) symbol matching prologue_start. */
2087 bl = block_for_pc (prologue_start);
2088 if (bl != NULL)
2089 func_size = bl->end () - bl->start ();
2090 else
2091 {
2092 struct bound_minimal_symbol msymbol
2093 = lookup_minimal_symbol_by_pc (prologue_start);
2094 if (msymbol.minsym != NULL)
2095 func_size = msymbol.minsym->size ();
2096 }
2097
2098 /* If FUNC_SIZE is 0 we may have a special-case use of lr
2099 e.g. exception or interrupt. */
2100 if (func_size == 0)
2101 lr_type = csky_analyze_lr_type (gdbarch, prologue_start, func_end);
2102
2103 prologue_end = std::min (func_end, prev_pc);
2104
2105 /* Analyze the function prologue. */
2106 csky_analyze_prologue (gdbarch, prologue_start, prologue_end,
2107 func_end, this_frame, cache, lr_type);
2108
2109 /* gdbarch_sp_regnum contains the value and not the address. */
2110 cache->saved_regs[sp_regnum].set_value (cache->prev_sp);
2111 return cache;
2112 }
2113
2114 /* Implement the this_id function for the normal unwinder. */
2115
2116 static void
2117 csky_frame_this_id (struct frame_info *this_frame,
2118 void **this_prologue_cache, struct frame_id *this_id)
2119 {
2120 struct csky_unwind_cache *cache;
2121 struct frame_id id;
2122
2123 if (*this_prologue_cache == NULL)
2124 *this_prologue_cache = csky_frame_unwind_cache (this_frame);
2125 cache = (struct csky_unwind_cache *) *this_prologue_cache;
2126
2127 /* This marks the outermost frame. */
2128 if (cache->prev_sp == 0)
2129 return;
2130
2131 id = frame_id_build (cache->prev_sp, get_frame_func (this_frame));
2132 *this_id = id;
2133 }
2134
2135 /* Implement the prev_register function for the normal unwinder. */
2136
2137 static struct value *
2138 csky_frame_prev_register (struct frame_info *this_frame,
2139 void **this_prologue_cache, int regnum)
2140 {
2141 struct csky_unwind_cache *cache;
2142
2143 if (*this_prologue_cache == NULL)
2144 *this_prologue_cache = csky_frame_unwind_cache (this_frame);
2145 cache = (struct csky_unwind_cache *) *this_prologue_cache;
2146
2147 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2148 regnum);
2149 }
2150
2151 /* Data structures for the normal prologue-analysis-based
2152 unwinder. */
2153
2154 static const struct frame_unwind csky_unwind_cache = {
2155 "cski prologue",
2156 NORMAL_FRAME,
2157 default_frame_unwind_stop_reason,
2158 csky_frame_this_id,
2159 csky_frame_prev_register,
2160 NULL,
2161 default_frame_sniffer,
2162 NULL,
2163 NULL
2164 };
2165
2166 static CORE_ADDR
2167 csky_check_long_branch (struct frame_info *frame, CORE_ADDR pc)
2168 {
2169 gdb_byte buf[8];
2170 struct gdbarch *gdbarch = get_frame_arch (frame);
2171 enum bfd_endian byte_order_for_code
2172 = gdbarch_byte_order_for_code (gdbarch);
2173
2174 if (target_read_memory (pc, buf, 8) == 0)
2175 {
2176 unsigned int data0
2177 = extract_unsigned_integer (buf, 4, byte_order_for_code);
2178 unsigned int data1
2179 = extract_unsigned_integer (buf + 4, 4, byte_order_for_code);
2180
2181 /* Case: jmpi [pc+4] : 0xeac00001
2182 .long addr */
2183 if (data0 == CSKY_JMPI_PC_4)
2184 return data1;
2185
2186 /* Case: lrw t1, [pc+8] : 0xea8d0002
2187 jmp t1 : 0x7834
2188 nop : 0x6c03
2189 .long addr */
2190 if ((data0 == CSKY_LRW_T1_PC_8) && (data1 == CSKY_JMP_T1_VS_NOP))
2191 {
2192 if (target_read_memory (pc + 8, buf, 4) == 0)
2193 return extract_unsigned_integer (buf, 4, byte_order_for_code);
2194 }
2195
2196 return 0;
2197 }
2198
2199 return 0;
2200 }
2201
2202 static int
2203 csky_stub_unwind_sniffer (const struct frame_unwind *self,
2204 struct frame_info *this_frame,
2205 void **this_prologue_cache)
2206 {
2207 CORE_ADDR addr_in_block, pc;
2208 gdb_byte dummy[4];
2209 const char *name;
2210 CORE_ADDR start_addr;
2211
2212 /* Get pc */
2213 addr_in_block = get_frame_address_in_block (this_frame);
2214 pc = get_frame_pc (this_frame);
2215
2216 if (in_plt_section (addr_in_block)
2217 || target_read_memory (pc, dummy, 4) != 0)
2218 return 1;
2219
2220 /* Find the starting address and name of the function containing the PC. */
2221 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2222 {
2223 start_addr = csky_check_long_branch (this_frame, pc);
2224 /* if not long branch, return 0. */
2225 if (start_addr != 0)
2226 return 1;
2227
2228 return 0;
2229 }
2230
2231 return 0;
2232 }
2233
2234 static struct csky_unwind_cache *
2235 csky_make_stub_cache (struct frame_info *this_frame)
2236 {
2237 struct csky_unwind_cache *cache;
2238
2239 cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
2240 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2241 cache->prev_sp = get_frame_register_unsigned (this_frame, CSKY_SP_REGNUM);
2242
2243 return cache;
2244 }
2245
2246 static void
2247 csky_stub_this_id (struct frame_info *this_frame,
2248 void **this_cache,
2249 struct frame_id *this_id)
2250 {
2251 struct csky_unwind_cache *cache;
2252
2253 if (*this_cache == NULL)
2254 *this_cache = csky_make_stub_cache (this_frame);
2255 cache = (struct csky_unwind_cache *) *this_cache;
2256
2257 /* Our frame ID for a stub frame is the current SP and LR. */
2258 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2259 }
2260
2261 static struct value *
2262 csky_stub_prev_register (struct frame_info *this_frame,
2263 void **this_cache,
2264 int prev_regnum)
2265 {
2266 struct csky_unwind_cache *cache;
2267
2268 if (*this_cache == NULL)
2269 *this_cache = csky_make_stub_cache (this_frame);
2270 cache = (struct csky_unwind_cache *) *this_cache;
2271
2272 /* If we are asked to unwind the PC, then return the LR. */
2273 if (prev_regnum == CSKY_PC_REGNUM)
2274 {
2275 CORE_ADDR lr;
2276
2277 lr = frame_unwind_register_unsigned (this_frame, CSKY_LR_REGNUM);
2278 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
2279 }
2280
2281 if (prev_regnum == CSKY_SP_REGNUM)
2282 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2283
2284 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2285 prev_regnum);
2286 }
2287
2288 static frame_unwind csky_stub_unwind = {
2289 "csky stub",
2290 NORMAL_FRAME,
2291 default_frame_unwind_stop_reason,
2292 csky_stub_this_id,
2293 csky_stub_prev_register,
2294 NULL,
2295 csky_stub_unwind_sniffer
2296 };
2297
2298 /* Implement the this_base, this_locals, and this_args hooks
2299 for the normal unwinder. */
2300
2301 static CORE_ADDR
2302 csky_frame_base_address (struct frame_info *this_frame, void **this_cache)
2303 {
2304 struct csky_unwind_cache *cache;
2305
2306 if (*this_cache == NULL)
2307 *this_cache = csky_frame_unwind_cache (this_frame);
2308 cache = (struct csky_unwind_cache *) *this_cache;
2309
2310 return cache->prev_sp - cache->framesize;
2311 }
2312
2313 static const struct frame_base csky_frame_base = {
2314 &csky_unwind_cache,
2315 csky_frame_base_address,
2316 csky_frame_base_address,
2317 csky_frame_base_address
2318 };
2319
2320 /* Initialize register access method. */
2321
2322 static void
2323 csky_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2324 struct dwarf2_frame_state_reg *reg,
2325 struct frame_info *this_frame)
2326 {
2327 if (regnum == gdbarch_pc_regnum (gdbarch))
2328 reg->how = DWARF2_FRAME_REG_RA;
2329 else if (regnum == gdbarch_sp_regnum (gdbarch))
2330 reg->how = DWARF2_FRAME_REG_CFA;
2331 }
2332
2333 /* Create csky register groups. */
2334
2335 static void
2336 csky_init_reggroup ()
2337 {
2338 cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
2339 fr_reggroup = reggroup_new ("fr", USER_REGGROUP);
2340 vr_reggroup = reggroup_new ("vr", USER_REGGROUP);
2341 mmu_reggroup = reggroup_new ("mmu", USER_REGGROUP);
2342 prof_reggroup = reggroup_new ("profiling", USER_REGGROUP);
2343 }
2344
2345 /* Add register groups into reggroup list. */
2346
2347 static void
2348 csky_add_reggroups (struct gdbarch *gdbarch)
2349 {
2350 reggroup_add (gdbarch, cr_reggroup);
2351 reggroup_add (gdbarch, fr_reggroup);
2352 reggroup_add (gdbarch, vr_reggroup);
2353 reggroup_add (gdbarch, mmu_reggroup);
2354 reggroup_add (gdbarch, prof_reggroup);
2355 }
2356
2357 /* Return the groups that a CSKY register can be categorised into. */
2358
2359 static int
2360 csky_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2361 const struct reggroup *reggroup)
2362 {
2363 int raw_p;
2364
2365 if (gdbarch_register_name (gdbarch, regnum) == NULL
2366 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
2367 return 0;
2368
2369 if (reggroup == all_reggroup)
2370 return 1;
2371
2372 raw_p = regnum < gdbarch_num_regs (gdbarch);
2373 if (reggroup == save_reggroup || reggroup == restore_reggroup)
2374 return raw_p;
2375
2376 if ((((regnum >= CSKY_R0_REGNUM) && (regnum <= CSKY_R0_REGNUM + 31))
2377 || (regnum == CSKY_PC_REGNUM)
2378 || (regnum == CSKY_EPC_REGNUM)
2379 || (regnum == CSKY_CR0_REGNUM)
2380 || (regnum == CSKY_EPSR_REGNUM))
2381 && (reggroup == general_reggroup))
2382 return 1;
2383
2384 if (((regnum == CSKY_PC_REGNUM)
2385 || ((regnum >= CSKY_CR0_REGNUM)
2386 && (regnum <= CSKY_CR0_REGNUM + 30)))
2387 && (reggroup == cr_reggroup))
2388 return 2;
2389
2390 if ((((regnum >= CSKY_VR0_REGNUM) && (regnum <= CSKY_VR0_REGNUM + 15))
2391 || ((regnum >= CSKY_FCR_REGNUM)
2392 && (regnum <= CSKY_FCR_REGNUM + 2)))
2393 && (reggroup == vr_reggroup))
2394 return 3;
2395
2396 if (((regnum >= CSKY_MMU_REGNUM) && (regnum <= CSKY_MMU_REGNUM + 8))
2397 && (reggroup == mmu_reggroup))
2398 return 4;
2399
2400 if (((regnum >= CSKY_PROFCR_REGNUM)
2401 && (regnum <= CSKY_PROFCR_REGNUM + 48))
2402 && (reggroup == prof_reggroup))
2403 return 5;
2404
2405 if ((((regnum >= CSKY_FR0_REGNUM) && (regnum <= CSKY_FR0_REGNUM + 15))
2406 || ((regnum >= CSKY_FCR_REGNUM) && (regnum <= CSKY_FCR_REGNUM + 2)))
2407 && (reggroup == fr_reggroup))
2408 return 6;
2409
2410 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
2411 {
2412 if (tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup) > 0)
2413 return 7;
2414 }
2415
2416 return 0;
2417 }
2418
2419 /* Implement the dwarf2_reg_to_regnum gdbarch method. */
2420
2421 static int
2422 csky_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg)
2423 {
2424 /* For GPRs. */
2425 if (dw_reg >= CSKY_R0_REGNUM && dw_reg <= CSKY_R0_REGNUM + 31)
2426 return dw_reg;
2427
2428 /* For Hi, Lo, PC. */
2429 if (dw_reg == CSKY_HI_REGNUM || dw_reg == CSKY_LO_REGNUM
2430 || dw_reg == CSKY_PC_REGNUM)
2431 return dw_reg;
2432
2433 /* For Float and Vector pseudo registers. */
2434 if (dw_reg >= FV_PSEUDO_REGNO_FIRST && dw_reg <= FV_PSEUDO_REGNO_LAST)
2435 {
2436 char name_buf[4];
2437
2438 xsnprintf (name_buf, sizeof (name_buf), "s%d",
2439 dw_reg - FV_PSEUDO_REGNO_FIRST);
2440 return user_reg_map_name_to_regnum (gdbarch, name_buf,
2441 strlen (name_buf));
2442 }
2443
2444 /* Others, unknown. */
2445 return -1;
2446 }
2447
2448 /* Check whether xml has discribled the essential regs. */
2449
2450 static int
2451 csky_essential_reg_check (const struct csky_supported_tdesc_register *reg)
2452 {
2453 if ((strcmp (reg->name , "pc") == 0)
2454 && (reg->num == CSKY_PC_REGNUM))
2455 return CSKY_TDESC_REGS_PC_NUMBERED;
2456 else if ((strcmp (reg->name , "r14") == 0)
2457 && (reg->num == CSKY_SP_REGNUM))
2458 return CSKY_TDESC_REGS_SP_NUMBERED;
2459 else if ((strcmp (reg->name , "r15") == 0)
2460 && (reg->num == CSKY_LR_REGNUM))
2461 return CSKY_TDESC_REGS_LR_NUMBERED;
2462 else
2463 return 0;
2464 }
2465
2466 /* Check whether xml has discribled the fr0~fr15 regs. */
2467
2468 static int
2469 csky_fr0_fr15_reg_check (const struct csky_supported_tdesc_register *reg) {
2470 int i = 0;
2471 for (i = 0; i < 16; i++)
2472 {
2473 if ((strcmp (reg->name, csky_supported_fpu_regs[i].name) == 0)
2474 && (csky_supported_fpu_regs[i].num == reg->num))
2475 return (1 << i);
2476 }
2477
2478 return 0;
2479 };
2480
2481 /* Check whether xml has discribled the fr16~fr31 regs. */
2482
2483 static int
2484 csky_fr16_fr31_reg_check (const struct csky_supported_tdesc_register *reg) {
2485 int i = 0;
2486 for (i = 0; i < 16; i++)
2487 {
2488 if ((strcmp (reg->name, csky_supported_fpu_regs[i + 16].name) == 0)
2489 && (csky_supported_fpu_regs[i + 16].num == reg->num))
2490 return (1 << i);
2491 }
2492
2493 return 0;
2494 };
2495
2496 /* Check whether xml has discribled the vr0~vr15 regs. */
2497
2498 static int
2499 csky_vr0_vr15_reg_check (const struct csky_supported_tdesc_register *reg) {
2500 int i = 0;
2501 for (i = 0; i < 16; i++)
2502 {
2503 if ((strcmp (reg->name, csky_supported_fpu_regs[i + 32].name) == 0)
2504 && (csky_supported_fpu_regs[i + 32].num == reg->num))
2505 return (1 << i);
2506 }
2507
2508 return 0;
2509 };
2510
2511 /* Return pseudo reg's name. */
2512
2513 static const char *
2514 csky_pseudo_register_name (struct gdbarch *gdbarch, int regno)
2515 {
2516 int num_regs = gdbarch_num_regs (gdbarch);
2517 csky_gdbarch_tdep *tdep
2518 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2519
2520 regno -= num_regs;
2521
2522 if (tdep->fv_pseudo_registers_count)
2523 {
2524 static const char *const fv_pseudo_names[] = {
2525 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2526 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2527 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2528 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2529 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2530 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2531 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2532 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2533 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2534 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2535 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2536 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2537 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2538 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2539 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2540 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2541 };
2542
2543 if (regno < tdep->fv_pseudo_registers_count)
2544 {
2545 if ((regno < 64) && ((regno % 4) >= 2) && !tdep->has_vr0)
2546 return NULL;
2547 else if ((regno >= 64) && ((regno % 4) >= 2))
2548 return NULL;
2549 else
2550 return fv_pseudo_names[regno];
2551 }
2552 }
2553
2554 return NULL;
2555 }
2556
2557 /* Read for csky pseudo regs. */
2558
2559 static enum register_status
2560 csky_pseudo_register_read (struct gdbarch *gdbarch,
2561 struct readable_regcache *regcache,
2562 int regnum, gdb_byte *buf)
2563 {
2564 int num_regs = gdbarch_num_regs (gdbarch);
2565 csky_gdbarch_tdep *tdep
2566 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2567
2568 regnum -= num_regs;
2569
2570 if (regnum < tdep->fv_pseudo_registers_count)
2571 {
2572 enum register_status status;
2573 int gdb_regnum = 0;
2574 int offset = 0;
2575 gdb_byte reg_buf[16];
2576
2577 /* Ensure getting s0~s63 from vrx if tdep->has_vr0 is ture. */
2578 if (tdep->has_vr0)
2579 {
2580 if (regnum < 64)
2581 {
2582 gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
2583 offset = (regnum % 4) * 4;
2584 }
2585 else
2586 {
2587 gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
2588 if ((regnum % 4) >= 2)
2589 return REG_UNAVAILABLE;
2590 offset = (regnum % 2) * 4;
2591 }
2592 }
2593 else
2594 {
2595 gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
2596 if ((regnum % 4) >= 2)
2597 return REG_UNAVAILABLE;
2598 offset = (regnum % 2) * 4;
2599 }
2600
2601 status = regcache->raw_read (gdb_regnum, reg_buf);
2602 if (status == REG_VALID)
2603 memcpy (buf, reg_buf + offset, 4);
2604 return status;
2605 }
2606
2607 return REG_UNKNOWN;
2608 }
2609
2610 /* Write for csky pseudo regs. */
2611
2612 static void
2613 csky_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2614 int regnum, const gdb_byte *buf)
2615 {
2616 int num_regs = gdbarch_num_regs (gdbarch);
2617 csky_gdbarch_tdep *tdep
2618 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2619
2620 regnum -= num_regs;
2621
2622 if (regnum < tdep->fv_pseudo_registers_count)
2623 {
2624 gdb_byte reg_buf[16];
2625 int gdb_regnum = 0;
2626 int offset = 0;
2627
2628 if (tdep->has_vr0)
2629 {
2630 if (regnum < 64)
2631 {
2632 gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
2633 offset = (regnum % 4) * 4;
2634 }
2635 else
2636 {
2637 gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
2638 if ((regnum % 4) >= 2)
2639 return;
2640 offset = (regnum % 2) * 4;
2641 }
2642 }
2643 else
2644 {
2645 gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
2646 if ((regnum % 4) >= 2)
2647 return;
2648 offset = (regnum % 2) * 4;
2649 }
2650
2651 regcache->raw_read (gdb_regnum, reg_buf);
2652 memcpy (reg_buf + offset, buf, 4);
2653 regcache->raw_write (gdb_regnum, reg_buf);
2654 return;
2655 }
2656
2657 return;
2658 }
2659
2660 /* Initialize the current architecture based on INFO. If possible,
2661 re-use an architecture from ARCHES, which is a list of
2662 architectures already created during this debugging session.
2663
2664 Called at program startup, when reading a core file, and when
2665 reading a binary file. */
2666
2667 static struct gdbarch *
2668 csky_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2669 {
2670 struct gdbarch *gdbarch;
2671 /* Analyze info.abfd. */
2672 unsigned int fpu_abi = 0;
2673 unsigned int vdsp_version = 0;
2674 unsigned int fpu_hardfp = 0;
2675 /* Analyze info.target_desc */
2676 int num_regs = 0;
2677 int has_fr0 = 0;
2678 int has_fr16 = 0;
2679 int has_vr0 = 0;
2680 tdesc_arch_data_up tdesc_data;
2681
2682 if (tdesc_has_registers (info.target_desc))
2683 {
2684 int valid_p = 0;
2685 int numbered = 0;
2686 int index = 0;
2687 int i = 0;
2688 int feature_names_count = ARRAY_SIZE (csky_supported_tdesc_feature_names);
2689 int support_tdesc_regs_count
2690 = csky_get_supported_tdesc_registers_count();
2691 const struct csky_supported_tdesc_register *tdesc_reg;
2692 const struct tdesc_feature *feature;
2693
2694 tdesc_data = tdesc_data_alloc ();
2695 for (index = 0; index < feature_names_count; index ++)
2696 {
2697 feature = tdesc_find_feature (info.target_desc,
2698 csky_supported_tdesc_feature_names[index]);
2699 if (feature != NULL)
2700 {
2701 for (i = 0; i < support_tdesc_regs_count; i++)
2702 {
2703 tdesc_reg = csky_get_supported_register_by_index (i);
2704 if (!tdesc_reg)
2705 break;
2706 numbered = tdesc_numbered_register (feature, tdesc_data.get(),
2707 tdesc_reg->num,
2708 tdesc_reg->name);
2709 if (numbered) {
2710 valid_p |= csky_essential_reg_check (tdesc_reg);
2711 has_fr0 |= csky_fr0_fr15_reg_check (tdesc_reg);
2712 has_fr16 |= csky_fr16_fr31_reg_check (tdesc_reg);
2713 has_vr0 |= csky_vr0_vr15_reg_check (tdesc_reg);
2714 if (num_regs < tdesc_reg->num)
2715 num_regs = tdesc_reg->num;
2716 }
2717 }
2718 }
2719 }
2720 if (valid_p != CSKY_TDESC_REGS_ESSENTIAL_VALUE)
2721 return NULL;
2722 }
2723
2724 /* When the type of bfd file is srec(or any files are not elf),
2725 the E_FLAGS will be not credible. */
2726 if (info.abfd != NULL && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2727 {
2728 /* Get FPU, VDSP build options. */
2729 fpu_abi = bfd_elf_get_obj_attr_int (info.abfd,
2730 OBJ_ATTR_PROC,
2731 Tag_CSKY_FPU_ABI);
2732 vdsp_version = bfd_elf_get_obj_attr_int (info.abfd,
2733 OBJ_ATTR_PROC,
2734 Tag_CSKY_VDSP_VERSION);
2735 fpu_hardfp = bfd_elf_get_obj_attr_int (info.abfd,
2736 OBJ_ATTR_PROC,
2737 Tag_CSKY_FPU_HARDFP);
2738 }
2739
2740 /* Find a candidate among the list of pre-declared architectures. */
2741 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2742 arches != NULL;
2743 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2744 {
2745 csky_gdbarch_tdep *tdep
2746 = gdbarch_tdep<csky_gdbarch_tdep> (arches->gdbarch);
2747 if (fpu_abi != tdep->fpu_abi)
2748 continue;
2749 if (vdsp_version != tdep->vdsp_version)
2750 continue;
2751 if (fpu_hardfp != tdep->fpu_hardfp)
2752 continue;
2753
2754 /* Found a match. */
2755 return arches->gdbarch;
2756 }
2757
2758 /* None found, create a new architecture from the information
2759 provided. */
2760 csky_gdbarch_tdep *tdep = new csky_gdbarch_tdep;
2761 gdbarch = gdbarch_alloc (&info, tdep);
2762 tdep->fpu_abi = fpu_abi;
2763 tdep->vdsp_version = vdsp_version;
2764 tdep->fpu_hardfp = fpu_hardfp;
2765
2766 if (tdesc_data != NULL)
2767 {
2768 if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
2769 && (has_fr16 == CSKY_FULL16_ONEHOT_VALUE))
2770 {
2771 tdep->has_vr0 = 1;
2772 tdep->fv_pseudo_registers_count = 128;
2773 }
2774 else if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
2775 && (has_fr16 != CSKY_FULL16_ONEHOT_VALUE))
2776 {
2777 tdep->has_vr0 = 1;
2778 tdep->fv_pseudo_registers_count = 64;
2779 }
2780 else if ((has_fr0 == CSKY_FULL16_ONEHOT_VALUE)
2781 && (has_vr0 != CSKY_FULL16_ONEHOT_VALUE))
2782 {
2783 tdep->has_vr0 = 0;
2784 tdep->fv_pseudo_registers_count = 64;
2785 }
2786 else
2787 {
2788 tdep->has_vr0 = 0;
2789 tdep->fv_pseudo_registers_count = 0;
2790 }
2791 }
2792 else
2793 {
2794 tdep->has_vr0 = 1;
2795 tdep->fv_pseudo_registers_count = 64;
2796 }
2797
2798 /* Target data types. */
2799 set_gdbarch_ptr_bit (gdbarch, 32);
2800 set_gdbarch_addr_bit (gdbarch, 32);
2801 set_gdbarch_short_bit (gdbarch, 16);
2802 set_gdbarch_int_bit (gdbarch, 32);
2803 set_gdbarch_long_bit (gdbarch, 32);
2804 set_gdbarch_long_long_bit (gdbarch, 64);
2805 set_gdbarch_float_bit (gdbarch, 32);
2806 set_gdbarch_double_bit (gdbarch, 64);
2807 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2808 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2809
2810 /* Information about the target architecture. */
2811 set_gdbarch_return_value (gdbarch, csky_return_value);
2812 set_gdbarch_breakpoint_kind_from_pc (gdbarch, csky_breakpoint_kind_from_pc);
2813 set_gdbarch_sw_breakpoint_from_kind (gdbarch, csky_sw_breakpoint_from_kind);
2814
2815 /* Register architecture. */
2816 set_gdbarch_num_regs (gdbarch, CSKY_NUM_REGS);
2817 set_gdbarch_pc_regnum (gdbarch, CSKY_PC_REGNUM);
2818 set_gdbarch_sp_regnum (gdbarch, CSKY_SP_REGNUM);
2819 set_gdbarch_register_name (gdbarch, csky_register_name);
2820 set_gdbarch_register_type (gdbarch, csky_register_type);
2821 set_gdbarch_read_pc (gdbarch, csky_read_pc);
2822 set_gdbarch_write_pc (gdbarch, csky_write_pc);
2823 csky_add_reggroups (gdbarch);
2824 set_gdbarch_register_reggroup_p (gdbarch, csky_register_reggroup_p);
2825 set_gdbarch_stab_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
2826 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
2827 dwarf2_frame_set_init_reg (gdbarch, csky_dwarf2_frame_init_reg);
2828
2829 /* Functions to analyze frames. */
2830 frame_base_set_default (gdbarch, &csky_frame_base);
2831 set_gdbarch_skip_prologue (gdbarch, csky_skip_prologue);
2832 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2833 set_gdbarch_frame_align (gdbarch, csky_frame_align);
2834 set_gdbarch_stack_frame_destroyed_p (gdbarch, csky_stack_frame_destroyed_p);
2835
2836 /* Functions handling dummy frames. */
2837 set_gdbarch_push_dummy_call (gdbarch, csky_push_dummy_call);
2838
2839 /* Frame unwinders. Use DWARF debug info if available,
2840 otherwise use our own unwinder. */
2841 dwarf2_append_unwinders (gdbarch);
2842 frame_unwind_append_unwinder (gdbarch, &csky_stub_unwind);
2843 frame_unwind_append_unwinder (gdbarch, &csky_unwind_cache);
2844
2845 /* Hook in ABI-specific overrides, if they have been registered. */
2846 gdbarch_init_osabi (info, gdbarch);
2847
2848 /* Support simple overlay manager. */
2849 set_gdbarch_overlay_update (gdbarch, simple_overlay_update);
2850 set_gdbarch_char_signed (gdbarch, 0);
2851
2852 if (tdesc_data != nullptr)
2853 {
2854 set_gdbarch_num_regs (gdbarch, (num_regs + 1));
2855 tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data));
2856 set_gdbarch_register_type (gdbarch, csky_register_type);
2857 set_gdbarch_register_reggroup_p (gdbarch,
2858 csky_register_reggroup_p);
2859 }
2860
2861 if (tdep->fv_pseudo_registers_count)
2862 {
2863 set_gdbarch_num_pseudo_regs (gdbarch,
2864 tdep->fv_pseudo_registers_count);
2865 set_gdbarch_pseudo_register_read (gdbarch,
2866 csky_pseudo_register_read);
2867 set_gdbarch_pseudo_register_write (gdbarch,
2868 csky_pseudo_register_write);
2869 set_tdesc_pseudo_register_name (gdbarch, csky_pseudo_register_name);
2870 }
2871
2872 return gdbarch;
2873 }
2874
2875 void _initialize_csky_tdep ();
2876 void
2877 _initialize_csky_tdep ()
2878 {
2879
2880 gdbarch_register (bfd_arch_csky, csky_gdbarch_init);
2881
2882 csky_init_reggroup ();
2883
2884 /* Allow debugging this file's internals. */
2885 add_setshow_boolean_cmd ("csky", class_maintenance, &csky_debug,
2886 _("Set C-Sky debugging."),
2887 _("Show C-Sky debugging."),
2888 _("When on, C-Sky specific debugging is enabled."),
2889 NULL,
2890 NULL,
2891 &setdebuglist, &showdebuglist);
2892 }
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