]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - gdb/frv-tdep.c
Copyright updates for 2007.
[thirdparty/binutils-gdb.git] / gdb / frv-tdep.c
1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
2
3 Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include "defs.h"
23 #include "gdb_string.h"
24 #include "inferior.h"
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "regcache.h"
28 #include "frame.h"
29 #include "frame-unwind.h"
30 #include "frame-base.h"
31 #include "trad-frame.h"
32 #include "dis-asm.h"
33 #include "gdb_assert.h"
34 #include "sim-regno.h"
35 #include "gdb/sim-frv.h"
36 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
37 #include "symtab.h"
38 #include "elf-bfd.h"
39 #include "elf/frv.h"
40 #include "osabi.h"
41 #include "infcall.h"
42 #include "frv-tdep.h"
43
44 extern void _initialize_frv_tdep (void);
45
46 static gdbarch_init_ftype frv_gdbarch_init;
47
48 static gdbarch_register_name_ftype frv_register_name;
49 static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc;
50 static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address;
51 static gdbarch_skip_prologue_ftype frv_skip_prologue;
52
53
54 struct frv_unwind_cache /* was struct frame_extra_info */
55 {
56 /* The previous frame's inner-most stack address. Used as this
57 frame ID's stack_addr. */
58 CORE_ADDR prev_sp;
59
60 /* The frame's base, optionally used by the high-level debug info. */
61 CORE_ADDR base;
62
63 /* Table indicating the location of each and every register. */
64 struct trad_frame_saved_reg *saved_regs;
65 };
66
67 /* A structure describing a particular variant of the FRV.
68 We allocate and initialize one of these structures when we create
69 the gdbarch object for a variant.
70
71 At the moment, all the FR variants we support differ only in which
72 registers are present; the portable code of GDB knows that
73 registers whose names are the empty string don't exist, so the
74 `register_names' array captures all the per-variant information we
75 need.
76
77 in the future, if we need to have per-variant maps for raw size,
78 virtual type, etc., we should replace register_names with an array
79 of structures, each of which gives all the necessary info for one
80 register. Don't stick parallel arrays in here --- that's so
81 Fortran. */
82 struct gdbarch_tdep
83 {
84 /* Which ABI is in use? */
85 enum frv_abi frv_abi;
86
87 /* How many general-purpose registers does this variant have? */
88 int num_gprs;
89
90 /* How many floating-point registers does this variant have? */
91 int num_fprs;
92
93 /* How many hardware watchpoints can it support? */
94 int num_hw_watchpoints;
95
96 /* How many hardware breakpoints can it support? */
97 int num_hw_breakpoints;
98
99 /* Register names. */
100 char **register_names;
101 };
102
103 #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
104
105 /* Return the FR-V ABI associated with GDBARCH. */
106 enum frv_abi
107 frv_abi (struct gdbarch *gdbarch)
108 {
109 return gdbarch_tdep (gdbarch)->frv_abi;
110 }
111
112 /* Fetch the interpreter and executable loadmap addresses (for shared
113 library support) for the FDPIC ABI. Return 0 if successful, -1 if
114 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
115 int
116 frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr,
117 CORE_ADDR *exec_addr)
118 {
119 if (frv_abi (gdbarch) != FRV_ABI_FDPIC)
120 return -1;
121 else
122 {
123 if (interp_addr != NULL)
124 {
125 ULONGEST val;
126 regcache_cooked_read_unsigned (current_regcache,
127 fdpic_loadmap_interp_regnum, &val);
128 *interp_addr = val;
129 }
130 if (exec_addr != NULL)
131 {
132 ULONGEST val;
133 regcache_cooked_read_unsigned (current_regcache,
134 fdpic_loadmap_exec_regnum, &val);
135 *exec_addr = val;
136 }
137 return 0;
138 }
139 }
140
141 /* Allocate a new variant structure, and set up default values for all
142 the fields. */
143 static struct gdbarch_tdep *
144 new_variant (void)
145 {
146 struct gdbarch_tdep *var;
147 int r;
148 char buf[20];
149
150 var = xmalloc (sizeof (*var));
151 memset (var, 0, sizeof (*var));
152
153 var->frv_abi = FRV_ABI_EABI;
154 var->num_gprs = 64;
155 var->num_fprs = 64;
156 var->num_hw_watchpoints = 0;
157 var->num_hw_breakpoints = 0;
158
159 /* By default, don't supply any general-purpose or floating-point
160 register names. */
161 var->register_names
162 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
163 * sizeof (char *));
164 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
165 var->register_names[r] = "";
166
167 /* Do, however, supply default names for the known special-purpose
168 registers. */
169
170 var->register_names[pc_regnum] = "pc";
171 var->register_names[lr_regnum] = "lr";
172 var->register_names[lcr_regnum] = "lcr";
173
174 var->register_names[psr_regnum] = "psr";
175 var->register_names[ccr_regnum] = "ccr";
176 var->register_names[cccr_regnum] = "cccr";
177 var->register_names[tbr_regnum] = "tbr";
178
179 /* Debug registers. */
180 var->register_names[brr_regnum] = "brr";
181 var->register_names[dbar0_regnum] = "dbar0";
182 var->register_names[dbar1_regnum] = "dbar1";
183 var->register_names[dbar2_regnum] = "dbar2";
184 var->register_names[dbar3_regnum] = "dbar3";
185
186 /* iacc0 (Only found on MB93405.) */
187 var->register_names[iacc0h_regnum] = "iacc0h";
188 var->register_names[iacc0l_regnum] = "iacc0l";
189 var->register_names[iacc0_regnum] = "iacc0";
190
191 /* fsr0 (Found on FR555 and FR501.) */
192 var->register_names[fsr0_regnum] = "fsr0";
193
194 /* acc0 - acc7. The architecture provides for the possibility of many
195 more (up to 64 total), but we don't want to make that big of a hole
196 in the G packet. If we need more in the future, we'll add them
197 elsewhere. */
198 for (r = acc0_regnum; r <= acc7_regnum; r++)
199 {
200 char *buf;
201 buf = xstrprintf ("acc%d", r - acc0_regnum);
202 var->register_names[r] = buf;
203 }
204
205 /* accg0 - accg7: These are one byte registers. The remote protocol
206 provides the raw values packed four into a slot. accg0123 and
207 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
208 We don't provide names for accg0123 and accg4567 since the user will
209 likely not want to see these raw values. */
210
211 for (r = accg0_regnum; r <= accg7_regnum; r++)
212 {
213 char *buf;
214 buf = xstrprintf ("accg%d", r - accg0_regnum);
215 var->register_names[r] = buf;
216 }
217
218 /* msr0 and msr1. */
219
220 var->register_names[msr0_regnum] = "msr0";
221 var->register_names[msr1_regnum] = "msr1";
222
223 /* gner and fner registers. */
224 var->register_names[gner0_regnum] = "gner0";
225 var->register_names[gner1_regnum] = "gner1";
226 var->register_names[fner0_regnum] = "fner0";
227 var->register_names[fner1_regnum] = "fner1";
228
229 return var;
230 }
231
232
233 /* Indicate that the variant VAR has NUM_GPRS general-purpose
234 registers, and fill in the names array appropriately. */
235 static void
236 set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
237 {
238 int r;
239
240 var->num_gprs = num_gprs;
241
242 for (r = 0; r < num_gprs; ++r)
243 {
244 char buf[20];
245
246 sprintf (buf, "gr%d", r);
247 var->register_names[first_gpr_regnum + r] = xstrdup (buf);
248 }
249 }
250
251
252 /* Indicate that the variant VAR has NUM_FPRS floating-point
253 registers, and fill in the names array appropriately. */
254 static void
255 set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
256 {
257 int r;
258
259 var->num_fprs = num_fprs;
260
261 for (r = 0; r < num_fprs; ++r)
262 {
263 char buf[20];
264
265 sprintf (buf, "fr%d", r);
266 var->register_names[first_fpr_regnum + r] = xstrdup (buf);
267 }
268 }
269
270 static void
271 set_variant_abi_fdpic (struct gdbarch_tdep *var)
272 {
273 var->frv_abi = FRV_ABI_FDPIC;
274 var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec");
275 var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp");
276 }
277
278 static void
279 set_variant_scratch_registers (struct gdbarch_tdep *var)
280 {
281 var->register_names[scr0_regnum] = xstrdup ("scr0");
282 var->register_names[scr1_regnum] = xstrdup ("scr1");
283 var->register_names[scr2_regnum] = xstrdup ("scr2");
284 var->register_names[scr3_regnum] = xstrdup ("scr3");
285 }
286
287 static const char *
288 frv_register_name (int reg)
289 {
290 if (reg < 0)
291 return "?toosmall?";
292 if (reg >= frv_num_regs + frv_num_pseudo_regs)
293 return "?toolarge?";
294
295 return CURRENT_VARIANT->register_names[reg];
296 }
297
298
299 static struct type *
300 frv_register_type (struct gdbarch *gdbarch, int reg)
301 {
302 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
303 return builtin_type_float;
304 else if (reg == iacc0_regnum)
305 return builtin_type_int64;
306 else
307 return builtin_type_int32;
308 }
309
310 static void
311 frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
312 int reg, gdb_byte *buffer)
313 {
314 if (reg == iacc0_regnum)
315 {
316 regcache_raw_read (regcache, iacc0h_regnum, buffer);
317 regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
318 }
319 else if (accg0_regnum <= reg && reg <= accg7_regnum)
320 {
321 /* The accg raw registers have four values in each slot with the
322 lowest register number occupying the first byte. */
323
324 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
325 int byte_num = (reg - accg0_regnum) % 4;
326 bfd_byte buf[4];
327
328 regcache_raw_read (regcache, raw_regnum, buf);
329 memset (buffer, 0, 4);
330 /* FR-V is big endian, so put the requested byte in the first byte
331 of the buffer allocated to hold the pseudo-register. */
332 ((bfd_byte *) buffer)[0] = buf[byte_num];
333 }
334 }
335
336 static void
337 frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
338 int reg, const gdb_byte *buffer)
339 {
340 if (reg == iacc0_regnum)
341 {
342 regcache_raw_write (regcache, iacc0h_regnum, buffer);
343 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
344 }
345 else if (accg0_regnum <= reg && reg <= accg7_regnum)
346 {
347 /* The accg raw registers have four values in each slot with the
348 lowest register number occupying the first byte. */
349
350 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
351 int byte_num = (reg - accg0_regnum) % 4;
352 char buf[4];
353
354 regcache_raw_read (regcache, raw_regnum, buf);
355 buf[byte_num] = ((bfd_byte *) buffer)[0];
356 regcache_raw_write (regcache, raw_regnum, buf);
357 }
358 }
359
360 static int
361 frv_register_sim_regno (int reg)
362 {
363 static const int spr_map[] =
364 {
365 H_SPR_PSR, /* psr_regnum */
366 H_SPR_CCR, /* ccr_regnum */
367 H_SPR_CCCR, /* cccr_regnum */
368 -1, /* fdpic_loadmap_exec_regnum */
369 -1, /* fdpic_loadmap_interp_regnum */
370 -1, /* 134 */
371 H_SPR_TBR, /* tbr_regnum */
372 H_SPR_BRR, /* brr_regnum */
373 H_SPR_DBAR0, /* dbar0_regnum */
374 H_SPR_DBAR1, /* dbar1_regnum */
375 H_SPR_DBAR2, /* dbar2_regnum */
376 H_SPR_DBAR3, /* dbar3_regnum */
377 H_SPR_SCR0, /* scr0_regnum */
378 H_SPR_SCR1, /* scr1_regnum */
379 H_SPR_SCR2, /* scr2_regnum */
380 H_SPR_SCR3, /* scr3_regnum */
381 H_SPR_LR, /* lr_regnum */
382 H_SPR_LCR, /* lcr_regnum */
383 H_SPR_IACC0H, /* iacc0h_regnum */
384 H_SPR_IACC0L, /* iacc0l_regnum */
385 H_SPR_FSR0, /* fsr0_regnum */
386 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
387 -1, /* acc0_regnum */
388 -1, /* acc1_regnum */
389 -1, /* acc2_regnum */
390 -1, /* acc3_regnum */
391 -1, /* acc4_regnum */
392 -1, /* acc5_regnum */
393 -1, /* acc6_regnum */
394 -1, /* acc7_regnum */
395 -1, /* acc0123_regnum */
396 -1, /* acc4567_regnum */
397 H_SPR_MSR0, /* msr0_regnum */
398 H_SPR_MSR1, /* msr1_regnum */
399 H_SPR_GNER0, /* gner0_regnum */
400 H_SPR_GNER1, /* gner1_regnum */
401 H_SPR_FNER0, /* fner0_regnum */
402 H_SPR_FNER1, /* fner1_regnum */
403 };
404
405 gdb_assert (reg >= 0 && reg < NUM_REGS);
406
407 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
408 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
409 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
410 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
411 else if (pc_regnum == reg)
412 return SIM_FRV_PC_REGNUM;
413 else if (reg >= first_spr_regnum
414 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
415 {
416 int spr_reg_offset = spr_map[reg - first_spr_regnum];
417
418 if (spr_reg_offset < 0)
419 return SIM_REGNO_DOES_NOT_EXIST;
420 else
421 return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
422 }
423
424 internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg);
425 }
426
427 static const unsigned char *
428 frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp)
429 {
430 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
431 *lenp = sizeof (breakpoint);
432 return breakpoint;
433 }
434
435 /* Define the maximum number of instructions which may be packed into a
436 bundle (VLIW instruction). */
437 static const int max_instrs_per_bundle = 8;
438
439 /* Define the size (in bytes) of an FR-V instruction. */
440 static const int frv_instr_size = 4;
441
442 /* Adjust a breakpoint's address to account for the FR-V architecture's
443 constraint that a break instruction must not appear as any but the
444 first instruction in the bundle. */
445 static CORE_ADDR
446 frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
447 {
448 int count = max_instrs_per_bundle;
449 CORE_ADDR addr = bpaddr - frv_instr_size;
450 CORE_ADDR func_start = get_pc_function_start (bpaddr);
451
452 /* Find the end of the previous packing sequence. This will be indicated
453 by either attempting to access some inaccessible memory or by finding
454 an instruction word whose packing bit is set to one. */
455 while (count-- > 0 && addr >= func_start)
456 {
457 char instr[frv_instr_size];
458 int status;
459
460 status = read_memory_nobpt (addr, instr, sizeof instr);
461
462 if (status != 0)
463 break;
464
465 /* This is a big endian architecture, so byte zero will have most
466 significant byte. The most significant bit of this byte is the
467 packing bit. */
468 if (instr[0] & 0x80)
469 break;
470
471 addr -= frv_instr_size;
472 }
473
474 if (count > 0)
475 bpaddr = addr + frv_instr_size;
476
477 return bpaddr;
478 }
479
480
481 /* Return true if REG is a caller-saves ("scratch") register,
482 false otherwise. */
483 static int
484 is_caller_saves_reg (int reg)
485 {
486 return ((4 <= reg && reg <= 7)
487 || (14 <= reg && reg <= 15)
488 || (32 <= reg && reg <= 47));
489 }
490
491
492 /* Return true if REG is a callee-saves register, false otherwise. */
493 static int
494 is_callee_saves_reg (int reg)
495 {
496 return ((16 <= reg && reg <= 31)
497 || (48 <= reg && reg <= 63));
498 }
499
500
501 /* Return true if REG is an argument register, false otherwise. */
502 static int
503 is_argument_reg (int reg)
504 {
505 return (8 <= reg && reg <= 13);
506 }
507
508 /* Scan an FR-V prologue, starting at PC, until frame->PC.
509 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
510 We assume FRAME's saved_regs array has already been allocated and cleared.
511 Return the first PC value after the prologue.
512
513 Note that, for unoptimized code, we almost don't need this function
514 at all; all arguments and locals live on the stack, so we just need
515 the FP to find everything. The catch: structures passed by value
516 have their addresses living in registers; they're never spilled to
517 the stack. So if you ever want to be able to get to these
518 arguments in any frame but the top, you'll need to do this serious
519 prologue analysis. */
520 static CORE_ADDR
521 frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame,
522 struct frv_unwind_cache *info)
523 {
524 /* When writing out instruction bitpatterns, we use the following
525 letters to label instruction fields:
526 P - The parallel bit. We don't use this.
527 J - The register number of GRj in the instruction description.
528 K - The register number of GRk in the instruction description.
529 I - The register number of GRi.
530 S - a signed imediate offset.
531 U - an unsigned immediate offset.
532
533 The dots below the numbers indicate where hex digit boundaries
534 fall, to make it easier to check the numbers. */
535
536 /* Non-zero iff we've seen the instruction that initializes the
537 frame pointer for this function's frame. */
538 int fp_set = 0;
539
540 /* If fp_set is non_zero, then this is the distance from
541 the stack pointer to frame pointer: fp = sp + fp_offset. */
542 int fp_offset = 0;
543
544 /* Total size of frame prior to any alloca operations. */
545 int framesize = 0;
546
547 /* Flag indicating if lr has been saved on the stack. */
548 int lr_saved_on_stack = 0;
549
550 /* The number of the general-purpose register we saved the return
551 address ("link register") in, or -1 if we haven't moved it yet. */
552 int lr_save_reg = -1;
553
554 /* Offset (from sp) at which lr has been saved on the stack. */
555
556 int lr_sp_offset = 0;
557
558 /* If gr_saved[i] is non-zero, then we've noticed that general
559 register i has been saved at gr_sp_offset[i] from the stack
560 pointer. */
561 char gr_saved[64];
562 int gr_sp_offset[64];
563
564 /* The address of the most recently scanned prologue instruction. */
565 CORE_ADDR last_prologue_pc;
566
567 /* The address of the next instruction. */
568 CORE_ADDR next_pc;
569
570 /* The upper bound to of the pc values to scan. */
571 CORE_ADDR lim_pc;
572
573 memset (gr_saved, 0, sizeof (gr_saved));
574
575 last_prologue_pc = pc;
576
577 /* Try to compute an upper limit (on how far to scan) based on the
578 line number info. */
579 lim_pc = skip_prologue_using_sal (pc);
580 /* If there's no line number info, lim_pc will be 0. In that case,
581 set the limit to be 100 instructions away from pc. Hopefully, this
582 will be far enough away to account for the entire prologue. Don't
583 worry about overshooting the end of the function. The scan loop
584 below contains some checks to avoid scanning unreasonably far. */
585 if (lim_pc == 0)
586 lim_pc = pc + 400;
587
588 /* If we have a frame, we don't want to scan past the frame's pc. This
589 will catch those cases where the pc is in the prologue. */
590 if (next_frame)
591 {
592 CORE_ADDR frame_pc = frame_pc_unwind (next_frame);
593 if (frame_pc < lim_pc)
594 lim_pc = frame_pc;
595 }
596
597 /* Scan the prologue. */
598 while (pc < lim_pc)
599 {
600 char buf[frv_instr_size];
601 LONGEST op;
602
603 if (target_read_memory (pc, buf, sizeof buf) != 0)
604 break;
605 op = extract_signed_integer (buf, sizeof buf);
606
607 next_pc = pc + 4;
608
609 /* The tests in this chain of ifs should be in order of
610 decreasing selectivity, so that more particular patterns get
611 to fire before less particular patterns. */
612
613 /* Some sort of control transfer instruction: stop scanning prologue.
614 Integer Conditional Branch:
615 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
616 Floating-point / media Conditional Branch:
617 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
618 LCR Conditional Branch to LR
619 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
620 Integer conditional Branches to LR
621 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
622 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
623 Floating-point/Media Branches to LR
624 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
625 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
626 Jump and Link
627 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
628 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
629 Call
630 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
631 Return from Trap
632 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
633 Integer Conditional Trap
634 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
635 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
636 Floating-point /media Conditional Trap
637 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
638 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
639 Break
640 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
641 Media Trap
642 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
643 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
644 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */
645 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
646 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
647 {
648 /* Stop scanning; not in prologue any longer. */
649 break;
650 }
651
652 /* Loading something from memory into fp probably means that
653 we're in the epilogue. Stop scanning the prologue.
654 ld @(GRi, GRk), fp
655 X 000010 0000010 XXXXXX 000100 XXXXXX
656 ldi @(GRi, d12), fp
657 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
658 else if ((op & 0x7ffc0fc0) == 0x04080100
659 || (op & 0x7ffc0000) == 0x04c80000)
660 {
661 break;
662 }
663
664 /* Setting the FP from the SP:
665 ori sp, 0, fp
666 P 000010 0100010 000001 000000000000 = 0x04881000
667 0 111111 1111111 111111 111111111111 = 0x7fffffff
668 . . . . . . . .
669 We treat this as part of the prologue. */
670 else if ((op & 0x7fffffff) == 0x04881000)
671 {
672 fp_set = 1;
673 fp_offset = 0;
674 last_prologue_pc = next_pc;
675 }
676
677 /* Move the link register to the scratch register grJ, before saving:
678 movsg lr, grJ
679 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
680 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
681 . . . . . . . .
682 We treat this as part of the prologue. */
683 else if ((op & 0x7fffffc0) == 0x080d01c0)
684 {
685 int gr_j = op & 0x3f;
686
687 /* If we're moving it to a scratch register, that's fine. */
688 if (is_caller_saves_reg (gr_j))
689 {
690 lr_save_reg = gr_j;
691 last_prologue_pc = next_pc;
692 }
693 }
694
695 /* To save multiple callee-saves registers on the stack, at
696 offset zero:
697
698 std grK,@(sp,gr0)
699 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
700 0 000000 1111111 111111 111111 111111 = 0x01ffffff
701
702 stq grK,@(sp,gr0)
703 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
704 0 000000 1111111 111111 111111 111111 = 0x01ffffff
705 . . . . . . . .
706 We treat this as part of the prologue, and record the register's
707 saved address in the frame structure. */
708 else if ((op & 0x01ffffff) == 0x000c10c0
709 || (op & 0x01ffffff) == 0x000c1100)
710 {
711 int gr_k = ((op >> 25) & 0x3f);
712 int ope = ((op >> 6) & 0x3f);
713 int count;
714 int i;
715
716 /* Is it an std or an stq? */
717 if (ope == 0x03)
718 count = 2;
719 else
720 count = 4;
721
722 /* Is it really a callee-saves register? */
723 if (is_callee_saves_reg (gr_k))
724 {
725 for (i = 0; i < count; i++)
726 {
727 gr_saved[gr_k + i] = 1;
728 gr_sp_offset[gr_k + i] = 4 * i;
729 }
730 last_prologue_pc = next_pc;
731 }
732 }
733
734 /* Adjusting the stack pointer. (The stack pointer is GR1.)
735 addi sp, S, sp
736 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
737 0 111111 1111111 111111 000000000000 = 0x7ffff000
738 . . . . . . . .
739 We treat this as part of the prologue. */
740 else if ((op & 0x7ffff000) == 0x02401000)
741 {
742 if (framesize == 0)
743 {
744 /* Sign-extend the twelve-bit field.
745 (Isn't there a better way to do this?) */
746 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
747
748 framesize -= s;
749 last_prologue_pc = pc;
750 }
751 else
752 {
753 /* If the prologue is being adjusted again, we've
754 likely gone too far; i.e. we're probably in the
755 epilogue. */
756 break;
757 }
758 }
759
760 /* Setting the FP to a constant distance from the SP:
761 addi sp, S, fp
762 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
763 0 111111 1111111 111111 000000000000 = 0x7ffff000
764 . . . . . . . .
765 We treat this as part of the prologue. */
766 else if ((op & 0x7ffff000) == 0x04401000)
767 {
768 /* Sign-extend the twelve-bit field.
769 (Isn't there a better way to do this?) */
770 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
771 fp_set = 1;
772 fp_offset = s;
773 last_prologue_pc = pc;
774 }
775
776 /* To spill an argument register to a scratch register:
777 ori GRi, 0, GRk
778 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
779 0 000000 1111111 000000 111111111111 = 0x01fc0fff
780 . . . . . . . .
781 For the time being, we treat this as a prologue instruction,
782 assuming that GRi is an argument register. This one's kind
783 of suspicious, because it seems like it could be part of a
784 legitimate body instruction. But we only come here when the
785 source info wasn't helpful, so we have to do the best we can.
786 Hopefully once GCC and GDB agree on how to emit line number
787 info for prologues, then this code will never come into play. */
788 else if ((op & 0x01fc0fff) == 0x00880000)
789 {
790 int gr_i = ((op >> 12) & 0x3f);
791
792 /* Make sure that the source is an arg register; if it is, we'll
793 treat it as a prologue instruction. */
794 if (is_argument_reg (gr_i))
795 last_prologue_pc = next_pc;
796 }
797
798 /* To spill 16-bit values to the stack:
799 sthi GRk, @(fp, s)
800 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
801 0 000000 1111111 111111 000000000000 = 0x01fff000
802 . . . . . . . .
803 And for 8-bit values, we use STB instructions.
804 stbi GRk, @(fp, s)
805 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
806 0 000000 1111111 111111 000000000000 = 0x01fff000
807 . . . . . . . .
808 We check that GRk is really an argument register, and treat
809 all such as part of the prologue. */
810 else if ( (op & 0x01fff000) == 0x01442000
811 || (op & 0x01fff000) == 0x01402000)
812 {
813 int gr_k = ((op >> 25) & 0x3f);
814
815 /* Make sure that GRk is really an argument register; treat
816 it as a prologue instruction if so. */
817 if (is_argument_reg (gr_k))
818 last_prologue_pc = next_pc;
819 }
820
821 /* To save multiple callee-saves register on the stack, at a
822 non-zero offset:
823
824 stdi GRk, @(sp, s)
825 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
826 0 000000 1111111 111111 000000000000 = 0x01fff000
827 . . . . . . . .
828 stqi GRk, @(sp, s)
829 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
830 0 000000 1111111 111111 000000000000 = 0x01fff000
831 . . . . . . . .
832 We treat this as part of the prologue, and record the register's
833 saved address in the frame structure. */
834 else if ((op & 0x01fff000) == 0x014c1000
835 || (op & 0x01fff000) == 0x01501000)
836 {
837 int gr_k = ((op >> 25) & 0x3f);
838 int count;
839 int i;
840
841 /* Is it a stdi or a stqi? */
842 if ((op & 0x01fff000) == 0x014c1000)
843 count = 2;
844 else
845 count = 4;
846
847 /* Is it really a callee-saves register? */
848 if (is_callee_saves_reg (gr_k))
849 {
850 /* Sign-extend the twelve-bit field.
851 (Isn't there a better way to do this?) */
852 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
853
854 for (i = 0; i < count; i++)
855 {
856 gr_saved[gr_k + i] = 1;
857 gr_sp_offset[gr_k + i] = s + (4 * i);
858 }
859 last_prologue_pc = next_pc;
860 }
861 }
862
863 /* Storing any kind of integer register at any constant offset
864 from any other register.
865
866 st GRk, @(GRi, gr0)
867 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
868 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
869 . . . . . . . .
870 sti GRk, @(GRi, d12)
871 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
872 0 000000 1111111 000000 000000000000 = 0x01fc0000
873 . . . . . . . .
874 These could be almost anything, but a lot of prologue
875 instructions fall into this pattern, so let's decode the
876 instruction once, and then work at a higher level. */
877 else if (((op & 0x01fc0fff) == 0x000c0080)
878 || ((op & 0x01fc0000) == 0x01480000))
879 {
880 int gr_k = ((op >> 25) & 0x3f);
881 int gr_i = ((op >> 12) & 0x3f);
882 int offset;
883
884 /* Are we storing with gr0 as an offset, or using an
885 immediate value? */
886 if ((op & 0x01fc0fff) == 0x000c0080)
887 offset = 0;
888 else
889 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
890
891 /* If the address isn't relative to the SP or FP, it's not a
892 prologue instruction. */
893 if (gr_i != sp_regnum && gr_i != fp_regnum)
894 {
895 /* Do nothing; not a prologue instruction. */
896 }
897
898 /* Saving the old FP in the new frame (relative to the SP). */
899 else if (gr_k == fp_regnum && gr_i == sp_regnum)
900 {
901 gr_saved[fp_regnum] = 1;
902 gr_sp_offset[fp_regnum] = offset;
903 last_prologue_pc = next_pc;
904 }
905
906 /* Saving callee-saves register(s) on the stack, relative to
907 the SP. */
908 else if (gr_i == sp_regnum
909 && is_callee_saves_reg (gr_k))
910 {
911 gr_saved[gr_k] = 1;
912 if (gr_i == sp_regnum)
913 gr_sp_offset[gr_k] = offset;
914 else
915 gr_sp_offset[gr_k] = offset + fp_offset;
916 last_prologue_pc = next_pc;
917 }
918
919 /* Saving the scratch register holding the return address. */
920 else if (lr_save_reg != -1
921 && gr_k == lr_save_reg)
922 {
923 lr_saved_on_stack = 1;
924 if (gr_i == sp_regnum)
925 lr_sp_offset = offset;
926 else
927 lr_sp_offset = offset + fp_offset;
928 last_prologue_pc = next_pc;
929 }
930
931 /* Spilling int-sized arguments to the stack. */
932 else if (is_argument_reg (gr_k))
933 last_prologue_pc = next_pc;
934 }
935 pc = next_pc;
936 }
937
938 if (next_frame && info)
939 {
940 int i;
941 ULONGEST this_base;
942
943 /* If we know the relationship between the stack and frame
944 pointers, record the addresses of the registers we noticed.
945 Note that we have to do this as a separate step at the end,
946 because instructions may save relative to the SP, but we need
947 their addresses relative to the FP. */
948 if (fp_set)
949 frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base);
950 else
951 frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base);
952
953 for (i = 0; i < 64; i++)
954 if (gr_saved[i])
955 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
956
957 info->prev_sp = this_base - fp_offset + framesize;
958 info->base = this_base;
959
960 /* If LR was saved on the stack, record its location. */
961 if (lr_saved_on_stack)
962 info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset;
963
964 /* The call instruction moves the caller's PC in the callee's LR.
965 Since this is an unwind, do the reverse. Copy the location of LR
966 into PC (the address / regnum) so that a request for PC will be
967 converted into a request for the LR. */
968 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
969
970 /* Save the previous frame's computed SP value. */
971 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
972 }
973
974 return last_prologue_pc;
975 }
976
977
978 static CORE_ADDR
979 frv_skip_prologue (CORE_ADDR pc)
980 {
981 CORE_ADDR func_addr, func_end, new_pc;
982
983 new_pc = pc;
984
985 /* If the line table has entry for a line *within* the function
986 (i.e., not in the prologue, and not past the end), then that's
987 our location. */
988 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
989 {
990 struct symtab_and_line sal;
991
992 sal = find_pc_line (func_addr, 0);
993
994 if (sal.line != 0 && sal.end < func_end)
995 {
996 new_pc = sal.end;
997 }
998 }
999
1000 /* The FR-V prologue is at least five instructions long (twenty bytes).
1001 If we didn't find a real source location past that, then
1002 do a full analysis of the prologue. */
1003 if (new_pc < pc + 20)
1004 new_pc = frv_analyze_prologue (pc, 0, 0);
1005
1006 return new_pc;
1007 }
1008
1009
1010 static struct frv_unwind_cache *
1011 frv_frame_unwind_cache (struct frame_info *next_frame,
1012 void **this_prologue_cache)
1013 {
1014 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1015 CORE_ADDR pc;
1016 ULONGEST this_base;
1017 struct frv_unwind_cache *info;
1018
1019 if ((*this_prologue_cache))
1020 return (*this_prologue_cache);
1021
1022 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
1023 (*this_prologue_cache) = info;
1024 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1025
1026 /* Prologue analysis does the rest... */
1027 frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info);
1028
1029 return info;
1030 }
1031
1032 static void
1033 frv_extract_return_value (struct type *type, struct regcache *regcache,
1034 gdb_byte *valbuf)
1035 {
1036 int len = TYPE_LENGTH (type);
1037
1038 if (len <= 4)
1039 {
1040 ULONGEST gpr8_val;
1041 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1042 store_unsigned_integer (valbuf, len, gpr8_val);
1043 }
1044 else if (len == 8)
1045 {
1046 ULONGEST regval;
1047 regcache_cooked_read_unsigned (regcache, 8, &regval);
1048 store_unsigned_integer (valbuf, 4, regval);
1049 regcache_cooked_read_unsigned (regcache, 9, &regval);
1050 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval);
1051 }
1052 else
1053 internal_error (__FILE__, __LINE__, _("Illegal return value length: %d"), len);
1054 }
1055
1056 static CORE_ADDR
1057 frv_extract_struct_value_address (struct regcache *regcache)
1058 {
1059 ULONGEST addr;
1060 regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr);
1061 return addr;
1062 }
1063
1064 static void
1065 frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
1066 {
1067 write_register (struct_return_regnum, addr);
1068 }
1069
1070 static CORE_ADDR
1071 frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1072 {
1073 /* Require dword alignment. */
1074 return align_down (sp, 8);
1075 }
1076
1077 static CORE_ADDR
1078 find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point)
1079 {
1080 CORE_ADDR descr;
1081 char valbuf[4];
1082 CORE_ADDR start_addr;
1083
1084 /* If we can't find the function in the symbol table, then we assume
1085 that the function address is already in descriptor form. */
1086 if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL)
1087 || entry_point != start_addr)
1088 return entry_point;
1089
1090 descr = frv_fdpic_find_canonical_descriptor (entry_point);
1091
1092 if (descr != 0)
1093 return descr;
1094
1095 /* Construct a non-canonical descriptor from space allocated on
1096 the stack. */
1097
1098 descr = value_as_long (value_allocate_space_in_inferior (8));
1099 store_unsigned_integer (valbuf, 4, entry_point);
1100 write_memory (descr, valbuf, 4);
1101 store_unsigned_integer (valbuf, 4,
1102 frv_fdpic_find_global_pointer (entry_point));
1103 write_memory (descr + 4, valbuf, 4);
1104 return descr;
1105 }
1106
1107 static CORE_ADDR
1108 frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
1109 struct target_ops *targ)
1110 {
1111 CORE_ADDR entry_point;
1112 CORE_ADDR got_address;
1113
1114 entry_point = get_target_memory_unsigned (targ, addr, 4);
1115 got_address = get_target_memory_unsigned (targ, addr + 4, 4);
1116
1117 if (got_address == frv_fdpic_find_global_pointer (entry_point))
1118 return entry_point;
1119 else
1120 return addr;
1121 }
1122
1123 static CORE_ADDR
1124 frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1125 struct regcache *regcache, CORE_ADDR bp_addr,
1126 int nargs, struct value **args, CORE_ADDR sp,
1127 int struct_return, CORE_ADDR struct_addr)
1128 {
1129 int argreg;
1130 int argnum;
1131 char *val;
1132 char valbuf[4];
1133 struct value *arg;
1134 struct type *arg_type;
1135 int len;
1136 enum type_code typecode;
1137 CORE_ADDR regval;
1138 int stack_space;
1139 int stack_offset;
1140 enum frv_abi abi = frv_abi (gdbarch);
1141 CORE_ADDR func_addr = find_function_addr (function, NULL);
1142
1143 #if 0
1144 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1145 nargs, (int) sp, struct_return, struct_addr);
1146 #endif
1147
1148 stack_space = 0;
1149 for (argnum = 0; argnum < nargs; ++argnum)
1150 stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
1151
1152 stack_space -= (6 * 4);
1153 if (stack_space > 0)
1154 sp -= stack_space;
1155
1156 /* Make sure stack is dword aligned. */
1157 sp = align_down (sp, 8);
1158
1159 stack_offset = 0;
1160
1161 argreg = 8;
1162
1163 if (struct_return)
1164 regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1165 struct_addr);
1166
1167 for (argnum = 0; argnum < nargs; ++argnum)
1168 {
1169 arg = args[argnum];
1170 arg_type = check_typedef (value_type (arg));
1171 len = TYPE_LENGTH (arg_type);
1172 typecode = TYPE_CODE (arg_type);
1173
1174 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1175 {
1176 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg));
1177 typecode = TYPE_CODE_PTR;
1178 len = 4;
1179 val = valbuf;
1180 }
1181 else if (abi == FRV_ABI_FDPIC
1182 && len == 4
1183 && typecode == TYPE_CODE_PTR
1184 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
1185 {
1186 /* The FDPIC ABI requires function descriptors to be passed instead
1187 of entry points. */
1188 store_unsigned_integer
1189 (valbuf, 4,
1190 find_func_descr (gdbarch,
1191 extract_unsigned_integer (value_contents (arg),
1192 4)));
1193 typecode = TYPE_CODE_PTR;
1194 len = 4;
1195 val = valbuf;
1196 }
1197 else
1198 {
1199 val = (char *) value_contents (arg);
1200 }
1201
1202 while (len > 0)
1203 {
1204 int partial_len = (len < 4 ? len : 4);
1205
1206 if (argreg < 14)
1207 {
1208 regval = extract_unsigned_integer (val, partial_len);
1209 #if 0
1210 printf(" Argnum %d data %x -> reg %d\n",
1211 argnum, (int) regval, argreg);
1212 #endif
1213 regcache_cooked_write_unsigned (regcache, argreg, regval);
1214 ++argreg;
1215 }
1216 else
1217 {
1218 #if 0
1219 printf(" Argnum %d data %x -> offset %d (%x)\n",
1220 argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
1221 #endif
1222 write_memory (sp + stack_offset, val, partial_len);
1223 stack_offset += align_up (partial_len, 4);
1224 }
1225 len -= partial_len;
1226 val += partial_len;
1227 }
1228 }
1229
1230 /* Set the return address. For the frv, the return breakpoint is
1231 always at BP_ADDR. */
1232 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1233
1234 if (abi == FRV_ABI_FDPIC)
1235 {
1236 /* Set the GOT register for the FDPIC ABI. */
1237 regcache_cooked_write_unsigned
1238 (regcache, first_gpr_regnum + 15,
1239 frv_fdpic_find_global_pointer (func_addr));
1240 }
1241
1242 /* Finally, update the SP register. */
1243 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1244
1245 return sp;
1246 }
1247
1248 static void
1249 frv_store_return_value (struct type *type, struct regcache *regcache,
1250 const gdb_byte *valbuf)
1251 {
1252 int len = TYPE_LENGTH (type);
1253
1254 if (len <= 4)
1255 {
1256 bfd_byte val[4];
1257 memset (val, 0, sizeof (val));
1258 memcpy (val + (4 - len), valbuf, len);
1259 regcache_cooked_write (regcache, 8, val);
1260 }
1261 else if (len == 8)
1262 {
1263 regcache_cooked_write (regcache, 8, valbuf);
1264 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1265 }
1266 else
1267 internal_error (__FILE__, __LINE__,
1268 _("Don't know how to return a %d-byte value."), len);
1269 }
1270
1271
1272 /* Hardware watchpoint / breakpoint support for the FR500
1273 and FR400. */
1274
1275 int
1276 frv_check_watch_resources (int type, int cnt, int ot)
1277 {
1278 struct gdbarch_tdep *var = CURRENT_VARIANT;
1279
1280 /* Watchpoints not supported on simulator. */
1281 if (strcmp (target_shortname, "sim") == 0)
1282 return 0;
1283
1284 if (type == bp_hardware_breakpoint)
1285 {
1286 if (var->num_hw_breakpoints == 0)
1287 return 0;
1288 else if (cnt <= var->num_hw_breakpoints)
1289 return 1;
1290 }
1291 else
1292 {
1293 if (var->num_hw_watchpoints == 0)
1294 return 0;
1295 else if (ot)
1296 return -1;
1297 else if (cnt <= var->num_hw_watchpoints)
1298 return 1;
1299 }
1300 return -1;
1301 }
1302
1303
1304 int
1305 frv_stopped_data_address (CORE_ADDR *addr_p)
1306 {
1307 CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
1308
1309 brr = read_register (brr_regnum);
1310 dbar0 = read_register (dbar0_regnum);
1311 dbar1 = read_register (dbar1_regnum);
1312 dbar2 = read_register (dbar2_regnum);
1313 dbar3 = read_register (dbar3_regnum);
1314
1315 if (brr & (1<<11))
1316 *addr_p = dbar0;
1317 else if (brr & (1<<10))
1318 *addr_p = dbar1;
1319 else if (brr & (1<<9))
1320 *addr_p = dbar2;
1321 else if (brr & (1<<8))
1322 *addr_p = dbar3;
1323 else
1324 return 0;
1325
1326 return 1;
1327 }
1328
1329 int
1330 frv_have_stopped_data_address (void)
1331 {
1332 CORE_ADDR addr = 0;
1333 return frv_stopped_data_address (&addr);
1334 }
1335
1336 static CORE_ADDR
1337 frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1338 {
1339 return frame_unwind_register_unsigned (next_frame, pc_regnum);
1340 }
1341
1342 /* Given a GDB frame, determine the address of the calling function's
1343 frame. This will be used to create a new GDB frame struct. */
1344
1345 static void
1346 frv_frame_this_id (struct frame_info *next_frame,
1347 void **this_prologue_cache, struct frame_id *this_id)
1348 {
1349 struct frv_unwind_cache *info
1350 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1351 CORE_ADDR base;
1352 CORE_ADDR func;
1353 struct minimal_symbol *msym_stack;
1354 struct frame_id id;
1355
1356 /* The FUNC is easy. */
1357 func = frame_func_unwind (next_frame);
1358
1359 /* Check if the stack is empty. */
1360 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1361 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1362 return;
1363
1364 /* Hopefully the prologue analysis either correctly determined the
1365 frame's base (which is the SP from the previous frame), or set
1366 that base to "NULL". */
1367 base = info->prev_sp;
1368 if (base == 0)
1369 return;
1370
1371 id = frame_id_build (base, func);
1372 (*this_id) = id;
1373 }
1374
1375 static void
1376 frv_frame_prev_register (struct frame_info *next_frame,
1377 void **this_prologue_cache,
1378 int regnum, int *optimizedp,
1379 enum lval_type *lvalp, CORE_ADDR *addrp,
1380 int *realnump, gdb_byte *bufferp)
1381 {
1382 struct frv_unwind_cache *info
1383 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1384 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
1385 optimizedp, lvalp, addrp, realnump, bufferp);
1386 }
1387
1388 static const struct frame_unwind frv_frame_unwind = {
1389 NORMAL_FRAME,
1390 frv_frame_this_id,
1391 frv_frame_prev_register
1392 };
1393
1394 static const struct frame_unwind *
1395 frv_frame_sniffer (struct frame_info *next_frame)
1396 {
1397 return &frv_frame_unwind;
1398 }
1399
1400 static CORE_ADDR
1401 frv_frame_base_address (struct frame_info *next_frame, void **this_cache)
1402 {
1403 struct frv_unwind_cache *info
1404 = frv_frame_unwind_cache (next_frame, this_cache);
1405 return info->base;
1406 }
1407
1408 static const struct frame_base frv_frame_base = {
1409 &frv_frame_unwind,
1410 frv_frame_base_address,
1411 frv_frame_base_address,
1412 frv_frame_base_address
1413 };
1414
1415 static CORE_ADDR
1416 frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1417 {
1418 return frame_unwind_register_unsigned (next_frame, sp_regnum);
1419 }
1420
1421
1422 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1423 dummy frame. The frame ID's base needs to match the TOS value
1424 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1425 breakpoint. */
1426
1427 static struct frame_id
1428 frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1429 {
1430 return frame_id_build (frv_unwind_sp (gdbarch, next_frame),
1431 frame_pc_unwind (next_frame));
1432 }
1433
1434 static struct gdbarch *
1435 frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1436 {
1437 struct gdbarch *gdbarch;
1438 struct gdbarch_tdep *var;
1439 int elf_flags = 0;
1440
1441 /* Check to see if we've already built an appropriate architecture
1442 object for this executable. */
1443 arches = gdbarch_list_lookup_by_info (arches, &info);
1444 if (arches)
1445 return arches->gdbarch;
1446
1447 /* Select the right tdep structure for this variant. */
1448 var = new_variant ();
1449 switch (info.bfd_arch_info->mach)
1450 {
1451 case bfd_mach_frv:
1452 case bfd_mach_frvsimple:
1453 case bfd_mach_fr500:
1454 case bfd_mach_frvtomcat:
1455 case bfd_mach_fr550:
1456 set_variant_num_gprs (var, 64);
1457 set_variant_num_fprs (var, 64);
1458 break;
1459
1460 case bfd_mach_fr400:
1461 case bfd_mach_fr450:
1462 set_variant_num_gprs (var, 32);
1463 set_variant_num_fprs (var, 32);
1464 break;
1465
1466 default:
1467 /* Never heard of this variant. */
1468 return 0;
1469 }
1470
1471 /* Extract the ELF flags, if available. */
1472 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1473 elf_flags = elf_elfheader (info.abfd)->e_flags;
1474
1475 if (elf_flags & EF_FRV_FDPIC)
1476 set_variant_abi_fdpic (var);
1477
1478 if (elf_flags & EF_FRV_CPU_FR450)
1479 set_variant_scratch_registers (var);
1480
1481 gdbarch = gdbarch_alloc (&info, var);
1482
1483 set_gdbarch_short_bit (gdbarch, 16);
1484 set_gdbarch_int_bit (gdbarch, 32);
1485 set_gdbarch_long_bit (gdbarch, 32);
1486 set_gdbarch_long_long_bit (gdbarch, 64);
1487 set_gdbarch_float_bit (gdbarch, 32);
1488 set_gdbarch_double_bit (gdbarch, 64);
1489 set_gdbarch_long_double_bit (gdbarch, 64);
1490 set_gdbarch_ptr_bit (gdbarch, 32);
1491
1492 set_gdbarch_num_regs (gdbarch, frv_num_regs);
1493 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1494
1495 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1496 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
1497 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1498
1499 set_gdbarch_register_name (gdbarch, frv_register_name);
1500 set_gdbarch_register_type (gdbarch, frv_register_type);
1501 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
1502
1503 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1504 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1505
1506 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1507 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
1508 set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address);
1509
1510 set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention);
1511 set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value);
1512
1513 set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return);
1514 set_gdbarch_store_return_value (gdbarch, frv_store_return_value);
1515 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address);
1516
1517 /* Frame stuff. */
1518 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1519 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1520 set_gdbarch_frame_align (gdbarch, frv_frame_align);
1521 frame_base_set_default (gdbarch, &frv_frame_base);
1522 /* We set the sniffer lower down after the OSABI hooks have been
1523 established. */
1524
1525 /* Settings for calling functions in the inferior. */
1526 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1527 set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id);
1528
1529 /* Settings that should be unnecessary. */
1530 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1531
1532 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
1533
1534 set_gdbarch_remote_translate_xfer_address
1535 (gdbarch, generic_remote_translate_xfer_address);
1536
1537 /* Hardware watchpoint / breakpoint support. */
1538 switch (info.bfd_arch_info->mach)
1539 {
1540 case bfd_mach_frv:
1541 case bfd_mach_frvsimple:
1542 case bfd_mach_fr500:
1543 case bfd_mach_frvtomcat:
1544 /* fr500-style hardware debugging support. */
1545 var->num_hw_watchpoints = 4;
1546 var->num_hw_breakpoints = 4;
1547 break;
1548
1549 case bfd_mach_fr400:
1550 case bfd_mach_fr450:
1551 /* fr400-style hardware debugging support. */
1552 var->num_hw_watchpoints = 2;
1553 var->num_hw_breakpoints = 4;
1554 break;
1555
1556 default:
1557 /* Otherwise, assume we don't have hardware debugging support. */
1558 var->num_hw_watchpoints = 0;
1559 var->num_hw_breakpoints = 0;
1560 break;
1561 }
1562
1563 set_gdbarch_print_insn (gdbarch, print_insn_frv);
1564 if (frv_abi (gdbarch) == FRV_ABI_FDPIC)
1565 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
1566 frv_convert_from_func_ptr_addr);
1567
1568 /* Hook in ABI-specific overrides, if they have been registered. */
1569 gdbarch_init_osabi (info, gdbarch);
1570
1571 /* Set the fallback (prologue based) frame sniffer. */
1572 frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer);
1573
1574 /* Enable TLS support. */
1575 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1576 frv_fetch_objfile_link_map);
1577
1578 return gdbarch;
1579 }
1580
1581 void
1582 _initialize_frv_tdep (void)
1583 {
1584 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);
1585 }