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Add AVX512 registers support to GDB and GDBserver.
[thirdparty/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "doublest.h"
22 #include "floatformat.h"
23 #include "frame.h"
24 #include "gdbcore.h"
25 #include "inferior.h"
26 #include "language.h"
27 #include "regcache.h"
28 #include "value.h"
29
30 #include "gdb_assert.h"
31 #include <string.h>
32
33 #include "i386-tdep.h"
34 #include "i387-tdep.h"
35 #include "i386-xstate.h"
36
37 /* Print the floating point number specified by RAW. */
38
39 static void
40 print_i387_value (struct gdbarch *gdbarch,
41 const gdb_byte *raw, struct ui_file *file)
42 {
43 DOUBLEST value;
44
45 /* Using extract_typed_floating here might affect the representation
46 of certain numbers such as NaNs, even if GDB is running natively.
47 This is fine since our caller already detects such special
48 numbers and we print the hexadecimal representation anyway. */
49 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
50
51 /* We try to print 19 digits. The last digit may or may not contain
52 garbage, but we'd better print one too many. We need enough room
53 to print the value, 1 position for the sign, 1 for the decimal
54 point, 19 for the digits and 6 for the exponent adds up to 27. */
55 #ifdef PRINTF_HAS_LONG_DOUBLE
56 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
57 #else
58 fprintf_filtered (file, " %-+27.19g", (double) value);
59 #endif
60 }
61
62 /* Print the classification for the register contents RAW. */
63
64 static void
65 print_i387_ext (struct gdbarch *gdbarch,
66 const gdb_byte *raw, struct ui_file *file)
67 {
68 int sign;
69 int integer;
70 unsigned int exponent;
71 unsigned long fraction[2];
72
73 sign = raw[9] & 0x80;
74 integer = raw[7] & 0x80;
75 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
76 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
77 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
78 | (raw[5] << 8) | raw[4]);
79
80 if (exponent == 0x7fff && integer)
81 {
82 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
83 /* Infinity. */
84 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
85 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
86 /* Real Indefinite (QNaN). */
87 fputs_unfiltered (" Real Indefinite (QNaN)", file);
88 else if (fraction[1] & 0x40000000)
89 /* QNaN. */
90 fputs_filtered (" QNaN", file);
91 else
92 /* SNaN. */
93 fputs_filtered (" SNaN", file);
94 }
95 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
96 /* Normal. */
97 print_i387_value (gdbarch, raw, file);
98 else if (exponent == 0x0000)
99 {
100 /* Denormal or zero. */
101 print_i387_value (gdbarch, raw, file);
102
103 if (integer)
104 /* Pseudo-denormal. */
105 fputs_filtered (" Pseudo-denormal", file);
106 else if (fraction[0] || fraction[1])
107 /* Denormal. */
108 fputs_filtered (" Denormal", file);
109 }
110 else
111 /* Unsupported. */
112 fputs_filtered (" Unsupported", file);
113 }
114
115 /* Print the status word STATUS. If STATUS_P is false, then STATUS
116 was unavailable. */
117
118 static void
119 print_i387_status_word (int status_p,
120 unsigned int status, struct ui_file *file)
121 {
122 fprintf_filtered (file, "Status Word: ");
123 if (!status_p)
124 {
125 fprintf_filtered (file, "%s\n", _("<unavailable>"));
126 return;
127 }
128
129 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
130 fputs_filtered (" ", file);
131 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
132 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
133 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
134 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
135 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
136 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
137 fputs_filtered (" ", file);
138 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
139 fputs_filtered (" ", file);
140 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
141 fputs_filtered (" ", file);
142 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
143 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
144 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
145 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
146
147 fputs_filtered ("\n", file);
148
149 fprintf_filtered (file,
150 " TOP: %d\n", ((status >> 11) & 7));
151 }
152
153 /* Print the control word CONTROL. If CONTROL_P is false, then
154 CONTROL was unavailable. */
155
156 static void
157 print_i387_control_word (int control_p,
158 unsigned int control, struct ui_file *file)
159 {
160 fprintf_filtered (file, "Control Word: ");
161 if (!control_p)
162 {
163 fprintf_filtered (file, "%s\n", _("<unavailable>"));
164 return;
165 }
166
167 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
168 fputs_filtered (" ", file);
169 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
170 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
171 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
172 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
173 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
174 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
175
176 fputs_filtered ("\n", file);
177
178 fputs_filtered (" PC: ", file);
179 switch ((control >> 8) & 3)
180 {
181 case 0:
182 fputs_filtered ("Single Precision (24-bits)\n", file);
183 break;
184 case 1:
185 fputs_filtered ("Reserved\n", file);
186 break;
187 case 2:
188 fputs_filtered ("Double Precision (53-bits)\n", file);
189 break;
190 case 3:
191 fputs_filtered ("Extended Precision (64-bits)\n", file);
192 break;
193 }
194
195 fputs_filtered (" RC: ", file);
196 switch ((control >> 10) & 3)
197 {
198 case 0:
199 fputs_filtered ("Round to nearest\n", file);
200 break;
201 case 1:
202 fputs_filtered ("Round down\n", file);
203 break;
204 case 2:
205 fputs_filtered ("Round up\n", file);
206 break;
207 case 3:
208 fputs_filtered ("Round toward zero\n", file);
209 break;
210 }
211 }
212
213 /* Print out the i387 floating point state. Note that we ignore FRAME
214 in the code below. That's OK since floating-point registers are
215 never saved on the stack. */
216
217 void
218 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
219 struct frame_info *frame, const char *args)
220 {
221 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
222 ULONGEST fctrl;
223 int fctrl_p;
224 ULONGEST fstat;
225 int fstat_p;
226 ULONGEST ftag;
227 int ftag_p;
228 ULONGEST fiseg;
229 int fiseg_p;
230 ULONGEST fioff;
231 int fioff_p;
232 ULONGEST foseg;
233 int foseg_p;
234 ULONGEST fooff;
235 int fooff_p;
236 ULONGEST fop;
237 int fop_p;
238 int fpreg;
239 int top;
240
241 gdb_assert (gdbarch == get_frame_arch (frame));
242
243 fctrl_p = read_frame_register_unsigned (frame,
244 I387_FCTRL_REGNUM (tdep), &fctrl);
245 fstat_p = read_frame_register_unsigned (frame,
246 I387_FSTAT_REGNUM (tdep), &fstat);
247 ftag_p = read_frame_register_unsigned (frame,
248 I387_FTAG_REGNUM (tdep), &ftag);
249 fiseg_p = read_frame_register_unsigned (frame,
250 I387_FISEG_REGNUM (tdep), &fiseg);
251 fioff_p = read_frame_register_unsigned (frame,
252 I387_FIOFF_REGNUM (tdep), &fioff);
253 foseg_p = read_frame_register_unsigned (frame,
254 I387_FOSEG_REGNUM (tdep), &foseg);
255 fooff_p = read_frame_register_unsigned (frame,
256 I387_FOOFF_REGNUM (tdep), &fooff);
257 fop_p = read_frame_register_unsigned (frame,
258 I387_FOP_REGNUM (tdep), &fop);
259
260 if (fstat_p)
261 {
262 top = ((fstat >> 11) & 7);
263
264 for (fpreg = 7; fpreg >= 0; fpreg--)
265 {
266 struct value *regval;
267 int regnum;
268 int i;
269 int tag = -1;
270
271 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
272
273 if (ftag_p)
274 {
275 tag = (ftag >> (fpreg * 2)) & 3;
276
277 switch (tag)
278 {
279 case 0:
280 fputs_filtered ("Valid ", file);
281 break;
282 case 1:
283 fputs_filtered ("Zero ", file);
284 break;
285 case 2:
286 fputs_filtered ("Special ", file);
287 break;
288 case 3:
289 fputs_filtered ("Empty ", file);
290 break;
291 }
292 }
293 else
294 fputs_filtered ("Unknown ", file);
295
296 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
297 regval = get_frame_register_value (frame, regnum);
298
299 if (value_entirely_available (regval))
300 {
301 const gdb_byte *raw = value_contents (regval);
302
303 fputs_filtered ("0x", file);
304 for (i = 9; i >= 0; i--)
305 fprintf_filtered (file, "%02x", raw[i]);
306
307 if (tag != -1 && tag != 3)
308 print_i387_ext (gdbarch, raw, file);
309 }
310 else
311 fprintf_filtered (file, "%s", _("<unavailable>"));
312
313 fputs_filtered ("\n", file);
314 }
315 }
316
317 fputs_filtered ("\n", file);
318 print_i387_status_word (fstat_p, fstat, file);
319 print_i387_control_word (fctrl_p, fctrl, file);
320 fprintf_filtered (file, "Tag Word: %s\n",
321 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
322 fprintf_filtered (file, "Instruction Pointer: %s:",
323 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
324 fprintf_filtered (file, "%s\n",
325 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
326 fprintf_filtered (file, "Operand Pointer: %s:",
327 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
328 fprintf_filtered (file, "%s\n",
329 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
330 fprintf_filtered (file, "Opcode: %s\n",
331 fop_p
332 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
333 : _("<unavailable>"));
334 }
335 \f
336
337 /* Return nonzero if a value of type TYPE stored in register REGNUM
338 needs any special handling. */
339
340 int
341 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
342 struct type *type)
343 {
344 if (i386_fp_regnum_p (gdbarch, regnum))
345 {
346 /* Floating point registers must be converted unless we are
347 accessing them in their hardware type. */
348 if (type == i387_ext_type (gdbarch))
349 return 0;
350 else
351 return 1;
352 }
353
354 return 0;
355 }
356
357 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
358 return its contents in TO. */
359
360 int
361 i387_register_to_value (struct frame_info *frame, int regnum,
362 struct type *type, gdb_byte *to,
363 int *optimizedp, int *unavailablep)
364 {
365 struct gdbarch *gdbarch = get_frame_arch (frame);
366 gdb_byte from[I386_MAX_REGISTER_SIZE];
367
368 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
369
370 /* We only support floating-point values. */
371 if (TYPE_CODE (type) != TYPE_CODE_FLT)
372 {
373 warning (_("Cannot convert floating-point register value "
374 "to non-floating-point type."));
375 *optimizedp = *unavailablep = 0;
376 return 0;
377 }
378
379 /* Convert to TYPE. */
380 if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type),
381 from, optimizedp, unavailablep))
382 return 0;
383
384 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
385 *optimizedp = *unavailablep = 0;
386 return 1;
387 }
388
389 /* Write the contents FROM of a value of type TYPE into register
390 REGNUM in frame FRAME. */
391
392 void
393 i387_value_to_register (struct frame_info *frame, int regnum,
394 struct type *type, const gdb_byte *from)
395 {
396 struct gdbarch *gdbarch = get_frame_arch (frame);
397 gdb_byte to[I386_MAX_REGISTER_SIZE];
398
399 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
400
401 /* We only support floating-point values. */
402 if (TYPE_CODE (type) != TYPE_CODE_FLT)
403 {
404 warning (_("Cannot convert non-floating-point type "
405 "to floating-point register value."));
406 return;
407 }
408
409 /* Convert from TYPE. */
410 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
411 put_frame_register (frame, regnum, to);
412 }
413 \f
414
415 /* Handle FSAVE and FXSAVE formats. */
416
417 /* At fsave_offset[REGNUM] you'll find the offset to the location in
418 the data structure used by the "fsave" instruction where GDB
419 register REGNUM is stored. */
420
421 static int fsave_offset[] =
422 {
423 28 + 0 * 10, /* %st(0) ... */
424 28 + 1 * 10,
425 28 + 2 * 10,
426 28 + 3 * 10,
427 28 + 4 * 10,
428 28 + 5 * 10,
429 28 + 6 * 10,
430 28 + 7 * 10, /* ... %st(7). */
431 0, /* `fctrl' (16 bits). */
432 4, /* `fstat' (16 bits). */
433 8, /* `ftag' (16 bits). */
434 16, /* `fiseg' (16 bits). */
435 12, /* `fioff'. */
436 24, /* `foseg' (16 bits). */
437 20, /* `fooff'. */
438 18 /* `fop' (bottom 11 bits). */
439 };
440
441 #define FSAVE_ADDR(tdep, fsave, regnum) \
442 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
443 \f
444
445 /* Fill register REGNUM in REGCACHE with the appropriate value from
446 *FSAVE. This function masks off any of the reserved bits in
447 *FSAVE. */
448
449 void
450 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
451 {
452 struct gdbarch *gdbarch = get_regcache_arch (regcache);
453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
454 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
455 const gdb_byte *regs = fsave;
456 int i;
457
458 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
459
460 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
461 if (regnum == -1 || regnum == i)
462 {
463 if (fsave == NULL)
464 {
465 regcache_raw_supply (regcache, i, NULL);
466 continue;
467 }
468
469 /* Most of the FPU control registers occupy only 16 bits in the
470 fsave area. Give those a special treatment. */
471 if (i >= I387_FCTRL_REGNUM (tdep)
472 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
473 {
474 gdb_byte val[4];
475
476 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
477 val[2] = val[3] = 0;
478 if (i == I387_FOP_REGNUM (tdep))
479 val[1] &= ((1 << 3) - 1);
480 regcache_raw_supply (regcache, i, val);
481 }
482 else
483 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
484 }
485
486 /* Provide dummy values for the SSE registers. */
487 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
488 if (regnum == -1 || regnum == i)
489 regcache_raw_supply (regcache, i, NULL);
490 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
491 {
492 gdb_byte buf[4];
493
494 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
495 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
496 }
497 }
498
499 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
500 with the value from REGCACHE. If REGNUM is -1, do this for all
501 registers. This function doesn't touch any of the reserved bits in
502 *FSAVE. */
503
504 void
505 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
506 {
507 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
508 gdb_byte *regs = fsave;
509 int i;
510
511 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
512
513 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
514 if (regnum == -1 || regnum == i)
515 {
516 /* Most of the FPU control registers occupy only 16 bits in
517 the fsave area. Give those a special treatment. */
518 if (i >= I387_FCTRL_REGNUM (tdep)
519 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
520 {
521 gdb_byte buf[4];
522
523 regcache_raw_collect (regcache, i, buf);
524
525 if (i == I387_FOP_REGNUM (tdep))
526 {
527 /* The opcode occupies only 11 bits. Make sure we
528 don't touch the other bits. */
529 buf[1] &= ((1 << 3) - 1);
530 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
531 }
532 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
533 }
534 else
535 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
536 }
537 }
538 \f
539
540 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
541 the data structure used by the "fxsave" instruction where GDB
542 register REGNUM is stored. */
543
544 static int fxsave_offset[] =
545 {
546 32, /* %st(0) through ... */
547 48,
548 64,
549 80,
550 96,
551 112,
552 128,
553 144, /* ... %st(7) (80 bits each). */
554 0, /* `fctrl' (16 bits). */
555 2, /* `fstat' (16 bits). */
556 4, /* `ftag' (16 bits). */
557 12, /* `fiseg' (16 bits). */
558 8, /* `fioff'. */
559 20, /* `foseg' (16 bits). */
560 16, /* `fooff'. */
561 6, /* `fop' (bottom 11 bits). */
562 160 + 0 * 16, /* %xmm0 through ... */
563 160 + 1 * 16,
564 160 + 2 * 16,
565 160 + 3 * 16,
566 160 + 4 * 16,
567 160 + 5 * 16,
568 160 + 6 * 16,
569 160 + 7 * 16,
570 160 + 8 * 16,
571 160 + 9 * 16,
572 160 + 10 * 16,
573 160 + 11 * 16,
574 160 + 12 * 16,
575 160 + 13 * 16,
576 160 + 14 * 16,
577 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
578 };
579
580 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
581 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
582
583 /* We made an unfortunate choice in putting %mxcsr after the SSE
584 registers %xmm0-%xmm7 instead of before, since it makes supporting
585 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
586 don't include the offset for %mxcsr here above. */
587
588 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
589
590 static int i387_tag (const gdb_byte *raw);
591 \f
592
593 /* Fill register REGNUM in REGCACHE with the appropriate
594 floating-point or SSE register value from *FXSAVE. This function
595 masks off any of the reserved bits in *FXSAVE. */
596
597 void
598 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
599 {
600 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
601 const gdb_byte *regs = fxsave;
602 int i;
603
604 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
605 gdb_assert (tdep->num_xmm_regs > 0);
606
607 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
608 if (regnum == -1 || regnum == i)
609 {
610 if (regs == NULL)
611 {
612 regcache_raw_supply (regcache, i, NULL);
613 continue;
614 }
615
616 /* Most of the FPU control registers occupy only 16 bits in
617 the fxsave area. Give those a special treatment. */
618 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
619 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
620 {
621 gdb_byte val[4];
622
623 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
624 val[2] = val[3] = 0;
625 if (i == I387_FOP_REGNUM (tdep))
626 val[1] &= ((1 << 3) - 1);
627 else if (i== I387_FTAG_REGNUM (tdep))
628 {
629 /* The fxsave area contains a simplified version of
630 the tag word. We have to look at the actual 80-bit
631 FP data to recreate the traditional i387 tag word. */
632
633 unsigned long ftag = 0;
634 int fpreg;
635 int top;
636
637 top = ((FXSAVE_ADDR (tdep, regs,
638 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
639 top &= 0x7;
640
641 for (fpreg = 7; fpreg >= 0; fpreg--)
642 {
643 int tag;
644
645 if (val[0] & (1 << fpreg))
646 {
647 int thisreg = (fpreg + 8 - top) % 8
648 + I387_ST0_REGNUM (tdep);
649 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
650 }
651 else
652 tag = 3; /* Empty */
653
654 ftag |= tag << (2 * fpreg);
655 }
656 val[0] = ftag & 0xff;
657 val[1] = (ftag >> 8) & 0xff;
658 }
659 regcache_raw_supply (regcache, i, val);
660 }
661 else
662 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
663 }
664
665 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
666 {
667 if (regs == NULL)
668 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
669 else
670 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
671 FXSAVE_MXCSR_ADDR (regs));
672 }
673 }
674
675 /* Fill register REGNUM (if it is a floating-point or SSE register) in
676 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
677 all registers. This function doesn't touch any of the reserved
678 bits in *FXSAVE. */
679
680 void
681 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
682 {
683 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
684 gdb_byte *regs = fxsave;
685 int i;
686
687 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
688 gdb_assert (tdep->num_xmm_regs > 0);
689
690 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
691 if (regnum == -1 || regnum == i)
692 {
693 /* Most of the FPU control registers occupy only 16 bits in
694 the fxsave area. Give those a special treatment. */
695 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
696 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
697 {
698 gdb_byte buf[4];
699
700 regcache_raw_collect (regcache, i, buf);
701
702 if (i == I387_FOP_REGNUM (tdep))
703 {
704 /* The opcode occupies only 11 bits. Make sure we
705 don't touch the other bits. */
706 buf[1] &= ((1 << 3) - 1);
707 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
708 }
709 else if (i == I387_FTAG_REGNUM (tdep))
710 {
711 /* Converting back is much easier. */
712
713 unsigned short ftag;
714 int fpreg;
715
716 ftag = (buf[1] << 8) | buf[0];
717 buf[0] = 0;
718 buf[1] = 0;
719
720 for (fpreg = 7; fpreg >= 0; fpreg--)
721 {
722 int tag = (ftag >> (fpreg * 2)) & 3;
723
724 if (tag != 3)
725 buf[0] |= (1 << fpreg);
726 }
727 }
728 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
729 }
730 else
731 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
732 }
733
734 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
735 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
736 FXSAVE_MXCSR_ADDR (regs));
737 }
738
739 /* `xstate_bv' is at byte offset 512. */
740 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
741
742 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
743 the upper 128bit of AVX register data structure used by the "xsave"
744 instruction where GDB register REGNUM is stored. */
745
746 static int xsave_avxh_offset[] =
747 {
748 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
749 576 + 1 * 16,
750 576 + 2 * 16,
751 576 + 3 * 16,
752 576 + 4 * 16,
753 576 + 5 * 16,
754 576 + 6 * 16,
755 576 + 7 * 16,
756 576 + 8 * 16,
757 576 + 9 * 16,
758 576 + 10 * 16,
759 576 + 11 * 16,
760 576 + 12 * 16,
761 576 + 13 * 16,
762 576 + 14 * 16,
763 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
764 };
765
766 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
767 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
768
769 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
770 the upper 128bit of ZMM register data structure used by the "xsave"
771 instruction where GDB register REGNUM is stored. */
772
773 static int xsave_ymm_avx512_offset[] =
774 {
775 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
776 1664 + 16 + 0 * 64, /* %ymm16 through... */
777 1664 + 16 + 1 * 64,
778 1664 + 16 + 2 * 64,
779 1664 + 16 + 3 * 64,
780 1664 + 16 + 4 * 64,
781 1664 + 16 + 5 * 64,
782 1664 + 16 + 6 * 64,
783 1664 + 16 + 7 * 64,
784 1664 + 16 + 8 * 64,
785 1664 + 16 + 9 * 64,
786 1664 + 16 + 10 * 64,
787 1664 + 16 + 11 * 64,
788 1664 + 16 + 12 * 64,
789 1664 + 16 + 13 * 64,
790 1664 + 16 + 14 * 64,
791 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
792 };
793
794 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
795 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
796
797 static int xsave_xmm_avx512_offset[] =
798 {
799 1664 + 0 * 64, /* %ymm16 through... */
800 1664 + 1 * 64,
801 1664 + 2 * 64,
802 1664 + 3 * 64,
803 1664 + 4 * 64,
804 1664 + 5 * 64,
805 1664 + 6 * 64,
806 1664 + 7 * 64,
807 1664 + 8 * 64,
808 1664 + 9 * 64,
809 1664 + 10 * 64,
810 1664 + 11 * 64,
811 1664 + 12 * 64,
812 1664 + 13 * 64,
813 1664 + 14 * 64,
814 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
815 };
816
817 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
818 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
819
820 static int xsave_mpx_offset[] = {
821 960 + 0 * 16, /* bnd0r...bnd3r registers. */
822 960 + 1 * 16,
823 960 + 2 * 16,
824 960 + 3 * 16,
825 1024 + 0 * 8, /* bndcfg ... bndstatus. */
826 1024 + 1 * 8,
827 };
828
829 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
830 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
831
832 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
833 of the AVX512 opmask register data structure used by the "xsave"
834 instruction where GDB register REGNUM is stored. */
835
836 static int xsave_avx512_k_offset[] =
837 {
838 1088 + 0 * 8, /* %k0 through... */
839 1088 + 1 * 8,
840 1088 + 2 * 8,
841 1088 + 3 * 8,
842 1088 + 4 * 8,
843 1088 + 5 * 8,
844 1088 + 6 * 8,
845 1088 + 7 * 8 /* %k7 (64 bits each). */
846 };
847
848 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
849 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
850
851 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
852 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
853 instruction where GDB register REGNUM is stored. */
854
855 static int xsave_avx512_zmm_h_offset[] =
856 {
857 1152 + 0 * 32,
858 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
859 1152 + 2 * 32,
860 1152 + 3 * 32,
861 1152 + 4 * 32,
862 1152 + 5 * 32,
863 1152 + 6 * 32,
864 1152 + 7 * 32,
865 1152 + 8 * 32,
866 1152 + 9 * 32,
867 1152 + 10 * 32,
868 1152 + 11 * 32,
869 1152 + 12 * 32,
870 1152 + 13 * 32,
871 1152 + 14 * 32,
872 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
873 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
874 1664 + 32 + 1 * 64,
875 1664 + 32 + 2 * 64,
876 1664 + 32 + 3 * 64,
877 1664 + 32 + 4 * 64,
878 1664 + 32 + 5 * 64,
879 1664 + 32 + 6 * 64,
880 1664 + 32 + 7 * 64,
881 1664 + 32 + 8 * 64,
882 1664 + 32 + 9 * 64,
883 1664 + 32 + 10 * 64,
884 1664 + 32 + 11 * 64,
885 1664 + 32 + 12 * 64,
886 1664 + 32 + 13 * 64,
887 1664 + 32 + 14 * 64,
888 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
889 };
890
891 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
892 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
893
894 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
895
896 void
897 i387_supply_xsave (struct regcache *regcache, int regnum,
898 const void *xsave)
899 {
900 struct gdbarch *gdbarch = get_regcache_arch (regcache);
901 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
902 const gdb_byte *regs = xsave;
903 int i;
904 unsigned int clear_bv;
905 static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 };
906 enum
907 {
908 none = 0x0,
909 x87 = 0x1,
910 sse = 0x2,
911 avxh = 0x4,
912 mpx = 0x8,
913 avx512_k = 0x10,
914 avx512_zmm_h = 0x20,
915 avx512_ymmh_avx512 = 0x40,
916 avx512_xmm_avx512 = 0x80,
917 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
918 | avx512_ymmh_avx512 | avx512_xmm_avx512
919 } regclass;
920
921 gdb_assert (regs != NULL);
922 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
923 gdb_assert (tdep->num_xmm_regs > 0);
924
925 if (regnum == -1)
926 regclass = all;
927 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
928 && regnum < I387_ZMMENDH_REGNUM (tdep))
929 regclass = avx512_zmm_h;
930 else if (regnum >= I387_K0_REGNUM (tdep)
931 && regnum < I387_KEND_REGNUM (tdep))
932 regclass = avx512_k;
933 else if (regnum >= I387_YMM16H_REGNUM (tdep)
934 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
935 regclass = avx512_ymmh_avx512;
936 else if (regnum >= I387_XMM16_REGNUM (tdep)
937 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
938 regclass = avx512_xmm_avx512;
939 else if (regnum >= I387_YMM0H_REGNUM (tdep)
940 && regnum < I387_YMMENDH_REGNUM (tdep))
941 regclass = avxh;
942 else if (regnum >= I387_BND0R_REGNUM (tdep)
943 && regnum < I387_MPXEND_REGNUM (tdep))
944 regclass = mpx;
945 else if (regnum >= I387_XMM0_REGNUM (tdep)
946 && regnum < I387_MXCSR_REGNUM (tdep))
947 regclass = sse;
948 else if (regnum >= I387_ST0_REGNUM (tdep)
949 && regnum < I387_FCTRL_REGNUM (tdep))
950 regclass = x87;
951 else
952 regclass = none;
953
954 if (regclass != none)
955 {
956 /* Get `xstat_bv'. */
957 const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
958
959 /* The supported bits in `xstat_bv' are 1 byte. Clear part in
960 vector registers if its bit in xstat_bv is zero. */
961 clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
962 }
963 else
964 clear_bv = I386_XSTATE_ALL_MASK;
965
966 /* With the delayed xsave mechanism, in between the program
967 starting, and the program accessing the vector registers for the
968 first time, the register's values are invalid. The kernel
969 initializes register states to zero when they are set the first
970 time in a program. This means that from the user-space programs'
971 perspective, it's the same as if the registers have always been
972 zero from the start of the program. Therefore, the debugger
973 should provide the same illusion to the user. */
974
975 switch (regclass)
976 {
977 case none:
978 break;
979
980 case avx512_zmm_h:
981 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
982 regcache_raw_supply (regcache, regnum, zero);
983 else
984 regcache_raw_supply (regcache, regnum,
985 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
986 return;
987
988 case avx512_k:
989 if ((clear_bv & I386_XSTATE_K))
990 regcache_raw_supply (regcache, regnum, zero);
991 else
992 regcache_raw_supply (regcache, regnum,
993 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
994 return;
995
996 case avx512_ymmh_avx512:
997 if ((clear_bv & I386_XSTATE_ZMM))
998 regcache_raw_supply (regcache, regnum, zero);
999 else
1000 regcache_raw_supply (regcache, regnum,
1001 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1002 return;
1003
1004 case avx512_xmm_avx512:
1005 if ((clear_bv & I386_XSTATE_ZMM))
1006 regcache_raw_supply (regcache, regnum, zero);
1007 else
1008 regcache_raw_supply (regcache, regnum,
1009 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1010 return;
1011
1012 case avxh:
1013 if ((clear_bv & I386_XSTATE_AVX))
1014 regcache_raw_supply (regcache, regnum, zero);
1015 else
1016 regcache_raw_supply (regcache, regnum,
1017 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1018 return;
1019
1020 case mpx:
1021 if ((clear_bv & I386_XSTATE_BNDREGS))
1022 regcache_raw_supply (regcache, regnum, zero);
1023 else
1024 regcache_raw_supply (regcache, regnum,
1025 XSAVE_MPX_ADDR (tdep, regs, regnum));
1026 return;
1027
1028 case sse:
1029 if ((clear_bv & I386_XSTATE_SSE))
1030 regcache_raw_supply (regcache, regnum, zero);
1031 else
1032 regcache_raw_supply (regcache, regnum,
1033 FXSAVE_ADDR (tdep, regs, regnum));
1034 return;
1035
1036 case x87:
1037 if ((clear_bv & I386_XSTATE_X87))
1038 regcache_raw_supply (regcache, regnum, zero);
1039 else
1040 regcache_raw_supply (regcache, regnum,
1041 FXSAVE_ADDR (tdep, regs, regnum));
1042 return;
1043
1044 case all:
1045 /* Handle the upper ZMM registers. */
1046 if ((tdep->xcr0 & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1047 {
1048 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1049 {
1050 for (i = I387_ZMM0H_REGNUM (tdep);
1051 i < I387_ZMMENDH_REGNUM (tdep);
1052 i++)
1053 regcache_raw_supply (regcache, i, zero);
1054 }
1055 else
1056 {
1057 for (i = I387_ZMM0H_REGNUM (tdep);
1058 i < I387_ZMMENDH_REGNUM (tdep);
1059 i++)
1060 regcache_raw_supply (regcache, i,
1061 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1062 }
1063 }
1064
1065 /* Handle AVX512 OpMask registers. */
1066 if ((tdep->xcr0 & I386_XSTATE_K))
1067 {
1068 if ((clear_bv & I386_XSTATE_K))
1069 {
1070 for (i = I387_K0_REGNUM (tdep);
1071 i < I387_KEND_REGNUM (tdep);
1072 i++)
1073 regcache_raw_supply (regcache, i, zero);
1074 }
1075 else
1076 {
1077 for (i = I387_K0_REGNUM (tdep);
1078 i < I387_KEND_REGNUM (tdep);
1079 i++)
1080 regcache_raw_supply (regcache, i,
1081 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1082 }
1083 }
1084
1085 /* Handle the YMM_AVX512 registers. */
1086 if ((tdep->xcr0 & I386_XSTATE_ZMM))
1087 {
1088 if ((clear_bv & I386_XSTATE_ZMM))
1089 {
1090 for (i = I387_YMM16H_REGNUM (tdep);
1091 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1092 i++)
1093 regcache_raw_supply (regcache, i, zero);
1094 for (i = I387_XMM16_REGNUM (tdep);
1095 i < I387_XMM_AVX512_END_REGNUM (tdep);
1096 i++)
1097 regcache_raw_supply (regcache, i, zero);
1098 }
1099 else
1100 {
1101 for (i = I387_YMM16H_REGNUM (tdep);
1102 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1103 i++)
1104 regcache_raw_supply (regcache, i,
1105 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1106 for (i = I387_XMM16_REGNUM (tdep);
1107 i < I387_XMM_AVX512_END_REGNUM (tdep);
1108 i++)
1109 regcache_raw_supply (regcache, i,
1110 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1111 }
1112 }
1113 /* Handle the upper YMM registers. */
1114 if ((tdep->xcr0 & I386_XSTATE_AVX))
1115 {
1116 if ((clear_bv & I386_XSTATE_AVX))
1117 {
1118 for (i = I387_YMM0H_REGNUM (tdep);
1119 i < I387_YMMENDH_REGNUM (tdep);
1120 i++)
1121 regcache_raw_supply (regcache, i, zero);
1122 }
1123 else
1124 {
1125 for (i = I387_YMM0H_REGNUM (tdep);
1126 i < I387_YMMENDH_REGNUM (tdep);
1127 i++)
1128 regcache_raw_supply (regcache, i,
1129 XSAVE_AVXH_ADDR (tdep, regs, i));
1130 }
1131 }
1132
1133 /* Handle the MPX registers. */
1134 if ((tdep->xcr0 & I386_XSTATE_BNDREGS))
1135 {
1136 if (clear_bv & I386_XSTATE_BNDREGS)
1137 {
1138 for (i = I387_BND0R_REGNUM (tdep);
1139 i < I387_BNDCFGU_REGNUM (tdep); i++)
1140 regcache_raw_supply (regcache, i, zero);
1141 }
1142 else
1143 {
1144 for (i = I387_BND0R_REGNUM (tdep);
1145 i < I387_BNDCFGU_REGNUM (tdep); i++)
1146 regcache_raw_supply (regcache, i,
1147 XSAVE_MPX_ADDR (tdep, regs, i));
1148 }
1149 }
1150
1151 /* Handle the MPX registers. */
1152 if ((tdep->xcr0 & I386_XSTATE_BNDCFG))
1153 {
1154 if (clear_bv & I386_XSTATE_BNDCFG)
1155 {
1156 for (i = I387_BNDCFGU_REGNUM (tdep);
1157 i < I387_MPXEND_REGNUM (tdep); i++)
1158 regcache_raw_supply (regcache, i, zero);
1159 }
1160 else
1161 {
1162 for (i = I387_BNDCFGU_REGNUM (tdep);
1163 i < I387_MPXEND_REGNUM (tdep); i++)
1164 regcache_raw_supply (regcache, i,
1165 XSAVE_MPX_ADDR (tdep, regs, i));
1166 }
1167 }
1168
1169 /* Handle the XMM registers. */
1170 if ((tdep->xcr0 & I386_XSTATE_SSE))
1171 {
1172 if ((clear_bv & I386_XSTATE_SSE))
1173 {
1174 for (i = I387_XMM0_REGNUM (tdep);
1175 i < I387_MXCSR_REGNUM (tdep);
1176 i++)
1177 regcache_raw_supply (regcache, i, zero);
1178 }
1179 else
1180 {
1181 for (i = I387_XMM0_REGNUM (tdep);
1182 i < I387_MXCSR_REGNUM (tdep); i++)
1183 regcache_raw_supply (regcache, i,
1184 FXSAVE_ADDR (tdep, regs, i));
1185 }
1186 }
1187
1188 /* Handle the x87 registers. */
1189 if ((tdep->xcr0 & I386_XSTATE_X87))
1190 {
1191 if ((clear_bv & I386_XSTATE_X87))
1192 {
1193 for (i = I387_ST0_REGNUM (tdep);
1194 i < I387_FCTRL_REGNUM (tdep);
1195 i++)
1196 regcache_raw_supply (regcache, i, zero);
1197 }
1198 else
1199 {
1200 for (i = I387_ST0_REGNUM (tdep);
1201 i < I387_FCTRL_REGNUM (tdep);
1202 i++)
1203 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1204 }
1205 }
1206 break;
1207 }
1208
1209 /* Only handle x87 control registers. */
1210 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1211 if (regnum == -1 || regnum == i)
1212 {
1213 /* Most of the FPU control registers occupy only 16 bits in
1214 the xsave extended state. Give those a special treatment. */
1215 if (i != I387_FIOFF_REGNUM (tdep)
1216 && i != I387_FOOFF_REGNUM (tdep))
1217 {
1218 gdb_byte val[4];
1219
1220 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1221 val[2] = val[3] = 0;
1222 if (i == I387_FOP_REGNUM (tdep))
1223 val[1] &= ((1 << 3) - 1);
1224 else if (i== I387_FTAG_REGNUM (tdep))
1225 {
1226 /* The fxsave area contains a simplified version of
1227 the tag word. We have to look at the actual 80-bit
1228 FP data to recreate the traditional i387 tag word. */
1229
1230 unsigned long ftag = 0;
1231 int fpreg;
1232 int top;
1233
1234 top = ((FXSAVE_ADDR (tdep, regs,
1235 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1236 top &= 0x7;
1237
1238 for (fpreg = 7; fpreg >= 0; fpreg--)
1239 {
1240 int tag;
1241
1242 if (val[0] & (1 << fpreg))
1243 {
1244 int thisreg = (fpreg + 8 - top) % 8
1245 + I387_ST0_REGNUM (tdep);
1246 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1247 }
1248 else
1249 tag = 3; /* Empty */
1250
1251 ftag |= tag << (2 * fpreg);
1252 }
1253 val[0] = ftag & 0xff;
1254 val[1] = (ftag >> 8) & 0xff;
1255 }
1256 regcache_raw_supply (regcache, i, val);
1257 }
1258 else
1259 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1260 }
1261
1262 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1263 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1264 FXSAVE_MXCSR_ADDR (regs));
1265 }
1266
1267 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1268
1269 void
1270 i387_collect_xsave (const struct regcache *regcache, int regnum,
1271 void *xsave, int gcore)
1272 {
1273 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1275 gdb_byte *regs = xsave;
1276 int i;
1277 enum
1278 {
1279 none = 0x0,
1280 check = 0x1,
1281 x87 = 0x2 | check,
1282 sse = 0x4 | check,
1283 avxh = 0x8 | check,
1284 mpx = 0x10 | check,
1285 avx512_k = 0x20 | check,
1286 avx512_zmm_h = 0x40 | check,
1287 avx512_ymmh_avx512 = 0x80 | check,
1288 avx512_xmm_avx512 = 0x100 | check,
1289 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1290 | avx512_ymmh_avx512 | avx512_xmm_avx512
1291 } regclass;
1292
1293 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1294 gdb_assert (tdep->num_xmm_regs > 0);
1295
1296 if (regnum == -1)
1297 regclass = all;
1298 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1299 && regnum < I387_ZMMENDH_REGNUM (tdep))
1300 regclass = avx512_zmm_h;
1301 else if (regnum >= I387_K0_REGNUM (tdep)
1302 && regnum < I387_KEND_REGNUM (tdep))
1303 regclass = avx512_k;
1304 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1305 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1306 regclass = avx512_ymmh_avx512;
1307 else if (regnum >= I387_XMM16_REGNUM (tdep)
1308 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1309 regclass = avx512_xmm_avx512;
1310 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1311 && regnum < I387_YMMENDH_REGNUM (tdep))
1312 regclass = avxh;
1313 else if (regnum >= I387_BND0R_REGNUM (tdep)
1314 && regnum < I387_MPXEND_REGNUM (tdep))
1315 regclass = mpx;
1316 else if (regnum >= I387_XMM0_REGNUM (tdep)
1317 && regnum < I387_MXCSR_REGNUM (tdep))
1318 regclass = sse;
1319 else if (regnum >= I387_ST0_REGNUM (tdep)
1320 && regnum < I387_FCTRL_REGNUM (tdep))
1321 regclass = x87;
1322 else
1323 regclass = none;
1324
1325 if (gcore)
1326 {
1327 /* Clear XSAVE extended state. */
1328 memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0));
1329
1330 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1331 if (tdep->xsave_xcr0_offset != -1)
1332 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1333 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1334 }
1335
1336 if ((regclass & check))
1337 {
1338 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1339 gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
1340 unsigned int xstate_bv = 0;
1341 /* The supported bits in `xstat_bv' are 1 byte. */
1342 unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
1343 gdb_byte *p;
1344
1345 /* Clear register set if its bit in xstat_bv is zero. */
1346 if (clear_bv)
1347 {
1348 if ((clear_bv & I386_XSTATE_BNDREGS))
1349 for (i = I387_BND0R_REGNUM (tdep);
1350 i < I387_BNDCFGU_REGNUM (tdep); i++)
1351 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1352
1353 if ((clear_bv & I386_XSTATE_BNDCFG))
1354 for (i = I387_BNDCFGU_REGNUM (tdep);
1355 i < I387_MPXEND_REGNUM (tdep); i++)
1356 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1357
1358 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1359 for (i = I387_ZMM0H_REGNUM (tdep);
1360 i < I387_ZMMENDH_REGNUM (tdep); i++)
1361 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1362
1363 if ((clear_bv & I386_XSTATE_K))
1364 for (i = I387_K0_REGNUM (tdep);
1365 i < I387_KEND_REGNUM (tdep); i++)
1366 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1367
1368 if ((clear_bv & I386_XSTATE_ZMM))
1369 {
1370 for (i = I387_YMM16H_REGNUM (tdep);
1371 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1372 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1373 for (i = I387_XMM16_REGNUM (tdep);
1374 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1375 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1376 }
1377
1378 if ((clear_bv & I386_XSTATE_AVX))
1379 for (i = I387_YMM0H_REGNUM (tdep);
1380 i < I387_YMMENDH_REGNUM (tdep); i++)
1381 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1382
1383 if ((clear_bv & I386_XSTATE_SSE))
1384 for (i = I387_XMM0_REGNUM (tdep);
1385 i < I387_MXCSR_REGNUM (tdep); i++)
1386 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1387
1388 if ((clear_bv & I386_XSTATE_X87))
1389 for (i = I387_ST0_REGNUM (tdep);
1390 i < I387_FCTRL_REGNUM (tdep); i++)
1391 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1392 }
1393
1394 if (regclass == all)
1395 {
1396 /* Check if any ZMMH registers are changed. */
1397 if ((tdep->xcr0 & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1398 for (i = I387_ZMM0H_REGNUM (tdep);
1399 i < I387_ZMMENDH_REGNUM (tdep); i++)
1400 {
1401 regcache_raw_collect (regcache, i, raw);
1402 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1403 if (memcmp (raw, p, 32) != 0)
1404 {
1405 xstate_bv |= (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM);
1406 memcpy (p, raw, 32);
1407 }
1408 }
1409
1410 /* Check if any K registers are changed. */
1411 if ((tdep->xcr0 & I386_XSTATE_K))
1412 for (i = I387_K0_REGNUM (tdep);
1413 i < I387_KEND_REGNUM (tdep); i++)
1414 {
1415 regcache_raw_collect (regcache, i, raw);
1416 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1417 if (memcmp (raw, p, 8) != 0)
1418 {
1419 xstate_bv |= I386_XSTATE_K;
1420 memcpy (p, raw, 8);
1421 }
1422 }
1423
1424 /* Check if any XMM or upper YMM registers are changed. */
1425 if ((tdep->xcr0 & I386_XSTATE_ZMM))
1426 {
1427 for (i = I387_YMM16H_REGNUM (tdep);
1428 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1429 {
1430 regcache_raw_collect (regcache, i, raw);
1431 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1432 if (memcmp (raw, p, 16) != 0)
1433 {
1434 xstate_bv |= I386_XSTATE_ZMM;
1435 memcpy (p, raw, 16);
1436 }
1437 }
1438 for (i = I387_XMM16_REGNUM (tdep);
1439 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1440 {
1441 regcache_raw_collect (regcache, i, raw);
1442 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1443 if (memcmp (raw, p, 16) != 0)
1444 {
1445 xstate_bv |= I386_XSTATE_ZMM;
1446 memcpy (p, raw, 16);
1447 }
1448 }
1449 }
1450
1451 /* Check if any upper YMM registers are changed. */
1452 if ((tdep->xcr0 & I386_XSTATE_AVX))
1453 for (i = I387_YMM0H_REGNUM (tdep);
1454 i < I387_YMMENDH_REGNUM (tdep); i++)
1455 {
1456 regcache_raw_collect (regcache, i, raw);
1457 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1458 if (memcmp (raw, p, 16))
1459 {
1460 xstate_bv |= I386_XSTATE_AVX;
1461 memcpy (p, raw, 16);
1462 }
1463 }
1464 /* Check if any upper MPX registers are changed. */
1465 if ((tdep->xcr0 & I386_XSTATE_BNDREGS))
1466 for (i = I387_BND0R_REGNUM (tdep);
1467 i < I387_BNDCFGU_REGNUM (tdep); i++)
1468 {
1469 regcache_raw_collect (regcache, i, raw);
1470 p = XSAVE_MPX_ADDR (tdep, regs, i);
1471 if (memcmp (raw, p, 16))
1472 {
1473 xstate_bv |= I386_XSTATE_BNDREGS;
1474 memcpy (p, raw, 16);
1475 }
1476 }
1477
1478 /* Check if any upper MPX registers are changed. */
1479 if ((tdep->xcr0 & I386_XSTATE_BNDCFG))
1480 for (i = I387_BNDCFGU_REGNUM (tdep);
1481 i < I387_MPXEND_REGNUM (tdep); i++)
1482 {
1483 regcache_raw_collect (regcache, i, raw);
1484 p = XSAVE_MPX_ADDR (tdep, regs, i);
1485 if (memcmp (raw, p, 8))
1486 {
1487 xstate_bv |= I386_XSTATE_BNDCFG;
1488 memcpy (p, raw, 8);
1489 }
1490 }
1491
1492 /* Check if any SSE registers are changed. */
1493 if ((tdep->xcr0 & I386_XSTATE_SSE))
1494 for (i = I387_XMM0_REGNUM (tdep);
1495 i < I387_MXCSR_REGNUM (tdep); i++)
1496 {
1497 regcache_raw_collect (regcache, i, raw);
1498 p = FXSAVE_ADDR (tdep, regs, i);
1499 if (memcmp (raw, p, 16))
1500 {
1501 xstate_bv |= I386_XSTATE_SSE;
1502 memcpy (p, raw, 16);
1503 }
1504 }
1505
1506 /* Check if any X87 registers are changed. */
1507 if ((tdep->xcr0 & I386_XSTATE_X87))
1508 for (i = I387_ST0_REGNUM (tdep);
1509 i < I387_FCTRL_REGNUM (tdep); i++)
1510 {
1511 regcache_raw_collect (regcache, i, raw);
1512 p = FXSAVE_ADDR (tdep, regs, i);
1513 if (memcmp (raw, p, 10))
1514 {
1515 xstate_bv |= I386_XSTATE_X87;
1516 memcpy (p, raw, 10);
1517 }
1518 }
1519 }
1520 else
1521 {
1522 /* Check if REGNUM is changed. */
1523 regcache_raw_collect (regcache, regnum, raw);
1524
1525 switch (regclass)
1526 {
1527 default:
1528 internal_error (__FILE__, __LINE__,
1529 _("invalid i387 regclass"));
1530
1531 case avx512_zmm_h:
1532 /* This is a ZMM register. */
1533 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1534 if (memcmp (raw, p, 32) != 0)
1535 {
1536 xstate_bv |= (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM);
1537 memcpy (p, raw, 32);
1538 }
1539 break;
1540 case avx512_k:
1541 /* This is a AVX512 mask register. */
1542 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1543 if (memcmp (raw, p, 8) != 0)
1544 {
1545 xstate_bv |= I386_XSTATE_K;
1546 memcpy (p, raw, 8);
1547 }
1548 break;
1549
1550 case avx512_ymmh_avx512:
1551 /* This is an upper YMM16-31 register. */
1552 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1553 if (memcmp (raw, p, 16) != 0)
1554 {
1555 xstate_bv |= I386_XSTATE_ZMM;
1556 memcpy (p, raw, 16);
1557 }
1558 break;
1559
1560 case avx512_xmm_avx512:
1561 /* This is an upper XMM16-31 register. */
1562 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1563 if (memcmp (raw, p, 16) != 0)
1564 {
1565 xstate_bv |= I386_XSTATE_ZMM;
1566 memcpy (p, raw, 16);
1567 }
1568 break;
1569
1570 case avxh:
1571 /* This is an upper YMM register. */
1572 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1573 if (memcmp (raw, p, 16))
1574 {
1575 xstate_bv |= I386_XSTATE_AVX;
1576 memcpy (p, raw, 16);
1577 }
1578 break;
1579
1580 case mpx:
1581 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1582 {
1583 regcache_raw_collect (regcache, regnum, raw);
1584 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1585 if (memcmp (raw, p, 16))
1586 {
1587 xstate_bv |= I386_XSTATE_BNDREGS;
1588 memcpy (p, raw, 16);
1589 }
1590 }
1591 else
1592 {
1593 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1594 xstate_bv |= I386_XSTATE_BNDCFG;
1595 memcpy (p, raw, 8);
1596 }
1597 break;
1598
1599 case sse:
1600 /* This is an SSE register. */
1601 p = FXSAVE_ADDR (tdep, regs, regnum);
1602 if (memcmp (raw, p, 16))
1603 {
1604 xstate_bv |= I386_XSTATE_SSE;
1605 memcpy (p, raw, 16);
1606 }
1607 break;
1608
1609 case x87:
1610 /* This is an x87 register. */
1611 p = FXSAVE_ADDR (tdep, regs, regnum);
1612 if (memcmp (raw, p, 10))
1613 {
1614 xstate_bv |= I386_XSTATE_X87;
1615 memcpy (p, raw, 10);
1616 }
1617 break;
1618 }
1619 }
1620
1621 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1622 registers are changed. */
1623 if (xstate_bv)
1624 {
1625 /* The supported bits in `xstat_bv' are 1 byte. */
1626 *xstate_bv_p |= (gdb_byte) xstate_bv;
1627
1628 switch (regclass)
1629 {
1630 default:
1631 internal_error (__FILE__, __LINE__,
1632 _("invalid i387 regclass"));
1633
1634 case all:
1635 break;
1636
1637 case x87:
1638 case sse:
1639 case avxh:
1640 case mpx:
1641 case avx512_k:
1642 case avx512_zmm_h:
1643 case avx512_ymmh_avx512:
1644 case avx512_xmm_avx512:
1645 /* Register REGNUM has been updated. Return. */
1646 return;
1647 }
1648 }
1649 else
1650 {
1651 /* Return if REGNUM isn't changed. */
1652 if (regclass != all)
1653 return;
1654 }
1655 }
1656
1657 /* Only handle x87 control registers. */
1658 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1659 if (regnum == -1 || regnum == i)
1660 {
1661 /* Most of the FPU control registers occupy only 16 bits in
1662 the xsave extended state. Give those a special treatment. */
1663 if (i != I387_FIOFF_REGNUM (tdep)
1664 && i != I387_FOOFF_REGNUM (tdep))
1665 {
1666 gdb_byte buf[4];
1667
1668 regcache_raw_collect (regcache, i, buf);
1669
1670 if (i == I387_FOP_REGNUM (tdep))
1671 {
1672 /* The opcode occupies only 11 bits. Make sure we
1673 don't touch the other bits. */
1674 buf[1] &= ((1 << 3) - 1);
1675 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1676 }
1677 else if (i == I387_FTAG_REGNUM (tdep))
1678 {
1679 /* Converting back is much easier. */
1680
1681 unsigned short ftag;
1682 int fpreg;
1683
1684 ftag = (buf[1] << 8) | buf[0];
1685 buf[0] = 0;
1686 buf[1] = 0;
1687
1688 for (fpreg = 7; fpreg >= 0; fpreg--)
1689 {
1690 int tag = (ftag >> (fpreg * 2)) & 3;
1691
1692 if (tag != 3)
1693 buf[0] |= (1 << fpreg);
1694 }
1695 }
1696 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1697 }
1698 else
1699 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1700 }
1701
1702 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1703 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1704 FXSAVE_MXCSR_ADDR (regs));
1705 }
1706
1707 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1708 *RAW. */
1709
1710 static int
1711 i387_tag (const gdb_byte *raw)
1712 {
1713 int integer;
1714 unsigned int exponent;
1715 unsigned long fraction[2];
1716
1717 integer = raw[7] & 0x80;
1718 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1719 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1720 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1721 | (raw[5] << 8) | raw[4]);
1722
1723 if (exponent == 0x7fff)
1724 {
1725 /* Special. */
1726 return (2);
1727 }
1728 else if (exponent == 0x0000)
1729 {
1730 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1731 {
1732 /* Zero. */
1733 return (1);
1734 }
1735 else
1736 {
1737 /* Special. */
1738 return (2);
1739 }
1740 }
1741 else
1742 {
1743 if (integer)
1744 {
1745 /* Valid. */
1746 return (0);
1747 }
1748 else
1749 {
1750 /* Special. */
1751 return (2);
1752 }
1753 }
1754 }
1755
1756 /* Prepare the FPU stack in REGCACHE for a function return. */
1757
1758 void
1759 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1760 {
1761 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1762 ULONGEST fstat;
1763
1764 /* Set the top of the floating-point register stack to 7. The
1765 actual value doesn't really matter, but 7 is what a normal
1766 function return would end up with if the program started out with
1767 a freshly initialized FPU. */
1768 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1769 fstat |= (7 << 11);
1770 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1771
1772 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1773 floating-point register stack to 7, the appropriate value for the
1774 tag word is 0x3fff. */
1775 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1776
1777 }
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