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1 /* Target-dependent code for Renesas M32R, for GDB.
2
3 Copyright (C) 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "symtab.h"
28 #include "gdbtypes.h"
29 #include "gdbcmd.h"
30 #include "gdbcore.h"
31 #include "gdb_string.h"
32 #include "value.h"
33 #include "inferior.h"
34 #include "symfile.h"
35 #include "objfiles.h"
36 #include "osabi.h"
37 #include "language.h"
38 #include "arch-utils.h"
39 #include "regcache.h"
40 #include "trad-frame.h"
41 #include "dis-asm.h"
42
43 #include "gdb_assert.h"
44
45 #include "m32r-tdep.h"
46
47 /* Local functions */
48
49 extern void _initialize_m32r_tdep (void);
50
51 static CORE_ADDR
52 m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
53 {
54 /* Align to the size of an instruction (so that they can safely be
55 pushed onto the stack. */
56 return sp & ~3;
57 }
58
59
60 /* Breakpoints
61
62 The little endian mode of M32R is unique. In most of architectures,
63 two 16-bit instructions, A and B, are placed as the following:
64
65 Big endian:
66 A0 A1 B0 B1
67
68 Little endian:
69 A1 A0 B1 B0
70
71 In M32R, they are placed like this:
72
73 Big endian:
74 A0 A1 B0 B1
75
76 Little endian:
77 B1 B0 A1 A0
78
79 This is because M32R always fetches instructions in 32-bit.
80
81 The following functions take care of this behavior. */
82
83 static int
84 m32r_memory_insert_breakpoint (struct bp_target_info *bp_tgt)
85 {
86 CORE_ADDR addr = bp_tgt->placed_address;
87 int val;
88 gdb_byte buf[4];
89 gdb_byte *contents_cache = bp_tgt->shadow_contents;
90 gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */
91
92 /* Save the memory contents. */
93 val = target_read_memory (addr & 0xfffffffc, contents_cache, 4);
94 if (val != 0)
95 return val; /* return error */
96
97 bp_tgt->placed_size = bp_tgt->shadow_len = 4;
98
99 /* Determine appropriate breakpoint contents and size for this address. */
100 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
101 {
102 if ((addr & 3) == 0)
103 {
104 buf[0] = bp_entry[0];
105 buf[1] = bp_entry[1];
106 buf[2] = contents_cache[2] & 0x7f;
107 buf[3] = contents_cache[3];
108 }
109 else
110 {
111 buf[0] = contents_cache[0];
112 buf[1] = contents_cache[1];
113 buf[2] = bp_entry[0];
114 buf[3] = bp_entry[1];
115 }
116 }
117 else /* little-endian */
118 {
119 if ((addr & 3) == 0)
120 {
121 buf[0] = contents_cache[0];
122 buf[1] = contents_cache[1] & 0x7f;
123 buf[2] = bp_entry[1];
124 buf[3] = bp_entry[0];
125 }
126 else
127 {
128 buf[0] = bp_entry[1];
129 buf[1] = bp_entry[0];
130 buf[2] = contents_cache[2];
131 buf[3] = contents_cache[3];
132 }
133 }
134
135 /* Write the breakpoint. */
136 val = target_write_memory (addr & 0xfffffffc, buf, 4);
137 return val;
138 }
139
140 static int
141 m32r_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
142 {
143 CORE_ADDR addr = bp_tgt->placed_address;
144 int val;
145 gdb_byte buf[4];
146 gdb_byte *contents_cache = bp_tgt->shadow_contents;
147
148 buf[0] = contents_cache[0];
149 buf[1] = contents_cache[1];
150 buf[2] = contents_cache[2];
151 buf[3] = contents_cache[3];
152
153 /* Remove parallel bit. */
154 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
155 {
156 if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0)
157 buf[2] &= 0x7f;
158 }
159 else /* little-endian */
160 {
161 if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0)
162 buf[1] &= 0x7f;
163 }
164
165 /* Write contents. */
166 val = target_write_memory (addr & 0xfffffffc, buf, 4);
167 return val;
168 }
169
170 static const gdb_byte *
171 m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
172 {
173 static gdb_byte be_bp_entry[] = { 0x10, 0xf1, 0x70, 0x00 }; /* dpt -> nop */
174 static gdb_byte le_bp_entry[] = { 0x00, 0x70, 0xf1, 0x10 }; /* dpt -> nop */
175 gdb_byte *bp;
176
177 /* Determine appropriate breakpoint. */
178 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
179 {
180 if ((*pcptr & 3) == 0)
181 {
182 bp = be_bp_entry;
183 *lenptr = 4;
184 }
185 else
186 {
187 bp = be_bp_entry;
188 *lenptr = 2;
189 }
190 }
191 else
192 {
193 if ((*pcptr & 3) == 0)
194 {
195 bp = le_bp_entry;
196 *lenptr = 4;
197 }
198 else
199 {
200 bp = le_bp_entry + 2;
201 *lenptr = 2;
202 }
203 }
204
205 return bp;
206 }
207
208
209 char *m32r_register_names[] = {
210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
212 "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
213 "evb"
214 };
215
216 static const char *
217 m32r_register_name (int reg_nr)
218 {
219 if (reg_nr < 0)
220 return NULL;
221 if (reg_nr >= M32R_NUM_REGS)
222 return NULL;
223 return m32r_register_names[reg_nr];
224 }
225
226
227 /* Return the GDB type object for the "standard" data type
228 of data in register N. */
229
230 static struct type *
231 m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
232 {
233 if (reg_nr == M32R_PC_REGNUM)
234 return builtin_type_void_func_ptr;
235 else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
236 return builtin_type_void_data_ptr;
237 else
238 return builtin_type_int32;
239 }
240
241
242 /* Write into appropriate registers a function return value
243 of type TYPE, given in virtual format.
244
245 Things always get returned in RET1_REGNUM, RET2_REGNUM. */
246
247 static void
248 m32r_store_return_value (struct type *type, struct regcache *regcache,
249 const void *valbuf)
250 {
251 CORE_ADDR regval;
252 int len = TYPE_LENGTH (type);
253
254 regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len);
255 regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);
256
257 if (len > 4)
258 {
259 regval = extract_unsigned_integer ((gdb_byte *) valbuf + 4, len - 4);
260 regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
261 }
262 }
263
264 /* This is required by skip_prologue. The results of decoding a prologue
265 should be cached because this thrashing is getting nuts. */
266
267 static int
268 decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit,
269 CORE_ADDR *pl_endptr, unsigned long *framelength)
270 {
271 unsigned long framesize;
272 int insn;
273 int op1;
274 CORE_ADDR after_prologue = 0;
275 CORE_ADDR after_push = 0;
276 CORE_ADDR after_stack_adjust = 0;
277 CORE_ADDR current_pc;
278 LONGEST return_value;
279
280 framesize = 0;
281 after_prologue = 0;
282
283 for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
284 {
285 /* Check if current pc's location is readable. */
286 if (!safe_read_memory_integer (current_pc, 2, &return_value))
287 return -1;
288
289 insn = read_memory_unsigned_integer (current_pc, 2);
290
291 if (insn == 0x0000)
292 break;
293
294 /* If this is a 32 bit instruction, we dont want to examine its
295 immediate data as though it were an instruction */
296 if (current_pc & 0x02)
297 {
298 /* decode this instruction further */
299 insn &= 0x7fff;
300 }
301 else
302 {
303 if (insn & 0x8000)
304 {
305 if (current_pc == scan_limit)
306 scan_limit += 2; /* extend the search */
307
308 current_pc += 2; /* skip the immediate data */
309
310 /* Check if current pc's location is readable. */
311 if (!safe_read_memory_integer (current_pc, 2, &return_value))
312 return -1;
313
314 if (insn == 0x8faf) /* add3 sp, sp, xxxx */
315 /* add 16 bit sign-extended offset */
316 {
317 framesize +=
318 -((short) read_memory_unsigned_integer (current_pc, 2));
319 }
320 else
321 {
322 if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */
323 && safe_read_memory_integer (current_pc + 2, 2,
324 &return_value)
325 && read_memory_unsigned_integer (current_pc + 2,
326 2) == 0x0f24)
327 /* subtract 24 bit sign-extended negative-offset */
328 {
329 insn = read_memory_unsigned_integer (current_pc - 2, 4);
330 if (insn & 0x00800000) /* sign extend */
331 insn |= 0xff000000; /* negative */
332 else
333 insn &= 0x00ffffff; /* positive */
334 framesize += insn;
335 }
336 }
337 after_push = current_pc + 2;
338 continue;
339 }
340 }
341 op1 = insn & 0xf000; /* isolate just the first nibble */
342
343 if ((insn & 0xf0ff) == 0x207f)
344 { /* st reg, @-sp */
345 int regno;
346 framesize += 4;
347 regno = ((insn >> 8) & 0xf);
348 after_prologue = 0;
349 continue;
350 }
351 if ((insn >> 8) == 0x4f) /* addi sp, xx */
352 /* add 8 bit sign-extended offset */
353 {
354 int stack_adjust = (gdb_byte) (insn & 0xff);
355
356 /* there are probably two of these stack adjustments:
357 1) A negative one in the prologue, and
358 2) A positive one in the epilogue.
359 We are only interested in the first one. */
360
361 if (stack_adjust < 0)
362 {
363 framesize -= stack_adjust;
364 after_prologue = 0;
365 /* A frameless function may have no "mv fp, sp".
366 In that case, this is the end of the prologue. */
367 after_stack_adjust = current_pc + 2;
368 }
369 continue;
370 }
371 if (insn == 0x1d8f)
372 { /* mv fp, sp */
373 after_prologue = current_pc + 2;
374 break; /* end of stack adjustments */
375 }
376
377 /* Nop looks like a branch, continue explicitly */
378 if (insn == 0x7000)
379 {
380 after_prologue = current_pc + 2;
381 continue; /* nop occurs between pushes */
382 }
383 /* End of prolog if any of these are trap instructions */
384 if ((insn & 0xfff0) == 0x10f0)
385 {
386 after_prologue = current_pc;
387 break;
388 }
389 /* End of prolog if any of these are branch instructions */
390 if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
391 {
392 after_prologue = current_pc;
393 continue;
394 }
395 /* Some of the branch instructions are mixed with other types */
396 if (op1 == 0x1000)
397 {
398 int subop = insn & 0x0ff0;
399 if ((subop == 0x0ec0) || (subop == 0x0fc0))
400 {
401 after_prologue = current_pc;
402 continue; /* jmp , jl */
403 }
404 }
405 }
406
407 if (framelength)
408 *framelength = framesize;
409
410 if (current_pc >= scan_limit)
411 {
412 if (pl_endptr)
413 {
414 if (after_stack_adjust != 0)
415 /* We did not find a "mv fp,sp", but we DID find
416 a stack_adjust. Is it safe to use that as the
417 end of the prologue? I just don't know. */
418 {
419 *pl_endptr = after_stack_adjust;
420 }
421 else if (after_push != 0)
422 /* We did not find a "mv fp,sp", but we DID find
423 a push. Is it safe to use that as the
424 end of the prologue? I just don't know. */
425 {
426 *pl_endptr = after_push;
427 }
428 else
429 /* We reached the end of the loop without finding the end
430 of the prologue. No way to win -- we should report failure.
431 The way we do that is to return the original start_pc.
432 GDB will set a breakpoint at the start of the function (etc.) */
433 *pl_endptr = start_pc;
434 }
435 return 0;
436 }
437
438 if (after_prologue == 0)
439 after_prologue = current_pc;
440
441 if (pl_endptr)
442 *pl_endptr = after_prologue;
443
444 return 0;
445 } /* decode_prologue */
446
447 /* Function: skip_prologue
448 Find end of function prologue */
449
450 #define DEFAULT_SEARCH_LIMIT 128
451
452 CORE_ADDR
453 m32r_skip_prologue (CORE_ADDR pc)
454 {
455 CORE_ADDR func_addr, func_end;
456 struct symtab_and_line sal;
457 LONGEST return_value;
458
459 /* See what the symbol table says */
460
461 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
462 {
463 sal = find_pc_line (func_addr, 0);
464
465 if (sal.line != 0 && sal.end <= func_end)
466 {
467 func_end = sal.end;
468 }
469 else
470 /* Either there's no line info, or the line after the prologue is after
471 the end of the function. In this case, there probably isn't a
472 prologue. */
473 {
474 func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
475 }
476 }
477 else
478 func_end = pc + DEFAULT_SEARCH_LIMIT;
479
480 /* If pc's location is not readable, just quit. */
481 if (!safe_read_memory_integer (pc, 4, &return_value))
482 return pc;
483
484 /* Find the end of prologue. */
485 if (decode_prologue (pc, func_end, &sal.end, NULL) < 0)
486 return pc;
487
488 return sal.end;
489 }
490
491 struct m32r_unwind_cache
492 {
493 /* The previous frame's inner most stack address. Used as this
494 frame ID's stack_addr. */
495 CORE_ADDR prev_sp;
496 /* The frame's base, optionally used by the high-level debug info. */
497 CORE_ADDR base;
498 int size;
499 /* How far the SP and r13 (FP) have been offset from the start of
500 the stack frame (as defined by the previous frame's stack
501 pointer). */
502 LONGEST sp_offset;
503 LONGEST r13_offset;
504 int uses_frame;
505 /* Table indicating the location of each and every register. */
506 struct trad_frame_saved_reg *saved_regs;
507 };
508
509 /* Put here the code to store, into fi->saved_regs, the addresses of
510 the saved registers of frame described by FRAME_INFO. This
511 includes special registers such as pc and fp saved in special ways
512 in the stack frame. sp is even more special: the address we return
513 for it IS the sp for the next frame. */
514
515 static struct m32r_unwind_cache *
516 m32r_frame_unwind_cache (struct frame_info *next_frame,
517 void **this_prologue_cache)
518 {
519 CORE_ADDR pc, scan_limit;
520 ULONGEST prev_sp;
521 ULONGEST this_base;
522 unsigned long op, op2;
523 int i;
524 struct m32r_unwind_cache *info;
525
526
527 if ((*this_prologue_cache))
528 return (*this_prologue_cache);
529
530 info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
531 (*this_prologue_cache) = info;
532 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
533
534 info->size = 0;
535 info->sp_offset = 0;
536 info->uses_frame = 0;
537
538 scan_limit = frame_pc_unwind (next_frame);
539 for (pc = frame_func_unwind (next_frame);
540 pc > 0 && pc < scan_limit; pc += 2)
541 {
542 if ((pc & 2) == 0)
543 {
544 op = get_frame_memory_unsigned (next_frame, pc, 4);
545 if ((op & 0x80000000) == 0x80000000)
546 {
547 /* 32-bit instruction */
548 if ((op & 0xffff0000) == 0x8faf0000)
549 {
550 /* add3 sp,sp,xxxx */
551 short n = op & 0xffff;
552 info->sp_offset += n;
553 }
554 else if (((op >> 8) == 0xe4)
555 && get_frame_memory_unsigned (next_frame, pc + 2,
556 2) == 0x0f24)
557 {
558 /* ld24 r4, xxxxxx; sub sp, r4 */
559 unsigned long n = op & 0xffffff;
560 info->sp_offset += n;
561 pc += 2; /* skip sub instruction */
562 }
563
564 if (pc == scan_limit)
565 scan_limit += 2; /* extend the search */
566 pc += 2; /* skip the immediate data */
567 continue;
568 }
569 }
570
571 /* 16-bit instructions */
572 op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff;
573 if ((op & 0xf0ff) == 0x207f)
574 {
575 /* st rn, @-sp */
576 int regno = ((op >> 8) & 0xf);
577 info->sp_offset -= 4;
578 info->saved_regs[regno].addr = info->sp_offset;
579 }
580 else if ((op & 0xff00) == 0x4f00)
581 {
582 /* addi sp, xx */
583 int n = (gdb_byte) (op & 0xff);
584 info->sp_offset += n;
585 }
586 else if (op == 0x1d8f)
587 {
588 /* mv fp, sp */
589 info->uses_frame = 1;
590 info->r13_offset = info->sp_offset;
591 break; /* end of stack adjustments */
592 }
593 else if ((op & 0xfff0) == 0x10f0)
594 {
595 /* end of prologue if this is a trap instruction */
596 break; /* end of stack adjustments */
597 }
598 }
599
600 info->size = -info->sp_offset;
601
602 /* Compute the previous frame's stack pointer (which is also the
603 frame's ID's stack address), and this frame's base pointer. */
604 if (info->uses_frame)
605 {
606 /* The SP was moved to the FP. This indicates that a new frame
607 was created. Get THIS frame's FP value by unwinding it from
608 the next frame. */
609 this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM);
610 /* The FP points at the last saved register. Adjust the FP back
611 to before the first saved register giving the SP. */
612 prev_sp = this_base + info->size;
613 }
614 else
615 {
616 /* Assume that the FP is this frame's SP but with that pushed
617 stack space added back. */
618 this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
619 prev_sp = this_base + info->size;
620 }
621
622 /* Convert that SP/BASE into real addresses. */
623 info->prev_sp = prev_sp;
624 info->base = this_base;
625
626 /* Adjust all the saved registers so that they contain addresses and
627 not offsets. */
628 for (i = 0; i < NUM_REGS - 1; i++)
629 if (trad_frame_addr_p (info->saved_regs, i))
630 info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);
631
632 /* The call instruction moves the caller's PC in the callee's LR.
633 Since this is an unwind, do the reverse. Copy the location of LR
634 into PC (the address / regnum) so that a request for PC will be
635 converted into a request for the LR. */
636 info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];
637
638 /* The previous frame's SP needed to be computed. Save the computed
639 value. */
640 trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);
641
642 return info;
643 }
644
645 static CORE_ADDR
646 m32r_read_pc (ptid_t ptid)
647 {
648 ptid_t save_ptid;
649 ULONGEST pc;
650
651 save_ptid = inferior_ptid;
652 inferior_ptid = ptid;
653 regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc);
654 inferior_ptid = save_ptid;
655 return pc;
656 }
657
658 static void
659 m32r_write_pc (CORE_ADDR val, ptid_t ptid)
660 {
661 ptid_t save_ptid;
662
663 save_ptid = inferior_ptid;
664 inferior_ptid = ptid;
665 write_register (M32R_PC_REGNUM, val);
666 inferior_ptid = save_ptid;
667 }
668
669 static CORE_ADDR
670 m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
671 {
672 return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
673 }
674
675
676 static CORE_ADDR
677 m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
678 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
679 struct value **args, CORE_ADDR sp, int struct_return,
680 CORE_ADDR struct_addr)
681 {
682 int stack_offset, stack_alloc;
683 int argreg = ARG1_REGNUM;
684 int argnum;
685 struct type *type;
686 enum type_code typecode;
687 CORE_ADDR regval;
688 gdb_byte *val;
689 gdb_byte valbuf[MAX_REGISTER_SIZE];
690 int len;
691 int odd_sized_struct;
692
693 /* first force sp to a 4-byte alignment */
694 sp = sp & ~3;
695
696 /* Set the return address. For the m32r, the return breakpoint is
697 always at BP_ADDR. */
698 regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);
699
700 /* If STRUCT_RETURN is true, then the struct return address (in
701 STRUCT_ADDR) will consume the first argument-passing register.
702 Both adjust the register count and store that value. */
703 if (struct_return)
704 {
705 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
706 argreg++;
707 }
708
709 /* Now make sure there's space on the stack */
710 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
711 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
712 sp -= stack_alloc; /* make room on stack for args */
713
714 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
715 {
716 type = value_type (args[argnum]);
717 typecode = TYPE_CODE (type);
718 len = TYPE_LENGTH (type);
719
720 memset (valbuf, 0, sizeof (valbuf));
721
722 /* Passes structures that do not fit in 2 registers by reference. */
723 if (len > 8
724 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
725 {
726 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum]));
727 typecode = TYPE_CODE_PTR;
728 len = 4;
729 val = valbuf;
730 }
731 else if (len < 4)
732 {
733 /* value gets right-justified in the register or stack word */
734 memcpy (valbuf + (register_size (gdbarch, argreg) - len),
735 (gdb_byte *) value_contents (args[argnum]), len);
736 val = valbuf;
737 }
738 else
739 val = (gdb_byte *) value_contents (args[argnum]);
740
741 while (len > 0)
742 {
743 if (argreg > ARGN_REGNUM)
744 {
745 /* must go on the stack */
746 write_memory (sp + stack_offset, val, 4);
747 stack_offset += 4;
748 }
749 else if (argreg <= ARGN_REGNUM)
750 {
751 /* there's room in a register */
752 regval =
753 extract_unsigned_integer (val,
754 register_size (gdbarch, argreg));
755 regcache_cooked_write_unsigned (regcache, argreg++, regval);
756 }
757
758 /* Store the value 4 bytes at a time. This means that things
759 larger than 4 bytes may go partly in registers and partly
760 on the stack. */
761 len -= register_size (gdbarch, argreg);
762 val += register_size (gdbarch, argreg);
763 }
764 }
765
766 /* Finally, update the SP register. */
767 regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);
768
769 return sp;
770 }
771
772
773 /* Given a return value in `regbuf' with a type `valtype',
774 extract and copy its value into `valbuf'. */
775
776 static void
777 m32r_extract_return_value (struct type *type, struct regcache *regcache,
778 void *dst)
779 {
780 bfd_byte *valbuf = dst;
781 int len = TYPE_LENGTH (type);
782 ULONGEST tmp;
783
784 /* By using store_unsigned_integer we avoid having to do
785 anything special for small big-endian values. */
786 regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
787 store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp);
788
789 /* Ignore return values more than 8 bytes in size because the m32r
790 returns anything more than 8 bytes in the stack. */
791 if (len > 4)
792 {
793 regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
794 store_unsigned_integer (valbuf + len - 4, 4, tmp);
795 }
796 }
797
798 enum return_value_convention
799 m32r_return_value (struct gdbarch *gdbarch, struct type *valtype,
800 struct regcache *regcache, gdb_byte *readbuf,
801 const gdb_byte *writebuf)
802 {
803 if (TYPE_LENGTH (valtype) > 8)
804 return RETURN_VALUE_STRUCT_CONVENTION;
805 else
806 {
807 if (readbuf != NULL)
808 m32r_extract_return_value (valtype, regcache, readbuf);
809 if (writebuf != NULL)
810 m32r_store_return_value (valtype, regcache, writebuf);
811 return RETURN_VALUE_REGISTER_CONVENTION;
812 }
813 }
814
815
816
817 static CORE_ADDR
818 m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
819 {
820 return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
821 }
822
823 /* Given a GDB frame, determine the address of the calling function's
824 frame. This will be used to create a new GDB frame struct. */
825
826 static void
827 m32r_frame_this_id (struct frame_info *next_frame,
828 void **this_prologue_cache, struct frame_id *this_id)
829 {
830 struct m32r_unwind_cache *info
831 = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
832 CORE_ADDR base;
833 CORE_ADDR func;
834 struct minimal_symbol *msym_stack;
835 struct frame_id id;
836
837 /* The FUNC is easy. */
838 func = frame_func_unwind (next_frame);
839
840 /* Check if the stack is empty. */
841 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
842 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
843 return;
844
845 /* Hopefully the prologue analysis either correctly determined the
846 frame's base (which is the SP from the previous frame), or set
847 that base to "NULL". */
848 base = info->prev_sp;
849 if (base == 0)
850 return;
851
852 id = frame_id_build (base, func);
853 (*this_id) = id;
854 }
855
856 static void
857 m32r_frame_prev_register (struct frame_info *next_frame,
858 void **this_prologue_cache,
859 int regnum, int *optimizedp,
860 enum lval_type *lvalp, CORE_ADDR *addrp,
861 int *realnump, gdb_byte *bufferp)
862 {
863 struct m32r_unwind_cache *info
864 = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
865 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
866 optimizedp, lvalp, addrp, realnump, bufferp);
867 }
868
869 static const struct frame_unwind m32r_frame_unwind = {
870 NORMAL_FRAME,
871 m32r_frame_this_id,
872 m32r_frame_prev_register
873 };
874
875 static const struct frame_unwind *
876 m32r_frame_sniffer (struct frame_info *next_frame)
877 {
878 return &m32r_frame_unwind;
879 }
880
881 static CORE_ADDR
882 m32r_frame_base_address (struct frame_info *next_frame, void **this_cache)
883 {
884 struct m32r_unwind_cache *info
885 = m32r_frame_unwind_cache (next_frame, this_cache);
886 return info->base;
887 }
888
889 static const struct frame_base m32r_frame_base = {
890 &m32r_frame_unwind,
891 m32r_frame_base_address,
892 m32r_frame_base_address,
893 m32r_frame_base_address
894 };
895
896 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
897 dummy frame. The frame ID's base needs to match the TOS value
898 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
899 breakpoint. */
900
901 static struct frame_id
902 m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
903 {
904 return frame_id_build (m32r_unwind_sp (gdbarch, next_frame),
905 frame_pc_unwind (next_frame));
906 }
907
908
909 static gdbarch_init_ftype m32r_gdbarch_init;
910
911 static struct gdbarch *
912 m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
913 {
914 struct gdbarch *gdbarch;
915 struct gdbarch_tdep *tdep;
916
917 /* If there is already a candidate, use it. */
918 arches = gdbarch_list_lookup_by_info (arches, &info);
919 if (arches != NULL)
920 return arches->gdbarch;
921
922 /* Allocate space for the new architecture. */
923 tdep = XMALLOC (struct gdbarch_tdep);
924 gdbarch = gdbarch_alloc (&info, tdep);
925
926 set_gdbarch_read_pc (gdbarch, m32r_read_pc);
927 set_gdbarch_write_pc (gdbarch, m32r_write_pc);
928 set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
929
930 set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);
931 set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
932 set_gdbarch_register_name (gdbarch, m32r_register_name);
933 set_gdbarch_register_type (gdbarch, m32r_register_type);
934
935 set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
936 set_gdbarch_return_value (gdbarch, m32r_return_value);
937
938 set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
939 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
940 set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
941 set_gdbarch_memory_insert_breakpoint (gdbarch,
942 m32r_memory_insert_breakpoint);
943 set_gdbarch_memory_remove_breakpoint (gdbarch,
944 m32r_memory_remove_breakpoint);
945
946 set_gdbarch_frame_align (gdbarch, m32r_frame_align);
947
948 frame_base_set_default (gdbarch, &m32r_frame_base);
949
950 /* Methods for saving / extracting a dummy frame's ID. The ID's
951 stack address must match the SP value returned by
952 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
953 set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id);
954
955 /* Return the unwound PC value. */
956 set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
957
958 set_gdbarch_print_insn (gdbarch, print_insn_m32r);
959
960 /* Hook in ABI-specific overrides, if they have been registered. */
961 gdbarch_init_osabi (info, gdbarch);
962
963 /* Hook in the default unwinders. */
964 frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer);
965
966 return gdbarch;
967 }
968
969 void
970 _initialize_m32r_tdep (void)
971 {
972 register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);
973 }