1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
78 static const char *mips_abi_string
;
80 static const char *mips_abi_strings
[] = {
91 /* Various MIPS ISA options (related to stack analysis) can be
92 overridden dynamically. Establish an enum/array for managing
95 static const char size_auto
[] = "auto";
96 static const char size_32
[] = "32";
97 static const char size_64
[] = "64";
99 static const char *size_enums
[] = {
106 /* Some MIPS boards don't support floating point while others only
107 support single-precision floating-point operations. */
111 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
112 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
113 MIPS_FPU_NONE
/* No floating point. */
116 #ifndef MIPS_DEFAULT_FPU_TYPE
117 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
119 static int mips_fpu_type_auto
= 1;
120 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
122 static int mips_debug
= 0;
124 /* Properties (for struct target_desc) describing the g/G packet
126 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
127 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
152 /* The size of register data available from the target, if known.
153 This doesn't quite obsolete the manual
154 mips64_transfers_32bit_regs_p, since that is documented to force
155 left alignment even for big endian (very strange). */
156 int register_size_valid_p
;
161 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
167 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
168 They are implemented as a pair of 64bit doubles where the high
169 part holds the result of the operation rounded to double, and
170 the low double holds the difference between the exact result and
171 the rounded result. So "high" + "low" contains the result with
172 added precision. Unfortunately, the floatformat structure used
173 by GDB is not powerful enough to describe this format. As a temporary
174 measure, we define a 128bit floatformat that only uses the high part.
175 We lose a bit of precision but that's probably the best we can do
176 for now with the current infrastructure. */
178 static const struct floatformat floatformat_n32n64_long_double_big
=
180 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
181 floatformat_intbit_no
,
182 "floatformat_n32n64_long_double_big",
183 n32n64_floatformat_always_valid
186 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
188 &floatformat_n32n64_long_double_big
,
189 &floatformat_n32n64_long_double_big
192 const struct mips_regnum
*
193 mips_regnum (struct gdbarch
*gdbarch
)
195 return gdbarch_tdep (gdbarch
)->regnum
;
199 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
201 return mips_regnum (gdbarch
)->fp0
+ 12;
204 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
205 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
207 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
209 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
211 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
213 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
214 functions to test, set, or clear bit 0 of addresses. */
217 is_mips16_addr (CORE_ADDR addr
)
223 unmake_mips16_addr (CORE_ADDR addr
)
225 return ((addr
) & ~(CORE_ADDR
) 1);
228 /* Return the contents of register REGNUM as a signed integer. */
231 read_signed_register (int regnum
)
234 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
239 read_signed_register_pid (int regnum
, ptid_t ptid
)
244 if (ptid_equal (ptid
, inferior_ptid
))
245 return read_signed_register (regnum
);
247 save_ptid
= inferior_ptid
;
249 inferior_ptid
= ptid
;
251 retval
= read_signed_register (regnum
);
253 inferior_ptid
= save_ptid
;
258 /* Return the MIPS ABI associated with GDBARCH. */
260 mips_abi (struct gdbarch
*gdbarch
)
262 return gdbarch_tdep (gdbarch
)->mips_abi
;
266 mips_isa_regsize (struct gdbarch
*gdbarch
)
268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 /* If we know how big the registers are, use that size. */
271 if (tdep
->register_size_valid_p
)
272 return tdep
->register_size
;
274 /* Fall back to the previous behavior. */
275 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
276 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
279 /* Return the currently configured (or set) saved register size. */
281 static const char *mips_abi_regsize_string
= size_auto
;
284 mips_abi_regsize (struct gdbarch
*gdbarch
)
286 if (mips_abi_regsize_string
== size_auto
)
287 switch (mips_abi (gdbarch
))
289 case MIPS_ABI_EABI32
:
295 case MIPS_ABI_EABI64
:
297 case MIPS_ABI_UNKNOWN
:
300 internal_error (__FILE__
, __LINE__
, _("bad switch"));
302 else if (mips_abi_regsize_string
== size_64
)
304 else /* if (mips_abi_regsize_string == size_32) */
308 /* Functions for setting and testing a bit in a minimal symbol that
309 marks it as 16-bit function. The MSB of the minimal symbol's
310 "info" field is used for this purpose.
312 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
313 i.e. refers to a 16-bit function, and sets a "special" bit in a
314 minimal symbol to mark it as a 16-bit function
316 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
319 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
321 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
323 MSYMBOL_INFO (msym
) = (char *)
324 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
325 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
330 msymbol_is_special (struct minimal_symbol
*msym
)
332 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
335 /* XFER a value from the big/little/left end of the register.
336 Depending on the size of the value it might occupy the entire
337 register or just part of it. Make an allowance for this, aligning
338 things accordingly. */
341 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
342 enum bfd_endian endian
, gdb_byte
*in
,
343 const gdb_byte
*out
, int buf_offset
)
346 gdb_assert (reg_num
>= NUM_REGS
);
347 /* Need to transfer the left or right part of the register, based on
348 the targets byte order. */
352 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
354 case BFD_ENDIAN_LITTLE
:
357 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
361 internal_error (__FILE__
, __LINE__
, _("bad switch"));
364 fprintf_unfiltered (gdb_stderr
,
365 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
366 reg_num
, reg_offset
, buf_offset
, length
);
367 if (mips_debug
&& out
!= NULL
)
370 fprintf_unfiltered (gdb_stdlog
, "out ");
371 for (i
= 0; i
< length
; i
++)
372 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
375 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
378 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
380 if (mips_debug
&& in
!= NULL
)
383 fprintf_unfiltered (gdb_stdlog
, "in ");
384 for (i
= 0; i
< length
; i
++)
385 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
388 fprintf_unfiltered (gdb_stdlog
, "\n");
391 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
392 compatiblity mode. A return value of 1 means that we have
393 physical 64-bit registers, but should treat them as 32-bit registers. */
396 mips2_fp_compat (void)
398 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
400 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
405 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
406 in all the places we deal with FP registers. PR gdb/413. */
407 /* Otherwise check the FR bit in the status register - it controls
408 the FP compatiblity mode. If it is clear we are in compatibility
410 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
417 /* The amount of space reserved on the stack for registers. This is
418 different to MIPS_ABI_REGSIZE as it determines the alignment of
419 data allocated after the registers have run out. */
421 static const char *mips_stack_argsize_string
= size_auto
;
424 mips_stack_argsize (struct gdbarch
*gdbarch
)
426 if (mips_stack_argsize_string
== size_auto
)
427 return mips_abi_regsize (gdbarch
);
428 else if (mips_stack_argsize_string
== size_64
)
430 else /* if (mips_stack_argsize_string == size_32) */
434 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
436 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
438 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
440 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
442 static struct type
*mips_float_register_type (void);
443 static struct type
*mips_double_register_type (void);
445 /* The list of available "set mips " and "show mips " commands */
447 static struct cmd_list_element
*setmipscmdlist
= NULL
;
448 static struct cmd_list_element
*showmipscmdlist
= NULL
;
450 /* Integer registers 0 thru 31 are handled explicitly by
451 mips_register_name(). Processor specific registers 32 and above
452 are listed in the following tables. */
455 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
459 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
460 "sr", "lo", "hi", "bad", "cause", "pc",
461 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
462 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
463 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
464 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
465 "fsr", "fir", "" /*"fp" */ , "",
466 "", "", "", "", "", "", "", "",
467 "", "", "", "", "", "", "", "",
470 /* Names of IDT R3041 registers. */
472 static const char *mips_r3041_reg_names
[] = {
473 "sr", "lo", "hi", "bad", "cause", "pc",
474 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
475 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
476 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
477 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
478 "fsr", "fir", "", /*"fp" */ "",
479 "", "", "bus", "ccfg", "", "", "", "",
480 "", "", "port", "cmp", "", "", "epc", "prid",
483 /* Names of tx39 registers. */
485 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
486 "sr", "lo", "hi", "bad", "cause", "pc",
487 "", "", "", "", "", "", "", "",
488 "", "", "", "", "", "", "", "",
489 "", "", "", "", "", "", "", "",
490 "", "", "", "", "", "", "", "",
492 "", "", "", "", "", "", "", "",
493 "", "", "config", "cache", "debug", "depc", "epc", ""
496 /* Names of IRIX registers. */
497 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
498 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
502 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
506 /* Return the name of the register corresponding to REGNO. */
508 mips_register_name (int regno
)
510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
511 /* GPR names for all ABIs other than n32/n64. */
512 static char *mips_gpr_names
[] = {
513 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
514 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
515 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
516 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
519 /* GPR names for n32 and n64 ABIs. */
520 static char *mips_n32_n64_gpr_names
[] = {
521 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
522 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
523 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
524 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
527 enum mips_abi abi
= mips_abi (current_gdbarch
);
529 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
530 don't make the raw register names visible. */
531 int rawnum
= regno
% NUM_REGS
;
532 if (regno
< NUM_REGS
)
535 /* The MIPS integer registers are always mapped from 0 to 31. The
536 names of the registers (which reflects the conventions regarding
537 register use) vary depending on the ABI. */
538 if (0 <= rawnum
&& rawnum
< 32)
540 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
541 return mips_n32_n64_gpr_names
[rawnum
];
543 return mips_gpr_names
[rawnum
];
545 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
547 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
548 return tdep
->mips_processor_reg_names
[rawnum
- 32];
551 internal_error (__FILE__
, __LINE__
,
552 _("mips_register_name: bad register number %d"), rawnum
);
555 /* Return the groups that a MIPS register can be categorised into. */
558 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
559 struct reggroup
*reggroup
)
564 int rawnum
= regnum
% NUM_REGS
;
565 int pseudo
= regnum
/ NUM_REGS
;
566 if (reggroup
== all_reggroup
)
568 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
569 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
570 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
571 (gdbarch), as not all architectures are multi-arch. */
572 raw_p
= rawnum
< NUM_REGS
;
573 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
575 if (reggroup
== float_reggroup
)
576 return float_p
&& pseudo
;
577 if (reggroup
== vector_reggroup
)
578 return vector_p
&& pseudo
;
579 if (reggroup
== general_reggroup
)
580 return (!vector_p
&& !float_p
) && pseudo
;
581 /* Save the pseudo registers. Need to make certain that any code
582 extracting register values from a saved register cache also uses
584 if (reggroup
== save_reggroup
)
585 return raw_p
&& pseudo
;
586 /* Restore the same pseudo register. */
587 if (reggroup
== restore_reggroup
)
588 return raw_p
&& pseudo
;
592 /* Map the symbol table registers which live in the range [1 *
593 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
594 registers. Take care of alignment and size problems. */
597 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
598 int cookednum
, gdb_byte
*buf
)
600 int rawnum
= cookednum
% NUM_REGS
;
601 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
602 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
603 regcache_raw_read (regcache
, rawnum
, buf
);
604 else if (register_size (gdbarch
, rawnum
) >
605 register_size (gdbarch
, cookednum
))
607 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
608 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
609 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
611 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
614 internal_error (__FILE__
, __LINE__
, _("bad register size"));
618 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
619 struct regcache
*regcache
, int cookednum
,
622 int rawnum
= cookednum
% NUM_REGS
;
623 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
624 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
625 regcache_raw_write (regcache
, rawnum
, buf
);
626 else if (register_size (gdbarch
, rawnum
) >
627 register_size (gdbarch
, cookednum
))
629 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
630 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
631 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
633 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
636 internal_error (__FILE__
, __LINE__
, _("bad register size"));
639 /* Table to translate MIPS16 register field to actual register number. */
640 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
642 /* Heuristic_proc_start may hunt through the text section for a long
643 time across a 2400 baud serial line. Allows the user to limit this
646 static unsigned int heuristic_fence_post
= 0;
648 /* Number of bytes of storage in the actual machine representation for
649 register N. NOTE: This defines the pseudo register type so need to
650 rebuild the architecture vector. */
652 static int mips64_transfers_32bit_regs_p
= 0;
655 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
656 struct cmd_list_element
*c
)
658 struct gdbarch_info info
;
659 gdbarch_info_init (&info
);
660 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
661 instead of relying on globals. Doing that would let generic code
662 handle the search for this specific architecture. */
663 if (!gdbarch_update_p (info
))
665 mips64_transfers_32bit_regs_p
= 0;
666 error (_("32-bit compatibility mode not supported"));
670 /* Convert to/from a register and the corresponding memory value. */
673 mips_convert_register_p (int regnum
, struct type
*type
)
675 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
676 && register_size (current_gdbarch
, regnum
) == 4
677 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
678 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
679 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
683 mips_register_to_value (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, gdb_byte
*to
)
686 get_frame_register (frame
, regnum
+ 0, to
+ 4);
687 get_frame_register (frame
, regnum
+ 1, to
+ 0);
691 mips_value_to_register (struct frame_info
*frame
, int regnum
,
692 struct type
*type
, const gdb_byte
*from
)
694 put_frame_register (frame
, regnum
+ 0, from
+ 4);
695 put_frame_register (frame
, regnum
+ 1, from
+ 0);
698 /* Return the GDB type object for the "standard" data type of data in
702 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
704 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
705 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
706 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
708 /* The floating-point registers raw, or cooked, always match
709 mips_isa_regsize(), and also map 1:1, byte for byte. */
710 if (mips_isa_regsize (gdbarch
) == 4)
711 return builtin_type_ieee_single
;
713 return builtin_type_ieee_double
;
715 else if (regnum
< NUM_REGS
)
717 /* The raw or ISA registers. These are all sized according to
719 if (mips_isa_regsize (gdbarch
) == 4)
720 return builtin_type_int32
;
722 return builtin_type_int64
;
726 /* The cooked or ABI registers. These are sized according to
727 the ABI (with a few complications). */
728 if (regnum
>= (NUM_REGS
729 + mips_regnum (current_gdbarch
)->fp_control_status
)
730 && regnum
<= NUM_REGS
+ MIPS_LAST_EMBED_REGNUM
)
731 /* The pseudo/cooked view of the embedded registers is always
732 32-bit. The raw view is handled below. */
733 return builtin_type_int32
;
734 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
735 /* The target, while possibly using a 64-bit register buffer,
736 is only transfering 32-bits of each integer register.
737 Reflect this in the cooked/pseudo (ABI) register value. */
738 return builtin_type_int32
;
739 else if (mips_abi_regsize (gdbarch
) == 4)
740 /* The ABI is restricted to 32-bit registers (the ISA could be
742 return builtin_type_int32
;
745 return builtin_type_int64
;
750 /* Should the upper word of 64-bit addresses be zeroed? */
751 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
754 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
756 switch (mask_address_var
)
758 case AUTO_BOOLEAN_TRUE
:
760 case AUTO_BOOLEAN_FALSE
:
763 case AUTO_BOOLEAN_AUTO
:
764 return tdep
->default_mask_address_p
;
766 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
772 show_mask_address (struct ui_file
*file
, int from_tty
,
773 struct cmd_list_element
*c
, const char *value
)
775 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
777 deprecated_show_value_hack (file
, from_tty
, c
, value
);
778 switch (mask_address_var
)
780 case AUTO_BOOLEAN_TRUE
:
781 printf_filtered ("The 32 bit mips address mask is enabled\n");
783 case AUTO_BOOLEAN_FALSE
:
784 printf_filtered ("The 32 bit mips address mask is disabled\n");
786 case AUTO_BOOLEAN_AUTO
:
788 ("The 32 bit address mask is set automatically. Currently %s\n",
789 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
792 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
797 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
800 mips_pc_is_mips16 (CORE_ADDR memaddr
)
802 struct minimal_symbol
*sym
;
804 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
805 if (is_mips16_addr (memaddr
))
808 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
809 the high bit of the info field. Use this to decide if the function is
810 MIPS16 or normal MIPS. */
811 sym
= lookup_minimal_symbol_by_pc (memaddr
);
813 return msymbol_is_special (sym
);
818 /* MIPS believes that the PC has a sign extended value. Perhaps the
819 all registers should be sign extended for simplicity? */
822 mips_read_pc (ptid_t ptid
)
824 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
828 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
830 return frame_unwind_register_signed (next_frame
,
831 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
835 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
837 return frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
840 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
841 dummy frame. The frame ID's base needs to match the TOS value
842 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
845 static struct frame_id
846 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
848 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
849 frame_pc_unwind (next_frame
));
853 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
855 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
858 /* Fetch and return instruction from the specified location. If the PC
859 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
862 mips_fetch_instruction (CORE_ADDR addr
)
864 gdb_byte buf
[MIPS_INSN32_SIZE
];
868 if (mips_pc_is_mips16 (addr
))
870 instlen
= MIPS_INSN16_SIZE
;
871 addr
= unmake_mips16_addr (addr
);
874 instlen
= MIPS_INSN32_SIZE
;
875 status
= read_memory_nobpt (addr
, buf
, instlen
);
877 memory_error (status
, addr
);
878 return extract_unsigned_integer (buf
, instlen
);
881 /* These the fields of 32 bit mips instructions */
882 #define mips32_op(x) (x >> 26)
883 #define itype_op(x) (x >> 26)
884 #define itype_rs(x) ((x >> 21) & 0x1f)
885 #define itype_rt(x) ((x >> 16) & 0x1f)
886 #define itype_immediate(x) (x & 0xffff)
888 #define jtype_op(x) (x >> 26)
889 #define jtype_target(x) (x & 0x03ffffff)
891 #define rtype_op(x) (x >> 26)
892 #define rtype_rs(x) ((x >> 21) & 0x1f)
893 #define rtype_rt(x) ((x >> 16) & 0x1f)
894 #define rtype_rd(x) ((x >> 11) & 0x1f)
895 #define rtype_shamt(x) ((x >> 6) & 0x1f)
896 #define rtype_funct(x) (x & 0x3f)
899 mips32_relative_offset (ULONGEST inst
)
901 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
904 /* Determine where to set a single step breakpoint while considering
905 branch prediction. */
907 mips32_next_pc (CORE_ADDR pc
)
911 inst
= mips_fetch_instruction (pc
);
912 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
914 if (itype_op (inst
) >> 2 == 5)
915 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
917 op
= (itype_op (inst
) & 0x03);
932 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
933 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
935 int tf
= itype_rt (inst
) & 0x01;
936 int cnum
= itype_rt (inst
) >> 2;
938 read_signed_register (mips_regnum (current_gdbarch
)->
940 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
942 if (((cond
>> cnum
) & 0x01) == tf
)
943 pc
+= mips32_relative_offset (inst
) + 4;
948 pc
+= 4; /* Not a branch, next instruction is easy */
951 { /* This gets way messy */
953 /* Further subdivide into SPECIAL, REGIMM and other */
954 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
956 case 0: /* SPECIAL */
957 op
= rtype_funct (inst
);
962 /* Set PC to that address */
963 pc
= read_signed_register (rtype_rs (inst
));
969 break; /* end SPECIAL */
972 op
= itype_rt (inst
); /* branch condition */
977 case 16: /* BLTZAL */
978 case 18: /* BLTZALL */
980 if (read_signed_register (itype_rs (inst
)) < 0)
981 pc
+= mips32_relative_offset (inst
) + 4;
983 pc
+= 8; /* after the delay slot */
987 case 17: /* BGEZAL */
988 case 19: /* BGEZALL */
989 if (read_signed_register (itype_rs (inst
)) >= 0)
990 pc
+= mips32_relative_offset (inst
) + 4;
992 pc
+= 8; /* after the delay slot */
994 /* All of the other instructions in the REGIMM category */
999 break; /* end REGIMM */
1004 reg
= jtype_target (inst
) << 2;
1005 /* Upper four bits get never changed... */
1006 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1009 /* FIXME case JALX : */
1012 reg
= jtype_target (inst
) << 2;
1013 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1014 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1016 break; /* The new PC will be alternate mode */
1017 case 4: /* BEQ, BEQL */
1019 if (read_signed_register (itype_rs (inst
)) ==
1020 read_signed_register (itype_rt (inst
)))
1021 pc
+= mips32_relative_offset (inst
) + 4;
1025 case 5: /* BNE, BNEL */
1027 if (read_signed_register (itype_rs (inst
)) !=
1028 read_signed_register (itype_rt (inst
)))
1029 pc
+= mips32_relative_offset (inst
) + 4;
1033 case 6: /* BLEZ, BLEZL */
1034 if (read_signed_register (itype_rs (inst
)) <= 0)
1035 pc
+= mips32_relative_offset (inst
) + 4;
1041 greater_branch
: /* BGTZ, BGTZL */
1042 if (read_signed_register (itype_rs (inst
)) > 0)
1043 pc
+= mips32_relative_offset (inst
) + 4;
1050 } /* mips32_next_pc */
1052 /* Decoding the next place to set a breakpoint is irregular for the
1053 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1054 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1055 We dont want to set a single step instruction on the extend instruction
1059 /* Lots of mips16 instruction formats */
1060 /* Predicting jumps requires itype,ritype,i8type
1061 and their extensions extItype,extritype,extI8type
1063 enum mips16_inst_fmts
1065 itype
, /* 0 immediate 5,10 */
1066 ritype
, /* 1 5,3,8 */
1067 rrtype
, /* 2 5,3,3,5 */
1068 rritype
, /* 3 5,3,3,5 */
1069 rrrtype
, /* 4 5,3,3,3,2 */
1070 rriatype
, /* 5 5,3,3,1,4 */
1071 shifttype
, /* 6 5,3,3,3,2 */
1072 i8type
, /* 7 5,3,8 */
1073 i8movtype
, /* 8 5,3,3,5 */
1074 i8mov32rtype
, /* 9 5,3,5,3 */
1075 i64type
, /* 10 5,3,8 */
1076 ri64type
, /* 11 5,3,3,5 */
1077 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1078 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1079 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1080 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1081 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1082 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1083 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1084 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1085 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1086 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1088 /* I am heaping all the fields of the formats into one structure and
1089 then, only the fields which are involved in instruction extension */
1093 unsigned int regx
; /* Function in i8 type */
1098 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1099 for the bits which make up the immediatate extension. */
1102 extended_offset (unsigned int extension
)
1105 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1107 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1109 value
|= extension
& 0x01f; /* extract 4:0 */
1113 /* Only call this function if you know that this is an extendable
1114 instruction, It wont malfunction, but why make excess remote memory references?
1115 If the immediate operands get sign extended or somthing, do it after
1116 the extension is performed.
1118 /* FIXME: Every one of these cases needs to worry about sign extension
1119 when the offset is to be used in relative addressing */
1123 fetch_mips_16 (CORE_ADDR pc
)
1126 pc
&= 0xfffffffe; /* clear the low order bit */
1127 target_read_memory (pc
, buf
, 2);
1128 return extract_unsigned_integer (buf
, 2);
1132 unpack_mips16 (CORE_ADDR pc
,
1133 unsigned int extension
,
1135 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1140 switch (insn_format
)
1147 value
= extended_offset (extension
);
1148 value
= value
<< 11; /* rom for the original value */
1149 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1153 value
= inst
& 0x7ff;
1154 /* FIXME : Consider sign extension */
1163 { /* A register identifier and an offset */
1164 /* Most of the fields are the same as I type but the
1165 immediate value is of a different length */
1169 value
= extended_offset (extension
);
1170 value
= value
<< 8; /* from the original instruction */
1171 value
|= inst
& 0xff; /* eleven bits from instruction */
1172 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1173 if (value
& 0x4000) /* test the sign bit , bit 26 */
1175 value
&= ~0x3fff; /* remove the sign bit */
1181 value
= inst
& 0xff; /* 8 bits */
1182 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1183 /* FIXME: Do sign extension , this format needs it */
1184 if (value
& 0x80) /* THIS CONFUSES ME */
1186 value
&= 0xef; /* remove the sign bit */
1196 unsigned long value
;
1197 unsigned int nexthalf
;
1198 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1199 value
= value
<< 16;
1200 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1208 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1210 upk
->offset
= offset
;
1217 add_offset_16 (CORE_ADDR pc
, int offset
)
1219 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1223 extended_mips16_next_pc (CORE_ADDR pc
,
1224 unsigned int extension
, unsigned int insn
)
1226 int op
= (insn
>> 11);
1229 case 2: /* Branch */
1232 struct upk_mips16 upk
;
1233 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1234 offset
= upk
.offset
;
1240 pc
+= (offset
<< 1) + 2;
1243 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1245 struct upk_mips16 upk
;
1246 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1247 pc
= add_offset_16 (pc
, upk
.offset
);
1248 if ((insn
>> 10) & 0x01) /* Exchange mode */
1249 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1256 struct upk_mips16 upk
;
1258 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1259 reg
= read_signed_register (upk
.regx
);
1261 pc
+= (upk
.offset
<< 1) + 2;
1268 struct upk_mips16 upk
;
1270 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1271 reg
= read_signed_register (upk
.regx
);
1273 pc
+= (upk
.offset
<< 1) + 2;
1278 case 12: /* I8 Formats btez btnez */
1280 struct upk_mips16 upk
;
1282 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1283 /* upk.regx contains the opcode */
1284 reg
= read_signed_register (24); /* Test register is 24 */
1285 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1286 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1287 /* pc = add_offset_16(pc,upk.offset) ; */
1288 pc
+= (upk
.offset
<< 1) + 2;
1293 case 29: /* RR Formats JR, JALR, JALR-RA */
1295 struct upk_mips16 upk
;
1296 /* upk.fmt = rrtype; */
1301 upk
.regx
= (insn
>> 8) & 0x07;
1302 upk
.regy
= (insn
>> 5) & 0x07;
1310 break; /* Function return instruction */
1316 break; /* BOGUS Guess */
1318 pc
= read_signed_register (reg
);
1325 /* This is an instruction extension. Fetch the real instruction
1326 (which follows the extension) and decode things based on
1330 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1343 mips16_next_pc (CORE_ADDR pc
)
1345 unsigned int insn
= fetch_mips_16 (pc
);
1346 return extended_mips16_next_pc (pc
, 0, insn
);
1349 /* The mips_next_pc function supports single_step when the remote
1350 target monitor or stub is not developed enough to do a single_step.
1351 It works by decoding the current instruction and predicting where a
1352 branch will go. This isnt hard because all the data is available.
1353 The MIPS32 and MIPS16 variants are quite different */
1355 mips_next_pc (CORE_ADDR pc
)
1358 return mips16_next_pc (pc
);
1360 return mips32_next_pc (pc
);
1363 struct mips_frame_cache
1366 struct trad_frame_saved_reg
*saved_regs
;
1369 /* Set a register's saved stack address in temp_saved_regs. If an
1370 address has already been set for this register, do nothing; this
1371 way we will only recognize the first save of a given register in a
1374 For simplicity, save the address in both [0 .. NUM_REGS) and
1375 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1376 is used as it is only second range (the ABI instead of ISA
1377 registers) that comes into play when finding saved registers in a
1381 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1384 if (this_cache
!= NULL
1385 && this_cache
->saved_regs
[regnum
].addr
== -1)
1387 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1388 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1393 /* Fetch the immediate value from a MIPS16 instruction.
1394 If the previous instruction was an EXTEND, use it to extend
1395 the upper bits of the immediate value. This is a helper function
1396 for mips16_scan_prologue. */
1399 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1400 unsigned short inst
, /* current instruction */
1401 int nbits
, /* number of bits in imm field */
1402 int scale
, /* scale factor to be applied to imm */
1403 int is_signed
) /* is the imm field signed? */
1407 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1409 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1410 if (offset
& 0x8000) /* check for negative extend */
1411 offset
= 0 - (0x10000 - (offset
& 0xffff));
1412 return offset
| (inst
& 0x1f);
1416 int max_imm
= 1 << nbits
;
1417 int mask
= max_imm
- 1;
1418 int sign_bit
= max_imm
>> 1;
1420 offset
= inst
& mask
;
1421 if (is_signed
&& (offset
& sign_bit
))
1422 offset
= 0 - (max_imm
- offset
);
1423 return offset
* scale
;
1428 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1429 the associated FRAME_CACHE if not null.
1430 Return the address of the first instruction past the prologue. */
1433 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1434 struct frame_info
*next_frame
,
1435 struct mips_frame_cache
*this_cache
)
1438 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1440 long frame_offset
= 0; /* Size of stack frame. */
1441 long frame_adjust
= 0; /* Offset of FP from SP. */
1442 int frame_reg
= MIPS_SP_REGNUM
;
1443 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1444 unsigned inst
= 0; /* current instruction */
1445 unsigned entry_inst
= 0; /* the entry instruction */
1448 int extend_bytes
= 0;
1449 int prev_extend_bytes
;
1450 CORE_ADDR end_prologue_addr
= 0;
1452 /* Can be called when there's no process, and hence when there's no
1454 if (next_frame
!= NULL
)
1455 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1459 if (limit_pc
> start_pc
+ 200)
1460 limit_pc
= start_pc
+ 200;
1462 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1464 /* Save the previous instruction. If it's an EXTEND, we'll extract
1465 the immediate offset extension from it in mips16_get_imm. */
1468 /* Fetch and decode the instruction. */
1469 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1471 /* Normally we ignore extend instructions. However, if it is
1472 not followed by a valid prologue instruction, then this
1473 instruction is not part of the prologue either. We must
1474 remember in this case to adjust the end_prologue_addr back
1476 if ((inst
& 0xf800) == 0xf000) /* extend */
1478 extend_bytes
= MIPS_INSN16_SIZE
;
1482 prev_extend_bytes
= extend_bytes
;
1485 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1486 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1488 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1489 if (offset
< 0) /* negative stack adjustment? */
1490 frame_offset
-= offset
;
1492 /* Exit loop if a positive stack adjustment is found, which
1493 usually means that the stack cleanup code in the function
1494 epilogue is reached. */
1497 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1499 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1500 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1501 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1503 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1505 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1506 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1507 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1509 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1511 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1512 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1514 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1516 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1517 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1519 else if (inst
== 0x673d) /* move $s1, $sp */
1524 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1526 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1527 frame_addr
= sp
+ offset
;
1529 frame_adjust
= offset
;
1531 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1533 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1534 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1535 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1537 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1539 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1540 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1541 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1543 else if ((inst
& 0xf81f) == 0xe809
1544 && (inst
& 0x700) != 0x700) /* entry */
1545 entry_inst
= inst
; /* save for later processing */
1546 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1547 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1548 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1550 /* This instruction is part of the prologue, but we don't
1551 need to do anything special to handle it. */
1555 /* This instruction is not an instruction typically found
1556 in a prologue, so we must have reached the end of the
1558 if (end_prologue_addr
== 0)
1559 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1563 /* The entry instruction is typically the first instruction in a function,
1564 and it stores registers at offsets relative to the value of the old SP
1565 (before the prologue). But the value of the sp parameter to this
1566 function is the new SP (after the prologue has been executed). So we
1567 can't calculate those offsets until we've seen the entire prologue,
1568 and can calculate what the old SP must have been. */
1569 if (entry_inst
!= 0)
1571 int areg_count
= (entry_inst
>> 8) & 7;
1572 int sreg_count
= (entry_inst
>> 6) & 3;
1574 /* The entry instruction always subtracts 32 from the SP. */
1577 /* Now we can calculate what the SP must have been at the
1578 start of the function prologue. */
1581 /* Check if a0-a3 were saved in the caller's argument save area. */
1582 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1584 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1585 offset
+= mips_abi_regsize (current_gdbarch
);
1588 /* Check if the ra register was pushed on the stack. */
1590 if (entry_inst
& 0x20)
1592 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1593 offset
-= mips_abi_regsize (current_gdbarch
);
1596 /* Check if the s0 and s1 registers were pushed on the stack. */
1597 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1599 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1600 offset
-= mips_abi_regsize (current_gdbarch
);
1604 if (this_cache
!= NULL
)
1607 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1608 + frame_offset
- frame_adjust
);
1609 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1610 be able to get rid of the assignment below, evetually. But it's
1611 still needed for now. */
1612 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1613 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1616 /* If we didn't reach the end of the prologue when scanning the function
1617 instructions, then set end_prologue_addr to the address of the
1618 instruction immediately after the last one we scanned. */
1619 if (end_prologue_addr
== 0)
1620 end_prologue_addr
= cur_pc
;
1622 return end_prologue_addr
;
1625 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1626 Procedures that use the 32-bit instruction set are handled by the
1627 mips_insn32 unwinder. */
1629 static struct mips_frame_cache
*
1630 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1632 struct mips_frame_cache
*cache
;
1634 if ((*this_cache
) != NULL
)
1635 return (*this_cache
);
1636 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1637 (*this_cache
) = cache
;
1638 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1640 /* Analyze the function prologue. */
1642 const CORE_ADDR pc
=
1643 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1644 CORE_ADDR start_addr
;
1646 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1647 if (start_addr
== 0)
1648 start_addr
= heuristic_proc_start (pc
);
1649 /* We can't analyze the prologue if we couldn't find the begining
1651 if (start_addr
== 0)
1654 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1657 /* SP_REGNUM, contains the value and not the address. */
1658 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1660 return (*this_cache
);
1664 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1665 struct frame_id
*this_id
)
1667 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1669 (*this_id
) = frame_id_build (info
->base
,
1670 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1674 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1676 int regnum
, int *optimizedp
,
1677 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1678 int *realnump
, gdb_byte
*valuep
)
1680 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1682 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1683 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1686 static const struct frame_unwind mips_insn16_frame_unwind
=
1689 mips_insn16_frame_this_id
,
1690 mips_insn16_frame_prev_register
1693 static const struct frame_unwind
*
1694 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1696 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1697 if (mips_pc_is_mips16 (pc
))
1698 return &mips_insn16_frame_unwind
;
1703 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1706 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1711 static const struct frame_base mips_insn16_frame_base
=
1713 &mips_insn16_frame_unwind
,
1714 mips_insn16_frame_base_address
,
1715 mips_insn16_frame_base_address
,
1716 mips_insn16_frame_base_address
1719 static const struct frame_base
*
1720 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1722 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1723 return &mips_insn16_frame_base
;
1728 /* Mark all the registers as unset in the saved_regs array
1729 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1732 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1734 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1738 const int num_regs
= NUM_REGS
;
1741 for (i
= 0; i
< num_regs
; i
++)
1743 this_cache
->saved_regs
[i
].addr
= -1;
1748 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1749 the associated FRAME_CACHE if not null.
1750 Return the address of the first instruction past the prologue. */
1753 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1754 struct frame_info
*next_frame
,
1755 struct mips_frame_cache
*this_cache
)
1758 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1761 int frame_reg
= MIPS_SP_REGNUM
;
1763 CORE_ADDR end_prologue_addr
= 0;
1764 int seen_sp_adjust
= 0;
1765 int load_immediate_bytes
= 0;
1767 /* Can be called when there's no process, and hence when there's no
1769 if (next_frame
!= NULL
)
1770 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1774 if (limit_pc
> start_pc
+ 200)
1775 limit_pc
= start_pc
+ 200;
1780 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1782 unsigned long inst
, high_word
, low_word
;
1785 /* Fetch the instruction. */
1786 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1788 /* Save some code by pre-extracting some useful fields. */
1789 high_word
= (inst
>> 16) & 0xffff;
1790 low_word
= inst
& 0xffff;
1791 reg
= high_word
& 0x1f;
1793 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1794 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1795 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1797 if (low_word
& 0x8000) /* negative stack adjustment? */
1798 frame_offset
+= 0x10000 - low_word
;
1800 /* Exit loop if a positive stack adjustment is found, which
1801 usually means that the stack cleanup code in the function
1802 epilogue is reached. */
1806 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1808 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1810 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1812 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1813 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1815 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1817 /* Old gcc frame, r30 is virtual frame pointer. */
1818 if ((long) low_word
!= frame_offset
)
1819 frame_addr
= sp
+ low_word
;
1820 else if (frame_reg
== MIPS_SP_REGNUM
)
1822 unsigned alloca_adjust
;
1825 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1826 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1827 if (alloca_adjust
> 0)
1829 /* FP > SP + frame_size. This may be because of
1830 an alloca or somethings similar. Fix sp to
1831 "pre-alloca" value, and try again. */
1832 sp
+= alloca_adjust
;
1833 /* Need to reset the status of all registers. Otherwise,
1834 we will hit a guard that prevents the new address
1835 for each register to be recomputed during the second
1837 reset_saved_regs (this_cache
);
1842 /* move $30,$sp. With different versions of gas this will be either
1843 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1844 Accept any one of these. */
1845 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1847 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1848 if (frame_reg
== MIPS_SP_REGNUM
)
1850 unsigned alloca_adjust
;
1853 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1854 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1855 if (alloca_adjust
> 0)
1857 /* FP > SP + frame_size. This may be because of
1858 an alloca or somethings similar. Fix sp to
1859 "pre-alloca" value, and try again. */
1861 /* Need to reset the status of all registers. Otherwise,
1862 we will hit a guard that prevents the new address
1863 for each register to be recomputed during the second
1865 reset_saved_regs (this_cache
);
1870 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1872 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1874 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1875 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1876 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1877 || high_word
== 0x3c1c /* lui $gp,n */
1878 || high_word
== 0x279c /* addiu $gp,$gp,n */
1879 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1880 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1883 /* These instructions are part of the prologue, but we don't
1884 need to do anything special to handle them. */
1886 /* The instructions below load $at or $t0 with an immediate
1887 value in preparation for a stack adjustment via
1888 subu $sp,$sp,[$at,$t0]. These instructions could also
1889 initialize a local variable, so we accept them only before
1890 a stack adjustment instruction was seen. */
1891 else if (!seen_sp_adjust
1892 && (high_word
== 0x3c01 /* lui $at,n */
1893 || high_word
== 0x3c08 /* lui $t0,n */
1894 || high_word
== 0x3421 /* ori $at,$at,n */
1895 || high_word
== 0x3508 /* ori $t0,$t0,n */
1896 || high_word
== 0x3401 /* ori $at,$zero,n */
1897 || high_word
== 0x3408 /* ori $t0,$zero,n */
1900 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1904 /* This instruction is not an instruction typically found
1905 in a prologue, so we must have reached the end of the
1907 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1908 loop now? Why would we need to continue scanning the function
1910 if (end_prologue_addr
== 0)
1911 end_prologue_addr
= cur_pc
;
1915 if (this_cache
!= NULL
)
1918 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1920 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1921 this assignment below, eventually. But it's still needed
1923 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1924 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1927 /* If we didn't reach the end of the prologue when scanning the function
1928 instructions, then set end_prologue_addr to the address of the
1929 instruction immediately after the last one we scanned. */
1930 /* brobecker/2004-10-10: I don't think this would ever happen, but
1931 we may as well be careful and do our best if we have a null
1932 end_prologue_addr. */
1933 if (end_prologue_addr
== 0)
1934 end_prologue_addr
= cur_pc
;
1936 /* In a frameless function, we might have incorrectly
1937 skipped some load immediate instructions. Undo the skipping
1938 if the load immediate was not followed by a stack adjustment. */
1939 if (load_immediate_bytes
&& !seen_sp_adjust
)
1940 end_prologue_addr
-= load_immediate_bytes
;
1942 return end_prologue_addr
;
1945 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1946 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1947 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1950 static struct mips_frame_cache
*
1951 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1953 struct mips_frame_cache
*cache
;
1955 if ((*this_cache
) != NULL
)
1956 return (*this_cache
);
1958 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1959 (*this_cache
) = cache
;
1960 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1962 /* Analyze the function prologue. */
1964 const CORE_ADDR pc
=
1965 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1966 CORE_ADDR start_addr
;
1968 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1969 if (start_addr
== 0)
1970 start_addr
= heuristic_proc_start (pc
);
1971 /* We can't analyze the prologue if we couldn't find the begining
1973 if (start_addr
== 0)
1976 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1979 /* SP_REGNUM, contains the value and not the address. */
1980 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1982 return (*this_cache
);
1986 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1987 struct frame_id
*this_id
)
1989 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1991 (*this_id
) = frame_id_build (info
->base
,
1992 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1996 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1998 int regnum
, int *optimizedp
,
1999 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2000 int *realnump
, gdb_byte
*valuep
)
2002 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2004 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2005 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2008 static const struct frame_unwind mips_insn32_frame_unwind
=
2011 mips_insn32_frame_this_id
,
2012 mips_insn32_frame_prev_register
2015 static const struct frame_unwind
*
2016 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2018 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2019 if (! mips_pc_is_mips16 (pc
))
2020 return &mips_insn32_frame_unwind
;
2025 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2028 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2033 static const struct frame_base mips_insn32_frame_base
=
2035 &mips_insn32_frame_unwind
,
2036 mips_insn32_frame_base_address
,
2037 mips_insn32_frame_base_address
,
2038 mips_insn32_frame_base_address
2041 static const struct frame_base
*
2042 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2044 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2045 return &mips_insn32_frame_base
;
2050 static struct trad_frame_cache
*
2051 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2054 CORE_ADDR start_addr
;
2055 CORE_ADDR stack_addr
;
2056 struct trad_frame_cache
*this_trad_cache
;
2058 if ((*this_cache
) != NULL
)
2059 return (*this_cache
);
2060 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2061 (*this_cache
) = this_trad_cache
;
2063 /* The return address is in the link register. */
2064 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2066 /* Frame ID, since it's a frameless / stackless function, no stack
2067 space is allocated and SP on entry is the current SP. */
2068 pc
= frame_pc_unwind (next_frame
);
2069 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2070 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2071 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2073 /* Assume that the frame's base is the same as the
2075 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2077 return this_trad_cache
;
2081 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2082 struct frame_id
*this_id
)
2084 struct trad_frame_cache
*this_trad_cache
2085 = mips_stub_frame_cache (next_frame
, this_cache
);
2086 trad_frame_get_id (this_trad_cache
, this_id
);
2090 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2092 int regnum
, int *optimizedp
,
2093 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2094 int *realnump
, gdb_byte
*valuep
)
2096 struct trad_frame_cache
*this_trad_cache
2097 = mips_stub_frame_cache (next_frame
, this_cache
);
2098 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2099 lvalp
, addrp
, realnump
, valuep
);
2102 static const struct frame_unwind mips_stub_frame_unwind
=
2105 mips_stub_frame_this_id
,
2106 mips_stub_frame_prev_register
2109 static const struct frame_unwind
*
2110 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2112 struct obj_section
*s
;
2113 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2115 if (in_plt_section (pc
, NULL
))
2116 return &mips_stub_frame_unwind
;
2118 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2119 s
= find_pc_section (pc
);
2122 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2123 ".MIPS.stubs") == 0)
2124 return &mips_stub_frame_unwind
;
2130 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2133 struct trad_frame_cache
*this_trad_cache
2134 = mips_stub_frame_cache (next_frame
, this_cache
);
2135 return trad_frame_get_this_base (this_trad_cache
);
2138 static const struct frame_base mips_stub_frame_base
=
2140 &mips_stub_frame_unwind
,
2141 mips_stub_frame_base_address
,
2142 mips_stub_frame_base_address
,
2143 mips_stub_frame_base_address
2146 static const struct frame_base
*
2147 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2149 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2150 return &mips_stub_frame_base
;
2156 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2158 /* Always a pseudo. */
2159 gdb_assert (regno
>= NUM_REGS
);
2163 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2167 return frame_unwind_register_signed (fi
, regno
);
2171 /* mips_addr_bits_remove - remove useless address bits */
2174 mips_addr_bits_remove (CORE_ADDR addr
)
2176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2177 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2178 /* This hack is a work-around for existing boards using PMON, the
2179 simulator, and any other 64-bit targets that doesn't have true
2180 64-bit addressing. On these targets, the upper 32 bits of
2181 addresses are ignored by the hardware. Thus, the PC or SP are
2182 likely to have been sign extended to all 1s by instruction
2183 sequences that load 32-bit addresses. For example, a typical
2184 piece of code that loads an address is this:
2186 lui $r2, <upper 16 bits>
2187 ori $r2, <lower 16 bits>
2189 But the lui sign-extends the value such that the upper 32 bits
2190 may be all 1s. The workaround is simply to mask off these
2191 bits. In the future, gcc may be changed to support true 64-bit
2192 addressing, and this masking will have to be disabled. */
2193 return addr
&= 0xffffffffUL
;
2198 /* mips_software_single_step() is called just before we want to resume
2199 the inferior, if we want to single-step it but there is no hardware
2200 or kernel single-step support (MIPS on GNU/Linux for example). We find
2201 the target of the coming instruction and breakpoint it. */
2204 mips_software_single_step (struct regcache
*regcache
)
2206 CORE_ADDR pc
, next_pc
;
2208 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2209 next_pc
= mips_next_pc (pc
);
2211 insert_single_step_breakpoint (next_pc
);
2215 /* Test whether the PC points to the return instruction at the
2216 end of a function. */
2219 mips_about_to_return (CORE_ADDR pc
)
2221 if (mips_pc_is_mips16 (pc
))
2222 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2223 generates a "jr $ra"; other times it generates code to load
2224 the return address from the stack to an accessible register (such
2225 as $a3), then a "jr" using that register. This second case
2226 is almost impossible to distinguish from an indirect jump
2227 used for switch statements, so we don't even try. */
2228 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2230 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2234 /* This fencepost looks highly suspicious to me. Removing it also
2235 seems suspicious as it could affect remote debugging across serial
2239 heuristic_proc_start (CORE_ADDR pc
)
2246 pc
= ADDR_BITS_REMOVE (pc
);
2248 fence
= start_pc
- heuristic_fence_post
;
2252 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2253 fence
= VM_MIN_ADDRESS
;
2255 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2257 /* search back for previous return */
2258 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2259 if (start_pc
< fence
)
2261 /* It's not clear to me why we reach this point when
2262 stop_soon, but with this test, at least we
2263 don't print out warnings for every child forked (eg, on
2264 decstation). 22apr93 rich@cygnus.com. */
2265 if (stop_soon
== NO_STOP_QUIETLY
)
2267 static int blurb_printed
= 0;
2269 warning (_("GDB can't find the start of the function at 0x%s."),
2274 /* This actually happens frequently in embedded
2275 development, when you first connect to a board
2276 and your stack pointer and pc are nowhere in
2277 particular. This message needs to give people
2278 in that situation enough information to
2279 determine that it's no big deal. */
2280 printf_filtered ("\n\
2281 GDB is unable to find the start of the function at 0x%s\n\
2282 and thus can't determine the size of that function's stack frame.\n\
2283 This means that GDB may be unable to access that stack frame, or\n\
2284 the frames below it.\n\
2285 This problem is most likely caused by an invalid program counter or\n\
2287 However, if you think GDB should simply search farther back\n\
2288 from 0x%s for code which looks like the beginning of a\n\
2289 function, you can increase the range of the search using the `set\n\
2290 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2297 else if (mips_pc_is_mips16 (start_pc
))
2299 unsigned short inst
;
2301 /* On MIPS16, any one of the following is likely to be the
2302 start of a function:
2306 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2307 inst
= mips_fetch_instruction (start_pc
);
2308 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2309 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2310 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2311 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2313 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2314 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2319 else if (mips_about_to_return (start_pc
))
2321 /* Skip return and its delay slot. */
2322 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2329 struct mips_objfile_private
2335 /* According to the current ABI, should the type be passed in a
2336 floating-point register (assuming that there is space)? When there
2337 is no FPU, FP are not even considered as possible candidates for
2338 FP registers and, consequently this returns false - forces FP
2339 arguments into integer registers. */
2342 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2344 return ((typecode
== TYPE_CODE_FLT
2346 && (typecode
== TYPE_CODE_STRUCT
2347 || typecode
== TYPE_CODE_UNION
)
2348 && TYPE_NFIELDS (arg_type
) == 1
2349 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2351 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2354 /* On o32, argument passing in GPRs depends on the alignment of the type being
2355 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2358 mips_type_needs_double_align (struct type
*type
)
2360 enum type_code typecode
= TYPE_CODE (type
);
2362 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2364 else if (typecode
== TYPE_CODE_STRUCT
)
2366 if (TYPE_NFIELDS (type
) < 1)
2368 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2370 else if (typecode
== TYPE_CODE_UNION
)
2374 n
= TYPE_NFIELDS (type
);
2375 for (i
= 0; i
< n
; i
++)
2376 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2383 /* Adjust the address downward (direction of stack growth) so that it
2384 is correctly aligned for a new stack frame. */
2386 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2388 return align_down (addr
, 16);
2392 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2393 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2394 int nargs
, struct value
**args
, CORE_ADDR sp
,
2395 int struct_return
, CORE_ADDR struct_addr
)
2401 int stack_offset
= 0;
2402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2403 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2405 /* For shared libraries, "t9" needs to point at the function
2407 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2409 /* Set the return address register to point to the entry point of
2410 the program, where a breakpoint lies in wait. */
2411 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2413 /* First ensure that the stack and structure return address (if any)
2414 are properly aligned. The stack has to be at least 64-bit
2415 aligned even on 32-bit machines, because doubles must be 64-bit
2416 aligned. For n32 and n64, stack frames need to be 128-bit
2417 aligned, so we round to this widest known alignment. */
2419 sp
= align_down (sp
, 16);
2420 struct_addr
= align_down (struct_addr
, 16);
2422 /* Now make space on the stack for the args. We allocate more
2423 than necessary for EABI, because the first few arguments are
2424 passed in registers, but that's OK. */
2425 for (argnum
= 0; argnum
< nargs
; argnum
++)
2426 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2427 mips_stack_argsize (gdbarch
));
2428 sp
-= align_up (len
, 16);
2431 fprintf_unfiltered (gdb_stdlog
,
2432 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2433 paddr_nz (sp
), (long) align_up (len
, 16));
2435 /* Initialize the integer and float register pointers. */
2436 argreg
= MIPS_A0_REGNUM
;
2437 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2439 /* The struct_return pointer occupies the first parameter-passing reg. */
2443 fprintf_unfiltered (gdb_stdlog
,
2444 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2445 argreg
, paddr_nz (struct_addr
));
2446 write_register (argreg
++, struct_addr
);
2449 /* Now load as many as possible of the first arguments into
2450 registers, and push the rest onto the stack. Loop thru args
2451 from first to last. */
2452 for (argnum
= 0; argnum
< nargs
; argnum
++)
2454 const gdb_byte
*val
;
2455 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2456 struct value
*arg
= args
[argnum
];
2457 struct type
*arg_type
= check_typedef (value_type (arg
));
2458 int len
= TYPE_LENGTH (arg_type
);
2459 enum type_code typecode
= TYPE_CODE (arg_type
);
2462 fprintf_unfiltered (gdb_stdlog
,
2463 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2464 argnum
+ 1, len
, (int) typecode
);
2466 /* The EABI passes structures that do not fit in a register by
2468 if (len
> mips_abi_regsize (gdbarch
)
2469 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2471 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2472 VALUE_ADDRESS (arg
));
2473 typecode
= TYPE_CODE_PTR
;
2474 len
= mips_abi_regsize (gdbarch
);
2477 fprintf_unfiltered (gdb_stdlog
, " push");
2480 val
= value_contents (arg
);
2482 /* 32-bit ABIs always start floating point arguments in an
2483 even-numbered floating point register. Round the FP register
2484 up before the check to see if there are any FP registers
2485 left. Non MIPS_EABI targets also pass the FP in the integer
2486 registers so also round up normal registers. */
2487 if (mips_abi_regsize (gdbarch
) < 8
2488 && fp_register_arg_p (typecode
, arg_type
))
2490 if ((float_argreg
& 1))
2494 /* Floating point arguments passed in registers have to be
2495 treated specially. On 32-bit architectures, doubles
2496 are passed in register pairs; the even register gets
2497 the low word, and the odd register gets the high word.
2498 On non-EABI processors, the first two floating point arguments are
2499 also copied to general registers, because MIPS16 functions
2500 don't use float registers for arguments. This duplication of
2501 arguments in general registers can't hurt non-MIPS16 functions
2502 because those registers are normally skipped. */
2503 /* MIPS_EABI squeezes a struct that contains a single floating
2504 point value into an FP register instead of pushing it onto the
2506 if (fp_register_arg_p (typecode
, arg_type
)
2507 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2509 /* EABI32 will pass doubles in consecutive registers, even on
2510 64-bit cores. At one time, we used to check the size of
2511 `float_argreg' to determine whether or not to pass doubles
2512 in consecutive registers, but this is not sufficient for
2513 making the ABI determination. */
2514 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2516 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2517 unsigned long regval
;
2519 /* Write the low word of the double to the even register(s). */
2520 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2522 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2523 float_argreg
, phex (regval
, 4));
2524 write_register (float_argreg
++, regval
);
2526 /* Write the high word of the double to the odd register(s). */
2527 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2529 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2530 float_argreg
, phex (regval
, 4));
2531 write_register (float_argreg
++, regval
);
2535 /* This is a floating point value that fits entirely
2536 in a single register. */
2537 /* On 32 bit ABI's the float_argreg is further adjusted
2538 above to ensure that it is even register aligned. */
2539 LONGEST regval
= extract_unsigned_integer (val
, len
);
2541 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2542 float_argreg
, phex (regval
, len
));
2543 write_register (float_argreg
++, regval
);
2548 /* Copy the argument to general registers or the stack in
2549 register-sized pieces. Large arguments are split between
2550 registers and stack. */
2551 /* Note: structs whose size is not a multiple of
2552 mips_abi_regsize() are treated specially: Irix cc passes
2553 them in registers where gcc sometimes puts them on the
2554 stack. For maximum compatibility, we will put them in
2556 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2557 && (len
% mips_abi_regsize (gdbarch
) != 0));
2559 /* Note: Floating-point values that didn't fit into an FP
2560 register are only written to memory. */
2563 /* Remember if the argument was written to the stack. */
2564 int stack_used_p
= 0;
2565 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2566 ? len
: mips_abi_regsize (gdbarch
));
2569 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2572 /* Write this portion of the argument to the stack. */
2573 if (argreg
> MIPS_LAST_ARG_REGNUM
2575 || fp_register_arg_p (typecode
, arg_type
))
2577 /* Should shorter than int integer values be
2578 promoted to int before being stored? */
2579 int longword_offset
= 0;
2582 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2584 if (mips_stack_argsize (gdbarch
) == 8
2585 && (typecode
== TYPE_CODE_INT
2586 || typecode
== TYPE_CODE_PTR
2587 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2588 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2589 else if ((typecode
== TYPE_CODE_STRUCT
2590 || typecode
== TYPE_CODE_UNION
)
2591 && (TYPE_LENGTH (arg_type
)
2592 < mips_stack_argsize (gdbarch
)))
2593 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2598 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2599 paddr_nz (stack_offset
));
2600 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2601 paddr_nz (longword_offset
));
2604 addr
= sp
+ stack_offset
+ longword_offset
;
2609 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2611 for (i
= 0; i
< partial_len
; i
++)
2613 fprintf_unfiltered (gdb_stdlog
, "%02x",
2617 write_memory (addr
, val
, partial_len
);
2620 /* Note!!! This is NOT an else clause. Odd sized
2621 structs may go thru BOTH paths. Floating point
2622 arguments will not. */
2623 /* Write this portion of the argument to a general
2624 purpose register. */
2625 if (argreg
<= MIPS_LAST_ARG_REGNUM
2626 && !fp_register_arg_p (typecode
, arg_type
))
2629 extract_unsigned_integer (val
, partial_len
);
2632 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2635 mips_abi_regsize (gdbarch
)));
2636 write_register (argreg
, regval
);
2643 /* Compute the the offset into the stack at which we
2644 will copy the next parameter.
2646 In the new EABI (and the NABI32), the stack_offset
2647 only needs to be adjusted when it has been used. */
2650 stack_offset
+= align_up (partial_len
,
2651 mips_stack_argsize (gdbarch
));
2655 fprintf_unfiltered (gdb_stdlog
, "\n");
2658 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2660 /* Return adjusted stack pointer. */
2664 /* Determine the return value convention being used. */
2666 static enum return_value_convention
2667 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2668 struct type
*type
, struct regcache
*regcache
,
2669 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2671 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2672 return RETURN_VALUE_STRUCT_CONVENTION
;
2674 memset (readbuf
, 0, TYPE_LENGTH (type
));
2675 return RETURN_VALUE_REGISTER_CONVENTION
;
2679 /* N32/N64 ABI stuff. */
2682 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2683 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2684 int nargs
, struct value
**args
, CORE_ADDR sp
,
2685 int struct_return
, CORE_ADDR struct_addr
)
2691 int stack_offset
= 0;
2692 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2693 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2695 /* For shared libraries, "t9" needs to point at the function
2697 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2699 /* Set the return address register to point to the entry point of
2700 the program, where a breakpoint lies in wait. */
2701 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2703 /* First ensure that the stack and structure return address (if any)
2704 are properly aligned. The stack has to be at least 64-bit
2705 aligned even on 32-bit machines, because doubles must be 64-bit
2706 aligned. For n32 and n64, stack frames need to be 128-bit
2707 aligned, so we round to this widest known alignment. */
2709 sp
= align_down (sp
, 16);
2710 struct_addr
= align_down (struct_addr
, 16);
2712 /* Now make space on the stack for the args. */
2713 for (argnum
= 0; argnum
< nargs
; argnum
++)
2714 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2715 mips_stack_argsize (gdbarch
));
2716 sp
-= align_up (len
, 16);
2719 fprintf_unfiltered (gdb_stdlog
,
2720 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2721 paddr_nz (sp
), (long) align_up (len
, 16));
2723 /* Initialize the integer and float register pointers. */
2724 argreg
= MIPS_A0_REGNUM
;
2725 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2727 /* The struct_return pointer occupies the first parameter-passing reg. */
2731 fprintf_unfiltered (gdb_stdlog
,
2732 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2733 argreg
, paddr_nz (struct_addr
));
2734 write_register (argreg
++, struct_addr
);
2737 /* Now load as many as possible of the first arguments into
2738 registers, and push the rest onto the stack. Loop thru args
2739 from first to last. */
2740 for (argnum
= 0; argnum
< nargs
; argnum
++)
2742 const gdb_byte
*val
;
2743 struct value
*arg
= args
[argnum
];
2744 struct type
*arg_type
= check_typedef (value_type (arg
));
2745 int len
= TYPE_LENGTH (arg_type
);
2746 enum type_code typecode
= TYPE_CODE (arg_type
);
2749 fprintf_unfiltered (gdb_stdlog
,
2750 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2751 argnum
+ 1, len
, (int) typecode
);
2753 val
= value_contents (arg
);
2755 if (fp_register_arg_p (typecode
, arg_type
)
2756 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2758 /* This is a floating point value that fits entirely
2759 in a single register. */
2760 /* On 32 bit ABI's the float_argreg is further adjusted
2761 above to ensure that it is even register aligned. */
2762 LONGEST regval
= extract_unsigned_integer (val
, len
);
2764 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2765 float_argreg
, phex (regval
, len
));
2766 write_register (float_argreg
++, regval
);
2769 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2770 argreg
, phex (regval
, len
));
2771 write_register (argreg
, regval
);
2776 /* Copy the argument to general registers or the stack in
2777 register-sized pieces. Large arguments are split between
2778 registers and stack. */
2779 /* Note: structs whose size is not a multiple of
2780 mips_abi_regsize() are treated specially: Irix cc passes
2781 them in registers where gcc sometimes puts them on the
2782 stack. For maximum compatibility, we will put them in
2784 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2785 && (len
% mips_abi_regsize (gdbarch
) != 0));
2786 /* Note: Floating-point values that didn't fit into an FP
2787 register are only written to memory. */
2790 /* Remember if the argument was written to the stack. */
2791 int stack_used_p
= 0;
2792 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2793 ? len
: mips_abi_regsize (gdbarch
));
2796 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2799 /* Write this portion of the argument to the stack. */
2800 if (argreg
> MIPS_LAST_ARG_REGNUM
2802 || fp_register_arg_p (typecode
, arg_type
))
2804 /* Should shorter than int integer values be
2805 promoted to int before being stored? */
2806 int longword_offset
= 0;
2809 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2811 if (mips_stack_argsize (gdbarch
) == 8
2812 && (typecode
== TYPE_CODE_INT
2813 || typecode
== TYPE_CODE_PTR
2814 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2815 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2820 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2821 paddr_nz (stack_offset
));
2822 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2823 paddr_nz (longword_offset
));
2826 addr
= sp
+ stack_offset
+ longword_offset
;
2831 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2833 for (i
= 0; i
< partial_len
; i
++)
2835 fprintf_unfiltered (gdb_stdlog
, "%02x",
2839 write_memory (addr
, val
, partial_len
);
2842 /* Note!!! This is NOT an else clause. Odd sized
2843 structs may go thru BOTH paths. Floating point
2844 arguments will not. */
2845 /* Write this portion of the argument to a general
2846 purpose register. */
2847 if (argreg
<= MIPS_LAST_ARG_REGNUM
2848 && !fp_register_arg_p (typecode
, arg_type
))
2851 extract_unsigned_integer (val
, partial_len
);
2853 /* A non-floating-point argument being passed in a
2854 general register. If a struct or union, and if
2855 the remaining length is smaller than the register
2856 size, we have to adjust the register value on
2859 It does not seem to be necessary to do the
2860 same for integral types.
2862 cagney/2001-07-23: gdb/179: Also, GCC, when
2863 outputting LE O32 with sizeof (struct) <
2864 mips_abi_regsize(), generates a left shift
2865 as part of storing the argument in a register
2866 (the left shift isn't generated when
2867 sizeof (struct) >= mips_abi_regsize()). Since
2868 it is quite possible that this is GCC
2869 contradicting the LE/O32 ABI, GDB has not been
2870 adjusted to accommodate this. Either someone
2871 needs to demonstrate that the LE/O32 ABI
2872 specifies such a left shift OR this new ABI gets
2873 identified as such and GDB gets tweaked
2876 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2877 && partial_len
< mips_abi_regsize (gdbarch
)
2878 && (typecode
== TYPE_CODE_STRUCT
2879 || typecode
== TYPE_CODE_UNION
))
2880 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
)
2884 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2887 mips_abi_regsize (gdbarch
)));
2888 write_register (argreg
, regval
);
2895 /* Compute the the offset into the stack at which we
2896 will copy the next parameter.
2898 In N32 (N64?), the stack_offset only needs to be
2899 adjusted when it has been used. */
2902 stack_offset
+= align_up (partial_len
,
2903 mips_stack_argsize (gdbarch
));
2907 fprintf_unfiltered (gdb_stdlog
, "\n");
2910 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2912 /* Return adjusted stack pointer. */
2916 static enum return_value_convention
2917 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2918 struct type
*type
, struct regcache
*regcache
,
2919 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2921 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2922 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2923 || TYPE_CODE (type
) == TYPE_CODE_UNION
2924 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2925 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2926 return RETURN_VALUE_STRUCT_CONVENTION
;
2927 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2928 && TYPE_LENGTH (type
) == 16
2929 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2931 /* A 128-bit floating-point value fills both $f0 and $f2. The
2932 two registers are used in the same as memory order, so the
2933 eight bytes with the lower memory address are in $f0. */
2935 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2936 mips_xfer_register (regcache
,
2937 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2938 8, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2939 mips_xfer_register (regcache
,
2940 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 2,
2941 8, TARGET_BYTE_ORDER
, readbuf
? readbuf
+ 8 : readbuf
,
2942 writebuf
? writebuf
+ 8 : writebuf
, 0);
2943 return RETURN_VALUE_REGISTER_CONVENTION
;
2945 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2946 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2948 /* A floating-point value belongs in the least significant part
2951 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2952 mips_xfer_register (regcache
,
2953 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2955 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2956 return RETURN_VALUE_REGISTER_CONVENTION
;
2958 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2959 && TYPE_NFIELDS (type
) <= 2
2960 && TYPE_NFIELDS (type
) >= 1
2961 && ((TYPE_NFIELDS (type
) == 1
2962 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2964 || (TYPE_NFIELDS (type
) == 2
2965 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2967 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2969 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2971 /* A struct that contains one or two floats. Each value is part
2972 in the least significant part of their floating point
2976 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2977 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2979 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2982 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2984 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2985 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2986 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2988 return RETURN_VALUE_REGISTER_CONVENTION
;
2990 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2991 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2993 /* A structure or union. Extract the left justified value,
2994 regardless of the byte order. I.e. DO NOT USE
2998 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2999 offset
< TYPE_LENGTH (type
);
3000 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3002 int xfer
= register_size (current_gdbarch
, regnum
);
3003 if (offset
+ xfer
> TYPE_LENGTH (type
))
3004 xfer
= TYPE_LENGTH (type
) - offset
;
3006 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3007 offset
, xfer
, regnum
);
3008 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3009 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3011 return RETURN_VALUE_REGISTER_CONVENTION
;
3015 /* A scalar extract each part but least-significant-byte
3019 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3020 offset
< TYPE_LENGTH (type
);
3021 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3023 int xfer
= register_size (current_gdbarch
, regnum
);
3024 if (offset
+ xfer
> TYPE_LENGTH (type
))
3025 xfer
= TYPE_LENGTH (type
) - offset
;
3027 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3028 offset
, xfer
, regnum
);
3029 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3030 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3032 return RETURN_VALUE_REGISTER_CONVENTION
;
3036 /* O32 ABI stuff. */
3039 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3040 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3041 int nargs
, struct value
**args
, CORE_ADDR sp
,
3042 int struct_return
, CORE_ADDR struct_addr
)
3048 int stack_offset
= 0;
3049 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3050 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3052 /* For shared libraries, "t9" needs to point at the function
3054 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3056 /* Set the return address register to point to the entry point of
3057 the program, where a breakpoint lies in wait. */
3058 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3060 /* First ensure that the stack and structure return address (if any)
3061 are properly aligned. The stack has to be at least 64-bit
3062 aligned even on 32-bit machines, because doubles must be 64-bit
3063 aligned. For n32 and n64, stack frames need to be 128-bit
3064 aligned, so we round to this widest known alignment. */
3066 sp
= align_down (sp
, 16);
3067 struct_addr
= align_down (struct_addr
, 16);
3069 /* Now make space on the stack for the args. */
3070 for (argnum
= 0; argnum
< nargs
; argnum
++)
3072 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3073 int arglen
= TYPE_LENGTH (arg_type
);
3075 /* Align to double-word if necessary. */
3076 if (mips_type_needs_double_align (arg_type
))
3077 len
= align_up (len
, mips_stack_argsize (gdbarch
) * 2);
3078 /* Allocate space on the stack. */
3079 len
+= align_up (arglen
, mips_stack_argsize (gdbarch
));
3081 sp
-= align_up (len
, 16);
3084 fprintf_unfiltered (gdb_stdlog
,
3085 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3086 paddr_nz (sp
), (long) align_up (len
, 16));
3088 /* Initialize the integer and float register pointers. */
3089 argreg
= MIPS_A0_REGNUM
;
3090 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3092 /* The struct_return pointer occupies the first parameter-passing reg. */
3096 fprintf_unfiltered (gdb_stdlog
,
3097 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3098 argreg
, paddr_nz (struct_addr
));
3099 write_register (argreg
++, struct_addr
);
3100 stack_offset
+= mips_stack_argsize (gdbarch
);
3103 /* Now load as many as possible of the first arguments into
3104 registers, and push the rest onto the stack. Loop thru args
3105 from first to last. */
3106 for (argnum
= 0; argnum
< nargs
; argnum
++)
3108 const gdb_byte
*val
;
3109 struct value
*arg
= args
[argnum
];
3110 struct type
*arg_type
= check_typedef (value_type (arg
));
3111 int len
= TYPE_LENGTH (arg_type
);
3112 enum type_code typecode
= TYPE_CODE (arg_type
);
3115 fprintf_unfiltered (gdb_stdlog
,
3116 "mips_o32_push_dummy_call: %d len=%d type=%d",
3117 argnum
+ 1, len
, (int) typecode
);
3119 val
= value_contents (arg
);
3121 /* 32-bit ABIs always start floating point arguments in an
3122 even-numbered floating point register. Round the FP register
3123 up before the check to see if there are any FP registers
3124 left. O32/O64 targets also pass the FP in the integer
3125 registers so also round up normal registers. */
3126 if (fp_register_arg_p (typecode
, arg_type
))
3128 if ((float_argreg
& 1))
3132 /* Floating point arguments passed in registers have to be
3133 treated specially. On 32-bit architectures, doubles
3134 are passed in register pairs; the even register gets
3135 the low word, and the odd register gets the high word.
3136 On O32/O64, the first two floating point arguments are
3137 also copied to general registers, because MIPS16 functions
3138 don't use float registers for arguments. This duplication of
3139 arguments in general registers can't hurt non-MIPS16 functions
3140 because those registers are normally skipped. */
3142 if (fp_register_arg_p (typecode
, arg_type
)
3143 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3145 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3147 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3148 unsigned long regval
;
3150 /* Write the low word of the double to the even register(s). */
3151 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3153 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3154 float_argreg
, phex (regval
, 4));
3155 write_register (float_argreg
++, regval
);
3157 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3158 argreg
, phex (regval
, 4));
3159 write_register (argreg
++, regval
);
3161 /* Write the high word of the double to the odd register(s). */
3162 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3164 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3165 float_argreg
, phex (regval
, 4));
3166 write_register (float_argreg
++, regval
);
3169 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3170 argreg
, phex (regval
, 4));
3171 write_register (argreg
++, regval
);
3175 /* This is a floating point value that fits entirely
3176 in a single register. */
3177 /* On 32 bit ABI's the float_argreg is further adjusted
3178 above to ensure that it is even register aligned. */
3179 LONGEST regval
= extract_unsigned_integer (val
, len
);
3181 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3182 float_argreg
, phex (regval
, len
));
3183 write_register (float_argreg
++, regval
);
3184 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3185 registers for each argument. The below is (my
3186 guess) to ensure that the corresponding integer
3187 register has reserved the same space. */
3189 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3190 argreg
, phex (regval
, len
));
3191 write_register (argreg
, regval
);
3194 /* Reserve space for the FP register. */
3195 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3199 /* Copy the argument to general registers or the stack in
3200 register-sized pieces. Large arguments are split between
3201 registers and stack. */
3202 /* Note: structs whose size is not a multiple of
3203 mips_abi_regsize() are treated specially: Irix cc passes
3204 them in registers where gcc sometimes puts them on the
3205 stack. For maximum compatibility, we will put them in
3207 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3208 && (len
% mips_abi_regsize (gdbarch
) != 0));
3209 /* Structures should be aligned to eight bytes (even arg registers)
3210 on MIPS_ABI_O32, if their first member has double precision. */
3211 if (mips_type_needs_double_align (arg_type
))
3216 stack_offset
+= mips_abi_regsize (gdbarch
);
3221 /* Remember if the argument was written to the stack. */
3222 int stack_used_p
= 0;
3223 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3224 ? len
: mips_abi_regsize (gdbarch
));
3227 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3230 /* Write this portion of the argument to the stack. */
3231 if (argreg
> MIPS_LAST_ARG_REGNUM
3232 || odd_sized_struct
)
3234 /* Should shorter than int integer values be
3235 promoted to int before being stored? */
3236 int longword_offset
= 0;
3239 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3241 if (mips_stack_argsize (gdbarch
) == 8
3242 && (typecode
== TYPE_CODE_INT
3243 || typecode
== TYPE_CODE_PTR
3244 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3245 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3250 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3251 paddr_nz (stack_offset
));
3252 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3253 paddr_nz (longword_offset
));
3256 addr
= sp
+ stack_offset
+ longword_offset
;
3261 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3263 for (i
= 0; i
< partial_len
; i
++)
3265 fprintf_unfiltered (gdb_stdlog
, "%02x",
3269 write_memory (addr
, val
, partial_len
);
3272 /* Note!!! This is NOT an else clause. Odd sized
3273 structs may go thru BOTH paths. */
3274 /* Write this portion of the argument to a general
3275 purpose register. */
3276 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3278 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3279 /* Value may need to be sign extended, because
3280 mips_isa_regsize() != mips_abi_regsize(). */
3282 /* A non-floating-point argument being passed in a
3283 general register. If a struct or union, and if
3284 the remaining length is smaller than the register
3285 size, we have to adjust the register value on
3288 It does not seem to be necessary to do the
3289 same for integral types.
3291 Also don't do this adjustment on O64 binaries.
3293 cagney/2001-07-23: gdb/179: Also, GCC, when
3294 outputting LE O32 with sizeof (struct) <
3295 mips_abi_regsize(), generates a left shift
3296 as part of storing the argument in a register
3297 (the left shift isn't generated when
3298 sizeof (struct) >= mips_abi_regsize()). Since
3299 it is quite possible that this is GCC
3300 contradicting the LE/O32 ABI, GDB has not been
3301 adjusted to accommodate this. Either someone
3302 needs to demonstrate that the LE/O32 ABI
3303 specifies such a left shift OR this new ABI gets
3304 identified as such and GDB gets tweaked
3307 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3308 && partial_len
< mips_abi_regsize (gdbarch
)
3309 && (typecode
== TYPE_CODE_STRUCT
3310 || typecode
== TYPE_CODE_UNION
))
3311 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
)
3315 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3318 mips_abi_regsize (gdbarch
)));
3319 write_register (argreg
, regval
);
3322 /* Prevent subsequent floating point arguments from
3323 being passed in floating point registers. */
3324 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3330 /* Compute the the offset into the stack at which we
3331 will copy the next parameter.
3333 In older ABIs, the caller reserved space for
3334 registers that contained arguments. This was loosely
3335 refered to as their "home". Consequently, space is
3336 always allocated. */
3338 stack_offset
+= align_up (partial_len
,
3339 mips_stack_argsize (gdbarch
));
3343 fprintf_unfiltered (gdb_stdlog
, "\n");
3346 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3348 /* Return adjusted stack pointer. */
3352 static enum return_value_convention
3353 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3354 struct regcache
*regcache
,
3355 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3357 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3359 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3360 || TYPE_CODE (type
) == TYPE_CODE_UNION
3361 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3362 return RETURN_VALUE_STRUCT_CONVENTION
;
3363 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3364 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3366 /* A single-precision floating-point value. It fits in the
3367 least significant part of FP0. */
3369 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3370 mips_xfer_register (regcache
,
3371 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3373 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3374 return RETURN_VALUE_REGISTER_CONVENTION
;
3376 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3377 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3379 /* A double-precision floating-point value. The most
3380 significant part goes in FP1, and the least significant in
3383 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3384 switch (TARGET_BYTE_ORDER
)
3386 case BFD_ENDIAN_LITTLE
:
3387 mips_xfer_register (regcache
,
3388 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3389 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3390 mips_xfer_register (regcache
,
3391 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3392 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3394 case BFD_ENDIAN_BIG
:
3395 mips_xfer_register (regcache
,
3396 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3397 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3398 mips_xfer_register (regcache
,
3399 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3400 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3403 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3405 return RETURN_VALUE_REGISTER_CONVENTION
;
3408 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3409 && TYPE_NFIELDS (type
) <= 2
3410 && TYPE_NFIELDS (type
) >= 1
3411 && ((TYPE_NFIELDS (type
) == 1
3412 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3414 || (TYPE_NFIELDS (type
) == 2
3415 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3417 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3419 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3421 /* A struct that contains one or two floats. Each value is part
3422 in the least significant part of their floating point
3424 gdb_byte reg
[MAX_REGISTER_SIZE
];
3427 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3428 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3430 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3433 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3435 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3436 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3437 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3439 return RETURN_VALUE_REGISTER_CONVENTION
;
3443 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3444 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3446 /* A structure or union. Extract the left justified value,
3447 regardless of the byte order. I.e. DO NOT USE
3451 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3452 offset
< TYPE_LENGTH (type
);
3453 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3455 int xfer
= register_size (current_gdbarch
, regnum
);
3456 if (offset
+ xfer
> TYPE_LENGTH (type
))
3457 xfer
= TYPE_LENGTH (type
) - offset
;
3459 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3460 offset
, xfer
, regnum
);
3461 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3462 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3464 return RETURN_VALUE_REGISTER_CONVENTION
;
3469 /* A scalar extract each part but least-significant-byte
3470 justified. o32 thinks registers are 4 byte, regardless of
3471 the ISA. mips_stack_argsize controls this. */
3474 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3475 offset
< TYPE_LENGTH (type
);
3476 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3478 int xfer
= mips_stack_argsize (gdbarch
);
3479 if (offset
+ xfer
> TYPE_LENGTH (type
))
3480 xfer
= TYPE_LENGTH (type
) - offset
;
3482 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3483 offset
, xfer
, regnum
);
3484 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3485 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3487 return RETURN_VALUE_REGISTER_CONVENTION
;
3491 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3495 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3496 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3498 struct value
**args
, CORE_ADDR sp
,
3499 int struct_return
, CORE_ADDR struct_addr
)
3505 int stack_offset
= 0;
3506 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3507 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3509 /* For shared libraries, "t9" needs to point at the function
3511 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3513 /* Set the return address register to point to the entry point of
3514 the program, where a breakpoint lies in wait. */
3515 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3517 /* First ensure that the stack and structure return address (if any)
3518 are properly aligned. The stack has to be at least 64-bit
3519 aligned even on 32-bit machines, because doubles must be 64-bit
3520 aligned. For n32 and n64, stack frames need to be 128-bit
3521 aligned, so we round to this widest known alignment. */
3523 sp
= align_down (sp
, 16);
3524 struct_addr
= align_down (struct_addr
, 16);
3526 /* Now make space on the stack for the args. */
3527 for (argnum
= 0; argnum
< nargs
; argnum
++)
3529 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3530 int arglen
= TYPE_LENGTH (arg_type
);
3532 /* Allocate space on the stack. */
3533 len
+= align_up (arglen
, mips_stack_argsize (gdbarch
));
3535 sp
-= align_up (len
, 16);
3538 fprintf_unfiltered (gdb_stdlog
,
3539 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3540 paddr_nz (sp
), (long) align_up (len
, 16));
3542 /* Initialize the integer and float register pointers. */
3543 argreg
= MIPS_A0_REGNUM
;
3544 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3546 /* The struct_return pointer occupies the first parameter-passing reg. */
3550 fprintf_unfiltered (gdb_stdlog
,
3551 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3552 argreg
, paddr_nz (struct_addr
));
3553 write_register (argreg
++, struct_addr
);
3554 stack_offset
+= mips_stack_argsize (gdbarch
);
3557 /* Now load as many as possible of the first arguments into
3558 registers, and push the rest onto the stack. Loop thru args
3559 from first to last. */
3560 for (argnum
= 0; argnum
< nargs
; argnum
++)
3562 const gdb_byte
*val
;
3563 struct value
*arg
= args
[argnum
];
3564 struct type
*arg_type
= check_typedef (value_type (arg
));
3565 int len
= TYPE_LENGTH (arg_type
);
3566 enum type_code typecode
= TYPE_CODE (arg_type
);
3569 fprintf_unfiltered (gdb_stdlog
,
3570 "mips_o64_push_dummy_call: %d len=%d type=%d",
3571 argnum
+ 1, len
, (int) typecode
);
3573 val
= value_contents (arg
);
3575 /* Floating point arguments passed in registers have to be
3576 treated specially. On 32-bit architectures, doubles
3577 are passed in register pairs; the even register gets
3578 the low word, and the odd register gets the high word.
3579 On O32/O64, the first two floating point arguments are
3580 also copied to general registers, because MIPS16 functions
3581 don't use float registers for arguments. This duplication of
3582 arguments in general registers can't hurt non-MIPS16 functions
3583 because those registers are normally skipped. */
3585 if (fp_register_arg_p (typecode
, arg_type
)
3586 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3588 LONGEST regval
= extract_unsigned_integer (val
, len
);
3590 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3591 float_argreg
, phex (regval
, len
));
3592 write_register (float_argreg
++, regval
);
3594 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3595 argreg
, phex (regval
, len
));
3596 write_register (argreg
, regval
);
3598 /* Reserve space for the FP register. */
3599 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3603 /* Copy the argument to general registers or the stack in
3604 register-sized pieces. Large arguments are split between
3605 registers and stack. */
3606 /* Note: structs whose size is not a multiple of
3607 mips_abi_regsize() are treated specially: Irix cc passes
3608 them in registers where gcc sometimes puts them on the
3609 stack. For maximum compatibility, we will put them in
3611 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3612 && (len
% mips_abi_regsize (gdbarch
) != 0));
3615 /* Remember if the argument was written to the stack. */
3616 int stack_used_p
= 0;
3617 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3618 ? len
: mips_abi_regsize (gdbarch
));
3621 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3624 /* Write this portion of the argument to the stack. */
3625 if (argreg
> MIPS_LAST_ARG_REGNUM
3626 || odd_sized_struct
)
3628 /* Should shorter than int integer values be
3629 promoted to int before being stored? */
3630 int longword_offset
= 0;
3633 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3635 if (mips_stack_argsize (gdbarch
) == 8
3636 && (typecode
== TYPE_CODE_INT
3637 || typecode
== TYPE_CODE_PTR
3638 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3639 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3644 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3645 paddr_nz (stack_offset
));
3646 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3647 paddr_nz (longword_offset
));
3650 addr
= sp
+ stack_offset
+ longword_offset
;
3655 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3657 for (i
= 0; i
< partial_len
; i
++)
3659 fprintf_unfiltered (gdb_stdlog
, "%02x",
3663 write_memory (addr
, val
, partial_len
);
3666 /* Note!!! This is NOT an else clause. Odd sized
3667 structs may go thru BOTH paths. */
3668 /* Write this portion of the argument to a general
3669 purpose register. */
3670 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3672 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3673 /* Value may need to be sign extended, because
3674 mips_isa_regsize() != mips_abi_regsize(). */
3676 /* A non-floating-point argument being passed in a
3677 general register. If a struct or union, and if
3678 the remaining length is smaller than the register
3679 size, we have to adjust the register value on
3682 It does not seem to be necessary to do the
3683 same for integral types. */
3685 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3686 && partial_len
< mips_abi_regsize (gdbarch
)
3687 && (typecode
== TYPE_CODE_STRUCT
3688 || typecode
== TYPE_CODE_UNION
))
3689 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
)
3693 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3696 mips_abi_regsize (gdbarch
)));
3697 write_register (argreg
, regval
);
3700 /* Prevent subsequent floating point arguments from
3701 being passed in floating point registers. */
3702 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3708 /* Compute the the offset into the stack at which we
3709 will copy the next parameter.
3711 In older ABIs, the caller reserved space for
3712 registers that contained arguments. This was loosely
3713 refered to as their "home". Consequently, space is
3714 always allocated. */
3716 stack_offset
+= align_up (partial_len
,
3717 mips_stack_argsize (gdbarch
));
3721 fprintf_unfiltered (gdb_stdlog
, "\n");
3724 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3726 /* Return adjusted stack pointer. */
3730 static enum return_value_convention
3731 mips_o64_return_value (struct gdbarch
*gdbarch
,
3732 struct type
*type
, struct regcache
*regcache
,
3733 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3735 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3737 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3738 || TYPE_CODE (type
) == TYPE_CODE_UNION
3739 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3740 return RETURN_VALUE_STRUCT_CONVENTION
;
3741 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3743 /* A floating-point value. It fits in the least significant
3746 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3747 mips_xfer_register (regcache
,
3748 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3750 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3751 return RETURN_VALUE_REGISTER_CONVENTION
;
3755 /* A scalar extract each part but least-significant-byte
3759 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3760 offset
< TYPE_LENGTH (type
);
3761 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3763 int xfer
= mips_stack_argsize (gdbarch
);
3764 if (offset
+ xfer
> TYPE_LENGTH (type
))
3765 xfer
= TYPE_LENGTH (type
) - offset
;
3767 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3768 offset
, xfer
, regnum
);
3769 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3770 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3772 return RETURN_VALUE_REGISTER_CONVENTION
;
3776 /* Floating point register management.
3778 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3779 64bit operations, these early MIPS cpus treat fp register pairs
3780 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3781 registers and offer a compatibility mode that emulates the MIPS2 fp
3782 model. When operating in MIPS2 fp compat mode, later cpu's split
3783 double precision floats into two 32-bit chunks and store them in
3784 consecutive fp regs. To display 64-bit floats stored in this
3785 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3786 Throw in user-configurable endianness and you have a real mess.
3788 The way this works is:
3789 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3790 double-precision value will be split across two logical registers.
3791 The lower-numbered logical register will hold the low-order bits,
3792 regardless of the processor's endianness.
3793 - If we are on a 64-bit processor, and we are looking for a
3794 single-precision value, it will be in the low ordered bits
3795 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3796 save slot in memory.
3797 - If we are in 64-bit mode, everything is straightforward.
3799 Note that this code only deals with "live" registers at the top of the
3800 stack. We will attempt to deal with saved registers later, when
3801 the raw/cooked register interface is in place. (We need a general
3802 interface that can deal with dynamic saved register sizes -- fp
3803 regs could be 32 bits wide in one frame and 64 on the frame above
3806 static struct type
*
3807 mips_float_register_type (void)
3809 return builtin_type_ieee_single
;
3812 static struct type
*
3813 mips_double_register_type (void)
3815 return builtin_type_ieee_double
;
3818 /* Copy a 32-bit single-precision value from the current frame
3819 into rare_buffer. */
3822 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3823 gdb_byte
*rare_buffer
)
3825 int raw_size
= register_size (current_gdbarch
, regno
);
3826 gdb_byte
*raw_buffer
= alloca (raw_size
);
3828 if (!frame_register_read (frame
, regno
, raw_buffer
))
3829 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3832 /* We have a 64-bit value for this register. Find the low-order
3836 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3841 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3845 memcpy (rare_buffer
, raw_buffer
, 4);
3849 /* Copy a 64-bit double-precision value from the current frame into
3850 rare_buffer. This may include getting half of it from the next
3854 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3855 gdb_byte
*rare_buffer
)
3857 int raw_size
= register_size (current_gdbarch
, regno
);
3859 if (raw_size
== 8 && !mips2_fp_compat ())
3861 /* We have a 64-bit value for this register, and we should use
3863 if (!frame_register_read (frame
, regno
, rare_buffer
))
3864 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3868 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3869 internal_error (__FILE__
, __LINE__
,
3870 _("mips_read_fp_register_double: bad access to "
3871 "odd-numbered FP register"));
3873 /* mips_read_fp_register_single will find the correct 32 bits from
3875 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3877 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3878 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3882 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3883 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3889 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3891 { /* do values for FP (float) regs */
3892 gdb_byte
*raw_buffer
;
3893 double doub
, flt1
; /* doubles extracted from raw hex data */
3896 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3897 mips_regnum (current_gdbarch
)->fp0
));
3899 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3900 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3903 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3905 /* 4-byte registers: Print hex and floating. Also print even
3906 numbered registers as doubles. */
3907 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3908 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3910 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3913 fprintf_filtered (file
, " flt: ");
3915 fprintf_filtered (file
, " <invalid float> ");
3917 fprintf_filtered (file
, "%-17.9g", flt1
);
3919 if (regnum
% 2 == 0)
3921 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3922 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3925 fprintf_filtered (file
, " dbl: ");
3927 fprintf_filtered (file
, "<invalid double>");
3929 fprintf_filtered (file
, "%-24.17g", doub
);
3934 /* Eight byte registers: print each one as hex, float and double. */
3935 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3936 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3938 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3939 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3942 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
3945 fprintf_filtered (file
, " flt: ");
3947 fprintf_filtered (file
, "<invalid float>");
3949 fprintf_filtered (file
, "%-17.9g", flt1
);
3951 fprintf_filtered (file
, " dbl: ");
3953 fprintf_filtered (file
, "<invalid double>");
3955 fprintf_filtered (file
, "%-24.17g", doub
);
3960 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
3961 int regnum
, int all
)
3963 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3964 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
3967 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
3969 mips_print_fp_register (file
, frame
, regnum
);
3973 /* Get the data in raw format. */
3974 if (!frame_register_read (frame
, regnum
, raw_buffer
))
3976 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
3980 fputs_filtered (REGISTER_NAME (regnum
), file
);
3982 /* The problem with printing numeric register names (r26, etc.) is that
3983 the user can't use them on input. Probably the best solution is to
3984 fix it so that either the numeric or the funky (a2, etc.) names
3985 are accepted on input. */
3986 if (regnum
< MIPS_NUMREGS
)
3987 fprintf_filtered (file
, "(r%d): ", regnum
);
3989 fprintf_filtered (file
, ": ");
3991 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3993 register_size (current_gdbarch
,
3994 regnum
) - register_size (current_gdbarch
, regnum
);
3998 print_scalar_formatted (raw_buffer
+ offset
,
3999 register_type (gdbarch
, regnum
), 'x', 0,
4003 /* Replacement for generic do_registers_info.
4004 Print regs in pretty columns. */
4007 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4010 fprintf_filtered (file
, " ");
4011 mips_print_fp_register (file
, frame
, regnum
);
4012 fprintf_filtered (file
, "\n");
4017 /* Print a row's worth of GP (int) registers, with name labels above */
4020 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4023 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4024 /* do values for GP (int) regs */
4025 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4026 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4030 /* For GP registers, we print a separate row of names above the vals */
4031 for (col
= 0, regnum
= start_regnum
;
4032 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4034 if (*REGISTER_NAME (regnum
) == '\0')
4035 continue; /* unused register */
4036 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4038 break; /* end the row: reached FP register */
4040 fprintf_filtered (file
, " ");
4041 fprintf_filtered (file
,
4042 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4043 REGISTER_NAME (regnum
));
4050 /* print the R0 to R31 names */
4051 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4052 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4054 fprintf_filtered (file
, "\n ");
4056 /* now print the values in hex, 4 or 8 to the row */
4057 for (col
= 0, regnum
= start_regnum
;
4058 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4060 if (*REGISTER_NAME (regnum
) == '\0')
4061 continue; /* unused register */
4062 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4064 break; /* end row: reached FP register */
4065 /* OK: get the data in raw format. */
4066 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4067 error (_("can't read register %d (%s)"), regnum
, REGISTER_NAME (regnum
));
4068 /* pad small registers */
4070 byte
< (mips_abi_regsize (current_gdbarch
)
4071 - register_size (current_gdbarch
, regnum
)); byte
++)
4072 printf_filtered (" ");
4073 /* Now print the register value in hex, endian order. */
4074 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4076 register_size (current_gdbarch
,
4077 regnum
) - register_size (current_gdbarch
, regnum
);
4078 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4079 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4081 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4083 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4084 fprintf_filtered (file
, " ");
4087 if (col
> 0) /* ie. if we actually printed anything... */
4088 fprintf_filtered (file
, "\n");
4093 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4096 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4097 struct frame_info
*frame
, int regnum
, int all
)
4099 if (regnum
!= -1) /* do one specified register */
4101 gdb_assert (regnum
>= NUM_REGS
);
4102 if (*(REGISTER_NAME (regnum
)) == '\0')
4103 error (_("Not a valid register for the current processor type"));
4105 mips_print_register (file
, frame
, regnum
, 0);
4106 fprintf_filtered (file
, "\n");
4109 /* do all (or most) registers */
4112 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4114 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4117 if (all
) /* true for "INFO ALL-REGISTERS" command */
4118 regnum
= print_fp_register_row (file
, frame
, regnum
);
4120 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4123 regnum
= print_gp_register_row (file
, frame
, regnum
);
4128 /* Is this a branch with a delay slot? */
4131 is_delayed (unsigned long insn
)
4134 for (i
= 0; i
< NUMOPCODES
; ++i
)
4135 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4136 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4138 return (i
< NUMOPCODES
4139 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4140 | INSN_COND_BRANCH_DELAY
4141 | INSN_COND_BRANCH_LIKELY
)));
4145 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4146 struct frame_info
*frame
)
4148 CORE_ADDR pc
= get_frame_pc (frame
);
4149 gdb_byte buf
[MIPS_INSN32_SIZE
];
4151 /* There is no branch delay slot on MIPS16. */
4152 if (mips_pc_is_mips16 (pc
))
4155 if (!breakpoint_here_p (pc
+ 4))
4158 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4159 /* If error reading memory, guess that it is not a delayed
4162 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4165 /* To skip prologues, I use this predicate. Returns either PC itself
4166 if the code at PC does not look like a function prologue; otherwise
4167 returns an address that (if we're lucky) follows the prologue. If
4168 LENIENT, then we must skip everything which is involved in setting
4169 up the frame (it's OK to skip more, just so long as we don't skip
4170 anything which might clobber the registers which are being saved.
4171 We must skip more in the case where part of the prologue is in the
4172 delay slot of a non-prologue instruction). */
4175 mips_skip_prologue (CORE_ADDR pc
)
4178 CORE_ADDR func_addr
;
4180 /* See if we can determine the end of the prologue via the symbol table.
4181 If so, then return either PC, or the PC after the prologue, whichever
4183 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4185 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4186 if (post_prologue_pc
!= 0)
4187 return max (pc
, post_prologue_pc
);
4190 /* Can't determine prologue from the symbol table, need to examine
4193 /* Find an upper limit on the function prologue using the debug
4194 information. If the debug information could not be used to provide
4195 that bound, then use an arbitrary large number as the upper bound. */
4196 limit_pc
= skip_prologue_using_sal (pc
);
4198 limit_pc
= pc
+ 100; /* Magic. */
4200 if (mips_pc_is_mips16 (pc
))
4201 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4203 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4206 /* Root of all "set mips "/"show mips " commands. This will eventually be
4207 used for all MIPS-specific commands. */
4210 show_mips_command (char *args
, int from_tty
)
4212 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4216 set_mips_command (char *args
, int from_tty
)
4219 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4220 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4223 /* Commands to show/set the MIPS FPU type. */
4226 show_mipsfpu_command (char *args
, int from_tty
)
4229 switch (MIPS_FPU_TYPE
)
4231 case MIPS_FPU_SINGLE
:
4232 fpu
= "single-precision";
4234 case MIPS_FPU_DOUBLE
:
4235 fpu
= "double-precision";
4238 fpu
= "absent (none)";
4241 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4243 if (mips_fpu_type_auto
)
4245 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4249 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4254 set_mipsfpu_command (char *args
, int from_tty
)
4257 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4258 show_mipsfpu_command (args
, from_tty
);
4262 set_mipsfpu_single_command (char *args
, int from_tty
)
4264 struct gdbarch_info info
;
4265 gdbarch_info_init (&info
);
4266 mips_fpu_type
= MIPS_FPU_SINGLE
;
4267 mips_fpu_type_auto
= 0;
4268 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4269 instead of relying on globals. Doing that would let generic code
4270 handle the search for this specific architecture. */
4271 if (!gdbarch_update_p (info
))
4272 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4276 set_mipsfpu_double_command (char *args
, int from_tty
)
4278 struct gdbarch_info info
;
4279 gdbarch_info_init (&info
);
4280 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4281 mips_fpu_type_auto
= 0;
4282 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4283 instead of relying on globals. Doing that would let generic code
4284 handle the search for this specific architecture. */
4285 if (!gdbarch_update_p (info
))
4286 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4290 set_mipsfpu_none_command (char *args
, int from_tty
)
4292 struct gdbarch_info info
;
4293 gdbarch_info_init (&info
);
4294 mips_fpu_type
= MIPS_FPU_NONE
;
4295 mips_fpu_type_auto
= 0;
4296 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4297 instead of relying on globals. Doing that would let generic code
4298 handle the search for this specific architecture. */
4299 if (!gdbarch_update_p (info
))
4300 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4304 set_mipsfpu_auto_command (char *args
, int from_tty
)
4306 mips_fpu_type_auto
= 1;
4309 /* Attempt to identify the particular processor model by reading the
4310 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4311 the relevant processor still exists (it dates back to '94) and
4312 secondly this is not the way to do this. The processor type should
4313 be set by forcing an architecture change. */
4316 deprecated_mips_set_processor_regs_hack (void)
4318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4321 prid
= read_register (MIPS_PRID_REGNUM
);
4323 if ((prid
& ~0xf) == 0x700)
4324 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4327 /* Just like reinit_frame_cache, but with the right arguments to be
4328 callable as an sfunc. */
4331 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4332 struct cmd_list_element
*c
)
4334 reinit_frame_cache ();
4338 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4342 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4343 disassembler needs to be able to locally determine the ISA, and
4344 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4346 if (mips_pc_is_mips16 (memaddr
))
4347 info
->mach
= bfd_mach_mips16
;
4349 /* Round down the instruction address to the appropriate boundary. */
4350 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4352 /* Set the disassembler options. */
4353 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4355 /* Set up the disassembler info, so that we get the right
4356 register names from libopcodes. */
4357 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4358 info
->disassembler_options
= "gpr-names=n32";
4360 info
->disassembler_options
= "gpr-names=64";
4361 info
->flavour
= bfd_target_elf_flavour
;
4364 /* This string is not recognized explicitly by the disassembler,
4365 but it tells the disassembler to not try to guess the ABI from
4366 the bfd elf headers, such that, if the user overrides the ABI
4367 of a program linked as NewABI, the disassembly will follow the
4368 register naming conventions specified by the user. */
4369 info
->disassembler_options
= "gpr-names=32";
4371 /* Call the appropriate disassembler based on the target endian-ness. */
4372 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4373 return print_insn_big_mips (memaddr
, info
);
4375 return print_insn_little_mips (memaddr
, info
);
4378 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4379 counter value to determine whether a 16- or 32-bit breakpoint should be
4380 used. It returns a pointer to a string of bytes that encode a breakpoint
4381 instruction, stores the length of the string to *lenptr, and adjusts pc
4382 (if necessary) to point to the actual memory location where the
4383 breakpoint should be inserted. */
4385 static const gdb_byte
*
4386 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4388 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4390 if (mips_pc_is_mips16 (*pcptr
))
4392 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4393 *pcptr
= unmake_mips16_addr (*pcptr
);
4394 *lenptr
= sizeof (mips16_big_breakpoint
);
4395 return mips16_big_breakpoint
;
4399 /* The IDT board uses an unusual breakpoint value, and
4400 sometimes gets confused when it sees the usual MIPS
4401 breakpoint instruction. */
4402 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4403 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4404 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4406 *lenptr
= sizeof (big_breakpoint
);
4408 if (strcmp (target_shortname
, "mips") == 0)
4409 return idt_big_breakpoint
;
4410 else if (strcmp (target_shortname
, "ddb") == 0
4411 || strcmp (target_shortname
, "pmon") == 0
4412 || strcmp (target_shortname
, "lsi") == 0)
4413 return pmon_big_breakpoint
;
4415 return big_breakpoint
;
4420 if (mips_pc_is_mips16 (*pcptr
))
4422 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4423 *pcptr
= unmake_mips16_addr (*pcptr
);
4424 *lenptr
= sizeof (mips16_little_breakpoint
);
4425 return mips16_little_breakpoint
;
4429 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4430 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4431 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4433 *lenptr
= sizeof (little_breakpoint
);
4435 if (strcmp (target_shortname
, "mips") == 0)
4436 return idt_little_breakpoint
;
4437 else if (strcmp (target_shortname
, "ddb") == 0
4438 || strcmp (target_shortname
, "pmon") == 0
4439 || strcmp (target_shortname
, "lsi") == 0)
4440 return pmon_little_breakpoint
;
4442 return little_breakpoint
;
4447 /* If PC is in a mips16 call or return stub, return the address of the target
4448 PC, which is either the callee or the caller. There are several
4449 cases which must be handled:
4451 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4452 target PC is in $31 ($ra).
4453 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4454 and the target PC is in $2.
4455 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4456 before the jal instruction, this is effectively a call stub
4457 and the the target PC is in $2. Otherwise this is effectively
4458 a return stub and the target PC is in $18.
4460 See the source code for the stubs in gcc/config/mips/mips16.S for
4464 mips_skip_trampoline_code (CORE_ADDR pc
)
4467 CORE_ADDR start_addr
;
4469 /* Find the starting address and name of the function containing the PC. */
4470 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4473 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4474 target PC is in $31 ($ra). */
4475 if (strcmp (name
, "__mips16_ret_sf") == 0
4476 || strcmp (name
, "__mips16_ret_df") == 0)
4477 return read_signed_register (MIPS_RA_REGNUM
);
4479 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4481 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4482 and the target PC is in $2. */
4483 if (name
[19] >= '0' && name
[19] <= '9')
4484 return read_signed_register (2);
4486 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4487 before the jal instruction, this is effectively a call stub
4488 and the the target PC is in $2. Otherwise this is effectively
4489 a return stub and the target PC is in $18. */
4490 else if (name
[19] == 's' || name
[19] == 'd')
4492 if (pc
== start_addr
)
4494 /* Check if the target of the stub is a compiler-generated
4495 stub. Such a stub for a function bar might have a name
4496 like __fn_stub_bar, and might look like this:
4501 la $1,bar (becomes a lui/addiu pair)
4503 So scan down to the lui/addi and extract the target
4504 address from those two instructions. */
4506 CORE_ADDR target_pc
= read_signed_register (2);
4510 /* See if the name of the target function is __fn_stub_*. */
4511 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4514 if (strncmp (name
, "__fn_stub_", 10) != 0
4515 && strcmp (name
, "etext") != 0
4516 && strcmp (name
, "_etext") != 0)
4519 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4520 The limit on the search is arbitrarily set to 20
4521 instructions. FIXME. */
4522 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4524 inst
= mips_fetch_instruction (target_pc
);
4525 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4526 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4527 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4528 return pc
| (inst
& 0xffff); /* low word */
4531 /* Couldn't find the lui/addui pair, so return stub address. */
4535 /* This is the 'return' part of a call stub. The return
4536 address is in $r18. */
4537 return read_signed_register (18);
4540 return 0; /* not a stub */
4543 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4544 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4547 mips_stab_reg_to_regnum (int num
)
4550 if (num
>= 0 && num
< 32)
4552 else if (num
>= 38 && num
< 70)
4553 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4555 regnum
= mips_regnum (current_gdbarch
)->hi
;
4557 regnum
= mips_regnum (current_gdbarch
)->lo
;
4559 /* This will hopefully (eventually) provoke a warning. Should
4560 we be calling complaint() here? */
4561 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4562 return NUM_REGS
+ regnum
;
4566 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4567 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4570 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4573 if (num
>= 0 && num
< 32)
4575 else if (num
>= 32 && num
< 64)
4576 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4578 regnum
= mips_regnum (current_gdbarch
)->hi
;
4580 regnum
= mips_regnum (current_gdbarch
)->lo
;
4582 /* This will hopefully (eventually) provoke a warning. Should we
4583 be calling complaint() here? */
4584 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4585 return NUM_REGS
+ regnum
;
4589 mips_register_sim_regno (int regnum
)
4591 /* Only makes sense to supply raw registers. */
4592 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4593 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4594 decide if it is valid. Should instead define a standard sim/gdb
4595 register numbering scheme. */
4596 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4597 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4600 return LEGACY_SIM_REGNO_IGNORE
;
4604 /* Convert an integer into an address. Extracting the value signed
4605 guarantees a correctly sign extended address. */
4608 mips_integer_to_address (struct gdbarch
*gdbarch
,
4609 struct type
*type
, const gdb_byte
*buf
)
4611 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4615 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4617 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4618 const char *name
= bfd_get_section_name (abfd
, sect
);
4620 if (*abip
!= MIPS_ABI_UNKNOWN
)
4623 if (strncmp (name
, ".mdebug.", 8) != 0)
4626 if (strcmp (name
, ".mdebug.abi32") == 0)
4627 *abip
= MIPS_ABI_O32
;
4628 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4629 *abip
= MIPS_ABI_N32
;
4630 else if (strcmp (name
, ".mdebug.abi64") == 0)
4631 *abip
= MIPS_ABI_N64
;
4632 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4633 *abip
= MIPS_ABI_O64
;
4634 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4635 *abip
= MIPS_ABI_EABI32
;
4636 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4637 *abip
= MIPS_ABI_EABI64
;
4639 warning (_("unsupported ABI %s."), name
+ 8);
4643 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4645 int *lbp
= (int *) obj
;
4646 const char *name
= bfd_get_section_name (abfd
, sect
);
4648 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4650 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4652 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4653 warning (_("unrecognized .gcc_compiled_longXX"));
4656 static enum mips_abi
4657 global_mips_abi (void)
4661 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4662 if (mips_abi_strings
[i
] == mips_abi_string
)
4663 return (enum mips_abi
) i
;
4665 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4669 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4671 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4673 if (tdesc_gp32
== NULL
)
4675 /* Create feature sets with the appropriate properties. The values
4676 are not important. */
4678 tdesc_gp32
= allocate_target_description ();
4679 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4681 tdesc_gp64
= allocate_target_description ();
4682 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4685 /* If the size matches the set of 32-bit or 64-bit integer registers,
4686 assume that's what we've got. */
4687 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4688 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4690 /* If the size matches the full set of registers GDB traditionally
4691 knows about, including floating point, for either 32-bit or
4692 64-bit, assume that's what we've got. */
4693 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4694 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4696 /* Otherwise we don't have a useful guess. */
4699 static struct gdbarch
*
4700 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4702 struct gdbarch
*gdbarch
;
4703 struct gdbarch_tdep
*tdep
;
4705 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4707 enum mips_fpu_type fpu_type
;
4709 /* First of all, extract the elf_flags, if available. */
4710 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4711 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4712 else if (arches
!= NULL
)
4713 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4717 fprintf_unfiltered (gdb_stdlog
,
4718 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4720 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4721 switch ((elf_flags
& EF_MIPS_ABI
))
4723 case E_MIPS_ABI_O32
:
4724 found_abi
= MIPS_ABI_O32
;
4726 case E_MIPS_ABI_O64
:
4727 found_abi
= MIPS_ABI_O64
;
4729 case E_MIPS_ABI_EABI32
:
4730 found_abi
= MIPS_ABI_EABI32
;
4732 case E_MIPS_ABI_EABI64
:
4733 found_abi
= MIPS_ABI_EABI64
;
4736 if ((elf_flags
& EF_MIPS_ABI2
))
4737 found_abi
= MIPS_ABI_N32
;
4739 found_abi
= MIPS_ABI_UNKNOWN
;
4743 /* GCC creates a pseudo-section whose name describes the ABI. */
4744 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4745 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4747 /* If we have no useful BFD information, use the ABI from the last
4748 MIPS architecture (if there is one). */
4749 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4750 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4752 /* Try the architecture for any hint of the correct ABI. */
4753 if (found_abi
== MIPS_ABI_UNKNOWN
4754 && info
.bfd_arch_info
!= NULL
4755 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4757 switch (info
.bfd_arch_info
->mach
)
4759 case bfd_mach_mips3900
:
4760 found_abi
= MIPS_ABI_EABI32
;
4762 case bfd_mach_mips4100
:
4763 case bfd_mach_mips5000
:
4764 found_abi
= MIPS_ABI_EABI64
;
4766 case bfd_mach_mips8000
:
4767 case bfd_mach_mips10000
:
4768 /* On Irix, ELF64 executables use the N64 ABI. The
4769 pseudo-sections which describe the ABI aren't present
4770 on IRIX. (Even for executables created by gcc.) */
4771 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4772 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4773 found_abi
= MIPS_ABI_N64
;
4775 found_abi
= MIPS_ABI_N32
;
4780 /* Default 64-bit objects to N64 instead of O32. */
4781 if (found_abi
== MIPS_ABI_UNKNOWN
4782 && info
.abfd
!= NULL
4783 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4784 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4785 found_abi
= MIPS_ABI_N64
;
4788 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4791 /* What has the user specified from the command line? */
4792 wanted_abi
= global_mips_abi ();
4794 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4797 /* Now that we have found what the ABI for this binary would be,
4798 check whether the user is overriding it. */
4799 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4800 mips_abi
= wanted_abi
;
4801 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4802 mips_abi
= found_abi
;
4804 mips_abi
= MIPS_ABI_O32
;
4806 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4809 /* Also used when doing an architecture lookup. */
4811 fprintf_unfiltered (gdb_stdlog
,
4812 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4813 mips64_transfers_32bit_regs_p
);
4815 /* Determine the MIPS FPU type. */
4816 if (!mips_fpu_type_auto
)
4817 fpu_type
= mips_fpu_type
;
4818 else if (info
.bfd_arch_info
!= NULL
4819 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4820 switch (info
.bfd_arch_info
->mach
)
4822 case bfd_mach_mips3900
:
4823 case bfd_mach_mips4100
:
4824 case bfd_mach_mips4111
:
4825 case bfd_mach_mips4120
:
4826 fpu_type
= MIPS_FPU_NONE
;
4828 case bfd_mach_mips4650
:
4829 fpu_type
= MIPS_FPU_SINGLE
;
4832 fpu_type
= MIPS_FPU_DOUBLE
;
4835 else if (arches
!= NULL
)
4836 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4838 fpu_type
= MIPS_FPU_DOUBLE
;
4840 fprintf_unfiltered (gdb_stdlog
,
4841 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4843 /* Check for blatant incompatibilities. */
4845 /* If we have only 32-bit registers, then we can't debug a 64-bit
4847 if (info
.target_desc
4848 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4849 && mips_abi
!= MIPS_ABI_EABI32
4850 && mips_abi
!= MIPS_ABI_O32
)
4853 /* try to find a pre-existing architecture */
4854 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4856 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4858 /* MIPS needs to be pedantic about which ABI the object is
4860 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4862 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4864 /* Need to be pedantic about which register virtual size is
4866 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4867 != mips64_transfers_32bit_regs_p
)
4869 /* Be pedantic about which FPU is selected. */
4870 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4872 return arches
->gdbarch
;
4875 /* Need a new architecture. Fill in a target specific vector. */
4876 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4877 gdbarch
= gdbarch_alloc (&info
, tdep
);
4878 tdep
->elf_flags
= elf_flags
;
4879 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4880 tdep
->found_abi
= found_abi
;
4881 tdep
->mips_abi
= mips_abi
;
4882 tdep
->mips_fpu_type
= fpu_type
;
4883 tdep
->register_size_valid_p
= 0;
4884 tdep
->register_size
= 0;
4886 if (info
.target_desc
)
4888 /* Some useful properties can be inferred from the target. */
4889 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4891 tdep
->register_size_valid_p
= 1;
4892 tdep
->register_size
= 4;
4894 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4896 tdep
->register_size_valid_p
= 1;
4897 tdep
->register_size
= 8;
4901 /* Initially set everything according to the default ABI/ISA. */
4902 set_gdbarch_short_bit (gdbarch
, 16);
4903 set_gdbarch_int_bit (gdbarch
, 32);
4904 set_gdbarch_float_bit (gdbarch
, 32);
4905 set_gdbarch_double_bit (gdbarch
, 64);
4906 set_gdbarch_long_double_bit (gdbarch
, 64);
4907 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4908 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4909 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4911 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4912 mips_elf_make_msymbol_special
);
4914 /* Fill in the OS dependant register numbers and names. */
4916 const char **reg_names
;
4917 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4918 struct mips_regnum
);
4919 if (info
.osabi
== GDB_OSABI_IRIX
)
4924 regnum
->badvaddr
= 66;
4927 regnum
->fp_control_status
= 69;
4928 regnum
->fp_implementation_revision
= 70;
4930 reg_names
= mips_irix_reg_names
;
4934 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4935 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4936 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4937 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4938 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4939 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4940 regnum
->fp_control_status
= 70;
4941 regnum
->fp_implementation_revision
= 71;
4943 if (info
.bfd_arch_info
!= NULL
4944 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
4945 reg_names
= mips_tx39_reg_names
;
4947 reg_names
= mips_generic_reg_names
;
4949 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4950 replaced by read_pc? */
4951 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
4952 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
4953 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
4954 set_gdbarch_num_regs (gdbarch
, num_regs
);
4955 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
4956 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4957 tdep
->mips_processor_reg_names
= reg_names
;
4958 tdep
->regnum
= regnum
;
4964 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
4965 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
4966 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4967 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4968 tdep
->default_mask_address_p
= 0;
4969 set_gdbarch_long_bit (gdbarch
, 32);
4970 set_gdbarch_ptr_bit (gdbarch
, 32);
4971 set_gdbarch_long_long_bit (gdbarch
, 64);
4974 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
4975 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
4976 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4977 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4978 tdep
->default_mask_address_p
= 0;
4979 set_gdbarch_long_bit (gdbarch
, 32);
4980 set_gdbarch_ptr_bit (gdbarch
, 32);
4981 set_gdbarch_long_long_bit (gdbarch
, 64);
4983 case MIPS_ABI_EABI32
:
4984 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4985 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4986 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4987 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4988 tdep
->default_mask_address_p
= 0;
4989 set_gdbarch_long_bit (gdbarch
, 32);
4990 set_gdbarch_ptr_bit (gdbarch
, 32);
4991 set_gdbarch_long_long_bit (gdbarch
, 64);
4993 case MIPS_ABI_EABI64
:
4994 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4995 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4996 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4997 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4998 tdep
->default_mask_address_p
= 0;
4999 set_gdbarch_long_bit (gdbarch
, 64);
5000 set_gdbarch_ptr_bit (gdbarch
, 64);
5001 set_gdbarch_long_long_bit (gdbarch
, 64);
5004 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5005 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5006 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5007 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5008 tdep
->default_mask_address_p
= 0;
5009 set_gdbarch_long_bit (gdbarch
, 32);
5010 set_gdbarch_ptr_bit (gdbarch
, 32);
5011 set_gdbarch_long_long_bit (gdbarch
, 64);
5012 set_gdbarch_long_double_bit (gdbarch
, 128);
5013 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5016 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5017 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5018 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5019 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5020 tdep
->default_mask_address_p
= 0;
5021 set_gdbarch_long_bit (gdbarch
, 64);
5022 set_gdbarch_ptr_bit (gdbarch
, 64);
5023 set_gdbarch_long_long_bit (gdbarch
, 64);
5024 set_gdbarch_long_double_bit (gdbarch
, 128);
5025 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5028 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5031 /* GCC creates a pseudo-section whose name specifies the size of
5032 longs, since -mlong32 or -mlong64 may be used independent of
5033 other options. How those options affect pointer sizes is ABI and
5034 architecture dependent, so use them to override the default sizes
5035 set by the ABI. This table shows the relationship between ABI,
5036 -mlongXX, and size of pointers:
5038 ABI -mlongXX ptr bits
5039 --- -------- --------
5053 Note that for o32 and eabi32, pointers are always 32 bits
5054 regardless of any -mlongXX option. For all others, pointers and
5055 longs are the same, as set by -mlongXX or set by defaults.
5058 if (info
.abfd
!= NULL
)
5062 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5065 set_gdbarch_long_bit (gdbarch
, long_bit
);
5069 case MIPS_ABI_EABI32
:
5074 case MIPS_ABI_EABI64
:
5075 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5078 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5083 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5084 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5087 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5088 flag in object files because to do so would make it impossible to
5089 link with libraries compiled without "-gp32". This is
5090 unnecessarily restrictive.
5092 We could solve this problem by adding "-gp32" multilibs to gcc,
5093 but to set this flag before gcc is built with such multilibs will
5094 break too many systems.''
5096 But even more unhelpfully, the default linker output target for
5097 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5098 for 64-bit programs - you need to change the ABI to change this,
5099 and not all gcc targets support that currently. Therefore using
5100 this flag to detect 32-bit mode would do the wrong thing given
5101 the current gcc - it would make GDB treat these 64-bit programs
5102 as 32-bit programs by default. */
5104 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5105 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5107 /* Add/remove bits from an address. The MIPS needs be careful to
5108 ensure that all 32 bit addresses are sign extended to 64 bits. */
5109 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5111 /* Unwind the frame. */
5112 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5113 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5114 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5116 /* Map debug register numbers onto internal register numbers. */
5117 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5118 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5119 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5120 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5121 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5122 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5123 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5124 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5126 /* MIPS version of CALL_DUMMY */
5128 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5129 replaced by a command, and all targets will default to on stack
5130 (regardless of the stack's execute status). */
5131 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5132 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5134 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5135 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5136 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5138 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5139 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5141 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5143 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5144 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5145 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5147 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5149 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5151 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5153 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5154 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5155 need to all be folded into the target vector. Since they are
5156 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5157 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5159 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5161 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5163 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5165 /* Virtual tables. */
5166 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5168 mips_register_g_packet_guesses (gdbarch
);
5170 /* Hook in OS ABI-specific overrides, if they have been registered. */
5171 gdbarch_init_osabi (info
, gdbarch
);
5173 /* Unwind the frame. */
5174 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5175 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5176 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5177 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5178 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5179 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5185 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5187 struct gdbarch_info info
;
5189 /* Force the architecture to update, and (if it's a MIPS architecture)
5190 mips_gdbarch_init will take care of the rest. */
5191 gdbarch_info_init (&info
);
5192 gdbarch_update_p (info
);
5195 /* Print out which MIPS ABI is in use. */
5198 show_mips_abi (struct ui_file
*file
,
5200 struct cmd_list_element
*ignored_cmd
,
5201 const char *ignored_value
)
5203 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5206 "The MIPS ABI is unknown because the current architecture "
5210 enum mips_abi global_abi
= global_mips_abi ();
5211 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5212 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5214 if (global_abi
== MIPS_ABI_UNKNOWN
)
5217 "The MIPS ABI is set automatically (currently \"%s\").\n",
5219 else if (global_abi
== actual_abi
)
5222 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5226 /* Probably shouldn't happen... */
5229 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5230 actual_abi_str
, mips_abi_strings
[global_abi
]);
5236 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5242 int ef_mips_32bitmode
;
5243 /* Determine the ISA. */
5244 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5262 /* Determine the size of a pointer. */
5263 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5264 fprintf_unfiltered (file
,
5265 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5267 fprintf_unfiltered (file
,
5268 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5270 fprintf_unfiltered (file
,
5271 "mips_dump_tdep: ef_mips_arch = %d\n",
5273 fprintf_unfiltered (file
,
5274 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5275 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5276 fprintf_unfiltered (file
,
5277 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5278 mips_mask_address_p (tdep
),
5279 tdep
->default_mask_address_p
);
5281 fprintf_unfiltered (file
,
5282 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5283 MIPS_DEFAULT_FPU_TYPE
,
5284 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5285 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5286 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5288 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5289 fprintf_unfiltered (file
,
5290 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5292 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5293 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5294 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5296 fprintf_unfiltered (file
,
5297 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5298 mips_stack_argsize (current_gdbarch
));
5301 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5304 _initialize_mips_tdep (void)
5306 static struct cmd_list_element
*mipsfpulist
= NULL
;
5307 struct cmd_list_element
*c
;
5309 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5310 if (MIPS_ABI_LAST
+ 1
5311 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5312 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5314 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5316 mips_pdr_data
= register_objfile_data ();
5318 /* Add root prefix command for all "set mips"/"show mips" commands */
5319 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5320 _("Various MIPS specific commands."),
5321 &setmipscmdlist
, "set mips ", 0, &setlist
);
5323 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5324 _("Various MIPS specific commands."),
5325 &showmipscmdlist
, "show mips ", 0, &showlist
);
5327 /* Allow the user to override the saved register size. */
5328 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5329 size_enums
, &mips_abi_regsize_string
, _("\
5330 Set size of general purpose registers saved on the stack."), _("\
5331 Show size of general purpose registers saved on the stack."), _("\
5332 This option can be set to one of:\n\
5333 32 - Force GDB to treat saved GP registers as 32-bit\n\
5334 64 - Force GDB to treat saved GP registers as 64-bit\n\
5335 auto - Allow GDB to use the target's default setting or autodetect the\n\
5336 saved GP register size from information contained in the\n\
5337 executable (default)."),
5339 NULL
, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */
5340 &setmipscmdlist
, &showmipscmdlist
);
5342 /* Allow the user to override the argument stack size. */
5343 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5344 size_enums
, &mips_stack_argsize_string
, _("\
5345 Set the amount of stack space reserved for each argument."), _("\
5346 Show the amount of stack space reserved for each argument."), _("\
5347 This option can be set to one of:\n\
5348 32 - Force GDB to allocate 32-bit chunks per argument\n\
5349 64 - Force GDB to allocate 64-bit chunks per argument\n\
5350 auto - Allow GDB to determine the correct setting from the current\n\
5351 target and executable (default)"),
5353 NULL
, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */
5354 &setmipscmdlist
, &showmipscmdlist
);
5356 /* Allow the user to override the ABI. */
5357 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5358 &mips_abi_string
, _("\
5359 Set the MIPS ABI used by this program."), _("\
5360 Show the MIPS ABI used by this program."), _("\
5361 This option can be set to one of:\n\
5362 auto - the default ABI associated with the current binary\n\
5371 &setmipscmdlist
, &showmipscmdlist
);
5373 /* Let the user turn off floating point and set the fence post for
5374 heuristic_proc_start. */
5376 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5377 _("Set use of MIPS floating-point coprocessor."),
5378 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5379 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5380 _("Select single-precision MIPS floating-point coprocessor."),
5382 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5383 _("Select double-precision MIPS floating-point coprocessor."),
5385 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5386 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5387 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5388 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5389 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5390 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5391 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5392 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5393 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5394 _("Select MIPS floating-point coprocessor automatically."),
5396 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5397 _("Show current use of MIPS floating-point coprocessor target."),
5400 /* We really would like to have both "0" and "unlimited" work, but
5401 command.c doesn't deal with that. So make it a var_zinteger
5402 because the user can always use "999999" or some such for unlimited. */
5403 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5404 &heuristic_fence_post
, _("\
5405 Set the distance searched for the start of a function."), _("\
5406 Show the distance searched for the start of a function."), _("\
5407 If you are debugging a stripped executable, GDB needs to search through the\n\
5408 program for the start of a function. This command sets the distance of the\n\
5409 search. The only need to set it is when debugging a stripped executable."),
5410 reinit_frame_cache_sfunc
,
5411 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5412 &setlist
, &showlist
);
5414 /* Allow the user to control whether the upper bits of 64-bit
5415 addresses should be zeroed. */
5416 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5417 &mask_address_var
, _("\
5418 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5419 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5420 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5421 allow GDB to determine the correct value."),
5422 NULL
, show_mask_address
,
5423 &setmipscmdlist
, &showmipscmdlist
);
5425 /* Allow the user to control the size of 32 bit registers within the
5426 raw remote packet. */
5427 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5428 &mips64_transfers_32bit_regs_p
, _("\
5429 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5431 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5433 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5434 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5435 64 bits for others. Use \"off\" to disable compatibility mode"),
5436 set_mips64_transfers_32bit_regs
,
5437 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5438 &setlist
, &showlist
);
5440 /* Debug this files internals. */
5441 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5443 Set mips debugging."), _("\
5444 Show mips debugging."), _("\
5445 When non-zero, mips specific debugging is enabled."),
5447 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5448 &setdebuglist
, &showdebuglist
);