1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
78 static const char *mips_abi_string
;
80 static const char *mips_abi_strings
[] = {
91 /* Various MIPS ISA options (related to stack analysis) can be
92 overridden dynamically. Establish an enum/array for managing
95 static const char size_auto
[] = "auto";
96 static const char size_32
[] = "32";
97 static const char size_64
[] = "64";
99 static const char *size_enums
[] = {
106 /* Some MIPS boards don't support floating point while others only
107 support single-precision floating-point operations. */
111 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
112 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
113 MIPS_FPU_NONE
/* No floating point. */
116 #ifndef MIPS_DEFAULT_FPU_TYPE
117 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
119 static int mips_fpu_type_auto
= 1;
120 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
122 static int mips_debug
= 0;
124 /* Properties (for struct target_desc) describing the g/G packet
126 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
127 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
152 /* The size of register data available from the target, if known.
153 This doesn't quite obsolete the manual
154 mips64_transfers_32bit_regs_p, since that is documented to force
155 left alignment even for big endian (very strange). */
156 int register_size_valid_p
;
161 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
167 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
168 They are implemented as a pair of 64bit doubles where the high
169 part holds the result of the operation rounded to double, and
170 the low double holds the difference between the exact result and
171 the rounded result. So "high" + "low" contains the result with
172 added precision. Unfortunately, the floatformat structure used
173 by GDB is not powerful enough to describe this format. As a temporary
174 measure, we define a 128bit floatformat that only uses the high part.
175 We lose a bit of precision but that's probably the best we can do
176 for now with the current infrastructure. */
178 static const struct floatformat floatformat_n32n64_long_double_big
=
180 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
181 floatformat_intbit_no
,
182 "floatformat_n32n64_long_double_big",
183 n32n64_floatformat_always_valid
186 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
188 &floatformat_n32n64_long_double_big
,
189 &floatformat_n32n64_long_double_big
192 const struct mips_regnum
*
193 mips_regnum (struct gdbarch
*gdbarch
)
195 return gdbarch_tdep (gdbarch
)->regnum
;
199 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
201 return mips_regnum (gdbarch
)->fp0
+ 12;
204 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
205 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
207 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
209 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
211 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
213 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
214 functions to test, set, or clear bit 0 of addresses. */
217 is_mips16_addr (CORE_ADDR addr
)
223 unmake_mips16_addr (CORE_ADDR addr
)
225 return ((addr
) & ~(CORE_ADDR
) 1);
228 /* Return the contents of register REGNUM as a signed integer. */
231 read_signed_register (int regnum
)
234 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
239 read_signed_register_pid (int regnum
, ptid_t ptid
)
244 if (ptid_equal (ptid
, inferior_ptid
))
245 return read_signed_register (regnum
);
247 save_ptid
= inferior_ptid
;
249 inferior_ptid
= ptid
;
251 retval
= read_signed_register (regnum
);
253 inferior_ptid
= save_ptid
;
258 /* Return the MIPS ABI associated with GDBARCH. */
260 mips_abi (struct gdbarch
*gdbarch
)
262 return gdbarch_tdep (gdbarch
)->mips_abi
;
266 mips_isa_regsize (struct gdbarch
*gdbarch
)
268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 /* If we know how big the registers are, use that size. */
271 if (tdep
->register_size_valid_p
)
272 return tdep
->register_size
;
274 /* Fall back to the previous behavior. */
275 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
276 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
279 /* Return the currently configured (or set) saved register size. */
281 static const char *mips_abi_regsize_string
= size_auto
;
284 mips_abi_regsize (struct gdbarch
*gdbarch
)
286 if (mips_abi_regsize_string
== size_auto
)
287 switch (mips_abi (gdbarch
))
289 case MIPS_ABI_EABI32
:
295 case MIPS_ABI_EABI64
:
297 case MIPS_ABI_UNKNOWN
:
300 internal_error (__FILE__
, __LINE__
, _("bad switch"));
302 else if (mips_abi_regsize_string
== size_64
)
304 else /* if (mips_abi_regsize_string == size_32) */
308 /* Functions for setting and testing a bit in a minimal symbol that
309 marks it as 16-bit function. The MSB of the minimal symbol's
310 "info" field is used for this purpose.
312 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
313 i.e. refers to a 16-bit function, and sets a "special" bit in a
314 minimal symbol to mark it as a 16-bit function
316 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
319 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
321 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
323 MSYMBOL_INFO (msym
) = (char *)
324 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
325 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
330 msymbol_is_special (struct minimal_symbol
*msym
)
332 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
335 /* XFER a value from the big/little/left end of the register.
336 Depending on the size of the value it might occupy the entire
337 register or just part of it. Make an allowance for this, aligning
338 things accordingly. */
341 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
342 enum bfd_endian endian
, gdb_byte
*in
,
343 const gdb_byte
*out
, int buf_offset
)
346 gdb_assert (reg_num
>= NUM_REGS
);
347 /* Need to transfer the left or right part of the register, based on
348 the targets byte order. */
352 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
354 case BFD_ENDIAN_LITTLE
:
357 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
361 internal_error (__FILE__
, __LINE__
, _("bad switch"));
364 fprintf_unfiltered (gdb_stderr
,
365 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
366 reg_num
, reg_offset
, buf_offset
, length
);
367 if (mips_debug
&& out
!= NULL
)
370 fprintf_unfiltered (gdb_stdlog
, "out ");
371 for (i
= 0; i
< length
; i
++)
372 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
375 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
378 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
380 if (mips_debug
&& in
!= NULL
)
383 fprintf_unfiltered (gdb_stdlog
, "in ");
384 for (i
= 0; i
< length
; i
++)
385 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
388 fprintf_unfiltered (gdb_stdlog
, "\n");
391 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
392 compatiblity mode. A return value of 1 means that we have
393 physical 64-bit registers, but should treat them as 32-bit registers. */
396 mips2_fp_compat (void)
398 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
400 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
405 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
406 in all the places we deal with FP registers. PR gdb/413. */
407 /* Otherwise check the FR bit in the status register - it controls
408 the FP compatiblity mode. If it is clear we are in compatibility
410 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
417 /* The amount of space reserved on the stack for registers. This is
418 different to MIPS_ABI_REGSIZE as it determines the alignment of
419 data allocated after the registers have run out. */
421 static const char *mips_stack_argsize_string
= size_auto
;
424 mips_stack_argsize (struct gdbarch
*gdbarch
)
426 if (mips_stack_argsize_string
== size_auto
)
427 return mips_abi_regsize (gdbarch
);
428 else if (mips_stack_argsize_string
== size_64
)
430 else /* if (mips_stack_argsize_string == size_32) */
434 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
436 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
438 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
440 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
442 static struct type
*mips_float_register_type (void);
443 static struct type
*mips_double_register_type (void);
445 /* The list of available "set mips " and "show mips " commands */
447 static struct cmd_list_element
*setmipscmdlist
= NULL
;
448 static struct cmd_list_element
*showmipscmdlist
= NULL
;
450 /* Integer registers 0 thru 31 are handled explicitly by
451 mips_register_name(). Processor specific registers 32 and above
452 are listed in the followign tables. */
455 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
459 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
460 "sr", "lo", "hi", "bad", "cause", "pc",
461 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
462 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
463 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
464 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
465 "fsr", "fir", "" /*"fp" */ , "",
466 "", "", "", "", "", "", "", "",
467 "", "", "", "", "", "", "", "",
470 /* Names of IDT R3041 registers. */
472 static const char *mips_r3041_reg_names
[] = {
473 "sr", "lo", "hi", "bad", "cause", "pc",
474 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
475 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
476 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
477 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
478 "fsr", "fir", "", /*"fp" */ "",
479 "", "", "bus", "ccfg", "", "", "", "",
480 "", "", "port", "cmp", "", "", "epc", "prid",
483 /* Names of tx39 registers. */
485 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
486 "sr", "lo", "hi", "bad", "cause", "pc",
487 "", "", "", "", "", "", "", "",
488 "", "", "", "", "", "", "", "",
489 "", "", "", "", "", "", "", "",
490 "", "", "", "", "", "", "", "",
492 "", "", "", "", "", "", "", "",
493 "", "", "config", "cache", "debug", "depc", "epc", ""
496 /* Names of IRIX registers. */
497 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
498 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
502 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
506 /* Return the name of the register corresponding to REGNO. */
508 mips_register_name (int regno
)
510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
511 /* GPR names for all ABIs other than n32/n64. */
512 static char *mips_gpr_names
[] = {
513 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
514 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
515 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
516 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
519 /* GPR names for n32 and n64 ABIs. */
520 static char *mips_n32_n64_gpr_names
[] = {
521 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
522 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
523 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
524 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
527 enum mips_abi abi
= mips_abi (current_gdbarch
);
529 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
530 don't make the raw register names visible. */
531 int rawnum
= regno
% NUM_REGS
;
532 if (regno
< NUM_REGS
)
535 /* The MIPS integer registers are always mapped from 0 to 31. The
536 names of the registers (which reflects the conventions regarding
537 register use) vary depending on the ABI. */
538 if (0 <= rawnum
&& rawnum
< 32)
540 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
541 return mips_n32_n64_gpr_names
[rawnum
];
543 return mips_gpr_names
[rawnum
];
545 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
547 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
548 return tdep
->mips_processor_reg_names
[rawnum
- 32];
551 internal_error (__FILE__
, __LINE__
,
552 _("mips_register_name: bad register number %d"), rawnum
);
555 /* Return the groups that a MIPS register can be categorised into. */
558 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
559 struct reggroup
*reggroup
)
564 int rawnum
= regnum
% NUM_REGS
;
565 int pseudo
= regnum
/ NUM_REGS
;
566 if (reggroup
== all_reggroup
)
568 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
569 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
570 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
571 (gdbarch), as not all architectures are multi-arch. */
572 raw_p
= rawnum
< NUM_REGS
;
573 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
575 if (reggroup
== float_reggroup
)
576 return float_p
&& pseudo
;
577 if (reggroup
== vector_reggroup
)
578 return vector_p
&& pseudo
;
579 if (reggroup
== general_reggroup
)
580 return (!vector_p
&& !float_p
) && pseudo
;
581 /* Save the pseudo registers. Need to make certain that any code
582 extracting register values from a saved register cache also uses
584 if (reggroup
== save_reggroup
)
585 return raw_p
&& pseudo
;
586 /* Restore the same pseudo register. */
587 if (reggroup
== restore_reggroup
)
588 return raw_p
&& pseudo
;
592 /* Map the symbol table registers which live in the range [1 *
593 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
594 registers. Take care of alignment and size problems. */
597 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
598 int cookednum
, gdb_byte
*buf
)
600 int rawnum
= cookednum
% NUM_REGS
;
601 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
602 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
603 regcache_raw_read (regcache
, rawnum
, buf
);
604 else if (register_size (gdbarch
, rawnum
) >
605 register_size (gdbarch
, cookednum
))
607 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
608 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
609 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
611 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
614 internal_error (__FILE__
, __LINE__
, _("bad register size"));
618 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
619 struct regcache
*regcache
, int cookednum
,
622 int rawnum
= cookednum
% NUM_REGS
;
623 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
624 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
625 regcache_raw_write (regcache
, rawnum
, buf
);
626 else if (register_size (gdbarch
, rawnum
) >
627 register_size (gdbarch
, cookednum
))
629 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
630 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
631 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
633 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
636 internal_error (__FILE__
, __LINE__
, _("bad register size"));
639 /* Table to translate MIPS16 register field to actual register number. */
640 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
642 /* Heuristic_proc_start may hunt through the text section for a long
643 time across a 2400 baud serial line. Allows the user to limit this
646 static unsigned int heuristic_fence_post
= 0;
648 /* Number of bytes of storage in the actual machine representation for
649 register N. NOTE: This defines the pseudo register type so need to
650 rebuild the architecture vector. */
652 static int mips64_transfers_32bit_regs_p
= 0;
655 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
656 struct cmd_list_element
*c
)
658 struct gdbarch_info info
;
659 gdbarch_info_init (&info
);
660 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
661 instead of relying on globals. Doing that would let generic code
662 handle the search for this specific architecture. */
663 if (!gdbarch_update_p (info
))
665 mips64_transfers_32bit_regs_p
= 0;
666 error (_("32-bit compatibility mode not supported"));
670 /* Convert to/from a register and the corresponding memory value. */
673 mips_convert_register_p (int regnum
, struct type
*type
)
675 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
676 && register_size (current_gdbarch
, regnum
) == 4
677 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
678 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
679 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
683 mips_register_to_value (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, gdb_byte
*to
)
686 get_frame_register (frame
, regnum
+ 0, to
+ 4);
687 get_frame_register (frame
, regnum
+ 1, to
+ 0);
691 mips_value_to_register (struct frame_info
*frame
, int regnum
,
692 struct type
*type
, const gdb_byte
*from
)
694 put_frame_register (frame
, regnum
+ 0, from
+ 4);
695 put_frame_register (frame
, regnum
+ 1, from
+ 0);
698 /* Return the GDB type object for the "standard" data type of data in
702 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
704 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
705 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
706 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
708 /* The floating-point registers raw, or cooked, always match
709 mips_isa_regsize(), and also map 1:1, byte for byte. */
710 if (mips_isa_regsize (gdbarch
) == 4)
711 return builtin_type_ieee_single
;
713 return builtin_type_ieee_double
;
715 else if (regnum
< NUM_REGS
)
717 /* The raw or ISA registers. These are all sized according to
719 if (mips_isa_regsize (gdbarch
) == 4)
720 return builtin_type_int32
;
722 return builtin_type_int64
;
726 /* The cooked or ABI registers. These are sized according to
727 the ABI (with a few complications). */
728 if (regnum
>= (NUM_REGS
729 + mips_regnum (current_gdbarch
)->fp_control_status
)
730 && regnum
<= NUM_REGS
+ MIPS_LAST_EMBED_REGNUM
)
731 /* The pseudo/cooked view of the embedded registers is always
732 32-bit. The raw view is handled below. */
733 return builtin_type_int32
;
734 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
735 /* The target, while possibly using a 64-bit register buffer,
736 is only transfering 32-bits of each integer register.
737 Reflect this in the cooked/pseudo (ABI) register value. */
738 return builtin_type_int32
;
739 else if (mips_abi_regsize (gdbarch
) == 4)
740 /* The ABI is restricted to 32-bit registers (the ISA could be
742 return builtin_type_int32
;
745 return builtin_type_int64
;
749 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
754 return read_signed_register (MIPS_SP_REGNUM
);
757 /* Should the upper word of 64-bit addresses be zeroed? */
758 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
761 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
763 switch (mask_address_var
)
765 case AUTO_BOOLEAN_TRUE
:
767 case AUTO_BOOLEAN_FALSE
:
770 case AUTO_BOOLEAN_AUTO
:
771 return tdep
->default_mask_address_p
;
773 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
779 show_mask_address (struct ui_file
*file
, int from_tty
,
780 struct cmd_list_element
*c
, const char *value
)
782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
784 deprecated_show_value_hack (file
, from_tty
, c
, value
);
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
788 printf_filtered ("The 32 bit mips address mask is enabled\n");
790 case AUTO_BOOLEAN_FALSE
:
791 printf_filtered ("The 32 bit mips address mask is disabled\n");
793 case AUTO_BOOLEAN_AUTO
:
795 ("The 32 bit address mask is set automatically. Currently %s\n",
796 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
799 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
804 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
807 mips_pc_is_mips16 (CORE_ADDR memaddr
)
809 struct minimal_symbol
*sym
;
811 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
812 if (is_mips16_addr (memaddr
))
815 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
816 the high bit of the info field. Use this to decide if the function is
817 MIPS16 or normal MIPS. */
818 sym
= lookup_minimal_symbol_by_pc (memaddr
);
820 return msymbol_is_special (sym
);
825 /* MIPS believes that the PC has a sign extended value. Perhaps the
826 all registers should be sign extended for simplicity? */
829 mips_read_pc (ptid_t ptid
)
831 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
835 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
837 return frame_unwind_register_signed (next_frame
,
838 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
841 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
842 dummy frame. The frame ID's base needs to match the TOS value
843 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
846 static struct frame_id
847 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
849 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
850 frame_pc_unwind (next_frame
));
854 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
856 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
859 /* Fetch and return instruction from the specified location. If the PC
860 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
863 mips_fetch_instruction (CORE_ADDR addr
)
865 gdb_byte buf
[MIPS_INSN32_SIZE
];
869 if (mips_pc_is_mips16 (addr
))
871 instlen
= MIPS_INSN16_SIZE
;
872 addr
= unmake_mips16_addr (addr
);
875 instlen
= MIPS_INSN32_SIZE
;
876 status
= read_memory_nobpt (addr
, buf
, instlen
);
878 memory_error (status
, addr
);
879 return extract_unsigned_integer (buf
, instlen
);
882 /* These the fields of 32 bit mips instructions */
883 #define mips32_op(x) (x >> 26)
884 #define itype_op(x) (x >> 26)
885 #define itype_rs(x) ((x >> 21) & 0x1f)
886 #define itype_rt(x) ((x >> 16) & 0x1f)
887 #define itype_immediate(x) (x & 0xffff)
889 #define jtype_op(x) (x >> 26)
890 #define jtype_target(x) (x & 0x03ffffff)
892 #define rtype_op(x) (x >> 26)
893 #define rtype_rs(x) ((x >> 21) & 0x1f)
894 #define rtype_rt(x) ((x >> 16) & 0x1f)
895 #define rtype_rd(x) ((x >> 11) & 0x1f)
896 #define rtype_shamt(x) ((x >> 6) & 0x1f)
897 #define rtype_funct(x) (x & 0x3f)
900 mips32_relative_offset (ULONGEST inst
)
902 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
905 /* Determine where to set a single step breakpoint while considering
906 branch prediction. */
908 mips32_next_pc (CORE_ADDR pc
)
912 inst
= mips_fetch_instruction (pc
);
913 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
915 if (itype_op (inst
) >> 2 == 5)
916 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
918 op
= (itype_op (inst
) & 0x03);
933 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
934 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
936 int tf
= itype_rt (inst
) & 0x01;
937 int cnum
= itype_rt (inst
) >> 2;
939 read_signed_register (mips_regnum (current_gdbarch
)->
941 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
943 if (((cond
>> cnum
) & 0x01) == tf
)
944 pc
+= mips32_relative_offset (inst
) + 4;
949 pc
+= 4; /* Not a branch, next instruction is easy */
952 { /* This gets way messy */
954 /* Further subdivide into SPECIAL, REGIMM and other */
955 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
957 case 0: /* SPECIAL */
958 op
= rtype_funct (inst
);
963 /* Set PC to that address */
964 pc
= read_signed_register (rtype_rs (inst
));
970 break; /* end SPECIAL */
973 op
= itype_rt (inst
); /* branch condition */
978 case 16: /* BLTZAL */
979 case 18: /* BLTZALL */
981 if (read_signed_register (itype_rs (inst
)) < 0)
982 pc
+= mips32_relative_offset (inst
) + 4;
984 pc
+= 8; /* after the delay slot */
988 case 17: /* BGEZAL */
989 case 19: /* BGEZALL */
990 if (read_signed_register (itype_rs (inst
)) >= 0)
991 pc
+= mips32_relative_offset (inst
) + 4;
993 pc
+= 8; /* after the delay slot */
995 /* All of the other instructions in the REGIMM category */
1000 break; /* end REGIMM */
1005 reg
= jtype_target (inst
) << 2;
1006 /* Upper four bits get never changed... */
1007 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1010 /* FIXME case JALX : */
1013 reg
= jtype_target (inst
) << 2;
1014 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1015 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1017 break; /* The new PC will be alternate mode */
1018 case 4: /* BEQ, BEQL */
1020 if (read_signed_register (itype_rs (inst
)) ==
1021 read_signed_register (itype_rt (inst
)))
1022 pc
+= mips32_relative_offset (inst
) + 4;
1026 case 5: /* BNE, BNEL */
1028 if (read_signed_register (itype_rs (inst
)) !=
1029 read_signed_register (itype_rt (inst
)))
1030 pc
+= mips32_relative_offset (inst
) + 4;
1034 case 6: /* BLEZ, BLEZL */
1035 if (read_signed_register (itype_rs (inst
)) <= 0)
1036 pc
+= mips32_relative_offset (inst
) + 4;
1042 greater_branch
: /* BGTZ, BGTZL */
1043 if (read_signed_register (itype_rs (inst
)) > 0)
1044 pc
+= mips32_relative_offset (inst
) + 4;
1051 } /* mips32_next_pc */
1053 /* Decoding the next place to set a breakpoint is irregular for the
1054 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1055 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1056 We dont want to set a single step instruction on the extend instruction
1060 /* Lots of mips16 instruction formats */
1061 /* Predicting jumps requires itype,ritype,i8type
1062 and their extensions extItype,extritype,extI8type
1064 enum mips16_inst_fmts
1066 itype
, /* 0 immediate 5,10 */
1067 ritype
, /* 1 5,3,8 */
1068 rrtype
, /* 2 5,3,3,5 */
1069 rritype
, /* 3 5,3,3,5 */
1070 rrrtype
, /* 4 5,3,3,3,2 */
1071 rriatype
, /* 5 5,3,3,1,4 */
1072 shifttype
, /* 6 5,3,3,3,2 */
1073 i8type
, /* 7 5,3,8 */
1074 i8movtype
, /* 8 5,3,3,5 */
1075 i8mov32rtype
, /* 9 5,3,5,3 */
1076 i64type
, /* 10 5,3,8 */
1077 ri64type
, /* 11 5,3,3,5 */
1078 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1079 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1080 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1081 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1082 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1083 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1084 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1085 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1086 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1087 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1089 /* I am heaping all the fields of the formats into one structure and
1090 then, only the fields which are involved in instruction extension */
1094 unsigned int regx
; /* Function in i8 type */
1099 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1100 for the bits which make up the immediatate extension. */
1103 extended_offset (unsigned int extension
)
1106 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1108 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1110 value
|= extension
& 0x01f; /* extract 4:0 */
1114 /* Only call this function if you know that this is an extendable
1115 instruction, It wont malfunction, but why make excess remote memory references?
1116 If the immediate operands get sign extended or somthing, do it after
1117 the extension is performed.
1119 /* FIXME: Every one of these cases needs to worry about sign extension
1120 when the offset is to be used in relative addressing */
1124 fetch_mips_16 (CORE_ADDR pc
)
1127 pc
&= 0xfffffffe; /* clear the low order bit */
1128 target_read_memory (pc
, buf
, 2);
1129 return extract_unsigned_integer (buf
, 2);
1133 unpack_mips16 (CORE_ADDR pc
,
1134 unsigned int extension
,
1136 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1141 switch (insn_format
)
1148 value
= extended_offset (extension
);
1149 value
= value
<< 11; /* rom for the original value */
1150 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1154 value
= inst
& 0x7ff;
1155 /* FIXME : Consider sign extension */
1164 { /* A register identifier and an offset */
1165 /* Most of the fields are the same as I type but the
1166 immediate value is of a different length */
1170 value
= extended_offset (extension
);
1171 value
= value
<< 8; /* from the original instruction */
1172 value
|= inst
& 0xff; /* eleven bits from instruction */
1173 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1174 if (value
& 0x4000) /* test the sign bit , bit 26 */
1176 value
&= ~0x3fff; /* remove the sign bit */
1182 value
= inst
& 0xff; /* 8 bits */
1183 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1184 /* FIXME: Do sign extension , this format needs it */
1185 if (value
& 0x80) /* THIS CONFUSES ME */
1187 value
&= 0xef; /* remove the sign bit */
1197 unsigned long value
;
1198 unsigned int nexthalf
;
1199 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1200 value
= value
<< 16;
1201 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1209 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1211 upk
->offset
= offset
;
1218 add_offset_16 (CORE_ADDR pc
, int offset
)
1220 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1224 extended_mips16_next_pc (CORE_ADDR pc
,
1225 unsigned int extension
, unsigned int insn
)
1227 int op
= (insn
>> 11);
1230 case 2: /* Branch */
1233 struct upk_mips16 upk
;
1234 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1235 offset
= upk
.offset
;
1241 pc
+= (offset
<< 1) + 2;
1244 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1246 struct upk_mips16 upk
;
1247 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1248 pc
= add_offset_16 (pc
, upk
.offset
);
1249 if ((insn
>> 10) & 0x01) /* Exchange mode */
1250 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1257 struct upk_mips16 upk
;
1259 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1260 reg
= read_signed_register (upk
.regx
);
1262 pc
+= (upk
.offset
<< 1) + 2;
1269 struct upk_mips16 upk
;
1271 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1272 reg
= read_signed_register (upk
.regx
);
1274 pc
+= (upk
.offset
<< 1) + 2;
1279 case 12: /* I8 Formats btez btnez */
1281 struct upk_mips16 upk
;
1283 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1284 /* upk.regx contains the opcode */
1285 reg
= read_signed_register (24); /* Test register is 24 */
1286 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1287 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1288 /* pc = add_offset_16(pc,upk.offset) ; */
1289 pc
+= (upk
.offset
<< 1) + 2;
1294 case 29: /* RR Formats JR, JALR, JALR-RA */
1296 struct upk_mips16 upk
;
1297 /* upk.fmt = rrtype; */
1302 upk
.regx
= (insn
>> 8) & 0x07;
1303 upk
.regy
= (insn
>> 5) & 0x07;
1311 break; /* Function return instruction */
1317 break; /* BOGUS Guess */
1319 pc
= read_signed_register (reg
);
1326 /* This is an instruction extension. Fetch the real instruction
1327 (which follows the extension) and decode things based on
1331 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1344 mips16_next_pc (CORE_ADDR pc
)
1346 unsigned int insn
= fetch_mips_16 (pc
);
1347 return extended_mips16_next_pc (pc
, 0, insn
);
1350 /* The mips_next_pc function supports single_step when the remote
1351 target monitor or stub is not developed enough to do a single_step.
1352 It works by decoding the current instruction and predicting where a
1353 branch will go. This isnt hard because all the data is available.
1354 The MIPS32 and MIPS16 variants are quite different */
1356 mips_next_pc (CORE_ADDR pc
)
1359 return mips16_next_pc (pc
);
1361 return mips32_next_pc (pc
);
1364 struct mips_frame_cache
1367 struct trad_frame_saved_reg
*saved_regs
;
1370 /* Set a register's saved stack address in temp_saved_regs. If an
1371 address has already been set for this register, do nothing; this
1372 way we will only recognize the first save of a given register in a
1375 For simplicity, save the address in both [0 .. NUM_REGS) and
1376 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1377 is used as it is only second range (the ABI instead of ISA
1378 registers) that comes into play when finding saved registers in a
1382 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1385 if (this_cache
!= NULL
1386 && this_cache
->saved_regs
[regnum
].addr
== -1)
1388 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1389 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1394 /* Fetch the immediate value from a MIPS16 instruction.
1395 If the previous instruction was an EXTEND, use it to extend
1396 the upper bits of the immediate value. This is a helper function
1397 for mips16_scan_prologue. */
1400 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1401 unsigned short inst
, /* current instruction */
1402 int nbits
, /* number of bits in imm field */
1403 int scale
, /* scale factor to be applied to imm */
1404 int is_signed
) /* is the imm field signed? */
1408 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1410 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1411 if (offset
& 0x8000) /* check for negative extend */
1412 offset
= 0 - (0x10000 - (offset
& 0xffff));
1413 return offset
| (inst
& 0x1f);
1417 int max_imm
= 1 << nbits
;
1418 int mask
= max_imm
- 1;
1419 int sign_bit
= max_imm
>> 1;
1421 offset
= inst
& mask
;
1422 if (is_signed
&& (offset
& sign_bit
))
1423 offset
= 0 - (max_imm
- offset
);
1424 return offset
* scale
;
1429 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1430 the associated FRAME_CACHE if not null.
1431 Return the address of the first instruction past the prologue. */
1434 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1435 struct frame_info
*next_frame
,
1436 struct mips_frame_cache
*this_cache
)
1439 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1441 long frame_offset
= 0; /* Size of stack frame. */
1442 long frame_adjust
= 0; /* Offset of FP from SP. */
1443 int frame_reg
= MIPS_SP_REGNUM
;
1444 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1445 unsigned inst
= 0; /* current instruction */
1446 unsigned entry_inst
= 0; /* the entry instruction */
1449 int extend_bytes
= 0;
1450 int prev_extend_bytes
;
1451 CORE_ADDR end_prologue_addr
= 0;
1453 /* Can be called when there's no process, and hence when there's no
1455 if (next_frame
!= NULL
)
1456 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1460 if (limit_pc
> start_pc
+ 200)
1461 limit_pc
= start_pc
+ 200;
1463 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1465 /* Save the previous instruction. If it's an EXTEND, we'll extract
1466 the immediate offset extension from it in mips16_get_imm. */
1469 /* Fetch and decode the instruction. */
1470 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1472 /* Normally we ignore extend instructions. However, if it is
1473 not followed by a valid prologue instruction, then this
1474 instruction is not part of the prologue either. We must
1475 remember in this case to adjust the end_prologue_addr back
1477 if ((inst
& 0xf800) == 0xf000) /* extend */
1479 extend_bytes
= MIPS_INSN16_SIZE
;
1483 prev_extend_bytes
= extend_bytes
;
1486 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1487 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1489 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1490 if (offset
< 0) /* negative stack adjustment? */
1491 frame_offset
-= offset
;
1493 /* Exit loop if a positive stack adjustment is found, which
1494 usually means that the stack cleanup code in the function
1495 epilogue is reached. */
1498 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1500 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1501 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1502 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1504 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1506 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1507 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1508 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1510 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1512 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1513 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1515 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1517 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1518 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1520 else if (inst
== 0x673d) /* move $s1, $sp */
1525 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1527 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1528 frame_addr
= sp
+ offset
;
1530 frame_adjust
= offset
;
1532 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1534 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1535 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1536 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1538 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1540 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1541 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1542 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1544 else if ((inst
& 0xf81f) == 0xe809
1545 && (inst
& 0x700) != 0x700) /* entry */
1546 entry_inst
= inst
; /* save for later processing */
1547 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1548 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1549 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1551 /* This instruction is part of the prologue, but we don't
1552 need to do anything special to handle it. */
1556 /* This instruction is not an instruction typically found
1557 in a prologue, so we must have reached the end of the
1559 if (end_prologue_addr
== 0)
1560 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1564 /* The entry instruction is typically the first instruction in a function,
1565 and it stores registers at offsets relative to the value of the old SP
1566 (before the prologue). But the value of the sp parameter to this
1567 function is the new SP (after the prologue has been executed). So we
1568 can't calculate those offsets until we've seen the entire prologue,
1569 and can calculate what the old SP must have been. */
1570 if (entry_inst
!= 0)
1572 int areg_count
= (entry_inst
>> 8) & 7;
1573 int sreg_count
= (entry_inst
>> 6) & 3;
1575 /* The entry instruction always subtracts 32 from the SP. */
1578 /* Now we can calculate what the SP must have been at the
1579 start of the function prologue. */
1582 /* Check if a0-a3 were saved in the caller's argument save area. */
1583 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1585 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1586 offset
+= mips_abi_regsize (current_gdbarch
);
1589 /* Check if the ra register was pushed on the stack. */
1591 if (entry_inst
& 0x20)
1593 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1594 offset
-= mips_abi_regsize (current_gdbarch
);
1597 /* Check if the s0 and s1 registers were pushed on the stack. */
1598 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1600 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1601 offset
-= mips_abi_regsize (current_gdbarch
);
1605 if (this_cache
!= NULL
)
1608 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1609 + frame_offset
- frame_adjust
);
1610 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1611 be able to get rid of the assignment below, evetually. But it's
1612 still needed for now. */
1613 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1614 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1617 /* If we didn't reach the end of the prologue when scanning the function
1618 instructions, then set end_prologue_addr to the address of the
1619 instruction immediately after the last one we scanned. */
1620 if (end_prologue_addr
== 0)
1621 end_prologue_addr
= cur_pc
;
1623 return end_prologue_addr
;
1626 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1627 Procedures that use the 32-bit instruction set are handled by the
1628 mips_insn32 unwinder. */
1630 static struct mips_frame_cache
*
1631 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1633 struct mips_frame_cache
*cache
;
1635 if ((*this_cache
) != NULL
)
1636 return (*this_cache
);
1637 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1638 (*this_cache
) = cache
;
1639 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1641 /* Analyze the function prologue. */
1643 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1644 CORE_ADDR start_addr
;
1646 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1647 if (start_addr
== 0)
1648 start_addr
= heuristic_proc_start (pc
);
1649 /* We can't analyze the prologue if we couldn't find the begining
1651 if (start_addr
== 0)
1654 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1657 /* SP_REGNUM, contains the value and not the address. */
1658 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1660 return (*this_cache
);
1664 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1665 struct frame_id
*this_id
)
1667 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1669 (*this_id
) = frame_id_build (info
->base
,
1670 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1674 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1676 int regnum
, int *optimizedp
,
1677 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1678 int *realnump
, gdb_byte
*valuep
)
1680 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1682 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1683 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1686 static const struct frame_unwind mips_insn16_frame_unwind
=
1689 mips_insn16_frame_this_id
,
1690 mips_insn16_frame_prev_register
1693 static const struct frame_unwind
*
1694 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1696 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1697 if (mips_pc_is_mips16 (pc
))
1698 return &mips_insn16_frame_unwind
;
1703 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1706 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1711 static const struct frame_base mips_insn16_frame_base
=
1713 &mips_insn16_frame_unwind
,
1714 mips_insn16_frame_base_address
,
1715 mips_insn16_frame_base_address
,
1716 mips_insn16_frame_base_address
1719 static const struct frame_base
*
1720 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1722 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1723 return &mips_insn16_frame_base
;
1728 /* Mark all the registers as unset in the saved_regs array
1729 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1732 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1734 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1738 const int num_regs
= NUM_REGS
;
1741 for (i
= 0; i
< num_regs
; i
++)
1743 this_cache
->saved_regs
[i
].addr
= -1;
1748 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1749 the associated FRAME_CACHE if not null.
1750 Return the address of the first instruction past the prologue. */
1753 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1754 struct frame_info
*next_frame
,
1755 struct mips_frame_cache
*this_cache
)
1758 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1761 int frame_reg
= MIPS_SP_REGNUM
;
1763 CORE_ADDR end_prologue_addr
= 0;
1764 int seen_sp_adjust
= 0;
1765 int load_immediate_bytes
= 0;
1767 /* Can be called when there's no process, and hence when there's no
1769 if (next_frame
!= NULL
)
1770 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1774 if (limit_pc
> start_pc
+ 200)
1775 limit_pc
= start_pc
+ 200;
1780 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1782 unsigned long inst
, high_word
, low_word
;
1785 /* Fetch the instruction. */
1786 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1788 /* Save some code by pre-extracting some useful fields. */
1789 high_word
= (inst
>> 16) & 0xffff;
1790 low_word
= inst
& 0xffff;
1791 reg
= high_word
& 0x1f;
1793 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1794 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1795 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1797 if (low_word
& 0x8000) /* negative stack adjustment? */
1798 frame_offset
+= 0x10000 - low_word
;
1800 /* Exit loop if a positive stack adjustment is found, which
1801 usually means that the stack cleanup code in the function
1802 epilogue is reached. */
1806 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1808 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1810 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1812 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1813 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1815 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1817 /* Old gcc frame, r30 is virtual frame pointer. */
1818 if ((long) low_word
!= frame_offset
)
1819 frame_addr
= sp
+ low_word
;
1820 else if (frame_reg
== MIPS_SP_REGNUM
)
1822 unsigned alloca_adjust
;
1825 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1826 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1827 if (alloca_adjust
> 0)
1829 /* FP > SP + frame_size. This may be because of
1830 an alloca or somethings similar. Fix sp to
1831 "pre-alloca" value, and try again. */
1832 sp
+= alloca_adjust
;
1833 /* Need to reset the status of all registers. Otherwise,
1834 we will hit a guard that prevents the new address
1835 for each register to be recomputed during the second
1837 reset_saved_regs (this_cache
);
1842 /* move $30,$sp. With different versions of gas this will be either
1843 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1844 Accept any one of these. */
1845 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1847 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1848 if (frame_reg
== MIPS_SP_REGNUM
)
1850 unsigned alloca_adjust
;
1853 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1854 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1855 if (alloca_adjust
> 0)
1857 /* FP > SP + frame_size. This may be because of
1858 an alloca or somethings similar. Fix sp to
1859 "pre-alloca" value, and try again. */
1861 /* Need to reset the status of all registers. Otherwise,
1862 we will hit a guard that prevents the new address
1863 for each register to be recomputed during the second
1865 reset_saved_regs (this_cache
);
1870 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1872 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1874 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1875 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1876 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1877 || high_word
== 0x3c1c /* lui $gp,n */
1878 || high_word
== 0x279c /* addiu $gp,$gp,n */
1879 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1880 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1883 /* These instructions are part of the prologue, but we don't
1884 need to do anything special to handle them. */
1886 /* The instructions below load $at or $t0 with an immediate
1887 value in preparation for a stack adjustment via
1888 subu $sp,$sp,[$at,$t0]. These instructions could also
1889 initialize a local variable, so we accept them only before
1890 a stack adjustment instruction was seen. */
1891 else if (!seen_sp_adjust
1892 && (high_word
== 0x3c01 /* lui $at,n */
1893 || high_word
== 0x3c08 /* lui $t0,n */
1894 || high_word
== 0x3421 /* ori $at,$at,n */
1895 || high_word
== 0x3508 /* ori $t0,$t0,n */
1896 || high_word
== 0x3401 /* ori $at,$zero,n */
1897 || high_word
== 0x3408 /* ori $t0,$zero,n */
1900 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1904 /* This instruction is not an instruction typically found
1905 in a prologue, so we must have reached the end of the
1907 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1908 loop now? Why would we need to continue scanning the function
1910 if (end_prologue_addr
== 0)
1911 end_prologue_addr
= cur_pc
;
1915 if (this_cache
!= NULL
)
1918 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1920 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1921 this assignment below, eventually. But it's still needed
1923 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1924 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1927 /* If we didn't reach the end of the prologue when scanning the function
1928 instructions, then set end_prologue_addr to the address of the
1929 instruction immediately after the last one we scanned. */
1930 /* brobecker/2004-10-10: I don't think this would ever happen, but
1931 we may as well be careful and do our best if we have a null
1932 end_prologue_addr. */
1933 if (end_prologue_addr
== 0)
1934 end_prologue_addr
= cur_pc
;
1936 /* In a frameless function, we might have incorrectly
1937 skipped some load immediate instructions. Undo the skipping
1938 if the load immediate was not followed by a stack adjustment. */
1939 if (load_immediate_bytes
&& !seen_sp_adjust
)
1940 end_prologue_addr
-= load_immediate_bytes
;
1942 return end_prologue_addr
;
1945 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1946 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1947 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1950 static struct mips_frame_cache
*
1951 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1953 struct mips_frame_cache
*cache
;
1955 if ((*this_cache
) != NULL
)
1956 return (*this_cache
);
1958 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1959 (*this_cache
) = cache
;
1960 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1962 /* Analyze the function prologue. */
1964 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1965 CORE_ADDR start_addr
;
1967 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1968 if (start_addr
== 0)
1969 start_addr
= heuristic_proc_start (pc
);
1970 /* We can't analyze the prologue if we couldn't find the begining
1972 if (start_addr
== 0)
1975 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1978 /* SP_REGNUM, contains the value and not the address. */
1979 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1981 return (*this_cache
);
1985 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1986 struct frame_id
*this_id
)
1988 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1990 (*this_id
) = frame_id_build (info
->base
,
1991 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1995 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1997 int regnum
, int *optimizedp
,
1998 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1999 int *realnump
, gdb_byte
*valuep
)
2001 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2003 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2004 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2007 static const struct frame_unwind mips_insn32_frame_unwind
=
2010 mips_insn32_frame_this_id
,
2011 mips_insn32_frame_prev_register
2014 static const struct frame_unwind
*
2015 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2017 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2018 if (! mips_pc_is_mips16 (pc
))
2019 return &mips_insn32_frame_unwind
;
2024 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2027 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2032 static const struct frame_base mips_insn32_frame_base
=
2034 &mips_insn32_frame_unwind
,
2035 mips_insn32_frame_base_address
,
2036 mips_insn32_frame_base_address
,
2037 mips_insn32_frame_base_address
2040 static const struct frame_base
*
2041 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2043 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2044 return &mips_insn32_frame_base
;
2049 static struct trad_frame_cache
*
2050 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2053 CORE_ADDR start_addr
;
2054 CORE_ADDR stack_addr
;
2055 struct trad_frame_cache
*this_trad_cache
;
2057 if ((*this_cache
) != NULL
)
2058 return (*this_cache
);
2059 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2060 (*this_cache
) = this_trad_cache
;
2062 /* The return address is in the link register. */
2063 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2065 /* Frame ID, since it's a frameless / stackless function, no stack
2066 space is allocated and SP on entry is the current SP. */
2067 pc
= frame_pc_unwind (next_frame
);
2068 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2069 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2070 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2072 /* Assume that the frame's base is the same as the
2074 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2076 return this_trad_cache
;
2080 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2081 struct frame_id
*this_id
)
2083 struct trad_frame_cache
*this_trad_cache
2084 = mips_stub_frame_cache (next_frame
, this_cache
);
2085 trad_frame_get_id (this_trad_cache
, this_id
);
2089 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2091 int regnum
, int *optimizedp
,
2092 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2093 int *realnump
, gdb_byte
*valuep
)
2095 struct trad_frame_cache
*this_trad_cache
2096 = mips_stub_frame_cache (next_frame
, this_cache
);
2097 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2098 lvalp
, addrp
, realnump
, valuep
);
2101 static const struct frame_unwind mips_stub_frame_unwind
=
2104 mips_stub_frame_this_id
,
2105 mips_stub_frame_prev_register
2108 static const struct frame_unwind
*
2109 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2111 struct obj_section
*s
;
2112 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2114 if (in_plt_section (pc
, NULL
))
2115 return &mips_stub_frame_unwind
;
2117 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2118 s
= find_pc_section (pc
);
2121 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2122 ".MIPS.stubs") == 0)
2123 return &mips_stub_frame_unwind
;
2129 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2132 struct trad_frame_cache
*this_trad_cache
2133 = mips_stub_frame_cache (next_frame
, this_cache
);
2134 return trad_frame_get_this_base (this_trad_cache
);
2137 static const struct frame_base mips_stub_frame_base
=
2139 &mips_stub_frame_unwind
,
2140 mips_stub_frame_base_address
,
2141 mips_stub_frame_base_address
,
2142 mips_stub_frame_base_address
2145 static const struct frame_base
*
2146 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2148 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2149 return &mips_stub_frame_base
;
2155 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2157 /* Always a pseudo. */
2158 gdb_assert (regno
>= NUM_REGS
);
2162 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2166 return frame_unwind_register_signed (fi
, regno
);
2170 /* mips_addr_bits_remove - remove useless address bits */
2173 mips_addr_bits_remove (CORE_ADDR addr
)
2175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2176 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2177 /* This hack is a work-around for existing boards using PMON, the
2178 simulator, and any other 64-bit targets that doesn't have true
2179 64-bit addressing. On these targets, the upper 32 bits of
2180 addresses are ignored by the hardware. Thus, the PC or SP are
2181 likely to have been sign extended to all 1s by instruction
2182 sequences that load 32-bit addresses. For example, a typical
2183 piece of code that loads an address is this:
2185 lui $r2, <upper 16 bits>
2186 ori $r2, <lower 16 bits>
2188 But the lui sign-extends the value such that the upper 32 bits
2189 may be all 1s. The workaround is simply to mask off these
2190 bits. In the future, gcc may be changed to support true 64-bit
2191 addressing, and this masking will have to be disabled. */
2192 return addr
&= 0xffffffffUL
;
2197 /* mips_software_single_step() is called just before we want to resume
2198 the inferior, if we want to single-step it but there is no hardware
2199 or kernel single-step support (MIPS on GNU/Linux for example). We find
2200 the target of the coming instruction and breakpoint it.
2202 single_step is also called just after the inferior stops. If we had
2203 set up a simulated single-step, we undo our damage. */
2206 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2208 CORE_ADDR pc
, next_pc
;
2210 if (insert_breakpoints_p
)
2212 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2213 next_pc
= mips_next_pc (pc
);
2215 insert_single_step_breakpoint (next_pc
);
2218 remove_single_step_breakpoints ();
2221 /* Test whether the PC points to the return instruction at the
2222 end of a function. */
2225 mips_about_to_return (CORE_ADDR pc
)
2227 if (mips_pc_is_mips16 (pc
))
2228 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2229 generates a "jr $ra"; other times it generates code to load
2230 the return address from the stack to an accessible register (such
2231 as $a3), then a "jr" using that register. This second case
2232 is almost impossible to distinguish from an indirect jump
2233 used for switch statements, so we don't even try. */
2234 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2236 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2240 /* This fencepost looks highly suspicious to me. Removing it also
2241 seems suspicious as it could affect remote debugging across serial
2245 heuristic_proc_start (CORE_ADDR pc
)
2252 pc
= ADDR_BITS_REMOVE (pc
);
2254 fence
= start_pc
- heuristic_fence_post
;
2258 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2259 fence
= VM_MIN_ADDRESS
;
2261 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2263 /* search back for previous return */
2264 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2265 if (start_pc
< fence
)
2267 /* It's not clear to me why we reach this point when
2268 stop_soon, but with this test, at least we
2269 don't print out warnings for every child forked (eg, on
2270 decstation). 22apr93 rich@cygnus.com. */
2271 if (stop_soon
== NO_STOP_QUIETLY
)
2273 static int blurb_printed
= 0;
2275 warning (_("GDB can't find the start of the function at 0x%s."),
2280 /* This actually happens frequently in embedded
2281 development, when you first connect to a board
2282 and your stack pointer and pc are nowhere in
2283 particular. This message needs to give people
2284 in that situation enough information to
2285 determine that it's no big deal. */
2286 printf_filtered ("\n\
2287 GDB is unable to find the start of the function at 0x%s\n\
2288 and thus can't determine the size of that function's stack frame.\n\
2289 This means that GDB may be unable to access that stack frame, or\n\
2290 the frames below it.\n\
2291 This problem is most likely caused by an invalid program counter or\n\
2293 However, if you think GDB should simply search farther back\n\
2294 from 0x%s for code which looks like the beginning of a\n\
2295 function, you can increase the range of the search using the `set\n\
2296 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2303 else if (mips_pc_is_mips16 (start_pc
))
2305 unsigned short inst
;
2307 /* On MIPS16, any one of the following is likely to be the
2308 start of a function:
2312 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2313 inst
= mips_fetch_instruction (start_pc
);
2314 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2315 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2316 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2317 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2319 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2320 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2325 else if (mips_about_to_return (start_pc
))
2327 /* Skip return and its delay slot. */
2328 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2335 struct mips_objfile_private
2341 /* According to the current ABI, should the type be passed in a
2342 floating-point register (assuming that there is space)? When there
2343 is no FPU, FP are not even considered as possible candidates for
2344 FP registers and, consequently this returns false - forces FP
2345 arguments into integer registers. */
2348 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2350 return ((typecode
== TYPE_CODE_FLT
2352 && (typecode
== TYPE_CODE_STRUCT
2353 || typecode
== TYPE_CODE_UNION
)
2354 && TYPE_NFIELDS (arg_type
) == 1
2355 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2357 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2360 /* On o32, argument passing in GPRs depends on the alignment of the type being
2361 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2364 mips_type_needs_double_align (struct type
*type
)
2366 enum type_code typecode
= TYPE_CODE (type
);
2368 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2370 else if (typecode
== TYPE_CODE_STRUCT
)
2372 if (TYPE_NFIELDS (type
) < 1)
2374 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2376 else if (typecode
== TYPE_CODE_UNION
)
2380 n
= TYPE_NFIELDS (type
);
2381 for (i
= 0; i
< n
; i
++)
2382 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2389 /* Adjust the address downward (direction of stack growth) so that it
2390 is correctly aligned for a new stack frame. */
2392 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2394 return align_down (addr
, 16);
2398 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2399 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2400 int nargs
, struct value
**args
, CORE_ADDR sp
,
2401 int struct_return
, CORE_ADDR struct_addr
)
2407 int stack_offset
= 0;
2408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2409 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2411 /* For shared libraries, "t9" needs to point at the function
2413 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2415 /* Set the return address register to point to the entry point of
2416 the program, where a breakpoint lies in wait. */
2417 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2419 /* First ensure that the stack and structure return address (if any)
2420 are properly aligned. The stack has to be at least 64-bit
2421 aligned even on 32-bit machines, because doubles must be 64-bit
2422 aligned. For n32 and n64, stack frames need to be 128-bit
2423 aligned, so we round to this widest known alignment. */
2425 sp
= align_down (sp
, 16);
2426 struct_addr
= align_down (struct_addr
, 16);
2428 /* Now make space on the stack for the args. We allocate more
2429 than necessary for EABI, because the first few arguments are
2430 passed in registers, but that's OK. */
2431 for (argnum
= 0; argnum
< nargs
; argnum
++)
2432 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2433 mips_stack_argsize (gdbarch
));
2434 sp
-= align_up (len
, 16);
2437 fprintf_unfiltered (gdb_stdlog
,
2438 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2439 paddr_nz (sp
), (long) align_up (len
, 16));
2441 /* Initialize the integer and float register pointers. */
2442 argreg
= MIPS_A0_REGNUM
;
2443 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2445 /* The struct_return pointer occupies the first parameter-passing reg. */
2449 fprintf_unfiltered (gdb_stdlog
,
2450 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2451 argreg
, paddr_nz (struct_addr
));
2452 write_register (argreg
++, struct_addr
);
2455 /* Now load as many as possible of the first arguments into
2456 registers, and push the rest onto the stack. Loop thru args
2457 from first to last. */
2458 for (argnum
= 0; argnum
< nargs
; argnum
++)
2460 const gdb_byte
*val
;
2461 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2462 struct value
*arg
= args
[argnum
];
2463 struct type
*arg_type
= check_typedef (value_type (arg
));
2464 int len
= TYPE_LENGTH (arg_type
);
2465 enum type_code typecode
= TYPE_CODE (arg_type
);
2468 fprintf_unfiltered (gdb_stdlog
,
2469 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2470 argnum
+ 1, len
, (int) typecode
);
2472 /* The EABI passes structures that do not fit in a register by
2474 if (len
> mips_abi_regsize (gdbarch
)
2475 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2477 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2478 VALUE_ADDRESS (arg
));
2479 typecode
= TYPE_CODE_PTR
;
2480 len
= mips_abi_regsize (gdbarch
);
2483 fprintf_unfiltered (gdb_stdlog
, " push");
2486 val
= value_contents (arg
);
2488 /* 32-bit ABIs always start floating point arguments in an
2489 even-numbered floating point register. Round the FP register
2490 up before the check to see if there are any FP registers
2491 left. Non MIPS_EABI targets also pass the FP in the integer
2492 registers so also round up normal registers. */
2493 if (mips_abi_regsize (gdbarch
) < 8
2494 && fp_register_arg_p (typecode
, arg_type
))
2496 if ((float_argreg
& 1))
2500 /* Floating point arguments passed in registers have to be
2501 treated specially. On 32-bit architectures, doubles
2502 are passed in register pairs; the even register gets
2503 the low word, and the odd register gets the high word.
2504 On non-EABI processors, the first two floating point arguments are
2505 also copied to general registers, because MIPS16 functions
2506 don't use float registers for arguments. This duplication of
2507 arguments in general registers can't hurt non-MIPS16 functions
2508 because those registers are normally skipped. */
2509 /* MIPS_EABI squeezes a struct that contains a single floating
2510 point value into an FP register instead of pushing it onto the
2512 if (fp_register_arg_p (typecode
, arg_type
)
2513 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2515 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
2517 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2518 unsigned long regval
;
2520 /* Write the low word of the double to the even register(s). */
2521 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2523 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2524 float_argreg
, phex (regval
, 4));
2525 write_register (float_argreg
++, regval
);
2527 /* Write the high word of the double to the odd register(s). */
2528 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2530 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2531 float_argreg
, phex (regval
, 4));
2532 write_register (float_argreg
++, regval
);
2536 /* This is a floating point value that fits entirely
2537 in a single register. */
2538 /* On 32 bit ABI's the float_argreg is further adjusted
2539 above to ensure that it is even register aligned. */
2540 LONGEST regval
= extract_unsigned_integer (val
, len
);
2542 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2543 float_argreg
, phex (regval
, len
));
2544 write_register (float_argreg
++, regval
);
2549 /* Copy the argument to general registers or the stack in
2550 register-sized pieces. Large arguments are split between
2551 registers and stack. */
2552 /* Note: structs whose size is not a multiple of
2553 mips_abi_regsize() are treated specially: Irix cc passes
2554 them in registers where gcc sometimes puts them on the
2555 stack. For maximum compatibility, we will put them in
2557 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2558 && (len
% mips_abi_regsize (gdbarch
) != 0));
2560 /* Note: Floating-point values that didn't fit into an FP
2561 register are only written to memory. */
2564 /* Remember if the argument was written to the stack. */
2565 int stack_used_p
= 0;
2566 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2567 ? len
: mips_abi_regsize (gdbarch
));
2570 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2573 /* Write this portion of the argument to the stack. */
2574 if (argreg
> MIPS_LAST_ARG_REGNUM
2576 || fp_register_arg_p (typecode
, arg_type
))
2578 /* Should shorter than int integer values be
2579 promoted to int before being stored? */
2580 int longword_offset
= 0;
2583 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2585 if (mips_stack_argsize (gdbarch
) == 8
2586 && (typecode
== TYPE_CODE_INT
2587 || typecode
== TYPE_CODE_PTR
2588 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2589 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2590 else if ((typecode
== TYPE_CODE_STRUCT
2591 || typecode
== TYPE_CODE_UNION
)
2592 && (TYPE_LENGTH (arg_type
)
2593 < mips_stack_argsize (gdbarch
)))
2594 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2599 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2600 paddr_nz (stack_offset
));
2601 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2602 paddr_nz (longword_offset
));
2605 addr
= sp
+ stack_offset
+ longword_offset
;
2610 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2612 for (i
= 0; i
< partial_len
; i
++)
2614 fprintf_unfiltered (gdb_stdlog
, "%02x",
2618 write_memory (addr
, val
, partial_len
);
2621 /* Note!!! This is NOT an else clause. Odd sized
2622 structs may go thru BOTH paths. Floating point
2623 arguments will not. */
2624 /* Write this portion of the argument to a general
2625 purpose register. */
2626 if (argreg
<= MIPS_LAST_ARG_REGNUM
2627 && !fp_register_arg_p (typecode
, arg_type
))
2630 extract_unsigned_integer (val
, partial_len
);
2633 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2636 mips_abi_regsize (gdbarch
)));
2637 write_register (argreg
, regval
);
2644 /* Compute the the offset into the stack at which we
2645 will copy the next parameter.
2647 In the new EABI (and the NABI32), the stack_offset
2648 only needs to be adjusted when it has been used. */
2651 stack_offset
+= align_up (partial_len
,
2652 mips_stack_argsize (gdbarch
));
2656 fprintf_unfiltered (gdb_stdlog
, "\n");
2659 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2661 /* Return adjusted stack pointer. */
2665 /* Determine the return value convention being used. */
2667 static enum return_value_convention
2668 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2669 struct type
*type
, struct regcache
*regcache
,
2670 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2672 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2673 return RETURN_VALUE_STRUCT_CONVENTION
;
2675 memset (readbuf
, 0, TYPE_LENGTH (type
));
2676 return RETURN_VALUE_REGISTER_CONVENTION
;
2680 /* N32/N64 ABI stuff. */
2683 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2684 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2685 int nargs
, struct value
**args
, CORE_ADDR sp
,
2686 int struct_return
, CORE_ADDR struct_addr
)
2692 int stack_offset
= 0;
2693 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2694 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2696 /* For shared libraries, "t9" needs to point at the function
2698 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2700 /* Set the return address register to point to the entry point of
2701 the program, where a breakpoint lies in wait. */
2702 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2704 /* First ensure that the stack and structure return address (if any)
2705 are properly aligned. The stack has to be at least 64-bit
2706 aligned even on 32-bit machines, because doubles must be 64-bit
2707 aligned. For n32 and n64, stack frames need to be 128-bit
2708 aligned, so we round to this widest known alignment. */
2710 sp
= align_down (sp
, 16);
2711 struct_addr
= align_down (struct_addr
, 16);
2713 /* Now make space on the stack for the args. */
2714 for (argnum
= 0; argnum
< nargs
; argnum
++)
2715 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2716 mips_stack_argsize (gdbarch
));
2717 sp
-= align_up (len
, 16);
2720 fprintf_unfiltered (gdb_stdlog
,
2721 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2722 paddr_nz (sp
), (long) align_up (len
, 16));
2724 /* Initialize the integer and float register pointers. */
2725 argreg
= MIPS_A0_REGNUM
;
2726 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2728 /* The struct_return pointer occupies the first parameter-passing reg. */
2732 fprintf_unfiltered (gdb_stdlog
,
2733 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2734 argreg
, paddr_nz (struct_addr
));
2735 write_register (argreg
++, struct_addr
);
2738 /* Now load as many as possible of the first arguments into
2739 registers, and push the rest onto the stack. Loop thru args
2740 from first to last. */
2741 for (argnum
= 0; argnum
< nargs
; argnum
++)
2743 const gdb_byte
*val
;
2744 struct value
*arg
= args
[argnum
];
2745 struct type
*arg_type
= check_typedef (value_type (arg
));
2746 int len
= TYPE_LENGTH (arg_type
);
2747 enum type_code typecode
= TYPE_CODE (arg_type
);
2750 fprintf_unfiltered (gdb_stdlog
,
2751 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2752 argnum
+ 1, len
, (int) typecode
);
2754 val
= value_contents (arg
);
2756 if (fp_register_arg_p (typecode
, arg_type
)
2757 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2759 /* This is a floating point value that fits entirely
2760 in a single register. */
2761 /* On 32 bit ABI's the float_argreg is further adjusted
2762 above to ensure that it is even register aligned. */
2763 LONGEST regval
= extract_unsigned_integer (val
, len
);
2765 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2766 float_argreg
, phex (regval
, len
));
2767 write_register (float_argreg
++, regval
);
2770 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2771 argreg
, phex (regval
, len
));
2772 write_register (argreg
, regval
);
2777 /* Copy the argument to general registers or the stack in
2778 register-sized pieces. Large arguments are split between
2779 registers and stack. */
2780 /* Note: structs whose size is not a multiple of
2781 mips_abi_regsize() are treated specially: Irix cc passes
2782 them in registers where gcc sometimes puts them on the
2783 stack. For maximum compatibility, we will put them in
2785 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2786 && (len
% mips_abi_regsize (gdbarch
) != 0));
2787 /* Note: Floating-point values that didn't fit into an FP
2788 register are only written to memory. */
2791 /* Rememer if the argument was written to the stack. */
2792 int stack_used_p
= 0;
2793 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2794 ? len
: mips_abi_regsize (gdbarch
));
2797 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2800 /* Write this portion of the argument to the stack. */
2801 if (argreg
> MIPS_LAST_ARG_REGNUM
2803 || fp_register_arg_p (typecode
, arg_type
))
2805 /* Should shorter than int integer values be
2806 promoted to int before being stored? */
2807 int longword_offset
= 0;
2810 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2812 if (mips_stack_argsize (gdbarch
) == 8
2813 && (typecode
== TYPE_CODE_INT
2814 || typecode
== TYPE_CODE_PTR
2815 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2816 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2821 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2822 paddr_nz (stack_offset
));
2823 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2824 paddr_nz (longword_offset
));
2827 addr
= sp
+ stack_offset
+ longword_offset
;
2832 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2834 for (i
= 0; i
< partial_len
; i
++)
2836 fprintf_unfiltered (gdb_stdlog
, "%02x",
2840 write_memory (addr
, val
, partial_len
);
2843 /* Note!!! This is NOT an else clause. Odd sized
2844 structs may go thru BOTH paths. Floating point
2845 arguments will not. */
2846 /* Write this portion of the argument to a general
2847 purpose register. */
2848 if (argreg
<= MIPS_LAST_ARG_REGNUM
2849 && !fp_register_arg_p (typecode
, arg_type
))
2852 extract_unsigned_integer (val
, partial_len
);
2854 /* A non-floating-point argument being passed in a
2855 general register. If a struct or union, and if
2856 the remaining length is smaller than the register
2857 size, we have to adjust the register value on
2860 It does not seem to be necessary to do the
2861 same for integral types.
2863 cagney/2001-07-23: gdb/179: Also, GCC, when
2864 outputting LE O32 with sizeof (struct) <
2865 mips_abi_regsize(), generates a left shift as
2866 part of storing the argument in a register a
2867 register (the left shift isn't generated when
2868 sizeof (struct) >= mips_abi_regsize()). Since
2869 it is quite possible that this is GCC
2870 contradicting the LE/O32 ABI, GDB has not been
2871 adjusted to accommodate this. Either someone
2872 needs to demonstrate that the LE/O32 ABI
2873 specifies such a left shift OR this new ABI gets
2874 identified as such and GDB gets tweaked
2877 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2878 && partial_len
< mips_abi_regsize (gdbarch
)
2879 && (typecode
== TYPE_CODE_STRUCT
||
2880 typecode
== TYPE_CODE_UNION
))
2881 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
2885 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2888 mips_abi_regsize (gdbarch
)));
2889 write_register (argreg
, regval
);
2896 /* Compute the the offset into the stack at which we
2897 will copy the next parameter.
2899 In N32 (N64?), the stack_offset only needs to be
2900 adjusted when it has been used. */
2903 stack_offset
+= align_up (partial_len
,
2904 mips_stack_argsize (gdbarch
));
2908 fprintf_unfiltered (gdb_stdlog
, "\n");
2911 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2913 /* Return adjusted stack pointer. */
2917 static enum return_value_convention
2918 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2919 struct type
*type
, struct regcache
*regcache
,
2920 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2922 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2923 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2924 || TYPE_CODE (type
) == TYPE_CODE_UNION
2925 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2926 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2927 return RETURN_VALUE_STRUCT_CONVENTION
;
2928 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2929 && TYPE_LENGTH (type
) == 16
2930 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2932 /* A 128-bit floating-point value fills both $f0 and $f2. The
2933 two registers are used in the same as memory order, so the
2934 eight bytes with the lower memory address are in $f0. */
2936 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2937 mips_xfer_register (regcache
,
2938 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2939 8, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2940 mips_xfer_register (regcache
,
2941 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 2,
2942 8, TARGET_BYTE_ORDER
, readbuf
? readbuf
+ 8 : readbuf
,
2943 writebuf
? writebuf
+ 8 : writebuf
, 0);
2944 return RETURN_VALUE_REGISTER_CONVENTION
;
2946 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2947 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2949 /* A floating-point value belongs in the least significant part
2952 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2953 mips_xfer_register (regcache
,
2954 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2956 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2957 return RETURN_VALUE_REGISTER_CONVENTION
;
2959 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2960 && TYPE_NFIELDS (type
) <= 2
2961 && TYPE_NFIELDS (type
) >= 1
2962 && ((TYPE_NFIELDS (type
) == 1
2963 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2965 || (TYPE_NFIELDS (type
) == 2
2966 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2968 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2970 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2972 /* A struct that contains one or two floats. Each value is part
2973 in the least significant part of their floating point
2977 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2978 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2980 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2983 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2985 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2986 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2987 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2989 return RETURN_VALUE_REGISTER_CONVENTION
;
2991 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2992 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2994 /* A structure or union. Extract the left justified value,
2995 regardless of the byte order. I.e. DO NOT USE
2999 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3000 offset
< TYPE_LENGTH (type
);
3001 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3003 int xfer
= register_size (current_gdbarch
, regnum
);
3004 if (offset
+ xfer
> TYPE_LENGTH (type
))
3005 xfer
= TYPE_LENGTH (type
) - offset
;
3007 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3008 offset
, xfer
, regnum
);
3009 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3010 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3012 return RETURN_VALUE_REGISTER_CONVENTION
;
3016 /* A scalar extract each part but least-significant-byte
3020 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3021 offset
< TYPE_LENGTH (type
);
3022 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3024 int xfer
= register_size (current_gdbarch
, regnum
);
3025 if (offset
+ xfer
> TYPE_LENGTH (type
))
3026 xfer
= TYPE_LENGTH (type
) - offset
;
3028 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3029 offset
, xfer
, regnum
);
3030 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3031 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3033 return RETURN_VALUE_REGISTER_CONVENTION
;
3037 /* O32 ABI stuff. */
3040 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3041 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3042 int nargs
, struct value
**args
, CORE_ADDR sp
,
3043 int struct_return
, CORE_ADDR struct_addr
)
3049 int stack_offset
= 0;
3050 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3051 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3053 /* For shared libraries, "t9" needs to point at the function
3055 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3057 /* Set the return address register to point to the entry point of
3058 the program, where a breakpoint lies in wait. */
3059 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3061 /* First ensure that the stack and structure return address (if any)
3062 are properly aligned. The stack has to be at least 64-bit
3063 aligned even on 32-bit machines, because doubles must be 64-bit
3064 aligned. For n32 and n64, stack frames need to be 128-bit
3065 aligned, so we round to this widest known alignment. */
3067 sp
= align_down (sp
, 16);
3068 struct_addr
= align_down (struct_addr
, 16);
3070 /* Now make space on the stack for the args. */
3071 for (argnum
= 0; argnum
< nargs
; argnum
++)
3072 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
3073 mips_stack_argsize (gdbarch
));
3074 sp
-= align_up (len
, 16);
3077 fprintf_unfiltered (gdb_stdlog
,
3078 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3079 paddr_nz (sp
), (long) align_up (len
, 16));
3081 /* Initialize the integer and float register pointers. */
3082 argreg
= MIPS_A0_REGNUM
;
3083 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3085 /* The struct_return pointer occupies the first parameter-passing reg. */
3089 fprintf_unfiltered (gdb_stdlog
,
3090 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3091 argreg
, paddr_nz (struct_addr
));
3092 write_register (argreg
++, struct_addr
);
3093 stack_offset
+= mips_stack_argsize (gdbarch
);
3096 /* Now load as many as possible of the first arguments into
3097 registers, and push the rest onto the stack. Loop thru args
3098 from first to last. */
3099 for (argnum
= 0; argnum
< nargs
; argnum
++)
3101 const gdb_byte
*val
;
3102 struct value
*arg
= args
[argnum
];
3103 struct type
*arg_type
= check_typedef (value_type (arg
));
3104 int len
= TYPE_LENGTH (arg_type
);
3105 enum type_code typecode
= TYPE_CODE (arg_type
);
3108 fprintf_unfiltered (gdb_stdlog
,
3109 "mips_o32_push_dummy_call: %d len=%d type=%d",
3110 argnum
+ 1, len
, (int) typecode
);
3112 val
= value_contents (arg
);
3114 /* 32-bit ABIs always start floating point arguments in an
3115 even-numbered floating point register. Round the FP register
3116 up before the check to see if there are any FP registers
3117 left. O32/O64 targets also pass the FP in the integer
3118 registers so also round up normal registers. */
3119 if (mips_abi_regsize (gdbarch
) < 8
3120 && fp_register_arg_p (typecode
, arg_type
))
3122 if ((float_argreg
& 1))
3126 /* Floating point arguments passed in registers have to be
3127 treated specially. On 32-bit architectures, doubles
3128 are passed in register pairs; the even register gets
3129 the low word, and the odd register gets the high word.
3130 On O32/O64, the first two floating point arguments are
3131 also copied to general registers, because MIPS16 functions
3132 don't use float registers for arguments. This duplication of
3133 arguments in general registers can't hurt non-MIPS16 functions
3134 because those registers are normally skipped. */
3136 if (fp_register_arg_p (typecode
, arg_type
)
3137 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3139 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3141 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3142 unsigned long regval
;
3144 /* Write the low word of the double to the even register(s). */
3145 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3147 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3148 float_argreg
, phex (regval
, 4));
3149 write_register (float_argreg
++, regval
);
3151 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3152 argreg
, phex (regval
, 4));
3153 write_register (argreg
++, regval
);
3155 /* Write the high word of the double to the odd register(s). */
3156 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3158 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3159 float_argreg
, phex (regval
, 4));
3160 write_register (float_argreg
++, regval
);
3163 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3164 argreg
, phex (regval
, 4));
3165 write_register (argreg
++, regval
);
3169 /* This is a floating point value that fits entirely
3170 in a single register. */
3171 /* On 32 bit ABI's the float_argreg is further adjusted
3172 above to ensure that it is even register aligned. */
3173 LONGEST regval
= extract_unsigned_integer (val
, len
);
3175 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3176 float_argreg
, phex (regval
, len
));
3177 write_register (float_argreg
++, regval
);
3178 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3179 registers for each argument. The below is (my
3180 guess) to ensure that the corresponding integer
3181 register has reserved the same space. */
3183 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3184 argreg
, phex (regval
, len
));
3185 write_register (argreg
, regval
);
3186 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3188 /* Reserve space for the FP register. */
3189 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3193 /* Copy the argument to general registers or the stack in
3194 register-sized pieces. Large arguments are split between
3195 registers and stack. */
3196 /* Note: structs whose size is not a multiple of
3197 mips_abi_regsize() are treated specially: Irix cc passes
3198 them in registers where gcc sometimes puts them on the
3199 stack. For maximum compatibility, we will put them in
3201 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3202 && (len
% mips_abi_regsize (gdbarch
) != 0));
3203 /* Structures should be aligned to eight bytes (even arg registers)
3204 on MIPS_ABI_O32, if their first member has double precision. */
3205 if (mips_abi_regsize (gdbarch
) < 8
3206 && mips_type_needs_double_align (arg_type
))
3211 /* Note: Floating-point values that didn't fit into an FP
3212 register are only written to memory. */
3215 /* Remember if the argument was written to the stack. */
3216 int stack_used_p
= 0;
3217 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3218 ? len
: mips_abi_regsize (gdbarch
));
3221 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3224 /* Write this portion of the argument to the stack. */
3225 if (argreg
> MIPS_LAST_ARG_REGNUM
3227 || fp_register_arg_p (typecode
, arg_type
))
3229 /* Should shorter than int integer values be
3230 promoted to int before being stored? */
3231 int longword_offset
= 0;
3234 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3236 if (mips_stack_argsize (gdbarch
) == 8
3237 && (typecode
== TYPE_CODE_INT
3238 || typecode
== TYPE_CODE_PTR
3239 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3240 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3245 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3246 paddr_nz (stack_offset
));
3247 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3248 paddr_nz (longword_offset
));
3251 addr
= sp
+ stack_offset
+ longword_offset
;
3256 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3258 for (i
= 0; i
< partial_len
; i
++)
3260 fprintf_unfiltered (gdb_stdlog
, "%02x",
3264 write_memory (addr
, val
, partial_len
);
3267 /* Note!!! This is NOT an else clause. Odd sized
3268 structs may go thru BOTH paths. Floating point
3269 arguments will not. */
3270 /* Write this portion of the argument to a general
3271 purpose register. */
3272 if (argreg
<= MIPS_LAST_ARG_REGNUM
3273 && !fp_register_arg_p (typecode
, arg_type
))
3275 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3276 /* Value may need to be sign extended, because
3277 mips_isa_regsize() != mips_abi_regsize(). */
3279 /* A non-floating-point argument being passed in a
3280 general register. If a struct or union, and if
3281 the remaining length is smaller than the register
3282 size, we have to adjust the register value on
3285 It does not seem to be necessary to do the
3286 same for integral types.
3288 Also don't do this adjustment on O64 binaries.
3290 cagney/2001-07-23: gdb/179: Also, GCC, when
3291 outputting LE O32 with sizeof (struct) <
3292 mips_abi_regsize(), generates a left shift as
3293 part of storing the argument in a register a
3294 register (the left shift isn't generated when
3295 sizeof (struct) >= mips_abi_regsize()). Since
3296 it is quite possible that this is GCC
3297 contradicting the LE/O32 ABI, GDB has not been
3298 adjusted to accommodate this. Either someone
3299 needs to demonstrate that the LE/O32 ABI
3300 specifies such a left shift OR this new ABI gets
3301 identified as such and GDB gets tweaked
3304 if (mips_abi_regsize (gdbarch
) < 8
3305 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3306 && partial_len
< mips_abi_regsize (gdbarch
)
3307 && (typecode
== TYPE_CODE_STRUCT
||
3308 typecode
== TYPE_CODE_UNION
))
3309 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3313 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3316 mips_abi_regsize (gdbarch
)));
3317 write_register (argreg
, regval
);
3320 /* Prevent subsequent floating point arguments from
3321 being passed in floating point registers. */
3322 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3328 /* Compute the the offset into the stack at which we
3329 will copy the next parameter.
3331 In older ABIs, the caller reserved space for
3332 registers that contained arguments. This was loosely
3333 refered to as their "home". Consequently, space is
3334 always allocated. */
3336 stack_offset
+= align_up (partial_len
,
3337 mips_stack_argsize (gdbarch
));
3341 fprintf_unfiltered (gdb_stdlog
, "\n");
3344 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3346 /* Return adjusted stack pointer. */
3350 static enum return_value_convention
3351 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3352 struct regcache
*regcache
,
3353 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3357 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3358 || TYPE_CODE (type
) == TYPE_CODE_UNION
3359 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3360 return RETURN_VALUE_STRUCT_CONVENTION
;
3361 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3362 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3364 /* A single-precision floating-point value. It fits in the
3365 least significant part of FP0. */
3367 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3368 mips_xfer_register (regcache
,
3369 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3371 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3372 return RETURN_VALUE_REGISTER_CONVENTION
;
3374 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3375 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3377 /* A double-precision floating-point value. The most
3378 significant part goes in FP1, and the least significant in
3381 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3382 switch (TARGET_BYTE_ORDER
)
3384 case BFD_ENDIAN_LITTLE
:
3385 mips_xfer_register (regcache
,
3386 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3387 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3388 mips_xfer_register (regcache
,
3389 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3390 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3392 case BFD_ENDIAN_BIG
:
3393 mips_xfer_register (regcache
,
3394 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3395 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3396 mips_xfer_register (regcache
,
3397 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3398 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3401 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3403 return RETURN_VALUE_REGISTER_CONVENTION
;
3406 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3407 && TYPE_NFIELDS (type
) <= 2
3408 && TYPE_NFIELDS (type
) >= 1
3409 && ((TYPE_NFIELDS (type
) == 1
3410 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3412 || (TYPE_NFIELDS (type
) == 2
3413 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3415 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3417 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3419 /* A struct that contains one or two floats. Each value is part
3420 in the least significant part of their floating point
3422 gdb_byte reg
[MAX_REGISTER_SIZE
];
3425 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3426 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3428 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3431 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3433 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3434 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3435 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3437 return RETURN_VALUE_REGISTER_CONVENTION
;
3441 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3442 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3444 /* A structure or union. Extract the left justified value,
3445 regardless of the byte order. I.e. DO NOT USE
3449 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3450 offset
< TYPE_LENGTH (type
);
3451 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3453 int xfer
= register_size (current_gdbarch
, regnum
);
3454 if (offset
+ xfer
> TYPE_LENGTH (type
))
3455 xfer
= TYPE_LENGTH (type
) - offset
;
3457 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3458 offset
, xfer
, regnum
);
3459 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3460 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3462 return RETURN_VALUE_REGISTER_CONVENTION
;
3467 /* A scalar extract each part but least-significant-byte
3468 justified. o32 thinks registers are 4 byte, regardless of
3469 the ISA. mips_stack_argsize controls this. */
3472 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3473 offset
< TYPE_LENGTH (type
);
3474 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3476 int xfer
= mips_stack_argsize (gdbarch
);
3477 if (offset
+ xfer
> TYPE_LENGTH (type
))
3478 xfer
= TYPE_LENGTH (type
) - offset
;
3480 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3481 offset
, xfer
, regnum
);
3482 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3483 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3485 return RETURN_VALUE_REGISTER_CONVENTION
;
3489 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3493 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3494 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3496 struct value
**args
, CORE_ADDR sp
,
3497 int struct_return
, CORE_ADDR struct_addr
)
3503 int stack_offset
= 0;
3504 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3505 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3507 /* For shared libraries, "t9" needs to point at the function
3509 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3511 /* Set the return address register to point to the entry point of
3512 the program, where a breakpoint lies in wait. */
3513 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3515 /* First ensure that the stack and structure return address (if any)
3516 are properly aligned. The stack has to be at least 64-bit
3517 aligned even on 32-bit machines, because doubles must be 64-bit
3518 aligned. For n32 and n64, stack frames need to be 128-bit
3519 aligned, so we round to this widest known alignment. */
3521 sp
= align_down (sp
, 16);
3522 struct_addr
= align_down (struct_addr
, 16);
3524 /* Now make space on the stack for the args. */
3525 for (argnum
= 0; argnum
< nargs
; argnum
++)
3526 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
3527 mips_stack_argsize (gdbarch
));
3528 sp
-= align_up (len
, 16);
3531 fprintf_unfiltered (gdb_stdlog
,
3532 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3533 paddr_nz (sp
), (long) align_up (len
, 16));
3535 /* Initialize the integer and float register pointers. */
3536 argreg
= MIPS_A0_REGNUM
;
3537 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3539 /* The struct_return pointer occupies the first parameter-passing reg. */
3543 fprintf_unfiltered (gdb_stdlog
,
3544 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3545 argreg
, paddr_nz (struct_addr
));
3546 write_register (argreg
++, struct_addr
);
3547 stack_offset
+= mips_stack_argsize (gdbarch
);
3550 /* Now load as many as possible of the first arguments into
3551 registers, and push the rest onto the stack. Loop thru args
3552 from first to last. */
3553 for (argnum
= 0; argnum
< nargs
; argnum
++)
3555 const gdb_byte
*val
;
3556 struct value
*arg
= args
[argnum
];
3557 struct type
*arg_type
= check_typedef (value_type (arg
));
3558 int len
= TYPE_LENGTH (arg_type
);
3559 enum type_code typecode
= TYPE_CODE (arg_type
);
3562 fprintf_unfiltered (gdb_stdlog
,
3563 "mips_o64_push_dummy_call: %d len=%d type=%d",
3564 argnum
+ 1, len
, (int) typecode
);
3566 val
= value_contents (arg
);
3568 /* 32-bit ABIs always start floating point arguments in an
3569 even-numbered floating point register. Round the FP register
3570 up before the check to see if there are any FP registers
3571 left. O32/O64 targets also pass the FP in the integer
3572 registers so also round up normal registers. */
3573 if (mips_abi_regsize (gdbarch
) < 8
3574 && fp_register_arg_p (typecode
, arg_type
))
3576 if ((float_argreg
& 1))
3580 /* Floating point arguments passed in registers have to be
3581 treated specially. On 32-bit architectures, doubles
3582 are passed in register pairs; the even register gets
3583 the low word, and the odd register gets the high word.
3584 On O32/O64, the first two floating point arguments are
3585 also copied to general registers, because MIPS16 functions
3586 don't use float registers for arguments. This duplication of
3587 arguments in general registers can't hurt non-MIPS16 functions
3588 because those registers are normally skipped. */
3590 if (fp_register_arg_p (typecode
, arg_type
)
3591 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3593 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3595 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3596 unsigned long regval
;
3598 /* Write the low word of the double to the even register(s). */
3599 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3601 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3602 float_argreg
, phex (regval
, 4));
3603 write_register (float_argreg
++, regval
);
3605 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3606 argreg
, phex (regval
, 4));
3607 write_register (argreg
++, regval
);
3609 /* Write the high word of the double to the odd register(s). */
3610 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3612 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3613 float_argreg
, phex (regval
, 4));
3614 write_register (float_argreg
++, regval
);
3617 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3618 argreg
, phex (regval
, 4));
3619 write_register (argreg
++, regval
);
3623 /* This is a floating point value that fits entirely
3624 in a single register. */
3625 /* On 32 bit ABI's the float_argreg is further adjusted
3626 above to ensure that it is even register aligned. */
3627 LONGEST regval
= extract_unsigned_integer (val
, len
);
3629 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3630 float_argreg
, phex (regval
, len
));
3631 write_register (float_argreg
++, regval
);
3632 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3633 registers for each argument. The below is (my
3634 guess) to ensure that the corresponding integer
3635 register has reserved the same space. */
3637 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3638 argreg
, phex (regval
, len
));
3639 write_register (argreg
, regval
);
3640 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3642 /* Reserve space for the FP register. */
3643 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3647 /* Copy the argument to general registers or the stack in
3648 register-sized pieces. Large arguments are split between
3649 registers and stack. */
3650 /* Note: structs whose size is not a multiple of
3651 mips_abi_regsize() are treated specially: Irix cc passes
3652 them in registers where gcc sometimes puts them on the
3653 stack. For maximum compatibility, we will put them in
3655 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3656 && (len
% mips_abi_regsize (gdbarch
) != 0));
3657 /* Structures should be aligned to eight bytes (even arg registers)
3658 on MIPS_ABI_O32, if their first member has double precision. */
3659 if (mips_abi_regsize (gdbarch
) < 8
3660 && mips_type_needs_double_align (arg_type
))
3665 /* Note: Floating-point values that didn't fit into an FP
3666 register are only written to memory. */
3669 /* Remember if the argument was written to the stack. */
3670 int stack_used_p
= 0;
3671 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3672 ? len
: mips_abi_regsize (gdbarch
));
3675 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3678 /* Write this portion of the argument to the stack. */
3679 if (argreg
> MIPS_LAST_ARG_REGNUM
3681 || fp_register_arg_p (typecode
, arg_type
))
3683 /* Should shorter than int integer values be
3684 promoted to int before being stored? */
3685 int longword_offset
= 0;
3688 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3690 if (mips_stack_argsize (gdbarch
) == 8
3691 && (typecode
== TYPE_CODE_INT
3692 || typecode
== TYPE_CODE_PTR
3693 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3694 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3699 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3700 paddr_nz (stack_offset
));
3701 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3702 paddr_nz (longword_offset
));
3705 addr
= sp
+ stack_offset
+ longword_offset
;
3710 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3712 for (i
= 0; i
< partial_len
; i
++)
3714 fprintf_unfiltered (gdb_stdlog
, "%02x",
3718 write_memory (addr
, val
, partial_len
);
3721 /* Note!!! This is NOT an else clause. Odd sized
3722 structs may go thru BOTH paths. Floating point
3723 arguments will not. */
3724 /* Write this portion of the argument to a general
3725 purpose register. */
3726 if (argreg
<= MIPS_LAST_ARG_REGNUM
3727 && !fp_register_arg_p (typecode
, arg_type
))
3729 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3730 /* Value may need to be sign extended, because
3731 mips_isa_regsize() != mips_abi_regsize(). */
3733 /* A non-floating-point argument being passed in a
3734 general register. If a struct or union, and if
3735 the remaining length is smaller than the register
3736 size, we have to adjust the register value on
3739 It does not seem to be necessary to do the
3740 same for integral types. */
3742 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3743 && partial_len
< mips_abi_regsize (gdbarch
)
3744 && (typecode
== TYPE_CODE_STRUCT
||
3745 typecode
== TYPE_CODE_UNION
))
3746 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3750 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3753 mips_abi_regsize (gdbarch
)));
3754 write_register (argreg
, regval
);
3757 /* Prevent subsequent floating point arguments from
3758 being passed in floating point registers. */
3759 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3765 /* Compute the the offset into the stack at which we
3766 will copy the next parameter.
3768 In older ABIs, the caller reserved space for
3769 registers that contained arguments. This was loosely
3770 refered to as their "home". Consequently, space is
3771 always allocated. */
3773 stack_offset
+= align_up (partial_len
,
3774 mips_stack_argsize (gdbarch
));
3778 fprintf_unfiltered (gdb_stdlog
, "\n");
3781 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3783 /* Return adjusted stack pointer. */
3787 static enum return_value_convention
3788 mips_o64_return_value (struct gdbarch
*gdbarch
,
3789 struct type
*type
, struct regcache
*regcache
,
3790 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3792 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3794 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3795 || TYPE_CODE (type
) == TYPE_CODE_UNION
3796 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3797 return RETURN_VALUE_STRUCT_CONVENTION
;
3798 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3800 /* A floating-point value. It fits in the least significant
3803 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3804 mips_xfer_register (regcache
,
3805 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3807 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3808 return RETURN_VALUE_REGISTER_CONVENTION
;
3812 /* A scalar extract each part but least-significant-byte
3816 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3817 offset
< TYPE_LENGTH (type
);
3818 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3820 int xfer
= mips_stack_argsize (gdbarch
);
3821 if (offset
+ xfer
> TYPE_LENGTH (type
))
3822 xfer
= TYPE_LENGTH (type
) - offset
;
3824 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3825 offset
, xfer
, regnum
);
3826 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3827 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3829 return RETURN_VALUE_REGISTER_CONVENTION
;
3833 /* Floating point register management.
3835 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3836 64bit operations, these early MIPS cpus treat fp register pairs
3837 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3838 registers and offer a compatibility mode that emulates the MIPS2 fp
3839 model. When operating in MIPS2 fp compat mode, later cpu's split
3840 double precision floats into two 32-bit chunks and store them in
3841 consecutive fp regs. To display 64-bit floats stored in this
3842 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3843 Throw in user-configurable endianness and you have a real mess.
3845 The way this works is:
3846 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3847 double-precision value will be split across two logical registers.
3848 The lower-numbered logical register will hold the low-order bits,
3849 regardless of the processor's endianness.
3850 - If we are on a 64-bit processor, and we are looking for a
3851 single-precision value, it will be in the low ordered bits
3852 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3853 save slot in memory.
3854 - If we are in 64-bit mode, everything is straightforward.
3856 Note that this code only deals with "live" registers at the top of the
3857 stack. We will attempt to deal with saved registers later, when
3858 the raw/cooked register interface is in place. (We need a general
3859 interface that can deal with dynamic saved register sizes -- fp
3860 regs could be 32 bits wide in one frame and 64 on the frame above
3863 static struct type
*
3864 mips_float_register_type (void)
3866 return builtin_type_ieee_single
;
3869 static struct type
*
3870 mips_double_register_type (void)
3872 return builtin_type_ieee_double
;
3875 /* Copy a 32-bit single-precision value from the current frame
3876 into rare_buffer. */
3879 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3880 gdb_byte
*rare_buffer
)
3882 int raw_size
= register_size (current_gdbarch
, regno
);
3883 gdb_byte
*raw_buffer
= alloca (raw_size
);
3885 if (!frame_register_read (frame
, regno
, raw_buffer
))
3886 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3889 /* We have a 64-bit value for this register. Find the low-order
3893 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3898 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3902 memcpy (rare_buffer
, raw_buffer
, 4);
3906 /* Copy a 64-bit double-precision value from the current frame into
3907 rare_buffer. This may include getting half of it from the next
3911 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3912 gdb_byte
*rare_buffer
)
3914 int raw_size
= register_size (current_gdbarch
, regno
);
3916 if (raw_size
== 8 && !mips2_fp_compat ())
3918 /* We have a 64-bit value for this register, and we should use
3920 if (!frame_register_read (frame
, regno
, rare_buffer
))
3921 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3925 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3926 internal_error (__FILE__
, __LINE__
,
3927 _("mips_read_fp_register_double: bad access to "
3928 "odd-numbered FP register"));
3930 /* mips_read_fp_register_single will find the correct 32 bits from
3932 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3934 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3935 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3939 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3940 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3946 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3948 { /* do values for FP (float) regs */
3949 gdb_byte
*raw_buffer
;
3950 double doub
, flt1
; /* doubles extracted from raw hex data */
3953 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3954 mips_regnum (current_gdbarch
)->fp0
));
3956 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3957 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3960 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3962 /* 4-byte registers: Print hex and floating. Also print even
3963 numbered registers as doubles. */
3964 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3965 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3967 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3970 fprintf_filtered (file
, " flt: ");
3972 fprintf_filtered (file
, " <invalid float> ");
3974 fprintf_filtered (file
, "%-17.9g", flt1
);
3976 if (regnum
% 2 == 0)
3978 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3979 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3982 fprintf_filtered (file
, " dbl: ");
3984 fprintf_filtered (file
, "<invalid double>");
3986 fprintf_filtered (file
, "%-24.17g", doub
);
3991 /* Eight byte registers: print each one as hex, float and double. */
3992 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3993 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3995 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3996 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3999 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4002 fprintf_filtered (file
, " flt: ");
4004 fprintf_filtered (file
, "<invalid float>");
4006 fprintf_filtered (file
, "%-17.9g", flt1
);
4008 fprintf_filtered (file
, " dbl: ");
4010 fprintf_filtered (file
, "<invalid double>");
4012 fprintf_filtered (file
, "%-24.17g", doub
);
4017 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4018 int regnum
, int all
)
4020 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4021 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4024 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4026 mips_print_fp_register (file
, frame
, regnum
);
4030 /* Get the data in raw format. */
4031 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4033 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4037 fputs_filtered (REGISTER_NAME (regnum
), file
);
4039 /* The problem with printing numeric register names (r26, etc.) is that
4040 the user can't use them on input. Probably the best solution is to
4041 fix it so that either the numeric or the funky (a2, etc.) names
4042 are accepted on input. */
4043 if (regnum
< MIPS_NUMREGS
)
4044 fprintf_filtered (file
, "(r%d): ", regnum
);
4046 fprintf_filtered (file
, ": ");
4048 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4050 register_size (current_gdbarch
,
4051 regnum
) - register_size (current_gdbarch
, regnum
);
4055 print_scalar_formatted (raw_buffer
+ offset
,
4056 register_type (gdbarch
, regnum
), 'x', 0,
4060 /* Replacement for generic do_registers_info.
4061 Print regs in pretty columns. */
4064 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4067 fprintf_filtered (file
, " ");
4068 mips_print_fp_register (file
, frame
, regnum
);
4069 fprintf_filtered (file
, "\n");
4074 /* Print a row's worth of GP (int) registers, with name labels above */
4077 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4080 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4081 /* do values for GP (int) regs */
4082 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4083 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4087 /* For GP registers, we print a separate row of names above the vals */
4088 for (col
= 0, regnum
= start_regnum
;
4089 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4091 if (*REGISTER_NAME (regnum
) == '\0')
4092 continue; /* unused register */
4093 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4095 break; /* end the row: reached FP register */
4097 fprintf_filtered (file
, " ");
4098 fprintf_filtered (file
,
4099 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4100 REGISTER_NAME (regnum
));
4107 /* print the R0 to R31 names */
4108 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4109 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4111 fprintf_filtered (file
, "\n ");
4113 /* now print the values in hex, 4 or 8 to the row */
4114 for (col
= 0, regnum
= start_regnum
;
4115 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4117 if (*REGISTER_NAME (regnum
) == '\0')
4118 continue; /* unused register */
4119 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4121 break; /* end row: reached FP register */
4122 /* OK: get the data in raw format. */
4123 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4124 error (_("can't read register %d (%s)"), regnum
, REGISTER_NAME (regnum
));
4125 /* pad small registers */
4127 byte
< (mips_abi_regsize (current_gdbarch
)
4128 - register_size (current_gdbarch
, regnum
)); byte
++)
4129 printf_filtered (" ");
4130 /* Now print the register value in hex, endian order. */
4131 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4133 register_size (current_gdbarch
,
4134 regnum
) - register_size (current_gdbarch
, regnum
);
4135 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4136 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4138 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4140 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4141 fprintf_filtered (file
, " ");
4144 if (col
> 0) /* ie. if we actually printed anything... */
4145 fprintf_filtered (file
, "\n");
4150 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4153 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4154 struct frame_info
*frame
, int regnum
, int all
)
4156 if (regnum
!= -1) /* do one specified register */
4158 gdb_assert (regnum
>= NUM_REGS
);
4159 if (*(REGISTER_NAME (regnum
)) == '\0')
4160 error (_("Not a valid register for the current processor type"));
4162 mips_print_register (file
, frame
, regnum
, 0);
4163 fprintf_filtered (file
, "\n");
4166 /* do all (or most) registers */
4169 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4171 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4174 if (all
) /* true for "INFO ALL-REGISTERS" command */
4175 regnum
= print_fp_register_row (file
, frame
, regnum
);
4177 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4180 regnum
= print_gp_register_row (file
, frame
, regnum
);
4185 /* Is this a branch with a delay slot? */
4188 is_delayed (unsigned long insn
)
4191 for (i
= 0; i
< NUMOPCODES
; ++i
)
4192 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4193 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4195 return (i
< NUMOPCODES
4196 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4197 | INSN_COND_BRANCH_DELAY
4198 | INSN_COND_BRANCH_LIKELY
)));
4202 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4203 struct frame_info
*frame
)
4205 CORE_ADDR pc
= get_frame_pc (frame
);
4206 gdb_byte buf
[MIPS_INSN32_SIZE
];
4208 /* There is no branch delay slot on MIPS16. */
4209 if (mips_pc_is_mips16 (pc
))
4212 if (!breakpoint_here_p (pc
+ 4))
4215 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4216 /* If error reading memory, guess that it is not a delayed
4219 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4222 /* To skip prologues, I use this predicate. Returns either PC itself
4223 if the code at PC does not look like a function prologue; otherwise
4224 returns an address that (if we're lucky) follows the prologue. If
4225 LENIENT, then we must skip everything which is involved in setting
4226 up the frame (it's OK to skip more, just so long as we don't skip
4227 anything which might clobber the registers which are being saved.
4228 We must skip more in the case where part of the prologue is in the
4229 delay slot of a non-prologue instruction). */
4232 mips_skip_prologue (CORE_ADDR pc
)
4235 CORE_ADDR func_addr
;
4237 /* See if we can determine the end of the prologue via the symbol table.
4238 If so, then return either PC, or the PC after the prologue, whichever
4240 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4242 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4243 if (post_prologue_pc
!= 0)
4244 return max (pc
, post_prologue_pc
);
4247 /* Can't determine prologue from the symbol table, need to examine
4250 /* Find an upper limit on the function prologue using the debug
4251 information. If the debug information could not be used to provide
4252 that bound, then use an arbitrary large number as the upper bound. */
4253 limit_pc
= skip_prologue_using_sal (pc
);
4255 limit_pc
= pc
+ 100; /* Magic. */
4257 if (mips_pc_is_mips16 (pc
))
4258 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4260 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4263 /* Root of all "set mips "/"show mips " commands. This will eventually be
4264 used for all MIPS-specific commands. */
4267 show_mips_command (char *args
, int from_tty
)
4269 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4273 set_mips_command (char *args
, int from_tty
)
4276 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4277 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4280 /* Commands to show/set the MIPS FPU type. */
4283 show_mipsfpu_command (char *args
, int from_tty
)
4286 switch (MIPS_FPU_TYPE
)
4288 case MIPS_FPU_SINGLE
:
4289 fpu
= "single-precision";
4291 case MIPS_FPU_DOUBLE
:
4292 fpu
= "double-precision";
4295 fpu
= "absent (none)";
4298 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4300 if (mips_fpu_type_auto
)
4302 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4306 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4311 set_mipsfpu_command (char *args
, int from_tty
)
4314 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4315 show_mipsfpu_command (args
, from_tty
);
4319 set_mipsfpu_single_command (char *args
, int from_tty
)
4321 struct gdbarch_info info
;
4322 gdbarch_info_init (&info
);
4323 mips_fpu_type
= MIPS_FPU_SINGLE
;
4324 mips_fpu_type_auto
= 0;
4325 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4326 instead of relying on globals. Doing that would let generic code
4327 handle the search for this specific architecture. */
4328 if (!gdbarch_update_p (info
))
4329 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4333 set_mipsfpu_double_command (char *args
, int from_tty
)
4335 struct gdbarch_info info
;
4336 gdbarch_info_init (&info
);
4337 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4338 mips_fpu_type_auto
= 0;
4339 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4340 instead of relying on globals. Doing that would let generic code
4341 handle the search for this specific architecture. */
4342 if (!gdbarch_update_p (info
))
4343 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4347 set_mipsfpu_none_command (char *args
, int from_tty
)
4349 struct gdbarch_info info
;
4350 gdbarch_info_init (&info
);
4351 mips_fpu_type
= MIPS_FPU_NONE
;
4352 mips_fpu_type_auto
= 0;
4353 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4354 instead of relying on globals. Doing that would let generic code
4355 handle the search for this specific architecture. */
4356 if (!gdbarch_update_p (info
))
4357 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4361 set_mipsfpu_auto_command (char *args
, int from_tty
)
4363 mips_fpu_type_auto
= 1;
4366 /* Attempt to identify the particular processor model by reading the
4367 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4368 the relevant processor still exists (it dates back to '94) and
4369 secondly this is not the way to do this. The processor type should
4370 be set by forcing an architecture change. */
4373 deprecated_mips_set_processor_regs_hack (void)
4375 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4378 prid
= read_register (MIPS_PRID_REGNUM
);
4380 if ((prid
& ~0xf) == 0x700)
4381 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4384 /* Just like reinit_frame_cache, but with the right arguments to be
4385 callable as an sfunc. */
4388 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4389 struct cmd_list_element
*c
)
4391 reinit_frame_cache ();
4395 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4399 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4400 disassembler needs to be able to locally determine the ISA, and
4401 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4403 if (mips_pc_is_mips16 (memaddr
))
4404 info
->mach
= bfd_mach_mips16
;
4406 /* Round down the instruction address to the appropriate boundary. */
4407 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4409 /* Set the disassembler options. */
4410 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4412 /* Set up the disassembler info, so that we get the right
4413 register names from libopcodes. */
4414 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4415 info
->disassembler_options
= "gpr-names=n32";
4417 info
->disassembler_options
= "gpr-names=64";
4418 info
->flavour
= bfd_target_elf_flavour
;
4421 /* This string is not recognized explicitly by the disassembler,
4422 but it tells the disassembler to not try to guess the ABI from
4423 the bfd elf headers, such that, if the user overrides the ABI
4424 of a program linked as NewABI, the disassembly will follow the
4425 register naming conventions specified by the user. */
4426 info
->disassembler_options
= "gpr-names=32";
4428 /* Call the appropriate disassembler based on the target endian-ness. */
4429 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4430 return print_insn_big_mips (memaddr
, info
);
4432 return print_insn_little_mips (memaddr
, info
);
4435 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4436 counter value to determine whether a 16- or 32-bit breakpoint should be
4437 used. It returns a pointer to a string of bytes that encode a breakpoint
4438 instruction, stores the length of the string to *lenptr, and adjusts pc
4439 (if necessary) to point to the actual memory location where the
4440 breakpoint should be inserted. */
4442 static const gdb_byte
*
4443 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4445 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4447 if (mips_pc_is_mips16 (*pcptr
))
4449 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4450 *pcptr
= unmake_mips16_addr (*pcptr
);
4451 *lenptr
= sizeof (mips16_big_breakpoint
);
4452 return mips16_big_breakpoint
;
4456 /* The IDT board uses an unusual breakpoint value, and
4457 sometimes gets confused when it sees the usual MIPS
4458 breakpoint instruction. */
4459 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4460 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4461 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4463 *lenptr
= sizeof (big_breakpoint
);
4465 if (strcmp (target_shortname
, "mips") == 0)
4466 return idt_big_breakpoint
;
4467 else if (strcmp (target_shortname
, "ddb") == 0
4468 || strcmp (target_shortname
, "pmon") == 0
4469 || strcmp (target_shortname
, "lsi") == 0)
4470 return pmon_big_breakpoint
;
4472 return big_breakpoint
;
4477 if (mips_pc_is_mips16 (*pcptr
))
4479 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4480 *pcptr
= unmake_mips16_addr (*pcptr
);
4481 *lenptr
= sizeof (mips16_little_breakpoint
);
4482 return mips16_little_breakpoint
;
4486 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4487 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4488 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4490 *lenptr
= sizeof (little_breakpoint
);
4492 if (strcmp (target_shortname
, "mips") == 0)
4493 return idt_little_breakpoint
;
4494 else if (strcmp (target_shortname
, "ddb") == 0
4495 || strcmp (target_shortname
, "pmon") == 0
4496 || strcmp (target_shortname
, "lsi") == 0)
4497 return pmon_little_breakpoint
;
4499 return little_breakpoint
;
4504 /* If PC is in a mips16 call or return stub, return the address of the target
4505 PC, which is either the callee or the caller. There are several
4506 cases which must be handled:
4508 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4509 target PC is in $31 ($ra).
4510 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4511 and the target PC is in $2.
4512 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4513 before the jal instruction, this is effectively a call stub
4514 and the the target PC is in $2. Otherwise this is effectively
4515 a return stub and the target PC is in $18.
4517 See the source code for the stubs in gcc/config/mips/mips16.S for
4521 mips_skip_trampoline_code (CORE_ADDR pc
)
4524 CORE_ADDR start_addr
;
4526 /* Find the starting address and name of the function containing the PC. */
4527 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4530 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4531 target PC is in $31 ($ra). */
4532 if (strcmp (name
, "__mips16_ret_sf") == 0
4533 || strcmp (name
, "__mips16_ret_df") == 0)
4534 return read_signed_register (MIPS_RA_REGNUM
);
4536 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4538 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4539 and the target PC is in $2. */
4540 if (name
[19] >= '0' && name
[19] <= '9')
4541 return read_signed_register (2);
4543 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4544 before the jal instruction, this is effectively a call stub
4545 and the the target PC is in $2. Otherwise this is effectively
4546 a return stub and the target PC is in $18. */
4547 else if (name
[19] == 's' || name
[19] == 'd')
4549 if (pc
== start_addr
)
4551 /* Check if the target of the stub is a compiler-generated
4552 stub. Such a stub for a function bar might have a name
4553 like __fn_stub_bar, and might look like this:
4558 la $1,bar (becomes a lui/addiu pair)
4560 So scan down to the lui/addi and extract the target
4561 address from those two instructions. */
4563 CORE_ADDR target_pc
= read_signed_register (2);
4567 /* See if the name of the target function is __fn_stub_*. */
4568 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4571 if (strncmp (name
, "__fn_stub_", 10) != 0
4572 && strcmp (name
, "etext") != 0
4573 && strcmp (name
, "_etext") != 0)
4576 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4577 The limit on the search is arbitrarily set to 20
4578 instructions. FIXME. */
4579 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4581 inst
= mips_fetch_instruction (target_pc
);
4582 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4583 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4584 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4585 return pc
| (inst
& 0xffff); /* low word */
4588 /* Couldn't find the lui/addui pair, so return stub address. */
4592 /* This is the 'return' part of a call stub. The return
4593 address is in $r18. */
4594 return read_signed_register (18);
4597 return 0; /* not a stub */
4600 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4601 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4604 mips_stab_reg_to_regnum (int num
)
4607 if (num
>= 0 && num
< 32)
4609 else if (num
>= 38 && num
< 70)
4610 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4612 regnum
= mips_regnum (current_gdbarch
)->hi
;
4614 regnum
= mips_regnum (current_gdbarch
)->lo
;
4616 /* This will hopefully (eventually) provoke a warning. Should
4617 we be calling complaint() here? */
4618 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4619 return NUM_REGS
+ regnum
;
4623 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4624 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4627 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4630 if (num
>= 0 && num
< 32)
4632 else if (num
>= 32 && num
< 64)
4633 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4635 regnum
= mips_regnum (current_gdbarch
)->hi
;
4637 regnum
= mips_regnum (current_gdbarch
)->lo
;
4639 /* This will hopefully (eventually) provoke a warning. Should we
4640 be calling complaint() here? */
4641 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4642 return NUM_REGS
+ regnum
;
4646 mips_register_sim_regno (int regnum
)
4648 /* Only makes sense to supply raw registers. */
4649 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4650 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4651 decide if it is valid. Should instead define a standard sim/gdb
4652 register numbering scheme. */
4653 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4654 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4657 return LEGACY_SIM_REGNO_IGNORE
;
4661 /* Convert an integer into an address. Extracting the value signed
4662 guarantees a correctly sign extended address. */
4665 mips_integer_to_address (struct gdbarch
*gdbarch
,
4666 struct type
*type
, const gdb_byte
*buf
)
4668 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4672 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4674 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4675 const char *name
= bfd_get_section_name (abfd
, sect
);
4677 if (*abip
!= MIPS_ABI_UNKNOWN
)
4680 if (strncmp (name
, ".mdebug.", 8) != 0)
4683 if (strcmp (name
, ".mdebug.abi32") == 0)
4684 *abip
= MIPS_ABI_O32
;
4685 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4686 *abip
= MIPS_ABI_N32
;
4687 else if (strcmp (name
, ".mdebug.abi64") == 0)
4688 *abip
= MIPS_ABI_N64
;
4689 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4690 *abip
= MIPS_ABI_O64
;
4691 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4692 *abip
= MIPS_ABI_EABI32
;
4693 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4694 *abip
= MIPS_ABI_EABI64
;
4696 warning (_("unsupported ABI %s."), name
+ 8);
4700 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4702 int *lbp
= (int *) obj
;
4703 const char *name
= bfd_get_section_name (abfd
, sect
);
4705 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4707 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4709 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4710 warning (_("unrecognized .gcc_compiled_longXX"));
4713 static enum mips_abi
4714 global_mips_abi (void)
4718 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4719 if (mips_abi_strings
[i
] == mips_abi_string
)
4720 return (enum mips_abi
) i
;
4722 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4726 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4728 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4730 if (tdesc_gp32
== NULL
)
4732 /* Create feature sets with the appropriate properties. The values
4733 are not important. */
4735 tdesc_gp32
= allocate_target_description ();
4736 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4738 tdesc_gp64
= allocate_target_description ();
4739 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4742 /* If the size matches the set of 32-bit or 64-bit integer registers,
4743 assume that's what we've got. */
4744 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4745 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4747 /* If the size matches the full set of registers GDB traditionally
4748 knows about, including floating point, for either 32-bit or
4749 64-bit, assume that's what we've got. */
4750 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4751 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4753 /* Otherwise we don't have a useful guess. */
4756 static struct gdbarch
*
4757 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4759 struct gdbarch
*gdbarch
;
4760 struct gdbarch_tdep
*tdep
;
4762 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4764 enum mips_fpu_type fpu_type
;
4766 /* First of all, extract the elf_flags, if available. */
4767 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4768 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4769 else if (arches
!= NULL
)
4770 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4774 fprintf_unfiltered (gdb_stdlog
,
4775 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4777 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4778 switch ((elf_flags
& EF_MIPS_ABI
))
4780 case E_MIPS_ABI_O32
:
4781 found_abi
= MIPS_ABI_O32
;
4783 case E_MIPS_ABI_O64
:
4784 found_abi
= MIPS_ABI_O64
;
4786 case E_MIPS_ABI_EABI32
:
4787 found_abi
= MIPS_ABI_EABI32
;
4789 case E_MIPS_ABI_EABI64
:
4790 found_abi
= MIPS_ABI_EABI64
;
4793 if ((elf_flags
& EF_MIPS_ABI2
))
4794 found_abi
= MIPS_ABI_N32
;
4796 found_abi
= MIPS_ABI_UNKNOWN
;
4800 /* GCC creates a pseudo-section whose name describes the ABI. */
4801 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4802 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4804 /* If we have no useful BFD information, use the ABI from the last
4805 MIPS architecture (if there is one). */
4806 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4807 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4809 /* Try the architecture for any hint of the correct ABI. */
4810 if (found_abi
== MIPS_ABI_UNKNOWN
4811 && info
.bfd_arch_info
!= NULL
4812 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4814 switch (info
.bfd_arch_info
->mach
)
4816 case bfd_mach_mips3900
:
4817 found_abi
= MIPS_ABI_EABI32
;
4819 case bfd_mach_mips4100
:
4820 case bfd_mach_mips5000
:
4821 found_abi
= MIPS_ABI_EABI64
;
4823 case bfd_mach_mips8000
:
4824 case bfd_mach_mips10000
:
4825 /* On Irix, ELF64 executables use the N64 ABI. The
4826 pseudo-sections which describe the ABI aren't present
4827 on IRIX. (Even for executables created by gcc.) */
4828 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4829 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4830 found_abi
= MIPS_ABI_N64
;
4832 found_abi
= MIPS_ABI_N32
;
4837 /* Default 64-bit objects to N64 instead of O32. */
4838 if (found_abi
== MIPS_ABI_UNKNOWN
4839 && info
.abfd
!= NULL
4840 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4841 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4842 found_abi
= MIPS_ABI_N64
;
4845 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4848 /* What has the user specified from the command line? */
4849 wanted_abi
= global_mips_abi ();
4851 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4854 /* Now that we have found what the ABI for this binary would be,
4855 check whether the user is overriding it. */
4856 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4857 mips_abi
= wanted_abi
;
4858 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4859 mips_abi
= found_abi
;
4861 mips_abi
= MIPS_ABI_O32
;
4863 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4866 /* Also used when doing an architecture lookup. */
4868 fprintf_unfiltered (gdb_stdlog
,
4869 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4870 mips64_transfers_32bit_regs_p
);
4872 /* Determine the MIPS FPU type. */
4873 if (!mips_fpu_type_auto
)
4874 fpu_type
= mips_fpu_type
;
4875 else if (info
.bfd_arch_info
!= NULL
4876 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4877 switch (info
.bfd_arch_info
->mach
)
4879 case bfd_mach_mips3900
:
4880 case bfd_mach_mips4100
:
4881 case bfd_mach_mips4111
:
4882 case bfd_mach_mips4120
:
4883 fpu_type
= MIPS_FPU_NONE
;
4885 case bfd_mach_mips4650
:
4886 fpu_type
= MIPS_FPU_SINGLE
;
4889 fpu_type
= MIPS_FPU_DOUBLE
;
4892 else if (arches
!= NULL
)
4893 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4895 fpu_type
= MIPS_FPU_DOUBLE
;
4897 fprintf_unfiltered (gdb_stdlog
,
4898 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4900 /* Check for blatant incompatibilities. */
4902 /* If we have only 32-bit registers, then we can't debug a 64-bit
4904 if (info
.target_desc
4905 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4906 && mips_abi
!= MIPS_ABI_EABI32
4907 && mips_abi
!= MIPS_ABI_O32
)
4910 /* try to find a pre-existing architecture */
4911 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4913 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4915 /* MIPS needs to be pedantic about which ABI the object is
4917 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4919 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4921 /* Need to be pedantic about which register virtual size is
4923 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4924 != mips64_transfers_32bit_regs_p
)
4926 /* Be pedantic about which FPU is selected. */
4927 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4929 return arches
->gdbarch
;
4932 /* Need a new architecture. Fill in a target specific vector. */
4933 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4934 gdbarch
= gdbarch_alloc (&info
, tdep
);
4935 tdep
->elf_flags
= elf_flags
;
4936 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4937 tdep
->found_abi
= found_abi
;
4938 tdep
->mips_abi
= mips_abi
;
4939 tdep
->mips_fpu_type
= fpu_type
;
4940 tdep
->register_size_valid_p
= 0;
4941 tdep
->register_size
= 0;
4943 if (info
.target_desc
)
4945 /* Some useful properties can be inferred from the target. */
4946 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4948 tdep
->register_size_valid_p
= 1;
4949 tdep
->register_size
= 4;
4951 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4953 tdep
->register_size_valid_p
= 1;
4954 tdep
->register_size
= 8;
4958 /* Initially set everything according to the default ABI/ISA. */
4959 set_gdbarch_short_bit (gdbarch
, 16);
4960 set_gdbarch_int_bit (gdbarch
, 32);
4961 set_gdbarch_float_bit (gdbarch
, 32);
4962 set_gdbarch_double_bit (gdbarch
, 64);
4963 set_gdbarch_long_double_bit (gdbarch
, 64);
4964 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4965 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4966 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4968 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4969 mips_elf_make_msymbol_special
);
4971 /* Fill in the OS dependant register numbers and names. */
4973 const char **reg_names
;
4974 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4975 struct mips_regnum
);
4976 if (info
.osabi
== GDB_OSABI_IRIX
)
4981 regnum
->badvaddr
= 66;
4984 regnum
->fp_control_status
= 69;
4985 regnum
->fp_implementation_revision
= 70;
4987 reg_names
= mips_irix_reg_names
;
4991 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4992 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4993 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4994 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4995 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4996 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4997 regnum
->fp_control_status
= 70;
4998 regnum
->fp_implementation_revision
= 71;
5000 if (info
.bfd_arch_info
!= NULL
5001 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5002 reg_names
= mips_tx39_reg_names
;
5004 reg_names
= mips_generic_reg_names
;
5006 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5007 replaced by read_pc? */
5008 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5009 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5010 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5011 set_gdbarch_num_regs (gdbarch
, num_regs
);
5012 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5013 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5014 tdep
->mips_processor_reg_names
= reg_names
;
5015 tdep
->regnum
= regnum
;
5021 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5022 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5023 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5024 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5025 tdep
->default_mask_address_p
= 0;
5026 set_gdbarch_long_bit (gdbarch
, 32);
5027 set_gdbarch_ptr_bit (gdbarch
, 32);
5028 set_gdbarch_long_long_bit (gdbarch
, 64);
5031 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5032 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5033 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5034 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5035 tdep
->default_mask_address_p
= 0;
5036 set_gdbarch_long_bit (gdbarch
, 32);
5037 set_gdbarch_ptr_bit (gdbarch
, 32);
5038 set_gdbarch_long_long_bit (gdbarch
, 64);
5040 case MIPS_ABI_EABI32
:
5041 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5042 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5043 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5044 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5045 tdep
->default_mask_address_p
= 0;
5046 set_gdbarch_long_bit (gdbarch
, 32);
5047 set_gdbarch_ptr_bit (gdbarch
, 32);
5048 set_gdbarch_long_long_bit (gdbarch
, 64);
5050 case MIPS_ABI_EABI64
:
5051 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5052 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5053 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5054 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5055 tdep
->default_mask_address_p
= 0;
5056 set_gdbarch_long_bit (gdbarch
, 64);
5057 set_gdbarch_ptr_bit (gdbarch
, 64);
5058 set_gdbarch_long_long_bit (gdbarch
, 64);
5061 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5062 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5063 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5064 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5065 tdep
->default_mask_address_p
= 0;
5066 set_gdbarch_long_bit (gdbarch
, 32);
5067 set_gdbarch_ptr_bit (gdbarch
, 32);
5068 set_gdbarch_long_long_bit (gdbarch
, 64);
5069 set_gdbarch_long_double_bit (gdbarch
, 128);
5070 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5073 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5074 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5075 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5076 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5077 tdep
->default_mask_address_p
= 0;
5078 set_gdbarch_long_bit (gdbarch
, 64);
5079 set_gdbarch_ptr_bit (gdbarch
, 64);
5080 set_gdbarch_long_long_bit (gdbarch
, 64);
5081 set_gdbarch_long_double_bit (gdbarch
, 128);
5082 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5085 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5088 /* GCC creates a pseudo-section whose name specifies the size of
5089 longs, since -mlong32 or -mlong64 may be used independent of
5090 other options. How those options affect pointer sizes is ABI and
5091 architecture dependent, so use them to override the default sizes
5092 set by the ABI. This table shows the relationship between ABI,
5093 -mlongXX, and size of pointers:
5095 ABI -mlongXX ptr bits
5096 --- -------- --------
5110 Note that for o32 and eabi32, pointers are always 32 bits
5111 regardless of any -mlongXX option. For all others, pointers and
5112 longs are the same, as set by -mlongXX or set by defaults.
5115 if (info
.abfd
!= NULL
)
5119 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5122 set_gdbarch_long_bit (gdbarch
, long_bit
);
5126 case MIPS_ABI_EABI32
:
5131 case MIPS_ABI_EABI64
:
5132 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5135 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5140 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5141 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5144 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5145 flag in object files because to do so would make it impossible to
5146 link with libraries compiled without "-gp32". This is
5147 unnecessarily restrictive.
5149 We could solve this problem by adding "-gp32" multilibs to gcc,
5150 but to set this flag before gcc is built with such multilibs will
5151 break too many systems.''
5153 But even more unhelpfully, the default linker output target for
5154 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5155 for 64-bit programs - you need to change the ABI to change this,
5156 and not all gcc targets support that currently. Therefore using
5157 this flag to detect 32-bit mode would do the wrong thing given
5158 the current gcc - it would make GDB treat these 64-bit programs
5159 as 32-bit programs by default. */
5161 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5162 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5163 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5165 /* Add/remove bits from an address. The MIPS needs be careful to
5166 ensure that all 32 bit addresses are sign extended to 64 bits. */
5167 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5169 /* Unwind the frame. */
5170 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5171 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5173 /* Map debug register numbers onto internal register numbers. */
5174 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5175 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5176 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5177 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5178 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5179 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5180 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5181 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5183 /* MIPS version of CALL_DUMMY */
5185 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5186 replaced by a command, and all targets will default to on stack
5187 (regardless of the stack's execute status). */
5188 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5189 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5191 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5192 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5193 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5195 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5196 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5198 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5200 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5201 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5202 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5204 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5206 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5208 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5210 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5211 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5212 need to all be folded into the target vector. Since they are
5213 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5214 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5216 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5218 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5220 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5222 /* Virtual tables. */
5223 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5225 mips_register_g_packet_guesses (gdbarch
);
5227 /* Hook in OS ABI-specific overrides, if they have been registered. */
5228 gdbarch_init_osabi (info
, gdbarch
);
5230 /* Unwind the frame. */
5231 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5232 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5233 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5234 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5235 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5236 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5242 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5244 struct gdbarch_info info
;
5246 /* Force the architecture to update, and (if it's a MIPS architecture)
5247 mips_gdbarch_init will take care of the rest. */
5248 gdbarch_info_init (&info
);
5249 gdbarch_update_p (info
);
5252 /* Print out which MIPS ABI is in use. */
5255 show_mips_abi (struct ui_file
*file
,
5257 struct cmd_list_element
*ignored_cmd
,
5258 const char *ignored_value
)
5260 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5263 "The MIPS ABI is unknown because the current architecture "
5267 enum mips_abi global_abi
= global_mips_abi ();
5268 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5269 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5271 if (global_abi
== MIPS_ABI_UNKNOWN
)
5274 "The MIPS ABI is set automatically (currently \"%s\").\n",
5276 else if (global_abi
== actual_abi
)
5279 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5283 /* Probably shouldn't happen... */
5286 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5287 actual_abi_str
, mips_abi_strings
[global_abi
]);
5293 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5299 int ef_mips_32bitmode
;
5300 /* Determine the ISA. */
5301 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5319 /* Determine the size of a pointer. */
5320 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5321 fprintf_unfiltered (file
,
5322 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5324 fprintf_unfiltered (file
,
5325 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5327 fprintf_unfiltered (file
,
5328 "mips_dump_tdep: ef_mips_arch = %d\n",
5330 fprintf_unfiltered (file
,
5331 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5332 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5333 fprintf_unfiltered (file
,
5334 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5335 mips_mask_address_p (tdep
),
5336 tdep
->default_mask_address_p
);
5338 fprintf_unfiltered (file
,
5339 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5340 MIPS_DEFAULT_FPU_TYPE
,
5341 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5342 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5343 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5345 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5346 fprintf_unfiltered (file
,
5347 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5349 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5350 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5351 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5353 fprintf_unfiltered (file
,
5354 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5355 mips_stack_argsize (current_gdbarch
));
5358 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5361 _initialize_mips_tdep (void)
5363 static struct cmd_list_element
*mipsfpulist
= NULL
;
5364 struct cmd_list_element
*c
;
5366 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5367 if (MIPS_ABI_LAST
+ 1
5368 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5369 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5371 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5373 mips_pdr_data
= register_objfile_data ();
5375 /* Add root prefix command for all "set mips"/"show mips" commands */
5376 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5377 _("Various MIPS specific commands."),
5378 &setmipscmdlist
, "set mips ", 0, &setlist
);
5380 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5381 _("Various MIPS specific commands."),
5382 &showmipscmdlist
, "show mips ", 0, &showlist
);
5384 /* Allow the user to override the saved register size. */
5385 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5386 size_enums
, &mips_abi_regsize_string
, _("\
5387 Set size of general purpose registers saved on the stack."), _("\
5388 Show size of general purpose registers saved on the stack."), _("\
5389 This option can be set to one of:\n\
5390 32 - Force GDB to treat saved GP registers as 32-bit\n\
5391 64 - Force GDB to treat saved GP registers as 64-bit\n\
5392 auto - Allow GDB to use the target's default setting or autodetect the\n\
5393 saved GP register size from information contained in the\n\
5394 executable (default)."),
5396 NULL
, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */
5397 &setmipscmdlist
, &showmipscmdlist
);
5399 /* Allow the user to override the argument stack size. */
5400 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5401 size_enums
, &mips_stack_argsize_string
, _("\
5402 Set the amount of stack space reserved for each argument."), _("\
5403 Show the amount of stack space reserved for each argument."), _("\
5404 This option can be set to one of:\n\
5405 32 - Force GDB to allocate 32-bit chunks per argument\n\
5406 64 - Force GDB to allocate 64-bit chunks per argument\n\
5407 auto - Allow GDB to determine the correct setting from the current\n\
5408 target and executable (default)"),
5410 NULL
, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */
5411 &setmipscmdlist
, &showmipscmdlist
);
5413 /* Allow the user to override the ABI. */
5414 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5415 &mips_abi_string
, _("\
5416 Set the MIPS ABI used by this program."), _("\
5417 Show the MIPS ABI used by this program."), _("\
5418 This option can be set to one of:\n\
5419 auto - the default ABI associated with the current binary\n\
5428 &setmipscmdlist
, &showmipscmdlist
);
5430 /* Let the user turn off floating point and set the fence post for
5431 heuristic_proc_start. */
5433 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5434 _("Set use of MIPS floating-point coprocessor."),
5435 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5436 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5437 _("Select single-precision MIPS floating-point coprocessor."),
5439 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5440 _("Select double-precision MIPS floating-point coprocessor."),
5442 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5443 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5444 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5445 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5446 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5447 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5448 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5449 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5450 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5451 _("Select MIPS floating-point coprocessor automatically."),
5453 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5454 _("Show current use of MIPS floating-point coprocessor target."),
5457 /* We really would like to have both "0" and "unlimited" work, but
5458 command.c doesn't deal with that. So make it a var_zinteger
5459 because the user can always use "999999" or some such for unlimited. */
5460 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5461 &heuristic_fence_post
, _("\
5462 Set the distance searched for the start of a function."), _("\
5463 Show the distance searched for the start of a function."), _("\
5464 If you are debugging a stripped executable, GDB needs to search through the\n\
5465 program for the start of a function. This command sets the distance of the\n\
5466 search. The only need to set it is when debugging a stripped executable."),
5467 reinit_frame_cache_sfunc
,
5468 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5469 &setlist
, &showlist
);
5471 /* Allow the user to control whether the upper bits of 64-bit
5472 addresses should be zeroed. */
5473 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5474 &mask_address_var
, _("\
5475 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5476 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5477 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5478 allow GDB to determine the correct value."),
5479 NULL
, show_mask_address
,
5480 &setmipscmdlist
, &showmipscmdlist
);
5482 /* Allow the user to control the size of 32 bit registers within the
5483 raw remote packet. */
5484 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5485 &mips64_transfers_32bit_regs_p
, _("\
5486 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5488 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5490 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5491 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5492 64 bits for others. Use \"off\" to disable compatibility mode"),
5493 set_mips64_transfers_32bit_regs
,
5494 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5495 &setlist
, &showlist
);
5497 /* Debug this files internals. */
5498 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5500 Set mips debugging."), _("\
5501 Show mips debugging."), _("\
5502 When non-zero, mips specific debugging is enabled."),
5504 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5505 &setdebuglist
, &showdebuglist
);