gdb/riscv-tdep.h

   1 /* Target-dependent header for the RISC-V architecture, for GDB, the
   2    GNU Debugger.
   3
   4    Copyright (C) 2018-2021 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef RISCV_TDEP_H
  22 #define RISCV_TDEP_H
  23
  24 #include "arch/riscv.h"
  25
  26 /* RiscV register numbers.  */
  27 enum
  28 {
  29   RISCV_ZERO_REGNUM = 0,        /* Read-only register, always 0.  */
  30   RISCV_RA_REGNUM = 1,          /* Return Address.  */
  31   RISCV_SP_REGNUM = 2,          /* Stack Pointer.  */
  32   RISCV_GP_REGNUM = 3,          /* Global Pointer.  */
  33   RISCV_TP_REGNUM = 4,          /* Thread Pointer.  */
  34   RISCV_FP_REGNUM = 8,          /* Frame Pointer.  */
  35   RISCV_A0_REGNUM = 10,         /* First argument.  */
  36   RISCV_A1_REGNUM = 11,         /* Second argument.  */
  37   RISCV_A7_REGNUM = 17,         /* Seventh argument.  */
  38   RISCV_PC_REGNUM = 32,         /* Program Counter.  */
  39
  40   RISCV_NUM_INTEGER_REGS = 32,
  41
  42   RISCV_FIRST_FP_REGNUM = 33,   /* First Floating Point Register */
  43   RISCV_FA0_REGNUM = 43,
  44   RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
  45   RISCV_LAST_FP_REGNUM = 64,    /* Last Floating Point Register */
  46
  47   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
  48 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
  49   RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
  50 #include "opcode/riscv-opc.h"
  51 #undef DECLARE_CSR
  52   RISCV_LAST_CSR_REGNUM = 4160,
  53   RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
  54
  55   RISCV_PRIV_REGNUM = 4161,
  56
  57   RISCV_V0_REGNUM,
  58
  59   RISCV_V31_REGNUM = RISCV_V0_REGNUM + 31,
  60
  61   RISCV_LAST_REGNUM = RISCV_V31_REGNUM
  62 };
  63
  64 /* RiscV DWARF register numbers.  */
  65 enum
  66 {
  67   RISCV_DWARF_REGNUM_X0 = 0,
  68   RISCV_DWARF_REGNUM_X31 = 31,
  69   RISCV_DWARF_REGNUM_F0 = 32,
  70   RISCV_DWARF_REGNUM_F31 = 63,
  71   RISCV_DWARF_REGNUM_V0 = 96,
  72   RISCV_DWARF_REGNUM_V31 = 127,
  73   RISCV_DWARF_FIRST_CSR = 4096,
  74   RISCV_DWARF_LAST_CSR = 8191,
  75 };
  76
  77 /* RISC-V specific per-architecture information.  */
  78 struct gdbarch_tdep
  79 {
  80   /* Features about the target hardware that impact how the gdbarch is
  81      configured.  Two gdbarch instances are compatible only if this field
  82      matches.  */
  83   struct riscv_gdbarch_features isa_features;
  84
  85   /* Features about the abi that impact how the gdbarch is configured.  Two
  86      gdbarch instances are compatible only if this field matches.  */
  87   struct riscv_gdbarch_features abi_features;
  88
  89   /* ISA-specific data types.  */
  90   struct type *riscv_fpreg_d_type = nullptr;
  91
  92   /* Use for tracking unknown CSRs in the target description.
  93      UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
  94      CSR.  All other unknown CSRs will be assigned sequential numbers after
  95      this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs.  */
  96   int unknown_csrs_first_regnum = -1;
  97   int unknown_csrs_count = 0;
  98
  99   /* Some targets (QEMU) are reporting three registers twice in the target
 100      description they send.  These three register numbers, when not set to
 101      -1, are for the duplicate copies of these registers.  */
 102   int duplicate_fflags_regnum = -1;
 103   int duplicate_frm_regnum = -1;
 104   int duplicate_fcsr_regnum = -1;
 105
 106   /* Return the expected next PC assuming FRAME is stopped at a syscall
 107      instruction.  */
 108   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 109 };
 110
 111
 112 /* Return the width in bytes  of the general purpose registers for GDBARCH.
 113    Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
 114    RV128.  */
 115 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 116
 117 /* Return the width in bytes of the hardware floating point registers for
 118    GDBARCH.  If this architecture has no floating point registers, then
 119    return 0.  Possible values are 4, 8, or 16 for depending on which of
 120    single, double or quad floating point support is available.  */
 121 extern int riscv_isa_flen (struct gdbarch *gdbarch);
 122
 123 /* Return the width in bytes of the general purpose register abi for
 124    GDBARCH.  This can be equal to, or less than RISCV_ISA_XLEN and reflects
 125    how the binary was compiled rather than the hardware that is available.
 126    It is possible that a binary compiled for RV32 is being run on an RV64
 127    target, in which case the isa xlen is 8-bytes, and the abi xlen is
 128    4-bytes.  This will impact how inferior functions are called.  */
 129 extern int riscv_abi_xlen (struct gdbarch *gdbarch);
 130
 131 /* Return the width in bytes of the floating point register abi for
 132    GDBARCH.  This reflects how the binary was compiled rather than the
 133    hardware that is available.  It is possible that a binary is compiled
 134    for single precision floating point, and then run on a target with
 135    double precision floating point.  A return value of 0 indicates that no
 136    floating point abi is in use (floating point arguments will be passed
 137    in integer registers) other possible return value are 4, 8, or 16 as
 138    with RISCV_ISA_FLEN.  */
 139 extern int riscv_abi_flen (struct gdbarch *gdbarch);
 140
 141 /* Return true if GDBARCH is using the embedded x-regs abi, that is the
 142    target only has 16 x-registers, which includes a reduced number of
 143    argument registers.  */
 144 extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
 145
 146 /* Single step based on where the current instruction will take us.  */
 147 extern std::vector<CORE_ADDR> riscv_software_single_step
 148   (struct regcache *regcache);
 149
 150 /* Supply register REGNUM from the buffer REGS (length LEN) into
 151    REGCACHE.  REGSET describes the layout of the buffer.  If REGNUM is -1
 152    then all registers described by REGSET are supplied.
 153
 154    The register RISCV_ZERO_REGNUM should not be described by REGSET,
 155    however, this register (which always has the value 0) will be supplied
 156    by this function if requested.
 157
 158    The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should
 159    not be described by REGSET, however, these register will be provided if
 160    requested assuming either:
 161    (a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or
 162    (b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS
 163        buffer.
 164
 165    This function can be used as the supply function for either x-regs or
 166    f-regs when loading corefiles, and doesn't care which abi is currently
 167    in use.  */
 168
 169 extern void riscv_supply_regset (const struct regset *regset,
 170                                   struct regcache *regcache, int regnum,
 171                                   const void *regs, size_t len);
 172
 173 /* The names of the RISC-V target description features.  */
 174 extern const char *riscv_feature_name_csr;
 175
 176 #endif /* RISCV_TDEP_H */