1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 static const registry
<inferior
>::key
<ppc_inferior_data
> ppc_inferior_data_key
;
160 /* Get the per-inferior PowerPC data for INF. */
163 get_ppc_per_inferior (inferior
*inf
)
165 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
167 if (per_inf
== nullptr)
168 per_inf
= ppc_inferior_data_key
.emplace (inf
);
173 /* To be used by skip_prologue. */
175 struct rs6000_framedata
177 int offset
; /* total size of frame --- the distance
178 by which we decrement sp to allocate
180 int saved_gpr
; /* smallest # of saved gpr */
181 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
182 int saved_fpr
; /* smallest # of saved fpr */
183 int saved_vr
; /* smallest # of saved vr */
184 int saved_ev
; /* smallest # of saved ev */
185 int alloca_reg
; /* alloca register number (frame ptr) */
186 char frameless
; /* true if frameless functions. */
187 char nosavedpc
; /* true if pc not saved. */
188 char used_bl
; /* true if link register clobbered */
189 int gpr_offset
; /* offset of saved gprs from prev sp */
190 int fpr_offset
; /* offset of saved fprs from prev sp */
191 int vr_offset
; /* offset of saved vrs from prev sp */
192 int ev_offset
; /* offset of saved evs from prev sp */
193 int lr_offset
; /* offset of saved lr */
194 int lr_register
; /* register of saved lr, if trustworthy */
195 int cr_offset
; /* offset of saved cr */
196 int vrsave_offset
; /* offset of saved vrsave register */
200 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
202 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
204 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
205 if (tdep
->ppc_vsr0_regnum
< 0)
208 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
209 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
212 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
214 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
216 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
217 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
220 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
224 /* Return true if REGNO is an SPE register, false otherwise. */
226 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
228 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
230 /* Is it a reference to EV0 -- EV31, and do we have those? */
231 if (IS_SPE_PSEUDOREG (tdep
, regno
))
234 /* Is it a reference to one of the raw upper GPR halves? */
235 if (tdep
->ppc_ev0_upper_regnum
>= 0
236 && tdep
->ppc_ev0_upper_regnum
<= regno
237 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
240 /* Is it a reference to the 64-bit accumulator, and do we have that? */
241 if (tdep
->ppc_acc_regnum
>= 0
242 && tdep
->ppc_acc_regnum
== regno
)
245 /* Is it a reference to the SPE floating-point status and control register,
246 and do we have that? */
247 if (tdep
->ppc_spefscr_regnum
>= 0
248 && tdep
->ppc_spefscr_regnum
== regno
)
255 /* Return non-zero if the architecture described by GDBARCH has
256 floating-point registers (f0 --- f31 and fpscr). */
258 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
260 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
262 return (tdep
->ppc_fp0_regnum
>= 0
263 && tdep
->ppc_fpscr_regnum
>= 0);
266 /* Return non-zero if the architecture described by GDBARCH has
267 Altivec registers (vr0 --- vr31, vrsave and vscr). */
269 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
271 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
273 return (tdep
->ppc_vr0_regnum
>= 0
274 && tdep
->ppc_vrsave_regnum
>= 0);
277 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
280 This is a helper function for init_sim_regno_table, constructing
281 the table mapping GDB register numbers to sim register numbers; we
282 initialize every element in that table to -1 before we start
285 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
287 /* Make sure we don't try to assign any given GDB register a sim
288 register number more than once. */
289 gdb_assert (table
[gdb_regno
] == -1);
290 table
[gdb_regno
] = sim_regno
;
294 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
295 numbers to simulator register numbers, based on the values placed
296 in the ARCH->tdep->ppc_foo_regnum members. */
298 init_sim_regno_table (struct gdbarch
*arch
)
300 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (arch
);
301 int total_regs
= gdbarch_num_regs (arch
);
302 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
304 static const char *const segment_regs
[] = {
305 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
306 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
309 /* Presume that all registers not explicitly mentioned below are
310 unavailable from the sim. */
311 for (i
= 0; i
< total_regs
; i
++)
314 /* General-purpose registers. */
315 for (i
= 0; i
< ppc_num_gprs
; i
++)
316 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
318 /* Floating-point registers. */
319 if (tdep
->ppc_fp0_regnum
>= 0)
320 for (i
= 0; i
< ppc_num_fprs
; i
++)
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_fp0_regnum
+ i
,
323 sim_ppc_f0_regnum
+ i
);
324 if (tdep
->ppc_fpscr_regnum
>= 0)
325 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
327 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
328 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
329 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
331 /* Segment registers. */
332 for (i
= 0; i
< ppc_num_srs
; i
++)
336 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
338 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
341 /* Altivec registers. */
342 if (tdep
->ppc_vr0_regnum
>= 0)
344 for (i
= 0; i
< ppc_num_vrs
; i
++)
345 set_sim_regno (sim_regno
,
346 tdep
->ppc_vr0_regnum
+ i
,
347 sim_ppc_vr0_regnum
+ i
);
349 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
350 we can treat this more like the other cases. */
351 set_sim_regno (sim_regno
,
352 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
353 sim_ppc_vscr_regnum
);
355 /* vsave is a special-purpose register, so the code below handles it. */
357 /* SPE APU (E500) registers. */
358 if (tdep
->ppc_ev0_upper_regnum
>= 0)
359 for (i
= 0; i
< ppc_num_gprs
; i
++)
360 set_sim_regno (sim_regno
,
361 tdep
->ppc_ev0_upper_regnum
+ i
,
362 sim_ppc_rh0_regnum
+ i
);
363 if (tdep
->ppc_acc_regnum
>= 0)
364 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
365 /* spefscr is a special-purpose register, so the code below handles it. */
368 /* Now handle all special-purpose registers. Verify that they
369 haven't mistakenly been assigned numbers by any of the above
371 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
373 const char *spr_name
= sim_spr_register_name (i
);
376 if (spr_name
!= NULL
)
377 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
380 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
384 /* Drop the initialized array into place. */
385 tdep
->sim_regno
= sim_regno
;
389 /* Given a GDB register number REG, return the corresponding SIM
392 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
394 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
397 if (tdep
->sim_regno
== NULL
)
398 init_sim_regno_table (gdbarch
);
400 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
401 sim_regno
= tdep
->sim_regno
[reg
];
406 return LEGACY_SIM_REGNO_IGNORE
;
411 /* Register set support functions. */
413 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
414 Write the register to REGCACHE. */
417 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
418 const gdb_byte
*regs
, size_t offset
, int regsize
)
420 if (regnum
!= -1 && offset
!= -1)
424 struct gdbarch
*gdbarch
= regcache
->arch ();
425 int gdb_regsize
= register_size (gdbarch
, regnum
);
426 if (gdb_regsize
< regsize
427 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
428 offset
+= regsize
- gdb_regsize
;
430 regcache
->raw_supply (regnum
, regs
+ offset
);
434 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
435 in a field REGSIZE wide. Zero pad as necessary. */
438 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
439 gdb_byte
*regs
, size_t offset
, int regsize
)
441 if (regnum
!= -1 && offset
!= -1)
445 struct gdbarch
*gdbarch
= regcache
->arch ();
446 int gdb_regsize
= register_size (gdbarch
, regnum
);
447 if (gdb_regsize
< regsize
)
449 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
451 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
452 offset
+= regsize
- gdb_regsize
;
455 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
456 regsize
- gdb_regsize
);
459 regcache
->raw_collect (regnum
, regs
+ offset
);
464 ppc_greg_offset (struct gdbarch
*gdbarch
,
465 ppc_gdbarch_tdep
*tdep
,
466 const struct ppc_reg_offsets
*offsets
,
470 *regsize
= offsets
->gpr_size
;
471 if (regnum
>= tdep
->ppc_gp0_regnum
472 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
473 return (offsets
->r0_offset
474 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
476 if (regnum
== gdbarch_pc_regnum (gdbarch
))
477 return offsets
->pc_offset
;
479 if (regnum
== tdep
->ppc_ps_regnum
)
480 return offsets
->ps_offset
;
482 if (regnum
== tdep
->ppc_lr_regnum
)
483 return offsets
->lr_offset
;
485 if (regnum
== tdep
->ppc_ctr_regnum
)
486 return offsets
->ctr_offset
;
488 *regsize
= offsets
->xr_size
;
489 if (regnum
== tdep
->ppc_cr_regnum
)
490 return offsets
->cr_offset
;
492 if (regnum
== tdep
->ppc_xer_regnum
)
493 return offsets
->xer_offset
;
495 if (regnum
== tdep
->ppc_mq_regnum
)
496 return offsets
->mq_offset
;
502 ppc_fpreg_offset (ppc_gdbarch_tdep
*tdep
,
503 const struct ppc_reg_offsets
*offsets
,
506 if (regnum
>= tdep
->ppc_fp0_regnum
507 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
508 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
510 if (regnum
== tdep
->ppc_fpscr_regnum
)
511 return offsets
->fpscr_offset
;
516 /* Supply register REGNUM in the general-purpose register set REGSET
517 from the buffer specified by GREGS and LEN to register cache
518 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
521 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
522 int regnum
, const void *gregs
, size_t len
)
524 struct gdbarch
*gdbarch
= regcache
->arch ();
525 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
526 const struct ppc_reg_offsets
*offsets
527 = (const struct ppc_reg_offsets
*) regset
->regmap
;
534 int gpr_size
= offsets
->gpr_size
;
536 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
537 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
538 i
++, offset
+= gpr_size
)
539 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
542 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
543 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
544 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
545 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
546 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
548 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
549 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
550 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
551 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
553 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
554 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
556 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
562 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
563 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
566 /* Supply register REGNUM in the floating-point register set REGSET
567 from the buffer specified by FPREGS and LEN to register cache
568 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
571 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
572 int regnum
, const void *fpregs
, size_t len
)
574 struct gdbarch
*gdbarch
= regcache
->arch ();
575 const struct ppc_reg_offsets
*offsets
;
578 if (!ppc_floating_point_unit_p (gdbarch
))
581 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
582 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
587 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
588 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
590 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
592 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
593 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
594 offsets
->fpscr_size
);
598 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
599 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
600 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
603 /* Collect register REGNUM in the general-purpose register set
604 REGSET from register cache REGCACHE into the buffer specified by
605 GREGS and LEN. If REGNUM is -1, do this for all registers in
609 ppc_collect_gregset (const struct regset
*regset
,
610 const struct regcache
*regcache
,
611 int regnum
, void *gregs
, size_t len
)
613 struct gdbarch
*gdbarch
= regcache
->arch ();
614 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
615 const struct ppc_reg_offsets
*offsets
616 = (const struct ppc_reg_offsets
*) regset
->regmap
;
623 int gpr_size
= offsets
->gpr_size
;
625 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
626 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
627 i
++, offset
+= gpr_size
)
628 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
630 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
631 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
632 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
633 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
634 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
635 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
636 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
637 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
638 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
639 (gdb_byte
*) gregs
, offsets
->cr_offset
,
641 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
642 (gdb_byte
*) gregs
, offsets
->xer_offset
,
644 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
645 (gdb_byte
*) gregs
, offsets
->mq_offset
,
650 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
651 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
654 /* Collect register REGNUM in the floating-point register set
655 REGSET from register cache REGCACHE into the buffer specified by
656 FPREGS and LEN. If REGNUM is -1, do this for all registers in
660 ppc_collect_fpregset (const struct regset
*regset
,
661 const struct regcache
*regcache
,
662 int regnum
, void *fpregs
, size_t len
)
664 struct gdbarch
*gdbarch
= regcache
->arch ();
665 const struct ppc_reg_offsets
*offsets
;
668 if (!ppc_floating_point_unit_p (gdbarch
))
671 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
672 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
677 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
678 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
680 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
682 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
683 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
684 offsets
->fpscr_size
);
688 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
689 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
690 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
694 insn_changes_sp_or_jumps (unsigned long insn
)
696 int opcode
= (insn
>> 26) & 0x03f;
697 int sd
= (insn
>> 21) & 0x01f;
698 int a
= (insn
>> 16) & 0x01f;
699 int subcode
= (insn
>> 1) & 0x3ff;
701 /* Changes the stack pointer. */
703 /* NOTE: There are many ways to change the value of a given register.
704 The ways below are those used when the register is R1, the SP,
705 in a funtion's epilogue. */
707 if (opcode
== 31 && subcode
== 444 && a
== 1)
708 return 1; /* mr R1,Rn */
709 if (opcode
== 14 && sd
== 1)
710 return 1; /* addi R1,Rn,simm */
711 if (opcode
== 58 && sd
== 1)
712 return 1; /* ld R1,ds(Rn) */
714 /* Transfers control. */
720 if (opcode
== 19 && subcode
== 16)
722 if (opcode
== 19 && subcode
== 528)
723 return 1; /* bcctr */
728 /* Return true if we are in the function's epilogue, i.e. after the
729 instruction that destroyed the function's stack frame.
731 1) scan forward from the point of execution:
732 a) If you find an instruction that modifies the stack pointer
733 or transfers control (except a return), execution is not in
735 b) Stop scanning if you find a return instruction or reach the
736 end of the function or reach the hard limit for the size of
738 2) scan backward from the point of execution:
739 a) If you find an instruction that modifies the stack pointer,
740 execution *is* in an epilogue, return.
741 b) Stop scanning if you reach an instruction that transfers
742 control or the beginning of the function or reach the hard
743 limit for the size of an epilogue. */
746 rs6000_in_function_epilogue_frame_p (frame_info_ptr curfrm
,
747 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
749 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
750 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
751 bfd_byte insn_buf
[PPC_INSN_SIZE
];
752 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
755 /* Find the search limits based on function boundaries and hard limit. */
757 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
760 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
761 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
763 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
764 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
766 /* Scan forward until next 'blr'. */
768 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
770 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
771 {insn_buf
, PPC_INSN_SIZE
}))
773 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
774 if (insn
== 0x4e800020)
776 /* Assume a bctr is a tail call unless it points strictly within
778 if (insn
== 0x4e800420)
780 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
781 tdep
->ppc_ctr_regnum
);
782 if (ctr
> func_start
&& ctr
< func_end
)
787 if (insn_changes_sp_or_jumps (insn
))
791 /* Scan backward until adjustment to stack pointer (R1). */
793 for (scan_pc
= pc
- PPC_INSN_SIZE
;
794 scan_pc
>= epilogue_start
;
795 scan_pc
-= PPC_INSN_SIZE
)
797 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
798 {insn_buf
, PPC_INSN_SIZE
}))
800 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
801 if (insn_changes_sp_or_jumps (insn
))
808 /* Implement the stack_frame_destroyed_p gdbarch method. */
811 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
813 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
817 /* Get the ith function argument for the current function. */
819 rs6000_fetch_pointer_argument (frame_info_ptr frame
, int argi
,
822 return get_frame_register_unsigned (frame
, 3 + argi
);
825 /* Sequence of bytes for breakpoint instruction. */
827 constexpr gdb_byte big_breakpoint
[] = { 0x7f, 0xe0, 0x00, 0x08 };
828 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x00, 0xe0, 0x7f };
830 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
833 /* Instruction masks for displaced stepping. */
834 #define OP_MASK 0xfc000000
835 #define BP_MASK 0xFC0007FE
836 #define B_INSN 0x48000000
837 #define BC_INSN 0x40000000
838 #define BXL_INSN 0x4c000000
839 #define BP_INSN 0x7C000008
841 /* Instruction masks used during single-stepping of atomic
843 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
844 #define LWARX_INSTRUCTION 0x7c000028
845 #define LDARX_INSTRUCTION 0x7c0000A8
846 #define LBARX_INSTRUCTION 0x7c000068
847 #define LHARX_INSTRUCTION 0x7c0000e8
848 #define LQARX_INSTRUCTION 0x7c000228
849 #define STORE_CONDITIONAL_MASK 0xfc0007ff
850 #define STWCX_INSTRUCTION 0x7c00012d
851 #define STDCX_INSTRUCTION 0x7c0001ad
852 #define STBCX_INSTRUCTION 0x7c00056d
853 #define STHCX_INSTRUCTION 0x7c0005ad
854 #define STQCX_INSTRUCTION 0x7c00016d
856 /* Instruction masks for single-stepping of addpcis/lnia. */
857 #define ADDPCIS_INSN 0x4c000004
858 #define ADDPCIS_INSN_MASK 0xfc00003e
859 #define ADDPCIS_TARGET_REGISTER 0x03F00000
860 #define ADDPCIS_INSN_REGSHIFT 21
862 #define PNOP_MASK 0xfff3ffff
863 #define PNOP_INSN 0x07000000
864 #define R_MASK 0x00100000
865 #define R_ZERO 0x00000000
867 /* Check if insn is one of the Load And Reserve instructions used for atomic
869 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
870 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
871 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
872 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
873 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
874 /* Check if insn is one of the Store Conditional instructions used for atomic
876 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
877 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
878 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
879 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
880 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
882 typedef buf_displaced_step_copy_insn_closure
883 ppc_displaced_step_copy_insn_closure
;
885 /* We can't displaced step atomic sequences. */
887 static displaced_step_copy_insn_closure_up
888 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
889 CORE_ADDR from
, CORE_ADDR to
,
890 struct regcache
*regs
)
892 size_t len
= gdbarch_max_insn_length (gdbarch
);
893 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
894 (new ppc_displaced_step_copy_insn_closure (len
));
895 gdb_byte
*buf
= closure
->buf
.data ();
896 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 len
= target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY
, NULL
,
901 if ((ssize_t
) len
< PPC_INSN_SIZE
)
902 memory_error (TARGET_XFER_E_IO
, from
);
904 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
906 /* Check for PNOP and for prefixed instructions with R=0. Those
907 instructions are safe to displace. Prefixed instructions with R=1
908 will read/write data to/from locations relative to the current PC.
909 We would not be able to fixup after an instruction has written data
910 into a displaced location, so decline to displace those instructions. */
911 if ((insn
& OP_MASK
) == 1 << 26)
913 if (((insn
& PNOP_MASK
) != PNOP_INSN
)
914 && ((insn
& R_MASK
) != R_ZERO
))
916 displaced_debug_printf ("Not displacing prefixed instruction %08x at %s",
917 insn
, paddress (gdbarch
, from
));
922 /* Non-prefixed instructions.. */
924 /* Set the instruction length to 4 to match the actual instruction
929 /* Assume all atomic sequences start with a Load and Reserve instruction. */
930 if (IS_LOAD_AND_RESERVE_INSN (insn
))
932 displaced_debug_printf ("can't displaced step atomic sequence at %s",
933 paddress (gdbarch
, from
));
938 write_memory (to
, buf
, len
);
940 displaced_debug_printf ("copy %s->%s: %s",
941 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
942 displaced_step_dump_bytes (buf
, len
).c_str ());
944 /* This is a work around for a problem with g++ 4.8. */
945 return displaced_step_copy_insn_closure_up (closure
.release ());
948 /* Fix up the state of registers and memory after having single-stepped
949 a displaced instruction. */
951 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
952 struct displaced_step_copy_insn_closure
*closure_
,
953 CORE_ADDR from
, CORE_ADDR to
,
954 struct regcache
*regs
)
956 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
957 /* Our closure is a copy of the instruction. */
958 ppc_displaced_step_copy_insn_closure
*closure
959 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
960 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
961 PPC_INSN_SIZE
, byte_order
);
963 /* Offset for non PC-relative instructions. */
966 opcode
= insn
& OP_MASK
;
968 /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
969 if ((opcode
) == 1 << 26)
970 offset
= 2 * PPC_INSN_SIZE
;
972 offset
= PPC_INSN_SIZE
;
974 displaced_debug_printf ("(ppc) fixup (%s, %s)",
975 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
977 /* Handle the addpcis/lnia instruction. */
978 if ((insn
& ADDPCIS_INSN_MASK
) == ADDPCIS_INSN
)
980 LONGEST displaced_offset
;
981 ULONGEST current_val
;
982 /* Measure the displacement. */
983 displaced_offset
= from
- to
;
984 /* Identify the target register that was updated by the instruction. */
985 int regnum
= (insn
& ADDPCIS_TARGET_REGISTER
) >> ADDPCIS_INSN_REGSHIFT
;
986 /* Read and update the target value. */
987 regcache_cooked_read_unsigned (regs
, regnum
, ¤t_val
);
988 displaced_debug_printf ("addpcis target regnum %d was %s now %s",
989 regnum
, paddress (gdbarch
, current_val
),
990 paddress (gdbarch
, current_val
991 + displaced_offset
));
992 regcache_cooked_write_unsigned (regs
, regnum
,
993 current_val
+ displaced_offset
);
994 /* point the PC back at the non-displaced instruction. */
995 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
998 /* Handle PC-relative branch instructions. */
999 else if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1001 ULONGEST current_pc
;
1003 /* Read the current PC value after the instruction has been executed
1004 in a displaced location. Calculate the offset to be applied to the
1005 original PC value before the displaced stepping. */
1006 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1008 offset
= current_pc
- to
;
1010 if (opcode
!= BXL_INSN
)
1012 /* Check for AA bit indicating whether this is an absolute
1013 addressing or PC-relative (1: absolute, 0: relative). */
1016 /* PC-relative addressing is being used in the branch. */
1017 displaced_debug_printf ("(ppc) branch instruction: %s",
1018 paddress (gdbarch
, insn
));
1019 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
1020 paddress (gdbarch
, current_pc
),
1021 paddress (gdbarch
, from
+ offset
));
1023 regcache_cooked_write_unsigned (regs
,
1024 gdbarch_pc_regnum (gdbarch
),
1030 /* If we're here, it means we have a branch to LR or CTR. If the
1031 branch was taken, the offset is probably greater than 4 (the next
1032 instruction), so it's safe to assume that an offset of 4 means we
1033 did not take the branch. */
1034 if (offset
== PPC_INSN_SIZE
)
1035 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1036 from
+ PPC_INSN_SIZE
);
1039 /* Check for LK bit indicating whether we should set the link
1040 register to point to the next instruction
1041 (1: Set, 0: Don't set). */
1044 /* Link register needs to be set to the next instruction's PC. */
1045 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
1046 regcache_cooked_write_unsigned (regs
,
1047 tdep
->ppc_lr_regnum
,
1048 from
+ PPC_INSN_SIZE
);
1049 displaced_debug_printf ("(ppc) adjusted LR to %s",
1050 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1054 /* Check for breakpoints in the inferior. If we've found one, place the PC
1055 right at the breakpoint instruction. */
1056 else if ((insn
& BP_MASK
) == BP_INSN
)
1057 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1060 /* Handle any other instructions that do not fit in the categories
1062 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1067 /* Implementation of gdbarch_displaced_step_prepare. */
1069 static displaced_step_prepare_status
1070 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1071 CORE_ADDR
&displaced_pc
)
1073 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1075 if (!per_inferior
->disp_step_buf
.has_value ())
1077 /* Figure out where the displaced step buffer is. */
1078 CORE_ADDR disp_step_buf_addr
1079 = displaced_step_at_entry_point (thread
->inf
->gdbarch
);
1081 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1084 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1087 /* Implementation of gdbarch_displaced_step_finish. */
1089 static displaced_step_finish_status
1090 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1093 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1095 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1097 return per_inferior
->disp_step_buf
->finish (arch
, thread
, sig
);
1100 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1103 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1105 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1107 if (per_inferior
== nullptr
1108 || !per_inferior
->disp_step_buf
.has_value ())
1111 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1114 /* Always use hardware single-stepping to execute the
1115 displaced instruction. */
1117 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1122 /* Checks for an atomic sequence of instructions beginning with a
1123 Load And Reserve instruction and ending with a Store Conditional
1124 instruction. If such a sequence is found, attempt to step through it.
1125 A breakpoint is placed at the end of the sequence. */
1126 std::vector
<CORE_ADDR
>
1127 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1129 struct gdbarch
*gdbarch
= regcache
->arch ();
1130 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1131 CORE_ADDR pc
= regcache_read_pc (regcache
);
1132 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1134 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1135 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1138 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1139 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1140 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1142 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1143 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1146 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1148 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1150 if ((insn
& OP_MASK
) == 1 << 26)
1151 loc
+= 2 * PPC_INSN_SIZE
;
1153 loc
+= PPC_INSN_SIZE
;
1154 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1156 /* Assume that there is at most one conditional branch in the atomic
1157 sequence. If a conditional branch is found, put a breakpoint in
1158 its destination address. */
1159 if ((insn
& OP_MASK
) == BC_INSN
)
1161 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1162 int absolute
= insn
& 2;
1164 if (bc_insn_count
>= 1)
1165 return {}; /* More than one conditional branch found, fallback
1166 to the standard single-step code. */
1169 breaks
[1] = immediate
;
1171 breaks
[1] = loc
+ immediate
;
1177 if (IS_STORE_CONDITIONAL_INSN (insn
))
1181 /* Assume that the atomic sequence ends with a Store Conditional
1183 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1187 loc
+= PPC_INSN_SIZE
;
1189 /* Insert a breakpoint right after the end of the atomic sequence. */
1192 /* Check for duplicated breakpoints. Check also for a breakpoint
1193 placed (branch instruction's destination) anywhere in sequence. */
1195 && (breaks
[1] == breaks
[0]
1196 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1197 last_breakpoint
= 0;
1199 std::vector
<CORE_ADDR
> next_pcs
;
1201 for (index
= 0; index
<= last_breakpoint
; index
++)
1202 next_pcs
.push_back (breaks
[index
]);
1208 #define SIGNED_SHORT(x) \
1209 ((sizeof (short) == 2) \
1210 ? ((int)(short)(x)) \
1211 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1213 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1215 /* Limit the number of skipped non-prologue instructions, as the examining
1216 of the prologue is expensive. */
1217 static int max_skip_non_prologue_insns
= 10;
1219 /* Return nonzero if the given instruction OP can be part of the prologue
1220 of a function and saves a parameter on the stack. FRAMEP should be
1221 set if one of the previous instructions in the function has set the
1225 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1227 /* Move parameters from argument registers to temporary register. */
1228 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1230 /* Rx must be scratch register r0. */
1231 const int rx_regno
= (op
>> 16) & 31;
1232 /* Ry: Only r3 - r10 are used for parameter passing. */
1233 const int ry_regno
= GET_SRC_REG (op
);
1235 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1237 *r0_contains_arg
= 1;
1244 /* Save a General Purpose Register on stack. */
1246 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1247 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1249 /* Rx: Only r3 - r10 are used for parameter passing. */
1250 const int rx_regno
= GET_SRC_REG (op
);
1252 return (rx_regno
>= 3 && rx_regno
<= 10);
1255 /* Save a General Purpose Register on stack via the Frame Pointer. */
1258 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1259 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1260 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1262 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1263 However, the compiler sometimes uses r0 to hold an argument. */
1264 const int rx_regno
= GET_SRC_REG (op
);
1266 return ((rx_regno
>= 3 && rx_regno
<= 10)
1267 || (rx_regno
== 0 && *r0_contains_arg
));
1270 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1272 /* Only f2 - f8 are used for parameter passing. */
1273 const int src_regno
= GET_SRC_REG (op
);
1275 return (src_regno
>= 2 && src_regno
<= 8);
1278 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1280 /* Only f2 - f8 are used for parameter passing. */
1281 const int src_regno
= GET_SRC_REG (op
);
1283 return (src_regno
>= 2 && src_regno
<= 8);
1286 /* Not an insn that saves a parameter on stack. */
1290 /* Assuming that INSN is a "bl" instruction located at PC, return
1291 nonzero if the destination of the branch is a "blrl" instruction.
1293 This sequence is sometimes found in certain function prologues.
1294 It allows the function to load the LR register with a value that
1295 they can use to access PIC data using PC-relative offsets. */
1298 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1305 absolute
= (int) ((insn
>> 1) & 1);
1306 immediate
= ((insn
& ~3) << 6) >> 6;
1310 dest
= pc
+ immediate
;
1312 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1313 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1319 /* Return true if OP is a stw or std instruction with
1320 register operands RS and RA and any immediate offset.
1322 If WITH_UPDATE is true, also return true if OP is
1323 a stwu or stdu instruction with the same operands.
1325 Return false otherwise.
1328 store_insn_p (unsigned long op
, unsigned long rs
,
1329 unsigned long ra
, bool with_update
)
1334 if (/* std RS, SIMM(RA) */
1335 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1336 /* stw RS, SIMM(RA) */
1337 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1342 if (/* stdu RS, SIMM(RA) */
1343 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1344 /* stwu RS, SIMM(RA) */
1345 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1352 /* Masks for decoding a branch-and-link (bl) instruction.
1354 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1355 The former is anded with the opcode in question; if the result of
1356 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1357 question is a ``bl'' instruction.
1359 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1360 the branch displacement. */
1362 #define BL_MASK 0xfc000001
1363 #define BL_INSTRUCTION 0x48000001
1364 #define BL_DISPLACEMENT_MASK 0x03fffffc
1366 static unsigned long
1367 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1369 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1373 /* Fetch the instruction and convert it to an integer. */
1374 if (target_read_memory (pc
, buf
, 4))
1376 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1381 /* GCC generates several well-known sequences of instructions at the begining
1382 of each function prologue when compiling with -fstack-check. If one of
1383 such sequences starts at START_PC, then return the address of the
1384 instruction immediately past this sequence. Otherwise, return START_PC. */
1387 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1389 CORE_ADDR pc
= start_pc
;
1390 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1392 /* First possible sequence: A small number of probes.
1393 stw 0, -<some immediate>(1)
1394 [repeat this instruction any (small) number of times]. */
1396 if ((op
& 0xffff0000) == 0x90010000)
1398 while ((op
& 0xffff0000) == 0x90010000)
1401 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1406 /* Second sequence: A probing loop.
1407 addi 12,1,-<some immediate>
1408 lis 0,-<some immediate>
1409 [possibly ori 0,0,<some immediate>]
1413 addi 12,12,-<some immediate>
1416 [possibly one last probe: stw 0,<some immediate>(12)]. */
1420 /* addi 12,1,-<some immediate> */
1421 if ((op
& 0xffff0000) != 0x39810000)
1424 /* lis 0,-<some immediate> */
1426 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1427 if ((op
& 0xffff0000) != 0x3c000000)
1431 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1432 /* [possibly ori 0,0,<some immediate>] */
1433 if ((op
& 0xffff0000) == 0x60000000)
1436 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1439 if (op
!= 0x7c0c0214)
1444 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1445 if (op
!= 0x7c0c0000)
1450 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1451 if ((op
& 0xff9f0001) != 0x41820000)
1454 /* addi 12,12,-<some immediate> */
1456 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1457 if ((op
& 0xffff0000) != 0x398c0000)
1462 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1463 if (op
!= 0x900c0000)
1468 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1469 if ((op
& 0xfc000001) != 0x48000000)
1472 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1474 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1475 if ((op
& 0xffff0000) == 0x900c0000)
1478 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1481 /* We found a valid stack-check sequence, return the new PC. */
1485 /* Third sequence: No probe; instead, a comparison between the stack size
1486 limit (saved in a run-time global variable) and the current stack
1489 addi 0,1,-<some immediate>
1490 lis 12,__gnat_stack_limit@ha
1491 lwz 12,__gnat_stack_limit@l(12)
1494 or, with a small variant in the case of a bigger stack frame:
1495 addis 0,1,<some immediate>
1496 addic 0,0,-<some immediate>
1497 lis 12,__gnat_stack_limit@ha
1498 lwz 12,__gnat_stack_limit@l(12)
1503 /* addi 0,1,-<some immediate> */
1504 if ((op
& 0xffff0000) != 0x38010000)
1506 /* small stack frame variant not recognized; try the
1507 big stack frame variant: */
1509 /* addis 0,1,<some immediate> */
1510 if ((op
& 0xffff0000) != 0x3c010000)
1513 /* addic 0,0,-<some immediate> */
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xffff0000) != 0x30000000)
1520 /* lis 12,<some immediate> */
1522 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1523 if ((op
& 0xffff0000) != 0x3d800000)
1526 /* lwz 12,<some immediate>(12) */
1528 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1529 if ((op
& 0xffff0000) != 0x818c0000)
1534 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1535 if ((op
& 0xfffffffe) != 0x7c406008)
1538 /* We found a valid stack-check sequence, return the new PC. */
1542 /* No stack check code in our prologue, return the start_pc. */
1546 /* return pc value after skipping a function prologue and also return
1547 information about a function frame.
1549 in struct rs6000_framedata fdata:
1550 - frameless is TRUE, if function does not have a frame.
1551 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1552 - offset is the initial size of this stack frame --- the amount by
1553 which we decrement the sp to allocate the frame.
1554 - saved_gpr is the number of the first saved gpr.
1555 - saved_fpr is the number of the first saved fpr.
1556 - saved_vr is the number of the first saved vr.
1557 - saved_ev is the number of the first saved ev.
1558 - alloca_reg is the number of the register used for alloca() handling.
1560 - gpr_offset is the offset of the first saved gpr from the previous frame.
1561 - fpr_offset is the offset of the first saved fpr from the previous frame.
1562 - vr_offset is the offset of the first saved vr from the previous frame.
1563 - ev_offset is the offset of the first saved ev from the previous frame.
1564 - lr_offset is the offset of the saved lr
1565 - cr_offset is the offset of the saved cr
1566 - vrsave_offset is the offset of the saved vrsave register. */
1569 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1570 struct rs6000_framedata
*fdata
)
1572 CORE_ADDR orig_pc
= pc
;
1573 CORE_ADDR last_prologue_pc
= pc
;
1574 CORE_ADDR li_found_pc
= 0;
1578 long alloca_reg_offset
= 0;
1579 long vr_saved_offset
= 0;
1585 int vrsave_reg
= -1;
1588 int minimal_toc_loaded
= 0;
1589 int prev_insn_was_prologue_insn
= 1;
1590 int num_skip_non_prologue_insns
= 0;
1591 int r0_contains_arg
= 0;
1592 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1593 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
1594 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1596 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1597 fdata
->saved_gpr
= -1;
1598 fdata
->saved_fpr
= -1;
1599 fdata
->saved_vr
= -1;
1600 fdata
->saved_ev
= -1;
1601 fdata
->alloca_reg
= -1;
1602 fdata
->frameless
= 1;
1603 fdata
->nosavedpc
= 1;
1604 fdata
->lr_register
= -1;
1606 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1612 /* Sometimes it isn't clear if an instruction is a prologue
1613 instruction or not. When we encounter one of these ambiguous
1614 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1615 Otherwise, we'll assume that it really is a prologue instruction. */
1616 if (prev_insn_was_prologue_insn
)
1617 last_prologue_pc
= pc
;
1619 /* Stop scanning if we've hit the limit. */
1623 prev_insn_was_prologue_insn
= 1;
1625 /* Fetch the instruction and convert it to an integer. */
1626 if (target_read_memory (pc
, buf
, 4))
1628 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1630 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1632 /* Since shared library / PIC code, which needs to get its
1633 address at runtime, can appear to save more than one link
1647 remember just the first one, but skip over additional
1650 lr_reg
= (op
& 0x03e00000) >> 21;
1652 r0_contains_arg
= 0;
1655 else if ((op
& 0xfc1fffff) == 0x7c000026)
1657 cr_reg
= (op
& 0x03e00000) >> 21;
1659 r0_contains_arg
= 0;
1663 else if ((op
& 0xfc1f0000) == 0xd8010000)
1664 { /* stfd Rx,NUM(r1) */
1665 reg
= GET_SRC_REG (op
);
1666 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1668 fdata
->saved_fpr
= reg
;
1669 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1674 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1675 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1676 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1677 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1680 reg
= GET_SRC_REG (op
);
1681 if ((op
& 0xfc1f0000) == 0xbc010000)
1682 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1684 fdata
->gpr_mask
|= 1U << reg
;
1685 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1687 fdata
->saved_gpr
= reg
;
1688 if ((op
& 0xfc1f0003) == 0xf8010000)
1690 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1695 else if ((op
& 0xffff0000) == 0x3c4c0000
1696 || (op
& 0xffff0000) == 0x3c400000
1697 || (op
& 0xffff0000) == 0x38420000)
1699 /* . 0: addis 2,12,.TOC.-0b@ha
1700 . addi 2,2,.TOC.-0b@l
1704 used by ELFv2 global entry points to set up r2. */
1707 else if (op
== 0x60000000)
1710 /* Allow nops in the prologue, but do not consider them to
1711 be part of the prologue unless followed by other prologue
1713 prev_insn_was_prologue_insn
= 0;
1717 else if ((op
& 0xffff0000) == 0x3c000000)
1718 { /* addis 0,0,NUM, used for >= 32k frames */
1719 fdata
->offset
= (op
& 0x0000ffff) << 16;
1720 fdata
->frameless
= 0;
1721 r0_contains_arg
= 0;
1725 else if ((op
& 0xffff0000) == 0x60000000)
1726 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1727 fdata
->offset
|= (op
& 0x0000ffff);
1728 fdata
->frameless
= 0;
1729 r0_contains_arg
= 0;
1733 else if (lr_reg
>= 0 &&
1734 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1736 (store_insn_p (op
, lr_reg
,
1737 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1740 if (store_insn_p (op
, lr_reg
, 1, true))
1741 fdata
->lr_offset
= offset
;
1742 else /* LR save through frame pointer. */
1743 fdata
->lr_offset
= alloca_reg_offset
;
1745 fdata
->nosavedpc
= 0;
1746 /* Invalidate lr_reg, but don't set it to -1.
1747 That would mean that it had never been set. */
1749 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1750 (op
& 0xfc000000) == 0x90000000) /* stw */
1752 /* Does not update r1, so add displacement to lr_offset. */
1753 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1758 else if (cr_reg
>= 0 &&
1759 (store_insn_p (op
, cr_reg
, 1, true)))
1761 fdata
->cr_offset
= offset
;
1762 /* Invalidate cr_reg, but don't set it to -1.
1763 That would mean that it had never been set. */
1765 if ((op
& 0xfc000003) == 0xf8000000 ||
1766 (op
& 0xfc000000) == 0x90000000)
1768 /* Does not update r1, so add displacement to cr_offset. */
1769 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1774 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1776 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1777 prediction bits. If the LR has already been saved, we can
1781 else if (op
== 0x48000005)
1788 else if (op
== 0x48000004)
1793 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1794 in V.4 -mminimal-toc */
1795 (op
& 0xffff0000) == 0x3bde0000)
1796 { /* addi 30,30,foo@l */
1800 else if ((op
& 0xfc000001) == 0x48000001)
1804 fdata
->frameless
= 0;
1806 /* If the return address has already been saved, we can skip
1807 calls to blrl (for PIC). */
1808 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1814 /* Don't skip over the subroutine call if it is not within
1815 the first three instructions of the prologue and either
1816 we have no line table information or the line info tells
1817 us that the subroutine call is not part of the line
1818 associated with the prologue. */
1819 if ((pc
- orig_pc
) > 8)
1821 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1822 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1824 if ((prologue_sal
.line
== 0)
1825 || (prologue_sal
.line
!= this_sal
.line
))
1829 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1831 /* At this point, make sure this is not a trampoline
1832 function (a function that simply calls another functions,
1833 and nothing else). If the next is not a nop, this branch
1834 was part of the function prologue. */
1836 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1837 break; /* Don't skip over
1843 /* update stack pointer */
1844 else if ((op
& 0xfc1f0000) == 0x94010000)
1845 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1846 fdata
->frameless
= 0;
1847 fdata
->offset
= SIGNED_SHORT (op
);
1848 offset
= fdata
->offset
;
1851 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1852 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1853 /* No way to figure out what r1 is going to be. */
1854 fdata
->frameless
= 0;
1855 offset
= fdata
->offset
;
1858 else if ((op
& 0xfc1f0003) == 0xf8010001)
1859 { /* stdu rX,NUM(r1) */
1860 fdata
->frameless
= 0;
1861 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1862 offset
= fdata
->offset
;
1865 else if ((op
& 0xffff0000) == 0x38210000)
1866 { /* addi r1,r1,SIMM */
1867 fdata
->frameless
= 0;
1868 fdata
->offset
+= SIGNED_SHORT (op
);
1869 offset
= fdata
->offset
;
1872 /* Load up minimal toc pointer. Do not treat an epilogue restore
1873 of r31 as a minimal TOC load. */
1874 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1875 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1877 && !minimal_toc_loaded
)
1879 minimal_toc_loaded
= 1;
1882 /* move parameters from argument registers to local variable
1885 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1886 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1887 (((op
>> 21) & 31) <= 10) &&
1888 ((long) ((op
>> 16) & 31)
1889 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1893 /* store parameters in stack */
1895 /* Move parameters from argument registers to temporary register. */
1896 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1900 /* Set up frame pointer */
1902 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1904 fdata
->frameless
= 0;
1906 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1907 alloca_reg_offset
= offset
;
1910 /* Another way to set up the frame pointer. */
1912 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1913 || op
== 0x7c3f0b78)
1915 fdata
->frameless
= 0;
1917 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1918 alloca_reg_offset
= offset
;
1921 /* Another way to set up the frame pointer. */
1923 else if ((op
& 0xfc1fffff) == 0x38010000)
1924 { /* addi rX, r1, 0x0 */
1925 fdata
->frameless
= 0;
1927 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1928 + ((op
& ~0x38010000) >> 21));
1929 alloca_reg_offset
= offset
;
1932 /* AltiVec related instructions. */
1933 /* Store the vrsave register (spr 256) in another register for
1934 later manipulation, or load a register into the vrsave
1935 register. 2 instructions are used: mfvrsave and
1936 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1937 and mtspr SPR256, Rn. */
1938 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1939 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1940 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1942 vrsave_reg
= GET_SRC_REG (op
);
1945 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1949 /* Store the register where vrsave was saved to onto the stack:
1950 rS is the register where vrsave was stored in a previous
1952 /* 100100 sssss 00001 dddddddd dddddddd */
1953 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1955 if (vrsave_reg
== GET_SRC_REG (op
))
1957 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1962 /* Compute the new value of vrsave, by modifying the register
1963 where vrsave was saved to. */
1964 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1965 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1969 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1970 in a pair of insns to save the vector registers on the
1972 /* 001110 00000 00000 iiii iiii iiii iiii */
1973 /* 001110 01110 00000 iiii iiii iiii iiii */
1974 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1975 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1977 if ((op
& 0xffff0000) == 0x38000000)
1978 r0_contains_arg
= 0;
1980 vr_saved_offset
= SIGNED_SHORT (op
);
1982 /* This insn by itself is not part of the prologue, unless
1983 if part of the pair of insns mentioned above. So do not
1984 record this insn as part of the prologue yet. */
1985 prev_insn_was_prologue_insn
= 0;
1987 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1988 /* 011111 sssss 11111 00000 00111001110 */
1989 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1991 if (pc
== (li_found_pc
+ 4))
1993 vr_reg
= GET_SRC_REG (op
);
1994 /* If this is the first vector reg to be saved, or if
1995 it has a lower number than others previously seen,
1996 reupdate the frame info. */
1997 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1999 fdata
->saved_vr
= vr_reg
;
2000 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2002 vr_saved_offset
= -1;
2007 /* End AltiVec related instructions. */
2009 /* Start BookE related instructions. */
2010 /* Store gen register S at (r31+uimm).
2011 Any register less than r13 is volatile, so we don't care. */
2012 /* 000100 sssss 11111 iiiii 01100100001 */
2013 else if (arch_info
->mach
== bfd_mach_ppc_e500
2014 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2016 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2019 ev_reg
= GET_SRC_REG (op
);
2020 imm
= (op
>> 11) & 0x1f;
2021 ev_offset
= imm
* 8;
2022 /* If this is the first vector reg to be saved, or if
2023 it has a lower number than others previously seen,
2024 reupdate the frame info. */
2025 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2027 fdata
->saved_ev
= ev_reg
;
2028 fdata
->ev_offset
= ev_offset
+ offset
;
2033 /* Store gen register rS at (r1+rB). */
2034 /* 000100 sssss 00001 bbbbb 01100100000 */
2035 else if (arch_info
->mach
== bfd_mach_ppc_e500
2036 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2038 if (pc
== (li_found_pc
+ 4))
2040 ev_reg
= GET_SRC_REG (op
);
2041 /* If this is the first vector reg to be saved, or if
2042 it has a lower number than others previously seen,
2043 reupdate the frame info. */
2044 /* We know the contents of rB from the previous instruction. */
2045 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2047 fdata
->saved_ev
= ev_reg
;
2048 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2050 vr_saved_offset
= -1;
2056 /* Store gen register r31 at (rA+uimm). */
2057 /* 000100 11111 aaaaa iiiii 01100100001 */
2058 else if (arch_info
->mach
== bfd_mach_ppc_e500
2059 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2061 /* Wwe know that the source register is 31 already, but
2062 it can't hurt to compute it. */
2063 ev_reg
= GET_SRC_REG (op
);
2064 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2065 /* If this is the first vector reg to be saved, or if
2066 it has a lower number than others previously seen,
2067 reupdate the frame info. */
2068 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2070 fdata
->saved_ev
= ev_reg
;
2071 fdata
->ev_offset
= ev_offset
+ offset
;
2076 /* Store gen register S at (r31+r0).
2077 Store param on stack when offset from SP bigger than 4 bytes. */
2078 /* 000100 sssss 11111 00000 01100100000 */
2079 else if (arch_info
->mach
== bfd_mach_ppc_e500
2080 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2082 if (pc
== (li_found_pc
+ 4))
2084 if ((op
& 0x03e00000) >= 0x01a00000)
2086 ev_reg
= GET_SRC_REG (op
);
2087 /* If this is the first vector reg to be saved, or if
2088 it has a lower number than others previously seen,
2089 reupdate the frame info. */
2090 /* We know the contents of r0 from the previous
2092 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2094 fdata
->saved_ev
= ev_reg
;
2095 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2099 vr_saved_offset
= -1;
2104 /* End BookE related instructions. */
2108 /* Not a recognized prologue instruction.
2109 Handle optimizer code motions into the prologue by continuing
2110 the search if we have no valid frame yet or if the return
2111 address is not yet saved in the frame. Also skip instructions
2112 if some of the GPRs expected to be saved are not yet saved. */
2113 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2114 && fdata
->saved_gpr
!= -1)
2116 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2118 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2122 if (op
== 0x4e800020 /* blr */
2123 || op
== 0x4e800420) /* bctr */
2124 /* Do not scan past epilogue in frameless functions or
2127 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2128 /* Never skip branches. */
2131 /* Test based on opcode and mask values of
2132 powerpc_opcodes[svc..svcla] in opcodes/ppc-opc.c. */
2133 if ((op
& 0xffff0000) == 0x44000000)
2134 /* Never skip system calls. */
2137 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2138 /* Do not scan too many insns, scanning insns is expensive with
2142 /* Continue scanning. */
2143 prev_insn_was_prologue_insn
= 0;
2149 /* I have problems with skipping over __main() that I need to address
2150 * sometime. Previously, I used to use misc_function_vector which
2151 * didn't work as well as I wanted to be. -MGO */
2153 /* If the first thing after skipping a prolog is a branch to a function,
2154 this might be a call to an initializer in main(), introduced by gcc2.
2155 We'd like to skip over it as well. Fortunately, xlc does some extra
2156 work before calling a function right after a prologue, thus we can
2157 single out such gcc2 behaviour. */
2160 if ((op
& 0xfc000001) == 0x48000001)
2161 { /* bl foo, an initializer function? */
2162 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2164 if (op
== 0x4def7b82)
2165 { /* cror 0xf, 0xf, 0xf (nop) */
2167 /* Check and see if we are in main. If so, skip over this
2168 initializer function as well. */
2170 tmp
= find_pc_misc_function (pc
);
2172 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2178 if (pc
== lim_pc
&& lr_reg
>= 0)
2179 fdata
->lr_register
= lr_reg
;
2181 fdata
->offset
= -fdata
->offset
;
2182 return last_prologue_pc
;
2186 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2188 struct rs6000_framedata frame
;
2189 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2191 /* See if we can determine the end of the prologue via the symbol table.
2192 If so, then return either PC, or the PC after the prologue, whichever
2194 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2196 CORE_ADDR post_prologue_pc
2197 = skip_prologue_using_sal (gdbarch
, func_addr
);
2198 if (post_prologue_pc
!= 0)
2199 return std::max (pc
, post_prologue_pc
);
2202 /* Can't determine prologue from the symbol table, need to examine
2205 /* Find an upper limit on the function prologue using the debug
2206 information. If the debug information could not be used to provide
2207 that bound, then use an arbitrary large number as the upper bound. */
2208 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2210 limit_pc
= pc
+ 100; /* Magic. */
2212 /* Do not allow limit_pc to be past the function end, if we know
2213 where that end is... */
2214 if (func_end_addr
&& limit_pc
> func_end_addr
)
2215 limit_pc
= func_end_addr
;
2217 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2221 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2222 in the prologue of main().
2224 The function below examines the code pointed at by PC and checks to
2225 see if it corresponds to a call to __eabi. If so, it returns the
2226 address of the instruction following that call. Otherwise, it simply
2230 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2236 if (target_read_memory (pc
, buf
, 4))
2238 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2240 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2242 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2243 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2244 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2246 /* We check for ___eabi (three leading underscores) in addition
2247 to __eabi in case the GCC option "-fleading-underscore" was
2248 used to compile the program. */
2249 if (s
.minsym
!= NULL
2250 && s
.minsym
->linkage_name () != NULL
2251 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2252 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2258 /* All the ABI's require 16 byte alignment. */
2260 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2262 return (addr
& -16);
2265 /* Return whether handle_inferior_event() should proceed through code
2266 starting at PC in function NAME when stepping.
2268 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2269 handle memory references that are too distant to fit in instructions
2270 generated by the compiler. For example, if 'foo' in the following
2275 is greater than 32767, the linker might replace the lwz with a branch to
2276 somewhere in @FIX1 that does the load in 2 instructions and then branches
2277 back to where execution should continue.
2279 GDB should silently step over @FIX code, just like AIX dbx does.
2280 Unfortunately, the linker uses the "b" instruction for the
2281 branches, meaning that the link register doesn't get set.
2282 Therefore, GDB's usual step_over_function () mechanism won't work.
2284 Instead, use the gdbarch_skip_trampoline_code and
2285 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2289 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2290 CORE_ADDR pc
, const char *name
)
2292 return name
&& startswith (name
, "@FIX");
2295 /* Skip code that the user doesn't want to see when stepping:
2297 1. Indirect function calls use a piece of trampoline code to do context
2298 switching, i.e. to set the new TOC table. Skip such code if we are on
2299 its first instruction (as when we have single-stepped to here).
2301 2. Skip shared library trampoline code (which is different from
2302 indirect function call trampolines).
2304 3. Skip bigtoc fixup code.
2306 Result is desired PC to step until, or NULL if we are not in
2307 code that should be skipped. */
2310 rs6000_skip_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
2312 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2313 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2314 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2315 unsigned int ii
, op
;
2317 CORE_ADDR solib_target_pc
;
2318 struct bound_minimal_symbol msymbol
;
2320 static unsigned trampoline_code
[] =
2322 0x800b0000, /* l r0,0x0(r11) */
2323 0x90410014, /* st r2,0x14(r1) */
2324 0x7c0903a6, /* mtctr r0 */
2325 0x804b0004, /* l r2,0x4(r11) */
2326 0x816b0008, /* l r11,0x8(r11) */
2327 0x4e800420, /* bctr */
2328 0x4e800020, /* br */
2332 /* Check for bigtoc fixup code. */
2333 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2335 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2336 msymbol
.minsym
->linkage_name ()))
2338 /* Double-check that the third instruction from PC is relative "b". */
2339 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2340 if ((op
& 0xfc000003) == 0x48000000)
2342 /* Extract bits 6-29 as a signed 24-bit relative word address and
2343 add it to the containing PC. */
2344 rel
= ((int)(op
<< 6) >> 6);
2345 return pc
+ 8 + rel
;
2349 /* If pc is in a shared library trampoline, return its target. */
2350 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2351 if (solib_target_pc
)
2352 return solib_target_pc
;
2354 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2356 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2357 if (op
!= trampoline_code
[ii
])
2360 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2362 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2366 /* ISA-specific vector types. */
2368 static struct type
*
2369 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2371 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2373 if (!tdep
->ppc_builtin_type_vec64
)
2375 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2377 /* The type we're building is this: */
2379 union __gdb_builtin_type_vec64
2383 int32_t v2_int32
[2];
2384 int16_t v4_int16
[4];
2391 t
= arch_composite_type (gdbarch
,
2392 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2393 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2394 append_composite_type_field (t
, "v2_float",
2395 init_vector_type (bt
->builtin_float
, 2));
2396 append_composite_type_field (t
, "v2_int32",
2397 init_vector_type (bt
->builtin_int32
, 2));
2398 append_composite_type_field (t
, "v4_int16",
2399 init_vector_type (bt
->builtin_int16
, 4));
2400 append_composite_type_field (t
, "v8_int8",
2401 init_vector_type (bt
->builtin_int8
, 8));
2403 t
->set_is_vector (true);
2404 t
->set_name ("ppc_builtin_type_vec64");
2405 tdep
->ppc_builtin_type_vec64
= t
;
2408 return tdep
->ppc_builtin_type_vec64
;
2411 /* Vector 128 type. */
2413 static struct type
*
2414 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2416 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2418 if (!tdep
->ppc_builtin_type_vec128
)
2420 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2422 /* The type we're building is this
2424 type = union __ppc_builtin_type_vec128 {
2425 float128_t float128;
2427 double v2_double[2];
2429 int32_t v4_int32[4];
2430 int16_t v8_int16[8];
2431 int8_t v16_int8[16];
2435 /* PPC specific type for IEEE 128-bit float field */
2436 struct type
*t_float128
2437 = arch_float_type (gdbarch
, 128, "float128_t", floatformats_ieee_quad
);
2441 t
= arch_composite_type (gdbarch
,
2442 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2443 append_composite_type_field (t
, "float128", t_float128
);
2444 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2445 append_composite_type_field (t
, "v2_double",
2446 init_vector_type (bt
->builtin_double
, 2));
2447 append_composite_type_field (t
, "v4_float",
2448 init_vector_type (bt
->builtin_float
, 4));
2449 append_composite_type_field (t
, "v4_int32",
2450 init_vector_type (bt
->builtin_int32
, 4));
2451 append_composite_type_field (t
, "v8_int16",
2452 init_vector_type (bt
->builtin_int16
, 8));
2453 append_composite_type_field (t
, "v16_int8",
2454 init_vector_type (bt
->builtin_int8
, 16));
2456 t
->set_is_vector (true);
2457 t
->set_name ("ppc_builtin_type_vec128");
2458 tdep
->ppc_builtin_type_vec128
= t
;
2461 return tdep
->ppc_builtin_type_vec128
;
2464 /* Return the name of register number REGNO, or the empty string if it
2465 is an anonymous register. */
2468 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2470 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2472 /* The upper half "registers" have names in the XML description,
2473 but we present only the low GPRs and the full 64-bit registers
2475 if (tdep
->ppc_ev0_upper_regnum
>= 0
2476 && tdep
->ppc_ev0_upper_regnum
<= regno
2477 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2480 /* Hide the upper halves of the vs0~vs31 registers. */
2481 if (tdep
->ppc_vsr0_regnum
>= 0
2482 && tdep
->ppc_vsr0_upper_regnum
<= regno
2483 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2486 /* Hide the upper halves of the cvs0~cvs31 registers. */
2487 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2488 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2491 /* Check if the SPE pseudo registers are available. */
2492 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2494 static const char *const spe_regnames
[] = {
2495 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2496 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2497 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2498 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2500 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2503 /* Check if the decimal128 pseudo-registers are available. */
2504 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2506 static const char *const dfp128_regnames
[] = {
2507 "dl0", "dl1", "dl2", "dl3",
2508 "dl4", "dl5", "dl6", "dl7",
2509 "dl8", "dl9", "dl10", "dl11",
2510 "dl12", "dl13", "dl14", "dl15"
2512 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2515 /* Check if this is a vX alias for a raw vrX vector register. */
2516 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2518 static const char *const vector_alias_regnames
[] = {
2519 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2520 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2521 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2522 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2524 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2527 /* Check if this is a VSX pseudo-register. */
2528 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2530 static const char *const vsx_regnames
[] = {
2531 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2532 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2533 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2534 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2535 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2536 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2537 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2538 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2539 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2541 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2544 /* Check if the this is a Extended FP pseudo-register. */
2545 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2547 static const char *const efpr_regnames
[] = {
2548 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2549 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2550 "f46", "f47", "f48", "f49", "f50", "f51",
2551 "f52", "f53", "f54", "f55", "f56", "f57",
2552 "f58", "f59", "f60", "f61", "f62", "f63"
2554 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2557 /* Check if this is a Checkpointed DFP pseudo-register. */
2558 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2560 static const char *const cdfp128_regnames
[] = {
2561 "cdl0", "cdl1", "cdl2", "cdl3",
2562 "cdl4", "cdl5", "cdl6", "cdl7",
2563 "cdl8", "cdl9", "cdl10", "cdl11",
2564 "cdl12", "cdl13", "cdl14", "cdl15"
2566 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2569 /* Check if this is a Checkpointed VSX pseudo-register. */
2570 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2572 static const char *const cvsx_regnames
[] = {
2573 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2574 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2575 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2576 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2577 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2578 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2579 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2580 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2581 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2583 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2586 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2587 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2589 static const char *const cefpr_regnames
[] = {
2590 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2591 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2592 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2593 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2594 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2596 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2599 return tdesc_register_name (gdbarch
, regno
);
2602 /* Return the GDB type object for the "standard" data type of data in
2605 static struct type
*
2606 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2608 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2610 /* These are the e500 pseudo-registers. */
2611 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2612 return rs6000_builtin_type_vec64 (gdbarch
);
2613 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2614 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2615 /* PPC decimal128 pseudo-registers. */
2616 return builtin_type (gdbarch
)->builtin_declong
;
2617 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2618 return gdbarch_register_type (gdbarch
,
2619 tdep
->ppc_vr0_regnum
2621 - tdep
->ppc_v0_alias_regnum
));
2622 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2623 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2624 /* POWER7 VSX pseudo-registers. */
2625 return rs6000_builtin_type_vec128 (gdbarch
);
2626 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2627 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2628 /* POWER7 Extended FP pseudo-registers. */
2629 return builtin_type (gdbarch
)->builtin_double
;
2631 internal_error (_("rs6000_pseudo_register_type: "
2632 "called on unexpected register '%s' (%d)"),
2633 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2636 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2637 the vX aliases for the vector registers by always returning false
2638 to avoid duplicated information in "info register vector/all",
2639 since the raw vrX registers will already show in these cases. For
2640 other pseudo-registers we use the default membership function. */
2643 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2644 const struct reggroup
*group
)
2646 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2648 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2651 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2654 /* The register format for RS/6000 floating point registers is always
2655 double, we need a conversion if the memory format is float. */
2658 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2661 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2663 return (tdep
->ppc_fp0_regnum
>= 0
2664 && regnum
>= tdep
->ppc_fp0_regnum
2665 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2666 && type
->code () == TYPE_CODE_FLT
2668 != builtin_type (gdbarch
)->builtin_double
->length ()));
2672 rs6000_register_to_value (frame_info_ptr frame
,
2676 int *optimizedp
, int *unavailablep
)
2678 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2679 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2681 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2683 if (!get_frame_register_bytes (frame
, regnum
, 0,
2684 gdb::make_array_view (from
,
2685 register_size (gdbarch
,
2687 optimizedp
, unavailablep
))
2690 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2692 *optimizedp
= *unavailablep
= 0;
2697 rs6000_value_to_register (frame_info_ptr frame
,
2700 const gdb_byte
*from
)
2702 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2703 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2705 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2707 target_float_convert (from
, type
,
2708 to
, builtin_type (gdbarch
)->builtin_double
);
2709 put_frame_register (frame
, regnum
, to
);
2712 /* The type of a function that moves the value of REG between CACHE
2713 or BUF --- in either direction. */
2714 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2717 /* Move SPE vector register values between a 64-bit buffer and the two
2718 32-bit raw register halves in a regcache. This function handles
2719 both splitting a 64-bit value into two 32-bit halves, and joining
2720 two halves into a whole 64-bit value, depending on the function
2721 passed as the MOVE argument.
2723 EV_REG must be the number of an SPE evN vector register --- a
2724 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2727 Call MOVE once for each 32-bit half of that register, passing
2728 REGCACHE, the number of the raw register corresponding to that
2729 half, and the address of the appropriate half of BUFFER.
2731 For example, passing 'regcache_raw_read' as the MOVE function will
2732 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2733 'regcache_raw_supply' will supply the contents of BUFFER to the
2734 appropriate pair of raw registers in REGCACHE.
2736 You may need to cast away some 'const' qualifiers when passing
2737 MOVE, since this function can't tell at compile-time which of
2738 REGCACHE or BUFFER is acting as the source of the data. If C had
2739 co-variant type qualifiers, ... */
2741 static enum register_status
2742 e500_move_ev_register (move_ev_register_func move
,
2743 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2745 struct gdbarch
*arch
= regcache
->arch ();
2746 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (arch
);
2748 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2749 enum register_status status
;
2751 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2753 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2755 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2757 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2759 if (status
== REG_VALID
)
2760 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2765 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2766 if (status
== REG_VALID
)
2767 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2774 static enum register_status
2775 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2777 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2782 static enum register_status
2783 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2784 int ev_reg
, gdb_byte
*buffer
)
2786 struct gdbarch
*arch
= regcache
->arch ();
2787 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2789 enum register_status status
;
2791 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2793 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2795 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2797 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2799 if (status
== REG_VALID
)
2800 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2805 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2806 if (status
== REG_VALID
)
2807 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2816 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2817 int reg_nr
, const gdb_byte
*buffer
)
2819 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2820 reg_nr
, (void *) buffer
);
2823 /* Read method for DFP pseudo-registers. */
2824 static enum register_status
2825 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2826 int reg_nr
, gdb_byte
*buffer
)
2828 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2830 enum register_status status
;
2832 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2834 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2835 fp0
= PPC_F0_REGNUM
;
2839 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2841 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2842 fp0
= PPC_CF0_REGNUM
;
2845 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2847 /* Read two FP registers to form a whole dl register. */
2848 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2849 if (status
== REG_VALID
)
2850 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2855 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2856 if (status
== REG_VALID
)
2857 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2863 /* Write method for DFP pseudo-registers. */
2865 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2866 int reg_nr
, const gdb_byte
*buffer
)
2868 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2871 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2873 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2874 fp0
= PPC_F0_REGNUM
;
2878 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2880 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2881 fp0
= PPC_CF0_REGNUM
;
2884 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2886 /* Write each half of the dl register into a separate
2888 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2889 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2893 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2894 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2898 /* Read method for the vX aliases for the raw vrX registers. */
2900 static enum register_status
2901 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2902 readable_regcache
*regcache
, int reg_nr
,
2905 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2906 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2908 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2909 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2913 /* Write method for the vX aliases for the raw vrX registers. */
2916 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2917 struct regcache
*regcache
,
2918 int reg_nr
, const gdb_byte
*buffer
)
2920 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2921 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2923 regcache
->raw_write (tdep
->ppc_vr0_regnum
2924 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2927 /* Read method for POWER7 VSX pseudo-registers. */
2928 static enum register_status
2929 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2930 int reg_nr
, gdb_byte
*buffer
)
2932 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2933 int reg_index
, vr0
, fp0
, vsr0_upper
;
2934 enum register_status status
;
2936 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2938 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2939 vr0
= PPC_VR0_REGNUM
;
2940 fp0
= PPC_F0_REGNUM
;
2941 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2945 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2947 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2948 vr0
= PPC_CVR0_REGNUM
;
2949 fp0
= PPC_CF0_REGNUM
;
2950 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2953 /* Read the portion that overlaps the VMX registers. */
2955 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2957 /* Read the portion that overlaps the FPR registers. */
2958 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2960 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2961 if (status
== REG_VALID
)
2962 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2967 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2968 if (status
== REG_VALID
)
2969 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2975 /* Write method for POWER7 VSX pseudo-registers. */
2977 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2978 int reg_nr
, const gdb_byte
*buffer
)
2980 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
2981 int reg_index
, vr0
, fp0
, vsr0_upper
;
2983 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2985 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2986 vr0
= PPC_VR0_REGNUM
;
2987 fp0
= PPC_F0_REGNUM
;
2988 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2992 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2994 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2995 vr0
= PPC_CVR0_REGNUM
;
2996 fp0
= PPC_CF0_REGNUM
;
2997 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3000 /* Write the portion that overlaps the VMX registers. */
3002 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
3004 /* Write the portion that overlaps the FPR registers. */
3005 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3007 regcache
->raw_write (fp0
+ reg_index
, buffer
);
3008 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
3012 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
3013 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
3017 /* Read method for POWER7 Extended FP pseudo-registers. */
3018 static enum register_status
3019 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
3020 int reg_nr
, gdb_byte
*buffer
)
3022 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3025 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3027 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3028 vr0
= PPC_VR0_REGNUM
;
3032 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3034 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3035 vr0
= PPC_CVR0_REGNUM
;
3038 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3040 /* Read the portion that overlaps the VMX register. */
3041 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
3042 register_size (gdbarch
, reg_nr
),
3046 /* Write method for POWER7 Extended FP pseudo-registers. */
3048 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3049 int reg_nr
, const gdb_byte
*buffer
)
3051 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3053 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3055 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3057 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3058 vr0
= PPC_VR0_REGNUM
;
3062 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3064 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3065 vr0
= PPC_CVR0_REGNUM
;
3067 /* The call to raw_write_part fails silently if the initial read
3068 of the read-update-write sequence returns an invalid status,
3069 so we check this manually and throw an error if needed. */
3070 regcache
->raw_update (vr0
+ reg_index
);
3071 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
3072 error (_("Cannot write to the checkpointed EFP register, "
3073 "the corresponding vector register is unavailable."));
3076 /* Write the portion that overlaps the VMX register. */
3077 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3078 register_size (gdbarch
, reg_nr
), buffer
);
3081 static enum register_status
3082 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3083 readable_regcache
*regcache
,
3084 int reg_nr
, gdb_byte
*buffer
)
3086 struct gdbarch
*regcache_arch
= regcache
->arch ();
3087 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3089 gdb_assert (regcache_arch
== gdbarch
);
3091 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3092 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3093 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3094 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3095 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3096 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3097 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3099 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3100 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3101 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3102 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3103 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3104 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3106 internal_error (_("rs6000_pseudo_register_read: "
3107 "called on unexpected register '%s' (%d)"),
3108 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3112 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3113 struct regcache
*regcache
,
3114 int reg_nr
, const gdb_byte
*buffer
)
3116 struct gdbarch
*regcache_arch
= regcache
->arch ();
3117 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3119 gdb_assert (regcache_arch
== gdbarch
);
3121 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3122 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3123 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3124 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3125 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3126 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3127 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3128 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3129 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3130 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3131 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3132 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3133 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3135 internal_error (_("rs6000_pseudo_register_write: "
3136 "called on unexpected register '%s' (%d)"),
3137 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3140 /* Set the register mask in AX with the registers that form the DFP or
3141 checkpointed DFP pseudo-register REG_NR. */
3144 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3145 struct agent_expr
*ax
, int reg_nr
)
3147 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3150 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3152 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3153 fp0
= PPC_F0_REGNUM
;
3157 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3159 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3160 fp0
= PPC_CF0_REGNUM
;
3163 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3164 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3167 /* Set the register mask in AX with the raw vector register that
3168 corresponds to its REG_NR alias. */
3171 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3172 struct agent_expr
*ax
, int reg_nr
)
3174 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3175 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3177 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3178 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3181 /* Set the register mask in AX with the registers that form the VSX or
3182 checkpointed VSX pseudo-register REG_NR. */
3185 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3186 struct agent_expr
*ax
, int reg_nr
)
3188 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3189 int reg_index
, vr0
, fp0
, vsr0_upper
;
3191 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3193 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3194 vr0
= PPC_VR0_REGNUM
;
3195 fp0
= PPC_F0_REGNUM
;
3196 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3200 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3202 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3203 vr0
= PPC_CVR0_REGNUM
;
3204 fp0
= PPC_CF0_REGNUM
;
3205 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3210 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3214 ax_reg_mask (ax
, fp0
+ reg_index
);
3215 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3219 /* Set the register mask in AX with the register that corresponds to
3220 the EFP or checkpointed EFP pseudo-register REG_NR. */
3223 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3224 struct agent_expr
*ax
, int reg_nr
)
3226 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3229 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3231 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3232 vr0
= PPC_VR0_REGNUM
;
3236 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3238 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3239 vr0
= PPC_CVR0_REGNUM
;
3242 ax_reg_mask (ax
, vr0
+ reg_index
);
3246 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3247 struct agent_expr
*ax
, int reg_nr
)
3249 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3250 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3252 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3253 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3254 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3256 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3257 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3259 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3261 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3263 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3265 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3266 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3268 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3270 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3271 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3273 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3276 internal_error (_("rs6000_pseudo_register_collect: "
3277 "called on unexpected register '%s' (%d)"),
3278 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3284 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3285 struct agent_expr
*ax
, struct axs_value
*value
,
3288 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3289 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3290 value
->kind
= axs_lvalue_register
;
3291 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3295 /* Convert a DBX STABS register number to a GDB register number. */
3297 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3299 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3301 if (0 <= num
&& num
<= 31)
3302 return tdep
->ppc_gp0_regnum
+ num
;
3303 else if (32 <= num
&& num
<= 63)
3304 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3305 specifies registers the architecture doesn't have? Our
3306 callers don't check the value we return. */
3307 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3308 else if (77 <= num
&& num
<= 108)
3309 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3310 else if (1200 <= num
&& num
< 1200 + 32)
3311 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3316 return tdep
->ppc_mq_regnum
;
3318 return tdep
->ppc_lr_regnum
;
3320 return tdep
->ppc_ctr_regnum
;
3322 return tdep
->ppc_xer_regnum
;
3324 return tdep
->ppc_vrsave_regnum
;
3326 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3328 return tdep
->ppc_acc_regnum
;
3330 return tdep
->ppc_spefscr_regnum
;
3337 /* Convert a Dwarf 2 register number to a GDB register number. */
3339 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3341 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3343 if (0 <= num
&& num
<= 31)
3344 return tdep
->ppc_gp0_regnum
+ num
;
3345 else if (32 <= num
&& num
<= 63)
3346 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3347 specifies registers the architecture doesn't have? Our
3348 callers don't check the value we return. */
3349 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3350 else if (1124 <= num
&& num
< 1124 + 32)
3351 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3352 else if (1200 <= num
&& num
< 1200 + 32)
3353 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3358 return tdep
->ppc_cr_regnum
;
3360 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3362 return tdep
->ppc_acc_regnum
;
3364 return tdep
->ppc_mq_regnum
;
3366 return tdep
->ppc_xer_regnum
;
3368 return tdep
->ppc_lr_regnum
;
3370 return tdep
->ppc_ctr_regnum
;
3372 return tdep
->ppc_vrsave_regnum
;
3374 return tdep
->ppc_spefscr_regnum
;
3377 /* Unknown DWARF register number. */
3381 /* Translate a .eh_frame register to DWARF register, or adjust a
3382 .debug_frame register. */
3385 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3387 /* GCC releases before 3.4 use GCC internal register numbering in
3388 .debug_frame (and .debug_info, et cetera). The numbering is
3389 different from the standard SysV numbering for everything except
3390 for GPRs and FPRs. We can not detect this problem in most cases
3391 - to get accurate debug info for variables living in lr, ctr, v0,
3392 et cetera, use a newer version of GCC. But we must detect
3393 one important case - lr is in column 65 in .debug_frame output,
3396 GCC 3.4, and the "hammer" branch, have a related problem. They
3397 record lr register saves in .debug_frame as 108, but still record
3398 the return column as 65. We fix that up too.
3400 We can do this because 65 is assigned to fpsr, and GCC never
3401 generates debug info referring to it. To add support for
3402 handwritten debug info that restores fpsr, we would need to add a
3403 producer version check to this. */
3412 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3413 internal register numbering; translate that to the standard DWARF2
3414 register numbering. */
3415 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3417 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3418 return num
- 68 + 86;
3419 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3420 return num
- 77 + 1124;
3432 case 109: /* vrsave */
3434 case 110: /* vscr */
3436 case 111: /* spe_acc */
3438 case 112: /* spefscr */
3446 /* Handling the various POWER/PowerPC variants. */
3448 /* Information about a particular processor variant. */
3452 /* Name of this variant. */
3455 /* English description of the variant. */
3456 const char *description
;
3458 /* bfd_arch_info.arch corresponding to variant. */
3459 enum bfd_architecture arch
;
3461 /* bfd_arch_info.mach corresponding to variant. */
3464 /* Target description for this variant. */
3465 const struct target_desc
**tdesc
;
3468 static struct ppc_variant variants
[] =
3470 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3471 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3472 {"power", "POWER user-level", bfd_arch_rs6000
,
3473 bfd_mach_rs6k
, &tdesc_rs6000
},
3474 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3475 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3476 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3477 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3478 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3479 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3480 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3481 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3482 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3483 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3484 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3485 604, &tdesc_powerpc_604
},
3486 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3487 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3488 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3489 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3490 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3491 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3492 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3493 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3494 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3495 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3496 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3497 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3500 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3501 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3502 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3503 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3504 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3505 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3506 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3507 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3508 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3509 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3510 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3511 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3513 /* FIXME: I haven't checked the register sets of the following. */
3514 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3515 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3516 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3517 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3518 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3519 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3521 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3524 /* Return the variant corresponding to architecture ARCH and machine number
3525 MACH. If no such variant exists, return null. */
3527 static const struct ppc_variant
*
3528 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3530 const struct ppc_variant
*v
;
3532 for (v
= variants
; v
->name
; v
++)
3533 if (arch
== v
->arch
&& mach
== v
->mach
)
3541 struct rs6000_frame_cache
3544 CORE_ADDR initial_sp
;
3545 trad_frame_saved_reg
*saved_regs
;
3547 /* Set BASE_P to true if this frame cache is properly initialized.
3548 Otherwise set to false because some registers or memory cannot
3551 /* Cache PC for building unavailable frame. */
3555 static struct rs6000_frame_cache
*
3556 rs6000_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3558 struct rs6000_frame_cache
*cache
;
3559 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3560 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3561 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3562 struct rs6000_framedata fdata
;
3563 int wordsize
= tdep
->wordsize
;
3564 CORE_ADDR func
= 0, pc
= 0;
3566 if ((*this_cache
) != NULL
)
3567 return (struct rs6000_frame_cache
*) (*this_cache
);
3568 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3569 (*this_cache
) = cache
;
3571 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3575 func
= get_frame_func (this_frame
);
3577 pc
= get_frame_pc (this_frame
);
3578 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3580 /* Figure out the parent's stack pointer. */
3582 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3583 address of the current frame. Things might be easier if the
3584 ->frame pointed to the outer-most address of the frame. In
3585 the mean time, the address of the prev frame is used as the
3586 base address of this frame. */
3587 cache
->base
= get_frame_register_unsigned
3588 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3590 catch (const gdb_exception_error
&ex
)
3592 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3594 return (struct rs6000_frame_cache
*) (*this_cache
);
3597 /* If the function appears to be frameless, check a couple of likely
3598 indicators that we have simply failed to find the frame setup.
3599 Two common cases of this are missing symbols (i.e.
3600 get_frame_func returns the wrong address or 0), and assembly
3601 stubs which have a fast exit path but set up a frame on the slow
3604 If the LR appears to return to this function, then presume that
3605 we have an ABI compliant frame that we failed to find. */
3606 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3611 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3612 if (func
== 0 && saved_lr
== pc
)
3616 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3617 if (func
== saved_func
)
3623 fdata
.frameless
= 0;
3624 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3628 if (!fdata
.frameless
)
3630 /* Frameless really means stackless. */
3633 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3634 byte_order
, &backchain
))
3635 cache
->base
= (CORE_ADDR
) backchain
;
3638 cache
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->base
);
3640 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3641 All fpr's from saved_fpr to fp31 are saved. */
3643 if (fdata
.saved_fpr
>= 0)
3646 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3648 /* If skip_prologue says floating-point registers were saved,
3649 but the current architecture has no floating-point registers,
3650 then that's strange. But we have no indices to even record
3651 the addresses under, so we just ignore it. */
3652 if (ppc_floating_point_unit_p (gdbarch
))
3653 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3655 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3660 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3661 All gpr's from saved_gpr to gpr31 are saved (except during the
3664 if (fdata
.saved_gpr
>= 0)
3667 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3668 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3670 if (fdata
.gpr_mask
& (1U << i
))
3671 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3672 gpr_addr
+= wordsize
;
3676 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3677 All vr's from saved_vr to vr31 are saved. */
3678 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3680 if (fdata
.saved_vr
>= 0)
3683 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3684 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3686 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3687 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3692 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3693 All vr's from saved_ev to ev31 are saved. ????? */
3694 if (tdep
->ppc_ev0_regnum
!= -1)
3696 if (fdata
.saved_ev
>= 0)
3699 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3700 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3702 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3704 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3705 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3707 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3712 /* If != 0, fdata.cr_offset is the offset from the frame that
3714 if (fdata
.cr_offset
!= 0)
3715 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3718 /* If != 0, fdata.lr_offset is the offset from the frame that
3720 if (fdata
.lr_offset
!= 0)
3721 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3723 else if (fdata
.lr_register
!= -1)
3724 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3725 /* The PC is found in the link register. */
3726 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3727 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3729 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3730 holds the VRSAVE. */
3731 if (fdata
.vrsave_offset
!= 0)
3732 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3733 + fdata
.vrsave_offset
);
3735 if (fdata
.alloca_reg
< 0)
3736 /* If no alloca register used, then fi->frame is the value of the
3737 %sp for this frame, and it is good enough. */
3739 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3742 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3749 rs6000_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3750 struct frame_id
*this_id
)
3752 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3757 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3761 /* This marks the outermost frame. */
3762 if (info
->base
== 0)
3765 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3768 static struct value
*
3769 rs6000_frame_prev_register (frame_info_ptr this_frame
,
3770 void **this_cache
, int regnum
)
3772 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3774 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3777 static const struct frame_unwind rs6000_frame_unwind
=
3781 default_frame_unwind_stop_reason
,
3782 rs6000_frame_this_id
,
3783 rs6000_frame_prev_register
,
3785 default_frame_sniffer
3788 /* Allocate and initialize a frame cache for an epilogue frame.
3789 SP is restored and prev-PC is stored in LR. */
3791 static struct rs6000_frame_cache
*
3792 rs6000_epilogue_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3794 struct rs6000_frame_cache
*cache
;
3795 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3796 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3799 return (struct rs6000_frame_cache
*) *this_cache
;
3801 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3802 (*this_cache
) = cache
;
3803 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3807 /* At this point the stack looks as if we just entered the
3808 function, and the return address is stored in LR. */
3811 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3812 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3815 cache
->initial_sp
= sp
;
3817 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)].set_value (lr
);
3819 catch (const gdb_exception_error
&ex
)
3821 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3828 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3829 Return the frame ID of an epilogue frame. */
3832 rs6000_epilogue_frame_this_id (frame_info_ptr this_frame
,
3833 void **this_cache
, struct frame_id
*this_id
)
3836 struct rs6000_frame_cache
*info
=
3837 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3839 pc
= get_frame_func (this_frame
);
3840 if (info
->base
== 0)
3841 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3843 (*this_id
) = frame_id_build (info
->base
, pc
);
3846 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3847 Return the register value of REGNUM in previous frame. */
3849 static struct value
*
3850 rs6000_epilogue_frame_prev_register (frame_info_ptr this_frame
,
3851 void **this_cache
, int regnum
)
3853 struct rs6000_frame_cache
*info
=
3854 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3855 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3858 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3859 Check whether this an epilogue frame. */
3862 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3863 frame_info_ptr this_frame
,
3864 void **this_prologue_cache
)
3866 if (frame_relative_level (this_frame
) == 0)
3867 return rs6000_in_function_epilogue_frame_p (this_frame
,
3868 get_frame_arch (this_frame
),
3869 get_frame_pc (this_frame
));
3874 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3875 a function without debug information. */
3877 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3881 default_frame_unwind_stop_reason
,
3882 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3884 rs6000_epilogue_frame_sniffer
3889 rs6000_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
3891 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3893 return info
->initial_sp
;
3896 static const struct frame_base rs6000_frame_base
= {
3897 &rs6000_frame_unwind
,
3898 rs6000_frame_base_address
,
3899 rs6000_frame_base_address
,
3900 rs6000_frame_base_address
3903 static const struct frame_base
*
3904 rs6000_frame_base_sniffer (frame_info_ptr this_frame
)
3906 return &rs6000_frame_base
;
3909 /* DWARF-2 frame support. Used to handle the detection of
3910 clobbered registers during function calls. */
3913 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3914 struct dwarf2_frame_state_reg
*reg
,
3915 frame_info_ptr this_frame
)
3917 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
3919 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3920 non-volatile registers. We will use the same code for both. */
3922 /* Call-saved GP registers. */
3923 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3924 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3925 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3926 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3928 /* Call-clobbered GP registers. */
3929 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3930 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3931 || (regnum
== tdep
->ppc_gp0_regnum
))
3932 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3934 /* Deal with FP registers, if supported. */
3935 if (tdep
->ppc_fp0_regnum
>= 0)
3937 /* Call-saved FP registers. */
3938 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3939 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3940 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3942 /* Call-clobbered FP registers. */
3943 if ((regnum
>= tdep
->ppc_fp0_regnum
3944 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3945 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3948 /* Deal with ALTIVEC registers, if supported. */
3949 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3951 /* Call-saved Altivec registers. */
3952 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3953 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3954 || regnum
== tdep
->ppc_vrsave_regnum
)
3955 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3957 /* Call-clobbered Altivec registers. */
3958 if ((regnum
>= tdep
->ppc_vr0_regnum
3959 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3960 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3963 /* Handle PC register and Stack Pointer correctly. */
3964 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3965 reg
->how
= DWARF2_FRAME_REG_RA
;
3966 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3967 reg
->how
= DWARF2_FRAME_REG_CFA
;
3971 /* Return true if a .gnu_attributes section exists in BFD and it
3972 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3973 section exists in BFD and it indicates that SPE extensions are in
3974 use. Check the .gnu.attributes section first, as the binary might be
3975 compiled for SPE, but not actually using SPE instructions. */
3978 bfd_uses_spe_extensions (bfd
*abfd
)
3981 gdb_byte
*contents
= NULL
;
3990 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3991 could be using the SPE vector abi without actually using any spe
3992 bits whatsoever. But it's close enough for now. */
3993 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3994 Tag_GNU_Power_ABI_Vector
);
3995 if (vector_abi
== 3)
3999 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
4003 size
= bfd_section_size (sect
);
4004 contents
= (gdb_byte
*) xmalloc (size
);
4005 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
4011 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
4017 char name[name_len rounded up to 4-byte alignment];
4018 char data[data_len];
4021 Technically, there's only supposed to be one such structure in a
4022 given apuinfo section, but the linker is not always vigilant about
4023 merging apuinfo sections from input files. Just go ahead and parse
4024 them all, exiting early when we discover the binary uses SPE
4027 It's not specified in what endianness the information in this
4028 section is stored. Assume that it's the endianness of the BFD. */
4032 unsigned int name_len
;
4033 unsigned int data_len
;
4036 /* If we can't read the first three fields, we're done. */
4040 name_len
= bfd_get_32 (abfd
, ptr
);
4041 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
4042 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
4043 type
= bfd_get_32 (abfd
, ptr
+ 8);
4046 /* The name must be "APUinfo\0". */
4048 && strcmp ((const char *) ptr
, "APUinfo") != 0)
4052 /* The type must be 2. */
4056 /* The data is stored as a series of uint32. The upper half of
4057 each uint32 indicates the particular APU used and the lower
4058 half indicates the revision of that APU. We just care about
4061 /* Not 4-byte quantities. */
4067 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
4068 unsigned int apu
= apuinfo
>> 16;
4072 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4074 if (apu
== 0x100 || apu
== 0x101)
4089 /* These are macros for parsing instruction fields (I.1.6.28) */
4091 #define PPC_FIELD(value, from, len) \
4092 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4093 #define PPC_SEXT(v, bs) \
4094 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4095 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4096 - ((CORE_ADDR) 1 << ((bs) - 1)))
4097 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4098 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4099 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4100 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4101 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4102 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4103 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4104 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4105 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4106 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4107 | (PPC_FIELD (insn, 16, 5) << 5))
4108 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4109 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4110 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4111 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4112 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4113 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4114 #define PPC_OE(insn) PPC_BIT (insn, 21)
4115 #define PPC_RC(insn) PPC_BIT (insn, 31)
4116 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4117 #define PPC_LK(insn) PPC_BIT (insn, 31)
4118 #define PPC_TX(insn) PPC_BIT (insn, 31)
4119 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4121 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4122 #define PPC_XTp(insn) ((PPC_BIT (insn, 10) << 5) \
4123 | PPC_FIELD (insn, 6, 4) << 1)
4124 #define PPC_XSp(insn) ((PPC_BIT (insn, 10) << 5) \
4125 | PPC_FIELD (insn, 6, 4) << 1)
4126 #define PPC_XER_NB(xer) (xer & 0x7f)
4128 /* The following macros are for the prefixed instructions. */
4129 #define P_PPC_D(insn_prefix, insn_suffix) \
4130 PPC_SEXT (PPC_FIELD (insn_prefix, 14, 18) << 16 \
4131 | PPC_FIELD (insn_suffix, 16, 16), 34)
4132 #define P_PPC_TX5(insn_sufix) PPC_BIT (insn_suffix, 5)
4133 #define P_PPC_TX15(insn_suffix) PPC_BIT (insn_suffix, 15)
4134 #define P_PPC_XT(insn_suffix) ((PPC_TX (insn_suffix) << 5) \
4135 | PPC_T (insn_suffix))
4136 #define P_PPC_XT5(insn_suffix) ((P_PPC_TX5 (insn_suffix) << 5) \
4137 | PPC_T (insn_suffix))
4138 #define P_PPC_XT15(insn_suffix) \
4139 ((P_PPC_TX15 (insn_suffix) << 5) | PPC_T (insn_suffix))
4141 /* Record Vector-Scalar Registers.
4142 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4143 Otherwise, it's just a VR register. Record them accordingly. */
4146 ppc_record_vsr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
, int vsr
)
4148 if (vsr
< 0 || vsr
>= 64)
4153 if (tdep
->ppc_vr0_regnum
>= 0)
4154 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4158 if (tdep
->ppc_fp0_regnum
>= 0)
4159 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4160 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4161 record_full_arch_list_add_reg (regcache
,
4162 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4168 /* The ppc_record_ACC_fpscr() records the changes to the VSR registers
4169 modified by a floating point instruction. The ENTRY argument selects which
4170 of the eight AT entries needs to be recorded. The boolean SAVE_FPSCR
4171 argument is set to TRUE to indicate the FPSCR also needs to be recorded.
4172 The function returns 0 on success. */
4175 ppc_record_ACC_fpscr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
,
4176 int entry
, bool save_fpscr
)
4179 if (entry
< 0 || entry
>= 8)
4182 /* The ACC register file consists of 8 register entries, each register
4183 entry consist of four 128-bit rows.
4185 The ACC rows map to specific VSR registers.
4191 ACC[7][0] -> VSR[28]
4192 ACC[7][1] -> VSR[29]
4193 ACC[7][2] -> VSR[30]
4194 ACC[7][3] -> VSR[31]
4197 In ISA 3.1 the ACC is mapped on top of VSR[0] thru VSR[31].
4199 In the future, the ACC may be implemented as an independent register file
4200 rather than mapping on top of the VSRs. This will then require the ACC to
4201 be assigned its own register number and the ptrace interface to be able
4202 access the ACC. Note the ptrace interface for the ACC will also need to
4205 /* ACC maps over the same VSR space as the fp registers. */
4206 for (i
= 0; i
< 4; i
++)
4208 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
4210 record_full_arch_list_add_reg (regcache
,
4211 tdep
->ppc_vsr0_upper_regnum
4216 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4221 /* Parse and record instructions primary opcode-4 at ADDR.
4222 Return 0 if successful. */
4225 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4226 CORE_ADDR addr
, uint32_t insn
)
4228 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4229 int ext
= PPC_FIELD (insn
, 21, 11);
4230 int vra
= PPC_FIELD (insn
, 11, 5);
4234 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4235 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4236 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4237 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4238 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4240 case 20: /* Move To VSR Byte Mask Immediate opcode, b2 = 0,
4242 case 21: /* Move To VSR Byte Mask Immediate opcode, b2 = 1,
4244 case 23: /* Vector Multiply-Sum & write Carry-out Unsigned
4246 case 24: /* Vector Extract Double Unsigned Byte to VSR
4247 using GPR-specified Left-Index */
4248 case 25: /* Vector Extract Double Unsigned Byte to VSR
4249 using GPR-specified Right-Index */
4250 case 26: /* Vector Extract Double Unsigned Halfword to VSR
4251 using GPR-specified Left-Index */
4252 case 27: /* Vector Extract Double Unsigned Halfword to VSR
4253 using GPR-specified Right-Index */
4254 case 28: /* Vector Extract Double Unsigned Word to VSR
4255 using GPR-specified Left-Index */
4256 case 29: /* Vector Extract Double Unsigned Word to VSR
4257 using GPR-specified Right-Index */
4258 case 30: /* Vector Extract Double Unsigned Doubleword to VSR
4259 using GPR-specified Left-Index */
4260 case 31: /* Vector Extract Double Unsigned Doubleword to VSR
4261 using GPR-specified Right-Index */
4262 case 42: /* Vector Select */
4263 case 43: /* Vector Permute */
4264 case 59: /* Vector Permute Right-indexed */
4265 case 22: /* Vector Shift
4266 Left Double by Bit Immediate if insn[21] = 0
4267 Right Double by Bit Immediate if insn[21] = 1 */
4268 case 44: /* Vector Shift Left Double by Octet Immediate */
4269 case 45: /* Vector Permute and Exclusive-OR */
4270 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4271 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4272 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4273 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4274 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4275 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4276 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4277 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4278 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4279 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4280 case 46: /* Vector Multiply-Add Single-Precision */
4281 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4282 record_full_arch_list_add_reg (regcache
,
4283 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4286 case 48: /* Multiply-Add High Doubleword */
4287 case 49: /* Multiply-Add High Doubleword Unsigned */
4288 case 51: /* Multiply-Add Low Doubleword */
4289 record_full_arch_list_add_reg (regcache
,
4290 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4294 switch ((ext
& 0x1ff))
4297 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4298 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4299 && vra
!= 4 /* Decimal Convert To Zoned */
4300 && vra
!= 5 /* Decimal Convert To National */
4301 && vra
!= 6 /* Decimal Convert From Zoned */
4302 && vra
!= 7 /* Decimal Convert From National */
4303 && vra
!= 31) /* Decimal Set Sign */
4306 /* 5.16 Decimal Integer Arithmetic Instructions */
4307 case 1: /* Decimal Add Modulo */
4308 case 65: /* Decimal Subtract Modulo */
4310 case 193: /* Decimal Shift */
4311 case 129: /* Decimal Unsigned Shift */
4312 case 449: /* Decimal Shift and Round */
4314 case 257: /* Decimal Truncate */
4315 case 321: /* Decimal Unsigned Truncate */
4317 /* Bit-21 should be set. */
4318 if (!PPC_BIT (insn
, 21))
4321 record_full_arch_list_add_reg (regcache
,
4322 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4323 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4327 /* Bit-21 is used for RC */
4328 switch (ext
& 0x3ff)
4330 case 5: /* Vector Rotate Left Quadword */
4331 case 69: /* Vector Rotate Left Quadword then Mask Insert */
4332 case 325: /* Vector Rotate Left Quadword then AND with Mask */
4333 case 6: /* Vector Compare Equal To Unsigned Byte */
4334 case 70: /* Vector Compare Equal To Unsigned Halfword */
4335 case 134: /* Vector Compare Equal To Unsigned Word */
4336 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4337 case 774: /* Vector Compare Greater Than Signed Byte */
4338 case 838: /* Vector Compare Greater Than Signed Halfword */
4339 case 902: /* Vector Compare Greater Than Signed Word */
4340 case 967: /* Vector Compare Greater Than Signed Doubleword */
4341 case 903: /* Vector Compare Greater Than Signed Quadword */
4342 case 518: /* Vector Compare Greater Than Unsigned Byte */
4343 case 646: /* Vector Compare Greater Than Unsigned Word */
4344 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4345 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4346 case 647: /* Vector Compare Greater Than Unsigned Quadword */
4347 case 966: /* Vector Compare Bounds Single-Precision */
4348 case 198: /* Vector Compare Equal To Single-Precision */
4349 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4350 case 455: /* Vector Compare Equal Quadword */
4351 case 710: /* Vector Compare Greater Than Single-Precision */
4352 case 7: /* Vector Compare Not Equal Byte */
4353 case 71: /* Vector Compare Not Equal Halfword */
4354 case 135: /* Vector Compare Not Equal Word */
4355 case 263: /* Vector Compare Not Equal or Zero Byte */
4356 case 327: /* Vector Compare Not Equal or Zero Halfword */
4357 case 391: /* Vector Compare Not Equal or Zero Word */
4359 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4360 record_full_arch_list_add_reg (regcache
,
4361 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4365 switch (vra
) /* Bit-21 is used for RC */
4367 case 0: /* Vector String Isolate Byte Left-justified */
4368 case 1: /* Vector String Isolate Byte Right-justified */
4369 case 2: /* Vector String Isolate Halfword Left-justified */
4370 case 3: /* Vector String Isolate Halfword Right-justified */
4372 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4373 record_full_arch_list_add_reg (regcache
,
4374 tdep
->ppc_vr0_regnum
4384 case 0: /* Vector Count Leading Zero Least-Significant Bits
4386 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4388 record_full_arch_list_add_reg (regcache
,
4389 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4392 case 6: /* Vector Negate Word */
4393 case 7: /* Vector Negate Doubleword */
4394 case 8: /* Vector Parity Byte Word */
4395 case 9: /* Vector Parity Byte Doubleword */
4396 case 10: /* Vector Parity Byte Quadword */
4397 case 16: /* Vector Extend Sign Byte To Word */
4398 case 17: /* Vector Extend Sign Halfword To Word */
4399 case 24: /* Vector Extend Sign Byte To Doubleword */
4400 case 25: /* Vector Extend Sign Halfword To Doubleword */
4401 case 26: /* Vector Extend Sign Word To Doubleword */
4402 case 27: /* Vector Extend Sign Doubleword To Quadword */
4403 case 28: /* Vector Count Trailing Zeros Byte */
4404 case 29: /* Vector Count Trailing Zeros Halfword */
4405 case 30: /* Vector Count Trailing Zeros Word */
4406 case 31: /* Vector Count Trailing Zeros Doubleword */
4407 record_full_arch_list_add_reg (regcache
,
4408 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4417 case 0: /* Vector Expand Byte Mask */
4418 case 1: /* Vector Expand Halfword Mask */
4419 case 2: /* Vector Expand Word Mask */
4420 case 3: /* Vector Expand Doubleword Mask */
4421 case 4: /* Vector Expand Quadword Mask */
4422 case 16: /* Move to VSR Byte Mask */
4423 case 17: /* Move to VSR Halfword Mask */
4424 case 18: /* Move to VSR Word Mask */
4425 case 19: /* Move to VSR Doubleword Mask */
4426 case 20: /* Move to VSR Quadword Mask */
4427 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
4430 case 8: /* Vector Extract Byte Mask */
4431 case 9: /* Vector Extract Halfword Mask */
4432 case 10: /* Vector Extract Word Mask */
4433 case 11: /* Vector Extract Doubleword Mask */
4434 case 12: /* Vector Extract Quadword Mask */
4436 /* Ignore the MP bit in the LSB position of the vra value. */
4437 case 24: /* Vector Count Mask Bits Byte, MP = 0 */
4438 case 25: /* Vector Count Mask Bits Byte, MP = 1 */
4439 case 26: /* Vector Count Mask Bits Halfword, MP = 0 */
4440 case 27: /* Vector Count Mask Bits Halfword, MP = 1 */
4441 case 28: /* Vector Count Mask Bits Word, MP = 0 */
4442 case 29: /* Vector Count Mask Bits Word, MP = 1 */
4443 case 30: /* Vector Count Mask Bits Doubleword, MP = 0 */
4444 case 31: /* Vector Count Mask Bits Doubleword, MP = 1 */
4445 record_full_arch_list_add_reg (regcache
,
4446 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4447 record_full_arch_list_add_reg (regcache
,
4448 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4456 case 257: /* Vector Compare Unsigned Quadword */
4457 case 321: /* Vector Compare Signed Quadword */
4458 /* Comparison tests that always set CR field BF */
4459 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4460 record_full_arch_list_add_reg (regcache
,
4461 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4464 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4465 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4466 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4467 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4468 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4469 case 462: /* Vector Pack Signed Word Signed Saturate */
4470 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4471 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4472 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4473 case 512: /* Vector Add Unsigned Byte Saturate */
4474 case 576: /* Vector Add Unsigned Halfword Saturate */
4475 case 640: /* Vector Add Unsigned Word Saturate */
4476 case 768: /* Vector Add Signed Byte Saturate */
4477 case 832: /* Vector Add Signed Halfword Saturate */
4478 case 896: /* Vector Add Signed Word Saturate */
4479 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4480 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4481 case 1664: /* Vector Subtract Unsigned Word Saturate */
4482 case 1792: /* Vector Subtract Signed Byte Saturate */
4483 case 1856: /* Vector Subtract Signed Halfword Saturate */
4484 case 1920: /* Vector Subtract Signed Word Saturate */
4486 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4487 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4488 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4489 case 1672: /* Vector Sum across Half Signed Word Saturate */
4490 case 1928: /* Vector Sum across Signed Word Saturate */
4491 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4492 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4493 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4495 case 12: /* Vector Merge High Byte */
4496 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4497 case 76: /* Vector Merge High Halfword */
4498 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4499 case 140: /* Vector Merge High Word */
4500 case 268: /* Vector Merge Low Byte */
4501 case 332: /* Vector Merge Low Halfword */
4502 case 396: /* Vector Merge Low Word */
4503 case 397: /* Vector Clear Leftmost Bytes */
4504 case 461: /* Vector Clear Rightmost Bytes */
4505 case 526: /* Vector Unpack High Signed Byte */
4506 case 590: /* Vector Unpack High Signed Halfword */
4507 case 654: /* Vector Unpack Low Signed Byte */
4508 case 718: /* Vector Unpack Low Signed Halfword */
4509 case 782: /* Vector Pack Pixel */
4510 case 846: /* Vector Unpack High Pixel */
4511 case 974: /* Vector Unpack Low Pixel */
4512 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4513 case 1614: /* Vector Unpack High Signed Word */
4514 case 1676: /* Vector Merge Odd Word */
4515 case 1742: /* Vector Unpack Low Signed Word */
4516 case 1932: /* Vector Merge Even Word */
4517 case 524: /* Vector Splat Byte */
4518 case 588: /* Vector Splat Halfword */
4519 case 652: /* Vector Splat Word */
4520 case 780: /* Vector Splat Immediate Signed Byte */
4521 case 844: /* Vector Splat Immediate Signed Halfword */
4522 case 908: /* Vector Splat Immediate Signed Word */
4523 case 261: /* Vector Shift Left Quadword */
4524 case 452: /* Vector Shift Left */
4525 case 517: /* Vector Shift Right Quadword */
4526 case 708: /* Vector Shift Right */
4527 case 773: /* Vector Shift Right Algebraic Quadword */
4528 case 1036: /* Vector Shift Left by Octet */
4529 case 1100: /* Vector Shift Right by Octet */
4530 case 0: /* Vector Add Unsigned Byte Modulo */
4531 case 64: /* Vector Add Unsigned Halfword Modulo */
4532 case 128: /* Vector Add Unsigned Word Modulo */
4533 case 192: /* Vector Add Unsigned Doubleword Modulo */
4534 case 256: /* Vector Add Unsigned Quadword Modulo */
4535 case 320: /* Vector Add & write Carry Unsigned Quadword */
4536 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4537 case 8: /* Vector Multiply Odd Unsigned Byte */
4538 case 72: /* Vector Multiply Odd Unsigned Halfword */
4539 case 136: /* Vector Multiply Odd Unsigned Word */
4540 case 200: /* Vector Multiply Odd Unsigned Doubleword */
4541 case 264: /* Vector Multiply Odd Signed Byte */
4542 case 328: /* Vector Multiply Odd Signed Halfword */
4543 case 392: /* Vector Multiply Odd Signed Word */
4544 case 456: /* Vector Multiply Odd Signed Doubleword */
4545 case 520: /* Vector Multiply Even Unsigned Byte */
4546 case 584: /* Vector Multiply Even Unsigned Halfword */
4547 case 648: /* Vector Multiply Even Unsigned Word */
4548 case 712: /* Vector Multiply Even Unsigned Doubleword */
4549 case 776: /* Vector Multiply Even Signed Byte */
4550 case 840: /* Vector Multiply Even Signed Halfword */
4551 case 904: /* Vector Multiply Even Signed Word */
4552 case 968: /* Vector Multiply Even Signed Doubleword */
4553 case 457: /* Vector Multiply Low Doubleword */
4554 case 649: /* Vector Multiply High Unsigned Word */
4555 case 713: /* Vector Multiply High Unsigned Doubleword */
4556 case 905: /* Vector Multiply High Signed Word */
4557 case 969: /* Vector Multiply High Signed Doubleword */
4558 case 11: /* Vector Divide Unsigned Quadword */
4559 case 203: /* Vector Divide Unsigned Doubleword */
4560 case 139: /* Vector Divide Unsigned Word */
4561 case 267: /* Vector Divide Signed Quadword */
4562 case 459: /* Vector Divide Signed Doubleword */
4563 case 395: /* Vector Divide Signed Word */
4564 case 523: /* Vector Divide Extended Unsigned Quadword */
4565 case 715: /* Vector Divide Extended Unsigned Doubleword */
4566 case 651: /* Vector Divide Extended Unsigned Word */
4567 case 779: /* Vector Divide Extended Signed Quadword */
4568 case 971: /* Vector Divide Extended Signed Doubleword */
4569 case 907: /* Vector Divide Extended Unsigned Word */
4570 case 1547: /* Vector Modulo Unsigned Quadword */
4571 case 1675: /* Vector Modulo Unsigned Word */
4572 case 1739: /* Vector Modulo Unsigned Doubleword */
4573 case 1803: /* Vector Modulo Signed Quadword */
4574 case 1931: /* Vector Modulo Signed Word */
4575 case 1995: /* Vector Modulo Signed Doubleword */
4577 case 137: /* Vector Multiply Unsigned Word Modulo */
4578 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4579 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4580 case 1152: /* Vector Subtract Unsigned Word Modulo */
4581 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4582 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4583 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4584 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4585 case 1282: /* Vector Average Signed Byte */
4586 case 1346: /* Vector Average Signed Halfword */
4587 case 1410: /* Vector Average Signed Word */
4588 case 1026: /* Vector Average Unsigned Byte */
4589 case 1090: /* Vector Average Unsigned Halfword */
4590 case 1154: /* Vector Average Unsigned Word */
4591 case 258: /* Vector Maximum Signed Byte */
4592 case 322: /* Vector Maximum Signed Halfword */
4593 case 386: /* Vector Maximum Signed Word */
4594 case 450: /* Vector Maximum Signed Doubleword */
4595 case 2: /* Vector Maximum Unsigned Byte */
4596 case 66: /* Vector Maximum Unsigned Halfword */
4597 case 130: /* Vector Maximum Unsigned Word */
4598 case 194: /* Vector Maximum Unsigned Doubleword */
4599 case 770: /* Vector Minimum Signed Byte */
4600 case 834: /* Vector Minimum Signed Halfword */
4601 case 898: /* Vector Minimum Signed Word */
4602 case 962: /* Vector Minimum Signed Doubleword */
4603 case 514: /* Vector Minimum Unsigned Byte */
4604 case 578: /* Vector Minimum Unsigned Halfword */
4605 case 642: /* Vector Minimum Unsigned Word */
4606 case 706: /* Vector Minimum Unsigned Doubleword */
4607 case 1028: /* Vector Logical AND */
4608 case 1668: /* Vector Logical Equivalent */
4609 case 1092: /* Vector Logical AND with Complement */
4610 case 1412: /* Vector Logical NAND */
4611 case 1348: /* Vector Logical OR with Complement */
4612 case 1156: /* Vector Logical OR */
4613 case 1284: /* Vector Logical NOR */
4614 case 1220: /* Vector Logical XOR */
4615 case 4: /* Vector Rotate Left Byte */
4616 case 132: /* Vector Rotate Left Word VX-form */
4617 case 68: /* Vector Rotate Left Halfword */
4618 case 196: /* Vector Rotate Left Doubleword */
4619 case 260: /* Vector Shift Left Byte */
4620 case 388: /* Vector Shift Left Word */
4621 case 324: /* Vector Shift Left Halfword */
4622 case 1476: /* Vector Shift Left Doubleword */
4623 case 516: /* Vector Shift Right Byte */
4624 case 644: /* Vector Shift Right Word */
4625 case 580: /* Vector Shift Right Halfword */
4626 case 1732: /* Vector Shift Right Doubleword */
4627 case 772: /* Vector Shift Right Algebraic Byte */
4628 case 900: /* Vector Shift Right Algebraic Word */
4629 case 836: /* Vector Shift Right Algebraic Halfword */
4630 case 964: /* Vector Shift Right Algebraic Doubleword */
4631 case 10: /* Vector Add Single-Precision */
4632 case 74: /* Vector Subtract Single-Precision */
4633 case 1034: /* Vector Maximum Single-Precision */
4634 case 1098: /* Vector Minimum Single-Precision */
4635 case 842: /* Vector Convert From Signed Fixed-Point Word */
4636 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4637 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4638 case 522: /* Vector Round to Single-Precision Integer Nearest */
4639 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4640 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4641 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4642 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4643 case 266: /* Vector Reciprocal Estimate Single-Precision */
4644 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4645 case 1288: /* Vector AES Cipher */
4646 case 1289: /* Vector AES Cipher Last */
4647 case 1352: /* Vector AES Inverse Cipher */
4648 case 1353: /* Vector AES Inverse Cipher Last */
4649 case 1480: /* Vector AES SubBytes */
4650 case 1730: /* Vector SHA-512 Sigma Doubleword */
4651 case 1666: /* Vector SHA-256 Sigma Word */
4652 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4653 case 1160: /* Vector Polynomial Multiply-Sum Word */
4654 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4655 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4656 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4657 case 1794: /* Vector Count Leading Zeros Byte */
4658 case 1858: /* Vector Count Leading Zeros Halfword */
4659 case 1922: /* Vector Count Leading Zeros Word */
4660 case 1924: /* Vector Count Leading Zeros Doubleword under
4662 case 1986: /* Vector Count Leading Zeros Doubleword */
4663 case 1988: /* Vector Count Trailing Zeros Doubleword under bit
4665 case 1795: /* Vector Population Count Byte */
4666 case 1859: /* Vector Population Count Halfword */
4667 case 1923: /* Vector Population Count Word */
4668 case 1987: /* Vector Population Count Doubleword */
4669 case 1356: /* Vector Bit Permute Quadword */
4670 case 1484: /* Vector Bit Permute Doubleword */
4671 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4672 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4674 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4675 case 65: /* Vector Multiply-by-10 Extended & write Carry
4676 Unsigned Quadword */
4677 case 1027: /* Vector Absolute Difference Unsigned Byte */
4678 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4679 case 1155: /* Vector Absolute Difference Unsigned Word */
4680 case 1796: /* Vector Shift Right Variable */
4681 case 1860: /* Vector Shift Left Variable */
4682 case 133: /* Vector Rotate Left Word then Mask Insert */
4683 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4684 case 389: /* Vector Rotate Left Word then AND with Mask */
4685 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4686 case 525: /* Vector Extract Unsigned Byte */
4687 case 589: /* Vector Extract Unsigned Halfword */
4688 case 653: /* Vector Extract Unsigned Word */
4689 case 717: /* Vector Extract Doubleword */
4690 case 15: /* Vector Insert Byte from VSR using GPR-specified
4692 case 79: /* Vector Insert Halfword from VSR using GPR-specified
4694 case 143: /* Vector Insert Word from VSR using GPR-specified
4696 case 207: /* Vector Insert Word from GPR using
4697 immediate-specified index */
4698 case 463: /* Vector Insert Doubleword from GPR using
4699 immediate-specified index */
4700 case 271: /* Vector Insert Byte from VSR using GPR-specified
4702 case 335: /* Vector Insert Halfword from VSR using GPR-specified
4704 case 399: /* Vector Insert Word from VSR using GPR-specified
4706 case 527: /* Vector Insert Byte from GPR using GPR-specified
4708 case 591: /* Vector Insert Halfword from GPR using GPR-specified
4710 case 655: /* Vector Insert Word from GPR using GPR-specified
4712 case 719: /* Vector Insert Doubleword from GPR using
4713 GPR-specified Left-Index */
4714 case 783: /* Vector Insert Byte from GPR using GPR-specified
4716 case 847: /* Vector Insert Halfword from GPR using GPR-specified
4718 case 911: /* Vector Insert Word from GPR using GPR-specified
4720 case 975: /* Vector Insert Doubleword from GPR using
4721 GPR-specified Right-Index */
4722 case 781: /* Vector Insert Byte */
4723 case 845: /* Vector Insert Halfword */
4724 case 909: /* Vector Insert Word */
4725 case 973: /* Vector Insert Doubleword */
4726 case 1357: /* Vector Centrifuge Doubleword */
4727 case 1421: /* Vector Parallel Bits Extract Doubleword */
4728 case 1485: /* Vector Parallel Bits Deposit Doubleword */
4729 record_full_arch_list_add_reg (regcache
,
4730 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4733 case 1228: /* Vector Gather every Nth Bit */
4734 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4735 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4736 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4737 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4738 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4739 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4740 record_full_arch_list_add_reg (regcache
,
4741 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4744 case 1604: /* Move To Vector Status and Control Register */
4745 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4747 case 1540: /* Move From Vector Status and Control Register */
4748 record_full_arch_list_add_reg (regcache
,
4749 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4751 case 833: /* Decimal Copy Sign */
4752 record_full_arch_list_add_reg (regcache
,
4753 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4754 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4758 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
4759 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4763 /* Parse and record instructions of primary opcode 6 at ADDR.
4764 Return 0 if successful. */
4767 ppc_process_record_op6 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4768 CORE_ADDR addr
, uint32_t insn
)
4770 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4771 int subtype
= PPC_FIELD (insn
, 28, 4);
4776 case 0: /* Load VSX Vector Paired */
4777 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
));
4778 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
) + 1);
4780 case 1: /* Store VSX Vector Paired */
4781 if (PPC_RA (insn
) != 0)
4782 regcache_raw_read_unsigned (regcache
,
4783 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ea
);
4784 ea
+= PPC_DQ (insn
) << 4;
4785 record_full_arch_list_add_mem (ea
, 32);
4791 /* Parse and record instructions of primary opcode-19 at ADDR.
4792 Return 0 if successful. */
4795 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4796 CORE_ADDR addr
, uint32_t insn
)
4798 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4799 int ext
= PPC_EXTOP (insn
);
4801 switch (ext
& 0x01f)
4803 case 2: /* Add PC Immediate Shifted */
4804 record_full_arch_list_add_reg (regcache
,
4805 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4811 case 0: /* Move Condition Register Field */
4812 case 33: /* Condition Register NOR */
4813 case 129: /* Condition Register AND with Complement */
4814 case 193: /* Condition Register XOR */
4815 case 225: /* Condition Register NAND */
4816 case 257: /* Condition Register AND */
4817 case 289: /* Condition Register Equivalent */
4818 case 417: /* Condition Register OR with Complement */
4819 case 449: /* Condition Register OR */
4820 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4823 case 16: /* Branch Conditional */
4824 case 560: /* Branch Conditional to Branch Target Address Register */
4825 if ((PPC_BO (insn
) & 0x4) == 0)
4826 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4828 case 528: /* Branch Conditional to Count Register */
4830 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4833 case 150: /* Instruction Synchronize */
4838 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
4839 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4843 /* Parse and record instructions of primary opcode-31 with the extended opcode
4844 177. The argument is the word instruction (insn). Return 0 if successful.
4848 ppc_process_record_op31_177 (struct gdbarch
*gdbarch
,
4849 struct regcache
*regcache
,
4852 int RA_opcode
= PPC_RA(insn
);
4853 int as
= PPC_FIELD (insn
, 6, 3);
4854 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4858 case 0: /* VSX Move From Accumulator, xxmfacc */
4859 case 1: /* VSX Move To Accumulator, xxmtacc */
4860 case 3: /* VSX Set Accumulator to Zero, xxsetaccz */
4861 ppc_record_ACC_fpscr (regcache
, tdep
, as
, false);
4867 /* Parse and record instructions of primary opcode-31 at ADDR.
4868 Return 0 if successful. */
4871 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4872 CORE_ADDR addr
, uint32_t insn
)
4874 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
4875 int ext
= PPC_EXTOP (insn
);
4876 int tmp
, nr
, nb
= 0, i
;
4877 CORE_ADDR at_dcsz
, ea
= 0;
4878 ULONGEST rb
, ra
, xer
;
4881 /* These instructions have OE bit. */
4882 switch (ext
& 0x1ff)
4884 /* These write RT and XER. Update CR if RC is set. */
4885 case 8: /* Subtract from carrying */
4886 case 10: /* Add carrying */
4887 case 136: /* Subtract from extended */
4888 case 138: /* Add extended */
4889 case 200: /* Subtract from zero extended */
4890 case 202: /* Add to zero extended */
4891 case 232: /* Subtract from minus one extended */
4892 case 234: /* Add to minus one extended */
4893 /* CA is always altered, but SO/OV are only altered when OE=1.
4894 In any case, XER is always altered. */
4895 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4897 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4898 record_full_arch_list_add_reg (regcache
,
4899 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4902 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4903 case 40: /* Subtract from */
4904 case 104: /* Negate */
4905 case 233: /* Multiply low doubleword */
4906 case 235: /* Multiply low word */
4908 case 393: /* Divide Doubleword Extended Unsigned */
4909 case 395: /* Divide Word Extended Unsigned */
4910 case 425: /* Divide Doubleword Extended */
4911 case 427: /* Divide Word Extended */
4912 case 457: /* Divide Doubleword Unsigned */
4913 case 459: /* Divide Word Unsigned */
4914 case 489: /* Divide Doubleword */
4915 case 491: /* Divide Word */
4917 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4919 case 9: /* Multiply High Doubleword Unsigned */
4920 case 11: /* Multiply High Word Unsigned */
4921 case 73: /* Multiply High Doubleword */
4922 case 75: /* Multiply High Word */
4924 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4925 record_full_arch_list_add_reg (regcache
,
4926 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4930 if ((ext
& 0x1f) == 15)
4932 /* Integer Select. bit[16:20] is used for BC. */
4933 record_full_arch_list_add_reg (regcache
,
4934 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4938 if ((ext
& 0xff) == 170)
4940 /* Add Extended using alternate carry bits */
4941 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4942 record_full_arch_list_add_reg (regcache
,
4943 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4949 case 78: /* Determine Leftmost Zero Byte */
4951 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4952 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4953 record_full_arch_list_add_reg (regcache
,
4954 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4957 /* These only write RT. */
4958 case 19: /* Move from condition register */
4959 /* Move From One Condition Register Field */
4960 case 74: /* Add and Generate Sixes */
4961 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4962 case 302: /* Move From Branch History Rolling Buffer */
4963 case 339: /* Move From Special Purpose Register */
4964 case 371: /* Move From Time Base [Phased-Out] */
4965 case 309: /* Load Doubleword Monitored Indexed */
4966 case 128: /* Set Boolean */
4967 case 384: /* Set Boolean Condition */
4968 case 416: /* Set Boolean Condition Reverse */
4969 case 448: /* Set Negative Boolean Condition */
4970 case 480: /* Set Negative Boolean Condition Reverse */
4971 case 755: /* Deliver A Random Number */
4972 record_full_arch_list_add_reg (regcache
,
4973 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4976 /* These only write to RA. */
4977 case 51: /* Move From VSR Doubleword */
4978 case 59: /* Count Leading Zeros Doubleword under bit Mask */
4979 case 115: /* Move From VSR Word and Zero */
4980 case 122: /* Population count bytes */
4981 case 155: /* Byte-Reverse Word */
4982 case 156: /* Parallel Bits Deposit Doubleword */
4983 case 187: /* Byte-Reverse Doubleword */
4984 case 188: /* Parallel Bits Extract Doubleword */
4985 case 219: /* Byte-Reverse Halfword */
4986 case 220: /* Centrifuge Doubleword */
4987 case 378: /* Population count words */
4988 case 506: /* Population count doublewords */
4989 case 154: /* Parity Word */
4990 case 186: /* Parity Doubleword */
4991 case 252: /* Bit Permute Doubleword */
4992 case 282: /* Convert Declets To Binary Coded Decimal */
4993 case 314: /* Convert Binary Coded Decimal To Declets */
4994 case 508: /* Compare bytes */
4995 case 307: /* Move From VSR Lower Doubleword */
4996 case 571: /* Count Trailing Zeros Doubleword under bit Mask */
4997 record_full_arch_list_add_reg (regcache
,
4998 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5001 /* These write CR and optional RA. */
5002 case 792: /* Shift Right Algebraic Word */
5003 case 794: /* Shift Right Algebraic Doubleword */
5004 case 824: /* Shift Right Algebraic Word Immediate */
5005 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
5006 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
5007 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5008 record_full_arch_list_add_reg (regcache
,
5009 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5011 case 0: /* Compare */
5012 case 32: /* Compare logical */
5013 case 144: /* Move To Condition Register Fields */
5014 /* Move To One Condition Register Field */
5015 case 192: /* Compare Ranged Byte */
5016 case 224: /* Compare Equal Byte */
5017 case 576: /* Move XER to CR Extended */
5018 case 902: /* Paste (should always fail due to single-stepping and
5019 the memory location might not be accessible, so
5021 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5024 /* These write to RT. Update RA if 'update indexed.' */
5025 case 53: /* Load Doubleword with Update Indexed */
5026 case 119: /* Load Byte and Zero with Update Indexed */
5027 case 311: /* Load Halfword and Zero with Update Indexed */
5028 case 55: /* Load Word and Zero with Update Indexed */
5029 case 375: /* Load Halfword Algebraic with Update Indexed */
5030 case 373: /* Load Word Algebraic with Update Indexed */
5031 record_full_arch_list_add_reg (regcache
,
5032 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5034 case 21: /* Load Doubleword Indexed */
5035 case 52: /* Load Byte And Reserve Indexed */
5036 case 116: /* Load Halfword And Reserve Indexed */
5037 case 20: /* Load Word And Reserve Indexed */
5038 case 84: /* Load Doubleword And Reserve Indexed */
5039 case 87: /* Load Byte and Zero Indexed */
5040 case 279: /* Load Halfword and Zero Indexed */
5041 case 23: /* Load Word and Zero Indexed */
5042 case 343: /* Load Halfword Algebraic Indexed */
5043 case 341: /* Load Word Algebraic Indexed */
5044 case 790: /* Load Halfword Byte-Reverse Indexed */
5045 case 534: /* Load Word Byte-Reverse Indexed */
5046 case 532: /* Load Doubleword Byte-Reverse Indexed */
5047 case 582: /* Load Word Atomic */
5048 case 614: /* Load Doubleword Atomic */
5049 case 265: /* Modulo Unsigned Doubleword */
5050 case 777: /* Modulo Signed Doubleword */
5051 case 267: /* Modulo Unsigned Word */
5052 case 779: /* Modulo Signed Word */
5053 record_full_arch_list_add_reg (regcache
,
5054 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5057 case 597: /* Load String Word Immediate */
5058 case 533: /* Load String Word Indexed */
5067 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5068 nr
= PPC_XER_NB (xer
);
5073 /* If n=0, the contents of register RT are undefined. */
5077 for (i
= 0; i
< nr
; i
++)
5078 record_full_arch_list_add_reg (regcache
,
5079 tdep
->ppc_gp0_regnum
5080 + ((PPC_RT (insn
) + i
) & 0x1f));
5083 case 276: /* Load Quadword And Reserve Indexed */
5084 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5085 record_full_arch_list_add_reg (regcache
, tmp
);
5086 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5089 /* These write VRT. */
5090 case 6: /* Load Vector for Shift Left Indexed */
5091 case 38: /* Load Vector for Shift Right Indexed */
5092 case 7: /* Load Vector Element Byte Indexed */
5093 case 39: /* Load Vector Element Halfword Indexed */
5094 case 71: /* Load Vector Element Word Indexed */
5095 case 103: /* Load Vector Indexed */
5096 case 359: /* Load Vector Indexed LRU */
5097 record_full_arch_list_add_reg (regcache
,
5098 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
5101 /* These write FRT. Update RA if 'update indexed.' */
5102 case 567: /* Load Floating-Point Single with Update Indexed */
5103 case 631: /* Load Floating-Point Double with Update Indexed */
5104 record_full_arch_list_add_reg (regcache
,
5105 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5107 case 535: /* Load Floating-Point Single Indexed */
5108 case 599: /* Load Floating-Point Double Indexed */
5109 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
5110 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
5111 record_full_arch_list_add_reg (regcache
,
5112 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5115 case 791: /* Load Floating-Point Double Pair Indexed */
5116 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5117 record_full_arch_list_add_reg (regcache
, tmp
);
5118 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5121 /* These write to destination register PPC_XT. */
5122 case 179: /* Move To VSR Doubleword */
5123 case 211: /* Move To VSR Word Algebraic */
5124 case 243: /* Move To VSR Word and Zero */
5125 case 588: /* Load VSX Scalar Doubleword Indexed */
5126 case 524: /* Load VSX Scalar Single-Precision Indexed */
5127 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
5128 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
5129 case 13: /* Load VSX Vector Rightmost Byte Indexed */
5130 case 45: /* Load VSX Vector Rightmost Halfword Indexed */
5131 case 77: /* Load VSX Vector Rightmost Word Indexed */
5132 case 109: /* Load VSX Vector Rightmost Doubleword Indexed */
5133 case 844: /* Load VSX Vector Doubleword*2 Indexed */
5134 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
5135 case 780: /* Load VSX Vector Word*4 Indexed */
5136 case 268: /* Load VSX Vector Indexed */
5137 case 364: /* Load VSX Vector Word & Splat Indexed */
5138 case 812: /* Load VSX Vector Halfword*8 Indexed */
5139 case 876: /* Load VSX Vector Byte*16 Indexed */
5140 case 269: /* Load VSX Vector with Length */
5141 case 301: /* Load VSX Vector Left-justified with Length */
5142 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
5143 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
5144 case 403: /* Move To VSR Word & Splat */
5145 case 435: /* Move To VSR Double Doubleword */
5146 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5149 case 333: /* Load VSX Vector Paired Indexed */
5150 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
));
5151 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn
) + 1);
5154 /* These write RA. Update CR if RC is set. */
5155 case 24: /* Shift Left Word */
5156 case 26: /* Count Leading Zeros Word */
5157 case 27: /* Shift Left Doubleword */
5159 case 58: /* Count Leading Zeros Doubleword */
5160 case 60: /* AND with Complement */
5162 case 284: /* Equivalent */
5164 case 476: /* NAND */
5165 case 412: /* OR with Complement */
5167 case 536: /* Shift Right Word */
5168 case 539: /* Shift Right Doubleword */
5169 case 922: /* Extend Sign Halfword */
5170 case 954: /* Extend Sign Byte */
5171 case 986: /* Extend Sign Word */
5172 case 538: /* Count Trailing Zeros Word */
5173 case 570: /* Count Trailing Zeros Doubleword */
5174 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
5175 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
5177 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
5178 && (PPC_RS (insn
) == PPC_RA (insn
))
5179 && (PPC_RA (insn
) == PPC_RB (insn
))
5182 /* or Rx,Rx,Rx alters PRI in PPR. */
5183 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5188 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5189 record_full_arch_list_add_reg (regcache
,
5190 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5194 case 181: /* Store Doubleword with Update Indexed */
5195 case 183: /* Store Word with Update Indexed */
5196 case 247: /* Store Byte with Update Indexed */
5197 case 439: /* Store Half Word with Update Indexed */
5198 case 695: /* Store Floating-Point Single with Update Indexed */
5199 case 759: /* Store Floating-Point Double with Update Indexed */
5200 record_full_arch_list_add_reg (regcache
,
5201 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5203 case 135: /* Store Vector Element Byte Indexed */
5204 case 167: /* Store Vector Element Halfword Indexed */
5205 case 199: /* Store Vector Element Word Indexed */
5206 case 231: /* Store Vector Indexed */
5207 case 487: /* Store Vector Indexed LRU */
5208 case 716: /* Store VSX Scalar Doubleword Indexed */
5209 case 140: /* Store VSX Scalar as Integer Word Indexed */
5210 case 652: /* Store VSX Scalar Single-Precision Indexed */
5211 case 972: /* Store VSX Vector Doubleword*2 Indexed */
5212 case 908: /* Store VSX Vector Word*4 Indexed */
5213 case 149: /* Store Doubleword Indexed */
5214 case 151: /* Store Word Indexed */
5215 case 215: /* Store Byte Indexed */
5216 case 407: /* Store Half Word Indexed */
5217 case 694: /* Store Byte Conditional Indexed */
5218 case 726: /* Store Halfword Conditional Indexed */
5219 case 150: /* Store Word Conditional Indexed */
5220 case 214: /* Store Doubleword Conditional Indexed */
5221 case 182: /* Store Quadword Conditional Indexed */
5222 case 662: /* Store Word Byte-Reverse Indexed */
5223 case 918: /* Store Halfword Byte-Reverse Indexed */
5224 case 660: /* Store Doubleword Byte-Reverse Indexed */
5225 case 663: /* Store Floating-Point Single Indexed */
5226 case 727: /* Store Floating-Point Double Indexed */
5227 case 919: /* Store Floating-Point Double Pair Indexed */
5228 case 983: /* Store Floating-Point as Integer Word Indexed */
5229 case 396: /* Store VSX Vector Indexed */
5230 case 940: /* Store VSX Vector Halfword*8 Indexed */
5231 case 1004: /* Store VSX Vector Byte*16 Indexed */
5232 case 909: /* Store VSX Scalar as Integer Byte Indexed */
5233 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
5234 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
5235 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5238 if (PPC_RA (insn
) != 0)
5239 regcache_raw_read_unsigned (regcache
,
5240 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5241 regcache_raw_read_unsigned (regcache
,
5242 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5247 case 183: /* Store Word with Update Indexed */
5248 case 199: /* Store Vector Element Word Indexed */
5249 case 140: /* Store VSX Scalar as Integer Word Indexed */
5250 case 652: /* Store VSX Scalar Single-Precision Indexed */
5251 case 151: /* Store Word Indexed */
5252 case 150: /* Store Word Conditional Indexed */
5253 case 662: /* Store Word Byte-Reverse Indexed */
5254 case 663: /* Store Floating-Point Single Indexed */
5255 case 695: /* Store Floating-Point Single with Update Indexed */
5256 case 983: /* Store Floating-Point as Integer Word Indexed */
5259 case 247: /* Store Byte with Update Indexed */
5260 case 135: /* Store Vector Element Byte Indexed */
5261 case 215: /* Store Byte Indexed */
5262 case 694: /* Store Byte Conditional Indexed */
5263 case 909: /* Store VSX Scalar as Integer Byte Indexed */
5266 case 439: /* Store Halfword with Update Indexed */
5267 case 167: /* Store Vector Element Halfword Indexed */
5268 case 407: /* Store Halfword Indexed */
5269 case 726: /* Store Halfword Conditional Indexed */
5270 case 918: /* Store Halfword Byte-Reverse Indexed */
5271 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
5274 case 181: /* Store Doubleword with Update Indexed */
5275 case 716: /* Store VSX Scalar Doubleword Indexed */
5276 case 149: /* Store Doubleword Indexed */
5277 case 214: /* Store Doubleword Conditional Indexed */
5278 case 660: /* Store Doubleword Byte-Reverse Indexed */
5279 case 727: /* Store Floating-Point Double Indexed */
5280 case 759: /* Store Floating-Point Double with Update Indexed */
5283 case 972: /* Store VSX Vector Doubleword*2 Indexed */
5284 case 908: /* Store VSX Vector Word*4 Indexed */
5285 case 182: /* Store Quadword Conditional Indexed */
5286 case 231: /* Store Vector Indexed */
5287 case 487: /* Store Vector Indexed LRU */
5288 case 919: /* Store Floating-Point Double Pair Indexed */
5289 case 396: /* Store VSX Vector Indexed */
5290 case 940: /* Store VSX Vector Halfword*8 Indexed */
5291 case 1004: /* Store VSX Vector Byte*16 Indexed */
5298 /* Align address for Store Vector instructions. */
5301 case 167: /* Store Vector Element Halfword Indexed */
5305 case 199: /* Store Vector Element Word Indexed */
5309 case 231: /* Store Vector Indexed */
5310 case 487: /* Store Vector Indexed LRU */
5315 record_full_arch_list_add_mem (ea
, size
);
5318 case 141: /* Store VSX Vector Rightmost Byte Indexed */
5319 case 173: /* Store VSX Vector Rightmost Halfword Indexed */
5320 case 205: /* Store VSX Vector Rightmost Word Indexed */
5321 case 237: /* Store VSX Vector Rightmost Doubleword Indexed */
5334 if (PPC_RA (insn
) != 0)
5335 regcache_raw_read_unsigned (regcache
,
5336 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5337 regcache_raw_read_unsigned (regcache
,
5338 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5340 record_full_arch_list_add_mem (ea
, nb
);
5343 case 397: /* Store VSX Vector with Length */
5344 case 429: /* Store VSX Vector Left-justified with Length */
5346 if (PPC_RA (insn
) != 0)
5347 regcache_raw_read_unsigned (regcache
,
5348 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5350 regcache_raw_read_unsigned (regcache
,
5351 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5352 /* Store up to 16 bytes. */
5353 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
5355 record_full_arch_list_add_mem (ea
, nb
);
5358 case 461: /* Store VSX Vector Paired Indexed */
5360 if (PPC_RA (insn
) != 0)
5361 regcache_raw_read_unsigned (regcache
,
5362 tdep
->ppc_gp0_regnum
5363 + PPC_RA (insn
), &ea
);
5364 regcache_raw_read_unsigned (regcache
,
5365 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5367 record_full_arch_list_add_mem (ea
, 32);
5371 case 710: /* Store Word Atomic */
5372 case 742: /* Store Doubleword Atomic */
5374 if (PPC_RA (insn
) != 0)
5375 regcache_raw_read_unsigned (regcache
,
5376 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5380 case 710: /* Store Word Atomic */
5383 case 742: /* Store Doubleword Atomic */
5389 record_full_arch_list_add_mem (ea
, size
);
5392 case 725: /* Store String Word Immediate */
5394 if (PPC_RA (insn
) != 0)
5395 regcache_raw_read_unsigned (regcache
,
5396 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5403 record_full_arch_list_add_mem (ea
, nb
);
5407 case 661: /* Store String Word Indexed */
5409 if (PPC_RA (insn
) != 0)
5410 regcache_raw_read_unsigned (regcache
,
5411 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5414 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5415 nb
= PPC_XER_NB (xer
);
5419 regcache_raw_read_unsigned (regcache
,
5420 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
5423 record_full_arch_list_add_mem (ea
, nb
);
5428 case 467: /* Move To Special Purpose Register */
5429 switch (PPC_SPR (insn
))
5432 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5435 if (tdep
->ppc_dscr_regnum
>= 0)
5436 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5439 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5442 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5444 case 256: /* VRSAVE */
5445 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5448 if (tdep
->ppc_tar_regnum
>= 0)
5449 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5453 if (tdep
->ppc_ppr_regnum
>= 0)
5454 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5460 case 147: /* Move To Split Little Endian */
5461 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5464 case 512: /* Move to Condition Register from XER */
5465 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5466 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5469 case 4: /* Trap Word */
5470 case 68: /* Trap Doubleword */
5471 case 430: /* Clear BHRB */
5472 case 598: /* Synchronize */
5473 case 62: /* Wait for Interrupt */
5475 case 22: /* Instruction Cache Block Touch */
5476 case 854: /* Enforce In-order Execution of I/O */
5477 case 246: /* Data Cache Block Touch for Store */
5478 case 54: /* Data Cache Block Store */
5479 case 86: /* Data Cache Block Flush */
5480 case 278: /* Data Cache Block Touch */
5481 case 758: /* Data Cache Block Allocate */
5482 case 982: /* Instruction Cache Block Invalidate */
5483 case 774: /* Copy */
5484 case 838: /* CP_Abort */
5487 case 654: /* Transaction Begin */
5488 case 686: /* Transaction End */
5489 case 750: /* Transaction Suspend or Resume */
5490 case 782: /* Transaction Abort Word Conditional */
5491 case 814: /* Transaction Abort Doubleword Conditional */
5492 case 846: /* Transaction Abort Word Conditional Immediate */
5493 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5494 case 910: /* Transaction Abort */
5495 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5497 case 718: /* Transaction Check */
5498 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5501 case 1014: /* Data Cache Block set to Zero */
5502 if (target_auxv_search (AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5504 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5507 if (PPC_RA (insn
) != 0)
5508 regcache_raw_read_unsigned (regcache
,
5509 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5510 regcache_raw_read_unsigned (regcache
,
5511 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5512 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5513 record_full_arch_list_add_mem (ea
, at_dcsz
);
5517 if (ppc_process_record_op31_177 (gdbarch
, regcache
, insn
) == 0)
5522 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
5523 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5527 /* Parse and record instructions of primary opcode-59 at ADDR.
5528 Return 0 if successful. */
5531 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5532 CORE_ADDR addr
, uint32_t insn
)
5534 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5535 int ext
= PPC_EXTOP (insn
);
5536 int at
= PPC_FIELD (insn
, 6, 3);
5540 case 18: /* Floating Divide */
5541 case 20: /* Floating Subtract */
5542 case 21: /* Floating Add */
5543 case 22: /* Floating Square Root */
5544 case 24: /* Floating Reciprocal Estimate */
5545 case 25: /* Floating Multiply */
5546 case 26: /* Floating Reciprocal Square Root Estimate */
5547 case 28: /* Floating Multiply-Subtract */
5548 case 29: /* Floating Multiply-Add */
5549 case 30: /* Floating Negative Multiply-Subtract */
5550 case 31: /* Floating Negative Multiply-Add */
5551 record_full_arch_list_add_reg (regcache
,
5552 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5554 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5555 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5560 /* MMA instructions, keep looking. */
5561 switch (ext
>> 2) /* Additional opcode field is upper 8-bits of ext */
5563 case 3: /* VSX Vector 8-bit Signed/Unsigned Integer GER, xvi8ger4 */
5564 case 2: /* VSX Vector 8-bit Signed/Unsigned Integer GER Positive
5565 multiply, Positive accumulate, xvi8ger4pp */
5567 case 99: /* VSX Vector 8-bit Signed/Unsigned Integer GER with
5568 Saturate Positive multiply, Positive accumulate,
5571 case 35: /* VSX Vector 4-bit Signed Integer GER, xvi4ger8 */
5572 case 34: /* VSX Vector 4-bit Signed Integer GER Positive multiply,
5573 Positive accumulate, xvi4ger8pp */
5575 case 75: /* VSX Vector 16-bit Signed Integer GER, xvi16ger2 */
5576 case 107: /* VSX Vector 16-bit Signed Integer GER Positive multiply,
5577 Positive accumulate, xvi16ger2pp */
5579 case 43: /* VSX Vector 16-bit Signed Integer GER with Saturation,
5581 case 42: /* VSX Vector 16-bit Signed Integer GER with Saturation
5582 Positive multiply, Positive accumulate, xvi16ger2spp */
5583 ppc_record_ACC_fpscr (regcache
, tdep
, at
, false);
5586 case 19: /* VSX Vector 16-bit Floating-Point GER, xvf16ger2 */
5587 case 18: /* VSX Vector 16-bit Floating-Point GER Positive multiply,
5588 Positive accumulate, xvf16ger2pp */
5589 case 146: /* VSX Vector 16-bit Floating-Point GER Positive multiply,
5590 Negative accumulate, xvf16ger2pn */
5591 case 82: /* VSX Vector 16-bit Floating-Point GER Negative multiply,
5592 Positive accumulate, xvf16ger2np */
5593 case 210: /* VSX Vector 16-bit Floating-Point GER Negative multiply,
5594 Negative accumulate, xvf16ger2nn */
5596 case 27: /* VSX Vector 32-bit Floating-Point GER, xvf32ger */
5597 case 26: /* VSX Vector 32-bit Floating-Point GER Positive multiply,
5598 Positive accumulate, xvf32gerpp */
5599 case 154: /* VSX Vector 32-bit Floating-Point GER Positive multiply,
5600 Negative accumulate, xvf32gerpn */
5601 case 90: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
5602 Positive accumulate, xvf32gernp */
5603 case 218: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
5604 Negative accumulate, xvf32gernn */
5606 case 59: /* VSX Vector 64-bit Floating-Point GER, pmxvf64ger */
5607 case 58: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
5608 Positive accumulate, xvf64gerpp */
5609 case 186: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
5610 Negative accumulate, xvf64gerpn */
5611 case 122: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
5612 Positive accumulate, xvf64gernp */
5613 case 250: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
5614 Negative accumulate, pmxvf64gernn */
5616 case 51: /* VSX Vector bfloat16 GER, xvbf16ger2 */
5617 case 50: /* VSX Vector bfloat16 GER Positive multiply,
5618 Positive accumulate, xvbf16ger2pp */
5619 case 178: /* VSX Vector bfloat16 GER Positive multiply,
5620 Negative accumulate, xvbf16ger2pn */
5621 case 114: /* VSX Vector bfloat16 GER Negative multiply,
5622 Positive accumulate, xvbf16ger2np */
5623 case 242: /* VSX Vector bfloat16 GER Negative multiply,
5624 Negative accumulate, xvbf16ger2nn */
5625 ppc_record_ACC_fpscr (regcache
, tdep
, at
, true);
5631 case 2: /* DFP Add */
5632 case 3: /* DFP Quantize */
5633 case 34: /* DFP Multiply */
5634 case 35: /* DFP Reround */
5635 case 67: /* DFP Quantize Immediate */
5636 case 99: /* DFP Round To FP Integer With Inexact */
5637 case 227: /* DFP Round To FP Integer Without Inexact */
5638 case 258: /* DFP Convert To DFP Long! */
5639 case 290: /* DFP Convert To Fixed */
5640 case 514: /* DFP Subtract */
5641 case 546: /* DFP Divide */
5642 case 770: /* DFP Round To DFP Short! */
5643 case 802: /* DFP Convert From Fixed */
5644 case 834: /* DFP Encode BCD To DPD */
5646 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5647 record_full_arch_list_add_reg (regcache
,
5648 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5649 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5652 case 130: /* DFP Compare Ordered */
5653 case 162: /* DFP Test Exponent */
5654 case 194: /* DFP Test Data Class */
5655 case 226: /* DFP Test Data Group */
5656 case 642: /* DFP Compare Unordered */
5657 case 674: /* DFP Test Significance */
5658 case 675: /* DFP Test Significance Immediate */
5659 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5660 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5663 case 66: /* DFP Shift Significand Left Immediate */
5664 case 98: /* DFP Shift Significand Right Immediate */
5665 case 322: /* DFP Decode DPD To BCD */
5666 case 354: /* DFP Extract Biased Exponent */
5667 case 866: /* DFP Insert Biased Exponent */
5668 record_full_arch_list_add_reg (regcache
,
5669 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5671 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5674 case 846: /* Floating Convert From Integer Doubleword Single */
5675 case 974: /* Floating Convert From Integer Doubleword Unsigned
5677 record_full_arch_list_add_reg (regcache
,
5678 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5680 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5681 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5686 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
5687 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5691 /* Parse and record an XX2-Form instruction with opcode 60 at ADDR. The
5692 word instruction is an argument insn. Return 0 if successful. */
5695 ppc_process_record_op60_XX2 (struct gdbarch
*gdbarch
,
5696 struct regcache
*regcache
,
5697 CORE_ADDR addr
, uint32_t insn
)
5699 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5700 int RA_opcode
= PPC_RA(insn
);
5704 case 2: /* VSX Vector Test Least-Significant Bit by Byte */
5705 case 25: /* VSX Vector round and Convert Single-Precision format
5706 to Half-Precision format. Only changes the CR
5708 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5710 case 17: /* VSX Vector Convert with round Single-Precision
5711 to bfloat16 format */
5712 case 24: /* VSX Vector Convert Half-Precision format to
5713 Single-Precision format */
5714 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5716 case 0: /* VSX Vector Extract Exponent Double-Precision */
5717 case 1: /* VSX Vector Extract Significand Double-Precision */
5718 case 7: /* VSX Vector Byte-Reverse Halfword */
5719 case 8: /* VSX Vector Extract Exponent Single-Precision */
5720 case 9: /* VSX Vector Extract Significand Single-Precision */
5721 case 15: /* VSX Vector Byte-Reverse Word */
5722 case 16: /* VSX Vector Convert bfloat16 to Single-Precision
5723 format Non-signaling */
5724 case 23: /* VSX Vector Byte-Reverse Doubleword */
5725 case 31: /* VSX Vector Byte-Reverse Quadword */
5726 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5733 /* Parse and record instructions of primary opcode-60 at ADDR.
5734 Return 0 if successful. */
5737 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5738 CORE_ADDR addr
, uint32_t insn
)
5740 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
5741 int ext
= PPC_EXTOP (insn
);
5745 case 0: /* VSX Scalar Add Single-Precision */
5746 case 32: /* VSX Scalar Add Double-Precision */
5747 case 24: /* VSX Scalar Divide Single-Precision */
5748 case 56: /* VSX Scalar Divide Double-Precision */
5749 case 176: /* VSX Scalar Copy Sign Double-Precision */
5750 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5751 case 41: /* ditto */
5752 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5754 case 160: /* VSX Scalar Maximum Double-Precision */
5755 case 168: /* VSX Scalar Minimum Double-Precision */
5756 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5757 case 57: /* ditto */
5758 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5759 case 25: /* ditto */
5760 case 48: /* VSX Scalar Multiply Double-Precision */
5761 case 16: /* VSX Scalar Multiply Single-Precision */
5762 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5763 case 169: /* ditto */
5764 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5765 case 137: /* ditto */
5766 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5767 case 185: /* ditto */
5768 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5769 case 153: /* ditto */
5770 case 40: /* VSX Scalar Subtract Double-Precision */
5771 case 8: /* VSX Scalar Subtract Single-Precision */
5772 case 96: /* VSX Vector Add Double-Precision */
5773 case 64: /* VSX Vector Add Single-Precision */
5774 case 120: /* VSX Vector Divide Double-Precision */
5775 case 88: /* VSX Vector Divide Single-Precision */
5776 case 97: /* VSX Vector Multiply-Add Double-Precision */
5777 case 105: /* ditto */
5778 case 65: /* VSX Vector Multiply-Add Single-Precision */
5779 case 73: /* ditto */
5780 case 224: /* VSX Vector Maximum Double-Precision */
5781 case 192: /* VSX Vector Maximum Single-Precision */
5782 case 232: /* VSX Vector Minimum Double-Precision */
5783 case 200: /* VSX Vector Minimum Single-Precision */
5784 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5785 case 121: /* ditto */
5786 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5787 case 89: /* ditto */
5788 case 112: /* VSX Vector Multiply Double-Precision */
5789 case 80: /* VSX Vector Multiply Single-Precision */
5790 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5791 case 233: /* ditto */
5792 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5793 case 201: /* ditto */
5794 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5795 case 249: /* ditto */
5796 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5797 case 217: /* ditto */
5798 case 104: /* VSX Vector Subtract Double-Precision */
5799 case 72: /* VSX Vector Subtract Single-Precision */
5800 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5801 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5802 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5803 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5804 case 3: /* VSX Scalar Compare Equal Double-Precision */
5805 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5806 case 19: /* VSX Scalar Compare Greater Than or Equal
5808 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5810 case 240: /* VSX Vector Copy Sign Double-Precision */
5811 case 208: /* VSX Vector Copy Sign Single-Precision */
5812 case 130: /* VSX Logical AND */
5813 case 138: /* VSX Logical AND with Complement */
5814 case 186: /* VSX Logical Equivalence */
5815 case 178: /* VSX Logical NAND */
5816 case 170: /* VSX Logical OR with Complement */
5817 case 162: /* VSX Logical NOR */
5818 case 146: /* VSX Logical OR */
5819 case 154: /* VSX Logical XOR */
5820 case 18: /* VSX Merge High Word */
5821 case 50: /* VSX Merge Low Word */
5822 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5823 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5824 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5825 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5826 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5827 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5828 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5829 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5830 case 216: /* VSX Vector Insert Exponent Single-Precision */
5831 case 248: /* VSX Vector Insert Exponent Double-Precision */
5832 case 26: /* VSX Vector Permute */
5833 case 58: /* VSX Vector Permute Right-indexed */
5834 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5835 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5836 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5837 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5838 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5841 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5842 case 125: /* VSX Vector Test for software Divide Double-Precision */
5843 case 93: /* VSX Vector Test for software Divide Single-Precision */
5844 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5847 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5848 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5849 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5850 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5851 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5855 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5857 case 99: /* VSX Vector Compare Equal To Double-Precision */
5858 case 67: /* VSX Vector Compare Equal To Single-Precision */
5859 case 115: /* VSX Vector Compare Greater Than or
5860 Equal To Double-Precision */
5861 case 83: /* VSX Vector Compare Greater Than or
5862 Equal To Single-Precision */
5863 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5864 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5866 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5867 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5868 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5874 case 265: /* VSX Scalar round Double-Precision to
5875 Single-Precision and Convert to
5876 Single-Precision format */
5877 case 344: /* VSX Scalar truncate Double-Precision to
5878 Integer and Convert to Signed Integer
5879 Doubleword format with Saturate */
5880 case 88: /* VSX Scalar truncate Double-Precision to
5881 Integer and Convert to Signed Integer Word
5882 Format with Saturate */
5883 case 328: /* VSX Scalar truncate Double-Precision integer
5884 and Convert to Unsigned Integer Doubleword
5885 Format with Saturate */
5886 case 72: /* VSX Scalar truncate Double-Precision to
5887 Integer and Convert to Unsigned Integer Word
5888 Format with Saturate */
5889 case 329: /* VSX Scalar Convert Single-Precision to
5890 Double-Precision format */
5891 case 376: /* VSX Scalar Convert Signed Integer
5892 Doubleword to floating-point format and
5893 Round to Double-Precision format */
5894 case 312: /* VSX Scalar Convert Signed Integer
5895 Doubleword to floating-point format and
5896 round to Single-Precision */
5897 case 360: /* VSX Scalar Convert Unsigned Integer
5898 Doubleword to floating-point format and
5899 Round to Double-Precision format */
5900 case 296: /* VSX Scalar Convert Unsigned Integer
5901 Doubleword to floating-point format and
5902 Round to Single-Precision */
5903 case 73: /* VSX Scalar Round to Double-Precision Integer
5904 Using Round to Nearest Away */
5905 case 107: /* VSX Scalar Round to Double-Precision Integer
5906 Exact using Current rounding mode */
5907 case 121: /* VSX Scalar Round to Double-Precision Integer
5908 Using Round toward -Infinity */
5909 case 105: /* VSX Scalar Round to Double-Precision Integer
5910 Using Round toward +Infinity */
5911 case 89: /* VSX Scalar Round to Double-Precision Integer
5912 Using Round toward Zero */
5913 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5914 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5915 case 281: /* VSX Scalar Round to Single-Precision */
5916 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5918 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5920 case 75: /* VSX Scalar Square Root Double-Precision */
5921 case 11: /* VSX Scalar Square Root Single-Precision */
5922 case 393: /* VSX Vector round Double-Precision to
5923 Single-Precision and Convert to
5924 Single-Precision format */
5925 case 472: /* VSX Vector truncate Double-Precision to
5926 Integer and Convert to Signed Integer
5927 Doubleword format with Saturate */
5928 case 216: /* VSX Vector truncate Double-Precision to
5929 Integer and Convert to Signed Integer Word
5930 Format with Saturate */
5931 case 456: /* VSX Vector truncate Double-Precision to
5932 Integer and Convert to Unsigned Integer
5933 Doubleword format with Saturate */
5934 case 200: /* VSX Vector truncate Double-Precision to
5935 Integer and Convert to Unsigned Integer Word
5936 Format with Saturate */
5937 case 457: /* VSX Vector Convert Single-Precision to
5938 Double-Precision format */
5939 case 408: /* VSX Vector truncate Single-Precision to
5940 Integer and Convert to Signed Integer
5941 Doubleword format with Saturate */
5942 case 152: /* VSX Vector truncate Single-Precision to
5943 Integer and Convert to Signed Integer Word
5944 Format with Saturate */
5945 case 392: /* VSX Vector truncate Single-Precision to
5946 Integer and Convert to Unsigned Integer
5947 Doubleword format with Saturate */
5948 case 136: /* VSX Vector truncate Single-Precision to
5949 Integer and Convert to Unsigned Integer Word
5950 Format with Saturate */
5951 case 504: /* VSX Vector Convert and round Signed Integer
5952 Doubleword to Double-Precision format */
5953 case 440: /* VSX Vector Convert and round Signed Integer
5954 Doubleword to Single-Precision format */
5955 case 248: /* VSX Vector Convert Signed Integer Word to
5956 Double-Precision format */
5957 case 184: /* VSX Vector Convert and round Signed Integer
5958 Word to Single-Precision format */
5959 case 488: /* VSX Vector Convert and round Unsigned
5960 Integer Doubleword to Double-Precision format */
5961 case 424: /* VSX Vector Convert and round Unsigned
5962 Integer Doubleword to Single-Precision format */
5963 case 232: /* VSX Vector Convert and round Unsigned
5964 Integer Word to Double-Precision format */
5965 case 168: /* VSX Vector Convert and round Unsigned
5966 Integer Word to Single-Precision format */
5967 case 201: /* VSX Vector Round to Double-Precision
5968 Integer using round to Nearest Away */
5969 case 235: /* VSX Vector Round to Double-Precision
5970 Integer Exact using Current rounding mode */
5971 case 249: /* VSX Vector Round to Double-Precision
5972 Integer using round toward -Infinity */
5973 case 233: /* VSX Vector Round to Double-Precision
5974 Integer using round toward +Infinity */
5975 case 217: /* VSX Vector Round to Double-Precision
5976 Integer using round toward Zero */
5977 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5978 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5979 case 137: /* VSX Vector Round to Single-Precision Integer
5980 Using Round to Nearest Away */
5981 case 171: /* VSX Vector Round to Single-Precision Integer
5982 Exact Using Current rounding mode */
5983 case 185: /* VSX Vector Round to Single-Precision Integer
5984 Using Round toward -Infinity */
5985 case 169: /* VSX Vector Round to Single-Precision Integer
5986 Using Round toward +Infinity */
5987 case 153: /* VSX Vector Round to Single-Precision Integer
5988 Using round toward Zero */
5989 case 202: /* VSX Vector Reciprocal Square Root Estimate
5991 case 138: /* VSX Vector Reciprocal Square Root Estimate
5993 case 203: /* VSX Vector Square Root Double-Precision */
5994 case 139: /* VSX Vector Square Root Single-Precision */
5995 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5997 case 345: /* VSX Scalar Absolute Value Double-Precision */
5998 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5999 Vector Single-Precision format Non-signalling */
6000 case 331: /* VSX Scalar Convert Single-Precision to
6001 Double-Precision format Non-signalling */
6002 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
6003 case 377: /* VSX Scalar Negate Double-Precision */
6004 case 473: /* VSX Vector Absolute Value Double-Precision */
6005 case 409: /* VSX Vector Absolute Value Single-Precision */
6006 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
6007 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
6008 case 505: /* VSX Vector Negate Double-Precision */
6009 case 441: /* VSX Vector Negate Single-Precision */
6010 case 164: /* VSX Splat Word */
6011 case 165: /* VSX Vector Extract Unsigned Word */
6012 case 181: /* VSX Vector Insert Word */
6013 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6016 case 298: /* VSX Scalar Test Data Class Single-Precision */
6017 case 362: /* VSX Scalar Test Data Class Double-Precision */
6018 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6020 case 106: /* VSX Scalar Test for software Square Root
6022 case 234: /* VSX Vector Test for software Square Root
6024 case 170: /* VSX Vector Test for software Square Root
6026 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6030 switch (PPC_FIELD (insn
, 11, 5))
6032 case 0: /* VSX Scalar Extract Exponent Double-Precision */
6033 case 1: /* VSX Scalar Extract Significand Double-Precision */
6034 record_full_arch_list_add_reg (regcache
,
6035 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6037 case 16: /* VSX Scalar Convert Half-Precision format to
6038 Double-Precision format */
6039 case 17: /* VSX Scalar round & Convert Double-Precision format
6040 to Half-Precision format */
6041 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6042 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6048 if (ppc_process_record_op60_XX2 (gdbarch
, regcache
, addr
, insn
) != 0)
6056 if (PPC_FIELD (insn
, 11, 2) == 0) /* VSX Vector Splat Immediate Byte */
6058 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6061 if (PPC_FIELD (insn
, 11, 5) == 31) /* Load VSX Vector Special Value
6064 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6068 case 916: /* VSX Vector Generate PCV from Byte Mask */
6069 case 917: /* VSX Vector Generate PCV from Halfword Mask */
6070 case 948: /* VSX Vector Generate PCV from Word Mask */
6071 case 949: /* VSX Vector Generate PCV from Doubleword Mask */
6072 case 918: /* VSX Scalar Insert Exponent Double-Precision */
6073 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6077 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
6079 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6083 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6084 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
6088 /* Parse and record instructions of primary opcode-61 at ADDR.
6089 Return 0 if successful. */
6092 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6093 CORE_ADDR addr
, uint32_t insn
)
6095 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6101 case 0: /* Store Floating-Point Double Pair */
6102 case 2: /* Store VSX Scalar Doubleword */
6103 case 3: /* Store VSX Scalar Single */
6104 if (PPC_RA (insn
) != 0)
6105 regcache_raw_read_unsigned (regcache
,
6106 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6108 ea
+= PPC_DS (insn
) << 2;
6111 case 0: /* Store Floating-Point Double Pair */
6114 case 2: /* Store VSX Scalar Doubleword */
6117 case 3: /* Store VSX Scalar Single */
6123 record_full_arch_list_add_mem (ea
, size
);
6129 case 1: /* Load VSX Vector */
6130 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
6132 case 5: /* Store VSX Vector */
6133 if (PPC_RA (insn
) != 0)
6134 regcache_raw_read_unsigned (regcache
,
6135 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6137 ea
+= PPC_DQ (insn
) << 4;
6138 record_full_arch_list_add_mem (ea
, 16);
6142 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6143 "at %s.\n", insn
, paddress (gdbarch
, addr
));
6147 /* Parse and record instructions of primary opcode-63 at ADDR.
6148 Return 0 if successful. */
6151 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6152 CORE_ADDR addr
, uint32_t insn
)
6154 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6155 int ext
= PPC_EXTOP (insn
);
6160 case 18: /* Floating Divide */
6161 case 20: /* Floating Subtract */
6162 case 21: /* Floating Add */
6163 case 22: /* Floating Square Root */
6164 case 24: /* Floating Reciprocal Estimate */
6165 case 25: /* Floating Multiply */
6166 case 26: /* Floating Reciprocal Square Root Estimate */
6167 case 28: /* Floating Multiply-Subtract */
6168 case 29: /* Floating Multiply-Add */
6169 case 30: /* Floating Negative Multiply-Subtract */
6170 case 31: /* Floating Negative Multiply-Add */
6171 record_full_arch_list_add_reg (regcache
,
6172 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6174 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6175 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6178 case 23: /* Floating Select */
6179 record_full_arch_list_add_reg (regcache
,
6180 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6182 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6188 case 5: /* VSX Scalar Round to Quad-Precision Integer */
6189 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
6191 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6192 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6198 case 2: /* DFP Add Quad */
6199 case 3: /* DFP Quantize Quad */
6200 case 34: /* DFP Multiply Quad */
6201 case 35: /* DFP Reround Quad */
6202 case 67: /* DFP Quantize Immediate Quad */
6203 case 99: /* DFP Round To FP Integer With Inexact Quad */
6204 case 227: /* DFP Round To FP Integer Without Inexact Quad */
6205 case 258: /* DFP Convert To DFP Extended Quad */
6206 case 514: /* DFP Subtract Quad */
6207 case 546: /* DFP Divide Quad */
6208 case 770: /* DFP Round To DFP Long Quad */
6209 case 802: /* DFP Convert From Fixed Quad */
6210 case 834: /* DFP Encode BCD To DPD Quad */
6212 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6213 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
6214 record_full_arch_list_add_reg (regcache
, tmp
);
6215 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6216 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6219 case 130: /* DFP Compare Ordered Quad */
6220 case 162: /* DFP Test Exponent Quad */
6221 case 194: /* DFP Test Data Class Quad */
6222 case 226: /* DFP Test Data Group Quad */
6223 case 642: /* DFP Compare Unordered Quad */
6224 case 674: /* DFP Test Significance Quad */
6225 case 675: /* DFP Test Significance Immediate Quad */
6226 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6227 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6230 case 66: /* DFP Shift Significand Left Immediate Quad */
6231 case 98: /* DFP Shift Significand Right Immediate Quad */
6232 case 322: /* DFP Decode DPD To BCD Quad */
6233 case 866: /* DFP Insert Biased Exponent Quad */
6234 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
6235 record_full_arch_list_add_reg (regcache
, tmp
);
6236 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6238 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6241 case 290: /* DFP Convert To Fixed Quad */
6242 record_full_arch_list_add_reg (regcache
,
6243 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6245 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6246 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6249 case 354: /* DFP Extract Biased Exponent Quad */
6250 record_full_arch_list_add_reg (regcache
,
6251 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6253 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6256 case 12: /* Floating Round to Single-Precision */
6257 case 14: /* Floating Convert To Integer Word */
6258 case 15: /* Floating Convert To Integer Word
6259 with round toward Zero */
6260 case 142: /* Floating Convert To Integer Word Unsigned */
6261 case 143: /* Floating Convert To Integer Word Unsigned
6262 with round toward Zero */
6263 case 392: /* Floating Round to Integer Nearest */
6264 case 424: /* Floating Round to Integer Toward Zero */
6265 case 456: /* Floating Round to Integer Plus */
6266 case 488: /* Floating Round to Integer Minus */
6267 case 814: /* Floating Convert To Integer Doubleword */
6268 case 815: /* Floating Convert To Integer Doubleword
6269 with round toward Zero */
6270 case 846: /* Floating Convert From Integer Doubleword */
6271 case 942: /* Floating Convert To Integer Doubleword Unsigned */
6272 case 943: /* Floating Convert To Integer Doubleword Unsigned
6273 with round toward Zero */
6274 case 974: /* Floating Convert From Integer Doubleword Unsigned */
6275 record_full_arch_list_add_reg (regcache
,
6276 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6278 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6279 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6283 switch (PPC_FIELD (insn
, 11, 5))
6285 case 1: /* Move From FPSCR & Clear Enables */
6286 case 20: /* Move From FPSCR Control & set DRN */
6287 case 21: /* Move From FPSCR Control & set DRN Immediate */
6288 case 22: /* Move From FPSCR Control & set RN */
6289 case 23: /* Move From FPSCR Control & set RN Immediate */
6290 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6292 case 0: /* Move From FPSCR */
6293 case 24: /* Move From FPSCR Lightweight */
6294 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
6295 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6296 record_full_arch_list_add_reg (regcache
,
6297 tdep
->ppc_fp0_regnum
6303 case 8: /* Floating Copy Sign */
6304 case 40: /* Floating Negate */
6305 case 72: /* Floating Move Register */
6306 case 136: /* Floating Negative Absolute Value */
6307 case 264: /* Floating Absolute Value */
6308 record_full_arch_list_add_reg (regcache
,
6309 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6311 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6314 case 838: /* Floating Merge Odd Word */
6315 case 966: /* Floating Merge Even Word */
6316 record_full_arch_list_add_reg (regcache
,
6317 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6320 case 38: /* Move To FPSCR Bit 1 */
6321 case 70: /* Move To FPSCR Bit 0 */
6322 case 134: /* Move To FPSCR Field Immediate */
6323 case 711: /* Move To FPSCR Fields */
6325 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6326 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6329 case 0: /* Floating Compare Unordered */
6330 case 32: /* Floating Compare Ordered */
6331 case 64: /* Move to Condition Register from FPSCR */
6332 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
6333 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
6334 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
6335 case 708: /* VSX Scalar Test Data Class Quad-Precision */
6336 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6338 case 128: /* Floating Test for software Divide */
6339 case 160: /* Floating Test for software Square Root */
6340 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6343 case 4: /* VSX Scalar Add Quad-Precision */
6344 case 36: /* VSX Scalar Multiply Quad-Precision */
6345 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
6346 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
6347 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
6348 case 484: /* VSX Scalar Negative Multiply-Subtract
6350 case 516: /* VSX Scalar Subtract Quad-Precision */
6351 case 548: /* VSX Scalar Divide Quad-Precision */
6354 switch (PPC_FIELD (insn
, 11, 5))
6356 case 0: /* DFP Convert From Fixed Quadword Quad */
6357 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6359 record_full_arch_list_add_reg (regcache
,
6360 tdep
->ppc_fp0_regnum
6362 record_full_arch_list_add_reg (regcache
,
6363 tdep
->ppc_fp0_regnum
6364 + PPC_FRT (insn
) + 1);
6366 case 1: /* DFP Convert To Fixed Quadword Quad */
6367 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6368 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6373 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6375 case 68: /* VSX Scalar Compare Equal Quad-Precision */
6376 case 196: /* VSX Scalar Compare Greater Than or Equal
6378 case 228: /* VSX Scalar Compare Greater Than Quad-Precision */
6379 case 676: /* VSX Scalar Maximum Type-C Quad-Precision */
6380 case 740: /* VSX Scalar Minimum Type-C Quad-Precision */
6381 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6383 case 100: /* VSX Scalar Copy Sign Quad-Precision */
6384 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
6385 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6389 switch (PPC_FIELD (insn
, 11, 5))
6391 case 27: /* VSX Scalar Square Root Quad-Precision */
6392 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6394 case 0: /* VSX Scalar Absolute Quad-Precision */
6395 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
6396 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
6397 case 16: /* VSX Scalar Negate Quad-Precision */
6398 case 18: /* VSX Scalar Extract Significand Quad-Precision */
6399 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6405 switch (PPC_FIELD (insn
, 11, 5))
6407 case 0: /* VSX Scalar Convert with round to zero
6408 Quad-Precision to Unsigned Quadword */
6409 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
6410 to Unsigned Word format */
6411 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
6412 Quad-Precision format */
6413 case 3: /* VSX Scalar Convert with round
6414 Unsigned Quadword to Quad-Precision */
6415 case 8: /* VSX Scalar Convert with round to zero
6416 Quad-Precision to Signed Quadword */
6417 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
6418 to Signed Word format */
6419 case 10: /* VSX Scalar Convert Signed Doubleword format to
6420 Quad-Precision format */
6421 case 11: /* VSX Scalar Convert with round
6422 Signed Quadword to Quad-Precision */
6423 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
6424 to Unsigned Doubleword format */
6425 case 20: /* VSX Scalar round & Convert Quad-Precision format to
6426 Double-Precision format */
6427 case 22: /* VSX Scalar Convert Double-Precision format to
6428 Quad-Precision format */
6429 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
6430 to Signed Doubleword format */
6431 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
6432 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6437 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
6438 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
6442 /* Record the prefixed instructions with primary opcode 32. The arguments are
6443 the first 32-bits of the instruction (insn_prefix), and the second 32-bits
6444 of the instruction (insn_suffix). Return 0 on success. */
6447 ppc_process_record_prefix_op42 (struct gdbarch
*gdbarch
,
6448 struct regcache
*regcache
,
6449 uint32_t insn_prefix
, uint32_t insn_suffix
)
6451 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6452 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6453 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6460 case 0: /* Prefixed Load VSX Scalar Doubleword, plxsd */
6461 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn_suffix
) + 32);
6463 case 2: /* Prefixed Load Halfword Algebraic, plha */
6464 record_full_arch_list_add_reg (regcache
,
6465 tdep
->ppc_gp0_regnum
6466 + PPC_RT (insn_suffix
));
6474 /* Record the prefixed XX3-Form instructions with primary opcode 59. The
6475 arguments are the first 32-bits of the instruction (insn_prefix), and the
6476 second 32-bits of the instruction (insn_suffix). Return 0 on success. */
6479 ppc_process_record_prefix_op59_XX3 (struct gdbarch
*gdbarch
,
6480 struct regcache
*regcache
,
6481 uint32_t insn_prefix
, uint32_t insn_suffix
)
6483 int opcode
= PPC_FIELD (insn_suffix
, 21, 8);
6484 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6485 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6486 int at
= PPC_FIELD (insn_suffix
, 6, 3);
6487 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6494 case 35: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
6495 MMIRR, pmxvi4ger8 */
6496 case 34: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
6497 MMIRR, pmxvi4ger8pp */
6499 case 99: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6500 Integer GER with Saturate Positive multiply,
6501 Positive accumulate, xvi8ger4spp */
6503 case 3: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6504 Integer GER MMIRR, pmxvi8ger4 */
6505 case 2: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
6506 Integer GER Positive multiply, Positive accumulate
6507 MMIRR, pmxvi8ger4pp */
6509 case 75: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6510 GER MMIRR, pmxvi16ger2 */
6511 case 107: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6512 GER Positive multiply, Positive accumulate,
6515 case 43: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6516 GER with Saturation MMIRR, pmxvi16ger2s */
6517 case 42: /* Prefixed Masked VSX Vector 16-bit Signed Integer
6518 GER with Saturation Positive multiply, Positive
6519 accumulate MMIRR, pmxvi16ger2spp */
6520 ppc_record_ACC_fpscr (regcache
, tdep
, at
, false);
6523 case 19: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6524 GER MMIRR, pmxvf16ger2 */
6525 case 18: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6526 GER Positive multiply, Positive accumulate MMIRR,
6528 case 146: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6529 GER Positive multiply, Negative accumulate MMIRR,
6531 case 82: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6532 GER Negative multiply, Positive accumulate MMIRR,
6534 case 210: /* Prefixed Masked VSX Vector 16-bit Floating-Point
6535 GER Negative multiply, Negative accumulate MMIRR,
6538 case 27: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6539 GER MMIRR, pmxvf32ger */
6540 case 26: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6541 GER Positive multiply, Positive accumulate MMIRR,
6543 case 154: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6544 GER Positive multiply, Negative accumulate MMIRR,
6546 case 90: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6547 GER Negative multiply, Positive accumulate MMIRR,
6549 case 218: /* Prefixed Masked VSX Vector 32-bit Floating-Point
6550 GER Negative multiply, Negative accumulate MMIRR,
6553 case 59: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6554 GER MMIRR, pmxvf64ger */
6555 case 58: /* Floating-Point GER Positive multiply, Positive
6556 accumulate MMIRR, pmxvf64gerpp */
6557 case 186: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6558 GER Positive multiply, Negative accumulate MMIRR,
6560 case 122: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6561 GER Negative multiply, Positive accumulate MMIRR,
6563 case 250: /* Prefixed Masked VSX Vector 64-bit Floating-Point
6564 GER Negative multiply, Negative accumulate MMIRR,
6567 case 51: /* Prefixed Masked VSX Vector bfloat16 GER MMIRR,
6569 case 50: /* Prefixed Masked VSX Vector bfloat16 GER Positive
6570 multiply, Positive accumulate MMIRR,
6572 case 178: /* Prefixed Masked VSX Vector bfloat16 GER Positive
6573 multiply, Negative accumulate MMIRR,
6575 case 114: /* Prefixed Masked VSX Vector bfloat16 GER Negative
6576 multiply, Positive accumulate MMIRR,
6578 case 242: /* Prefixed Masked VSX Vector bfloat16 GER Negative
6579 multiply, Negative accumulate MMIRR,
6581 ppc_record_ACC_fpscr (regcache
, tdep
, at
, true);
6591 /* Record the prefixed store instructions. The arguments are the instruction
6592 address, the first 32-bits of the instruction(insn_prefix) and the following
6593 32-bits of the instruction (insn_suffix). Return 0 on success. */
6596 ppc_process_record_prefix_store (struct gdbarch
*gdbarch
,
6597 struct regcache
*regcache
,
6598 CORE_ADDR addr
, uint32_t insn_prefix
,
6599 uint32_t insn_suffix
)
6601 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6604 int R
= PPC_BIT (insn_prefix
, 11);
6605 int op6
= PPC_OP6 (insn_suffix
);
6609 if (PPC_RA (insn_suffix
) != 0)
6610 regcache_raw_read_unsigned (regcache
, tdep
->ppc_gp0_regnum
6611 + PPC_RA (insn_suffix
), &iaddr
);
6615 iaddr
= addr
; /* PC relative */
6621 size
= 1; /* store byte, pstb */
6624 size
= 2; /* store halfword, psth */
6628 size
= 4; /* store word, pstw, pstfs */
6632 size
= 8; /* store double word, pstd, pstfd */
6635 size
= 16; /* store quadword, pstq */
6640 iaddr
+= P_PPC_D (insn_prefix
, insn_suffix
);
6641 record_full_arch_list_add_mem (iaddr
, size
);
6645 /* Record the prefixed instructions with primary op code 32. The arguments
6646 are the first 32-bits of the instruction (insn_prefix) and the following
6647 32-bits of the instruction (insn_suffix). Return 0 on success. */
6650 ppc_process_record_prefix_op32 (struct gdbarch
*gdbarch
,
6651 struct regcache
*regcache
,
6652 uint32_t insn_prefix
, uint32_t insn_suffix
)
6654 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6655 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6656 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6657 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6663 switch (PPC_FIELD (insn_suffix
, 11, 3))
6665 case 0: /* VSX Vector Splat Immediate Word 8RR, xxsplti32dx */
6666 ppc_record_vsr (regcache
, tdep
, P_PPC_XT15 (insn_suffix
));
6670 switch (PPC_FIELD (insn_suffix
, 11, 4))
6672 case 2: /* VSX Vector Splat Immediate Double-Precision
6674 case 3: /* VSX Vector Splat Immediate Word 8RR, xxspltiw */
6675 ppc_record_vsr (regcache
, tdep
, P_PPC_XT15 (insn_suffix
));
6687 if (ST1
== 0) /* Prefixed Load Word and Zero, plwz */
6688 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
6689 + PPC_RT (insn_suffix
));
6700 /* Record the prefixed instructions with primary op code 33. The arguments
6701 are the first 32-bits of the instruction(insn_prefix) and the following
6702 32-bits of the instruction (insn_suffix). Return 0 on success. */
6705 ppc_process_record_prefix_op33 (struct gdbarch
*gdbarch
,
6706 struct regcache
*regcache
,
6707 uint32_t insn_prefix
, uint32_t insn_suffix
)
6709 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6710 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6711 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6716 switch (PPC_FIELD (insn_suffix
, 26, 2))
6718 case 0: /* VSX Vector Blend Variable Byte 8RR, xxblendvb */
6719 case 1: /* VSX Vector Blend Variable Halfword, xxblendvh */
6720 case 2: /* VSX Vector Blend Variable Word, xxblendvw */
6721 case 3: /* VSX Vector Blend Variable Doubleword, xxblendvd */
6722 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn_suffix
));
6737 /* Record the prefixed instructions with primary op code 34. The arguments
6738 are the first 32-bits of the instruction(insn_prefix) and the following
6739 32-bits of the instruction (insn_suffix). Return 0 on success. */
6742 ppc_process_record_prefix_op34 (struct gdbarch
*gdbarch
,
6743 struct regcache
*regcache
,
6744 uint32_t insn_prefix
, uint32_t insn_suffix
)
6746 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6747 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6748 int ST4
= PPC_FIELD (insn_prefix
, 8, 4);
6749 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6754 switch (PPC_FIELD (insn_suffix
, 26, 2))
6756 case 0: /* VSX Vector Permute Extended 8RR, xxpermx */
6757 case 1: /* VSX Vector Evaluate 8RR, xxeval */
6758 ppc_record_vsr (regcache
, tdep
, P_PPC_XT (insn_suffix
));
6769 if (ST1
== 0) /* Prefixed Load Word and Zero, plbz */
6770 record_full_arch_list_add_reg (regcache
,
6771 tdep
->ppc_gp0_regnum
6772 + PPC_RT (insn_suffix
));
6783 /* Record the prefixed VSX store, form DS, instructions. The arguments are the
6784 instruction address (addr), the first 32-bits of the instruction
6785 (insn_prefix) followed by the 32-bit instruction suffix (insn_suffix).
6786 Return 0 on success. */
6789 ppc_process_record_prefix_store_vsx_ds_form (struct gdbarch
*gdbarch
,
6790 struct regcache
*regcache
,
6792 uint32_t insn_prefix
,
6793 uint32_t insn_suffix
)
6795 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6798 int R
= PPC_BIT (insn_prefix
, 11);
6799 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6800 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6802 if ((type
== 0) && (ST1
== 0))
6806 if (PPC_RA (insn_suffix
) != 0)
6807 regcache_raw_read_unsigned (regcache
,
6808 tdep
->ppc_gp0_regnum
6809 + PPC_RA (insn_suffix
),
6814 ea
= addr
; /* PC relative */
6817 ea
+= P_PPC_D (insn_prefix
, insn_suffix
);
6818 switch (PPC_FIELD (insn_suffix
, 0, 6))
6820 case 46: /* Prefixed Store VSX Scalar Doubleword, pstxsd */
6823 case 47: /* Prefixed,Store VSX Scalar Single-Precision, pstxssp */
6829 record_full_arch_list_add_mem (ea
, size
);
6836 /* Record the prefixed VSX, form D, instructions. The arguments are the
6837 instruction address for PC-relative addresss (addr), the first 32-bits of
6838 the instruction (insn_prefix) and the following 32-bits of the instruction
6839 (insn_suffix). Return 0 on success. */
6842 ppc_process_record_prefix_vsx_d_form (struct gdbarch
*gdbarch
,
6843 struct regcache
*regcache
,
6845 uint32_t insn_prefix
,
6846 uint32_t insn_suffix
)
6848 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6851 int R
= PPC_BIT (insn_prefix
, 11);
6852 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6853 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6855 if ((type
== 0) && (ST1
== 0))
6857 switch (PPC_FIELD (insn_suffix
, 0, 5))
6859 case 25: /* Prefixed Load VSX Vector, plxv */
6860 ppc_record_vsr (regcache
, tdep
, P_PPC_XT5 (insn_prefix
));
6862 case 27: /* Prefixed Store VSX Vector 8LS, pstxv */
6867 if (PPC_RA (insn_suffix
) != 0)
6868 regcache_raw_read_unsigned (regcache
,
6869 tdep
->ppc_gp0_regnum
6870 + PPC_RA (insn_suffix
),
6875 ea
= addr
; /* PC relative */
6878 ea
+= P_PPC_D (insn_prefix
, insn_suffix
);
6879 record_full_arch_list_add_mem (ea
, size
);
6889 /* Parse the current instruction and record the values of the registers and
6890 memory that will be changed in current instruction to "record_arch_list".
6891 Return -1 if something wrong. */
6893 /* This handles the recording of the various prefix instructions. It takes
6894 the instruction address, the first 32-bits of the instruction (insn_prefix)
6895 and the following 32-bits of the instruction (insn_suffix). Return 0 on
6899 ppc_process_prefix_instruction (int insn_prefix
, int insn_suffix
,
6900 CORE_ADDR addr
, struct gdbarch
*gdbarch
,
6901 struct regcache
*regcache
)
6903 int type
= PPC_FIELD (insn_prefix
, 6, 2);
6904 int ST1
= PPC_FIELD (insn_prefix
, 8, 1);
6905 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
6908 /* D-form has uses a 5-bit opcode in the instruction suffix */
6909 if (ppc_process_record_prefix_vsx_d_form ( gdbarch
, regcache
, addr
,
6910 insn_prefix
, insn_suffix
) == 0)
6913 op6
= PPC_OP6 (insn_suffix
); /* 6-bit opcode in the instruction suffix */
6917 case 14: /* Prefixed Add Immediate, paddi */
6918 if ((type
== 2) && (ST1
== 0))
6919 record_full_arch_list_add_reg (regcache
,
6920 tdep
->ppc_gp0_regnum
6921 + PPC_RT (insn_suffix
));
6923 goto UNKNOWN_PREFIX_OP
;
6927 if (ppc_process_record_prefix_op32 (gdbarch
, regcache
,
6928 insn_prefix
, insn_suffix
) != 0)
6929 goto UNKNOWN_PREFIX_OP
;
6933 if (ppc_process_record_prefix_op33 (gdbarch
, regcache
,
6934 insn_prefix
, insn_suffix
) != 0)
6935 goto UNKNOWN_PREFIX_OP
;
6938 case 34: /* Prefixed Load Byte and Zero, plbz */
6939 if (ppc_process_record_prefix_op34 (gdbarch
, regcache
,
6940 insn_prefix
, insn_suffix
) != 0)
6941 goto UNKNOWN_PREFIX_OP
;
6943 case 40: /* Prefixed Load Halfword and Zero, plhz */
6944 if ((type
== 2) && (ST1
== 0))
6945 record_full_arch_list_add_reg (regcache
,
6946 tdep
->ppc_gp0_regnum
6947 + PPC_RT (insn_suffix
));
6949 goto UNKNOWN_PREFIX_OP
;
6954 case 36: /* Prefixed Store Word, pstw */
6955 case 38: /* Prefixed Store Byte, pstb */
6956 case 44: /* Prefixed Store Halfword, psth */
6957 case 52: /* Prefixed Store Floating-Point Single, pstfs */
6958 case 54: /* Prefixed Store Floating-Point Double, pstfd */
6959 case 60: /* Prefixed Store Quadword, pstq */
6960 case 61: /* Prefixed Store Doubleword, pstd */
6961 if (ppc_process_record_prefix_store (gdbarch
, regcache
, addr
,
6962 insn_prefix
, insn_suffix
) != 0)
6963 goto UNKNOWN_PREFIX_OP
;
6967 if (ppc_process_record_prefix_op42 (gdbarch
, regcache
,
6968 insn_prefix
, insn_suffix
) != 0)
6969 goto UNKNOWN_PREFIX_OP
;
6972 case 43: /* Prefixed Load VSX Scalar Single-Precision, plxssp */
6973 if ((type
== 0) && (ST1
== 0))
6974 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn_suffix
) + 32);
6976 goto UNKNOWN_PREFIX_OP
;
6981 if (ppc_process_record_prefix_store_vsx_ds_form (gdbarch
, regcache
, addr
,
6982 insn_prefix
, insn_suffix
) != 0)
6983 goto UNKNOWN_PREFIX_OP
;
6986 case 56: /* Prefixed Load Quadword, plq */
6988 if ((type
== 0) && (ST1
== 0))
6991 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn_suffix
) & ~1);
6992 record_full_arch_list_add_reg (regcache
, tmp
);
6993 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6996 goto UNKNOWN_PREFIX_OP
;
7000 case 41: /* Prefixed Load Word Algebraic, plwa */
7001 case 57: /* Prefixed Load Doubleword, pld */
7002 if ((type
== 0) && (ST1
== 0))
7003 record_full_arch_list_add_reg (regcache
,
7004 tdep
->ppc_gp0_regnum
7005 + PPC_RT (insn_suffix
));
7007 goto UNKNOWN_PREFIX_OP
;
7010 case 48: /* Prefixed Load Floating-Point Single, plfs */
7011 case 50: /* Prefixed Load Floating-Point Double, plfd */
7012 if ((type
== 2) && (ST1
== 0))
7013 record_full_arch_list_add_reg (regcache
,
7014 tdep
->ppc_fp0_regnum
7015 + PPC_FRT (insn_suffix
));
7017 goto UNKNOWN_PREFIX_OP
;
7020 case 58: /* Prefixed Load VSX Vector Paired, plxvp */
7021 if ((type
== 0) && (ST1
== 0))
7023 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn_suffix
));
7024 ppc_record_vsr (regcache
, tdep
, PPC_XTp (insn_suffix
) + 1);
7027 goto UNKNOWN_PREFIX_OP
;
7031 if (ppc_process_record_prefix_op59_XX3 (gdbarch
, regcache
, insn_prefix
,
7033 goto UNKNOWN_PREFIX_OP
;
7036 case 62: /* Prefixed Store VSX Vector Paired 8LS, pstxvp */
7037 if ((type
== 0) && (ST1
== 0))
7039 int R
= PPC_BIT (insn_prefix
, 11);
7044 if (PPC_RA (insn_suffix
) != 0)
7045 regcache_raw_read_unsigned (regcache
,
7046 tdep
->ppc_gp0_regnum
7047 + PPC_RA (insn_suffix
), &ea
);
7051 ea
= addr
; /* PC relative */
7054 ea
+= P_PPC_D (insn_prefix
, insn_suffix
) << 4;
7055 record_full_arch_list_add_mem (ea
, 32);
7058 goto UNKNOWN_PREFIX_OP
;
7063 gdb_printf (gdb_stdlog
,
7064 "Warning: Don't know how to record prefix instruction "
7065 "%08x %08x at %s, %d.\n",
7066 insn_prefix
, insn_suffix
, paddress (gdbarch
, addr
),
7072 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
7075 if (record_full_arch_list_add_end ())
7081 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7084 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
7085 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7086 uint32_t insn
, insn_suffix
;
7089 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
7090 op6
= PPC_OP6 (insn
);
7094 case 1: /* prefixed instruction */
7096 /* Get the lower 32-bits of the prefixed instruction. */
7097 insn_suffix
= read_memory_unsigned_integer (addr
+4, 4, byte_order
);
7098 return ppc_process_prefix_instruction (insn
, insn_suffix
, addr
,
7101 case 2: /* Trap Doubleword Immediate */
7102 case 3: /* Trap Word Immediate */
7106 case 4: /* Vector Integer, Compare, Logical, Shift, etc. */
7107 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
7111 case 6: /* Vector Load and Store */
7112 if (ppc_process_record_op6 (gdbarch
, regcache
, addr
, insn
) != 0)
7116 case 17: /* System call */
7117 if (PPC_LEV (insn
) != 0)
7120 if (tdep
->ppc_syscall_record
!= NULL
)
7122 if (tdep
->ppc_syscall_record (regcache
) != 0)
7127 gdb_printf (gdb_stderr
, _("no syscall record support\n"));
7132 case 7: /* Multiply Low Immediate */
7133 record_full_arch_list_add_reg (regcache
,
7134 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7137 case 8: /* Subtract From Immediate Carrying */
7138 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
7139 record_full_arch_list_add_reg (regcache
,
7140 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7143 case 10: /* Compare Logical Immediate */
7144 case 11: /* Compare Immediate */
7145 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7148 case 13: /* Add Immediate Carrying and Record */
7149 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7151 case 12: /* Add Immediate Carrying */
7152 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
7154 case 14: /* Add Immediate */
7155 case 15: /* Add Immediate Shifted */
7156 record_full_arch_list_add_reg (regcache
,
7157 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7160 case 16: /* Branch Conditional */
7161 if ((PPC_BO (insn
) & 0x4) == 0)
7162 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
7164 case 18: /* Branch */
7166 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
7170 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
7174 case 20: /* Rotate Left Word Immediate then Mask Insert */
7175 case 21: /* Rotate Left Word Immediate then AND with Mask */
7176 case 23: /* Rotate Left Word then AND with Mask */
7177 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
7178 /* Rotate Left Doubleword Immediate then Clear Right */
7179 /* Rotate Left Doubleword Immediate then Clear */
7180 /* Rotate Left Doubleword then Clear Left */
7181 /* Rotate Left Doubleword then Clear Right */
7182 /* Rotate Left Doubleword Immediate then Mask Insert */
7184 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7185 record_full_arch_list_add_reg (regcache
,
7186 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7189 case 28: /* AND Immediate */
7190 case 29: /* AND Immediate Shifted */
7191 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
7193 case 24: /* OR Immediate */
7194 case 25: /* OR Immediate Shifted */
7195 case 26: /* XOR Immediate */
7196 case 27: /* XOR Immediate Shifted */
7197 record_full_arch_list_add_reg (regcache
,
7198 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7202 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
7206 case 33: /* Load Word and Zero with Update */
7207 case 35: /* Load Byte and Zero with Update */
7208 case 41: /* Load Halfword and Zero with Update */
7209 case 43: /* Load Halfword Algebraic with Update */
7210 record_full_arch_list_add_reg (regcache
,
7211 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7213 case 32: /* Load Word and Zero */
7214 case 34: /* Load Byte and Zero */
7215 case 40: /* Load Halfword and Zero */
7216 case 42: /* Load Halfword Algebraic */
7217 record_full_arch_list_add_reg (regcache
,
7218 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7221 case 46: /* Load Multiple Word */
7222 for (i
= PPC_RT (insn
); i
< 32; i
++)
7223 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
7226 case 56: /* Load Quadword */
7227 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
7228 record_full_arch_list_add_reg (regcache
, tmp
);
7229 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7232 case 49: /* Load Floating-Point Single with Update */
7233 case 51: /* Load Floating-Point Double with Update */
7234 record_full_arch_list_add_reg (regcache
,
7235 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7237 case 48: /* Load Floating-Point Single */
7238 case 50: /* Load Floating-Point Double */
7239 record_full_arch_list_add_reg (regcache
,
7240 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
7243 case 47: /* Store Multiple Word */
7247 if (PPC_RA (insn
) != 0)
7248 regcache_raw_read_unsigned (regcache
,
7249 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7252 iaddr
+= PPC_D (insn
);
7253 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
7257 case 37: /* Store Word with Update */
7258 case 39: /* Store Byte with Update */
7259 case 45: /* Store Halfword with Update */
7260 case 53: /* Store Floating-Point Single with Update */
7261 case 55: /* Store Floating-Point Double with Update */
7262 record_full_arch_list_add_reg (regcache
,
7263 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7265 case 36: /* Store Word */
7266 case 38: /* Store Byte */
7267 case 44: /* Store Halfword */
7268 case 52: /* Store Floating-Point Single */
7269 case 54: /* Store Floating-Point Double */
7274 if (PPC_RA (insn
) != 0)
7275 regcache_raw_read_unsigned (regcache
,
7276 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7278 iaddr
+= PPC_D (insn
);
7280 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
7282 else if (op6
== 54 || op6
== 55)
7284 else if (op6
== 44 || op6
== 45)
7286 else if (op6
== 38 || op6
== 39)
7291 record_full_arch_list_add_mem (iaddr
, size
);
7298 case 0: /* Load Floating-Point Double Pair */
7299 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
7300 record_full_arch_list_add_reg (regcache
, tmp
);
7301 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
7303 case 2: /* Load VSX Scalar Doubleword */
7304 case 3: /* Load VSX Scalar Single */
7305 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
7312 case 58: /* Load Doubleword */
7313 /* Load Doubleword with Update */
7314 /* Load Word Algebraic */
7315 if (PPC_FIELD (insn
, 30, 2) > 2)
7318 record_full_arch_list_add_reg (regcache
,
7319 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
7320 if (PPC_BIT (insn
, 31))
7321 record_full_arch_list_add_reg (regcache
,
7322 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
7326 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
7331 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
7336 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
7340 case 62: /* Store Doubleword */
7341 /* Store Doubleword with Update */
7342 /* Store Quadword with Update */
7346 int sub2
= PPC_FIELD (insn
, 30, 2);
7351 if (PPC_RA (insn
) != 0)
7352 regcache_raw_read_unsigned (regcache
,
7353 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
7356 size
= (sub2
== 2) ? 16 : 8;
7358 iaddr
+= PPC_DS (insn
) << 2;
7359 record_full_arch_list_add_mem (iaddr
, size
);
7361 if (op6
== 62 && sub2
== 1)
7362 record_full_arch_list_add_reg (regcache
,
7363 tdep
->ppc_gp0_regnum
+
7370 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
7376 gdb_printf (gdb_stdlog
, "Warning: Don't know how to record %08x "
7377 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
7381 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
7383 if (record_full_arch_list_add_end ())
7388 /* Used for matching tw, twi, td and tdi instructions for POWER. */
7390 static constexpr uint32_t TX_INSN_MASK
= 0xFC0007FF;
7391 static constexpr uint32_t TW_INSN
= 0x7C000008;
7392 static constexpr uint32_t TD_INSN
= 0x7C000088;
7394 static constexpr uint32_t TXI_INSN_MASK
= 0xFC000000;
7395 static constexpr uint32_t TWI_INSN
= 0x0C000000;
7396 static constexpr uint32_t TDI_INSN
= 0x08000000;
7399 is_tw_insn (uint32_t insn
)
7401 return (insn
& TX_INSN_MASK
) == TW_INSN
;
7405 is_twi_insn (uint32_t insn
)
7407 return (insn
& TXI_INSN_MASK
) == TWI_INSN
;
7411 is_td_insn (uint32_t insn
)
7413 return (insn
& TX_INSN_MASK
) == TD_INSN
;
7417 is_tdi_insn (uint32_t insn
)
7419 return (insn
& TXI_INSN_MASK
) == TDI_INSN
;
7422 /* Implementation of gdbarch_program_breakpoint_here_p for POWER. */
7425 rs6000_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
7427 gdb_byte target_mem
[PPC_INSN_SIZE
];
7429 /* Enable the automatic memory restoration from breakpoints while
7430 we read the memory. Otherwise we may find temporary breakpoints, ones
7431 inserted by GDB, and flag them as permanent breakpoints. */
7432 scoped_restore restore_memory
7433 = make_scoped_restore_show_memory_breakpoints (0);
7435 if (target_read_memory (address
, target_mem
, PPC_INSN_SIZE
) == 0)
7437 uint32_t insn
= (uint32_t) extract_unsigned_integer
7438 (target_mem
, PPC_INSN_SIZE
, gdbarch_byte_order_for_code (gdbarch
));
7440 /* Check if INSN is a TW, TWI, TD or TDI instruction. There
7441 are multiple choices of such instructions with different registers
7442 and / or immediate values but they all cause a break. */
7443 if (is_tw_insn (insn
) || is_twi_insn (insn
) || is_td_insn (insn
)
7444 || is_tdi_insn (insn
))
7451 /* Initialize the current architecture based on INFO. If possible, re-use an
7452 architecture from ARCHES, which is a list of architectures already created
7453 during this debugging session.
7455 Called e.g. at program startup, when reading a core file, and when reading
7458 static struct gdbarch
*
7459 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7461 struct gdbarch
*gdbarch
;
7462 int wordsize
, from_xcoff_exec
, from_elf_exec
;
7463 enum bfd_architecture arch
;
7466 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
7468 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
7469 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
7470 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
7471 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
7472 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
7473 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
7474 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
7475 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
7476 int have_htm_tar
= 0;
7477 int tdesc_wordsize
= -1;
7478 const struct target_desc
*tdesc
= info
.target_desc
;
7479 tdesc_arch_data_up tdesc_data
;
7480 int num_pseudoregs
= 0;
7483 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
7484 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
7486 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
7487 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
7489 /* Check word size. If INFO is from a binary file, infer it from
7490 that, else choose a likely default. */
7491 if (from_xcoff_exec
)
7493 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
7498 else if (from_elf_exec
)
7500 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
7505 else if (tdesc_has_registers (tdesc
))
7509 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
7510 wordsize
= (info
.bfd_arch_info
->bits_per_word
7511 / info
.bfd_arch_info
->bits_per_byte
);
7516 /* Get the architecture and machine from the BFD. */
7517 arch
= info
.bfd_arch_info
->arch
;
7518 mach
= info
.bfd_arch_info
->mach
;
7520 /* For e500 executables, the apuinfo section is of help here. Such
7521 section contains the identifier and revision number of each
7522 Application-specific Processing Unit that is present on the
7523 chip. The content of the section is determined by the assembler
7524 which looks at each instruction and determines which unit (and
7525 which version of it) can execute it. Grovel through the section
7526 looking for relevant e500 APUs. */
7528 if (bfd_uses_spe_extensions (info
.abfd
))
7530 arch
= info
.bfd_arch_info
->arch
;
7531 mach
= bfd_mach_ppc_e500
;
7532 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
7533 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
7536 /* Find a default target description which describes our register
7537 layout, if we do not already have one. */
7538 if (! tdesc_has_registers (tdesc
))
7540 const struct ppc_variant
*v
;
7542 /* Choose variant. */
7543 v
= find_variant_by_arch (arch
, mach
);
7550 gdb_assert (tdesc_has_registers (tdesc
));
7552 /* Check any target description for validity. */
7553 if (tdesc_has_registers (tdesc
))
7555 static const char *const gprs
[] = {
7556 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7557 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7558 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7559 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7561 const struct tdesc_feature
*feature
;
7563 static const char *const msr_names
[] = { "msr", "ps" };
7564 static const char *const cr_names
[] = { "cr", "cnd" };
7565 static const char *const ctr_names
[] = { "ctr", "cnt" };
7567 feature
= tdesc_find_feature (tdesc
,
7568 "org.gnu.gdb.power.core");
7569 if (feature
== NULL
)
7572 tdesc_data
= tdesc_data_alloc ();
7575 for (i
= 0; i
< ppc_num_gprs
; i
++)
7576 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7578 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7579 PPC_PC_REGNUM
, "pc");
7580 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7581 PPC_LR_REGNUM
, "lr");
7582 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7583 PPC_XER_REGNUM
, "xer");
7585 /* Allow alternate names for these registers, to accomodate GDB's
7587 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7588 PPC_MSR_REGNUM
, msr_names
);
7589 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7590 PPC_CR_REGNUM
, cr_names
);
7591 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
7592 PPC_CTR_REGNUM
, ctr_names
);
7597 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7598 PPC_MQ_REGNUM
, "mq");
7600 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
7602 wordsize
= tdesc_wordsize
;
7604 feature
= tdesc_find_feature (tdesc
,
7605 "org.gnu.gdb.power.fpu");
7606 if (feature
!= NULL
)
7608 static const char *const fprs
[] = {
7609 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7610 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7611 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7612 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
7615 for (i
= 0; i
< ppc_num_fprs
; i
++)
7616 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7617 PPC_F0_REGNUM
+ i
, fprs
[i
]);
7618 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7619 PPC_FPSCR_REGNUM
, "fpscr");
7625 /* The fpscr register was expanded in isa 2.05 to 64 bits
7626 along with the addition of the decimal floating point
7628 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
7634 feature
= tdesc_find_feature (tdesc
,
7635 "org.gnu.gdb.power.altivec");
7636 if (feature
!= NULL
)
7638 static const char *const vector_regs
[] = {
7639 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
7640 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
7641 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
7642 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
7646 for (i
= 0; i
< ppc_num_gprs
; i
++)
7647 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7650 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7651 PPC_VSCR_REGNUM
, "vscr");
7652 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7653 PPC_VRSAVE_REGNUM
, "vrsave");
7655 if (have_spe
|| !valid_p
)
7662 /* Check for POWER7 VSX registers support. */
7663 feature
= tdesc_find_feature (tdesc
,
7664 "org.gnu.gdb.power.vsx");
7666 if (feature
!= NULL
)
7668 static const char *const vsx_regs
[] = {
7669 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
7670 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
7671 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
7672 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
7673 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
7679 for (i
= 0; i
< ppc_num_vshrs
; i
++)
7680 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7681 PPC_VSR0_UPPER_REGNUM
+ i
,
7684 if (!valid_p
|| !have_fpu
|| !have_altivec
)
7692 /* On machines supporting the SPE APU, the general-purpose registers
7693 are 64 bits long. There are SIMD vector instructions to treat them
7694 as pairs of floats, but the rest of the instruction set treats them
7695 as 32-bit registers, and only operates on their lower halves.
7697 In the GDB regcache, we treat their high and low halves as separate
7698 registers. The low halves we present as the general-purpose
7699 registers, and then we have pseudo-registers that stitch together
7700 the upper and lower halves and present them as pseudo-registers.
7702 Thus, the target description is expected to supply the upper
7703 halves separately. */
7705 feature
= tdesc_find_feature (tdesc
,
7706 "org.gnu.gdb.power.spe");
7707 if (feature
!= NULL
)
7709 static const char *const upper_spe
[] = {
7710 "ev0h", "ev1h", "ev2h", "ev3h",
7711 "ev4h", "ev5h", "ev6h", "ev7h",
7712 "ev8h", "ev9h", "ev10h", "ev11h",
7713 "ev12h", "ev13h", "ev14h", "ev15h",
7714 "ev16h", "ev17h", "ev18h", "ev19h",
7715 "ev20h", "ev21h", "ev22h", "ev23h",
7716 "ev24h", "ev25h", "ev26h", "ev27h",
7717 "ev28h", "ev29h", "ev30h", "ev31h"
7721 for (i
= 0; i
< ppc_num_gprs
; i
++)
7722 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7723 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
7725 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7726 PPC_SPE_ACC_REGNUM
, "acc");
7727 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7728 PPC_SPE_FSCR_REGNUM
, "spefscr");
7730 if (have_mq
|| have_fpu
|| !valid_p
)
7737 /* Program Priority Register. */
7738 feature
= tdesc_find_feature (tdesc
,
7739 "org.gnu.gdb.power.ppr");
7740 if (feature
!= NULL
)
7743 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7744 PPC_PPR_REGNUM
, "ppr");
7753 /* Data Stream Control Register. */
7754 feature
= tdesc_find_feature (tdesc
,
7755 "org.gnu.gdb.power.dscr");
7756 if (feature
!= NULL
)
7759 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7760 PPC_DSCR_REGNUM
, "dscr");
7769 /* Target Address Register. */
7770 feature
= tdesc_find_feature (tdesc
,
7771 "org.gnu.gdb.power.tar");
7772 if (feature
!= NULL
)
7775 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7776 PPC_TAR_REGNUM
, "tar");
7785 /* Event-based Branching Registers. */
7786 feature
= tdesc_find_feature (tdesc
,
7787 "org.gnu.gdb.power.ebb");
7788 if (feature
!= NULL
)
7790 static const char *const ebb_regs
[] = {
7791 "bescr", "ebbhr", "ebbrr"
7795 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
7796 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7797 PPC_BESCR_REGNUM
+ i
,
7806 /* Subset of the ISA 2.07 Performance Monitor Registers provided
7808 feature
= tdesc_find_feature (tdesc
,
7809 "org.gnu.gdb.power.linux.pmu");
7810 if (feature
!= NULL
)
7814 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7817 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7820 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7823 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7826 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7837 /* Hardware Transactional Memory Registers. */
7838 feature
= tdesc_find_feature (tdesc
,
7839 "org.gnu.gdb.power.htm.spr");
7840 if (feature
!= NULL
)
7842 static const char *const tm_spr_regs
[] = {
7843 "tfhar", "texasr", "tfiar"
7847 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
7848 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7849 PPC_TFHAR_REGNUM
+ i
,
7859 feature
= tdesc_find_feature (tdesc
,
7860 "org.gnu.gdb.power.htm.core");
7861 if (feature
!= NULL
)
7863 static const char *const cgprs
[] = {
7864 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
7865 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
7866 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
7867 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
7868 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
7873 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
7874 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7885 feature
= tdesc_find_feature (tdesc
,
7886 "org.gnu.gdb.power.htm.fpu");
7887 if (feature
!= NULL
)
7891 static const char *const cfprs
[] = {
7892 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
7893 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
7894 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
7895 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
7896 "cf30", "cf31", "cfpscr"
7899 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
7900 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7911 feature
= tdesc_find_feature (tdesc
,
7912 "org.gnu.gdb.power.htm.altivec");
7913 if (feature
!= NULL
)
7917 static const char *const cvmx
[] = {
7918 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
7919 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
7920 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
7921 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
7922 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
7926 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
7927 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7928 PPC_CVR0_REGNUM
+ i
,
7933 have_htm_altivec
= 1;
7936 have_htm_altivec
= 0;
7938 feature
= tdesc_find_feature (tdesc
,
7939 "org.gnu.gdb.power.htm.vsx");
7940 if (feature
!= NULL
)
7944 static const char *const cvsx
[] = {
7945 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
7946 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
7947 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
7948 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
7949 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
7953 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
7954 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
7955 (PPC_CVSR0_UPPER_REGNUM
7959 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
7966 feature
= tdesc_find_feature (tdesc
,
7967 "org.gnu.gdb.power.htm.ppr");
7968 if (feature
!= NULL
)
7970 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7971 PPC_CPPR_REGNUM
, "cppr");
7980 feature
= tdesc_find_feature (tdesc
,
7981 "org.gnu.gdb.power.htm.dscr");
7982 if (feature
!= NULL
)
7984 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7985 PPC_CDSCR_REGNUM
, "cdscr");
7994 feature
= tdesc_find_feature (tdesc
,
7995 "org.gnu.gdb.power.htm.tar");
7996 if (feature
!= NULL
)
7998 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
7999 PPC_CTAR_REGNUM
, "ctar");
8009 /* If we have a 64-bit binary on a 32-bit target, complain. Also
8010 complain for a 32-bit binary on a 64-bit target; we do not yet
8011 support that. For instance, the 32-bit ABI routines expect
8014 As long as there isn't an explicit target description, we'll
8015 choose one based on the BFD architecture and get a word size
8016 matching the binary (probably powerpc:common or
8017 powerpc:common64). So there is only trouble if a 64-bit target
8018 supplies a 64-bit description while debugging a 32-bit
8020 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
8026 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
8029 elf_abi
= POWERPC_ELF_V1
;
8032 elf_abi
= POWERPC_ELF_V2
;
8039 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
8041 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8042 Tag_GNU_Power_ABI_FP
) & 3)
8045 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
8048 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
8055 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
8057 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8058 Tag_GNU_Power_ABI_FP
) >> 2)
8061 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
8064 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
8071 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
8073 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8074 Tag_GNU_Power_ABI_Vector
))
8077 vector_abi
= POWERPC_VEC_GENERIC
;
8080 vector_abi
= POWERPC_VEC_ALTIVEC
;
8083 vector_abi
= POWERPC_VEC_SPE
;
8091 /* At this point, the only supported ELF-based 64-bit little-endian
8092 operating system is GNU/Linux, and this uses the ELFv2 ABI by
8093 default. All other supported ELF-based operating systems use the
8094 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
8095 e.g. because we run a legacy binary, or have attached to a process
8096 and have not found any associated binary file, set the default
8097 according to this heuristic. */
8098 if (elf_abi
== POWERPC_ELF_AUTO
)
8100 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
8101 elf_abi
= POWERPC_ELF_V2
;
8103 elf_abi
= POWERPC_ELF_V1
;
8106 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
8108 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
8111 soft_float
= !have_fpu
;
8113 /* If we have a hard float binary or setting but no floating point
8114 registers, downgrade to soft float anyway. We're still somewhat
8115 useful in this scenario. */
8116 if (!soft_float
&& !have_fpu
)
8119 /* Similarly for vector registers. */
8120 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
8121 vector_abi
= POWERPC_VEC_GENERIC
;
8123 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
8124 vector_abi
= POWERPC_VEC_GENERIC
;
8126 if (vector_abi
== POWERPC_VEC_AUTO
)
8129 vector_abi
= POWERPC_VEC_ALTIVEC
;
8131 vector_abi
= POWERPC_VEC_SPE
;
8133 vector_abi
= POWERPC_VEC_GENERIC
;
8136 /* Do not limit the vector ABI based on available hardware, since we
8137 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
8139 /* Find a candidate among extant architectures. */
8140 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8142 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8144 /* Word size in the various PowerPC bfd_arch_info structs isn't
8145 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
8146 separate word size check. */
8147 ppc_gdbarch_tdep
*tdep
8148 = gdbarch_tdep
<ppc_gdbarch_tdep
> (arches
->gdbarch
);
8149 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
8151 if (tdep
&& tdep
->soft_float
!= soft_float
)
8153 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
8155 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
8157 if (tdep
&& tdep
->wordsize
== wordsize
)
8158 return arches
->gdbarch
;
8161 /* None found, create a new architecture from INFO, whose bfd_arch_info
8162 validity depends on the source:
8163 - executable useless
8164 - rs6000_host_arch() good
8166 - "set arch" trust blindly
8167 - GDB startup useless but harmless */
8169 ppc_gdbarch_tdep
*tdep
= new ppc_gdbarch_tdep
;
8170 tdep
->wordsize
= wordsize
;
8171 tdep
->elf_abi
= elf_abi
;
8172 tdep
->soft_float
= soft_float
;
8173 tdep
->long_double_abi
= long_double_abi
;
8174 tdep
->vector_abi
= vector_abi
;
8176 gdbarch
= gdbarch_alloc (&info
, tdep
);
8178 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
8179 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
8180 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
8181 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
8182 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
8183 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
8184 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
8185 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
8187 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
8188 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
8189 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
8190 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
8191 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
8192 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
8193 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
8194 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
8195 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
8196 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
8197 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
8198 tdep
->have_ebb
= have_ebb
;
8200 /* If additional pmu registers are added, care must be taken when
8201 setting new fields in the tdep below, to maintain compatibility
8202 with features that only provide some of the registers. Currently
8203 gdb access to the pmu registers is only supported in linux, and
8204 linux only provides a subset of the pmu registers defined in the
8207 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
8208 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
8209 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
8210 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
8211 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
8213 tdep
->have_htm_spr
= have_htm_spr
;
8214 tdep
->have_htm_core
= have_htm_core
;
8215 tdep
->have_htm_fpu
= have_htm_fpu
;
8216 tdep
->have_htm_altivec
= have_htm_altivec
;
8217 tdep
->have_htm_vsx
= have_htm_vsx
;
8218 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
8219 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
8220 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
8222 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
8223 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
8224 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
8225 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
8227 /* The XML specification for PowerPC sensibly calls the MSR "msr".
8228 GDB traditionally called it "ps", though, so let GDB add an
8230 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
8233 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
8235 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
8237 /* Set lr_frame_offset. */
8239 tdep
->lr_frame_offset
= 16;
8241 tdep
->lr_frame_offset
= 4;
8243 if (have_spe
|| have_dfp
|| have_altivec
8244 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
8246 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
8247 set_gdbarch_pseudo_register_write (gdbarch
,
8248 rs6000_pseudo_register_write
);
8249 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8250 rs6000_ax_pseudo_register_collect
);
8253 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
8255 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8257 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
8260 num_pseudoregs
+= 32;
8262 num_pseudoregs
+= 16;
8264 num_pseudoregs
+= 32;
8266 /* Include both VSX and Extended FP registers. */
8267 num_pseudoregs
+= 96;
8269 num_pseudoregs
+= 16;
8270 /* Include both checkpointed VSX and EFP registers. */
8272 num_pseudoregs
+= 64 + 32;
8274 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
8276 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
8277 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
8278 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
8279 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
8280 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
8281 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
8282 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
8283 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
8284 set_gdbarch_char_signed (gdbarch
, 0);
8286 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
8289 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
8291 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
8292 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
8293 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
8295 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
8296 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
8299 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
8300 else if (wordsize
== 8)
8301 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
8303 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
8304 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
8305 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
8307 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8309 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
8310 rs6000_breakpoint::kind_from_pc
);
8311 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
8312 rs6000_breakpoint::bp_from_kind
);
8313 set_gdbarch_program_breakpoint_here_p (gdbarch
,
8314 rs6000_program_breakpoint_here_p
);
8316 /* The value of symbols of type N_SO and N_FUN maybe null when
8318 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
8320 /* Handles single stepping of atomic sequences. */
8321 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
8323 /* Not sure on this. FIXMEmgo */
8324 set_gdbarch_frame_args_skip (gdbarch
, 8);
8326 /* Helpers for function argument information. */
8327 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
8330 set_gdbarch_in_solib_return_trampoline
8331 (gdbarch
, rs6000_in_solib_return_trampoline
);
8332 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
8334 /* Hook in the DWARF CFI frame unwinder. */
8335 dwarf2_append_unwinders (gdbarch
);
8336 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
8338 /* Frame handling. */
8339 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
8341 /* Setup displaced stepping. */
8342 set_gdbarch_displaced_step_copy_insn (gdbarch
,
8343 ppc_displaced_step_copy_insn
);
8344 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
8345 ppc_displaced_step_hw_singlestep
);
8346 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
8347 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
8348 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
8349 set_gdbarch_displaced_step_restore_all_in_ptid
8350 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
8352 set_gdbarch_max_insn_length (gdbarch
, 2 * PPC_INSN_SIZE
);
8354 /* Hook in ABI-specific overrides, if they have been registered. */
8355 info
.target_desc
= tdesc
;
8356 info
.tdesc_data
= tdesc_data
.get ();
8357 gdbarch_init_osabi (info
, gdbarch
);
8361 case GDB_OSABI_LINUX
:
8362 case GDB_OSABI_NETBSD
:
8363 case GDB_OSABI_UNKNOWN
:
8364 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
8365 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
8366 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
8369 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
8371 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
8372 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
8373 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
8376 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
8377 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
8378 rs6000_pseudo_register_reggroup_p
);
8379 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8381 /* Override the normal target description method to make the SPE upper
8382 halves anonymous. */
8383 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
8385 /* Choose register numbers for all supported pseudo-registers. */
8386 tdep
->ppc_ev0_regnum
= -1;
8387 tdep
->ppc_dl0_regnum
= -1;
8388 tdep
->ppc_v0_alias_regnum
= -1;
8389 tdep
->ppc_vsr0_regnum
= -1;
8390 tdep
->ppc_efpr0_regnum
= -1;
8391 tdep
->ppc_cdl0_regnum
= -1;
8392 tdep
->ppc_cvsr0_regnum
= -1;
8393 tdep
->ppc_cefpr0_regnum
= -1;
8395 cur_reg
= gdbarch_num_regs (gdbarch
);
8399 tdep
->ppc_ev0_regnum
= cur_reg
;
8404 tdep
->ppc_dl0_regnum
= cur_reg
;
8409 tdep
->ppc_v0_alias_regnum
= cur_reg
;
8414 tdep
->ppc_vsr0_regnum
= cur_reg
;
8416 tdep
->ppc_efpr0_regnum
= cur_reg
;
8421 tdep
->ppc_cdl0_regnum
= cur_reg
;
8426 tdep
->ppc_cvsr0_regnum
= cur_reg
;
8428 tdep
->ppc_cefpr0_regnum
= cur_reg
;
8432 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
8434 /* Register the ravenscar_arch_ops. */
8435 if (mach
== bfd_mach_ppc_e500
)
8436 register_e500_ravenscar_ops (gdbarch
);
8438 register_ppc_ravenscar_ops (gdbarch
);
8440 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
8441 set_gdbarch_valid_disassembler_options (gdbarch
,
8442 disassembler_options_powerpc ());
8448 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8450 ppc_gdbarch_tdep
*tdep
= gdbarch_tdep
<ppc_gdbarch_tdep
> (gdbarch
);
8455 /* FIXME: Dump gdbarch_tdep. */
8459 powerpc_set_soft_float (const char *args
, int from_tty
,
8460 struct cmd_list_element
*c
)
8462 struct gdbarch_info info
;
8464 /* Update the architecture. */
8465 if (!gdbarch_update_p (info
))
8466 internal_error (_("could not update architecture"));
8470 powerpc_set_vector_abi (const char *args
, int from_tty
,
8471 struct cmd_list_element
*c
)
8475 for (vector_abi
= POWERPC_VEC_AUTO
;
8476 vector_abi
!= POWERPC_VEC_LAST
;
8478 if (strcmp (powerpc_vector_abi_string
,
8479 powerpc_vector_strings
[vector_abi
]) == 0)
8481 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
8485 if (vector_abi
== POWERPC_VEC_LAST
)
8486 internal_error (_("Invalid vector ABI accepted: %s."),
8487 powerpc_vector_abi_string
);
8489 /* Update the architecture. */
8491 if (!gdbarch_update_p (info
))
8492 internal_error (_("could not update architecture"));
8495 /* Show the current setting of the exact watchpoints flag. */
8498 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
8499 struct cmd_list_element
*c
,
8502 gdb_printf (file
, _("Use of exact watchpoints is %s.\n"), value
);
8505 /* Read a PPC instruction from memory. */
8508 read_insn (frame_info_ptr frame
, CORE_ADDR pc
)
8510 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8511 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8513 return read_memory_unsigned_integer (pc
, 4, byte_order
);
8516 /* Return non-zero if the instructions at PC match the series
8517 described in PATTERN, or zero otherwise. PATTERN is an array of
8518 'struct ppc_insn_pattern' objects, terminated by an entry whose
8521 When the match is successful, fill INSNS[i] with what PATTERN[i]
8522 matched. If PATTERN[i] is optional, and the instruction wasn't
8523 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
8524 INSNS should have as many elements as PATTERN, minus the terminator.
8525 Note that, if PATTERN contains optional instructions which aren't
8526 present in memory, then INSNS will have holes, so INSNS[i] isn't
8527 necessarily the i'th instruction in memory. */
8530 ppc_insns_match_pattern (frame_info_ptr frame
, CORE_ADDR pc
,
8531 const struct ppc_insn_pattern
*pattern
,
8532 unsigned int *insns
)
8537 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
8540 insn
= read_insn (frame
, pc
);
8542 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
8548 else if (!pattern
[i
].optional
)
8555 /* Return the 'd' field of the d-form instruction INSN, properly
8559 ppc_insn_d_field (unsigned int insn
)
8561 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
8564 /* Return the 'ds' field of the ds-form instruction INSN, with the two
8565 zero bits concatenated at the right, and properly
8569 ppc_insn_ds_field (unsigned int insn
)
8571 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
8575 ppc_insn_prefix_dform (unsigned int insn1
, unsigned int insn2
)
8577 /* result is 34-bits */
8578 return (CORE_ADDR
) ((((insn1
& 0x3ffff) ^ 0x20000) - 0x20000) << 16)
8579 | (CORE_ADDR
)(insn2
& 0xffff);
8582 /* Initialization code. */
8584 void _initialize_rs6000_tdep ();
8586 _initialize_rs6000_tdep ()
8588 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
8589 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
8591 /* Initialize the standard target descriptions. */
8592 initialize_tdesc_powerpc_32 ();
8593 initialize_tdesc_powerpc_altivec32 ();
8594 initialize_tdesc_powerpc_vsx32 ();
8595 initialize_tdesc_powerpc_403 ();
8596 initialize_tdesc_powerpc_403gc ();
8597 initialize_tdesc_powerpc_405 ();
8598 initialize_tdesc_powerpc_505 ();
8599 initialize_tdesc_powerpc_601 ();
8600 initialize_tdesc_powerpc_602 ();
8601 initialize_tdesc_powerpc_603 ();
8602 initialize_tdesc_powerpc_604 ();
8603 initialize_tdesc_powerpc_64 ();
8604 initialize_tdesc_powerpc_altivec64 ();
8605 initialize_tdesc_powerpc_vsx64 ();
8606 initialize_tdesc_powerpc_7400 ();
8607 initialize_tdesc_powerpc_750 ();
8608 initialize_tdesc_powerpc_860 ();
8609 initialize_tdesc_powerpc_e500 ();
8610 initialize_tdesc_rs6000 ();
8612 /* Add root prefix command for all "set powerpc"/"show powerpc"
8614 add_setshow_prefix_cmd ("powerpc", no_class
,
8615 _("Various PowerPC-specific commands."),
8616 _("Various PowerPC-specific commands."),
8617 &setpowerpccmdlist
, &showpowerpccmdlist
,
8618 &setlist
, &showlist
);
8620 /* Add a command to allow the user to force the ABI. */
8621 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
8622 &powerpc_soft_float_global
,
8623 _("Set whether to use a soft-float ABI."),
8624 _("Show whether to use a soft-float ABI."),
8626 powerpc_set_soft_float
, NULL
,
8627 &setpowerpccmdlist
, &showpowerpccmdlist
);
8629 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
8630 &powerpc_vector_abi_string
,
8631 _("Set the vector ABI."),
8632 _("Show the vector ABI."),
8633 NULL
, powerpc_set_vector_abi
, NULL
,
8634 &setpowerpccmdlist
, &showpowerpccmdlist
);
8636 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
8637 &target_exact_watchpoints
,
8639 Set whether to use just one debug register for watchpoints on scalars."),
8641 Show whether to use just one debug register for watchpoints on scalars."),
8643 If true, GDB will use only one debug register when watching a variable of\n\
8644 scalar type, thus assuming that the variable is accessed through the address\n\
8645 of its first byte."),
8646 NULL
, show_powerpc_exact_watchpoints
,
8647 &setpowerpccmdlist
, &showpowerpccmdlist
);