1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
43 #include "libbfd.h" /* for bfd_default_set_arch_mach */
44 #include "coff/internal.h" /* for libcoff.h */
45 #include "libcoff.h" /* for xcoff_data */
46 #include "coff/xcoff.h"
51 #include "solib-svr4.h"
54 #include "gdb_assert.h"
57 #include "trad-frame.h"
58 #include "frame-unwind.h"
59 #include "frame-base.h"
61 /* If the kernel has to deliver a signal, it pushes a sigcontext
62 structure on the stack and then calls the signal handler, passing
63 the address of the sigcontext in an argument register. Usually
64 the signal handler doesn't save this register, so we have to
65 access the sigcontext structure via an offset from the signal handler
67 The following constants were determined by experimentation on AIX 3.2. */
68 #define SIG_FRAME_PC_OFFSET 96
69 #define SIG_FRAME_LR_OFFSET 108
70 #define SIG_FRAME_FP_OFFSET 284
72 /* To be used by skip_prologue. */
74 struct rs6000_framedata
76 int offset
; /* total size of frame --- the distance
77 by which we decrement sp to allocate
79 int saved_gpr
; /* smallest # of saved gpr */
80 int saved_fpr
; /* smallest # of saved fpr */
81 int saved_vr
; /* smallest # of saved vr */
82 int saved_ev
; /* smallest # of saved ev */
83 int alloca_reg
; /* alloca register number (frame ptr) */
84 char frameless
; /* true if frameless functions. */
85 char nosavedpc
; /* true if pc not saved. */
86 int gpr_offset
; /* offset of saved gprs from prev sp */
87 int fpr_offset
; /* offset of saved fprs from prev sp */
88 int vr_offset
; /* offset of saved vrs from prev sp */
89 int ev_offset
; /* offset of saved evs from prev sp */
90 int lr_offset
; /* offset of saved lr */
91 int cr_offset
; /* offset of saved cr */
92 int vrsave_offset
; /* offset of saved vrsave register */
95 /* Description of a single register. */
99 char *name
; /* name of register */
100 unsigned char sz32
; /* size on 32-bit arch, 0 if nonextant */
101 unsigned char sz64
; /* size on 64-bit arch, 0 if nonextant */
102 unsigned char fpr
; /* whether register is floating-point */
103 unsigned char pseudo
; /* whether register is pseudo */
104 int spr_num
; /* PowerPC SPR number, or -1 if not an SPR.
105 This is an ISA SPR number, not a GDB
109 /* Breakpoint shadows for the single step instructions will be kept here. */
111 static struct sstep_breaks
113 /* Address, or 0 if this is not in use. */
115 /* Shadow contents. */
120 /* Hook for determining the TOC address when calling functions in the
121 inferior under AIX. The initialization code in rs6000-nat.c sets
122 this hook to point to find_toc_address. */
124 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
126 /* Hook to set the current architecture when starting a child process.
127 rs6000-nat.c sets this. */
129 void (*rs6000_set_host_arch_hook
) (int) = NULL
;
131 /* Static function prototypes */
133 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
135 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
136 struct rs6000_framedata
*);
138 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
140 altivec_register_p (int regno
)
142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
143 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
146 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
150 /* Return true if REGNO is an SPE register, false otherwise. */
152 spe_register_p (int regno
)
154 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
156 /* Is it a reference to EV0 -- EV31, and do we have those? */
157 if (tdep
->ppc_ev0_regnum
>= 0
158 && tdep
->ppc_ev31_regnum
>= 0
159 && tdep
->ppc_ev0_regnum
<= regno
&& regno
<= tdep
->ppc_ev31_regnum
)
162 /* Is it a reference to the 64-bit accumulator, and do we have that? */
163 if (tdep
->ppc_acc_regnum
>= 0
164 && tdep
->ppc_acc_regnum
== regno
)
167 /* Is it a reference to the SPE floating-point status and control register,
168 and do we have that? */
169 if (tdep
->ppc_spefscr_regnum
>= 0
170 && tdep
->ppc_spefscr_regnum
== regno
)
177 /* Return non-zero if the architecture described by GDBARCH has
178 floating-point registers (f0 --- f31 and fpscr). */
180 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 return (tdep
->ppc_fp0_regnum
>= 0
185 && tdep
->ppc_fpscr_regnum
>= 0);
189 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
191 /* Make sure we don't try to assign any given GDB register a sim
192 register number more than once. */
193 gdb_assert (table
[gdb_regno
] == -1);
194 table
[gdb_regno
] = sim_regno
;
198 init_sim_regno_table (struct gdbarch
*arch
)
200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
201 int total_regs
= gdbarch_num_regs (arch
) + gdbarch_num_pseudo_regs (arch
);
202 const struct reg
*regs
= tdep
->regs
;
203 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
206 /* Presume that all registers not explicitly mentioned below are
207 unavailable from the sim. */
208 for (i
= 0; i
< total_regs
; i
++)
211 /* General-purpose registers. */
212 for (i
= 0; i
< ppc_num_gprs
; i
++)
213 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
215 /* Floating-point registers. */
216 if (tdep
->ppc_fp0_regnum
>= 0)
217 for (i
= 0; i
< ppc_num_fprs
; i
++)
218 set_sim_regno (sim_regno
,
219 tdep
->ppc_fp0_regnum
+ i
,
220 sim_ppc_f0_regnum
+ i
);
221 if (tdep
->ppc_fpscr_regnum
>= 0)
222 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
224 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
225 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
226 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
228 /* Segment registers. */
229 if (tdep
->ppc_sr0_regnum
>= 0)
230 for (i
= 0; i
< ppc_num_srs
; i
++)
231 set_sim_regno (sim_regno
,
232 tdep
->ppc_sr0_regnum
+ i
,
233 sim_ppc_sr0_regnum
+ i
);
235 /* Altivec registers. */
236 if (tdep
->ppc_vr0_regnum
>= 0)
238 for (i
= 0; i
< ppc_num_vrs
; i
++)
239 set_sim_regno (sim_regno
,
240 tdep
->ppc_vr0_regnum
+ i
,
241 sim_ppc_vr0_regnum
+ i
);
243 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
244 we can treat this more like the other cases. */
245 set_sim_regno (sim_regno
,
246 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
247 sim_ppc_vscr_regnum
);
249 /* vsave is a special-purpose register, so the code below handles it. */
251 /* SPE APU (E500) registers. */
252 if (tdep
->ppc_ev0_regnum
>= 0)
253 for (i
= 0; i
< ppc_num_gprs
; i
++)
254 set_sim_regno (sim_regno
,
255 tdep
->ppc_ev0_regnum
+ i
,
256 sim_ppc_ev0_regnum
+ i
);
257 if (tdep
->ppc_acc_regnum
>= 0)
258 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
259 /* spefscr is a special-purpose register, so the code below handles it. */
261 /* Now handle all special-purpose registers. Verify that they
262 haven't mistakenly been assigned numbers by any of the above
264 for (i
= 0; i
< total_regs
; i
++)
265 if (regs
[i
].spr_num
>= 0)
266 set_sim_regno (sim_regno
, i
, regs
[i
].spr_num
+ sim_ppc_spr0_regnum
);
268 /* Drop the initialized array into place. */
269 tdep
->sim_regno
= sim_regno
;
273 rs6000_register_sim_regno (int reg
)
275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
278 gdb_assert (0 <= reg
&& reg
<= NUM_REGS
+ NUM_PSEUDO_REGS
);
279 sim_regno
= tdep
->sim_regno
[reg
];
284 return LEGACY_SIM_REGNO_IGNORE
;
289 /* Register set support functions. */
292 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
293 const char *regs
, size_t offset
)
295 if (regnum
!= -1 && offset
!= -1)
296 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
300 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
301 char *regs
, size_t offset
)
303 if (regnum
!= -1 && offset
!= -1)
304 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
307 /* Supply register REGNUM in the general-purpose register set REGSET
308 from the buffer specified by GREGS and LEN to register cache
309 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
312 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
313 int regnum
, const void *gregs
, size_t len
)
315 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
317 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
321 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
322 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
325 if (regnum
== -1 || regnum
== i
)
326 ppc_supply_reg (regcache
, i
, gregs
, offset
);
329 if (regnum
== -1 || regnum
== PC_REGNUM
)
330 ppc_supply_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
331 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
332 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
333 gregs
, offsets
->ps_offset
);
334 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
335 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
336 gregs
, offsets
->cr_offset
);
337 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
338 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
339 gregs
, offsets
->lr_offset
);
340 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
341 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
342 gregs
, offsets
->ctr_offset
);
343 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
344 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
345 gregs
, offsets
->cr_offset
);
346 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
347 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
, gregs
, offsets
->mq_offset
);
350 /* Supply register REGNUM in the floating-point register set REGSET
351 from the buffer specified by FPREGS and LEN to register cache
352 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
355 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
356 int regnum
, const void *fpregs
, size_t len
)
358 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
359 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
360 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
364 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
366 offset
= offsets
->f0_offset
;
367 for (i
= tdep
->ppc_fp0_regnum
;
368 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
371 if (regnum
== -1 || regnum
== i
)
372 ppc_supply_reg (regcache
, i
, fpregs
, offset
);
375 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
376 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
377 fpregs
, offsets
->fpscr_offset
);
380 /* Collect register REGNUM in the general-purpose register set
381 REGSET. from register cache REGCACHE into the buffer specified by
382 GREGS and LEN. If REGNUM is -1, do this for all registers in
386 ppc_collect_gregset (const struct regset
*regset
,
387 const struct regcache
*regcache
,
388 int regnum
, void *gregs
, size_t len
)
390 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
391 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
392 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
396 offset
= offsets
->r0_offset
;
397 for (i
= tdep
->ppc_gp0_regnum
;
398 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
401 if (regnum
== -1 || regnum
== i
)
402 ppc_collect_reg (regcache
, i
, gregs
, offset
);
405 if (regnum
== -1 || regnum
== PC_REGNUM
)
406 ppc_collect_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
407 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
408 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
409 gregs
, offsets
->ps_offset
);
410 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
411 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
412 gregs
, offsets
->cr_offset
);
413 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
414 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
415 gregs
, offsets
->lr_offset
);
416 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
417 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
418 gregs
, offsets
->ctr_offset
);
419 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
420 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
421 gregs
, offsets
->xer_offset
);
422 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
423 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
424 gregs
, offsets
->mq_offset
);
427 /* Collect register REGNUM in the floating-point register set
428 REGSET. from register cache REGCACHE into the buffer specified by
429 FPREGS and LEN. If REGNUM is -1, do this for all registers in
433 ppc_collect_fpregset (const struct regset
*regset
,
434 const struct regcache
*regcache
,
435 int regnum
, void *fpregs
, size_t len
)
437 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
439 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
443 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
445 offset
= offsets
->f0_offset
;
446 for (i
= tdep
->ppc_fp0_regnum
;
447 i
<= tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
450 if (regnum
== -1 || regnum
== i
)
451 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
);
454 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
455 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
456 fpregs
, offsets
->fpscr_offset
);
460 /* Read a LEN-byte address from debugged memory address MEMADDR. */
463 read_memory_addr (CORE_ADDR memaddr
, int len
)
465 return read_memory_unsigned_integer (memaddr
, len
);
469 rs6000_skip_prologue (CORE_ADDR pc
)
471 struct rs6000_framedata frame
;
472 pc
= skip_prologue (pc
, 0, &frame
);
477 /* Fill in fi->saved_regs */
479 struct frame_extra_info
481 /* Functions calling alloca() change the value of the stack
482 pointer. We need to use initial stack pointer (which is saved in
483 r31 by gcc) in such cases. If a compiler emits traceback table,
484 then we should use the alloca register specified in traceback
486 CORE_ADDR initial_sp
; /* initial stack pointer. */
489 /* Get the ith function argument for the current function. */
491 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
495 get_frame_register (frame
, 3 + argi
, &addr
);
499 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
502 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
509 absolute
= (int) ((instr
>> 1) & 1);
514 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
518 dest
= pc
+ immediate
;
522 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
526 dest
= pc
+ immediate
;
530 ext_op
= (instr
>> 1) & 0x3ff;
532 if (ext_op
== 16) /* br conditional register */
534 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
536 /* If we are about to return from a signal handler, dest is
537 something like 0x3c90. The current frame is a signal handler
538 caller frame, upon completion of the sigreturn system call
539 execution will return to the saved PC in the frame. */
540 if (dest
< TEXT_SEGMENT_BASE
)
542 struct frame_info
*fi
;
544 fi
= get_current_frame ();
546 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
547 gdbarch_tdep (current_gdbarch
)->wordsize
);
551 else if (ext_op
== 528) /* br cond to count reg */
553 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
555 /* If we are about to execute a system call, dest is something
556 like 0x22fc or 0x3b00. Upon completion the system call
557 will return to the address in the link register. */
558 if (dest
< TEXT_SEGMENT_BASE
)
559 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
568 return (dest
< TEXT_SEGMENT_BASE
) ? safety
: dest
;
572 /* Sequence of bytes for breakpoint instruction. */
574 const static unsigned char *
575 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
577 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
578 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
580 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
581 return big_breakpoint
;
583 return little_breakpoint
;
587 /* AIX does not support PT_STEP. Simulate it. */
590 rs6000_software_single_step (enum target_signal signal
,
591 int insert_breakpoints_p
)
595 const char *breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
601 if (insert_breakpoints_p
)
606 insn
= read_memory_integer (loc
, 4);
608 breaks
[0] = loc
+ breakp_sz
;
610 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
612 /* Don't put two breakpoints on the same address. */
613 if (breaks
[1] == breaks
[0])
616 stepBreaks
[1].address
= 0;
618 for (ii
= 0; ii
< 2; ++ii
)
621 /* ignore invalid breakpoint. */
622 if (breaks
[ii
] == -1)
624 target_insert_breakpoint (breaks
[ii
], stepBreaks
[ii
].data
);
625 stepBreaks
[ii
].address
= breaks
[ii
];
632 /* remove step breakpoints. */
633 for (ii
= 0; ii
< 2; ++ii
)
634 if (stepBreaks
[ii
].address
!= 0)
635 target_remove_breakpoint (stepBreaks
[ii
].address
,
636 stepBreaks
[ii
].data
);
638 errno
= 0; /* FIXME, don't ignore errors! */
639 /* What errors? {read,write}_memory call error(). */
643 /* return pc value after skipping a function prologue and also return
644 information about a function frame.
646 in struct rs6000_framedata fdata:
647 - frameless is TRUE, if function does not have a frame.
648 - nosavedpc is TRUE, if function does not save %pc value in its frame.
649 - offset is the initial size of this stack frame --- the amount by
650 which we decrement the sp to allocate the frame.
651 - saved_gpr is the number of the first saved gpr.
652 - saved_fpr is the number of the first saved fpr.
653 - saved_vr is the number of the first saved vr.
654 - saved_ev is the number of the first saved ev.
655 - alloca_reg is the number of the register used for alloca() handling.
657 - gpr_offset is the offset of the first saved gpr from the previous frame.
658 - fpr_offset is the offset of the first saved fpr from the previous frame.
659 - vr_offset is the offset of the first saved vr from the previous frame.
660 - ev_offset is the offset of the first saved ev from the previous frame.
661 - lr_offset is the offset of the saved lr
662 - cr_offset is the offset of the saved cr
663 - vrsave_offset is the offset of the saved vrsave register
666 #define SIGNED_SHORT(x) \
667 ((sizeof (short) == 2) \
668 ? ((int)(short)(x)) \
669 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
671 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
673 /* Limit the number of skipped non-prologue instructions, as the examining
674 of the prologue is expensive. */
675 static int max_skip_non_prologue_insns
= 10;
677 /* Given PC representing the starting address of a function, and
678 LIM_PC which is the (sloppy) limit to which to scan when looking
679 for a prologue, attempt to further refine this limit by using
680 the line data in the symbol table. If successful, a better guess
681 on where the prologue ends is returned, otherwise the previous
682 value of lim_pc is returned. */
684 /* FIXME: cagney/2004-02-14: This function and logic have largely been
685 superseded by skip_prologue_using_sal. */
688 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
)
690 struct symtab_and_line prologue_sal
;
692 prologue_sal
= find_pc_line (pc
, 0);
693 if (prologue_sal
.line
!= 0)
696 CORE_ADDR addr
= prologue_sal
.end
;
698 /* Handle the case in which compiler's optimizer/scheduler
699 has moved instructions into the prologue. We scan ahead
700 in the function looking for address ranges whose corresponding
701 line number is less than or equal to the first one that we
702 found for the function. (It can be less than when the
703 scheduler puts a body instruction before the first prologue
705 for (i
= 2 * max_skip_non_prologue_insns
;
706 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
709 struct symtab_and_line sal
;
711 sal
= find_pc_line (addr
, 0);
714 if (sal
.line
<= prologue_sal
.line
715 && sal
.symtab
== prologue_sal
.symtab
)
722 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
723 lim_pc
= prologue_sal
.end
;
728 /* Return nonzero if the given instruction OP can be part of the prologue
729 of a function and saves a parameter on the stack. FRAMEP should be
730 set if one of the previous instructions in the function has set the
734 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
736 /* Move parameters from argument registers to temporary register. */
737 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
739 /* Rx must be scratch register r0. */
740 const int rx_regno
= (op
>> 16) & 31;
741 /* Ry: Only r3 - r10 are used for parameter passing. */
742 const int ry_regno
= GET_SRC_REG (op
);
744 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
746 *r0_contains_arg
= 1;
753 /* Save a General Purpose Register on stack. */
755 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
756 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
758 /* Rx: Only r3 - r10 are used for parameter passing. */
759 const int rx_regno
= GET_SRC_REG (op
);
761 return (rx_regno
>= 3 && rx_regno
<= 10);
764 /* Save a General Purpose Register on stack via the Frame Pointer. */
767 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
768 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
769 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
771 /* Rx: Usually, only r3 - r10 are used for parameter passing.
772 However, the compiler sometimes uses r0 to hold an argument. */
773 const int rx_regno
= GET_SRC_REG (op
);
775 return ((rx_regno
>= 3 && rx_regno
<= 10)
776 || (rx_regno
== 0 && *r0_contains_arg
));
779 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
781 /* Only f2 - f8 are used for parameter passing. */
782 const int src_regno
= GET_SRC_REG (op
);
784 return (src_regno
>= 2 && src_regno
<= 8);
787 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
789 /* Only f2 - f8 are used for parameter passing. */
790 const int src_regno
= GET_SRC_REG (op
);
792 return (src_regno
>= 2 && src_regno
<= 8);
795 /* Not an insn that saves a parameter on stack. */
800 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
802 CORE_ADDR orig_pc
= pc
;
803 CORE_ADDR last_prologue_pc
= pc
;
804 CORE_ADDR li_found_pc
= 0;
808 long vr_saved_offset
= 0;
817 int minimal_toc_loaded
= 0;
818 int prev_insn_was_prologue_insn
= 1;
819 int num_skip_non_prologue_insns
= 0;
820 int r0_contains_arg
= 0;
821 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
822 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
824 /* Attempt to find the end of the prologue when no limit is specified.
825 Note that refine_prologue_limit() has been written so that it may
826 be used to "refine" the limits of non-zero PC values too, but this
827 is only safe if we 1) trust the line information provided by the
828 compiler and 2) iterate enough to actually find the end of the
831 It may become a good idea at some point (for both performance and
832 accuracy) to unconditionally call refine_prologue_limit(). But,
833 until we can make a clear determination that this is beneficial,
834 we'll play it safe and only use it to obtain a limit when none
835 has been specified. */
837 lim_pc
= refine_prologue_limit (pc
, lim_pc
);
839 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
840 fdata
->saved_gpr
= -1;
841 fdata
->saved_fpr
= -1;
842 fdata
->saved_vr
= -1;
843 fdata
->saved_ev
= -1;
844 fdata
->alloca_reg
= -1;
845 fdata
->frameless
= 1;
846 fdata
->nosavedpc
= 1;
850 /* Sometimes it isn't clear if an instruction is a prologue
851 instruction or not. When we encounter one of these ambiguous
852 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
853 Otherwise, we'll assume that it really is a prologue instruction. */
854 if (prev_insn_was_prologue_insn
)
855 last_prologue_pc
= pc
;
857 /* Stop scanning if we've hit the limit. */
858 if (lim_pc
!= 0 && pc
>= lim_pc
)
861 prev_insn_was_prologue_insn
= 1;
863 /* Fetch the instruction and convert it to an integer. */
864 if (target_read_memory (pc
, buf
, 4))
866 op
= extract_signed_integer (buf
, 4);
868 if ((op
& 0xfc1fffff) == 0x7c0802a6)
870 /* Since shared library / PIC code, which needs to get its
871 address at runtime, can appear to save more than one link
885 remember just the first one, but skip over additional
888 lr_reg
= (op
& 0x03e00000);
893 else if ((op
& 0xfc1fffff) == 0x7c000026)
895 cr_reg
= (op
& 0x03e00000);
901 else if ((op
& 0xfc1f0000) == 0xd8010000)
902 { /* stfd Rx,NUM(r1) */
903 reg
= GET_SRC_REG (op
);
904 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
906 fdata
->saved_fpr
= reg
;
907 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
912 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
913 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
914 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
915 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
918 reg
= GET_SRC_REG (op
);
919 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
921 fdata
->saved_gpr
= reg
;
922 if ((op
& 0xfc1f0003) == 0xf8010000)
924 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
929 else if ((op
& 0xffff0000) == 0x60000000)
932 /* Allow nops in the prologue, but do not consider them to
933 be part of the prologue unless followed by other prologue
935 prev_insn_was_prologue_insn
= 0;
939 else if ((op
& 0xffff0000) == 0x3c000000)
940 { /* addis 0,0,NUM, used
942 fdata
->offset
= (op
& 0x0000ffff) << 16;
943 fdata
->frameless
= 0;
948 else if ((op
& 0xffff0000) == 0x60000000)
949 { /* ori 0,0,NUM, 2nd ha
950 lf of >= 32k frames */
951 fdata
->offset
|= (op
& 0x0000ffff);
952 fdata
->frameless
= 0;
957 else if (lr_reg
!= -1 &&
958 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
959 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
960 /* stw Rx, NUM(r1) */
961 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
962 /* stwu Rx, NUM(r1) */
963 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
964 { /* where Rx == lr */
965 fdata
->lr_offset
= offset
;
966 fdata
->nosavedpc
= 0;
968 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
969 (op
& 0xfc000000) == 0x90000000) /* stw */
971 /* Does not update r1, so add displacement to lr_offset. */
972 fdata
->lr_offset
+= SIGNED_SHORT (op
);
977 else if (cr_reg
!= -1 &&
978 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
979 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
980 /* stw Rx, NUM(r1) */
981 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
982 /* stwu Rx, NUM(r1) */
983 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
984 { /* where Rx == cr */
985 fdata
->cr_offset
= offset
;
987 if ((op
& 0xfc000003) == 0xf8000000 ||
988 (op
& 0xfc000000) == 0x90000000)
990 /* Does not update r1, so add displacement to cr_offset. */
991 fdata
->cr_offset
+= SIGNED_SHORT (op
);
996 else if (op
== 0x48000005)
1002 else if (op
== 0x48000004)
1007 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1008 in V.4 -mminimal-toc */
1009 (op
& 0xffff0000) == 0x3bde0000)
1010 { /* addi 30,30,foo@l */
1014 else if ((op
& 0xfc000001) == 0x48000001)
1018 fdata
->frameless
= 0;
1019 /* Don't skip over the subroutine call if it is not within
1020 the first three instructions of the prologue. */
1021 if ((pc
- orig_pc
) > 8)
1024 op
= read_memory_integer (pc
+ 4, 4);
1026 /* At this point, make sure this is not a trampoline
1027 function (a function that simply calls another functions,
1028 and nothing else). If the next is not a nop, this branch
1029 was part of the function prologue. */
1031 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1032 break; /* don't skip over
1037 /* update stack pointer */
1038 else if ((op
& 0xfc1f0000) == 0x94010000)
1039 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1040 fdata
->frameless
= 0;
1041 fdata
->offset
= SIGNED_SHORT (op
);
1042 offset
= fdata
->offset
;
1045 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1046 { /* stwux rX,r1,rY */
1047 /* no way to figure out what r1 is going to be */
1048 fdata
->frameless
= 0;
1049 offset
= fdata
->offset
;
1052 else if ((op
& 0xfc1f0003) == 0xf8010001)
1053 { /* stdu rX,NUM(r1) */
1054 fdata
->frameless
= 0;
1055 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1056 offset
= fdata
->offset
;
1059 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1060 { /* stdux rX,r1,rY */
1061 /* no way to figure out what r1 is going to be */
1062 fdata
->frameless
= 0;
1063 offset
= fdata
->offset
;
1066 /* Load up minimal toc pointer */
1067 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1068 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1069 && !minimal_toc_loaded
)
1071 minimal_toc_loaded
= 1;
1074 /* move parameters from argument registers to local variable
1077 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1078 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1079 (((op
>> 21) & 31) <= 10) &&
1080 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1084 /* store parameters in stack */
1086 /* Move parameters from argument registers to temporary register. */
1087 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1091 /* Set up frame pointer */
1093 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1094 || op
== 0x7c3f0b78)
1096 fdata
->frameless
= 0;
1098 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1101 /* Another way to set up the frame pointer. */
1103 else if ((op
& 0xfc1fffff) == 0x38010000)
1104 { /* addi rX, r1, 0x0 */
1105 fdata
->frameless
= 0;
1107 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1108 + ((op
& ~0x38010000) >> 21));
1111 /* AltiVec related instructions. */
1112 /* Store the vrsave register (spr 256) in another register for
1113 later manipulation, or load a register into the vrsave
1114 register. 2 instructions are used: mfvrsave and
1115 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1116 and mtspr SPR256, Rn. */
1117 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1118 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1119 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1121 vrsave_reg
= GET_SRC_REG (op
);
1124 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1128 /* Store the register where vrsave was saved to onto the stack:
1129 rS is the register where vrsave was stored in a previous
1131 /* 100100 sssss 00001 dddddddd dddddddd */
1132 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1134 if (vrsave_reg
== GET_SRC_REG (op
))
1136 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1141 /* Compute the new value of vrsave, by modifying the register
1142 where vrsave was saved to. */
1143 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1144 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1148 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1149 in a pair of insns to save the vector registers on the
1151 /* 001110 00000 00000 iiii iiii iiii iiii */
1152 /* 001110 01110 00000 iiii iiii iiii iiii */
1153 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1154 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1156 if ((op
& 0xffff0000) == 0x38000000)
1157 r0_contains_arg
= 0;
1159 vr_saved_offset
= SIGNED_SHORT (op
);
1161 /* This insn by itself is not part of the prologue, unless
1162 if part of the pair of insns mentioned above. So do not
1163 record this insn as part of the prologue yet. */
1164 prev_insn_was_prologue_insn
= 0;
1166 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1167 /* 011111 sssss 11111 00000 00111001110 */
1168 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1170 if (pc
== (li_found_pc
+ 4))
1172 vr_reg
= GET_SRC_REG (op
);
1173 /* If this is the first vector reg to be saved, or if
1174 it has a lower number than others previously seen,
1175 reupdate the frame info. */
1176 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1178 fdata
->saved_vr
= vr_reg
;
1179 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1181 vr_saved_offset
= -1;
1186 /* End AltiVec related instructions. */
1188 /* Start BookE related instructions. */
1189 /* Store gen register S at (r31+uimm).
1190 Any register less than r13 is volatile, so we don't care. */
1191 /* 000100 sssss 11111 iiiii 01100100001 */
1192 else if (arch_info
->mach
== bfd_mach_ppc_e500
1193 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1195 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1198 ev_reg
= GET_SRC_REG (op
);
1199 imm
= (op
>> 11) & 0x1f;
1200 ev_offset
= imm
* 8;
1201 /* If this is the first vector reg to be saved, or if
1202 it has a lower number than others previously seen,
1203 reupdate the frame info. */
1204 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1206 fdata
->saved_ev
= ev_reg
;
1207 fdata
->ev_offset
= ev_offset
+ offset
;
1212 /* Store gen register rS at (r1+rB). */
1213 /* 000100 sssss 00001 bbbbb 01100100000 */
1214 else if (arch_info
->mach
== bfd_mach_ppc_e500
1215 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1217 if (pc
== (li_found_pc
+ 4))
1219 ev_reg
= GET_SRC_REG (op
);
1220 /* If this is the first vector reg to be saved, or if
1221 it has a lower number than others previously seen,
1222 reupdate the frame info. */
1223 /* We know the contents of rB from the previous instruction. */
1224 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1226 fdata
->saved_ev
= ev_reg
;
1227 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1229 vr_saved_offset
= -1;
1235 /* Store gen register r31 at (rA+uimm). */
1236 /* 000100 11111 aaaaa iiiii 01100100001 */
1237 else if (arch_info
->mach
== bfd_mach_ppc_e500
1238 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1240 /* Wwe know that the source register is 31 already, but
1241 it can't hurt to compute it. */
1242 ev_reg
= GET_SRC_REG (op
);
1243 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1244 /* If this is the first vector reg to be saved, or if
1245 it has a lower number than others previously seen,
1246 reupdate the frame info. */
1247 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1249 fdata
->saved_ev
= ev_reg
;
1250 fdata
->ev_offset
= ev_offset
+ offset
;
1255 /* Store gen register S at (r31+r0).
1256 Store param on stack when offset from SP bigger than 4 bytes. */
1257 /* 000100 sssss 11111 00000 01100100000 */
1258 else if (arch_info
->mach
== bfd_mach_ppc_e500
1259 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1261 if (pc
== (li_found_pc
+ 4))
1263 if ((op
& 0x03e00000) >= 0x01a00000)
1265 ev_reg
= GET_SRC_REG (op
);
1266 /* If this is the first vector reg to be saved, or if
1267 it has a lower number than others previously seen,
1268 reupdate the frame info. */
1269 /* We know the contents of r0 from the previous
1271 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1273 fdata
->saved_ev
= ev_reg
;
1274 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1278 vr_saved_offset
= -1;
1283 /* End BookE related instructions. */
1287 /* Not a recognized prologue instruction.
1288 Handle optimizer code motions into the prologue by continuing
1289 the search if we have no valid frame yet or if the return
1290 address is not yet saved in the frame. */
1291 if (fdata
->frameless
== 0
1292 && (lr_reg
== -1 || fdata
->nosavedpc
== 0))
1295 if (op
== 0x4e800020 /* blr */
1296 || op
== 0x4e800420) /* bctr */
1297 /* Do not scan past epilogue in frameless functions or
1300 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1301 /* Never skip branches. */
1304 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1305 /* Do not scan too many insns, scanning insns is expensive with
1309 /* Continue scanning. */
1310 prev_insn_was_prologue_insn
= 0;
1316 /* I have problems with skipping over __main() that I need to address
1317 * sometime. Previously, I used to use misc_function_vector which
1318 * didn't work as well as I wanted to be. -MGO */
1320 /* If the first thing after skipping a prolog is a branch to a function,
1321 this might be a call to an initializer in main(), introduced by gcc2.
1322 We'd like to skip over it as well. Fortunately, xlc does some extra
1323 work before calling a function right after a prologue, thus we can
1324 single out such gcc2 behaviour. */
1327 if ((op
& 0xfc000001) == 0x48000001)
1328 { /* bl foo, an initializer function? */
1329 op
= read_memory_integer (pc
+ 4, 4);
1331 if (op
== 0x4def7b82)
1332 { /* cror 0xf, 0xf, 0xf (nop) */
1334 /* Check and see if we are in main. If so, skip over this
1335 initializer function as well. */
1337 tmp
= find_pc_misc_function (pc
);
1339 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1345 fdata
->offset
= -fdata
->offset
;
1346 return last_prologue_pc
;
1350 /*************************************************************************
1351 Support for creating pushing a dummy frame into the stack, and popping
1353 *************************************************************************/
1356 /* All the ABI's require 16 byte alignment. */
1358 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1360 return (addr
& -16);
1363 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1364 the first eight words of the argument list (that might be less than
1365 eight parameters if some parameters occupy more than one word) are
1366 passed in r3..r10 registers. float and double parameters are
1367 passed in fpr's, in addition to that. Rest of the parameters if any
1368 are passed in user stack. There might be cases in which half of the
1369 parameter is copied into registers, the other half is pushed into
1372 Stack must be aligned on 64-bit boundaries when synthesizing
1375 If the function is returning a structure, then the return address is passed
1376 in r3, then the first 7 words of the parameters can be passed in registers,
1377 starting from r4. */
1380 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1381 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1382 int nargs
, struct value
**args
, CORE_ADDR sp
,
1383 int struct_return
, CORE_ADDR struct_addr
)
1385 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1388 int argno
; /* current argument number */
1389 int argbytes
; /* current argument byte */
1390 char tmp_buffer
[50];
1391 int f_argno
= 0; /* current floating point argno */
1392 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1393 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1395 struct value
*arg
= 0;
1400 /* The calling convention this function implements assumes the
1401 processor has floating-point registers. We shouldn't be using it
1402 on PPC variants that lack them. */
1403 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1405 /* The first eight words of ther arguments are passed in registers.
1406 Copy them appropriately. */
1409 /* If the function is returning a `struct', then the first word
1410 (which will be passed in r3) is used for struct return address.
1411 In that case we should advance one word and start from r4
1412 register to copy parameters. */
1415 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1421 effectively indirect call... gcc does...
1423 return_val example( float, int);
1426 float in fp0, int in r3
1427 offset of stack on overflow 8/16
1428 for varargs, must go by type.
1430 float in r3&r4, int in r5
1431 offset of stack on overflow different
1433 return in r3 or f0. If no float, must study how gcc emulates floats;
1434 pay attention to arg promotion.
1435 User may have to cast\args to handle promotion correctly
1436 since gdb won't know if prototype supplied or not.
1439 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1441 int reg_size
= register_size (current_gdbarch
, ii
+ 3);
1444 type
= check_typedef (VALUE_TYPE (arg
));
1445 len
= TYPE_LENGTH (type
);
1447 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1450 /* Floating point arguments are passed in fpr's, as well as gpr's.
1451 There are 13 fpr's reserved for passing parameters. At this point
1452 there is no way we would run out of them. */
1455 printf_unfiltered ("Fatal Error: a floating point parameter "
1456 "#%d with a size > 8 is found!\n", argno
);
1458 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE
1459 (tdep
->ppc_fp0_regnum
+ 1 + f_argno
)],
1460 VALUE_CONTENTS (arg
),
1468 /* Argument takes more than one register. */
1469 while (argbytes
< len
)
1471 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0,
1473 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)],
1474 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1475 (len
- argbytes
) > reg_size
1476 ? reg_size
: len
- argbytes
);
1477 ++ii
, argbytes
+= reg_size
;
1480 goto ran_out_of_registers_for_arguments
;
1487 /* Argument can fit in one register. No problem. */
1488 int adj
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1489 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0, reg_size
);
1490 memcpy ((char *)&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)] + adj
,
1491 VALUE_CONTENTS (arg
), len
);
1496 ran_out_of_registers_for_arguments
:
1498 saved_sp
= read_sp ();
1500 /* Location for 8 parameters are always reserved. */
1503 /* Another six words for back chain, TOC register, link register, etc. */
1506 /* Stack pointer must be quadword aligned. */
1509 /* If there are more arguments, allocate space for them in
1510 the stack, then push them starting from the ninth one. */
1512 if ((argno
< nargs
) || argbytes
)
1518 space
+= ((len
- argbytes
+ 3) & -4);
1524 for (; jj
< nargs
; ++jj
)
1526 struct value
*val
= args
[jj
];
1527 space
+= ((TYPE_LENGTH (VALUE_TYPE (val
))) + 3) & -4;
1530 /* Add location required for the rest of the parameters. */
1531 space
= (space
+ 15) & -16;
1534 /* This is another instance we need to be concerned about
1535 securing our stack space. If we write anything underneath %sp
1536 (r1), we might conflict with the kernel who thinks he is free
1537 to use this area. So, update %sp first before doing anything
1540 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1542 /* If the last argument copied into the registers didn't fit there
1543 completely, push the rest of it into stack. */
1547 write_memory (sp
+ 24 + (ii
* 4),
1548 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1551 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1554 /* Push the rest of the arguments into stack. */
1555 for (; argno
< nargs
; ++argno
)
1559 type
= check_typedef (VALUE_TYPE (arg
));
1560 len
= TYPE_LENGTH (type
);
1563 /* Float types should be passed in fpr's, as well as in the
1565 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1569 printf_unfiltered ("Fatal Error: a floating point parameter"
1570 " #%d with a size > 8 is found!\n", argno
);
1572 memcpy (&(deprecated_registers
1573 [DEPRECATED_REGISTER_BYTE
1574 (tdep
->ppc_fp0_regnum
+ 1 + f_argno
)]),
1575 VALUE_CONTENTS (arg
),
1580 write_memory (sp
+ 24 + (ii
* 4),
1581 (char *) VALUE_CONTENTS (arg
),
1583 ii
+= ((len
+ 3) & -4) / 4;
1587 /* Set the stack pointer. According to the ABI, the SP is meant to
1588 be set _before_ the corresponding stack space is used. On AIX,
1589 this even applies when the target has been completely stopped!
1590 Not doing this can lead to conflicts with the kernel which thinks
1591 that it still has control over this not-yet-allocated stack
1593 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1595 /* Set back chain properly. */
1596 store_unsigned_integer (tmp_buffer
, 4, saved_sp
);
1597 write_memory (sp
, tmp_buffer
, 4);
1599 /* Point the inferior function call's return address at the dummy's
1601 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1603 /* Set the TOC register, get the value from the objfile reader
1604 which, in turn, gets it from the VMAP table. */
1605 if (rs6000_find_toc_address_hook
!= NULL
)
1607 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1608 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1611 target_store_registers (-1);
1615 /* PowerOpen always puts structures in memory. Vectors, which were
1616 added later, do get returned in a register though. */
1619 rs6000_use_struct_convention (int gcc_p
, struct type
*value_type
)
1621 if ((TYPE_LENGTH (value_type
) == 16 || TYPE_LENGTH (value_type
) == 8)
1622 && TYPE_VECTOR (value_type
))
1628 rs6000_extract_return_value (struct type
*valtype
, char *regbuf
, char *valbuf
)
1631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1633 /* The calling convention this function implements assumes the
1634 processor has floating-point registers. We shouldn't be using it
1635 on PPC variants that lack them. */
1636 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1638 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
)
1641 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1642 We need to truncate the return value into float size (4 byte) if
1645 convert_typed_floating (®buf
[DEPRECATED_REGISTER_BYTE
1646 (tdep
->ppc_fp0_regnum
+ 1)],
1647 builtin_type_double
,
1651 else if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
1652 && TYPE_LENGTH (valtype
) == 16
1653 && TYPE_VECTOR (valtype
))
1655 memcpy (valbuf
, regbuf
+ DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1656 TYPE_LENGTH (valtype
));
1660 /* return value is copied starting from r3. */
1661 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1662 && TYPE_LENGTH (valtype
) < register_size (current_gdbarch
, 3))
1663 offset
= register_size (current_gdbarch
, 3) - TYPE_LENGTH (valtype
);
1666 regbuf
+ DEPRECATED_REGISTER_BYTE (3) + offset
,
1667 TYPE_LENGTH (valtype
));
1671 /* Return whether handle_inferior_event() should proceed through code
1672 starting at PC in function NAME when stepping.
1674 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1675 handle memory references that are too distant to fit in instructions
1676 generated by the compiler. For example, if 'foo' in the following
1681 is greater than 32767, the linker might replace the lwz with a branch to
1682 somewhere in @FIX1 that does the load in 2 instructions and then branches
1683 back to where execution should continue.
1685 GDB should silently step over @FIX code, just like AIX dbx does.
1686 Unfortunately, the linker uses the "b" instruction for the branches,
1687 meaning that the link register doesn't get set. Therefore, GDB's usual
1688 step_over_function() mechanism won't work.
1690 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1691 in handle_inferior_event() to skip past @FIX code. */
1694 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1696 return name
&& !strncmp (name
, "@FIX", 4);
1699 /* Skip code that the user doesn't want to see when stepping:
1701 1. Indirect function calls use a piece of trampoline code to do context
1702 switching, i.e. to set the new TOC table. Skip such code if we are on
1703 its first instruction (as when we have single-stepped to here).
1705 2. Skip shared library trampoline code (which is different from
1706 indirect function call trampolines).
1708 3. Skip bigtoc fixup code.
1710 Result is desired PC to step until, or NULL if we are not in
1711 code that should be skipped. */
1714 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1716 unsigned int ii
, op
;
1718 CORE_ADDR solib_target_pc
;
1719 struct minimal_symbol
*msymbol
;
1721 static unsigned trampoline_code
[] =
1723 0x800b0000, /* l r0,0x0(r11) */
1724 0x90410014, /* st r2,0x14(r1) */
1725 0x7c0903a6, /* mtctr r0 */
1726 0x804b0004, /* l r2,0x4(r11) */
1727 0x816b0008, /* l r11,0x8(r11) */
1728 0x4e800420, /* bctr */
1729 0x4e800020, /* br */
1733 /* Check for bigtoc fixup code. */
1734 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1735 if (msymbol
&& rs6000_in_solib_return_trampoline (pc
, DEPRECATED_SYMBOL_NAME (msymbol
)))
1737 /* Double-check that the third instruction from PC is relative "b". */
1738 op
= read_memory_integer (pc
+ 8, 4);
1739 if ((op
& 0xfc000003) == 0x48000000)
1741 /* Extract bits 6-29 as a signed 24-bit relative word address and
1742 add it to the containing PC. */
1743 rel
= ((int)(op
<< 6) >> 6);
1744 return pc
+ 8 + rel
;
1748 /* If pc is in a shared library trampoline, return its target. */
1749 solib_target_pc
= find_solib_trampoline_target (pc
);
1750 if (solib_target_pc
)
1751 return solib_target_pc
;
1753 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1755 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1756 if (op
!= trampoline_code
[ii
])
1759 ii
= read_register (11); /* r11 holds destination addr */
1760 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
1764 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1765 isn't available with that word size, return 0. */
1768 regsize (const struct reg
*reg
, int wordsize
)
1770 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
1773 /* Return the name of register number N, or null if no such register exists
1774 in the current architecture. */
1777 rs6000_register_name (int n
)
1779 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1780 const struct reg
*reg
= tdep
->regs
+ n
;
1782 if (!regsize (reg
, tdep
->wordsize
))
1787 /* Return the GDB type object for the "standard" data type
1788 of data in register N. */
1790 static struct type
*
1791 rs6000_register_type (struct gdbarch
*gdbarch
, int n
)
1793 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1794 const struct reg
*reg
= tdep
->regs
+ n
;
1797 return builtin_type_double
;
1800 int size
= regsize (reg
, tdep
->wordsize
);
1804 return builtin_type_int0
;
1806 return builtin_type_uint32
;
1808 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
1809 return builtin_type_vec64
;
1811 return builtin_type_uint64
;
1814 return builtin_type_vec128
;
1817 internal_error (__FILE__
, __LINE__
, "Register %d size %d unknown",
1823 /* The register format for RS/6000 floating point registers is always
1824 double, we need a conversion if the memory format is float. */
1827 rs6000_convert_register_p (int regnum
, struct type
*type
)
1829 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
1832 && TYPE_CODE (type
) == TYPE_CODE_FLT
1833 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
1837 rs6000_register_to_value (struct frame_info
*frame
,
1842 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
1843 char from
[MAX_REGISTER_SIZE
];
1845 gdb_assert (reg
->fpr
);
1846 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
1848 get_frame_register (frame
, regnum
, from
);
1849 convert_typed_floating (from
, builtin_type_double
, to
, type
);
1853 rs6000_value_to_register (struct frame_info
*frame
,
1858 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
1859 char to
[MAX_REGISTER_SIZE
];
1861 gdb_assert (reg
->fpr
);
1862 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
1864 convert_typed_floating (from
, type
, to
, builtin_type_double
);
1865 put_frame_register (frame
, regnum
, to
);
1869 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1870 int reg_nr
, void *buffer
)
1874 char temp_buffer
[MAX_REGISTER_SIZE
];
1875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1877 if (reg_nr
>= tdep
->ppc_gp0_regnum
1878 && reg_nr
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
1880 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1882 /* Build the value in the provided buffer. */
1883 /* Read the raw register of which this one is the lower portion. */
1884 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1885 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1887 memcpy ((char *) buffer
, temp_buffer
+ offset
, 4);
1892 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1893 int reg_nr
, const void *buffer
)
1897 char temp_buffer
[MAX_REGISTER_SIZE
];
1898 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1900 if (reg_nr
>= tdep
->ppc_gp0_regnum
1901 && reg_nr
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
1903 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1904 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1905 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1908 /* Let's read the value of the base register into a temporary
1909 buffer, so that overwriting the last four bytes with the new
1910 value of the pseudo will leave the upper 4 bytes unchanged. */
1911 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1913 /* Write as an 8 byte quantity. */
1914 memcpy (temp_buffer
+ offset
, (char *) buffer
, 4);
1915 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1919 /* Convert a DBX STABS register number to a GDB register number. */
1921 rs6000_stab_reg_to_regnum (int num
)
1923 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1925 if (0 <= num
&& num
<= 31)
1926 return tdep
->ppc_gp0_regnum
+ num
;
1927 else if (32 <= num
&& num
<= 63)
1928 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1929 specifies registers the architecture doesn't have? Our
1930 callers don't check the value we return. */
1931 return tdep
->ppc_fp0_regnum
+ (num
- 32);
1932 else if (77 <= num
&& num
<= 108)
1933 return tdep
->ppc_vr0_regnum
+ (num
- 77);
1934 else if (1200 <= num
&& num
< 1200 + 32)
1935 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
1940 return tdep
->ppc_mq_regnum
;
1942 return tdep
->ppc_lr_regnum
;
1944 return tdep
->ppc_ctr_regnum
;
1946 return tdep
->ppc_xer_regnum
;
1948 return tdep
->ppc_vrsave_regnum
;
1950 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
1952 return tdep
->ppc_acc_regnum
;
1954 return tdep
->ppc_spefscr_regnum
;
1961 /* Convert a Dwarf 2 register number to a GDB register number. */
1963 rs6000_dwarf2_reg_to_regnum (int num
)
1965 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1967 if (0 <= num
&& num
<= 31)
1968 return tdep
->ppc_gp0_regnum
+ num
;
1969 else if (32 <= num
&& num
<= 63)
1970 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1971 specifies registers the architecture doesn't have? Our
1972 callers don't check the value we return. */
1973 return tdep
->ppc_fp0_regnum
+ (num
- 32);
1974 else if (1124 <= num
&& num
< 1124 + 32)
1975 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
1976 else if (1200 <= num
&& num
< 1200 + 32)
1977 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
1982 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
1984 return tdep
->ppc_acc_regnum
;
1986 return tdep
->ppc_mq_regnum
;
1988 return tdep
->ppc_xer_regnum
;
1990 return tdep
->ppc_lr_regnum
;
1992 return tdep
->ppc_ctr_regnum
;
1994 return tdep
->ppc_vrsave_regnum
;
1996 return tdep
->ppc_spefscr_regnum
;
2004 rs6000_store_return_value (struct type
*type
,
2005 struct regcache
*regcache
,
2008 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2009 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2012 /* The calling convention this function implements assumes the
2013 processor has floating-point registers. We shouldn't be using it
2014 on PPC variants that lack them. */
2015 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
2017 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2018 /* Floating point values are returned starting from FPR1 and up.
2019 Say a double_double_double type could be returned in
2020 FPR1/FPR2/FPR3 triple. */
2021 regnum
= tdep
->ppc_fp0_regnum
+ 1;
2022 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2024 if (TYPE_LENGTH (type
) == 16
2025 && TYPE_VECTOR (type
))
2026 regnum
= tdep
->ppc_vr0_regnum
+ 2;
2031 /* Everything else is returned in GPR3 and up. */
2032 regnum
= tdep
->ppc_gp0_regnum
+ 3;
2035 size_t bytes_written
= 0;
2037 while (bytes_written
< TYPE_LENGTH (type
))
2039 /* How much of this value can we write to this register? */
2040 size_t bytes_to_write
= min (TYPE_LENGTH (type
) - bytes_written
,
2041 register_size (gdbarch
, regnum
));
2042 regcache_cooked_write_part (regcache
, regnum
,
2044 (char *) valbuf
+ bytes_written
);
2046 bytes_written
+= bytes_to_write
;
2052 /* Extract from an array REGBUF containing the (raw) register state
2053 the address in which a function should return its structure value,
2054 as a CORE_ADDR (or an expression that can be used as one). */
2057 rs6000_extract_struct_value_address (struct regcache
*regcache
)
2059 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2060 function call GDB knows the address of the struct return value
2061 and hence, should not need to call this function. Unfortunately,
2062 the current call_function_by_hand() code only saves the most
2063 recent struct address leading to occasional calls. The code
2064 should instead maintain a stack of such addresses (in the dummy
2066 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2067 really got no idea where the return value is being stored. While
2068 r3, on function entry, contained the address it will have since
2069 been reused (scratch) and hence wouldn't be valid */
2073 /* Hook called when a new child process is started. */
2076 rs6000_create_inferior (int pid
)
2078 if (rs6000_set_host_arch_hook
)
2079 rs6000_set_host_arch_hook (pid
);
2082 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2084 Usually a function pointer's representation is simply the address
2085 of the function. On the RS/6000 however, a function pointer is
2086 represented by a pointer to a TOC entry. This TOC entry contains
2087 three words, the first word is the address of the function, the
2088 second word is the TOC pointer (r2), and the third word is the
2089 static chain value. Throughout GDB it is currently assumed that a
2090 function pointer contains the address of the function, which is not
2091 easy to fix. In addition, the conversion of a function address to
2092 a function pointer would require allocation of a TOC entry in the
2093 inferior's memory space, with all its drawbacks. To be able to
2094 call C++ virtual methods in the inferior (which are called via
2095 function pointers), find_function_addr uses this function to get the
2096 function address from a function pointer. */
2098 /* Return real function address if ADDR (a function pointer) is in the data
2099 space and is therefore a special function pointer. */
2102 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
2104 struct target_ops
*targ
)
2106 struct obj_section
*s
;
2108 s
= find_pc_section (addr
);
2109 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
2112 /* ADDR is in the data space, so it's a special function pointer. */
2113 return read_memory_addr (addr
, gdbarch_tdep (current_gdbarch
)->wordsize
);
2117 /* Handling the various POWER/PowerPC variants. */
2120 /* The arrays here called registers_MUMBLE hold information about available
2123 For each family of PPC variants, I've tried to isolate out the
2124 common registers and put them up front, so that as long as you get
2125 the general family right, GDB will correctly identify the registers
2126 common to that family. The common register sets are:
2128 For the 60x family: hid0 hid1 iabr dabr pir
2130 For the 505 and 860 family: eie eid nri
2132 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2133 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2136 Most of these register groups aren't anything formal. I arrived at
2137 them by looking at the registers that occurred in more than one
2140 Note: kevinb/2002-04-30: Support for the fpscr register was added
2141 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2142 for Power. For PowerPC, slot 70 was unused and was already in the
2143 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2144 slot 70 was being used for "mq", so the next available slot (71)
2145 was chosen. It would have been nice to be able to make the
2146 register numbers the same across processor cores, but this wasn't
2147 possible without either 1) renumbering some registers for some
2148 processors or 2) assigning fpscr to a really high slot that's
2149 larger than any current register number. Doing (1) is bad because
2150 existing stubs would break. Doing (2) is undesirable because it
2151 would introduce a really large gap between fpscr and the rest of
2152 the registers for most processors. */
2154 /* Convenience macros for populating register arrays. */
2156 /* Within another macro, convert S to a string. */
2160 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2161 and 64 bits on 64-bit systems. */
2162 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2164 /* Return a struct reg defining register NAME that's 32 bits on all
2166 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2168 /* Return a struct reg defining register NAME that's 64 bits on all
2170 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2172 /* Return a struct reg defining register NAME that's 128 bits on all
2174 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2176 /* Return a struct reg defining floating-point register NAME. */
2177 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2179 /* Return a struct reg defining a pseudo register NAME. */
2180 #define P(name) { STR(name), 4, 8, 0, 1, -1 }
2182 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2183 systems and that doesn't exist on 64-bit systems. */
2184 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2186 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2187 systems and that doesn't exist on 32-bit systems. */
2188 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2190 /* Return a struct reg placeholder for a register that doesn't exist. */
2191 #define R0 { 0, 0, 0, 0, 0, -1 }
2193 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2194 32-bit systems and 64 bits on 64-bit systems. */
2195 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2197 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2199 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2201 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2202 all systems, and whose SPR number is NUMBER. */
2203 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2205 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2206 64-bit systems and that doesn't exist on 32-bit systems. */
2207 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2209 /* UISA registers common across all architectures, including POWER. */
2211 #define COMMON_UISA_REGS \
2212 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2213 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2214 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2215 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2216 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2217 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2218 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2219 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2220 /* 64 */ R(pc), R(ps)
2222 /* UISA-level SPRs for PowerPC. */
2223 #define PPC_UISA_SPRS \
2224 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2226 /* UISA-level SPRs for PowerPC without floating point support. */
2227 #define PPC_UISA_NOFP_SPRS \
2228 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2230 /* Segment registers, for PowerPC. */
2231 #define PPC_SEGMENT_REGS \
2232 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2233 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2234 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2235 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2237 /* OEA SPRs for PowerPC. */
2238 #define PPC_OEA_SPRS \
2240 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2241 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2242 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2243 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2244 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2245 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2246 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2247 /* 116 */ S4(dec), S(dabr), S4(ear)
2249 /* AltiVec registers. */
2250 #define PPC_ALTIVEC_REGS \
2251 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2252 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2253 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2254 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2255 /*151*/R4(vscr), R4(vrsave)
2257 /* Vectors of hi-lo general purpose registers. */
2258 #define PPC_EV_REGS \
2259 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2260 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2261 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2262 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2264 /* Lower half of the EV registers. */
2265 #define PPC_GPRS_PSEUDO_REGS \
2266 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2267 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2268 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
2269 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
2271 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2272 user-level SPR's. */
2273 static const struct reg registers_power
[] =
2276 /* 66 */ R4(cnd
), S(lr
), S(cnt
), S4(xer
), S4(mq
),
2280 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2281 view of the PowerPC. */
2282 static const struct reg registers_powerpc
[] =
2291 Some notes about the "tcr" special-purpose register:
2292 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2293 403's programmable interval timer, fixed interval timer, and
2295 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2296 watchdog timer, and nothing else.
2298 Some of the fields are similar between the two, but they're not
2299 compatible with each other. Since the two variants have different
2300 registers, with different numbers, but the same name, we can't
2301 splice the register name to get the SPR number. */
2302 static const struct reg registers_403
[] =
2308 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2309 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2310 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2311 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2312 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2313 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
)
2316 /* IBM PowerPC 403GC.
2317 See the comments about 'tcr' for the 403, above. */
2318 static const struct reg registers_403GC
[] =
2324 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2325 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2326 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2327 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2328 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2329 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
),
2330 /* 143 */ S(zpr
), S(pid
), S(sgr
), S(dcwr
),
2331 /* 147 */ S(tbhu
), S(tblu
)
2334 /* Motorola PowerPC 505. */
2335 static const struct reg registers_505
[] =
2341 /* 119 */ S(eie
), S(eid
), S(nri
)
2344 /* Motorola PowerPC 860 or 850. */
2345 static const struct reg registers_860
[] =
2351 /* 119 */ S(eie
), S(eid
), S(nri
), S(cmpa
),
2352 /* 123 */ S(cmpb
), S(cmpc
), S(cmpd
), S(icr
),
2353 /* 127 */ S(der
), S(counta
), S(countb
), S(cmpe
),
2354 /* 131 */ S(cmpf
), S(cmpg
), S(cmph
), S(lctrl1
),
2355 /* 135 */ S(lctrl2
), S(ictrl
), S(bar
), S(ic_cst
),
2356 /* 139 */ S(ic_adr
), S(ic_dat
), S(dc_cst
), S(dc_adr
),
2357 /* 143 */ S(dc_dat
), S(dpdr
), S(dpir
), S(immr
),
2358 /* 147 */ S(mi_ctr
), S(mi_ap
), S(mi_epn
), S(mi_twc
),
2359 /* 151 */ S(mi_rpn
), S(md_ctr
), S(m_casid
), S(md_ap
),
2360 /* 155 */ S(md_epn
), S(m_twb
), S(md_twc
), S(md_rpn
),
2361 /* 159 */ S(m_tw
), S(mi_dbcam
), S(mi_dbram0
), S(mi_dbram1
),
2362 /* 163 */ S(md_dbcam
), S(md_dbram0
), S(md_dbram1
)
2365 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2366 for reading and writing RTCU and RTCL. However, how one reads and writes a
2367 register is the stub's problem. */
2368 static const struct reg registers_601
[] =
2374 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2375 /* 123 */ S(pir
), S(mq
), S(rtcu
), S(rtcl
)
2378 /* Motorola PowerPC 602.
2379 See the notes under the 403 about 'tcr'. */
2380 static const struct reg registers_602
[] =
2386 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2387 /* 123 */ R0
, SN4(tcr
, ppc_spr_602_tcr
), S(ibr
), S(esasrr
),
2388 /* 127 */ S(sebr
), S(ser
), S(sp
), S(lt
)
2391 /* Motorola/IBM PowerPC 603 or 603e. */
2392 static const struct reg registers_603
[] =
2398 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2399 /* 123 */ R0
, S(dmiss
), S(dcmp
), S(hash1
),
2400 /* 127 */ S(hash2
), S(imiss
), S(icmp
), S(rpa
)
2403 /* Motorola PowerPC 604 or 604e. */
2404 static const struct reg registers_604
[] =
2410 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2411 /* 123 */ S(pir
), S(mmcr0
), S(pmc1
), S(pmc2
),
2412 /* 127 */ S(sia
), S(sda
)
2415 /* Motorola/IBM PowerPC 750 or 740. */
2416 static const struct reg registers_750
[] =
2422 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2423 /* 123 */ R0
, S(ummcr0
), S(upmc1
), S(upmc2
),
2424 /* 127 */ S(usia
), S(ummcr1
), S(upmc3
), S(upmc4
),
2425 /* 131 */ S(mmcr0
), S(pmc1
), S(pmc2
), S(sia
),
2426 /* 135 */ S(mmcr1
), S(pmc3
), S(pmc4
), S(l2cr
),
2427 /* 139 */ S(ictc
), S(thrm1
), S(thrm2
), S(thrm3
)
2431 /* Motorola PowerPC 7400. */
2432 static const struct reg registers_7400
[] =
2434 /* gpr0-gpr31, fpr0-fpr31 */
2436 /* cr, lr, ctr, xer, fpscr */
2441 /* vr0-vr31, vrsave, vscr */
2443 /* FIXME? Add more registers? */
2446 /* Motorola e500. */
2447 static const struct reg registers_e500
[] =
2450 /* cr, lr, ctr, xer, "" */
2454 R8(acc
), S4(spefscr
),
2455 /* NOTE: Add new registers here the end of the raw register
2456 list and just before the first pseudo register. */
2458 PPC_GPRS_PSEUDO_REGS
2461 /* Information about a particular processor variant. */
2465 /* Name of this variant. */
2468 /* English description of the variant. */
2471 /* bfd_arch_info.arch corresponding to variant. */
2472 enum bfd_architecture arch
;
2474 /* bfd_arch_info.mach corresponding to variant. */
2477 /* Number of real registers. */
2480 /* Number of pseudo registers. */
2483 /* Number of total registers (the sum of nregs and npregs). */
2486 /* Table of register names; registers[R] is the name of the register
2488 const struct reg
*regs
;
2491 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2494 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2499 for (i
= 0; i
< num_tot_regs
; i
++)
2500 if (!reg_list
[i
].pseudo
)
2507 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2512 for (i
= 0; i
< num_tot_regs
; i
++)
2513 if (reg_list
[i
].pseudo
)
2519 /* Information in this table comes from the following web sites:
2520 IBM: http://www.chips.ibm.com:80/products/embedded/
2521 Motorola: http://www.mot.com/SPS/PowerPC/
2523 I'm sure I've got some of the variant descriptions not quite right.
2524 Please report any inaccuracies you find to GDB's maintainer.
2526 If you add entries to this table, please be sure to allow the new
2527 value as an argument to the --with-cpu flag, in configure.in. */
2529 static struct variant variants
[] =
2532 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2533 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2535 {"power", "POWER user-level", bfd_arch_rs6000
,
2536 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2538 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2539 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2541 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2542 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2544 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2545 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2547 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2548 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2550 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2551 604, -1, -1, tot_num_registers (registers_604
),
2553 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2554 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2556 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2557 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2559 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2560 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2562 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2563 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2565 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2566 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2568 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2569 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2573 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2574 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2576 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2577 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2579 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2580 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2582 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2583 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2585 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2586 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2588 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2589 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2592 /* FIXME: I haven't checked the register sets of the following. */
2593 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2594 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2596 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2597 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2599 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2600 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2603 {0, 0, 0, 0, 0, 0, 0, 0}
2606 /* Initialize the number of registers and pseudo registers in each variant. */
2609 init_variants (void)
2613 for (v
= variants
; v
->name
; v
++)
2616 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
2617 if (v
->npregs
== -1)
2618 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
2622 /* Return the variant corresponding to architecture ARCH and machine number
2623 MACH. If no such variant exists, return null. */
2625 static const struct variant
*
2626 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2628 const struct variant
*v
;
2630 for (v
= variants
; v
->name
; v
++)
2631 if (arch
== v
->arch
&& mach
== v
->mach
)
2638 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2640 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2641 return print_insn_big_powerpc (memaddr
, info
);
2643 return print_insn_little_powerpc (memaddr
, info
);
2647 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2649 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2652 static struct frame_id
2653 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2655 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
2657 frame_pc_unwind (next_frame
));
2660 struct rs6000_frame_cache
2663 CORE_ADDR initial_sp
;
2664 struct trad_frame_saved_reg
*saved_regs
;
2667 static struct rs6000_frame_cache
*
2668 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2670 struct rs6000_frame_cache
*cache
;
2671 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2672 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2673 struct rs6000_framedata fdata
;
2674 int wordsize
= tdep
->wordsize
;
2676 if ((*this_cache
) != NULL
)
2677 return (*this_cache
);
2678 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2679 (*this_cache
) = cache
;
2680 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2682 skip_prologue (frame_func_unwind (next_frame
), frame_pc_unwind (next_frame
),
2685 /* If there were any saved registers, figure out parent's stack
2687 /* The following is true only if the frame doesn't have a call to
2690 if (fdata
.saved_fpr
== 0
2691 && fdata
.saved_gpr
== 0
2692 && fdata
.saved_vr
== 0
2693 && fdata
.saved_ev
== 0
2694 && fdata
.lr_offset
== 0
2695 && fdata
.cr_offset
== 0
2696 && fdata
.vr_offset
== 0
2697 && fdata
.ev_offset
== 0)
2698 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2701 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2702 address of the current frame. Things might be easier if the
2703 ->frame pointed to the outer-most address of the frame. In
2704 the mean time, the address of the prev frame is used as the
2705 base address of this frame. */
2706 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2707 if (!fdata
.frameless
)
2708 /* Frameless really means stackless. */
2709 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
2711 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
2713 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2714 All fpr's from saved_fpr to fp31 are saved. */
2716 if (fdata
.saved_fpr
>= 0)
2719 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2721 /* If skip_prologue says floating-point registers were saved,
2722 but the current architecture has no floating-point registers,
2723 then that's strange. But we have no indices to even record
2724 the addresses under, so we just ignore it. */
2725 if (ppc_floating_point_unit_p (gdbarch
))
2726 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
2728 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2733 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2734 All gpr's from saved_gpr to gpr31 are saved. */
2736 if (fdata
.saved_gpr
>= 0)
2739 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2740 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
2742 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2743 gpr_addr
+= wordsize
;
2747 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2748 All vr's from saved_vr to vr31 are saved. */
2749 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2751 if (fdata
.saved_vr
>= 0)
2754 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2755 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2757 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2758 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2763 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2764 All vr's from saved_ev to ev31 are saved. ????? */
2765 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
2767 if (fdata
.saved_ev
>= 0)
2770 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2771 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
2773 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2774 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2775 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2780 /* If != 0, fdata.cr_offset is the offset from the frame that
2782 if (fdata
.cr_offset
!= 0)
2783 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2785 /* If != 0, fdata.lr_offset is the offset from the frame that
2787 if (fdata
.lr_offset
!= 0)
2788 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2789 /* The PC is found in the link register. */
2790 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2792 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2793 holds the VRSAVE. */
2794 if (fdata
.vrsave_offset
!= 0)
2795 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2797 if (fdata
.alloca_reg
< 0)
2798 /* If no alloca register used, then fi->frame is the value of the
2799 %sp for this frame, and it is good enough. */
2800 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2802 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
2809 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2810 struct frame_id
*this_id
)
2812 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2814 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2818 rs6000_frame_prev_register (struct frame_info
*next_frame
,
2820 int regnum
, int *optimizedp
,
2821 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2822 int *realnump
, void *valuep
)
2824 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2826 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2827 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2830 static const struct frame_unwind rs6000_frame_unwind
=
2833 rs6000_frame_this_id
,
2834 rs6000_frame_prev_register
2837 static const struct frame_unwind
*
2838 rs6000_frame_sniffer (struct frame_info
*next_frame
)
2840 return &rs6000_frame_unwind
;
2846 rs6000_frame_base_address (struct frame_info
*next_frame
,
2849 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2851 return info
->initial_sp
;
2854 static const struct frame_base rs6000_frame_base
= {
2855 &rs6000_frame_unwind
,
2856 rs6000_frame_base_address
,
2857 rs6000_frame_base_address
,
2858 rs6000_frame_base_address
2861 static const struct frame_base
*
2862 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
2864 return &rs6000_frame_base
;
2867 /* Initialize the current architecture based on INFO. If possible, re-use an
2868 architecture from ARCHES, which is a list of architectures already created
2869 during this debugging session.
2871 Called e.g. at program startup, when reading a core file, and when reading
2874 static struct gdbarch
*
2875 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2877 struct gdbarch
*gdbarch
;
2878 struct gdbarch_tdep
*tdep
;
2879 int wordsize
, from_xcoff_exec
, from_elf_exec
, i
, off
;
2881 const struct variant
*v
;
2882 enum bfd_architecture arch
;
2888 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2889 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2891 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2892 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2894 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2896 /* Check word size. If INFO is from a binary file, infer it from
2897 that, else choose a likely default. */
2898 if (from_xcoff_exec
)
2900 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2905 else if (from_elf_exec
)
2907 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2914 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2915 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2916 info
.bfd_arch_info
->bits_per_byte
;
2921 /* Find a candidate among extant architectures. */
2922 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2924 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2926 /* Word size in the various PowerPC bfd_arch_info structs isn't
2927 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2928 separate word size check. */
2929 tdep
= gdbarch_tdep (arches
->gdbarch
);
2930 if (tdep
&& tdep
->wordsize
== wordsize
)
2931 return arches
->gdbarch
;
2934 /* None found, create a new architecture from INFO, whose bfd_arch_info
2935 validity depends on the source:
2936 - executable useless
2937 - rs6000_host_arch() good
2939 - "set arch" trust blindly
2940 - GDB startup useless but harmless */
2942 if (!from_xcoff_exec
)
2944 arch
= info
.bfd_arch_info
->arch
;
2945 mach
= info
.bfd_arch_info
->mach
;
2949 arch
= bfd_arch_powerpc
;
2950 bfd_default_set_arch_mach (&abfd
, arch
, 0);
2951 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2952 mach
= info
.bfd_arch_info
->mach
;
2954 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2955 tdep
->wordsize
= wordsize
;
2957 /* For e500 executables, the apuinfo section is of help here. Such
2958 section contains the identifier and revision number of each
2959 Application-specific Processing Unit that is present on the
2960 chip. The content of the section is determined by the assembler
2961 which looks at each instruction and determines which unit (and
2962 which version of it) can execute it. In our case we just look for
2963 the existance of the section. */
2967 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2970 arch
= info
.bfd_arch_info
->arch
;
2971 mach
= bfd_mach_ppc_e500
;
2972 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2973 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2977 gdbarch
= gdbarch_alloc (&info
, tdep
);
2979 /* Initialize the number of real and pseudo registers in each variant. */
2982 /* Choose variant. */
2983 v
= find_variant_by_arch (arch
, mach
);
2987 tdep
->regs
= v
->regs
;
2989 tdep
->ppc_gp0_regnum
= 0;
2990 tdep
->ppc_gprs_pseudo_p
= 0;
2991 tdep
->ppc_toc_regnum
= 2;
2992 tdep
->ppc_ps_regnum
= 65;
2993 tdep
->ppc_cr_regnum
= 66;
2994 tdep
->ppc_lr_regnum
= 67;
2995 tdep
->ppc_ctr_regnum
= 68;
2996 tdep
->ppc_xer_regnum
= 69;
2997 if (v
->mach
== bfd_mach_ppc_601
)
2998 tdep
->ppc_mq_regnum
= 124;
2999 else if (arch
== bfd_arch_rs6000
)
3000 tdep
->ppc_mq_regnum
= 70;
3002 tdep
->ppc_mq_regnum
= -1;
3003 tdep
->ppc_fp0_regnum
= 32;
3004 tdep
->ppc_fpscr_regnum
= (arch
== bfd_arch_rs6000
) ? 71 : 70;
3005 tdep
->ppc_sr0_regnum
= 71;
3006 tdep
->ppc_vr0_regnum
= -1;
3007 tdep
->ppc_vrsave_regnum
= -1;
3008 tdep
->ppc_ev0_regnum
= -1;
3009 tdep
->ppc_ev31_regnum
= -1;
3010 tdep
->ppc_acc_regnum
= -1;
3011 tdep
->ppc_spefscr_regnum
= -1;
3013 set_gdbarch_pc_regnum (gdbarch
, 64);
3014 set_gdbarch_sp_regnum (gdbarch
, 1);
3015 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
3016 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3017 if (sysv_abi
&& wordsize
== 8)
3018 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3019 else if (sysv_abi
&& wordsize
== 4)
3020 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3023 set_gdbarch_deprecated_extract_return_value (gdbarch
, rs6000_extract_return_value
);
3024 set_gdbarch_store_return_value (gdbarch
, rs6000_store_return_value
);
3027 /* Set lr_frame_offset. */
3029 tdep
->lr_frame_offset
= 16;
3031 tdep
->lr_frame_offset
= 4;
3033 tdep
->lr_frame_offset
= 8;
3035 if (v
->arch
== bfd_arch_rs6000
)
3036 tdep
->ppc_sr0_regnum
= -1;
3037 else if (v
->arch
== bfd_arch_powerpc
)
3041 tdep
->ppc_sr0_regnum
= -1;
3042 tdep
->ppc_vr0_regnum
= 71;
3043 tdep
->ppc_vrsave_regnum
= 104;
3045 case bfd_mach_ppc_7400
:
3046 tdep
->ppc_vr0_regnum
= 119;
3047 tdep
->ppc_vrsave_regnum
= 152;
3049 case bfd_mach_ppc_e500
:
3050 tdep
->ppc_gp0_regnum
= 41;
3051 tdep
->ppc_gprs_pseudo_p
= 1;
3052 tdep
->ppc_toc_regnum
= -1;
3053 tdep
->ppc_ps_regnum
= 1;
3054 tdep
->ppc_cr_regnum
= 2;
3055 tdep
->ppc_lr_regnum
= 3;
3056 tdep
->ppc_ctr_regnum
= 4;
3057 tdep
->ppc_xer_regnum
= 5;
3058 tdep
->ppc_ev0_regnum
= 7;
3059 tdep
->ppc_ev31_regnum
= 38;
3060 tdep
->ppc_fp0_regnum
= -1;
3061 tdep
->ppc_fpscr_regnum
= -1;
3062 tdep
->ppc_sr0_regnum
= -1;
3063 tdep
->ppc_acc_regnum
= 39;
3064 tdep
->ppc_spefscr_regnum
= 40;
3065 set_gdbarch_pc_regnum (gdbarch
, 0);
3066 set_gdbarch_sp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
3067 set_gdbarch_deprecated_fp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
3068 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
3069 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
3072 case bfd_mach_ppc64
:
3073 case bfd_mach_ppc_620
:
3074 case bfd_mach_ppc_630
:
3075 case bfd_mach_ppc_a35
:
3076 case bfd_mach_ppc_rs64ii
:
3077 case bfd_mach_ppc_rs64iii
:
3078 /* These processor's register sets don't have segment registers. */
3079 tdep
->ppc_sr0_regnum
= -1;
3083 internal_error (__FILE__
, __LINE__
,
3084 "rs6000_gdbarch_init: "
3085 "received unexpected BFD 'arch' value");
3087 /* Sanity check on registers. */
3088 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
3090 /* Select instruction printer. */
3091 if (arch
== bfd_arch_rs6000
)
3092 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3094 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3096 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3098 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
3099 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
3100 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3101 set_gdbarch_register_type (gdbarch
, rs6000_register_type
);
3103 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3104 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3105 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3106 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3107 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3108 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3109 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3111 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3113 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3114 set_gdbarch_char_signed (gdbarch
, 0);
3116 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3117 if (sysv_abi
&& wordsize
== 8)
3119 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3120 else if (!sysv_abi
&& wordsize
== 4)
3121 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3122 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3123 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3125 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
3127 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3128 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3129 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3131 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3132 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3133 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3134 is correct for the SysV ABI when the wordsize is 8, but I'm also
3135 fairly certain that ppc_sysv_abi_push_arguments() will give even
3136 worse results since it only works for 32-bit code. So, for the moment,
3137 we're better off calling rs6000_push_arguments() since it works for
3138 64-bit code. At some point in the future, this matter needs to be
3140 if (sysv_abi
&& wordsize
== 4)
3141 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3142 else if (sysv_abi
&& wordsize
== 8)
3143 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3145 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
3147 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, rs6000_extract_struct_value_address
);
3149 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3150 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3151 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3153 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3154 for the descriptor and ".FN" for the entry-point -- a user
3155 specifying "break FN" will unexpectedly end up with a breakpoint
3156 on the descriptor and not the function. This architecture method
3157 transforms any breakpoints on descriptors into breakpoints on the
3158 corresponding entry point. */
3159 if (sysv_abi
&& wordsize
== 8)
3160 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
3162 /* Not sure on this. FIXMEmgo */
3163 set_gdbarch_frame_args_skip (gdbarch
, 8);
3166 set_gdbarch_deprecated_use_struct_convention (gdbarch
, rs6000_use_struct_convention
);
3170 /* Handle RS/6000 function pointers (which are really function
3172 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
3173 rs6000_convert_from_func_ptr_addr
);
3176 /* Helpers for function argument information. */
3177 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3179 /* Hook in ABI-specific overrides, if they have been registered. */
3180 gdbarch_init_osabi (info
, gdbarch
);
3184 case GDB_OSABI_NETBSD_AOUT
:
3185 case GDB_OSABI_NETBSD_ELF
:
3186 case GDB_OSABI_UNKNOWN
:
3187 case GDB_OSABI_LINUX
:
3188 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3189 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3190 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3191 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3194 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3196 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3197 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3198 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3199 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3202 if (from_xcoff_exec
)
3204 /* NOTE: jimix/2003-06-09: This test should really check for
3205 GDB_OSABI_AIX when that is defined and becomes
3206 available. (Actually, once things are properly split apart,
3207 the test goes away.) */
3208 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3209 set_gdbarch_software_single_step (gdbarch
, rs6000_software_single_step
);
3212 init_sim_regno_table (gdbarch
);
3218 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3225 /* FIXME: Dump gdbarch_tdep. */
3228 static struct cmd_list_element
*info_powerpc_cmdlist
= NULL
;
3231 rs6000_info_powerpc_command (char *args
, int from_tty
)
3233 help_list (info_powerpc_cmdlist
, "info powerpc ", class_info
, gdb_stdout
);
3236 /* Initialization code. */
3238 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3241 _initialize_rs6000_tdep (void)
3243 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3244 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3246 /* Add root prefix command for "info powerpc" commands */
3247 add_prefix_cmd ("powerpc", class_info
, rs6000_info_powerpc_command
,
3248 "Various POWERPC info specific commands.",
3249 &info_powerpc_cmdlist
, "info powerpc ", 0, &infolist
);