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* sh-tdep.c (sh_gdbarch_init): Fetch_registers for the sh3-dsp
[thirdparty/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "symtab.h"
30 #include "symfile.h"
31 #include "gdbtypes.h"
32 #include "gdbcmd.h"
33 #include "gdbcore.h"
34 #include "value.h"
35 #include "dis-asm.h"
36 #include "inferior.h"
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
40 #include "regcache.h"
41 #include "doublest.h"
42 #include "osabi.h"
43
44 #include "sh-tdep.h"
45
46 #include "elf-bfd.h"
47 #include "solib-svr4.h"
48
49 /* sh64 flags */
50 #include "elf/sh.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
53
54 void (*sh_show_regs) (void);
55 CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
56
57 #define SH_DEFAULT_NUM_REGS 59
58
59 /* Define other aspects of the stack frame.
60 we keep a copy of the worked out return pc lying around, since it
61 is a useful bit of info */
62
63 struct frame_extra_info
64 {
65 CORE_ADDR return_pc;
66 int leaf_function;
67 int f_offset;
68 };
69
70 static const char *
71 sh_generic_register_name (int reg_nr)
72 {
73 static char *register_names[] =
74 {
75 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
76 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
77 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
78 "fpul", "fpscr",
79 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
80 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
81 "ssr", "spc",
82 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
83 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
84 };
85 if (reg_nr < 0)
86 return NULL;
87 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
88 return NULL;
89 return register_names[reg_nr];
90 }
91
92 static const char *
93 sh_sh_register_name (int reg_nr)
94 {
95 static char *register_names[] =
96 {
97 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
98 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
99 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
100 "", "",
101 "", "", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
103 "", "",
104 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 };
107 if (reg_nr < 0)
108 return NULL;
109 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
110 return NULL;
111 return register_names[reg_nr];
112 }
113
114 static const char *
115 sh_sh3_register_name (int reg_nr)
116 {
117 static char *register_names[] =
118 {
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
122 "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "ssr", "spc",
126 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
127 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134 }
135
136 static const char *
137 sh_sh3e_register_name (int reg_nr)
138 {
139 static char *register_names[] =
140 {
141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fpul", "fpscr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "ssr", "spc",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156 }
157
158 static const char *
159 sh_sh2e_register_name (int reg_nr)
160 {
161 static char *register_names[] =
162 {
163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "fpul", "fpscr",
167 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
168 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
169 "", "",
170 "", "", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178 }
179
180 static const char *
181 sh_sh_dsp_register_name (int reg_nr)
182 {
183 static char *register_names[] =
184 {
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "", "dsr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
191 "", "",
192 "rs", "re", "", "", "", "", "", "",
193 "", "", "", "", "", "", "", "",
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200 }
201
202 static const char *
203 sh_sh3_dsp_register_name (int reg_nr)
204 {
205 static char *register_names[] =
206 {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "", "dsr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
213 "ssr", "spc",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223 }
224
225 static const char *
226 sh_sh4_register_name (int reg_nr)
227 {
228 static char *register_names[] =
229 {
230 /* general registers 0-15 */
231 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
232 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
233 /* 16 - 22 */
234 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
235 /* 23, 24 */
236 "fpul", "fpscr",
237 /* floating point registers 25 - 40 */
238 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
239 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
240 /* 41, 42 */
241 "ssr", "spc",
242 /* bank 0 43 - 50 */
243 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
244 /* bank 1 51 - 58 */
245 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
246 /* double precision (pseudo) 59 - 66 */
247 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
248 /* vectors (pseudo) 67 - 70 */
249 "fv0", "fv4", "fv8", "fv12",
250 /* FIXME: missing XF 71 - 86 */
251 /* FIXME: missing XD 87 - 94 */
252 };
253 if (reg_nr < 0)
254 return NULL;
255 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
256 return NULL;
257 return register_names[reg_nr];
258 }
259
260 static const char *
261 sh_sh64_register_name (int reg_nr)
262 {
263 static char *register_names[] =
264 {
265 /* SH MEDIA MODE (ISA 32) */
266 /* general registers (64-bit) 0-63 */
267 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
268 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
269 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
270 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
271 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
272 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
273 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
274 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
275
276 /* pc (64-bit) 64 */
277 "pc",
278
279 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
280 "sr", "ssr", "spc",
281
282 /* target registers (64-bit) 68-75*/
283 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
284
285 /* floating point state control register (32-bit) 76 */
286 "fpscr",
287
288 /* single precision floating point registers (32-bit) 77-140*/
289 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
290 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
291 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
292 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
293 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
294 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
295 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
296 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
297
298 /* double precision registers (pseudo) 141-172 */
299 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
300 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
301 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
302 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
303
304 /* floating point pairs (pseudo) 173-204*/
305 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
306 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
307 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
308 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
309
310 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
311 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
312 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
313
314 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
315 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
316 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
317 "pc_c",
318 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
319 "fpscr_c", "fpul_c",
320 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
321 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
322 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
323 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
324 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
325 };
326
327 if (reg_nr < 0)
328 return NULL;
329 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
330 return NULL;
331 return register_names[reg_nr];
332 }
333
334 #define NUM_PSEUDO_REGS_SH_MEDIA 80
335 #define NUM_PSEUDO_REGS_SH_COMPACT 51
336
337 static const unsigned char *
338 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
339 {
340 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
341 static unsigned char breakpoint[] = {0xc3, 0xc3};
342
343 *lenptr = sizeof (breakpoint);
344 return breakpoint;
345 }
346
347 static CORE_ADDR
348 sh_push_dummy_code (struct gdbarch *gdbarch,
349 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
350 struct value **args, int nargs,
351 struct type *value_type,
352 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
353 {
354 /* Allocate space sufficient for a breakpoint. */
355 sp = (sp - 2) & ~1;
356 /* Store the address of that breakpoint */
357 *bp_addr = sp;
358 /* sh always starts the call at the callee's entry point. */
359 *real_pc = funaddr;
360 return sp;
361 }
362
363 /* Macros and functions for setting and testing a bit in a minimal
364 symbol that marks it as 32-bit function. The MSB of the minimal
365 symbol's "info" field is used for this purpose. This field is
366 already being used to store the symbol size, so the assumption is
367 that the symbol size cannot exceed 2^31.
368
369 ELF_MAKE_MSYMBOL_SPECIAL
370 tests whether an ELF symbol is "special", i.e. refers
371 to a 32-bit function, and sets a "special" bit in a
372 minimal symbol to mark it as a 32-bit function
373 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
374 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
375 the "info" field with the "special" bit masked out */
376
377 #define MSYMBOL_IS_SPECIAL(msym) \
378 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
379
380 static void
381 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
382 {
383 if (msym == NULL)
384 return;
385
386 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
387 {
388 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
389 SYMBOL_VALUE_ADDRESS (msym) |= 1;
390 }
391 }
392
393 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
394 are some macros to test, set, or clear bit 0 of addresses. */
395 #define IS_ISA32_ADDR(addr) ((addr) & 1)
396 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
397 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
398
399 static int
400 pc_is_isa32 (bfd_vma memaddr)
401 {
402 struct minimal_symbol *sym;
403
404 /* If bit 0 of the address is set, assume this is a
405 ISA32 (shmedia) address. */
406 if (IS_ISA32_ADDR (memaddr))
407 return 1;
408
409 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
410 the high bit of the info field. Use this to decide if the function is
411 ISA16 or ISA32. */
412 sym = lookup_minimal_symbol_by_pc (memaddr);
413 if (sym)
414 return MSYMBOL_IS_SPECIAL (sym);
415 else
416 return 0;
417 }
418
419 static const unsigned char *
420 sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
421 {
422 /* The BRK instruction for shmedia is
423 01101111 11110101 11111111 11110000
424 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
425 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
426
427 /* The BRK instruction for shcompact is
428 00000000 00111011
429 which translates in big endian mode to 0x0, 0x3b
430 and in little endian mode to 0x3b, 0x0*/
431
432 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
433 {
434 if (pc_is_isa32 (*pcptr))
435 {
436 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
437 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
438 *lenptr = sizeof (big_breakpoint_media);
439 return big_breakpoint_media;
440 }
441 else
442 {
443 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
444 *lenptr = sizeof (big_breakpoint_compact);
445 return big_breakpoint_compact;
446 }
447 }
448 else
449 {
450 if (pc_is_isa32 (*pcptr))
451 {
452 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
453 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
454 *lenptr = sizeof (little_breakpoint_media);
455 return little_breakpoint_media;
456 }
457 else
458 {
459 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
460 *lenptr = sizeof (little_breakpoint_compact);
461 return little_breakpoint_compact;
462 }
463 }
464 }
465
466 /* Prologue looks like
467 [mov.l <regs>,@-r15]...
468 [sts.l pr,@-r15]
469 [mov.l r14,@-r15]
470 [mov r15,r14]
471
472 Actually it can be more complicated than this. For instance, with
473 newer gcc's:
474
475 mov.l r14,@-r15
476 add #-12,r15
477 mov r15,r14
478 mov r4,r1
479 mov r5,r2
480 mov.l r6,@(4,r14)
481 mov.l r7,@(8,r14)
482 mov.b r1,@r14
483 mov r14,r1
484 mov r14,r1
485 add #2,r1
486 mov.w r2,@r1
487
488 */
489
490 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
491 with l=1 and n = 18 0110101111110001010010100aaa0000 */
492 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
493
494 /* STS.L PR,@-r0 0100000000100010
495 r0-4-->r0, PR-->(r0) */
496 #define IS_STS_R0(x) ((x) == 0x4022)
497
498 /* STS PR, Rm 0000mmmm00101010
499 PR-->Rm */
500 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
501
502 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
503 Rm-->(dispx4+r15) */
504 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
505
506 /* MOV.L R14,@(disp,r15) 000111111110dddd
507 R14-->(dispx4+r15) */
508 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
509
510 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
511 R18-->(dispx8+R14) */
512 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
513
514 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
515 R18-->(dispx8+R15) */
516 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
517
518 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
519 R18-->(dispx4+R15) */
520 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
521
522 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
523 R14-->(dispx8+R15) */
524 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
525
526 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
527 R14-->(dispx4+R15) */
528 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
529
530 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
531 R15 + imm --> R15 */
532 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
533
534 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
535 R15 + imm --> R15 */
536 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
537
538 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
539 R15 + R63 --> R14 */
540 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
541
542 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
543 R15 + R63 --> R14 */
544 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
545
546 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
547
548 /* MOV #imm, R0 1110 0000 ssss ssss
549 #imm-->R0 */
550 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
551
552 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
553 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
554
555 /* ADD r15,r0 0011 0000 1111 1100
556 r15+r0-->r0 */
557 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
558
559 /* MOV.L R14 @-R0 0010 0000 1110 0110
560 R14-->(R0-4), R0-4-->R0 */
561 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
562
563 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
564 where Rm is one of r2-r9 which are the argument registers. */
565 /* FIXME: Recognize the float and double register moves too! */
566 #define IS_MEDIA_IND_ARG_MOV(x) \
567 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
568
569 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
570 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
571 where Rm is one of r2-r9 which are the argument registers. */
572 #define IS_MEDIA_ARG_MOV(x) \
573 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
574 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
575
576 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
577 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
578 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
579 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
580 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
581 #define IS_MEDIA_MOV_TO_R14(x) \
582 ((((x) & 0xfffffc0f) == 0xa0e00000) \
583 || (((x) & 0xfffffc0f) == 0xa4e00000) \
584 || (((x) & 0xfffffc0f) == 0xa8e00000) \
585 || (((x) & 0xfffffc0f) == 0xb4e00000) \
586 || (((x) & 0xfffffc0f) == 0xbce00000))
587
588 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
589 where Rm is r2-r9 */
590 #define IS_COMPACT_IND_ARG_MOV(x) \
591 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
592
593 /* compact direct arg move!
594 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
595 #define IS_COMPACT_ARG_MOV(x) \
596 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
597
598 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
599 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
600 #define IS_COMPACT_MOV_TO_R14(x) \
601 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
602
603 #define IS_JSR_R0(x) ((x) == 0x400b)
604 #define IS_NOP(x) ((x) == 0x0009)
605
606
607 /* STS.L PR,@-r15 0100111100100010
608 r15-4-->r15, PR-->(r15) */
609 #define IS_STS(x) ((x) == 0x4f22)
610
611 /* MOV.L Rm,@-r15 00101111mmmm0110
612 r15-4-->r15, Rm-->(R15) */
613 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
614
615 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
616
617 /* MOV r15,r14 0110111011110011
618 r15-->r14 */
619 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
620
621 /* ADD #imm,r15 01111111iiiiiiii
622 r15+imm-->r15 */
623 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
624
625 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
626 #define IS_SHLL_R3(x) ((x) == 0x4300)
627
628 /* ADD r3,r15 0011111100111100
629 r15+r3-->r15 */
630 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
631
632 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
633 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
634 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
635 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
636
637 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
638 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
639 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
640 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
641 #define IS_ARG_MOV(x) \
642 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
643 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
644 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
645
646 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
647 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
648 #define IS_MOV_TO_R14(x) \
649 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
650
651 #define FPSCR_SZ (1 << 20)
652
653 /* Skip any prologue before the guts of a function */
654
655 /* Skip the prologue using the debug information. If this fails we'll
656 fall back on the 'guess' method below. */
657 static CORE_ADDR
658 after_prologue (CORE_ADDR pc)
659 {
660 struct symtab_and_line sal;
661 CORE_ADDR func_addr, func_end;
662
663 /* If we can not find the symbol in the partial symbol table, then
664 there is no hope we can determine the function's start address
665 with this code. */
666 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
667 return 0;
668
669 /* Get the line associated with FUNC_ADDR. */
670 sal = find_pc_line (func_addr, 0);
671
672 /* There are only two cases to consider. First, the end of the source line
673 is within the function bounds. In that case we return the end of the
674 source line. Second is the end of the source line extends beyond the
675 bounds of the current function. We need to use the slow code to
676 examine instructions in that case. */
677 if (sal.end < func_end)
678 return sal.end;
679 else
680 return 0;
681 }
682
683 /* Here we look at each instruction in the function, and try to guess
684 where the prologue ends. Unfortunately this is not always
685 accurate. */
686 static CORE_ADDR
687 sh_skip_prologue_hard_way (CORE_ADDR start_pc)
688 {
689 CORE_ADDR here, end;
690 int updated_fp = 0;
691
692 if (!start_pc)
693 return 0;
694
695 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
696 {
697 int w = read_memory_integer (here, 2);
698 here += 2;
699 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
700 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
701 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
702 {
703 start_pc = here;
704 }
705 else if (IS_MOV_SP_FP (w))
706 {
707 start_pc = here;
708 updated_fp = 1;
709 }
710 else
711 /* Don't bail out yet, if we are before the copy of sp. */
712 if (updated_fp)
713 break;
714 }
715
716 return start_pc;
717 }
718
719 static CORE_ADDR
720 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
721 {
722 CORE_ADDR here, end;
723 int w;
724 int insn_size = (media_mode ? 4 : 2);
725
726 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
727 {
728 if (media_mode)
729 {
730 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
731 here += insn_size;
732 if (IS_MEDIA_IND_ARG_MOV (w))
733 {
734 /* This must be followed by a store to r14, so the argument
735 is where the debug info says it is. This can happen after
736 the SP has been saved, unfortunately. */
737
738 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
739 insn_size);
740 here += insn_size;
741 if (IS_MEDIA_MOV_TO_R14 (next_insn))
742 start_pc = here;
743 }
744 else if (IS_MEDIA_ARG_MOV (w))
745 {
746 /* These instructions store directly the argument in r14. */
747 start_pc = here;
748 }
749 else
750 break;
751 }
752 else
753 {
754 w = read_memory_integer (here, insn_size);
755 w = w & 0xffff;
756 here += insn_size;
757 if (IS_COMPACT_IND_ARG_MOV (w))
758 {
759 /* This must be followed by a store to r14, so the argument
760 is where the debug info says it is. This can happen after
761 the SP has been saved, unfortunately. */
762
763 int next_insn = 0xffff & read_memory_integer (here, insn_size);
764 here += insn_size;
765 if (IS_COMPACT_MOV_TO_R14 (next_insn))
766 start_pc = here;
767 }
768 else if (IS_COMPACT_ARG_MOV (w))
769 {
770 /* These instructions store directly the argument in r14. */
771 start_pc = here;
772 }
773 else if (IS_MOVL_R0 (w))
774 {
775 /* There is a function that gcc calls to get the arguments
776 passed correctly to the function. Only after this
777 function call the arguments will be found at the place
778 where they are supposed to be. This happens in case the
779 argument has to be stored into a 64-bit register (for
780 instance doubles, long longs). SHcompact doesn't have
781 access to the full 64-bits, so we store the register in
782 stack slot and store the address of the stack slot in
783 the register, then do a call through a wrapper that
784 loads the memory value into the register. A SHcompact
785 callee calls an argument decoder
786 (GCC_shcompact_incoming_args) that stores the 64-bit
787 value in a stack slot and stores the address of the
788 stack slot in the register. GCC thinks the argument is
789 just passed by transparent reference, but this is only
790 true after the argument decoder is called. Such a call
791 needs to be considered part of the prologue. */
792
793 /* This must be followed by a JSR @r0 instruction and by
794 a NOP instruction. After these, the prologue is over! */
795
796 int next_insn = 0xffff & read_memory_integer (here, insn_size);
797 here += insn_size;
798 if (IS_JSR_R0 (next_insn))
799 {
800 next_insn = 0xffff & read_memory_integer (here, insn_size);
801 here += insn_size;
802
803 if (IS_NOP (next_insn))
804 start_pc = here;
805 }
806 }
807 else
808 break;
809 }
810 }
811
812 return start_pc;
813 }
814
815 static CORE_ADDR
816 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
817 {
818 CORE_ADDR here, end;
819 int updated_fp = 0;
820 int insn_size = 4;
821 int media_mode = 1;
822
823 if (!start_pc)
824 return 0;
825
826 if (pc_is_isa32 (start_pc) == 0)
827 {
828 insn_size = 2;
829 media_mode = 0;
830 }
831
832 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
833 {
834
835 if (media_mode)
836 {
837 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
838 here += insn_size;
839 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
840 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
841 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
842 {
843 start_pc = here;
844 }
845 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
846 {
847 start_pc = here;
848 updated_fp = 1;
849 }
850 else
851 if (updated_fp)
852 {
853 /* Don't bail out yet, we may have arguments stored in
854 registers here, according to the debug info, so that
855 gdb can print the frames correctly. */
856 start_pc = look_for_args_moves (here - insn_size, media_mode);
857 break;
858 }
859 }
860 else
861 {
862 int w = 0xffff & read_memory_integer (here, insn_size);
863 here += insn_size;
864
865 if (IS_STS_R0 (w) || IS_STS_PR (w)
866 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
867 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
868 {
869 start_pc = here;
870 }
871 else if (IS_MOV_SP_FP (w))
872 {
873 start_pc = here;
874 updated_fp = 1;
875 }
876 else
877 if (updated_fp)
878 {
879 /* Don't bail out yet, we may have arguments stored in
880 registers here, according to the debug info, so that
881 gdb can print the frames correctly. */
882 start_pc = look_for_args_moves (here - insn_size, media_mode);
883 break;
884 }
885 }
886 }
887
888 return start_pc;
889 }
890
891 static CORE_ADDR
892 sh_skip_prologue (CORE_ADDR pc)
893 {
894 CORE_ADDR post_prologue_pc;
895
896 /* See if we can determine the end of the prologue via the symbol table.
897 If so, then return either PC, or the PC after the prologue, whichever
898 is greater. */
899 post_prologue_pc = after_prologue (pc);
900
901 /* If after_prologue returned a useful address, then use it. Else
902 fall back on the instruction skipping code. */
903 if (post_prologue_pc != 0)
904 return max (pc, post_prologue_pc);
905 else
906 return (skip_prologue_hard_way (pc));
907 }
908
909 /* Immediately after a function call, return the saved pc.
910 Can't always go through the frames for this because on some machines
911 the new frame is not set up until the new function executes
912 some instructions.
913
914 The return address is the value saved in the PR register + 4 */
915 static CORE_ADDR
916 sh_saved_pc_after_call (struct frame_info *frame)
917 {
918 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
919 }
920
921 /* Should call_function allocate stack space for a struct return? */
922 static int
923 sh_use_struct_convention (int gcc_p, struct type *type)
924 {
925 #if 0
926 return (TYPE_LENGTH (type) > 1);
927 #else
928 int len = TYPE_LENGTH (type);
929 int nelem = TYPE_NFIELDS (type);
930 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
931 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
932 #endif
933 }
934
935 static int
936 sh64_use_struct_convention (int gcc_p, struct type *type)
937 {
938 return (TYPE_LENGTH (type) > 8);
939 }
940
941 /* Store the address of the place in which to copy the structure the
942 subroutine will return. This is called from call_function.
943
944 We store structs through a pointer passed in R2 */
945 static void
946 sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
947 {
948 write_register (STRUCT_RETURN_REGNUM, (addr));
949 }
950
951 /* Disassemble an instruction. */
952 static int
953 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
954 {
955 info->endian = TARGET_BYTE_ORDER;
956 return print_insn_sh (memaddr, info);
957 }
958
959 /* Given a GDB frame, determine the address of the calling function's
960 frame. This will be used to create a new GDB frame struct, and
961 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
962 will be called for the new frame.
963
964 For us, the frame address is its stack pointer value, so we look up
965 the function prologue to determine the caller's sp value, and return it. */
966 static CORE_ADDR
967 sh_frame_chain (struct frame_info *frame)
968 {
969 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
970 get_frame_base (frame),
971 get_frame_base (frame)))
972 return get_frame_base (frame); /* dummy frame same as caller's frame */
973 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
974 return read_memory_integer (get_frame_base (frame)
975 + get_frame_extra_info (frame)->f_offset, 4);
976 else
977 return 0;
978 }
979
980 /* Given a register number RN as it appears in an assembly
981 instruction, find the corresponding register number in the GDB
982 scheme. */
983 static int
984 translate_insn_rn (int rn, int media_mode)
985 {
986 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
987
988 /* FIXME: this assumes that the number rn is for a not pseudo
989 register only. */
990 if (media_mode)
991 return rn;
992 else
993 {
994 /* These registers don't have a corresponding compact one. */
995 /* FIXME: This is probably not enough. */
996 #if 0
997 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
998 return rn;
999 #endif
1000 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
1001 return tdep->R0_C_REGNUM + rn;
1002 else
1003 return rn;
1004 }
1005 }
1006
1007 static CORE_ADDR
1008 sh64_frame_chain (struct frame_info *frame)
1009 {
1010 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1011 get_frame_base (frame),
1012 get_frame_base (frame)))
1013 return get_frame_base (frame); /* dummy frame same as caller's frame */
1014 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
1015 {
1016 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1017 int size;
1018 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1019 size = 4;
1020 else
1021 size = REGISTER_RAW_SIZE (translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode));
1022 return read_memory_integer (get_frame_base (frame)
1023 + get_frame_extra_info (frame)->f_offset,
1024 size);
1025 }
1026 else
1027 return 0;
1028 }
1029
1030 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
1031 we might want to do here is to check REGNUM against the clobber mask, and
1032 somehow flag it as invalid if it isn't saved on the stack somewhere. This
1033 would provide a graceful failure mode when trying to get the value of
1034 caller-saves registers for an inner frame. */
1035 static CORE_ADDR
1036 sh_find_callers_reg (struct frame_info *fi, int regnum)
1037 {
1038 for (; fi; fi = get_next_frame (fi))
1039 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1040 get_frame_base (fi)))
1041 /* When the caller requests PR from the dummy frame, we return PC because
1042 that's where the previous routine appears to have done a call from. */
1043 return deprecated_read_register_dummy (get_frame_pc (fi),
1044 get_frame_base (fi), regnum);
1045 else
1046 {
1047 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1048 if (!get_frame_pc (fi))
1049 return 0;
1050 if (get_frame_saved_regs (fi)[regnum] != 0)
1051 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
1052 register_size (current_gdbarch, regnum));
1053 }
1054 return read_register (regnum);
1055 }
1056
1057 static CORE_ADDR
1058 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1059 {
1060 int media_mode = 0;
1061
1062 for (; fi; fi = get_next_frame (fi))
1063 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1064 get_frame_base (fi)))
1065 /* When the caller requests PR from the dummy frame, we return PC because
1066 that's where the previous routine appears to have done a call from. */
1067 return deprecated_read_register_dummy (get_frame_pc (fi),
1068 get_frame_base (fi), pr_regnum);
1069 else
1070 {
1071 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1072 if (!get_frame_pc (fi))
1073 return 0;
1074
1075 media_mode = pc_is_isa32 (get_frame_pc (fi));
1076
1077 if (get_frame_saved_regs (fi)[pr_regnum] != 0)
1078 {
1079 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1080 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1081 ? 4
1082 : REGISTER_RAW_SIZE (gdb_reg_num));
1083 return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size);
1084 }
1085 }
1086 return read_register (pr_regnum);
1087 }
1088
1089 /* Put here the code to store, into a struct frame_saved_regs, the
1090 addresses of the saved registers of frame described by FRAME_INFO.
1091 This includes special registers such as pc and fp saved in special
1092 ways in the stack frame. sp is even more special: the address we
1093 return for it IS the sp for the next frame. */
1094 static void
1095 sh_nofp_frame_init_saved_regs (struct frame_info *fi)
1096 {
1097 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
1098 int rn;
1099 int have_fp = 0;
1100 int depth;
1101 int pc;
1102 int opc;
1103 int insn;
1104 int r3_val = 0;
1105 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1106 get_frame_base (fi));
1107
1108 if (get_frame_saved_regs (fi) == NULL)
1109 frame_saved_regs_zalloc (fi);
1110 else
1111 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1112
1113 if (dummy_regs)
1114 {
1115 /* DANGER! This is ONLY going to work if the char buffer format of
1116 the saved registers is byte-for-byte identical to the
1117 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1118 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1119 return;
1120 }
1121
1122 get_frame_extra_info (fi)->leaf_function = 1;
1123 get_frame_extra_info (fi)->f_offset = 0;
1124
1125 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1126 where[rn] = -1;
1127
1128 depth = 0;
1129
1130 /* Loop around examining the prologue insns until we find something
1131 that does not appear to be part of the prologue. But give up
1132 after 20 of them, since we're getting silly then. */
1133
1134 pc = get_frame_func (fi);
1135 if (!pc)
1136 {
1137 deprecated_update_frame_pc_hack (fi, 0);
1138 return;
1139 }
1140
1141 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1142 {
1143 insn = read_memory_integer (pc, 2);
1144 /* See where the registers will be saved to */
1145 if (IS_PUSH (insn))
1146 {
1147 rn = GET_PUSHED_REG (insn);
1148 where[rn] = depth;
1149 depth += 4;
1150 }
1151 else if (IS_STS (insn))
1152 {
1153 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
1154 /* If we're storing the pr then this isn't a leaf */
1155 get_frame_extra_info (fi)->leaf_function = 0;
1156 depth += 4;
1157 }
1158 else if (IS_MOV_R3 (insn))
1159 {
1160 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1161 }
1162 else if (IS_SHLL_R3 (insn))
1163 {
1164 r3_val <<= 1;
1165 }
1166 else if (IS_ADD_R3SP (insn))
1167 {
1168 depth += -r3_val;
1169 }
1170 else if (IS_ADD_SP (insn))
1171 {
1172 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1173 }
1174 else if (IS_MOV_SP_FP (insn))
1175 break;
1176 #if 0 /* This used to just stop when it found an instruction that
1177 was not considered part of the prologue. Now, we just
1178 keep going looking for likely instructions. */
1179 else
1180 break;
1181 #endif
1182 }
1183
1184 /* Now we know how deep things are, we can work out their addresses */
1185
1186 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1187 {
1188 if (where[rn] >= 0)
1189 {
1190 if (rn == DEPRECATED_FP_REGNUM)
1191 have_fp = 1;
1192
1193 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
1194 }
1195 else
1196 {
1197 get_frame_saved_regs (fi)[rn] = 0;
1198 }
1199 }
1200
1201 if (have_fp)
1202 {
1203 get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
1204 }
1205 else
1206 {
1207 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
1208 }
1209
1210 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
1211 /* Work out the return pc - either from the saved pr or the pr
1212 value */
1213 }
1214
1215 /* For vectors of 4 floating point registers. */
1216 static int
1217 fv_reg_base_num (int fv_regnum)
1218 {
1219 int fp_regnum;
1220
1221 fp_regnum = FP0_REGNUM +
1222 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1223 return fp_regnum;
1224 }
1225
1226 /* For double precision floating point registers, i.e 2 fp regs.*/
1227 static int
1228 dr_reg_base_num (int dr_regnum)
1229 {
1230 int fp_regnum;
1231
1232 fp_regnum = FP0_REGNUM +
1233 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1234 return fp_regnum;
1235 }
1236
1237 /* For pairs of floating point registers */
1238 static int
1239 fpp_reg_base_num (int fpp_regnum)
1240 {
1241 int fp_regnum;
1242
1243 fp_regnum = FP0_REGNUM +
1244 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1245 return fp_regnum;
1246 }
1247
1248 static int
1249 is_media_pseudo (int rn)
1250 {
1251 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1252
1253 return (rn >= tdep->DR0_REGNUM
1254 && rn <= tdep->FV_LAST_REGNUM);
1255 }
1256
1257 static int
1258 sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1259 {
1260 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1261 }
1262
1263 static int
1264 sh64_media_reg_base_num (int reg_nr)
1265 {
1266 int base_regnum = -1;
1267 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1268
1269 if (reg_nr >= tdep->DR0_REGNUM
1270 && reg_nr <= tdep->DR_LAST_REGNUM)
1271 base_regnum = dr_reg_base_num (reg_nr);
1272
1273 else if (reg_nr >= tdep->FPP0_REGNUM
1274 && reg_nr <= tdep->FPP_LAST_REGNUM)
1275 base_regnum = fpp_reg_base_num (reg_nr);
1276
1277 else if (reg_nr >= tdep->FV0_REGNUM
1278 && reg_nr <= tdep->FV_LAST_REGNUM)
1279 base_regnum = fv_reg_base_num (reg_nr);
1280
1281 return base_regnum;
1282 }
1283
1284 /* *INDENT-OFF* */
1285 /*
1286 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1287 GDB_REGNUM BASE_REGNUM
1288 r0_c 221 0
1289 r1_c 222 1
1290 r2_c 223 2
1291 r3_c 224 3
1292 r4_c 225 4
1293 r5_c 226 5
1294 r6_c 227 6
1295 r7_c 228 7
1296 r8_c 229 8
1297 r9_c 230 9
1298 r10_c 231 10
1299 r11_c 232 11
1300 r12_c 233 12
1301 r13_c 234 13
1302 r14_c 235 14
1303 r15_c 236 15
1304
1305 pc_c 237 64
1306 gbr_c 238 16
1307 mach_c 239 17
1308 macl_c 240 17
1309 pr_c 241 18
1310 t_c 242 19
1311 fpscr_c 243 76
1312 fpul_c 244 109
1313
1314 fr0_c 245 77
1315 fr1_c 246 78
1316 fr2_c 247 79
1317 fr3_c 248 80
1318 fr4_c 249 81
1319 fr5_c 250 82
1320 fr6_c 251 83
1321 fr7_c 252 84
1322 fr8_c 253 85
1323 fr9_c 254 86
1324 fr10_c 255 87
1325 fr11_c 256 88
1326 fr12_c 257 89
1327 fr13_c 258 90
1328 fr14_c 259 91
1329 fr15_c 260 92
1330
1331 dr0_c 261 77
1332 dr2_c 262 79
1333 dr4_c 263 81
1334 dr6_c 264 83
1335 dr8_c 265 85
1336 dr10_c 266 87
1337 dr12_c 267 89
1338 dr14_c 268 91
1339
1340 fv0_c 269 77
1341 fv4_c 270 81
1342 fv8_c 271 85
1343 fv12_c 272 91
1344 */
1345 /* *INDENT-ON* */
1346 static int
1347 sh64_compact_reg_base_num (int reg_nr)
1348 {
1349 int base_regnum = -1;
1350 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1351
1352 /* general register N maps to general register N */
1353 if (reg_nr >= tdep->R0_C_REGNUM
1354 && reg_nr <= tdep->R_LAST_C_REGNUM)
1355 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1356
1357 /* floating point register N maps to floating point register N */
1358 else if (reg_nr >= tdep->FP0_C_REGNUM
1359 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1360 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1361
1362 /* double prec register N maps to base regnum for double prec register N */
1363 else if (reg_nr >= tdep->DR0_C_REGNUM
1364 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1365 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1366 + reg_nr - tdep->DR0_C_REGNUM);
1367
1368 /* vector N maps to base regnum for vector register N */
1369 else if (reg_nr >= tdep->FV0_C_REGNUM
1370 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1371 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1372 + reg_nr - tdep->FV0_C_REGNUM);
1373
1374 else if (reg_nr == tdep->PC_C_REGNUM)
1375 base_regnum = PC_REGNUM;
1376
1377 else if (reg_nr == tdep->GBR_C_REGNUM)
1378 base_regnum = 16;
1379
1380 else if (reg_nr == tdep->MACH_C_REGNUM
1381 || reg_nr == tdep->MACL_C_REGNUM)
1382 base_regnum = 17;
1383
1384 else if (reg_nr == tdep->PR_C_REGNUM)
1385 base_regnum = 18;
1386
1387 else if (reg_nr == tdep->T_C_REGNUM)
1388 base_regnum = 19;
1389
1390 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1391 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1392
1393 else if (reg_nr == tdep->FPUL_C_REGNUM)
1394 base_regnum = FP0_REGNUM + 32;
1395
1396 return base_regnum;
1397 }
1398
1399 /* Given a register number RN (according to the gdb scheme) , return
1400 its corresponding architectural register. In media mode, only a
1401 subset of the registers is pseudo registers. For compact mode, all
1402 the registers are pseudo. */
1403 static int
1404 translate_rn_to_arch_reg_num (int rn, int media_mode)
1405 {
1406
1407 if (media_mode)
1408 {
1409 if (!is_media_pseudo (rn))
1410 return rn;
1411 else
1412 return sh64_media_reg_base_num (rn);
1413 }
1414 else
1415 /* All compact registers are pseudo. */
1416 return sh64_compact_reg_base_num (rn);
1417 }
1418
1419 static int
1420 sign_extend (int value, int bits)
1421 {
1422 value = value & ((1 << bits) - 1);
1423 return (value & (1 << (bits - 1))
1424 ? value | (~((1 << bits) - 1))
1425 : value);
1426 }
1427
1428 static void
1429 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1430 {
1431 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1432 int rn;
1433 int have_fp = 0;
1434 int fp_regnum;
1435 int sp_regnum;
1436 int depth;
1437 int pc;
1438 int opc;
1439 int insn;
1440 int r0_val = 0;
1441 int media_mode = 0;
1442 int insn_size;
1443 int gdb_register_number;
1444 int register_number;
1445 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1446 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1447
1448 if (get_frame_saved_regs (fi) == NULL)
1449 frame_saved_regs_zalloc (fi);
1450 else
1451 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1452
1453 if (dummy_regs)
1454 {
1455 /* DANGER! This is ONLY going to work if the char buffer format of
1456 the saved registers is byte-for-byte identical to the
1457 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1458 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1459 return;
1460 }
1461
1462 get_frame_extra_info (fi)->leaf_function = 1;
1463 get_frame_extra_info (fi)->f_offset = 0;
1464
1465 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1466 where[rn] = -1;
1467
1468 depth = 0;
1469
1470 /* Loop around examining the prologue insns until we find something
1471 that does not appear to be part of the prologue. But give up
1472 after 20 of them, since we're getting silly then. */
1473
1474 pc = get_frame_func (fi);
1475 if (!pc)
1476 {
1477 deprecated_update_frame_pc_hack (fi, 0);
1478 return;
1479 }
1480
1481 if (pc_is_isa32 (pc))
1482 {
1483 media_mode = 1;
1484 insn_size = 4;
1485 }
1486 else
1487 {
1488 media_mode = 0;
1489 insn_size = 2;
1490 }
1491
1492 /* The frame pointer register is general register 14 in shmedia and
1493 shcompact modes. In sh compact it is a pseudo register. Same goes
1494 for the stack pointer register, which is register 15. */
1495 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1496 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1497
1498 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1499 {
1500 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1501 insn_size);
1502
1503 if (media_mode == 0)
1504 {
1505 if (IS_STS_PR (insn))
1506 {
1507 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1508 if (IS_MOV_TO_R15 (next_insn))
1509 {
1510 int reg_nr = tdep->PR_C_REGNUM;
1511
1512 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1513 get_frame_extra_info (fi)->leaf_function = 0;
1514 pc += insn_size;
1515 }
1516 }
1517 else if (IS_MOV_R14 (insn))
1518 {
1519 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1520 }
1521
1522 else if (IS_MOV_R0 (insn))
1523 {
1524 /* Put in R0 the offset from SP at which to store some
1525 registers. We are interested in this value, because it
1526 will tell us where the given registers are stored within
1527 the frame. */
1528 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1529 }
1530 else if (IS_ADD_SP_R0 (insn))
1531 {
1532 /* This instruction still prepares r0, but we don't care.
1533 We already have the offset in r0_val. */
1534 }
1535 else if (IS_STS_R0 (insn))
1536 {
1537 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1538 int reg_nr = tdep->PR_C_REGNUM;
1539 where[reg_nr] = depth - (r0_val - 4);
1540 r0_val -= 4;
1541 get_frame_extra_info (fi)->leaf_function = 0;
1542 }
1543 else if (IS_MOV_R14_R0 (insn))
1544 {
1545 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1546 where[fp_regnum] = depth - (r0_val - 4);
1547 r0_val -= 4;
1548 }
1549
1550 else if (IS_ADD_SP (insn))
1551 {
1552 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1553 }
1554 else if (IS_MOV_SP_FP (insn))
1555 break;
1556 }
1557 else
1558 {
1559 if (IS_ADDIL_SP_MEDIA (insn)
1560 || IS_ADDI_SP_MEDIA (insn))
1561 {
1562 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1563 }
1564
1565 else if (IS_STQ_R18_R15 (insn))
1566 {
1567 where[tdep->PR_REGNUM] =
1568 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1569 get_frame_extra_info (fi)->leaf_function = 0;
1570 }
1571
1572 else if (IS_STL_R18_R15 (insn))
1573 {
1574 where[tdep->PR_REGNUM] =
1575 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1576 get_frame_extra_info (fi)->leaf_function = 0;
1577 }
1578
1579 else if (IS_STQ_R14_R15 (insn))
1580 {
1581 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1582 }
1583
1584 else if (IS_STL_R14_R15 (insn))
1585 {
1586 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1587 }
1588
1589 else if (IS_MOV_SP_FP_MEDIA (insn))
1590 break;
1591 }
1592 }
1593
1594 /* Now we know how deep things are, we can work out their addresses. */
1595 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1596 {
1597 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1598
1599 if (where[rn] >= 0)
1600 {
1601 if (rn == fp_regnum)
1602 have_fp = 1;
1603
1604 /* Watch out! saved_regs is only for the real registers, and
1605 doesn't include space for the pseudo registers. */
1606 get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth;
1607
1608 }
1609 else
1610 get_frame_saved_regs (fi)[register_number] = 0;
1611 }
1612
1613 if (have_fp)
1614 {
1615 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1616 shcompact 15 is the arch register corresponding to the pseudo
1617 register r15 which still is the SP register. */
1618 /* The place on the stack where fp is stored contains the sp of
1619 the caller. */
1620 /* Again, saved_registers contains only space for the real
1621 registers, so we store in DEPRECATED_FP_REGNUM position. */
1622 int size;
1623 if (tdep->sh_abi == SH_ABI_32)
1624 size = 4;
1625 else
1626 size = REGISTER_RAW_SIZE (fp_regnum);
1627 get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size);
1628 }
1629 else
1630 get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
1631
1632 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
1633 }
1634
1635 static void
1636 sh_fp_frame_init_saved_regs (struct frame_info *fi)
1637 {
1638 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1639 int rn;
1640 int have_fp = 0;
1641 int depth;
1642 int pc;
1643 int opc;
1644 int insn;
1645 int r3_val = 0;
1646 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1647 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1648
1649 if (get_frame_saved_regs (fi) == NULL)
1650 frame_saved_regs_zalloc (fi);
1651 else
1652 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1653
1654 if (dummy_regs)
1655 {
1656 /* DANGER! This is ONLY going to work if the char buffer format of
1657 the saved registers is byte-for-byte identical to the
1658 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1659 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1660 return;
1661 }
1662
1663 get_frame_extra_info (fi)->leaf_function = 1;
1664 get_frame_extra_info (fi)->f_offset = 0;
1665
1666 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1667 where[rn] = -1;
1668
1669 depth = 0;
1670
1671 /* Loop around examining the prologue insns until we find something
1672 that does not appear to be part of the prologue. But give up
1673 after 20 of them, since we're getting silly then. */
1674
1675 pc = get_frame_func (fi);
1676 if (!pc)
1677 {
1678 deprecated_update_frame_pc_hack (fi, 0);
1679 return;
1680 }
1681
1682 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1683 {
1684 insn = read_memory_integer (pc, 2);
1685 /* See where the registers will be saved to */
1686 if (IS_PUSH (insn))
1687 {
1688 rn = GET_PUSHED_REG (insn);
1689 where[rn] = depth;
1690 depth += 4;
1691 }
1692 else if (IS_STS (insn))
1693 {
1694 where[tdep->PR_REGNUM] = depth;
1695 /* If we're storing the pr then this isn't a leaf */
1696 get_frame_extra_info (fi)->leaf_function = 0;
1697 depth += 4;
1698 }
1699 else if (IS_MOV_R3 (insn))
1700 {
1701 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1702 }
1703 else if (IS_SHLL_R3 (insn))
1704 {
1705 r3_val <<= 1;
1706 }
1707 else if (IS_ADD_R3SP (insn))
1708 {
1709 depth += -r3_val;
1710 }
1711 else if (IS_ADD_SP (insn))
1712 {
1713 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1714 }
1715 else if (IS_FMOV (insn))
1716 {
1717 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
1718 {
1719 depth += 8;
1720 }
1721 else
1722 {
1723 depth += 4;
1724 }
1725 }
1726 else if (IS_MOV_SP_FP (insn))
1727 break;
1728 #if 0 /* This used to just stop when it found an instruction that
1729 was not considered part of the prologue. Now, we just
1730 keep going looking for likely instructions. */
1731 else
1732 break;
1733 #endif
1734 }
1735
1736 /* Now we know how deep things are, we can work out their addresses */
1737
1738 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1739 {
1740 if (where[rn] >= 0)
1741 {
1742 if (rn == DEPRECATED_FP_REGNUM)
1743 have_fp = 1;
1744
1745 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
1746 }
1747 else
1748 {
1749 get_frame_saved_regs (fi)[rn] = 0;
1750 }
1751 }
1752
1753 if (have_fp)
1754 {
1755 get_frame_saved_regs (fi)[SP_REGNUM] =
1756 read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
1757 }
1758 else
1759 {
1760 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
1761 }
1762
1763 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
1764 /* Work out the return pc - either from the saved pr or the pr
1765 value */
1766 }
1767
1768 /* Initialize the extra info saved in a FRAME */
1769 static void
1770 sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1771 {
1772
1773 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1774
1775 if (get_next_frame (fi))
1776 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1777
1778 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1779 get_frame_base (fi)))
1780 {
1781 /* We need to setup fi->frame here because call_function_by_hand
1782 gets it wrong by assuming it's always FP. */
1783 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi),
1784 SP_REGNUM));
1785 get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi),
1786 get_frame_base (fi),
1787 PC_REGNUM);
1788 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1789 get_frame_extra_info (fi)->leaf_function = 0;
1790 return;
1791 }
1792 else
1793 {
1794 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1795 get_frame_extra_info (fi)->return_pc =
1796 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1797 }
1798 }
1799
1800 static void
1801 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1802 {
1803 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1804
1805 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1806
1807 if (get_next_frame (fi))
1808 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1809
1810 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1811 get_frame_base (fi)))
1812 {
1813 /* We need to setup fi->frame here because call_function_by_hand
1814 gets it wrong by assuming it's always FP. */
1815 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1816 get_frame_extra_info (fi)->return_pc =
1817 deprecated_read_register_dummy (get_frame_pc (fi),
1818 get_frame_base (fi), PC_REGNUM);
1819 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1820 get_frame_extra_info (fi)->leaf_function = 0;
1821 return;
1822 }
1823 else
1824 {
1825 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1826 get_frame_extra_info (fi)->return_pc =
1827 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1828 }
1829 }
1830
1831 static void
1832 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1833 struct frame_info *frame, int regnum,
1834 enum lval_type *lval)
1835 {
1836 int media_mode;
1837 int live_regnum = regnum;
1838 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1839
1840 if (!target_has_registers)
1841 error ("No registers.");
1842
1843 /* Normal systems don't optimize out things with register numbers. */
1844 if (optimized != NULL)
1845 *optimized = 0;
1846
1847 if (addrp) /* default assumption: not found in memory */
1848 *addrp = 0;
1849
1850 if (raw_buffer)
1851 memset (raw_buffer, 0, sizeof (raw_buffer));
1852
1853 /* We must do this here, before the following while loop changes
1854 frame, and makes it NULL. If this is a media register number,
1855 but we are in compact mode, it will become the corresponding
1856 compact pseudo register. If there is no corresponding compact
1857 pseudo-register what do we do?*/
1858 media_mode = pc_is_isa32 (get_frame_pc (frame));
1859 live_regnum = translate_insn_rn (regnum, media_mode);
1860
1861 /* Note: since the current frame's registers could only have been
1862 saved by frames INTERIOR TO the current frame, we skip examining
1863 the current frame itself: otherwise, we would be getting the
1864 previous frame's registers which were saved by the current frame. */
1865
1866 while (frame && ((frame = get_next_frame (frame)) != NULL))
1867 {
1868 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1869 get_frame_base (frame),
1870 get_frame_base (frame)))
1871 {
1872 if (lval) /* found it in a CALL_DUMMY frame */
1873 *lval = not_lval;
1874 if (raw_buffer)
1875 memcpy (raw_buffer,
1876 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
1877 + REGISTER_BYTE (regnum)),
1878 REGISTER_RAW_SIZE (regnum));
1879 return;
1880 }
1881
1882 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1883 if (get_frame_saved_regs (frame) != NULL
1884 && get_frame_saved_regs (frame)[regnum] != 0)
1885 {
1886 if (lval) /* found it saved on the stack */
1887 *lval = lval_memory;
1888 if (regnum == SP_REGNUM)
1889 {
1890 if (raw_buffer) /* SP register treated specially */
1891 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum),
1892 get_frame_saved_regs (frame)[regnum]);
1893 }
1894 else
1895 { /* any other register */
1896
1897 if (addrp)
1898 *addrp = get_frame_saved_regs (frame)[regnum];
1899 if (raw_buffer)
1900 {
1901 int size;
1902 if (tdep->sh_abi == SH_ABI_32
1903 && (live_regnum == DEPRECATED_FP_REGNUM
1904 || live_regnum == tdep->PR_REGNUM))
1905 size = 4;
1906 else
1907 size = REGISTER_RAW_SIZE (live_regnum);
1908 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1909 read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size);
1910 else
1911 read_memory (get_frame_saved_regs (frame)[regnum],
1912 raw_buffer
1913 + REGISTER_RAW_SIZE (live_regnum)
1914 - size,
1915 size);
1916 }
1917 }
1918 return;
1919 }
1920 }
1921
1922 /* If we get thru the loop to this point, it means the register was
1923 not saved in any frame. Return the actual live-register value. */
1924
1925 if (lval) /* found it in a live register */
1926 *lval = lval_register;
1927 if (addrp)
1928 *addrp = REGISTER_BYTE (live_regnum);
1929 if (raw_buffer)
1930 deprecated_read_register_gen (live_regnum, raw_buffer);
1931 }
1932
1933 /* Extract from an array REGBUF containing the (raw) register state
1934 the address in which a function should return its structure value,
1935 as a CORE_ADDR (or an expression that can be used as one). */
1936 static CORE_ADDR
1937 sh_extract_struct_value_address (struct regcache *regcache)
1938 {
1939 ULONGEST addr;
1940 /*FIXME: Is R0 really correct here? Not STRUCT_RETURN_REGNUM? */
1941 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
1942 return addr;
1943 }
1944
1945 static CORE_ADDR
1946 sh64_extract_struct_value_address (char *regbuf)
1947 {
1948 return (extract_unsigned_integer ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1949 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1950 }
1951
1952 static CORE_ADDR
1953 sh_frame_saved_pc (struct frame_info *frame)
1954 {
1955 return (get_frame_extra_info (frame)->return_pc);
1956 }
1957
1958 /* Discard from the stack the innermost frame,
1959 restoring all saved registers. */
1960 static void
1961 sh_pop_frame (void)
1962 {
1963 register struct frame_info *frame = get_current_frame ();
1964 register CORE_ADDR fp;
1965 register int regnum;
1966
1967 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1968 get_frame_base (frame),
1969 get_frame_base (frame)))
1970 generic_pop_dummy_frame ();
1971 else
1972 {
1973 fp = get_frame_base (frame);
1974 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1975
1976 /* Copy regs from where they were saved in the frame */
1977 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1978 if (get_frame_saved_regs (frame)[regnum])
1979 write_register (regnum,
1980 read_memory_integer (get_frame_saved_regs (frame)[regnum], 4));
1981
1982 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1983 write_register (SP_REGNUM, fp + 4);
1984 }
1985 flush_cached_frames ();
1986 }
1987
1988 /* Used in the 'return' command. */
1989 static void
1990 sh64_pop_frame (void)
1991 {
1992 register struct frame_info *frame = get_current_frame ();
1993 register CORE_ADDR fp;
1994 register int regnum;
1995 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1996
1997 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1998
1999 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
2000 get_frame_base (frame),
2001 get_frame_base (frame)))
2002 generic_pop_dummy_frame ();
2003 else
2004 {
2005 fp = get_frame_base (frame);
2006 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
2007
2008 /* Copy regs from where they were saved in the frame */
2009 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
2010 if (get_frame_saved_regs (frame)[regnum])
2011 {
2012 int size;
2013 if (tdep->sh_abi == SH_ABI_32
2014 && (regnum == DEPRECATED_FP_REGNUM
2015 || regnum == tdep->PR_REGNUM))
2016 size = 4;
2017 else
2018 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
2019 media_mode));
2020 write_register (regnum,
2021 read_memory_integer (get_frame_saved_regs (frame)[regnum],
2022 size));
2023 }
2024
2025 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
2026 write_register (SP_REGNUM, fp + 8);
2027 }
2028 flush_cached_frames ();
2029 }
2030
2031 /* Function: push_arguments
2032 Setup the function arguments for calling a function in the inferior.
2033
2034 On the Hitachi SH architecture, there are four registers (R4 to R7)
2035 which are dedicated for passing function arguments. Up to the first
2036 four arguments (depending on size) may go into these registers.
2037 The rest go on the stack.
2038
2039 Arguments that are smaller than 4 bytes will still take up a whole
2040 register or a whole 32-bit word on the stack, and will be
2041 right-justified in the register or the stack word. This includes
2042 chars, shorts, and small aggregate types.
2043
2044 Arguments that are larger than 4 bytes may be split between two or
2045 more registers. If there are not enough registers free, an argument
2046 may be passed partly in a register (or registers), and partly on the
2047 stack. This includes doubles, long longs, and larger aggregates.
2048 As far as I know, there is no upper limit to the size of aggregates
2049 that will be passed in this way; in other words, the convention of
2050 passing a pointer to a large aggregate instead of a copy is not used.
2051
2052 An exceptional case exists for struct arguments (and possibly other
2053 aggregates such as arrays) if the size is larger than 4 bytes but
2054 not a multiple of 4 bytes. In this case the argument is never split
2055 between the registers and the stack, but instead is copied in its
2056 entirety onto the stack, AND also copied into as many registers as
2057 there is room for. In other words, space in registers permitting,
2058 two copies of the same argument are passed in. As far as I can tell,
2059 only the one on the stack is used, although that may be a function
2060 of the level of compiler optimization. I suspect this is a compiler
2061 bug. Arguments of these odd sizes are left-justified within the
2062 word (as opposed to arguments smaller than 4 bytes, which are
2063 right-justified).
2064
2065 If the function is to return an aggregate type such as a struct, it
2066 is either returned in the normal return value register R0 (if its
2067 size is no greater than one byte), or else the caller must allocate
2068 space into which the callee will copy the return value (if the size
2069 is greater than one byte). In this case, a pointer to the return
2070 value location is passed into the callee in register R2, which does
2071 not displace any of the other arguments passed in via registers R4
2072 to R7. */
2073
2074 static CORE_ADDR
2075 sh_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2076 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2077 struct value **args, CORE_ADDR sp, int struct_return,
2078 CORE_ADDR struct_addr)
2079
2080 {
2081 int stack_offset, stack_alloc;
2082 int argreg;
2083 int argnum;
2084 struct type *type;
2085 CORE_ADDR regval;
2086 char *val;
2087 char valbuf[4];
2088 int len;
2089 int odd_sized_struct;
2090 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2091
2092 /* first force sp to a 4-byte alignment */
2093 sp = sp & ~3;
2094
2095 /* The "struct return pointer" pseudo-argument has its own dedicated
2096 register */
2097 if (struct_return)
2098 regcache_cooked_write_unsigned (regcache, STRUCT_RETURN_REGNUM, struct_addr);
2099
2100 /* Now make sure there's space on the stack */
2101 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2102 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2103 sp -= stack_alloc; /* make room on stack for args */
2104
2105 /* Now load as many as possible of the first arguments into
2106 registers, and push the rest onto the stack. There are 16 bytes
2107 in four registers available. Loop thru args from first to last. */
2108
2109 argreg = tdep->ARG0_REGNUM;
2110 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2111 {
2112 type = VALUE_TYPE (args[argnum]);
2113 len = TYPE_LENGTH (type);
2114 memset (valbuf, 0, sizeof (valbuf));
2115 if (len < 4)
2116 {
2117 /* value gets right-justified in the register or stack word */
2118 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2119 memcpy (valbuf + (4 - len),
2120 (char *) VALUE_CONTENTS (args[argnum]), len);
2121 else
2122 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2123 val = valbuf;
2124 }
2125 else
2126 val = (char *) VALUE_CONTENTS (args[argnum]);
2127
2128 if (len > 4 && (len & 3) != 0)
2129 odd_sized_struct = 1; /* such structs go entirely on stack */
2130 else
2131 odd_sized_struct = 0;
2132 while (len > 0)
2133 {
2134 if (argreg > tdep->ARGLAST_REGNUM
2135 || odd_sized_struct)
2136 {
2137 /* must go on the stack */
2138 write_memory (sp + stack_offset, val, 4);
2139 stack_offset += 4;
2140 }
2141 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2142 That's because some *&^%$ things get passed on the stack
2143 AND in the registers! */
2144 if (argreg <= tdep->ARGLAST_REGNUM)
2145 {
2146 /* there's room in a register */
2147 regval = extract_unsigned_integer (val, register_size (gdbarch,
2148 argreg));
2149 regcache_cooked_write_unsigned (regcache, argreg++, regval);
2150 }
2151 /* Store the value 4 bytes at a time. This means that things
2152 larger than 4 bytes may go partly in registers and partly
2153 on the stack. */
2154 len -= register_size (gdbarch, argreg);
2155 val += register_size (gdbarch, argreg);
2156 }
2157 }
2158
2159 /* Store return address. */
2160 regcache_cooked_write_unsigned (regcache, tdep->PR_REGNUM, bp_addr);
2161
2162 /* Update stack pointer. */
2163 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
2164
2165 return sp;
2166 }
2167
2168 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2169 non-scalar (struct, union) elements (even if the elements are
2170 floats).
2171 FR0-FR11 for single precision floating point (float)
2172 DR0-DR10 for double precision floating point (double)
2173
2174 If a float is argument number 3 (for instance) and arguments number
2175 1,2, and 4 are integer, the mapping will be:
2176 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2177
2178 If a float is argument number 10 (for instance) and arguments number
2179 1 through 10 are integer, the mapping will be:
2180 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2181 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2182 I.e. there is hole in the stack.
2183
2184 Different rules apply for variable arguments functions, and for functions
2185 for which the prototype is not known. */
2186
2187 static CORE_ADDR
2188 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2189 int struct_return, CORE_ADDR struct_addr)
2190 {
2191 int stack_offset, stack_alloc;
2192 int int_argreg;
2193 int float_argreg;
2194 int double_argreg;
2195 int float_arg_index = 0;
2196 int double_arg_index = 0;
2197 int argnum;
2198 struct type *type;
2199 CORE_ADDR regval;
2200 char *val;
2201 char valbuf[8];
2202 char valbuf_tmp[8];
2203 int len;
2204 int argreg_size;
2205 int fp_args[12];
2206 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2207
2208 memset (fp_args, 0, sizeof (fp_args));
2209
2210 /* first force sp to a 8-byte alignment */
2211 sp = sp & ~7;
2212
2213 /* The "struct return pointer" pseudo-argument has its own dedicated
2214 register */
2215
2216 if (struct_return)
2217 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2218
2219 /* Now make sure there's space on the stack */
2220 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2221 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2222 sp -= stack_alloc; /* make room on stack for args */
2223
2224 /* Now load as many as possible of the first arguments into
2225 registers, and push the rest onto the stack. There are 64 bytes
2226 in eight registers available. Loop thru args from first to last. */
2227
2228 int_argreg = tdep->ARG0_REGNUM;
2229 float_argreg = FP0_REGNUM;
2230 double_argreg = tdep->DR0_REGNUM;
2231
2232 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2233 {
2234 type = VALUE_TYPE (args[argnum]);
2235 len = TYPE_LENGTH (type);
2236 memset (valbuf, 0, sizeof (valbuf));
2237
2238 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2239 {
2240 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2241
2242 if (len < argreg_size)
2243 {
2244 /* value gets right-justified in the register or stack word */
2245 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2246 memcpy (valbuf + argreg_size - len,
2247 (char *) VALUE_CONTENTS (args[argnum]), len);
2248 else
2249 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2250
2251 val = valbuf;
2252 }
2253 else
2254 val = (char *) VALUE_CONTENTS (args[argnum]);
2255
2256 while (len > 0)
2257 {
2258 if (int_argreg > tdep->ARGLAST_REGNUM)
2259 {
2260 /* must go on the stack */
2261 write_memory (sp + stack_offset, val, argreg_size);
2262 stack_offset += 8;/*argreg_size;*/
2263 }
2264 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2265 That's because some *&^%$ things get passed on the stack
2266 AND in the registers! */
2267 if (int_argreg <= tdep->ARGLAST_REGNUM)
2268 {
2269 /* there's room in a register */
2270 regval = extract_unsigned_integer (val, argreg_size);
2271 write_register (int_argreg, regval);
2272 }
2273 /* Store the value 8 bytes at a time. This means that
2274 things larger than 8 bytes may go partly in registers
2275 and partly on the stack. FIXME: argreg is incremented
2276 before we use its size. */
2277 len -= argreg_size;
2278 val += argreg_size;
2279 int_argreg++;
2280 }
2281 }
2282 else
2283 {
2284 val = (char *) VALUE_CONTENTS (args[argnum]);
2285 if (len == 4)
2286 {
2287 /* Where is it going to be stored? */
2288 while (fp_args[float_arg_index])
2289 float_arg_index ++;
2290
2291 /* Now float_argreg points to the register where it
2292 should be stored. Are we still within the allowed
2293 register set? */
2294 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2295 {
2296 /* Goes in FR0...FR11 */
2297 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
2298 val);
2299 fp_args[float_arg_index] = 1;
2300 /* Skip the corresponding general argument register. */
2301 int_argreg ++;
2302 }
2303 else
2304 ;
2305 /* Store it as the integers, 8 bytes at the time, if
2306 necessary spilling on the stack. */
2307
2308 }
2309 else if (len == 8)
2310 {
2311 /* Where is it going to be stored? */
2312 while (fp_args[double_arg_index])
2313 double_arg_index += 2;
2314 /* Now double_argreg points to the register
2315 where it should be stored.
2316 Are we still within the allowed register set? */
2317 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2318 {
2319 /* Goes in DR0...DR10 */
2320 /* The numbering of the DRi registers is consecutive,
2321 i.e. includes odd numbers. */
2322 int double_register_offset = double_arg_index / 2;
2323 int regnum = tdep->DR0_REGNUM +
2324 double_register_offset;
2325 #if 0
2326 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2327 {
2328 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2329 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
2330 type, val,
2331 valbuf_tmp);
2332 val = valbuf_tmp;
2333 }
2334 #endif
2335 /* Note: must use write_register_gen here instead
2336 of regcache_raw_write, because
2337 regcache_raw_write works only for real
2338 registers, not pseudo. write_register_gen will
2339 call the gdbarch function to do register
2340 writes, and that will properly know how to deal
2341 with pseudoregs. */
2342 deprecated_write_register_gen (regnum, val);
2343 fp_args[double_arg_index] = 1;
2344 fp_args[double_arg_index + 1] = 1;
2345 /* Skip the corresponding general argument register. */
2346 int_argreg ++;
2347 }
2348 else
2349 ;
2350 /* Store it as the integers, 8 bytes at the time, if
2351 necessary spilling on the stack. */
2352 }
2353 }
2354 }
2355 return sp;
2356 }
2357
2358 /* Function: push_return_address (pc)
2359 Set up the return address for the inferior function call.
2360 Needed for targets where we don't actually execute a JSR/BSR instruction */
2361
2362 static CORE_ADDR
2363 sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2364 {
2365 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2366 CALL_DUMMY_ADDRESS ());
2367 return sp;
2368 }
2369
2370 /* Function: fix_call_dummy
2371 Poke the callee function's address into the destination part of
2372 the CALL_DUMMY. The address is actually stored in a data word
2373 following the actualy CALL_DUMMY instructions, which will load
2374 it into a register using PC-relative addressing. This function
2375 expects the CALL_DUMMY to look like this:
2376
2377 mov.w @(2,PC), R8
2378 jsr @R8
2379 nop
2380 trap
2381 <destination>
2382 */
2383
2384 #if 0
2385 void
2386 sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
2387 struct value **args, struct type *type, int gcc_p)
2388 {
2389 *(unsigned long *) (dummy + 8) = fun;
2390 }
2391 #endif
2392
2393 /* Find a function's return value in the appropriate registers (in
2394 regbuf), and copy it into valbuf. Extract from an array REGBUF
2395 containing the (raw) register state a function return value of type
2396 TYPE, and copy that, in virtual format, into VALBUF. */
2397 static void
2398 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
2399 void *valbuf)
2400 {
2401 int len = TYPE_LENGTH (type);
2402 int return_register = R0_REGNUM;
2403 int offset;
2404
2405 if (len <= 4)
2406 {
2407 ULONGEST c;
2408
2409 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
2410 store_unsigned_integer (valbuf, len, c);
2411 }
2412 else if (len == 8)
2413 {
2414 int i, regnum = R0_REGNUM;
2415 for (i = 0; i < len; i += 4)
2416 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
2417 }
2418 else
2419 error ("bad size for return value");
2420 }
2421
2422 static void
2423 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
2424 void *valbuf)
2425 {
2426 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2427 {
2428 int len = TYPE_LENGTH (type);
2429 int i, regnum = FP0_REGNUM;
2430 for (i = 0; i < len; i += 4)
2431 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
2432 }
2433 else
2434 sh_default_extract_return_value (type, regcache, valbuf);
2435 }
2436
2437 static void
2438 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2439 {
2440 int offset;
2441 int return_register;
2442 int len = TYPE_LENGTH (type);
2443 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2444
2445 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2446 {
2447 if (len == 4)
2448 {
2449 /* Return value stored in FP0_REGNUM */
2450 return_register = FP0_REGNUM;
2451 offset = REGISTER_BYTE (return_register);
2452 memcpy (valbuf, (char *) regbuf + offset, len);
2453 }
2454 else if (len == 8)
2455 {
2456 /* return value stored in DR0_REGNUM */
2457 DOUBLEST val;
2458
2459 return_register = tdep->DR0_REGNUM;
2460 offset = REGISTER_BYTE (return_register);
2461
2462 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2463 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2464 (char *) regbuf + offset, &val);
2465 else
2466 floatformat_to_doublest (&floatformat_ieee_double_big,
2467 (char *) regbuf + offset, &val);
2468 deprecated_store_floating (valbuf, len, val);
2469 }
2470 }
2471 else
2472 {
2473 if (len <= 8)
2474 {
2475 /* Result is in register 2. If smaller than 8 bytes, it is padded
2476 at the most significant end. */
2477 return_register = tdep->RETURN_REGNUM;
2478 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2479 offset = REGISTER_BYTE (return_register) +
2480 REGISTER_RAW_SIZE (return_register) - len;
2481 else
2482 offset = REGISTER_BYTE (return_register);
2483 memcpy (valbuf, (char *) regbuf + offset, len);
2484 }
2485 else
2486 error ("bad size for return value");
2487 }
2488 }
2489
2490 /* Write into appropriate registers a function return value
2491 of type TYPE, given in virtual format.
2492 If the architecture is sh4 or sh3e, store a function's return value
2493 in the R0 general register or in the FP0 floating point register,
2494 depending on the type of the return value. In all the other cases
2495 the result is stored in r0, left-justified. */
2496 static void
2497 sh_default_store_return_value (struct type *type, struct regcache *regcache,
2498 const void *valbuf)
2499 {
2500 ULONGEST val;
2501 int len = TYPE_LENGTH (type);
2502
2503 if (len <= 4)
2504 {
2505 val = extract_unsigned_integer (valbuf, len);
2506 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
2507 }
2508 else
2509 {
2510 int i, regnum = R0_REGNUM;
2511 for (i = 0; i < len; i += 4)
2512 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
2513 }
2514 }
2515
2516 static void
2517 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
2518 const void *valbuf)
2519 {
2520 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2521 {
2522 int len = TYPE_LENGTH (type);
2523 int i, regnum = FP0_REGNUM;
2524 for (i = 0; i < len; i += 4)
2525 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
2526 }
2527 else
2528 sh_default_store_return_value (type, regcache, valbuf);
2529 }
2530
2531 static void
2532 sh64_store_return_value (struct type *type, char *valbuf)
2533 {
2534 char buf[64]; /* more than enough... */
2535 int len = TYPE_LENGTH (type);
2536
2537 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2538 {
2539 if (len == 4)
2540 {
2541 /* Return value stored in FP0_REGNUM */
2542 deprecated_write_register_gen (FP0_REGNUM, valbuf);
2543 }
2544 if (len == 8)
2545 {
2546 /* return value stored in DR0_REGNUM */
2547 /* FIXME: Implement */
2548 }
2549 }
2550 else
2551 {
2552 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2553 int offset = 0;
2554
2555 if (len <= REGISTER_RAW_SIZE (return_register))
2556 {
2557 /* Pad with zeros. */
2558 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2559 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2560 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2561 else
2562 offset = REGISTER_RAW_SIZE (return_register) - len;
2563
2564 memcpy (buf + offset, valbuf, len);
2565 deprecated_write_register_gen (return_register, buf);
2566 }
2567 else
2568 deprecated_write_register_gen (return_register, valbuf);
2569 }
2570 }
2571
2572 /* Print the registers in a form similar to the E7000 */
2573
2574 static void
2575 sh_generic_show_regs (void)
2576 {
2577 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2578
2579 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2580 paddr (read_register (PC_REGNUM)),
2581 (long) read_register (tdep->SR_REGNUM),
2582 (long) read_register (tdep->PR_REGNUM),
2583 (long) read_register (MACH_REGNUM),
2584 (long) read_register (MACL_REGNUM));
2585
2586 printf_filtered ("GBR=%08lx VBR=%08lx",
2587 (long) read_register (GBR_REGNUM),
2588 (long) read_register (VBR_REGNUM));
2589
2590 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2591 (long) read_register (0),
2592 (long) read_register (1),
2593 (long) read_register (2),
2594 (long) read_register (3),
2595 (long) read_register (4),
2596 (long) read_register (5),
2597 (long) read_register (6),
2598 (long) read_register (7));
2599 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2600 (long) read_register (8),
2601 (long) read_register (9),
2602 (long) read_register (10),
2603 (long) read_register (11),
2604 (long) read_register (12),
2605 (long) read_register (13),
2606 (long) read_register (14),
2607 (long) read_register (15));
2608 }
2609
2610 static void
2611 sh3_show_regs (void)
2612 {
2613 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2614
2615 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2616 paddr (read_register (PC_REGNUM)),
2617 (long) read_register (tdep->SR_REGNUM),
2618 (long) read_register (tdep->PR_REGNUM),
2619 (long) read_register (MACH_REGNUM),
2620 (long) read_register (MACL_REGNUM));
2621
2622 printf_filtered ("GBR=%08lx VBR=%08lx",
2623 (long) read_register (GBR_REGNUM),
2624 (long) read_register (VBR_REGNUM));
2625 printf_filtered (" SSR=%08lx SPC=%08lx",
2626 (long) read_register (tdep->SSR_REGNUM),
2627 (long) read_register (tdep->SPC_REGNUM));
2628
2629 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2630 (long) read_register (0),
2631 (long) read_register (1),
2632 (long) read_register (2),
2633 (long) read_register (3),
2634 (long) read_register (4),
2635 (long) read_register (5),
2636 (long) read_register (6),
2637 (long) read_register (7));
2638 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2639 (long) read_register (8),
2640 (long) read_register (9),
2641 (long) read_register (10),
2642 (long) read_register (11),
2643 (long) read_register (12),
2644 (long) read_register (13),
2645 (long) read_register (14),
2646 (long) read_register (15));
2647 }
2648
2649
2650 static void
2651 sh2e_show_regs (void)
2652 {
2653 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2654 paddr (read_register (PC_REGNUM)),
2655 (long) read_register (SR_REGNUM),
2656 (long) read_register (PR_REGNUM),
2657 (long) read_register (MACH_REGNUM),
2658 (long) read_register (MACL_REGNUM));
2659
2660 printf_filtered ("GBR=%08lx VBR=%08lx",
2661 (long) read_register (GBR_REGNUM),
2662 (long) read_register (VBR_REGNUM));
2663 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2664 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
2665 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
2666
2667 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2668 (long) read_register (0),
2669 (long) read_register (1),
2670 (long) read_register (2),
2671 (long) read_register (3),
2672 (long) read_register (4),
2673 (long) read_register (5),
2674 (long) read_register (6),
2675 (long) read_register (7));
2676 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2677 (long) read_register (8),
2678 (long) read_register (9),
2679 (long) read_register (10),
2680 (long) read_register (11),
2681 (long) read_register (12),
2682 (long) read_register (13),
2683 (long) read_register (14),
2684 (long) read_register (15));
2685
2686 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2687 (long) read_register (FP0_REGNUM + 0),
2688 (long) read_register (FP0_REGNUM + 1),
2689 (long) read_register (FP0_REGNUM + 2),
2690 (long) read_register (FP0_REGNUM + 3),
2691 (long) read_register (FP0_REGNUM + 4),
2692 (long) read_register (FP0_REGNUM + 5),
2693 (long) read_register (FP0_REGNUM + 6),
2694 (long) read_register (FP0_REGNUM + 7));
2695 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2696 (long) read_register (FP0_REGNUM + 8),
2697 (long) read_register (FP0_REGNUM + 9),
2698 (long) read_register (FP0_REGNUM + 10),
2699 (long) read_register (FP0_REGNUM + 11),
2700 (long) read_register (FP0_REGNUM + 12),
2701 (long) read_register (FP0_REGNUM + 13),
2702 (long) read_register (FP0_REGNUM + 14),
2703 (long) read_register (FP0_REGNUM + 15));
2704 }
2705
2706 static void
2707 sh3e_show_regs (void)
2708 {
2709 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2710
2711 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2712 paddr (read_register (PC_REGNUM)),
2713 (long) read_register (tdep->SR_REGNUM),
2714 (long) read_register (tdep->PR_REGNUM),
2715 (long) read_register (MACH_REGNUM),
2716 (long) read_register (MACL_REGNUM));
2717
2718 printf_filtered ("GBR=%08lx VBR=%08lx",
2719 (long) read_register (GBR_REGNUM),
2720 (long) read_register (VBR_REGNUM));
2721 printf_filtered (" SSR=%08lx SPC=%08lx",
2722 (long) read_register (tdep->SSR_REGNUM),
2723 (long) read_register (tdep->SPC_REGNUM));
2724 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2725 (long) read_register (tdep->FPUL_REGNUM),
2726 (long) read_register (tdep->FPSCR_REGNUM));
2727
2728 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2729 (long) read_register (0),
2730 (long) read_register (1),
2731 (long) read_register (2),
2732 (long) read_register (3),
2733 (long) read_register (4),
2734 (long) read_register (5),
2735 (long) read_register (6),
2736 (long) read_register (7));
2737 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2738 (long) read_register (8),
2739 (long) read_register (9),
2740 (long) read_register (10),
2741 (long) read_register (11),
2742 (long) read_register (12),
2743 (long) read_register (13),
2744 (long) read_register (14),
2745 (long) read_register (15));
2746
2747 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2748 (long) read_register (FP0_REGNUM + 0),
2749 (long) read_register (FP0_REGNUM + 1),
2750 (long) read_register (FP0_REGNUM + 2),
2751 (long) read_register (FP0_REGNUM + 3),
2752 (long) read_register (FP0_REGNUM + 4),
2753 (long) read_register (FP0_REGNUM + 5),
2754 (long) read_register (FP0_REGNUM + 6),
2755 (long) read_register (FP0_REGNUM + 7));
2756 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2757 (long) read_register (FP0_REGNUM + 8),
2758 (long) read_register (FP0_REGNUM + 9),
2759 (long) read_register (FP0_REGNUM + 10),
2760 (long) read_register (FP0_REGNUM + 11),
2761 (long) read_register (FP0_REGNUM + 12),
2762 (long) read_register (FP0_REGNUM + 13),
2763 (long) read_register (FP0_REGNUM + 14),
2764 (long) read_register (FP0_REGNUM + 15));
2765 }
2766
2767 static void
2768 sh3_dsp_show_regs (void)
2769 {
2770 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2771
2772 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2773 paddr (read_register (PC_REGNUM)),
2774 (long) read_register (tdep->SR_REGNUM),
2775 (long) read_register (tdep->PR_REGNUM),
2776 (long) read_register (MACH_REGNUM),
2777 (long) read_register (MACL_REGNUM));
2778
2779 printf_filtered ("GBR=%08lx VBR=%08lx",
2780 (long) read_register (GBR_REGNUM),
2781 (long) read_register (VBR_REGNUM));
2782
2783 printf_filtered (" SSR=%08lx SPC=%08lx",
2784 (long) read_register (tdep->SSR_REGNUM),
2785 (long) read_register (tdep->SPC_REGNUM));
2786
2787 printf_filtered (" DSR=%08lx",
2788 (long) read_register (tdep->DSR_REGNUM));
2789
2790 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2791 (long) read_register (0),
2792 (long) read_register (1),
2793 (long) read_register (2),
2794 (long) read_register (3),
2795 (long) read_register (4),
2796 (long) read_register (5),
2797 (long) read_register (6),
2798 (long) read_register (7));
2799 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2800 (long) read_register (8),
2801 (long) read_register (9),
2802 (long) read_register (10),
2803 (long) read_register (11),
2804 (long) read_register (12),
2805 (long) read_register (13),
2806 (long) read_register (14),
2807 (long) read_register (15));
2808
2809 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2810 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2811 (long) read_register (tdep->A0_REGNUM),
2812 (long) read_register (tdep->M0_REGNUM),
2813 (long) read_register (tdep->X0_REGNUM),
2814 (long) read_register (tdep->Y0_REGNUM),
2815 (long) read_register (tdep->RS_REGNUM),
2816 (long) read_register (tdep->MOD_REGNUM));
2817 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2818 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2819 (long) read_register (tdep->A1_REGNUM),
2820 (long) read_register (tdep->M1_REGNUM),
2821 (long) read_register (tdep->X1_REGNUM),
2822 (long) read_register (tdep->Y1_REGNUM),
2823 (long) read_register (tdep->RE_REGNUM));
2824 }
2825
2826 static void
2827 sh4_show_regs (void)
2828 {
2829 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2830
2831 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
2832 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2833 paddr (read_register (PC_REGNUM)),
2834 (long) read_register (tdep->SR_REGNUM),
2835 (long) read_register (tdep->PR_REGNUM),
2836 (long) read_register (MACH_REGNUM),
2837 (long) read_register (MACL_REGNUM));
2838
2839 printf_filtered ("GBR=%08lx VBR=%08lx",
2840 (long) read_register (GBR_REGNUM),
2841 (long) read_register (VBR_REGNUM));
2842 printf_filtered (" SSR=%08lx SPC=%08lx",
2843 (long) read_register (tdep->SSR_REGNUM),
2844 (long) read_register (tdep->SPC_REGNUM));
2845 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2846 (long) read_register (tdep->FPUL_REGNUM),
2847 (long) read_register (tdep->FPSCR_REGNUM));
2848
2849 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2850 (long) read_register (0),
2851 (long) read_register (1),
2852 (long) read_register (2),
2853 (long) read_register (3),
2854 (long) read_register (4),
2855 (long) read_register (5),
2856 (long) read_register (6),
2857 (long) read_register (7));
2858 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2859 (long) read_register (8),
2860 (long) read_register (9),
2861 (long) read_register (10),
2862 (long) read_register (11),
2863 (long) read_register (12),
2864 (long) read_register (13),
2865 (long) read_register (14),
2866 (long) read_register (15));
2867
2868 printf_filtered ((pr
2869 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2870 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2871 (long) read_register (FP0_REGNUM + 0),
2872 (long) read_register (FP0_REGNUM + 1),
2873 (long) read_register (FP0_REGNUM + 2),
2874 (long) read_register (FP0_REGNUM + 3),
2875 (long) read_register (FP0_REGNUM + 4),
2876 (long) read_register (FP0_REGNUM + 5),
2877 (long) read_register (FP0_REGNUM + 6),
2878 (long) read_register (FP0_REGNUM + 7));
2879 printf_filtered ((pr
2880 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2881 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2882 (long) read_register (FP0_REGNUM + 8),
2883 (long) read_register (FP0_REGNUM + 9),
2884 (long) read_register (FP0_REGNUM + 10),
2885 (long) read_register (FP0_REGNUM + 11),
2886 (long) read_register (FP0_REGNUM + 12),
2887 (long) read_register (FP0_REGNUM + 13),
2888 (long) read_register (FP0_REGNUM + 14),
2889 (long) read_register (FP0_REGNUM + 15));
2890 }
2891
2892 static void
2893 sh_dsp_show_regs (void)
2894 {
2895 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2896
2897 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2898 paddr (read_register (PC_REGNUM)),
2899 (long) read_register (tdep->SR_REGNUM),
2900 (long) read_register (tdep->PR_REGNUM),
2901 (long) read_register (MACH_REGNUM),
2902 (long) read_register (MACL_REGNUM));
2903
2904 printf_filtered ("GBR=%08lx VBR=%08lx",
2905 (long) read_register (GBR_REGNUM),
2906 (long) read_register (VBR_REGNUM));
2907
2908 printf_filtered (" DSR=%08lx",
2909 (long) read_register (tdep->DSR_REGNUM));
2910
2911 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2912 (long) read_register (0),
2913 (long) read_register (1),
2914 (long) read_register (2),
2915 (long) read_register (3),
2916 (long) read_register (4),
2917 (long) read_register (5),
2918 (long) read_register (6),
2919 (long) read_register (7));
2920 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2921 (long) read_register (8),
2922 (long) read_register (9),
2923 (long) read_register (10),
2924 (long) read_register (11),
2925 (long) read_register (12),
2926 (long) read_register (13),
2927 (long) read_register (14),
2928 (long) read_register (15));
2929
2930 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2931 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2932 (long) read_register (tdep->A0_REGNUM),
2933 (long) read_register (tdep->M0_REGNUM),
2934 (long) read_register (tdep->X0_REGNUM),
2935 (long) read_register (tdep->Y0_REGNUM),
2936 (long) read_register (tdep->RS_REGNUM),
2937 (long) read_register (tdep->MOD_REGNUM));
2938 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2939 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2940 (long) read_register (tdep->A1_REGNUM),
2941 (long) read_register (tdep->M1_REGNUM),
2942 (long) read_register (tdep->X1_REGNUM),
2943 (long) read_register (tdep->Y1_REGNUM),
2944 (long) read_register (tdep->RE_REGNUM));
2945 }
2946
2947 static void
2948 sh64_show_media_regs (void)
2949 {
2950 int i;
2951 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2952
2953 printf_filtered ("PC=%s SR=%016llx \n",
2954 paddr (read_register (PC_REGNUM)),
2955 (long long) read_register (tdep->SR_REGNUM));
2956
2957 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2958 (long long) read_register (tdep->SSR_REGNUM),
2959 (long long) read_register (tdep->SPC_REGNUM));
2960 printf_filtered ("FPSCR=%016lx\n ",
2961 (long) read_register (tdep->FPSCR_REGNUM));
2962
2963 for (i = 0; i < 64; i = i + 4)
2964 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2965 i, i + 3,
2966 (long long) read_register (i + 0),
2967 (long long) read_register (i + 1),
2968 (long long) read_register (i + 2),
2969 (long long) read_register (i + 3));
2970
2971 printf_filtered ("\n");
2972
2973 for (i = 0; i < 64; i = i + 8)
2974 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2975 i, i + 7,
2976 (long) read_register (FP0_REGNUM + i + 0),
2977 (long) read_register (FP0_REGNUM + i + 1),
2978 (long) read_register (FP0_REGNUM + i + 2),
2979 (long) read_register (FP0_REGNUM + i + 3),
2980 (long) read_register (FP0_REGNUM + i + 4),
2981 (long) read_register (FP0_REGNUM + i + 5),
2982 (long) read_register (FP0_REGNUM + i + 6),
2983 (long) read_register (FP0_REGNUM + i + 7));
2984 }
2985
2986 static void
2987 sh64_show_compact_regs (void)
2988 {
2989 int i;
2990 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2991
2992 printf_filtered ("PC=%s \n",
2993 paddr (read_register (tdep->PC_C_REGNUM)));
2994
2995 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2996 (long) read_register (tdep->GBR_C_REGNUM),
2997 (long) read_register (tdep->MACH_C_REGNUM),
2998 (long) read_register (tdep->MACL_C_REGNUM),
2999 (long) read_register (tdep->PR_C_REGNUM),
3000 (long) read_register (tdep->T_C_REGNUM));
3001 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
3002 (long) read_register (tdep->FPSCR_REGNUM),
3003 (long) read_register (tdep->FPUL_REGNUM));
3004
3005 for (i = 0; i < 16; i = i + 4)
3006 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
3007 i, i + 3,
3008 (long) read_register (i + 0),
3009 (long) read_register (i + 1),
3010 (long) read_register (i + 2),
3011 (long) read_register (i + 3));
3012
3013 printf_filtered ("\n");
3014
3015 for (i = 0; i < 16; i = i + 8)
3016 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3017 i, i + 7,
3018 (long) read_register (FP0_REGNUM + i + 0),
3019 (long) read_register (FP0_REGNUM + i + 1),
3020 (long) read_register (FP0_REGNUM + i + 2),
3021 (long) read_register (FP0_REGNUM + i + 3),
3022 (long) read_register (FP0_REGNUM + i + 4),
3023 (long) read_register (FP0_REGNUM + i + 5),
3024 (long) read_register (FP0_REGNUM + i + 6),
3025 (long) read_register (FP0_REGNUM + i + 7));
3026 }
3027
3028 /*FIXME!!! This only shows the registers for shmedia, excluding the
3029 pseudo registers. */
3030 static void
3031 sh64_show_regs (void)
3032 {
3033 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
3034 sh64_show_media_regs ();
3035 else
3036 sh64_show_compact_regs ();
3037 }
3038
3039 static void
3040 sh_show_regs_command (char *args, int from_tty)
3041 {
3042 if (sh_show_regs)
3043 (*sh_show_regs)();
3044 }
3045
3046 /* *INDENT-OFF* */
3047 /*
3048 SH MEDIA MODE (ISA 32)
3049 general registers (64-bit) 0-63
3050 0 r0, r1, r2, r3, r4, r5, r6, r7,
3051 64 r8, r9, r10, r11, r12, r13, r14, r15,
3052 128 r16, r17, r18, r19, r20, r21, r22, r23,
3053 192 r24, r25, r26, r27, r28, r29, r30, r31,
3054 256 r32, r33, r34, r35, r36, r37, r38, r39,
3055 320 r40, r41, r42, r43, r44, r45, r46, r47,
3056 384 r48, r49, r50, r51, r52, r53, r54, r55,
3057 448 r56, r57, r58, r59, r60, r61, r62, r63,
3058
3059 pc (64-bit) 64
3060 512 pc,
3061
3062 status reg., saved status reg., saved pc reg. (64-bit) 65-67
3063 520 sr, ssr, spc,
3064
3065 target registers (64-bit) 68-75
3066 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3067
3068 floating point state control register (32-bit) 76
3069 608 fpscr,
3070
3071 single precision floating point registers (32-bit) 77-140
3072 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3073 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3074 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3075 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3076 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3077 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3078 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3079 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3080
3081 TOTAL SPACE FOR REGISTERS: 868 bytes
3082
3083 From here on they are all pseudo registers: no memory allocated.
3084 REGISTER_BYTE returns the register byte for the base register.
3085
3086 double precision registers (pseudo) 141-172
3087 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3088 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3089 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3090 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3091
3092 floating point pairs (pseudo) 173-204
3093 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3094 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3095 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3096 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3097
3098 floating point vectors (4 floating point regs) (pseudo) 205-220
3099 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3100 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3101
3102 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3103 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3104 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3105 pc_c,
3106 gbr_c, mach_c, macl_c, pr_c, t_c,
3107 fpscr_c, fpul_c,
3108 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3109 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3110 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3111 fv0_c, fv4_c, fv8_c, fv12_c
3112 */
3113 /* *INDENT-ON* */
3114 static int
3115 sh_sh64_register_byte (int reg_nr)
3116 {
3117 int base_regnum = -1;
3118 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3119
3120 /* If it is a pseudo register, get the number of the first floating
3121 point register that is part of it. */
3122 if (reg_nr >= tdep->DR0_REGNUM
3123 && reg_nr <= tdep->DR_LAST_REGNUM)
3124 base_regnum = dr_reg_base_num (reg_nr);
3125
3126 else if (reg_nr >= tdep->FPP0_REGNUM
3127 && reg_nr <= tdep->FPP_LAST_REGNUM)
3128 base_regnum = fpp_reg_base_num (reg_nr);
3129
3130 else if (reg_nr >= tdep->FV0_REGNUM
3131 && reg_nr <= tdep->FV_LAST_REGNUM)
3132 base_regnum = fv_reg_base_num (reg_nr);
3133
3134 /* sh compact pseudo register. FPSCR is a pathological case, need to
3135 treat it as special. */
3136 else if ((reg_nr >= tdep->R0_C_REGNUM
3137 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3138 && reg_nr != tdep->FPSCR_C_REGNUM)
3139 base_regnum = sh64_compact_reg_base_num (reg_nr);
3140
3141 /* Now return the offset in bytes within the register cache. */
3142 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3143 if (reg_nr >= tdep->DR0_REGNUM
3144 && reg_nr <= tdep->FV_LAST_REGNUM)
3145 return (base_regnum - FP0_REGNUM + 1) * 4
3146 + (tdep->TR7_REGNUM + 1) * 8;
3147
3148 /* sh compact pseudo register: general register */
3149 if ((reg_nr >= tdep->R0_C_REGNUM
3150 && reg_nr <= tdep->R_LAST_C_REGNUM))
3151 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3152 ? base_regnum * 8 + 4
3153 : base_regnum * 8);
3154
3155 /* sh compact pseudo register: */
3156 if (reg_nr == tdep->PC_C_REGNUM
3157 || reg_nr == tdep->GBR_C_REGNUM
3158 || reg_nr == tdep->MACL_C_REGNUM
3159 || reg_nr == tdep->PR_C_REGNUM)
3160 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3161 ? base_regnum * 8 + 4
3162 : base_regnum * 8);
3163
3164 if (reg_nr == tdep->MACH_C_REGNUM)
3165 return base_regnum * 8;
3166
3167 if (reg_nr == tdep->T_C_REGNUM)
3168 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3169
3170 /* sh compact pseudo register: floating point register */
3171 else if (reg_nr >=tdep->FP0_C_REGNUM
3172 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3173 return (base_regnum - FP0_REGNUM) * 4
3174 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3175
3176 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3177 /* This is complicated, for now return the beginning of the
3178 architectural FPSCR register. */
3179 return (tdep->TR7_REGNUM + 1) * 8;
3180
3181 else if (reg_nr == tdep->FPUL_C_REGNUM)
3182 return ((base_regnum - FP0_REGNUM) * 4 +
3183 (tdep->TR7_REGNUM + 1) * 8 + 4);
3184
3185 /* It is not a pseudo register. */
3186 /* It is a 64 bit register. */
3187 else if (reg_nr <= tdep->TR7_REGNUM)
3188 return reg_nr * 8;
3189
3190 /* It is a 32 bit register. */
3191 else
3192 if (reg_nr == tdep->FPSCR_REGNUM)
3193 return (tdep->FPSCR_REGNUM * 8);
3194
3195 /* It is floating point 32-bit register */
3196 else
3197 return ((tdep->TR7_REGNUM + 1) * 8
3198 + (reg_nr - FP0_REGNUM + 1) * 4);
3199 }
3200
3201 static int
3202 sh_sh64_register_raw_size (int reg_nr)
3203 {
3204 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3205
3206 if ((reg_nr >= tdep->DR0_REGNUM
3207 && reg_nr <= tdep->DR_LAST_REGNUM)
3208 || (reg_nr >= tdep->FPP0_REGNUM
3209 && reg_nr <= tdep->FPP_LAST_REGNUM)
3210 || (reg_nr >= tdep->DR0_C_REGNUM
3211 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3212 || (reg_nr <= tdep->TR7_REGNUM))
3213 return 8;
3214
3215 else if ((reg_nr >= tdep->FV0_REGNUM
3216 && reg_nr <= tdep->FV_LAST_REGNUM)
3217 || (reg_nr >= tdep->FV0_C_REGNUM
3218 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3219 return 16;
3220
3221 else /* this covers also the 32-bit SH compact registers. */
3222 return 4;
3223 }
3224
3225 /* ??????? FIXME */
3226 static int
3227 sh_sh64_register_virtual_size (int reg_nr)
3228 {
3229 if (reg_nr >= FP0_REGNUM
3230 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3231 return 4;
3232 else
3233 return 8;
3234 }
3235
3236 /* Return the GDB type object for the "standard" data type
3237 of data in register N. */
3238 static struct type *
3239 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
3240 {
3241 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3242
3243 if ((reg_nr >= FP0_REGNUM
3244 && (reg_nr <= tdep->FP_LAST_REGNUM))
3245 || (reg_nr == tdep->FPUL_REGNUM))
3246 return builtin_type_float;
3247 else
3248 return builtin_type_int;
3249 }
3250
3251 static struct type *
3252 sh_sh4_build_float_register_type (int high)
3253 {
3254 struct type *temp;
3255
3256 temp = create_range_type (NULL, builtin_type_int, 0, high);
3257 return create_array_type (NULL, builtin_type_float, temp);
3258 }
3259
3260 static struct type *
3261 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
3262 {
3263 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3264
3265 if ((reg_nr >= FP0_REGNUM
3266 && (reg_nr <= tdep->FP_LAST_REGNUM))
3267 || (reg_nr == tdep->FPUL_REGNUM))
3268 return builtin_type_float;
3269 else if (reg_nr >= tdep->DR0_REGNUM
3270 && reg_nr <= tdep->DR_LAST_REGNUM)
3271 return builtin_type_double;
3272 else if (reg_nr >= tdep->FV0_REGNUM
3273 && reg_nr <= tdep->FV_LAST_REGNUM)
3274 return sh_sh4_build_float_register_type (3);
3275 else
3276 return builtin_type_int;
3277 }
3278
3279 static struct type *
3280 sh_sh64_register_virtual_type (int reg_nr)
3281 {
3282 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3283
3284 if ((reg_nr >= FP0_REGNUM
3285 && reg_nr <= tdep->FP_LAST_REGNUM)
3286 || (reg_nr >= tdep->FP0_C_REGNUM
3287 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3288 return builtin_type_float;
3289 else if ((reg_nr >= tdep->DR0_REGNUM
3290 && reg_nr <= tdep->DR_LAST_REGNUM)
3291 || (reg_nr >= tdep->DR0_C_REGNUM
3292 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3293 return builtin_type_double;
3294 else if (reg_nr >= tdep->FPP0_REGNUM
3295 && reg_nr <= tdep->FPP_LAST_REGNUM)
3296 return sh_sh4_build_float_register_type (1);
3297 else if ((reg_nr >= tdep->FV0_REGNUM
3298 && reg_nr <= tdep->FV_LAST_REGNUM)
3299 ||(reg_nr >= tdep->FV0_C_REGNUM
3300 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3301 return sh_sh4_build_float_register_type (3);
3302 else if (reg_nr == tdep->FPSCR_REGNUM)
3303 return builtin_type_int;
3304 else if (reg_nr >= tdep->R0_C_REGNUM
3305 && reg_nr < tdep->FP0_C_REGNUM)
3306 return builtin_type_int;
3307 else
3308 return builtin_type_long_long;
3309 }
3310
3311 static struct type *
3312 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
3313 {
3314 return builtin_type_int;
3315 }
3316
3317 /* On the sh4, the DRi pseudo registers are problematic if the target
3318 is little endian. When the user writes one of those registers, for
3319 instance with 'ser var $dr0=1', we want the double to be stored
3320 like this:
3321 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3322 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3323
3324 This corresponds to little endian byte order & big endian word
3325 order. However if we let gdb write the register w/o conversion, it
3326 will write fr0 and fr1 this way:
3327 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3328 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3329 because it will consider fr0 and fr1 as a single LE stretch of memory.
3330
3331 To achieve what we want we must force gdb to store things in
3332 floatformat_ieee_double_littlebyte_bigword (which is defined in
3333 include/floatformat.h and libiberty/floatformat.c.
3334
3335 In case the target is big endian, there is no problem, the
3336 raw bytes will look like:
3337 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3338 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3339
3340 The other pseudo registers (the FVs) also don't pose a problem
3341 because they are stored as 4 individual FP elements. */
3342
3343 static void
3344 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3345 char *from, char *to)
3346 {
3347 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3348
3349 if (regnum >= tdep->DR0_REGNUM
3350 && regnum <= tdep->DR_LAST_REGNUM)
3351 {
3352 DOUBLEST val;
3353 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3354 store_typed_floating (to, type, val);
3355 }
3356 else
3357 error ("sh_register_convert_to_virtual called with non DR register number");
3358 }
3359
3360 static void
3361 sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3362 char *from, char *to)
3363 {
3364 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3365
3366 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3367 {
3368 /* It is a no-op. */
3369 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3370 return;
3371 }
3372
3373 if ((regnum >= tdep->DR0_REGNUM
3374 && regnum <= tdep->DR_LAST_REGNUM)
3375 || (regnum >= tdep->DR0_C_REGNUM
3376 && regnum <= tdep->DR_LAST_C_REGNUM))
3377 {
3378 DOUBLEST val;
3379 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3380 deprecated_store_floating(to, TYPE_LENGTH(type), val);
3381 }
3382 else
3383 error("sh_register_convert_to_virtual called with non DR register number");
3384 }
3385
3386 static void
3387 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
3388 const void *from, void *to)
3389 {
3390 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3391
3392 if (regnum >= tdep->DR0_REGNUM
3393 && regnum <= tdep->DR_LAST_REGNUM)
3394 {
3395 DOUBLEST val = extract_typed_floating (from, type);
3396 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3397 }
3398 else
3399 error("sh_register_convert_to_raw called with non DR register number");
3400 }
3401
3402 static void
3403 sh_sh64_register_convert_to_raw (struct type *type, int regnum,
3404 const void *from, void *to)
3405 {
3406 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3407
3408 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3409 {
3410 /* It is a no-op. */
3411 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3412 return;
3413 }
3414
3415 if ((regnum >= tdep->DR0_REGNUM
3416 && regnum <= tdep->DR_LAST_REGNUM)
3417 || (regnum >= tdep->DR0_C_REGNUM
3418 && regnum <= tdep->DR_LAST_C_REGNUM))
3419 {
3420 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
3421 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3422 }
3423 else
3424 error("sh_register_convert_to_raw called with non DR register number");
3425 }
3426
3427 static void
3428 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3429 int reg_nr, void *buffer)
3430 {
3431 int base_regnum, portion;
3432 char temp_buffer[MAX_REGISTER_SIZE];
3433 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3434
3435 if (reg_nr >= tdep->DR0_REGNUM
3436 && reg_nr <= tdep->DR_LAST_REGNUM)
3437 {
3438 base_regnum = dr_reg_base_num (reg_nr);
3439
3440 /* Build the value in the provided buffer. */
3441 /* Read the real regs for which this one is an alias. */
3442 for (portion = 0; portion < 2; portion++)
3443 regcache_raw_read (regcache, base_regnum + portion,
3444 (temp_buffer
3445 + register_size (gdbarch, base_regnum) * portion));
3446 /* We must pay attention to the endiannes. */
3447 sh_sh4_register_convert_to_virtual (reg_nr,
3448 gdbarch_register_type (gdbarch, reg_nr),
3449 temp_buffer, buffer);
3450 }
3451 else if (reg_nr >= tdep->FV0_REGNUM
3452 && reg_nr <= tdep->FV_LAST_REGNUM)
3453 {
3454 base_regnum = fv_reg_base_num (reg_nr);
3455
3456 /* Read the real regs for which this one is an alias. */
3457 for (portion = 0; portion < 4; portion++)
3458 regcache_raw_read (regcache, base_regnum + portion,
3459 ((char *) buffer
3460 + register_size (gdbarch, base_regnum) * portion));
3461 }
3462 }
3463
3464 static void
3465 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3466 int reg_nr, void *buffer)
3467 {
3468 int base_regnum;
3469 int portion;
3470 int offset = 0;
3471 char temp_buffer[MAX_REGISTER_SIZE];
3472 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3473
3474 if (reg_nr >= tdep->DR0_REGNUM
3475 && reg_nr <= tdep->DR_LAST_REGNUM)
3476 {
3477 base_regnum = dr_reg_base_num (reg_nr);
3478
3479 /* Build the value in the provided buffer. */
3480 /* DR regs are double precision registers obtained by
3481 concatenating 2 single precision floating point registers. */
3482 for (portion = 0; portion < 2; portion++)
3483 regcache_raw_read (regcache, base_regnum + portion,
3484 (temp_buffer
3485 + REGISTER_RAW_SIZE (base_regnum) * portion));
3486
3487 /* We must pay attention to the endiannes. */
3488 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3489 temp_buffer, buffer);
3490
3491 }
3492
3493 else if (reg_nr >= tdep->FPP0_REGNUM
3494 && reg_nr <= tdep->FPP_LAST_REGNUM)
3495 {
3496 base_regnum = fpp_reg_base_num (reg_nr);
3497
3498 /* Build the value in the provided buffer. */
3499 /* FPP regs are pairs of single precision registers obtained by
3500 concatenating 2 single precision floating point registers. */
3501 for (portion = 0; portion < 2; portion++)
3502 regcache_raw_read (regcache, base_regnum + portion,
3503 ((char *) buffer
3504 + REGISTER_RAW_SIZE (base_regnum) * portion));
3505 }
3506
3507 else if (reg_nr >= tdep->FV0_REGNUM
3508 && reg_nr <= tdep->FV_LAST_REGNUM)
3509 {
3510 base_regnum = fv_reg_base_num (reg_nr);
3511
3512 /* Build the value in the provided buffer. */
3513 /* FV regs are vectors of single precision registers obtained by
3514 concatenating 4 single precision floating point registers. */
3515 for (portion = 0; portion < 4; portion++)
3516 regcache_raw_read (regcache, base_regnum + portion,
3517 ((char *) buffer
3518 + REGISTER_RAW_SIZE (base_regnum) * portion));
3519 }
3520
3521 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3522 else if (reg_nr >= tdep->R0_C_REGNUM
3523 && reg_nr <= tdep->T_C_REGNUM)
3524 {
3525 base_regnum = sh64_compact_reg_base_num (reg_nr);
3526
3527 /* Build the value in the provided buffer. */
3528 regcache_raw_read (regcache, base_regnum, temp_buffer);
3529 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3530 offset = 4;
3531 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3532 }
3533
3534 else if (reg_nr >= tdep->FP0_C_REGNUM
3535 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3536 {
3537 base_regnum = sh64_compact_reg_base_num (reg_nr);
3538
3539 /* Build the value in the provided buffer. */
3540 /* Floating point registers map 1-1 to the media fp regs,
3541 they have the same size and endienness. */
3542 regcache_raw_read (regcache, base_regnum, buffer);
3543 }
3544
3545 else if (reg_nr >= tdep->DR0_C_REGNUM
3546 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3547 {
3548 base_regnum = sh64_compact_reg_base_num (reg_nr);
3549
3550 /* DR_C regs are double precision registers obtained by
3551 concatenating 2 single precision floating point registers. */
3552 for (portion = 0; portion < 2; portion++)
3553 regcache_raw_read (regcache, base_regnum + portion,
3554 (temp_buffer
3555 + REGISTER_RAW_SIZE (base_regnum) * portion));
3556
3557 /* We must pay attention to the endiannes. */
3558 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3559 temp_buffer, buffer);
3560 }
3561
3562 else if (reg_nr >= tdep->FV0_C_REGNUM
3563 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3564 {
3565 base_regnum = sh64_compact_reg_base_num (reg_nr);
3566
3567 /* Build the value in the provided buffer. */
3568 /* FV_C regs are vectors of single precision registers obtained by
3569 concatenating 4 single precision floating point registers. */
3570 for (portion = 0; portion < 4; portion++)
3571 regcache_raw_read (regcache, base_regnum + portion,
3572 ((char *) buffer
3573 + REGISTER_RAW_SIZE (base_regnum) * portion));
3574 }
3575
3576 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3577 {
3578 int fpscr_base_regnum;
3579 int sr_base_regnum;
3580 unsigned int fpscr_value;
3581 unsigned int sr_value;
3582 unsigned int fpscr_c_value;
3583 unsigned int fpscr_c_part1_value;
3584 unsigned int fpscr_c_part2_value;
3585
3586 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3587 sr_base_regnum = tdep->SR_REGNUM;
3588
3589 /* Build the value in the provided buffer. */
3590 /* FPSCR_C is a very weird register that contains sparse bits
3591 from the FPSCR and the SR architectural registers.
3592 Specifically: */
3593 /* *INDENT-OFF* */
3594 /*
3595 FPSRC_C bit
3596 0 Bit 0 of FPSCR
3597 1 reserved
3598 2-17 Bit 2-18 of FPSCR
3599 18-20 Bits 12,13,14 of SR
3600 21-31 reserved
3601 */
3602 /* *INDENT-ON* */
3603 /* Get FPSCR into a local buffer */
3604 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3605 /* Get value as an int. */
3606 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3607 /* Get SR into a local buffer */
3608 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3609 /* Get value as an int. */
3610 sr_value = extract_unsigned_integer (temp_buffer, 4);
3611 /* Build the new value. */
3612 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3613 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3614 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3615 /* Store that in out buffer!!! */
3616 store_unsigned_integer (buffer, 4, fpscr_c_value);
3617 /* FIXME There is surely an endianness gotcha here. */
3618 }
3619
3620 else if (reg_nr == tdep->FPUL_C_REGNUM)
3621 {
3622 base_regnum = sh64_compact_reg_base_num (reg_nr);
3623
3624 /* FPUL_C register is floating point register 32,
3625 same size, same endianness. */
3626 regcache_raw_read (regcache, base_regnum, buffer);
3627 }
3628 }
3629
3630 static void
3631 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3632 int reg_nr, const void *buffer)
3633 {
3634 int base_regnum, portion;
3635 char temp_buffer[MAX_REGISTER_SIZE];
3636 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3637
3638 if (reg_nr >= tdep->DR0_REGNUM
3639 && reg_nr <= tdep->DR_LAST_REGNUM)
3640 {
3641 base_regnum = dr_reg_base_num (reg_nr);
3642
3643 /* We must pay attention to the endiannes. */
3644 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr,
3645 buffer, temp_buffer);
3646
3647 /* Write the real regs for which this one is an alias. */
3648 for (portion = 0; portion < 2; portion++)
3649 regcache_raw_write (regcache, base_regnum + portion,
3650 (temp_buffer
3651 + register_size (gdbarch, base_regnum) * portion));
3652 }
3653 else if (reg_nr >= tdep->FV0_REGNUM
3654 && reg_nr <= tdep->FV_LAST_REGNUM)
3655 {
3656 base_regnum = fv_reg_base_num (reg_nr);
3657
3658 /* Write the real regs for which this one is an alias. */
3659 for (portion = 0; portion < 4; portion++)
3660 regcache_raw_write (regcache, base_regnum + portion,
3661 ((char *) buffer
3662 + register_size (gdbarch, base_regnum) * portion));
3663 }
3664 }
3665
3666 static void
3667 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3668 int reg_nr, const void *buffer)
3669 {
3670 int base_regnum, portion;
3671 int offset;
3672 char temp_buffer[MAX_REGISTER_SIZE];
3673 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3674
3675 if (reg_nr >= tdep->DR0_REGNUM
3676 && reg_nr <= tdep->DR_LAST_REGNUM)
3677 {
3678 base_regnum = dr_reg_base_num (reg_nr);
3679 /* We must pay attention to the endiannes. */
3680 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3681 buffer, temp_buffer);
3682
3683
3684 /* Write the real regs for which this one is an alias. */
3685 for (portion = 0; portion < 2; portion++)
3686 regcache_raw_write (regcache, base_regnum + portion,
3687 (temp_buffer
3688 + REGISTER_RAW_SIZE (base_regnum) * portion));
3689 }
3690
3691 else if (reg_nr >= tdep->FPP0_REGNUM
3692 && reg_nr <= tdep->FPP_LAST_REGNUM)
3693 {
3694 base_regnum = fpp_reg_base_num (reg_nr);
3695
3696 /* Write the real regs for which this one is an alias. */
3697 for (portion = 0; portion < 2; portion++)
3698 regcache_raw_write (regcache, base_regnum + portion,
3699 ((char *) buffer
3700 + REGISTER_RAW_SIZE (base_regnum) * portion));
3701 }
3702
3703 else if (reg_nr >= tdep->FV0_REGNUM
3704 && reg_nr <= tdep->FV_LAST_REGNUM)
3705 {
3706 base_regnum = fv_reg_base_num (reg_nr);
3707
3708 /* Write the real regs for which this one is an alias. */
3709 for (portion = 0; portion < 4; portion++)
3710 regcache_raw_write (regcache, base_regnum + portion,
3711 ((char *) buffer
3712 + REGISTER_RAW_SIZE (base_regnum) * portion));
3713 }
3714
3715 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3716 register but only 4 bytes of it. */
3717 else if (reg_nr >= tdep->R0_C_REGNUM
3718 && reg_nr <= tdep->T_C_REGNUM)
3719 {
3720 base_regnum = sh64_compact_reg_base_num (reg_nr);
3721 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3722 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3723 offset = 4;
3724 else
3725 offset = 0;
3726 /* Let's read the value of the base register into a temporary
3727 buffer, so that overwriting the last four bytes with the new
3728 value of the pseudo will leave the upper 4 bytes unchanged. */
3729 regcache_raw_read (regcache, base_regnum, temp_buffer);
3730 /* Write as an 8 byte quantity */
3731 memcpy (temp_buffer + offset, buffer, 4);
3732 regcache_raw_write (regcache, base_regnum, temp_buffer);
3733 }
3734
3735 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3736 registers. Both are 4 bytes. */
3737 else if (reg_nr >= tdep->FP0_C_REGNUM
3738 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3739 {
3740 base_regnum = sh64_compact_reg_base_num (reg_nr);
3741 regcache_raw_write (regcache, base_regnum, buffer);
3742 }
3743
3744 else if (reg_nr >= tdep->DR0_C_REGNUM
3745 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3746 {
3747 base_regnum = sh64_compact_reg_base_num (reg_nr);
3748 for (portion = 0; portion < 2; portion++)
3749 {
3750 /* We must pay attention to the endiannes. */
3751 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3752 buffer, temp_buffer);
3753
3754 regcache_raw_write (regcache, base_regnum + portion,
3755 (temp_buffer
3756 + REGISTER_RAW_SIZE (base_regnum) * portion));
3757 }
3758 }
3759
3760 else if (reg_nr >= tdep->FV0_C_REGNUM
3761 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3762 {
3763 base_regnum = sh64_compact_reg_base_num (reg_nr);
3764
3765 for (portion = 0; portion < 4; portion++)
3766 {
3767 regcache_raw_write (regcache, base_regnum + portion,
3768 ((char *) buffer
3769 + REGISTER_RAW_SIZE (base_regnum) * portion));
3770 }
3771 }
3772
3773 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3774 {
3775 int fpscr_base_regnum;
3776 int sr_base_regnum;
3777 unsigned int fpscr_value;
3778 unsigned int sr_value;
3779 unsigned int old_fpscr_value;
3780 unsigned int old_sr_value;
3781 unsigned int fpscr_c_value;
3782 unsigned int fpscr_mask;
3783 unsigned int sr_mask;
3784
3785 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3786 sr_base_regnum = tdep->SR_REGNUM;
3787
3788 /* FPSCR_C is a very weird register that contains sparse bits
3789 from the FPSCR and the SR architectural registers.
3790 Specifically: */
3791 /* *INDENT-OFF* */
3792 /*
3793 FPSRC_C bit
3794 0 Bit 0 of FPSCR
3795 1 reserved
3796 2-17 Bit 2-18 of FPSCR
3797 18-20 Bits 12,13,14 of SR
3798 21-31 reserved
3799 */
3800 /* *INDENT-ON* */
3801 /* Get value as an int. */
3802 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3803
3804 /* Build the new values. */
3805 fpscr_mask = 0x0003fffd;
3806 sr_mask = 0x001c0000;
3807
3808 fpscr_value = fpscr_c_value & fpscr_mask;
3809 sr_value = (fpscr_value & sr_mask) >> 6;
3810
3811 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3812 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3813 old_fpscr_value &= 0xfffc0002;
3814 fpscr_value |= old_fpscr_value;
3815 store_unsigned_integer (temp_buffer, 4, fpscr_value);
3816 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
3817
3818 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3819 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3820 old_sr_value &= 0xffff8fff;
3821 sr_value |= old_sr_value;
3822 store_unsigned_integer (temp_buffer, 4, sr_value);
3823 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
3824 }
3825
3826 else if (reg_nr == tdep->FPUL_C_REGNUM)
3827 {
3828 base_regnum = sh64_compact_reg_base_num (reg_nr);
3829 regcache_raw_write (regcache, base_regnum, buffer);
3830 }
3831 }
3832
3833 /* Floating point vector of 4 float registers. */
3834 static void
3835 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
3836 int fv_regnum)
3837 {
3838 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3839 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3840 fv_regnum - gdbarch_tdep (gdbarch)->FV0_REGNUM,
3841 (int) read_register (first_fp_reg_num),
3842 (int) read_register (first_fp_reg_num + 1),
3843 (int) read_register (first_fp_reg_num + 2),
3844 (int) read_register (first_fp_reg_num + 3));
3845 }
3846
3847 /* Floating point vector of 4 float registers, compact mode. */
3848 static void
3849 do_fv_c_register_info (int fv_regnum)
3850 {
3851 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3852 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3853 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3854 (int) read_register (first_fp_reg_num),
3855 (int) read_register (first_fp_reg_num + 1),
3856 (int) read_register (first_fp_reg_num + 2),
3857 (int) read_register (first_fp_reg_num + 3));
3858 }
3859
3860 /* Pairs of single regs. The DR are instead double precision
3861 registers. */
3862 static void
3863 do_fpp_register_info (int fpp_regnum)
3864 {
3865 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3866
3867 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3868 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3869 (int) read_register (first_fp_reg_num),
3870 (int) read_register (first_fp_reg_num + 1));
3871 }
3872
3873 /* Double precision registers. */
3874 static void
3875 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
3876 int dr_regnum)
3877 {
3878 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3879
3880 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
3881 dr_regnum - gdbarch_tdep (gdbarch)->DR0_REGNUM,
3882 (int) read_register (first_fp_reg_num),
3883 (int) read_register (first_fp_reg_num + 1));
3884 }
3885
3886 /* Double precision registers, compact mode. */
3887 static void
3888 do_dr_c_register_info (int dr_regnum)
3889 {
3890 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3891
3892 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3893 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3894 (int) read_register (first_fp_reg_num),
3895 (int) read_register (first_fp_reg_num +1));
3896 }
3897
3898 /* General register in compact mode. */
3899 static void
3900 do_r_c_register_info (int r_c_regnum)
3901 {
3902 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3903
3904 printf_filtered ("r%d_c\t0x%08x\n",
3905 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3906 /*FIXME!!!*/ (int) read_register (regnum));
3907 }
3908
3909 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3910 shmedia REGISTERS. */
3911 /* Control registers, compact mode. */
3912 static void
3913 do_cr_c_register_info (int cr_c_regnum)
3914 {
3915 switch (cr_c_regnum)
3916 {
3917 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3918 break;
3919 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3920 break;
3921 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3922 break;
3923 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3924 break;
3925 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3926 break;
3927 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3928 break;
3929 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3930 break;
3931 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3932 break;
3933 }
3934 }
3935
3936 static void
3937 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
3938 int regnum)
3939 {
3940 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3941
3942 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
3943 internal_error (__FILE__, __LINE__,
3944 "Invalid pseudo register number %d\n", regnum);
3945 else if (regnum >= tdep->DR0_REGNUM
3946 && regnum <= tdep->DR_LAST_REGNUM)
3947 do_dr_register_info (gdbarch, file, regnum);
3948 else if (regnum >= tdep->FV0_REGNUM
3949 && regnum <= tdep->FV_LAST_REGNUM)
3950 do_fv_register_info (gdbarch, file, regnum);
3951 }
3952
3953 static void
3954 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
3955 { /* do values for FP (float) regs */
3956 char *raw_buffer;
3957 double flt; /* double extracted from raw hex data */
3958 int inv;
3959 int j;
3960
3961 /* Allocate space for the float. */
3962 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
3963
3964 /* Get the data in raw format. */
3965 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
3966 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3967
3968 /* Get the register as a number */
3969 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3970
3971 /* Print the name and some spaces. */
3972 fputs_filtered (REGISTER_NAME (regnum), file);
3973 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
3974
3975 /* Print the value. */
3976 if (inv)
3977 fprintf_filtered (file, "<invalid float>");
3978 else
3979 fprintf_filtered (file, "%-10.9g", flt);
3980
3981 /* Print the fp register as hex. */
3982 fprintf_filtered (file, "\t(raw 0x");
3983 for (j = 0; j < register_size (gdbarch, regnum); j++)
3984 {
3985 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
3986 : register_size (gdbarch, regnum) - 1 - j;
3987 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
3988 }
3989 fprintf_filtered (file, ")");
3990 fprintf_filtered (file, "\n");
3991 }
3992
3993 static void
3994 sh64_do_pseudo_register (int regnum)
3995 {
3996 /* All the sh64-compact mode registers are pseudo registers. */
3997 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3998
3999 if (regnum < NUM_REGS
4000 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
4001 internal_error (__FILE__, __LINE__,
4002 "Invalid pseudo register number %d\n", regnum);
4003
4004 else if ((regnum >= tdep->DR0_REGNUM
4005 && regnum <= tdep->DR_LAST_REGNUM))
4006 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
4007
4008 else if ((regnum >= tdep->DR0_C_REGNUM
4009 && regnum <= tdep->DR_LAST_C_REGNUM))
4010 do_dr_c_register_info (regnum);
4011
4012 else if ((regnum >= tdep->FV0_REGNUM
4013 && regnum <= tdep->FV_LAST_REGNUM))
4014 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
4015
4016 else if ((regnum >= tdep->FV0_C_REGNUM
4017 && regnum <= tdep->FV_LAST_C_REGNUM))
4018 do_fv_c_register_info (regnum);
4019
4020 else if (regnum >= tdep->FPP0_REGNUM
4021 && regnum <= tdep->FPP_LAST_REGNUM)
4022 do_fpp_register_info (regnum);
4023
4024 else if (regnum >= tdep->R0_C_REGNUM
4025 && regnum <= tdep->R_LAST_C_REGNUM)
4026 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
4027
4028 else if (regnum >= tdep->FP0_C_REGNUM
4029 && regnum <= tdep->FP_LAST_C_REGNUM)
4030 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum); /* this should work also for pseudoregs */
4031
4032 else if (regnum >= tdep->PC_C_REGNUM
4033 && regnum <= tdep->FPUL_C_REGNUM)
4034 do_cr_c_register_info (regnum);
4035
4036 }
4037
4038 static void
4039 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
4040 {
4041 char raw_buffer[MAX_REGISTER_SIZE];
4042
4043 fputs_filtered (REGISTER_NAME (regnum), file);
4044 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
4045
4046 /* Get the data in raw format. */
4047 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
4048 fprintf_filtered (file, "*value not available*\n");
4049
4050 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
4051 file, 'x', 1, 0, Val_pretty_default);
4052 fprintf_filtered (file, "\t");
4053 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
4054 file, 0, 1, 0, Val_pretty_default);
4055 fprintf_filtered (file, "\n");
4056 }
4057
4058 static void
4059 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
4060 {
4061 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
4062 internal_error (__FILE__, __LINE__,
4063 "Invalid register number %d\n", regnum);
4064
4065 else if (regnum >= 0 && regnum < NUM_REGS)
4066 {
4067 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4068 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
4069 else
4070 sh_do_register (gdbarch, file, regnum); /* All other regs */
4071 }
4072
4073 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4074 {
4075 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh5)
4076 sh64_do_pseudo_register (regnum);
4077 else
4078 sh_print_pseudo_register (gdbarch, file, regnum);
4079 }
4080 }
4081
4082 static void
4083 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4084 struct frame_info *frame, int regnum, int fpregs)
4085 {
4086 if (regnum != -1) /* do one specified register */
4087 {
4088 if (*(REGISTER_NAME (regnum)) == '\0')
4089 error ("Not a valid register for the current processor type");
4090
4091 sh_print_register (gdbarch, file, regnum);
4092 }
4093 else
4094 /* do all (or most) registers */
4095 {
4096 regnum = 0;
4097 while (regnum < NUM_REGS)
4098 {
4099 /* If the register name is empty, it is undefined for this
4100 processor, so don't display anything. */
4101 if (REGISTER_NAME (regnum) == NULL
4102 || *(REGISTER_NAME (regnum)) == '\0')
4103 {
4104 regnum++;
4105 continue;
4106 }
4107
4108 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4109 {
4110 if (fpregs)
4111 {
4112 /* true for "INFO ALL-REGISTERS" command */
4113 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
4114 regnum ++;
4115 }
4116 else
4117 regnum += (gdbarch_tdep (gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
4118 }
4119 else
4120 {
4121 sh_do_register (gdbarch, file, regnum); /* All other regs */
4122 regnum++;
4123 }
4124 }
4125
4126 if (fpregs)
4127 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4128 {
4129 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh5)
4130 sh64_do_pseudo_register (regnum);
4131 else
4132 sh_print_pseudo_register (gdbarch, file, regnum);
4133 regnum++;
4134 }
4135 }
4136 }
4137
4138 static void
4139 sh_compact_do_registers_info (int regnum, int fpregs)
4140 {
4141 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4142 if (regnum != -1) /* do one specified register */
4143 {
4144 if (*(REGISTER_NAME (regnum)) == '\0')
4145 error ("Not a valid register for the current processor type");
4146
4147 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4148 error ("Not a valid register for the current processor mode.");
4149
4150 sh_print_register (current_gdbarch, gdb_stdout, regnum);
4151 }
4152 else
4153 /* do all compact registers */
4154 {
4155 regnum = tdep->R0_C_REGNUM;
4156 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4157 {
4158 sh64_do_pseudo_register (regnum);
4159 regnum++;
4160 }
4161 }
4162 }
4163
4164 static void
4165 sh64_do_registers_info (int regnum, int fpregs)
4166 {
4167 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
4168 sh_print_registers_info (current_gdbarch, gdb_stdout,
4169 deprecated_selected_frame, regnum, fpregs);
4170 else
4171 sh_compact_do_registers_info (regnum, fpregs);
4172 }
4173
4174 #ifdef SVR4_SHARED_LIBS
4175
4176 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4177 for native i386 linux targets using the struct offsets defined in
4178 link.h (but without actual reference to that file).
4179
4180 This makes it possible to access i386-linux shared libraries from
4181 a gdb that was not built on an i386-linux host (for cross debugging).
4182 */
4183
4184 struct link_map_offsets *
4185 sh_linux_svr4_fetch_link_map_offsets (void)
4186 {
4187 static struct link_map_offsets lmo;
4188 static struct link_map_offsets *lmp = 0;
4189
4190 if (lmp == 0)
4191 {
4192 lmp = &lmo;
4193
4194 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4195
4196 lmo.r_map_offset = 4;
4197 lmo.r_map_size = 4;
4198
4199 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4200
4201 lmo.l_addr_offset = 0;
4202 lmo.l_addr_size = 4;
4203
4204 lmo.l_name_offset = 4;
4205 lmo.l_name_size = 4;
4206
4207 lmo.l_next_offset = 12;
4208 lmo.l_next_size = 4;
4209
4210 lmo.l_prev_offset = 16;
4211 lmo.l_prev_size = 4;
4212 }
4213
4214 return lmp;
4215 }
4216 #endif /* SVR4_SHARED_LIBS */
4217
4218 \f
4219 enum
4220 {
4221 DSP_DSR_REGNUM = 24,
4222 DSP_A0G_REGNUM,
4223 DSP_A0_REGNUM,
4224 DSP_A1G_REGNUM,
4225 DSP_A1_REGNUM,
4226 DSP_M0_REGNUM,
4227 DSP_M1_REGNUM,
4228 DSP_X0_REGNUM,
4229 DSP_X1_REGNUM,
4230 DSP_Y0_REGNUM,
4231 DSP_Y1_REGNUM,
4232
4233 DSP_MOD_REGNUM = 40,
4234
4235 DSP_RS_REGNUM = 43,
4236 DSP_RE_REGNUM,
4237
4238 DSP_R0_BANK_REGNUM = 51,
4239 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4240 };
4241
4242 static int
4243 sh_dsp_register_sim_regno (int nr)
4244 {
4245 if (legacy_register_sim_regno (nr) < 0)
4246 return legacy_register_sim_regno (nr);
4247 if (nr >= DSP_DSR_REGNUM && nr <= DSP_Y1_REGNUM)
4248 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4249 if (nr == DSP_MOD_REGNUM)
4250 return SIM_SH_MOD_REGNUM;
4251 if (nr == DSP_RS_REGNUM)
4252 return SIM_SH_RS_REGNUM;
4253 if (nr == DSP_RE_REGNUM)
4254 return SIM_SH_RE_REGNUM;
4255 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4256 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4257 return nr;
4258 }
4259 \f
4260 static gdbarch_init_ftype sh_gdbarch_init;
4261
4262 static struct gdbarch *
4263 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4264 {
4265 static LONGEST sh64_call_dummy_words[] = {0};
4266 struct gdbarch *gdbarch;
4267 struct gdbarch_tdep *tdep;
4268
4269 /* If there is already a candidate, use it. */
4270 arches = gdbarch_list_lookup_by_info (arches, &info);
4271 if (arches != NULL)
4272 return arches->gdbarch;
4273
4274 /* None found, create a new architecture from the information
4275 provided. */
4276 tdep = XMALLOC (struct gdbarch_tdep);
4277 gdbarch = gdbarch_alloc (&info, tdep);
4278
4279 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
4280 ready to unwind the PC first (see frame.c:get_prev_frame()). */
4281 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
4282
4283 /* Initialize the register numbers that are not common to all the
4284 variants to -1, if necessary thse will be overwritten in the case
4285 statement below. */
4286 tdep->FPUL_REGNUM = -1;
4287 tdep->FPSCR_REGNUM = -1;
4288 tdep->PR_REGNUM = 17;
4289 tdep->SR_REGNUM = 22;
4290 tdep->DSR_REGNUM = -1;
4291 tdep->FP_LAST_REGNUM = -1;
4292 tdep->A0G_REGNUM = -1;
4293 tdep->A0_REGNUM = -1;
4294 tdep->A1G_REGNUM = -1;
4295 tdep->A1_REGNUM = -1;
4296 tdep->M0_REGNUM = -1;
4297 tdep->M1_REGNUM = -1;
4298 tdep->X0_REGNUM = -1;
4299 tdep->X1_REGNUM = -1;
4300 tdep->Y0_REGNUM = -1;
4301 tdep->Y1_REGNUM = -1;
4302 tdep->MOD_REGNUM = -1;
4303 tdep->RS_REGNUM = -1;
4304 tdep->RE_REGNUM = -1;
4305 tdep->SSR_REGNUM = -1;
4306 tdep->SPC_REGNUM = -1;
4307 tdep->DR0_REGNUM = -1;
4308 tdep->DR_LAST_REGNUM = -1;
4309 tdep->FV0_REGNUM = -1;
4310 tdep->FV_LAST_REGNUM = -1;
4311 tdep->ARG0_REGNUM = 4;
4312 tdep->ARGLAST_REGNUM = 7;
4313 tdep->RETURN_REGNUM = 0;
4314 tdep->FLOAT_ARGLAST_REGNUM = -1;
4315
4316 tdep->sh_abi = SH_ABI_UNKNOWN;
4317
4318 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4319 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4320 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4321 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4322 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4323 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4324 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4325 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4326
4327 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
4328 set_gdbarch_sp_regnum (gdbarch, 15);
4329 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
4330 set_gdbarch_pc_regnum (gdbarch, 16);
4331 set_gdbarch_fp0_regnum (gdbarch, -1);
4332 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4333
4334 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
4335 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
4336
4337 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
4338 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
4339
4340 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4341
4342 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4343 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4344 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4345 set_gdbarch_function_start_offset (gdbarch, 0);
4346
4347 set_gdbarch_frame_args_skip (gdbarch, 0);
4348 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
4349 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4350
4351 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4352
4353 set_gdbarch_deprecated_frame_chain (gdbarch, sh_frame_chain);
4354 set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
4355 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
4356 set_gdbarch_deprecated_pop_frame (gdbarch, sh_pop_frame);
4357 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
4358 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4359
4360 switch (info.bfd_arch_info->mach)
4361 {
4362 case bfd_mach_sh:
4363 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
4364 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4365 sh_show_regs = sh_generic_show_regs;
4366 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4367 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4368 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4369 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4370 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4371 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4372
4373 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4374 break;
4375 case bfd_mach_sh2:
4376 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
4377 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4378 sh_show_regs = sh_generic_show_regs;
4379 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4380 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4381 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4382 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4383 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4384 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4385
4386 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4387 break;
4388 case bfd_mach_sh2e:
4389 /* doubles on sh2e and sh3e are actually 4 byte. */
4390 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4391
4392 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
4393 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4394 sh_show_regs = sh2e_show_regs;
4395 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
4396 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4397 set_gdbarch_fp0_regnum (gdbarch, 25);
4398 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
4399 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4400 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4401 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4402 tdep->FPUL_REGNUM = 23;
4403 tdep->FPSCR_REGNUM = 24;
4404 tdep->FP_LAST_REGNUM = 40;
4405
4406 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4407 break;
4408 case bfd_mach_sh_dsp:
4409 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
4410 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4411 sh_show_regs = sh_dsp_show_regs;
4412 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4413 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4414 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4415 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4416 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4417 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4418 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4419 tdep->DSR_REGNUM = 24;
4420 tdep->A0G_REGNUM = 25;
4421 tdep->A0_REGNUM = 26;
4422 tdep->A1G_REGNUM = 27;
4423 tdep->A1_REGNUM = 28;
4424 tdep->M0_REGNUM = 29;
4425 tdep->M1_REGNUM = 30;
4426 tdep->X0_REGNUM = 31;
4427 tdep->X1_REGNUM = 32;
4428 tdep->Y0_REGNUM = 33;
4429 tdep->Y1_REGNUM = 34;
4430 tdep->MOD_REGNUM = 40;
4431 tdep->RS_REGNUM = 43;
4432 tdep->RE_REGNUM = 44;
4433
4434 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4435 break;
4436 case bfd_mach_sh3:
4437 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
4438 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4439 sh_show_regs = sh3_show_regs;
4440 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4441 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4442 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4443 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4444 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4445 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4446 tdep->SSR_REGNUM = 41;
4447 tdep->SPC_REGNUM = 42;
4448
4449 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4450 break;
4451 case bfd_mach_sh3e:
4452 /* doubles on sh2e and sh3e are actually 4 byte. */
4453 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4454
4455 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
4456 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4457 sh_show_regs = sh3e_show_regs;
4458 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
4459 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4460 set_gdbarch_fp0_regnum (gdbarch, 25);
4461 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
4462 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4463 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4464 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4465 tdep->FPUL_REGNUM = 23;
4466 tdep->FPSCR_REGNUM = 24;
4467 tdep->FP_LAST_REGNUM = 40;
4468 tdep->SSR_REGNUM = 41;
4469 tdep->SPC_REGNUM = 42;
4470
4471 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4472 break;
4473 case bfd_mach_sh3_dsp:
4474 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
4475 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4476 sh_show_regs = sh3_dsp_show_regs;
4477 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4478 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4479 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4480 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4481 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4482 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4483 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4484 tdep->DSR_REGNUM = 24;
4485 tdep->A0G_REGNUM = 25;
4486 tdep->A0_REGNUM = 26;
4487 tdep->A1G_REGNUM = 27;
4488 tdep->A1_REGNUM = 28;
4489 tdep->M0_REGNUM = 29;
4490 tdep->M1_REGNUM = 30;
4491 tdep->X0_REGNUM = 31;
4492 tdep->X1_REGNUM = 32;
4493 tdep->Y0_REGNUM = 33;
4494 tdep->Y1_REGNUM = 34;
4495 tdep->MOD_REGNUM = 40;
4496 tdep->RS_REGNUM = 43;
4497 tdep->RE_REGNUM = 44;
4498 tdep->SSR_REGNUM = 41;
4499 tdep->SPC_REGNUM = 42;
4500
4501 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4502 break;
4503 case bfd_mach_sh4:
4504 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
4505 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4506 sh_show_regs = sh4_show_regs;
4507 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
4508 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4509 set_gdbarch_fp0_regnum (gdbarch, 25);
4510 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4511 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4512 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
4513 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
4514 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4515 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4516 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4517 tdep->FPUL_REGNUM = 23;
4518 tdep->FPSCR_REGNUM = 24;
4519 tdep->FP_LAST_REGNUM = 40;
4520 tdep->SSR_REGNUM = 41;
4521 tdep->SPC_REGNUM = 42;
4522 tdep->DR0_REGNUM = 59;
4523 tdep->DR_LAST_REGNUM = 66;
4524 tdep->FV0_REGNUM = 67;
4525 tdep->FV_LAST_REGNUM = 70;
4526
4527 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4528 break;
4529 case bfd_mach_sh5:
4530 tdep->PR_REGNUM = 18;
4531 tdep->SR_REGNUM = 65;
4532 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4533 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4534 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4535 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4536 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4537 tdep->FPP0_REGNUM = 173;
4538 tdep->FPP_LAST_REGNUM = 204;
4539 tdep->DR0_REGNUM = 141;
4540 tdep->DR_LAST_REGNUM = 172;
4541 tdep->FV0_REGNUM = 205;
4542 tdep->FV_LAST_REGNUM = 220;
4543 tdep->R0_C_REGNUM = 221;
4544 tdep->R_LAST_C_REGNUM = 236;
4545 tdep->PC_C_REGNUM = 237;
4546 tdep->GBR_C_REGNUM = 238;
4547 tdep->MACH_C_REGNUM = 239;
4548 tdep->MACL_C_REGNUM = 240;
4549 tdep->PR_C_REGNUM = 241;
4550 tdep->T_C_REGNUM = 242;
4551 tdep->FPSCR_C_REGNUM = 243;
4552 tdep->FPUL_C_REGNUM = 244;
4553 tdep->FP0_C_REGNUM = 245;
4554 tdep->FP_LAST_C_REGNUM = 260;
4555 tdep->DR0_C_REGNUM = 261;
4556 tdep->DR_LAST_C_REGNUM = 268;
4557 tdep->FV0_C_REGNUM = 269;
4558 tdep->FV_LAST_C_REGNUM = 272;
4559 tdep->ARG0_REGNUM = 2;
4560 tdep->ARGLAST_REGNUM = 9;
4561 tdep->RETURN_REGNUM = 2;
4562 tdep->FLOAT_ARGLAST_REGNUM = 11;
4563
4564 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4565 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4566 set_gdbarch_pc_regnum (gdbarch, 64);
4567
4568 /* Determine the ABI */
4569 if (bfd_get_arch_size (info.abfd) == 64)
4570 {
4571 /* If the ABI is the 64-bit one, it can only be sh-media. */
4572 tdep->sh_abi = SH_ABI_64;
4573 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4574 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4575 }
4576 else
4577 {
4578 /* If the ABI is the 32-bit one it could be either media or
4579 compact. */
4580 tdep->sh_abi = SH_ABI_32;
4581 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4582 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4583 }
4584
4585 /* the number of real registers is the same whether we are in
4586 ISA16(compact) or ISA32(media). */
4587 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4588 set_gdbarch_deprecated_register_size (gdbarch, 8); /*????*/
4589 set_gdbarch_deprecated_register_bytes (gdbarch,
4590 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4591 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4592
4593 set_gdbarch_register_name (gdbarch, sh_sh64_register_name);
4594 sh_show_regs = sh64_show_regs;
4595 set_gdbarch_deprecated_register_virtual_type (gdbarch, sh_sh64_register_virtual_type);
4596 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
4597 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4598 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4599 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4600 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte);
4601 /* This seems awfully wrong!*/
4602 /*set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8);*/
4603 /* should include the size of the pseudo regs. */
4604 set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4);
4605 /* Or should that go in the virtual_size? */
4606 /*set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8);*/
4607 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4);
4608 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4609 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
4610
4611 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
4612 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4613 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4614 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
4615 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
4616
4617 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4618 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
4619 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
4620 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
4621 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
4622 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
4623 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
4624 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
4625 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
4626 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4627 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
4628 set_gdbarch_elf_make_msymbol_special (gdbarch,
4629 sh64_elf_make_msymbol_special);
4630 break;
4631 default:
4632 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
4633 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4634 sh_show_regs = sh_generic_show_regs;
4635 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4636 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4637 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4638 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4639
4640 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4641 break;
4642 }
4643
4644 /* Hook in ABI-specific overrides, if they have been registered. */
4645 gdbarch_init_osabi (info, gdbarch);
4646
4647 return gdbarch;
4648 }
4649
4650 static void
4651 sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4652 {
4653 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4654
4655 if (tdep == NULL)
4656 return;
4657
4658 /* FIXME: dump the rest of gdbarch_tdep. */
4659 }
4660
4661 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
4662
4663 void
4664 _initialize_sh_tdep (void)
4665 {
4666 struct cmd_list_element *c;
4667
4668 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
4669
4670 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
4671 }
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