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2005-11-23 Andrew Stubbs <andrew.stubbs@st.com>
[thirdparty/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
4 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 /*
24 Contributed by Steve Chamberlain
25 sac@cygnus.com
26 */
27
28 #include "defs.h"
29 #include "frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
32 #include "dwarf2-frame.h"
33 #include "symtab.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "regcache.h"
45 #include "doublest.h"
46 #include "osabi.h"
47
48 #include "sh-tdep.h"
49
50 #include "elf-bfd.h"
51 #include "solib-svr4.h"
52
53 /* sh flags */
54 #include "elf/sh.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
57
58 static void (*sh_show_regs) (void);
59
60 #define SH_NUM_REGS 67
61
62 struct sh_frame_cache
63 {
64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
75 };
76
77 static const char *
78 sh_sh_register_name (int reg_nr)
79 {
80 static char *register_names[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "", "",
85 "", "", "", "", "", "", "", "",
86 "", "", "", "", "", "", "", "",
87 "", "",
88 "", "", "", "", "", "", "", "",
89 "", "", "", "", "", "", "", "",
90 "", "", "", "", "", "", "", "",
91 };
92 if (reg_nr < 0)
93 return NULL;
94 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
95 return NULL;
96 return register_names[reg_nr];
97 }
98
99 static const char *
100 sh_sh3_register_name (int reg_nr)
101 {
102 static char *register_names[] = {
103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
105 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
106 "", "",
107 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "", "",
109 "ssr", "spc",
110 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
111 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
112 "", "", "", "", "", "", "", "",
113 };
114 if (reg_nr < 0)
115 return NULL;
116 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
117 return NULL;
118 return register_names[reg_nr];
119 }
120
121 static const char *
122 sh_sh3e_register_name (int reg_nr)
123 {
124 static char *register_names[] = {
125 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
126 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
127 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
128 "fpul", "fpscr",
129 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
130 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
131 "ssr", "spc",
132 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
133 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
134 "", "", "", "", "", "", "", "",
135 };
136 if (reg_nr < 0)
137 return NULL;
138 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
139 return NULL;
140 return register_names[reg_nr];
141 }
142
143 static const char *
144 sh_sh2e_register_name (int reg_nr)
145 {
146 static char *register_names[] = {
147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
149 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
150 "fpul", "fpscr",
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
153 "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 };
158 if (reg_nr < 0)
159 return NULL;
160 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
161 return NULL;
162 return register_names[reg_nr];
163 }
164
165 static const char *
166 sh_sh2a_register_name (int reg_nr)
167 {
168 static char *register_names[] = {
169 /* general registers 0-15 */
170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 /* 16 - 22 */
173 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
174 /* 23, 24 */
175 "fpul", "fpscr",
176 /* floating point registers 25 - 40 */
177 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
178 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
179 /* 41, 42 */
180 "", "",
181 /* 43 - 62. Banked registers. The bank number used is determined by
182 the bank register (63). */
183 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
184 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
185 "machb", "ivnb", "prb", "gbrb", "maclb",
186 /* 63: register bank number, not a real register but used to
187 communicate the register bank currently get/set. This register
188 is hidden to the user, who manipulates it using the pseudo
189 register called "bank" (67). See below. */
190 "",
191 /* 64 - 66 */
192 "ibcr", "ibnr", "tbr",
193 /* 67: register bank number, the user visible pseudo register. */
194 "bank",
195 /* double precision (pseudo) 68 - 75 */
196 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
197 };
198 if (reg_nr < 0)
199 return NULL;
200 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
201 return NULL;
202 return register_names[reg_nr];
203 }
204
205 static const char *
206 sh_sh2a_nofpu_register_name (int reg_nr)
207 {
208 static char *register_names[] = {
209 /* general registers 0-15 */
210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
212 /* 16 - 22 */
213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
214 /* 23, 24 */
215 "", "",
216 /* floating point registers 25 - 40 */
217 "", "", "", "", "", "", "", "",
218 "", "", "", "", "", "", "", "",
219 /* 41, 42 */
220 "", "",
221 /* 43 - 62. Banked registers. The bank number used is determined by
222 the bank register (63). */
223 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
224 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
225 "machb", "ivnb", "prb", "gbrb", "maclb",
226 /* 63: register bank number, not a real register but used to
227 communicate the register bank currently get/set. This register
228 is hidden to the user, who manipulates it using the pseudo
229 register called "bank" (67). See below. */
230 "",
231 /* 64 - 66 */
232 "ibcr", "ibnr", "tbr",
233 /* 67: register bank number, the user visible pseudo register. */
234 "bank",
235 /* double precision (pseudo) 68 - 75 */
236 "", "", "", "", "", "", "", "",
237 };
238 if (reg_nr < 0)
239 return NULL;
240 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
241 return NULL;
242 return register_names[reg_nr];
243 }
244
245 static const char *
246 sh_sh_dsp_register_name (int reg_nr)
247 {
248 static char *register_names[] = {
249 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
250 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
251 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
252 "", "dsr",
253 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
254 "y0", "y1", "", "", "", "", "", "mod",
255 "", "",
256 "rs", "re", "", "", "", "", "", "",
257 "", "", "", "", "", "", "", "",
258 "", "", "", "", "", "", "", "",
259 };
260 if (reg_nr < 0)
261 return NULL;
262 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
263 return NULL;
264 return register_names[reg_nr];
265 }
266
267 static const char *
268 sh_sh3_dsp_register_name (int reg_nr)
269 {
270 static char *register_names[] = {
271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
273 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
274 "", "dsr",
275 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
276 "y0", "y1", "", "", "", "", "", "mod",
277 "ssr", "spc",
278 "rs", "re", "", "", "", "", "", "",
279 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
280 "", "", "", "", "", "", "", "",
281 "", "", "", "", "", "", "", "",
282 };
283 if (reg_nr < 0)
284 return NULL;
285 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
286 return NULL;
287 return register_names[reg_nr];
288 }
289
290 static const char *
291 sh_sh4_register_name (int reg_nr)
292 {
293 static char *register_names[] = {
294 /* general registers 0-15 */
295 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
296 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
297 /* 16 - 22 */
298 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
299 /* 23, 24 */
300 "fpul", "fpscr",
301 /* floating point registers 25 - 40 */
302 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
303 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
304 /* 41, 42 */
305 "ssr", "spc",
306 /* bank 0 43 - 50 */
307 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
308 /* bank 1 51 - 58 */
309 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
310 "", "", "", "", "", "", "", "",
311 /* pseudo bank register. */
312 "",
313 /* double precision (pseudo) 59 - 66 */
314 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
315 /* vectors (pseudo) 67 - 70 */
316 "fv0", "fv4", "fv8", "fv12",
317 /* FIXME: missing XF 71 - 86 */
318 /* FIXME: missing XD 87 - 94 */
319 };
320 if (reg_nr < 0)
321 return NULL;
322 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
323 return NULL;
324 return register_names[reg_nr];
325 }
326
327 static const char *
328 sh_sh4_nofpu_register_name (int reg_nr)
329 {
330 static char *register_names[] = {
331 /* general registers 0-15 */
332 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
333 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
334 /* 16 - 22 */
335 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
336 /* 23, 24 */
337 "", "",
338 /* floating point registers 25 - 40 -- not for nofpu target */
339 "", "", "", "", "", "", "", "",
340 "", "", "", "", "", "", "", "",
341 /* 41, 42 */
342 "ssr", "spc",
343 /* bank 0 43 - 50 */
344 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
345 /* bank 1 51 - 58 */
346 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
347 "", "", "", "", "", "", "", "",
348 /* pseudo bank register. */
349 "",
350 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
351 "", "", "", "", "", "", "", "",
352 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
353 "", "", "", "",
354 };
355 if (reg_nr < 0)
356 return NULL;
357 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
358 return NULL;
359 return register_names[reg_nr];
360 }
361
362 static const char *
363 sh_sh4al_dsp_register_name (int reg_nr)
364 {
365 static char *register_names[] = {
366 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
367 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
368 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
369 "", "dsr",
370 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
371 "y0", "y1", "", "", "", "", "", "mod",
372 "ssr", "spc",
373 "rs", "re", "", "", "", "", "", "",
374 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
375 "", "", "", "", "", "", "", "",
376 "", "", "", "", "", "", "", "",
377 };
378 if (reg_nr < 0)
379 return NULL;
380 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
381 return NULL;
382 return register_names[reg_nr];
383 }
384
385 static const unsigned char *
386 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
387 {
388 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
389 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
390
391 *lenptr = sizeof (breakpoint);
392 return breakpoint;
393 }
394
395 /* Prologue looks like
396 mov.l r14,@-r15
397 sts.l pr,@-r15
398 mov.l <regs>,@-r15
399 sub <room_for_loca_vars>,r15
400 mov r15,r14
401
402 Actually it can be more complicated than this but that's it, basically.
403 */
404
405 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
406 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
407
408 /* JSR @Rm 0100mmmm00001011 */
409 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
410
411 /* STS.L PR,@-r15 0100111100100010
412 r15-4-->r15, PR-->(r15) */
413 #define IS_STS(x) ((x) == 0x4f22)
414
415 /* STS.L MACL,@-r15 0100111100010010
416 r15-4-->r15, MACL-->(r15) */
417 #define IS_MACL_STS(x) ((x) == 0x4f12)
418
419 /* MOV.L Rm,@-r15 00101111mmmm0110
420 r15-4-->r15, Rm-->(R15) */
421 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
422
423 /* MOV r15,r14 0110111011110011
424 r15-->r14 */
425 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
426
427 /* ADD #imm,r15 01111111iiiiiiii
428 r15+imm-->r15 */
429 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
430
431 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
432 #define IS_SHLL_R3(x) ((x) == 0x4300)
433
434 /* ADD r3,r15 0011111100111100
435 r15+r3-->r15 */
436 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
437
438 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
439 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
440 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
441 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
442 make this entirely clear. */
443 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
444 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
445
446 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
447 #define IS_MOV_ARG_TO_REG(x) \
448 (((x) & 0xf00f) == 0x6003 && \
449 ((x) & 0x00f0) >= 0x0040 && \
450 ((x) & 0x00f0) <= 0x0070)
451 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
452 #define IS_MOV_ARG_TO_IND_R14(x) \
453 (((x) & 0xff0f) == 0x2e02 && \
454 ((x) & 0x00f0) >= 0x0040 && \
455 ((x) & 0x00f0) <= 0x0070)
456 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
457 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
458 (((x) & 0xff00) == 0x1e00 && \
459 ((x) & 0x00f0) >= 0x0040 && \
460 ((x) & 0x00f0) <= 0x0070)
461
462 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
463 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
464 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
465 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
466 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
467 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
468 /* SUB Rn,R15 00111111nnnn1000 */
469 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
470
471 #define FPSCR_SZ (1 << 20)
472
473 /* The following instructions are used for epilogue testing. */
474 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
475 #define IS_RTS(x) ((x) == 0x000b)
476 #define IS_LDS(x) ((x) == 0x4f26)
477 #define IS_MACL_LDS(x) ((x) == 0x4f16)
478 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
479 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
480 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
481
482 /* Disassemble an instruction. */
483 static int
484 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
485 {
486 info->endian = TARGET_BYTE_ORDER;
487 return print_insn_sh (memaddr, info);
488 }
489
490 static CORE_ADDR
491 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
492 struct sh_frame_cache *cache)
493 {
494 ULONGEST inst;
495 CORE_ADDR opc;
496 int offset;
497 int sav_offset = 0;
498 int r3_val = 0;
499 int reg, sav_reg = -1;
500
501 if (pc >= current_pc)
502 return current_pc;
503
504 cache->uses_fp = 0;
505 for (opc = pc + (2 * 28); pc < opc; pc += 2)
506 {
507 inst = read_memory_unsigned_integer (pc, 2);
508 /* See where the registers will be saved to */
509 if (IS_PUSH (inst))
510 {
511 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
512 cache->sp_offset += 4;
513 }
514 else if (IS_STS (inst))
515 {
516 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
517 cache->sp_offset += 4;
518 }
519 else if (IS_MACL_STS (inst))
520 {
521 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
522 cache->sp_offset += 4;
523 }
524 else if (IS_MOV_R3 (inst))
525 {
526 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
527 }
528 else if (IS_SHLL_R3 (inst))
529 {
530 r3_val <<= 1;
531 }
532 else if (IS_ADD_R3SP (inst))
533 {
534 cache->sp_offset += -r3_val;
535 }
536 else if (IS_ADD_IMM_SP (inst))
537 {
538 offset = ((inst & 0xff) ^ 0x80) - 0x80;
539 cache->sp_offset -= offset;
540 }
541 else if (IS_MOVW_PCREL_TO_REG (inst))
542 {
543 if (sav_reg < 0)
544 {
545 reg = GET_TARGET_REG (inst);
546 if (reg < 14)
547 {
548 sav_reg = reg;
549 offset = (inst & 0xff) << 1;
550 sav_offset =
551 read_memory_integer ((pc + 4) + offset, 2);
552 }
553 }
554 }
555 else if (IS_MOVL_PCREL_TO_REG (inst))
556 {
557 if (sav_reg < 0)
558 {
559 reg = GET_TARGET_REG (inst);
560 if (reg < 14)
561 {
562 sav_reg = reg;
563 offset = (inst & 0xff) << 2;
564 sav_offset =
565 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
566 }
567 }
568 }
569 else if (IS_MOVI20 (inst))
570 {
571 if (sav_reg < 0)
572 {
573 reg = GET_TARGET_REG (inst);
574 if (reg < 14)
575 {
576 sav_reg = reg;
577 sav_offset = GET_SOURCE_REG (inst) << 16;
578 /* MOVI20 is a 32 bit instruction! */
579 pc += 2;
580 sav_offset |= read_memory_unsigned_integer (pc, 2);
581 /* Now sav_offset contains an unsigned 20 bit value.
582 It must still get sign extended. */
583 if (sav_offset & 0x00080000)
584 sav_offset |= 0xfff00000;
585 }
586 }
587 }
588 else if (IS_SUB_REG_FROM_SP (inst))
589 {
590 reg = GET_SOURCE_REG (inst);
591 if (sav_reg > 0 && reg == sav_reg)
592 {
593 sav_reg = -1;
594 }
595 cache->sp_offset += sav_offset;
596 }
597 else if (IS_FPUSH (inst))
598 {
599 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
600 {
601 cache->sp_offset += 8;
602 }
603 else
604 {
605 cache->sp_offset += 4;
606 }
607 }
608 else if (IS_MOV_SP_FP (inst))
609 {
610 cache->uses_fp = 1;
611 /* At this point, only allow argument register moves to other
612 registers or argument register moves to @(X,fp) which are
613 moving the register arguments onto the stack area allocated
614 by a former add somenumber to SP call. Don't allow moving
615 to an fp indirect address above fp + cache->sp_offset. */
616 pc += 2;
617 for (opc = pc + 12; pc < opc; pc += 2)
618 {
619 inst = read_memory_integer (pc, 2);
620 if (IS_MOV_ARG_TO_IND_R14 (inst))
621 {
622 reg = GET_SOURCE_REG (inst);
623 if (cache->sp_offset > 0)
624 cache->saved_regs[reg] = cache->sp_offset;
625 }
626 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
627 {
628 reg = GET_SOURCE_REG (inst);
629 offset = (inst & 0xf) * 4;
630 if (cache->sp_offset > offset)
631 cache->saved_regs[reg] = cache->sp_offset - offset;
632 }
633 else if (IS_MOV_ARG_TO_REG (inst))
634 continue;
635 else
636 break;
637 }
638 break;
639 }
640 else if (IS_JSR (inst))
641 {
642 /* We have found a jsr that has been scheduled into the prologue.
643 If we continue the scan and return a pc someplace after this,
644 then setting a breakpoint on this function will cause it to
645 appear to be called after the function it is calling via the
646 jsr, which will be very confusing. Most likely the next
647 instruction is going to be IS_MOV_SP_FP in the delay slot. If
648 so, note that before returning the current pc. */
649 inst = read_memory_integer (pc + 2, 2);
650 if (IS_MOV_SP_FP (inst))
651 cache->uses_fp = 1;
652 break;
653 }
654 #if 0 /* This used to just stop when it found an instruction that
655 was not considered part of the prologue. Now, we just
656 keep going looking for likely instructions. */
657 else
658 break;
659 #endif
660 }
661
662 return pc;
663 }
664
665 /* Skip any prologue before the guts of a function */
666
667 /* Skip the prologue using the debug information. If this fails we'll
668 fall back on the 'guess' method below. */
669 static CORE_ADDR
670 after_prologue (CORE_ADDR pc)
671 {
672 struct symtab_and_line sal;
673 CORE_ADDR func_addr, func_end;
674
675 /* If we can not find the symbol in the partial symbol table, then
676 there is no hope we can determine the function's start address
677 with this code. */
678 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
679 return 0;
680
681 /* Get the line associated with FUNC_ADDR. */
682 sal = find_pc_line (func_addr, 0);
683
684 /* There are only two cases to consider. First, the end of the source line
685 is within the function bounds. In that case we return the end of the
686 source line. Second is the end of the source line extends beyond the
687 bounds of the current function. We need to use the slow code to
688 examine instructions in that case. */
689 if (sal.end < func_end)
690 return sal.end;
691 else
692 return 0;
693 }
694
695 static CORE_ADDR
696 sh_skip_prologue (CORE_ADDR start_pc)
697 {
698 CORE_ADDR pc;
699 struct sh_frame_cache cache;
700
701 /* See if we can determine the end of the prologue via the symbol table.
702 If so, then return either PC, or the PC after the prologue, whichever
703 is greater. */
704 pc = after_prologue (start_pc);
705
706 /* If after_prologue returned a useful address, then use it. Else
707 fall back on the instruction skipping code. */
708 if (pc)
709 return max (pc, start_pc);
710
711 cache.sp_offset = -4;
712 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
713 if (!cache.uses_fp)
714 return start_pc;
715
716 return pc;
717 }
718
719 /* The ABI says:
720
721 Aggregate types not bigger than 8 bytes that have the same size and
722 alignment as one of the integer scalar types are returned in the
723 same registers as the integer type they match.
724
725 For example, a 2-byte aligned structure with size 2 bytes has the
726 same size and alignment as a short int, and will be returned in R0.
727 A 4-byte aligned structure with size 8 bytes has the same size and
728 alignment as a long long int, and will be returned in R0 and R1.
729
730 When an aggregate type is returned in R0 and R1, R0 contains the
731 first four bytes of the aggregate, and R1 contains the
732 remainder. If the size of the aggregate type is not a multiple of 4
733 bytes, the aggregate is tail-padded up to a multiple of 4
734 bytes. The value of the padding is undefined. For little-endian
735 targets the padding will appear at the most significant end of the
736 last element, for big-endian targets the padding appears at the
737 least significant end of the last element.
738
739 All other aggregate types are returned by address. The caller
740 function passes the address of an area large enough to hold the
741 aggregate value in R2. The called function stores the result in
742 this location.
743
744 To reiterate, structs smaller than 8 bytes could also be returned
745 in memory, if they don't pass the "same size and alignment as an
746 integer type" rule.
747
748 For example, in
749
750 struct s { char c[3]; } wibble;
751 struct s foo(void) { return wibble; }
752
753 the return value from foo() will be in memory, not
754 in R0, because there is no 3-byte integer type.
755
756 Similarly, in
757
758 struct s { char c[2]; } wibble;
759 struct s foo(void) { return wibble; }
760
761 because a struct containing two chars has alignment 1, that matches
762 type char, but size 2, that matches type short. There's no integer
763 type that has alignment 1 and size 2, so the struct is returned in
764 memory.
765
766 */
767
768 static int
769 sh_use_struct_convention (int gcc_p, struct type *type)
770 {
771 int len = TYPE_LENGTH (type);
772 int nelem = TYPE_NFIELDS (type);
773
774 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
775 fit in two registers anyway) use struct convention. */
776 if (len != 1 && len != 2 && len != 4 && len != 8)
777 return 1;
778
779 /* Scalar types and aggregate types with exactly one field are aligned
780 by definition. They are returned in registers. */
781 if (nelem <= 1)
782 return 0;
783
784 /* If the first field in the aggregate has the same length as the entire
785 aggregate type, the type is returned in registers. */
786 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
787 return 0;
788
789 /* If the size of the aggregate is 8 bytes and the first field is
790 of size 4 bytes its alignment is equal to long long's alignment,
791 so it's returned in registers. */
792 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
793 return 0;
794
795 /* Otherwise use struct convention. */
796 return 1;
797 }
798
799 /* Extract from an array REGBUF containing the (raw) register state
800 the address in which a function should return its structure value,
801 as a CORE_ADDR (or an expression that can be used as one). */
802 static CORE_ADDR
803 sh_extract_struct_value_address (struct regcache *regcache)
804 {
805 ULONGEST addr;
806
807 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
808 return addr;
809 }
810
811 static CORE_ADDR
812 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
813 {
814 return sp & ~3;
815 }
816
817 /* Function: push_dummy_call (formerly push_arguments)
818 Setup the function arguments for calling a function in the inferior.
819
820 On the Renesas SH architecture, there are four registers (R4 to R7)
821 which are dedicated for passing function arguments. Up to the first
822 four arguments (depending on size) may go into these registers.
823 The rest go on the stack.
824
825 MVS: Except on SH variants that have floating point registers.
826 In that case, float and double arguments are passed in the same
827 manner, but using FP registers instead of GP registers.
828
829 Arguments that are smaller than 4 bytes will still take up a whole
830 register or a whole 32-bit word on the stack, and will be
831 right-justified in the register or the stack word. This includes
832 chars, shorts, and small aggregate types.
833
834 Arguments that are larger than 4 bytes may be split between two or
835 more registers. If there are not enough registers free, an argument
836 may be passed partly in a register (or registers), and partly on the
837 stack. This includes doubles, long longs, and larger aggregates.
838 As far as I know, there is no upper limit to the size of aggregates
839 that will be passed in this way; in other words, the convention of
840 passing a pointer to a large aggregate instead of a copy is not used.
841
842 MVS: The above appears to be true for the SH variants that do not
843 have an FPU, however those that have an FPU appear to copy the
844 aggregate argument onto the stack (and not place it in registers)
845 if it is larger than 16 bytes (four GP registers).
846
847 An exceptional case exists for struct arguments (and possibly other
848 aggregates such as arrays) if the size is larger than 4 bytes but
849 not a multiple of 4 bytes. In this case the argument is never split
850 between the registers and the stack, but instead is copied in its
851 entirety onto the stack, AND also copied into as many registers as
852 there is room for. In other words, space in registers permitting,
853 two copies of the same argument are passed in. As far as I can tell,
854 only the one on the stack is used, although that may be a function
855 of the level of compiler optimization. I suspect this is a compiler
856 bug. Arguments of these odd sizes are left-justified within the
857 word (as opposed to arguments smaller than 4 bytes, which are
858 right-justified).
859
860 If the function is to return an aggregate type such as a struct, it
861 is either returned in the normal return value register R0 (if its
862 size is no greater than one byte), or else the caller must allocate
863 space into which the callee will copy the return value (if the size
864 is greater than one byte). In this case, a pointer to the return
865 value location is passed into the callee in register R2, which does
866 not displace any of the other arguments passed in via registers R4
867 to R7. */
868
869 /* Helper function to justify value in register according to endianess. */
870 static char *
871 sh_justify_value_in_reg (struct value *val, int len)
872 {
873 static char valbuf[4];
874
875 memset (valbuf, 0, sizeof (valbuf));
876 if (len < 4)
877 {
878 /* value gets right-justified in the register or stack word */
879 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
880 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
881 else
882 memcpy (valbuf, (char *) value_contents (val), len);
883 return valbuf;
884 }
885 return (char *) value_contents (val);
886 }
887
888 /* Helper function to eval number of bytes to allocate on stack. */
889 static CORE_ADDR
890 sh_stack_allocsize (int nargs, struct value **args)
891 {
892 int stack_alloc = 0;
893 while (nargs-- > 0)
894 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
895 return stack_alloc;
896 }
897
898 /* Helper functions for getting the float arguments right. Registers usage
899 depends on the ABI and the endianess. The comments should enlighten how
900 it's intended to work. */
901
902 /* This array stores which of the float arg registers are already in use. */
903 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
904
905 /* This function just resets the above array to "no reg used so far". */
906 static void
907 sh_init_flt_argreg (void)
908 {
909 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
910 }
911
912 /* This function returns the next register to use for float arg passing.
913 It returns either a valid value between FLOAT_ARG0_REGNUM and
914 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
915 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
916
917 Note that register number 0 in flt_argreg_array corresponds with the
918 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
919 29) the parity of the register number is preserved, which is important
920 for the double register passing test (see the "argreg & 1" test below). */
921 static int
922 sh_next_flt_argreg (int len)
923 {
924 int argreg;
925
926 /* First search for the next free register. */
927 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
928 ++argreg)
929 if (!flt_argreg_array[argreg])
930 break;
931
932 /* No register left? */
933 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
934 return FLOAT_ARGLAST_REGNUM + 1;
935
936 if (len == 8)
937 {
938 /* Doubles are always starting in a even register number. */
939 if (argreg & 1)
940 {
941 flt_argreg_array[argreg] = 1;
942
943 ++argreg;
944
945 /* No register left? */
946 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
947 return FLOAT_ARGLAST_REGNUM + 1;
948 }
949 /* Also mark the next register as used. */
950 flt_argreg_array[argreg + 1] = 1;
951 }
952 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
953 {
954 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
955 if (!flt_argreg_array[argreg + 1])
956 ++argreg;
957 }
958 flt_argreg_array[argreg] = 1;
959 return FLOAT_ARG0_REGNUM + argreg;
960 }
961
962 /* Helper function which figures out, if a type is treated like a float type.
963
964 The FPU ABIs have a special way how to treat types as float types.
965 Structures with exactly one member, which is of type float or double, are
966 treated exactly as the base types float or double:
967
968 struct sf {
969 float f;
970 };
971
972 struct sd {
973 double d;
974 };
975
976 are handled the same way as just
977
978 float f;
979
980 double d;
981
982 As a result, arguments of these struct types are pushed into floating point
983 registers exactly as floats or doubles, using the same decision algorithm.
984
985 The same is valid if these types are used as function return types. The
986 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
987 or even using struct convention as it is for other structs. */
988
989 static int
990 sh_treat_as_flt_p (struct type *type)
991 {
992 int len = TYPE_LENGTH (type);
993
994 /* Ordinary float types are obviously treated as float. */
995 if (TYPE_CODE (type) == TYPE_CODE_FLT)
996 return 1;
997 /* Otherwise non-struct types are not treated as float. */
998 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
999 return 0;
1000 /* Otherwise structs with more than one memeber are not treated as float. */
1001 if (TYPE_NFIELDS (type) != 1)
1002 return 0;
1003 /* Otherwise if the type of that member is float, the whole type is
1004 treated as float. */
1005 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1006 return 1;
1007 /* Otherwise it's not treated as float. */
1008 return 0;
1009 }
1010
1011 static CORE_ADDR
1012 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1013 struct value *function,
1014 struct regcache *regcache,
1015 CORE_ADDR bp_addr, int nargs,
1016 struct value **args,
1017 CORE_ADDR sp, int struct_return,
1018 CORE_ADDR struct_addr)
1019 {
1020 int stack_offset = 0;
1021 int argreg = ARG0_REGNUM;
1022 int flt_argreg = 0;
1023 int argnum;
1024 struct type *type;
1025 CORE_ADDR regval;
1026 char *val;
1027 int len, reg_size = 0;
1028 int pass_on_stack = 0;
1029 int treat_as_flt;
1030
1031 /* first force sp to a 4-byte alignment */
1032 sp = sh_frame_align (gdbarch, sp);
1033
1034 if (struct_return)
1035 regcache_cooked_write_unsigned (regcache,
1036 STRUCT_RETURN_REGNUM, struct_addr);
1037
1038 /* make room on stack for args */
1039 sp -= sh_stack_allocsize (nargs, args);
1040
1041 /* Initialize float argument mechanism. */
1042 sh_init_flt_argreg ();
1043
1044 /* Now load as many as possible of the first arguments into
1045 registers, and push the rest onto the stack. There are 16 bytes
1046 in four registers available. Loop thru args from first to last. */
1047 for (argnum = 0; argnum < nargs; argnum++)
1048 {
1049 type = value_type (args[argnum]);
1050 len = TYPE_LENGTH (type);
1051 val = sh_justify_value_in_reg (args[argnum], len);
1052
1053 /* Some decisions have to be made how various types are handled.
1054 This also differs in different ABIs. */
1055 pass_on_stack = 0;
1056
1057 /* Find out the next register to use for a floating point value. */
1058 treat_as_flt = sh_treat_as_flt_p (type);
1059 if (treat_as_flt)
1060 flt_argreg = sh_next_flt_argreg (len);
1061 /* In contrast to non-FPU CPUs, arguments are never split between
1062 registers and stack. If an argument doesn't fit in the remaining
1063 registers it's always pushed entirely on the stack. */
1064 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1065 pass_on_stack = 1;
1066
1067 while (len > 0)
1068 {
1069 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1070 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1071 || pass_on_stack)))
1072 {
1073 /* The data goes entirely on the stack, 4-byte aligned. */
1074 reg_size = (len + 3) & ~3;
1075 write_memory (sp + stack_offset, val, reg_size);
1076 stack_offset += reg_size;
1077 }
1078 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1079 {
1080 /* Argument goes in a float argument register. */
1081 reg_size = register_size (gdbarch, flt_argreg);
1082 regval = extract_unsigned_integer (val, reg_size);
1083 /* In little endian mode, float types taking two registers
1084 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1085 be stored swapped in the argument registers. The below
1086 code first writes the first 32 bits in the next but one
1087 register, increments the val and len values accordingly
1088 and then proceeds as normal by writing the second 32 bits
1089 into the next register. */
1090 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
1091 && TYPE_LENGTH (type) == 2 * reg_size)
1092 {
1093 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1094 regval);
1095 val += reg_size;
1096 len -= reg_size;
1097 regval = extract_unsigned_integer (val, reg_size);
1098 }
1099 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1100 }
1101 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1102 {
1103 /* there's room in a register */
1104 reg_size = register_size (gdbarch, argreg);
1105 regval = extract_unsigned_integer (val, reg_size);
1106 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1107 }
1108 /* Store the value one register at a time or in one step on stack. */
1109 len -= reg_size;
1110 val += reg_size;
1111 }
1112 }
1113
1114 /* Store return address. */
1115 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1116
1117 /* Update stack pointer. */
1118 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1119
1120 return sp;
1121 }
1122
1123 static CORE_ADDR
1124 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1125 struct value *function,
1126 struct regcache *regcache,
1127 CORE_ADDR bp_addr,
1128 int nargs, struct value **args,
1129 CORE_ADDR sp, int struct_return,
1130 CORE_ADDR struct_addr)
1131 {
1132 int stack_offset = 0;
1133 int argreg = ARG0_REGNUM;
1134 int argnum;
1135 struct type *type;
1136 CORE_ADDR regval;
1137 char *val;
1138 int len, reg_size;
1139
1140 /* first force sp to a 4-byte alignment */
1141 sp = sh_frame_align (gdbarch, sp);
1142
1143 if (struct_return)
1144 regcache_cooked_write_unsigned (regcache,
1145 STRUCT_RETURN_REGNUM, struct_addr);
1146
1147 /* make room on stack for args */
1148 sp -= sh_stack_allocsize (nargs, args);
1149
1150 /* Now load as many as possible of the first arguments into
1151 registers, and push the rest onto the stack. There are 16 bytes
1152 in four registers available. Loop thru args from first to last. */
1153 for (argnum = 0; argnum < nargs; argnum++)
1154 {
1155 type = value_type (args[argnum]);
1156 len = TYPE_LENGTH (type);
1157 val = sh_justify_value_in_reg (args[argnum], len);
1158
1159 while (len > 0)
1160 {
1161 if (argreg > ARGLAST_REGNUM)
1162 {
1163 /* The remainder of the data goes entirely on the stack,
1164 4-byte aligned. */
1165 reg_size = (len + 3) & ~3;
1166 write_memory (sp + stack_offset, val, reg_size);
1167 stack_offset += reg_size;
1168 }
1169 else if (argreg <= ARGLAST_REGNUM)
1170 {
1171 /* there's room in a register */
1172 reg_size = register_size (gdbarch, argreg);
1173 regval = extract_unsigned_integer (val, reg_size);
1174 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1175 }
1176 /* Store the value reg_size bytes at a time. This means that things
1177 larger than reg_size bytes may go partly in registers and partly
1178 on the stack. */
1179 len -= reg_size;
1180 val += reg_size;
1181 }
1182 }
1183
1184 /* Store return address. */
1185 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1186
1187 /* Update stack pointer. */
1188 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1189
1190 return sp;
1191 }
1192
1193 /* Find a function's return value in the appropriate registers (in
1194 regbuf), and copy it into valbuf. Extract from an array REGBUF
1195 containing the (raw) register state a function return value of type
1196 TYPE, and copy that, in virtual format, into VALBUF. */
1197 static void
1198 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1199 void *valbuf)
1200 {
1201 int len = TYPE_LENGTH (type);
1202 int return_register = R0_REGNUM;
1203 int offset;
1204
1205 if (len <= 4)
1206 {
1207 ULONGEST c;
1208
1209 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1210 store_unsigned_integer (valbuf, len, c);
1211 }
1212 else if (len == 8)
1213 {
1214 int i, regnum = R0_REGNUM;
1215 for (i = 0; i < len; i += 4)
1216 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1217 }
1218 else
1219 error (_("bad size for return value"));
1220 }
1221
1222 static void
1223 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1224 void *valbuf)
1225 {
1226 if (sh_treat_as_flt_p (type))
1227 {
1228 int len = TYPE_LENGTH (type);
1229 int i, regnum = FP0_REGNUM;
1230 for (i = 0; i < len; i += 4)
1231 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1232 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1233 else
1234 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1235 }
1236 else
1237 sh_extract_return_value_nofpu (type, regcache, valbuf);
1238 }
1239
1240 /* Write into appropriate registers a function return value
1241 of type TYPE, given in virtual format.
1242 If the architecture is sh4 or sh3e, store a function's return value
1243 in the R0 general register or in the FP0 floating point register,
1244 depending on the type of the return value. In all the other cases
1245 the result is stored in r0, left-justified. */
1246 static void
1247 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1248 const void *valbuf)
1249 {
1250 ULONGEST val;
1251 int len = TYPE_LENGTH (type);
1252
1253 if (len <= 4)
1254 {
1255 val = extract_unsigned_integer (valbuf, len);
1256 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1257 }
1258 else
1259 {
1260 int i, regnum = R0_REGNUM;
1261 for (i = 0; i < len; i += 4)
1262 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1263 }
1264 }
1265
1266 static void
1267 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1268 const void *valbuf)
1269 {
1270 if (sh_treat_as_flt_p (type))
1271 {
1272 int len = TYPE_LENGTH (type);
1273 int i, regnum = FP0_REGNUM;
1274 for (i = 0; i < len; i += 4)
1275 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1276 regcache_raw_write (regcache, regnum++,
1277 (char *) valbuf + len - 4 - i);
1278 else
1279 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1280 }
1281 else
1282 sh_store_return_value_nofpu (type, regcache, valbuf);
1283 }
1284
1285 static enum return_value_convention
1286 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1287 struct regcache *regcache,
1288 gdb_byte *readbuf, const gdb_byte *writebuf)
1289 {
1290 if (sh_use_struct_convention (0, type))
1291 return RETURN_VALUE_STRUCT_CONVENTION;
1292 if (writebuf)
1293 sh_store_return_value_nofpu (type, regcache, writebuf);
1294 else if (readbuf)
1295 sh_extract_return_value_nofpu (type, regcache, readbuf);
1296 return RETURN_VALUE_REGISTER_CONVENTION;
1297 }
1298
1299 static enum return_value_convention
1300 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1301 struct regcache *regcache,
1302 gdb_byte *readbuf, const gdb_byte *writebuf)
1303 {
1304 if (sh_use_struct_convention (0, type))
1305 return RETURN_VALUE_STRUCT_CONVENTION;
1306 if (writebuf)
1307 sh_store_return_value_fpu (type, regcache, writebuf);
1308 else if (readbuf)
1309 sh_extract_return_value_fpu (type, regcache, readbuf);
1310 return RETURN_VALUE_REGISTER_CONVENTION;
1311 }
1312
1313 /* Print the registers in a form similar to the E7000 */
1314
1315 static void
1316 sh_generic_show_regs (void)
1317 {
1318 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1319 paddr (read_register (PC_REGNUM)),
1320 (long) read_register (SR_REGNUM),
1321 (long) read_register (PR_REGNUM),
1322 (long) read_register (MACH_REGNUM),
1323 (long) read_register (MACL_REGNUM));
1324
1325 printf_filtered ("GBR=%08lx VBR=%08lx",
1326 (long) read_register (GBR_REGNUM),
1327 (long) read_register (VBR_REGNUM));
1328
1329 printf_filtered
1330 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1331 (long) read_register (0), (long) read_register (1),
1332 (long) read_register (2), (long) read_register (3),
1333 (long) read_register (4), (long) read_register (5),
1334 (long) read_register (6), (long) read_register (7));
1335 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1336 (long) read_register (8), (long) read_register (9),
1337 (long) read_register (10), (long) read_register (11),
1338 (long) read_register (12), (long) read_register (13),
1339 (long) read_register (14), (long) read_register (15));
1340 }
1341
1342 static void
1343 sh3_show_regs (void)
1344 {
1345 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1346 paddr (read_register (PC_REGNUM)),
1347 (long) read_register (SR_REGNUM),
1348 (long) read_register (PR_REGNUM),
1349 (long) read_register (MACH_REGNUM),
1350 (long) read_register (MACL_REGNUM));
1351
1352 printf_filtered ("GBR=%08lx VBR=%08lx",
1353 (long) read_register (GBR_REGNUM),
1354 (long) read_register (VBR_REGNUM));
1355 printf_filtered (" SSR=%08lx SPC=%08lx",
1356 (long) read_register (SSR_REGNUM),
1357 (long) read_register (SPC_REGNUM));
1358
1359 printf_filtered
1360 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1361 (long) read_register (0), (long) read_register (1),
1362 (long) read_register (2), (long) read_register (3),
1363 (long) read_register (4), (long) read_register (5),
1364 (long) read_register (6), (long) read_register (7));
1365 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1366 (long) read_register (8), (long) read_register (9),
1367 (long) read_register (10), (long) read_register (11),
1368 (long) read_register (12), (long) read_register (13),
1369 (long) read_register (14), (long) read_register (15));
1370 }
1371
1372
1373 static void
1374 sh2e_show_regs (void)
1375 {
1376 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1377 paddr (read_register (PC_REGNUM)),
1378 (long) read_register (SR_REGNUM),
1379 (long) read_register (PR_REGNUM),
1380 (long) read_register (MACH_REGNUM),
1381 (long) read_register (MACL_REGNUM));
1382
1383 printf_filtered ("GBR=%08lx VBR=%08lx",
1384 (long) read_register (GBR_REGNUM),
1385 (long) read_register (VBR_REGNUM));
1386 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1387 (long) read_register (FPUL_REGNUM),
1388 (long) read_register (FPSCR_REGNUM));
1389
1390 printf_filtered
1391 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1392 (long) read_register (0), (long) read_register (1),
1393 (long) read_register (2), (long) read_register (3),
1394 (long) read_register (4), (long) read_register (5),
1395 (long) read_register (6), (long) read_register (7));
1396 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1397 (long) read_register (8), (long) read_register (9),
1398 (long) read_register (10), (long) read_register (11),
1399 (long) read_register (12), (long) read_register (13),
1400 (long) read_register (14), (long) read_register (15));
1401
1402 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1403 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1404 }
1405
1406 static void
1407 sh2a_show_regs (void)
1408 {
1409 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1410 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1411 paddr (read_register (PC_REGNUM)),
1412 (long) read_register (SR_REGNUM),
1413 (long) read_register (PR_REGNUM),
1414 (long) read_register (MACH_REGNUM),
1415 (long) read_register (MACL_REGNUM));
1416
1417 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx",
1418 (long) read_register (GBR_REGNUM),
1419 (long) read_register (VBR_REGNUM),
1420 (long) read_register (TBR_REGNUM));
1421 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n",
1422 (long) read_register (FPUL_REGNUM),
1423 (long) read_register (FPSCR_REGNUM));
1424
1425 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1426 (long) read_register (0), (long) read_register (1),
1427 (long) read_register (2), (long) read_register (3),
1428 (long) read_register (4), (long) read_register (5),
1429 (long) read_register (6), (long) read_register (7));
1430 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1431 (long) read_register (8), (long) read_register (9),
1432 (long) read_register (10), (long) read_register (11),
1433 (long) read_register (12), (long) read_register (13),
1434 (long) read_register (14), (long) read_register (15));
1435
1436 printf_filtered ((pr
1437 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1438 :
1439 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1440 (long) read_register (FP0_REGNUM + 0),
1441 (long) read_register (FP0_REGNUM + 1),
1442 (long) read_register (FP0_REGNUM + 2),
1443 (long) read_register (FP0_REGNUM + 3),
1444 (long) read_register (FP0_REGNUM + 4),
1445 (long) read_register (FP0_REGNUM + 5),
1446 (long) read_register (FP0_REGNUM + 6),
1447 (long) read_register (FP0_REGNUM + 7));
1448 printf_filtered ((pr ?
1449 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1450 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1451 (long) read_register (FP0_REGNUM + 8),
1452 (long) read_register (FP0_REGNUM + 9),
1453 (long) read_register (FP0_REGNUM + 10),
1454 (long) read_register (FP0_REGNUM + 11),
1455 (long) read_register (FP0_REGNUM + 12),
1456 (long) read_register (FP0_REGNUM + 13),
1457 (long) read_register (FP0_REGNUM + 14),
1458 (long) read_register (FP0_REGNUM + 15));
1459 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
1460 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1461 (long) read_register (R0_BANK0_REGNUM + 0),
1462 (long) read_register (R0_BANK0_REGNUM + 1),
1463 (long) read_register (R0_BANK0_REGNUM + 2),
1464 (long) read_register (R0_BANK0_REGNUM + 3),
1465 (long) read_register (R0_BANK0_REGNUM + 4),
1466 (long) read_register (R0_BANK0_REGNUM + 5),
1467 (long) read_register (R0_BANK0_REGNUM + 6),
1468 (long) read_register (R0_BANK0_REGNUM + 7));
1469 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1470 (long) read_register (R0_BANK0_REGNUM + 8),
1471 (long) read_register (R0_BANK0_REGNUM + 9),
1472 (long) read_register (R0_BANK0_REGNUM + 10),
1473 (long) read_register (R0_BANK0_REGNUM + 11),
1474 (long) read_register (R0_BANK0_REGNUM + 12),
1475 (long) read_register (R0_BANK0_REGNUM + 13),
1476 (long) read_register (R0_BANK0_REGNUM + 14));
1477 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1478 (long) read_register (R0_BANK0_REGNUM + 15),
1479 (long) read_register (R0_BANK0_REGNUM + 16),
1480 (long) read_register (R0_BANK0_REGNUM + 17),
1481 (long) read_register (R0_BANK0_REGNUM + 18),
1482 (long) read_register (R0_BANK0_REGNUM + 19));
1483 }
1484
1485 static void
1486 sh2a_nofpu_show_regs (void)
1487 {
1488 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1489 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1490 paddr (read_register (PC_REGNUM)),
1491 (long) read_register (SR_REGNUM),
1492 (long) read_register (PR_REGNUM),
1493 (long) read_register (MACH_REGNUM),
1494 (long) read_register (MACL_REGNUM));
1495
1496 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx",
1497 (long) read_register (GBR_REGNUM),
1498 (long) read_register (VBR_REGNUM),
1499 (long) read_register (TBR_REGNUM));
1500 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n",
1501 (long) read_register (FPUL_REGNUM),
1502 (long) read_register (FPSCR_REGNUM));
1503
1504 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1505 (long) read_register (0), (long) read_register (1),
1506 (long) read_register (2), (long) read_register (3),
1507 (long) read_register (4), (long) read_register (5),
1508 (long) read_register (6), (long) read_register (7));
1509 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1510 (long) read_register (8), (long) read_register (9),
1511 (long) read_register (10), (long) read_register (11),
1512 (long) read_register (12), (long) read_register (13),
1513 (long) read_register (14), (long) read_register (15));
1514
1515 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
1516 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1517 (long) read_register (R0_BANK0_REGNUM + 0),
1518 (long) read_register (R0_BANK0_REGNUM + 1),
1519 (long) read_register (R0_BANK0_REGNUM + 2),
1520 (long) read_register (R0_BANK0_REGNUM + 3),
1521 (long) read_register (R0_BANK0_REGNUM + 4),
1522 (long) read_register (R0_BANK0_REGNUM + 5),
1523 (long) read_register (R0_BANK0_REGNUM + 6),
1524 (long) read_register (R0_BANK0_REGNUM + 7));
1525 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1526 (long) read_register (R0_BANK0_REGNUM + 8),
1527 (long) read_register (R0_BANK0_REGNUM + 9),
1528 (long) read_register (R0_BANK0_REGNUM + 10),
1529 (long) read_register (R0_BANK0_REGNUM + 11),
1530 (long) read_register (R0_BANK0_REGNUM + 12),
1531 (long) read_register (R0_BANK0_REGNUM + 13),
1532 (long) read_register (R0_BANK0_REGNUM + 14));
1533 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1534 (long) read_register (R0_BANK0_REGNUM + 15),
1535 (long) read_register (R0_BANK0_REGNUM + 16),
1536 (long) read_register (R0_BANK0_REGNUM + 17),
1537 (long) read_register (R0_BANK0_REGNUM + 18),
1538 (long) read_register (R0_BANK0_REGNUM + 19));
1539 }
1540
1541 static void
1542 sh3e_show_regs (void)
1543 {
1544 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1545 paddr (read_register (PC_REGNUM)),
1546 (long) read_register (SR_REGNUM),
1547 (long) read_register (PR_REGNUM),
1548 (long) read_register (MACH_REGNUM),
1549 (long) read_register (MACL_REGNUM));
1550
1551 printf_filtered ("GBR=%08lx VBR=%08lx",
1552 (long) read_register (GBR_REGNUM),
1553 (long) read_register (VBR_REGNUM));
1554 printf_filtered (" SSR=%08lx SPC=%08lx",
1555 (long) read_register (SSR_REGNUM),
1556 (long) read_register (SPC_REGNUM));
1557 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1558 (long) read_register (FPUL_REGNUM),
1559 (long) read_register (FPSCR_REGNUM));
1560
1561 printf_filtered
1562 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1563 (long) read_register (0), (long) read_register (1),
1564 (long) read_register (2), (long) read_register (3),
1565 (long) read_register (4), (long) read_register (5),
1566 (long) read_register (6), (long) read_register (7));
1567 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1568 (long) read_register (8), (long) read_register (9),
1569 (long) read_register (10), (long) read_register (11),
1570 (long) read_register (12), (long) read_register (13),
1571 (long) read_register (14), (long) read_register (15));
1572
1573 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1574 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1575 }
1576
1577 static void
1578 sh3_dsp_show_regs (void)
1579 {
1580 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1581 paddr (read_register (PC_REGNUM)),
1582 (long) read_register (SR_REGNUM),
1583 (long) read_register (PR_REGNUM),
1584 (long) read_register (MACH_REGNUM),
1585 (long) read_register (MACL_REGNUM));
1586
1587 printf_filtered ("GBR=%08lx VBR=%08lx",
1588 (long) read_register (GBR_REGNUM),
1589 (long) read_register (VBR_REGNUM));
1590
1591 printf_filtered (" SSR=%08lx SPC=%08lx",
1592 (long) read_register (SSR_REGNUM),
1593 (long) read_register (SPC_REGNUM));
1594
1595 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1596
1597 printf_filtered
1598 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1599 (long) read_register (0), (long) read_register (1),
1600 (long) read_register (2), (long) read_register (3),
1601 (long) read_register (4), (long) read_register (5),
1602 (long) read_register (6), (long) read_register (7));
1603 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1604 (long) read_register (8), (long) read_register (9),
1605 (long) read_register (10), (long) read_register (11),
1606 (long) read_register (12), (long) read_register (13),
1607 (long) read_register (14), (long) read_register (15));
1608
1609 printf_filtered
1610 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1611 (long) read_register (A0G_REGNUM) & 0xff,
1612 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1613 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1614 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1615 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1616 (long) read_register (A1G_REGNUM) & 0xff,
1617 (long) read_register (A1_REGNUM),
1618 (long) read_register (M1_REGNUM),
1619 (long) read_register (X1_REGNUM),
1620 (long) read_register (Y1_REGNUM),
1621 (long) read_register (RE_REGNUM));
1622 }
1623
1624 static void
1625 sh4_show_regs (void)
1626 {
1627 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1628 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1629 paddr (read_register (PC_REGNUM)),
1630 (long) read_register (SR_REGNUM),
1631 (long) read_register (PR_REGNUM),
1632 (long) read_register (MACH_REGNUM),
1633 (long) read_register (MACL_REGNUM));
1634
1635 printf_filtered ("GBR=%08lx VBR=%08lx",
1636 (long) read_register (GBR_REGNUM),
1637 (long) read_register (VBR_REGNUM));
1638 printf_filtered (" SSR=%08lx SPC=%08lx",
1639 (long) read_register (SSR_REGNUM),
1640 (long) read_register (SPC_REGNUM));
1641 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1642 (long) read_register (FPUL_REGNUM),
1643 (long) read_register (FPSCR_REGNUM));
1644
1645 printf_filtered
1646 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1647 (long) read_register (0), (long) read_register (1),
1648 (long) read_register (2), (long) read_register (3),
1649 (long) read_register (4), (long) read_register (5),
1650 (long) read_register (6), (long) read_register (7));
1651 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1652 (long) read_register (8), (long) read_register (9),
1653 (long) read_register (10), (long) read_register (11),
1654 (long) read_register (12), (long) read_register (13),
1655 (long) read_register (14), (long) read_register (15));
1656
1657 printf_filtered ((pr
1658 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1659 :
1660 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1661 (long) read_register (FP0_REGNUM + 0),
1662 (long) read_register (FP0_REGNUM + 1),
1663 (long) read_register (FP0_REGNUM + 2),
1664 (long) read_register (FP0_REGNUM + 3),
1665 (long) read_register (FP0_REGNUM + 4),
1666 (long) read_register (FP0_REGNUM + 5),
1667 (long) read_register (FP0_REGNUM + 6),
1668 (long) read_register (FP0_REGNUM + 7));
1669 printf_filtered ((pr ?
1670 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1671 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1672 (long) read_register (FP0_REGNUM + 8),
1673 (long) read_register (FP0_REGNUM + 9),
1674 (long) read_register (FP0_REGNUM + 10),
1675 (long) read_register (FP0_REGNUM + 11),
1676 (long) read_register (FP0_REGNUM + 12),
1677 (long) read_register (FP0_REGNUM + 13),
1678 (long) read_register (FP0_REGNUM + 14),
1679 (long) read_register (FP0_REGNUM + 15));
1680 }
1681
1682 static void
1683 sh4_nofpu_show_regs (void)
1684 {
1685 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1686 paddr (read_register (PC_REGNUM)),
1687 (long) read_register (SR_REGNUM),
1688 (long) read_register (PR_REGNUM),
1689 (long) read_register (MACH_REGNUM),
1690 (long) read_register (MACL_REGNUM));
1691
1692 printf_filtered ("GBR=%08lx VBR=%08lx",
1693 (long) read_register (GBR_REGNUM),
1694 (long) read_register (VBR_REGNUM));
1695 printf_filtered (" SSR=%08lx SPC=%08lx",
1696 (long) read_register (SSR_REGNUM),
1697 (long) read_register (SPC_REGNUM));
1698
1699 printf_filtered
1700 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1701 (long) read_register (0), (long) read_register (1),
1702 (long) read_register (2), (long) read_register (3),
1703 (long) read_register (4), (long) read_register (5),
1704 (long) read_register (6), (long) read_register (7));
1705 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1706 (long) read_register (8), (long) read_register (9),
1707 (long) read_register (10), (long) read_register (11),
1708 (long) read_register (12), (long) read_register (13),
1709 (long) read_register (14), (long) read_register (15));
1710 }
1711
1712 static void
1713 sh_dsp_show_regs (void)
1714 {
1715 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1716 paddr (read_register (PC_REGNUM)),
1717 (long) read_register (SR_REGNUM),
1718 (long) read_register (PR_REGNUM),
1719 (long) read_register (MACH_REGNUM),
1720 (long) read_register (MACL_REGNUM));
1721
1722 printf_filtered ("GBR=%08lx VBR=%08lx",
1723 (long) read_register (GBR_REGNUM),
1724 (long) read_register (VBR_REGNUM));
1725
1726 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1727
1728 printf_filtered
1729 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1730 (long) read_register (0), (long) read_register (1),
1731 (long) read_register (2), (long) read_register (3),
1732 (long) read_register (4), (long) read_register (5),
1733 (long) read_register (6), (long) read_register (7));
1734 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1735 (long) read_register (8), (long) read_register (9),
1736 (long) read_register (10), (long) read_register (11),
1737 (long) read_register (12), (long) read_register (13),
1738 (long) read_register (14), (long) read_register (15));
1739
1740 printf_filtered
1741 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1742 (long) read_register (A0G_REGNUM) & 0xff,
1743 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1744 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1745 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1746 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1747 (long) read_register (A1G_REGNUM) & 0xff,
1748 (long) read_register (A1_REGNUM),
1749 (long) read_register (M1_REGNUM),
1750 (long) read_register (X1_REGNUM),
1751 (long) read_register (Y1_REGNUM),
1752 (long) read_register (RE_REGNUM));
1753 }
1754
1755 static void
1756 sh_show_regs_command (char *args, int from_tty)
1757 {
1758 if (sh_show_regs)
1759 (*sh_show_regs) ();
1760 }
1761
1762 static struct type *
1763 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
1764 {
1765 if ((reg_nr >= FP0_REGNUM
1766 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1767 return builtin_type_float;
1768 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1769 return builtin_type_double;
1770 else
1771 return builtin_type_int;
1772 }
1773
1774 /* Return the GDB type object for the "standard" data type
1775 of data in register N. */
1776 static struct type *
1777 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1778 {
1779 if ((reg_nr >= FP0_REGNUM
1780 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1781 return builtin_type_float;
1782 else
1783 return builtin_type_int;
1784 }
1785
1786 static struct type *
1787 sh_sh4_build_float_register_type (int high)
1788 {
1789 struct type *temp;
1790
1791 temp = create_range_type (NULL, builtin_type_int, 0, high);
1792 return create_array_type (NULL, builtin_type_float, temp);
1793 }
1794
1795 static struct type *
1796 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1797 {
1798 if ((reg_nr >= FP0_REGNUM
1799 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1800 return builtin_type_float;
1801 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1802 return builtin_type_double;
1803 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1804 return sh_sh4_build_float_register_type (3);
1805 else
1806 return builtin_type_int;
1807 }
1808
1809 static struct type *
1810 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1811 {
1812 return builtin_type_int;
1813 }
1814
1815 /* On the sh4, the DRi pseudo registers are problematic if the target
1816 is little endian. When the user writes one of those registers, for
1817 instance with 'ser var $dr0=1', we want the double to be stored
1818 like this:
1819 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1820 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1821
1822 This corresponds to little endian byte order & big endian word
1823 order. However if we let gdb write the register w/o conversion, it
1824 will write fr0 and fr1 this way:
1825 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1826 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1827 because it will consider fr0 and fr1 as a single LE stretch of memory.
1828
1829 To achieve what we want we must force gdb to store things in
1830 floatformat_ieee_double_littlebyte_bigword (which is defined in
1831 include/floatformat.h and libiberty/floatformat.c.
1832
1833 In case the target is big endian, there is no problem, the
1834 raw bytes will look like:
1835 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1836 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1837
1838 The other pseudo registers (the FVs) also don't pose a problem
1839 because they are stored as 4 individual FP elements. */
1840
1841 static void
1842 sh_register_convert_to_virtual (int regnum, struct type *type,
1843 char *from, char *to)
1844 {
1845 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1846 {
1847 DOUBLEST val;
1848 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1849 from, &val);
1850 store_typed_floating (to, type, val);
1851 }
1852 else
1853 error
1854 ("sh_register_convert_to_virtual called with non DR register number");
1855 }
1856
1857 static void
1858 sh_register_convert_to_raw (struct type *type, int regnum,
1859 const void *from, void *to)
1860 {
1861 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1862 {
1863 DOUBLEST val = extract_typed_floating (from, type);
1864 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1865 &val, to);
1866 }
1867 else
1868 error (_("sh_register_convert_to_raw called with non DR register number"));
1869 }
1870
1871 /* For vectors of 4 floating point registers. */
1872 static int
1873 fv_reg_base_num (int fv_regnum)
1874 {
1875 int fp_regnum;
1876
1877 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1878 return fp_regnum;
1879 }
1880
1881 /* For double precision floating point registers, i.e 2 fp regs.*/
1882 static int
1883 dr_reg_base_num (int dr_regnum)
1884 {
1885 int fp_regnum;
1886
1887 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1888 return fp_regnum;
1889 }
1890
1891 static void
1892 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1893 int reg_nr, gdb_byte *buffer)
1894 {
1895 int base_regnum, portion;
1896 char temp_buffer[MAX_REGISTER_SIZE];
1897
1898 if (reg_nr == PSEUDO_BANK_REGNUM)
1899 regcache_raw_read (regcache, BANK_REGNUM, buffer);
1900 else
1901 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1902 {
1903 base_regnum = dr_reg_base_num (reg_nr);
1904
1905 /* Build the value in the provided buffer. */
1906 /* Read the real regs for which this one is an alias. */
1907 for (portion = 0; portion < 2; portion++)
1908 regcache_raw_read (regcache, base_regnum + portion,
1909 (temp_buffer
1910 + register_size (gdbarch,
1911 base_regnum) * portion));
1912 /* We must pay attention to the endiannes. */
1913 sh_register_convert_to_virtual (reg_nr,
1914 gdbarch_register_type (gdbarch, reg_nr),
1915 temp_buffer, buffer);
1916 }
1917 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1918 {
1919 base_regnum = fv_reg_base_num (reg_nr);
1920
1921 /* Read the real regs for which this one is an alias. */
1922 for (portion = 0; portion < 4; portion++)
1923 regcache_raw_read (regcache, base_regnum + portion,
1924 ((char *) buffer
1925 + register_size (gdbarch,
1926 base_regnum) * portion));
1927 }
1928 }
1929
1930 static void
1931 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1932 int reg_nr, const gdb_byte *buffer)
1933 {
1934 int base_regnum, portion;
1935 char temp_buffer[MAX_REGISTER_SIZE];
1936
1937 if (reg_nr == PSEUDO_BANK_REGNUM)
1938 {
1939 /* When the bank register is written to, the whole register bank
1940 is switched and all values in the bank registers must be read
1941 from the target/sim again. We're just invalidating the regcache
1942 so that a re-read happens next time it's necessary. */
1943 int bregnum;
1944
1945 regcache_raw_write (regcache, BANK_REGNUM, buffer);
1946 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
1947 set_register_cached (bregnum, 0);
1948 }
1949 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1950 {
1951 base_regnum = dr_reg_base_num (reg_nr);
1952
1953 /* We must pay attention to the endiannes. */
1954 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1955 reg_nr, buffer, temp_buffer);
1956
1957 /* Write the real regs for which this one is an alias. */
1958 for (portion = 0; portion < 2; portion++)
1959 regcache_raw_write (regcache, base_regnum + portion,
1960 (temp_buffer
1961 + register_size (gdbarch,
1962 base_regnum) * portion));
1963 }
1964 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1965 {
1966 base_regnum = fv_reg_base_num (reg_nr);
1967
1968 /* Write the real regs for which this one is an alias. */
1969 for (portion = 0; portion < 4; portion++)
1970 regcache_raw_write (regcache, base_regnum + portion,
1971 ((char *) buffer
1972 + register_size (gdbarch,
1973 base_regnum) * portion));
1974 }
1975 }
1976
1977 static int
1978 sh_dsp_register_sim_regno (int nr)
1979 {
1980 if (legacy_register_sim_regno (nr) < 0)
1981 return legacy_register_sim_regno (nr);
1982 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1983 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1984 if (nr == MOD_REGNUM)
1985 return SIM_SH_MOD_REGNUM;
1986 if (nr == RS_REGNUM)
1987 return SIM_SH_RS_REGNUM;
1988 if (nr == RE_REGNUM)
1989 return SIM_SH_RE_REGNUM;
1990 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
1991 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1992 return nr;
1993 }
1994
1995 static int
1996 sh_sh2a_register_sim_regno (int nr)
1997 {
1998 switch (nr)
1999 {
2000 case TBR_REGNUM:
2001 return SIM_SH_TBR_REGNUM;
2002 case IBNR_REGNUM:
2003 return SIM_SH_IBNR_REGNUM;
2004 case IBCR_REGNUM:
2005 return SIM_SH_IBCR_REGNUM;
2006 case BANK_REGNUM:
2007 return SIM_SH_BANK_REGNUM;
2008 case MACLB_REGNUM:
2009 return SIM_SH_BANK_MACL_REGNUM;
2010 case GBRB_REGNUM:
2011 return SIM_SH_BANK_GBR_REGNUM;
2012 case PRB_REGNUM:
2013 return SIM_SH_BANK_PR_REGNUM;
2014 case IVNB_REGNUM:
2015 return SIM_SH_BANK_IVN_REGNUM;
2016 case MACHB_REGNUM:
2017 return SIM_SH_BANK_MACH_REGNUM;
2018 default:
2019 break;
2020 }
2021 return legacy_register_sim_regno (nr);
2022 }
2023
2024 static struct sh_frame_cache *
2025 sh_alloc_frame_cache (void)
2026 {
2027 struct sh_frame_cache *cache;
2028 int i;
2029
2030 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2031
2032 /* Base address. */
2033 cache->base = 0;
2034 cache->saved_sp = 0;
2035 cache->sp_offset = 0;
2036 cache->pc = 0;
2037
2038 /* Frameless until proven otherwise. */
2039 cache->uses_fp = 0;
2040
2041 /* Saved registers. We initialize these to -1 since zero is a valid
2042 offset (that's where fp is supposed to be stored). */
2043 for (i = 0; i < SH_NUM_REGS; i++)
2044 {
2045 cache->saved_regs[i] = -1;
2046 }
2047
2048 return cache;
2049 }
2050
2051 static struct sh_frame_cache *
2052 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2053 {
2054 struct sh_frame_cache *cache;
2055 CORE_ADDR current_pc;
2056 int i;
2057
2058 if (*this_cache)
2059 return *this_cache;
2060
2061 cache = sh_alloc_frame_cache ();
2062 *this_cache = cache;
2063
2064 /* In principle, for normal frames, fp holds the frame pointer,
2065 which holds the base address for the current stack frame.
2066 However, for functions that don't need it, the frame pointer is
2067 optional. For these "frameless" functions the frame pointer is
2068 actually the frame pointer of the calling frame. */
2069 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2070 if (cache->base == 0)
2071 return cache;
2072
2073 cache->pc = frame_func_unwind (next_frame);
2074 current_pc = frame_pc_unwind (next_frame);
2075 if (cache->pc != 0)
2076 sh_analyze_prologue (cache->pc, current_pc, cache);
2077
2078 if (!cache->uses_fp)
2079 {
2080 /* We didn't find a valid frame, which means that CACHE->base
2081 currently holds the frame pointer for our calling frame. If
2082 we're at the start of a function, or somewhere half-way its
2083 prologue, the function's frame probably hasn't been fully
2084 setup yet. Try to reconstruct the base address for the stack
2085 frame by looking at the stack pointer. For truly "frameless"
2086 functions this might work too. */
2087 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2088 }
2089
2090 /* Now that we have the base address for the stack frame we can
2091 calculate the value of sp in the calling frame. */
2092 cache->saved_sp = cache->base + cache->sp_offset;
2093
2094 /* Adjust all the saved registers such that they contain addresses
2095 instead of offsets. */
2096 for (i = 0; i < SH_NUM_REGS; i++)
2097 if (cache->saved_regs[i] != -1)
2098 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2099
2100 return cache;
2101 }
2102
2103 static void
2104 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2105 int regnum, int *optimizedp,
2106 enum lval_type *lvalp, CORE_ADDR *addrp,
2107 int *realnump, gdb_byte *valuep)
2108 {
2109 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2110
2111 gdb_assert (regnum >= 0);
2112
2113 if (regnum == SP_REGNUM && cache->saved_sp)
2114 {
2115 *optimizedp = 0;
2116 *lvalp = not_lval;
2117 *addrp = 0;
2118 *realnump = -1;
2119 if (valuep)
2120 {
2121 /* Store the value. */
2122 store_unsigned_integer (valuep, 4, cache->saved_sp);
2123 }
2124 return;
2125 }
2126
2127 /* The PC of the previous frame is stored in the PR register of
2128 the current frame. Frob regnum so that we pull the value from
2129 the correct place. */
2130 if (regnum == PC_REGNUM)
2131 regnum = PR_REGNUM;
2132
2133 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2134 {
2135 *optimizedp = 0;
2136 *lvalp = lval_memory;
2137 *addrp = cache->saved_regs[regnum];
2138 *realnump = -1;
2139 if (valuep)
2140 {
2141 /* Read the value in from memory. */
2142 read_memory (*addrp, valuep,
2143 register_size (current_gdbarch, regnum));
2144 }
2145 return;
2146 }
2147
2148 *optimizedp = 0;
2149 *lvalp = lval_register;
2150 *addrp = 0;
2151 *realnump = regnum;
2152 if (valuep)
2153 frame_unwind_register (next_frame, (*realnump), valuep);
2154 }
2155
2156 static void
2157 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2158 struct frame_id *this_id)
2159 {
2160 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2161
2162 /* This marks the outermost frame. */
2163 if (cache->base == 0)
2164 return;
2165
2166 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2167 }
2168
2169 static const struct frame_unwind sh_frame_unwind = {
2170 NORMAL_FRAME,
2171 sh_frame_this_id,
2172 sh_frame_prev_register
2173 };
2174
2175 static const struct frame_unwind *
2176 sh_frame_sniffer (struct frame_info *next_frame)
2177 {
2178 return &sh_frame_unwind;
2179 }
2180
2181 static CORE_ADDR
2182 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2183 {
2184 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2185 }
2186
2187 static CORE_ADDR
2188 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2189 {
2190 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2191 }
2192
2193 static struct frame_id
2194 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2195 {
2196 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2197 frame_pc_unwind (next_frame));
2198 }
2199
2200 static CORE_ADDR
2201 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2202 {
2203 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2204
2205 return cache->base;
2206 }
2207
2208 static const struct frame_base sh_frame_base = {
2209 &sh_frame_unwind,
2210 sh_frame_base_address,
2211 sh_frame_base_address,
2212 sh_frame_base_address
2213 };
2214
2215 /* The epilogue is defined here as the area at the end of a function,
2216 either on the `ret' instruction itself or after an instruction which
2217 destroys the function's stack frame. */
2218 static int
2219 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2220 {
2221 CORE_ADDR func_addr = 0, func_end = 0;
2222
2223 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2224 {
2225 ULONGEST inst;
2226 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2227 for a nop and some fixed data (e.g. big offsets) which are
2228 unfortunately also treated as part of the function (which
2229 means, they are below func_end. */
2230 CORE_ADDR addr = func_end - 28;
2231 if (addr < func_addr + 4)
2232 addr = func_addr + 4;
2233 if (pc < addr)
2234 return 0;
2235
2236 /* First search forward until hitting an rts. */
2237 while (addr < func_end
2238 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2239 addr += 2;
2240 if (addr >= func_end)
2241 return 0;
2242
2243 /* At this point we should find a mov.l @r15+,r14 instruction,
2244 either before or after the rts. If not, then the function has
2245 probably no "normal" epilogue and we bail out here. */
2246 inst = read_memory_unsigned_integer (addr - 2, 2);
2247 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2248 addr -= 2;
2249 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2250 return 0;
2251
2252 inst = read_memory_unsigned_integer (addr - 2, 2);
2253
2254 /* Step over possible lds.l @r15+,macl. */
2255 if (IS_MACL_LDS (inst))
2256 {
2257 addr -= 2;
2258 inst = read_memory_unsigned_integer (addr - 2, 2);
2259 }
2260
2261 /* Step over possible lds.l @r15+,pr. */
2262 if (IS_LDS (inst))
2263 {
2264 addr -= 2;
2265 inst = read_memory_unsigned_integer (addr - 2, 2);
2266 }
2267
2268 /* Step over possible mov r14,r15. */
2269 if (IS_MOV_FP_SP (inst))
2270 {
2271 addr -= 2;
2272 inst = read_memory_unsigned_integer (addr - 2, 2);
2273 }
2274
2275 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2276 instructions. */
2277 while (addr > func_addr + 4
2278 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2279 {
2280 addr -= 2;
2281 inst = read_memory_unsigned_integer (addr - 2, 2);
2282 }
2283
2284 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2285 That's allowed for the epilogue. */
2286 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2287 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2288 && addr > func_addr + 6
2289 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2290 addr -= 4;
2291
2292 if (pc >= addr)
2293 return 1;
2294 }
2295 return 0;
2296 }
2297 \f
2298
2299 static struct gdbarch *
2300 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2301 {
2302 struct gdbarch *gdbarch;
2303
2304 sh_show_regs = sh_generic_show_regs;
2305 switch (info.bfd_arch_info->mach)
2306 {
2307 case bfd_mach_sh2e:
2308 sh_show_regs = sh2e_show_regs;
2309 break;
2310 case bfd_mach_sh2a:
2311 sh_show_regs = sh2a_show_regs;
2312 break;
2313 case bfd_mach_sh2a_nofpu:
2314 sh_show_regs = sh2a_nofpu_show_regs;
2315 break;
2316 case bfd_mach_sh_dsp:
2317 sh_show_regs = sh_dsp_show_regs;
2318 break;
2319
2320 case bfd_mach_sh3:
2321 sh_show_regs = sh3_show_regs;
2322 break;
2323
2324 case bfd_mach_sh3e:
2325 sh_show_regs = sh3e_show_regs;
2326 break;
2327
2328 case bfd_mach_sh3_dsp:
2329 case bfd_mach_sh4al_dsp:
2330 sh_show_regs = sh3_dsp_show_regs;
2331 break;
2332
2333 case bfd_mach_sh4:
2334 case bfd_mach_sh4a:
2335 sh_show_regs = sh4_show_regs;
2336 break;
2337
2338 case bfd_mach_sh4_nofpu:
2339 case bfd_mach_sh4a_nofpu:
2340 sh_show_regs = sh4_nofpu_show_regs;
2341 break;
2342
2343 case bfd_mach_sh5:
2344 sh_show_regs = sh64_show_regs;
2345 /* SH5 is handled entirely in sh64-tdep.c */
2346 return sh64_gdbarch_init (info, arches);
2347 }
2348
2349 /* If there is already a candidate, use it. */
2350 arches = gdbarch_list_lookup_by_info (arches, &info);
2351 if (arches != NULL)
2352 return arches->gdbarch;
2353
2354 /* None found, create a new architecture from the information
2355 provided. */
2356 gdbarch = gdbarch_alloc (&info, NULL);
2357
2358 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2359 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2360 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2361 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2362 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2363 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2364 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2365 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2366
2367 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2368 set_gdbarch_sp_regnum (gdbarch, 15);
2369 set_gdbarch_pc_regnum (gdbarch, 16);
2370 set_gdbarch_fp0_regnum (gdbarch, -1);
2371 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2372
2373 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2374
2375 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2376
2377 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2378 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2379
2380 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2381
2382 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2383 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2384 sh_extract_struct_value_address);
2385
2386 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2387 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2388
2389 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2390
2391 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2392
2393 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2394 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2395 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2396 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2397 frame_base_set_default (gdbarch, &sh_frame_base);
2398
2399 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2400
2401 switch (info.bfd_arch_info->mach)
2402 {
2403 case bfd_mach_sh:
2404 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2405 break;
2406
2407 case bfd_mach_sh2:
2408 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2409 break;
2410
2411 case bfd_mach_sh2e:
2412 /* doubles on sh2e and sh3e are actually 4 byte. */
2413 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2414
2415 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2416 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2417 set_gdbarch_fp0_regnum (gdbarch, 25);
2418 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2419 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2420 break;
2421
2422 case bfd_mach_sh2a:
2423 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2424 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2425 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2426
2427 set_gdbarch_fp0_regnum (gdbarch, 25);
2428 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2429 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2430 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2431 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2432 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2433 break;
2434
2435 case bfd_mach_sh2a_nofpu:
2436 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2437 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2438
2439 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2440 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2441 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2442 break;
2443
2444 case bfd_mach_sh_dsp:
2445 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2446 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2447 break;
2448
2449 case bfd_mach_sh3:
2450 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2451 break;
2452
2453 case bfd_mach_sh3e:
2454 /* doubles on sh2e and sh3e are actually 4 byte. */
2455 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2456
2457 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2458 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2459 set_gdbarch_fp0_regnum (gdbarch, 25);
2460 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2461 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2462 break;
2463
2464 case bfd_mach_sh3_dsp:
2465 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2466 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2467 break;
2468
2469 case bfd_mach_sh4:
2470 case bfd_mach_sh4a:
2471 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2472 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2473 set_gdbarch_fp0_regnum (gdbarch, 25);
2474 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2475 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2476 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2477 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2478 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2479 break;
2480
2481 case bfd_mach_sh4_nofpu:
2482 case bfd_mach_sh4a_nofpu:
2483 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2484 break;
2485
2486 case bfd_mach_sh4al_dsp:
2487 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2488 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2489 break;
2490
2491 default:
2492 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2493 break;
2494 }
2495
2496 /* Hook in ABI-specific overrides, if they have been registered. */
2497 gdbarch_init_osabi (info, gdbarch);
2498
2499 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2500 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2501
2502 return gdbarch;
2503 }
2504
2505 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2506
2507 void
2508 _initialize_sh_tdep (void)
2509 {
2510 struct cmd_list_element *c;
2511
2512 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2513
2514 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2515 }
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