gdb/testsuite/gdb.arch/vsx-regs.exp

   1 # Copyright (C) 2008-2018 Free Software Foundation, Inc.
   2 #
   3 # This program is free software; you can redistribute it and/or modify
   4 # it under the terms of the GNU General Public License as published by
   5 # the Free Software Foundation; either version 3 of the License, or
   6 # (at your option) any later version.
   7 #
   8 # This program is distributed in the hope that it will be useful,
   9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 # GNU General Public License for more details.
  12 #
  13 # You should have received a copy of the GNU General Public License
  14 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 #
  16
  17 #
  18 # Test the use of VSX registers, for Powerpc.
  19 #
  20
  21
  22 if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
  23     verbose "Skipping vsx register tests."
  24     return
  25 }
  26
  27 standard_testfile
  28
  29 set compile_flags {debug nowarnings quiet}
  30 if [get_compiler_info] {
  31     warning "get_compiler failed"
  32     return -1
  33 }
  34
  35 if [test_compiler_info gcc*] {
  36     set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
  37 } elseif [test_compiler_info xlc*] {
  38     set compile_flags "$compile_flags additional_flags=-qaltivec"
  39 } else {
  40     warning "unknown compiler"
  41     return -1
  42 }
  43
  44 if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
  45      untested "failed to compile"
  46      return -1
  47 }
  48
  49 gdb_start
  50 gdb_reinitialize_dir $srcdir/$subdir
  51 gdb_load ${binfile}
  52
  53 # Run to `main' where we begin our tests.
  54
  55 if ![runto_main] then {
  56     gdb_suppress_tests
  57 }
  58
  59 set endianness [get_endianness]
  60
  61 # Data sets used throughout the test
  62
  63 if {$endianness == "big"} {
  64     set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
  65
  66     set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  67
  68     set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
  69
  70     set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
  71
  72     set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  73
  74     set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  75 } else {
  76     set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
  77
  78     set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
  79
  80     set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
  81
  82     set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
  83
  84     set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
  85
  86     set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
  87 }
  88
  89 set float_register ".raw 0xdeadbeefdeadbeef."
  90
  91 # First run the F0~F31/VS0~VS31 tests
  92
  93 # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
  94 for {set i 0} {$i < 32} {incr i 1} {
  95     gdb_test_no_output "set \$f$i = 1\.3"
  96 }
  97
  98 for {set i 0} {$i < 32} {incr i 1} {
  99     gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
 100 }
 101
 102 # 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
 103 for {set i 0} {$i < 32} {incr i 1} {
 104         for {set j 0} {$j < 4} {incr j 1} {
 105            gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
 106         }
 107 }
 108
 109 for {set i 0} {$i < 32} {incr i 1} {
 110     gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
 111 }
 112
 113 for {set i 0} {$i < 32} {incr i 1} {
 114     gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
 115 }
 116
 117 # Now run the VR0~VR31/VS32~VS63 tests
 118
 119 # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
 120 for {set i 0} {$i < 32} {incr i 1} {
 121         for {set j 0} {$j < 4} {incr j 1} {
 122            gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
 123         }
 124 }
 125
 126 for {set i 32} {$i < 64} {incr i 1} {
 127     gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
 128 }
 129 # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
 130 for {set i 32} {$i < 64} {incr i 1} {
 131         for {set j 0} {$j < 4} {incr j 1} {
 132            gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
 133         }
 134 }
 135
 136 for {set i 0} {$i < 32} {incr i 1} {
 137     gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
 138 }
 139
 140 # Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
 141 # below because then we'll have more interesting register values to verify
 142 # later when loading the core file (i.e., different register values for different
 143 # vector register banks).
 144
 145 set corefile [standard_output_file vsx-core.test]
 146 set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"]
 147
 148 # Now run the F32~F63/VR0~VR31 tests.
 149
 150 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
 151 for {set i 32} {$i < 64} {incr i 1} {
 152     gdb_test_no_output "set \$f$i = 1\.3"
 153 }
 154
 155 for {set i 0} {$i < 32} {incr i 1} {
 156     gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
 157 }
 158
 159 # 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
 160 for {set i 0} {$i < 32} {incr i 1} {
 161         for {set j 0} {$j < 4} {incr j 1} {
 162            gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
 163         }
 164 }
 165
 166 for {set i 32} {$i < 64} {incr i 1} {
 167     gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
 168 }
 169
 170 for {set i 0} {$i < 32} {incr i 1} {
 171     gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
 172 }
 173
 174 # Test reading the core file.
 175
 176 if {!$core_supported} {
 177   return -1
 178 }
 179
 180 gdb_exit
 181 gdb_start
 182 gdb_reinitialize_dir $srcdir/$subdir
 183 gdb_load ${binfile}
 184
 185 set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"]
 186 if { $core_loaded == -1 } {
 187     # No use proceeding from here.
 188     return
 189 }
 190
 191 for {set i 0} {$i < 32} {incr i 1} {
 192     gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file"
 193 }
 194
 195 for {set i 32} {$i < 64} {incr i 1} {
 196     gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file"
 197 }