1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static target_desc_up tdesc_amd64_linux_no_xml
;
53 static target_desc_up tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char xmltarget_i386_linux_no_xml
[] = "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char xmltarget_amd64_linux_no_xml
[] = "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 const regs_info
*get_regs_info () override
;
105 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
107 bool supports_z_point_type (char z_type
) override
;
109 void process_qsupported (gdb::array_view
<const char * const> features
) override
;
111 bool supports_tracepoints () override
;
113 bool supports_fast_tracepoints () override
;
115 int install_fast_tracepoint_jump_pad
116 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
117 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
118 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
119 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
120 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
123 int get_min_fast_tracepoint_insn_len () override
;
125 struct emit_ops
*emit_ops () override
;
127 int get_ipa_tdesc_idx () override
;
131 void low_arch_setup () override
;
133 bool low_cannot_fetch_register (int regno
) override
;
135 bool low_cannot_store_register (int regno
) override
;
137 bool low_supports_breakpoints () override
;
139 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
141 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
143 int low_decr_pc_after_break () override
;
145 bool low_breakpoint_at (CORE_ADDR pc
) override
;
147 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
148 int size
, raw_breakpoint
*bp
) override
;
150 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
151 int size
, raw_breakpoint
*bp
) override
;
153 bool low_stopped_by_watchpoint () override
;
155 CORE_ADDR
low_stopped_data_address () override
;
157 /* collect_ptrace_register/supply_ptrace_register are not needed in the
158 native i386 case (no registers smaller than an xfer unit), and are not
159 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
161 /* Need to fix up i386 siginfo if host is amd64. */
162 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
163 int direction
) override
;
165 arch_process_info
*low_new_process () override
;
167 void low_delete_process (arch_process_info
*info
) override
;
169 void low_new_thread (lwp_info
*) override
;
171 void low_delete_thread (arch_lwp_info
*) override
;
173 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
175 void low_prepare_to_resume (lwp_info
*lwp
) override
;
177 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
179 bool low_supports_range_stepping () override
;
181 bool low_supports_catch_syscall () override
;
183 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
187 /* Update all the target description of all processes; a new GDB
188 connected, and it may or not support xml target descriptions. */
189 void update_xmltarget ();
192 /* The singleton target ops object. */
194 static x86_target the_x86_target
;
196 /* Per-process arch-specific data we want to keep. */
198 struct arch_process_info
200 struct x86_debug_reg_state debug_reg_state
;
205 /* Mapping between the general-purpose registers in `struct user'
206 format and GDB's register array layout.
207 Note that the transfer layout uses 64-bit regs. */
208 static /*const*/ int i386_regmap
[] =
210 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
211 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
212 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
213 DS
* 8, ES
* 8, FS
* 8, GS
* 8
216 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
218 /* So code below doesn't have to care, i386 or amd64. */
219 #define ORIG_EAX ORIG_RAX
222 static const int x86_64_regmap
[] =
224 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
225 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
226 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
227 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
228 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
229 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
230 -1, -1, -1, -1, -1, -1, -1, -1,
231 -1, -1, -1, -1, -1, -1, -1, -1,
232 -1, -1, -1, -1, -1, -1, -1, -1,
234 -1, -1, -1, -1, -1, -1, -1, -1,
237 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
238 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
239 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
240 -1, -1, -1, -1, -1, -1, -1, -1,
241 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
242 -1, -1, -1, -1, -1, -1, -1, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
244 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
245 -1, -1, -1, -1, -1, -1, -1, -1,
246 -1, -1, -1, -1, -1, -1, -1, -1,
247 -1, -1, -1, -1, -1, -1, -1, -1,
251 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
252 #define X86_64_USER_REGS (GS + 1)
254 #else /* ! __x86_64__ */
256 /* Mapping between the general-purpose registers in `struct user'
257 format and GDB's register array layout. */
258 static /*const*/ int i386_regmap
[] =
260 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
261 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
262 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
263 DS
* 4, ES
* 4, FS
* 4, GS
* 4
266 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
274 /* Returns true if the current inferior belongs to a x86-64 process,
278 is_64bit_tdesc (void)
280 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
282 return register_size (regcache
->tdesc
, 0) == 8;
288 /* Called by libthread_db. */
291 ps_get_thread_area (struct ps_prochandle
*ph
,
292 lwpid_t lwpid
, int idx
, void **base
)
295 int use_64bit
= is_64bit_tdesc ();
302 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
306 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
317 unsigned int desc
[4];
319 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
320 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
323 /* Ensure we properly extend the value to 64-bits for x86_64. */
324 *base
= (void *) (uintptr_t) desc
[1];
329 /* Get the thread area address. This is used to recognize which
330 thread is which when tracing with the in-process agent library. We
331 don't read anything from the address, and treat it as opaque; it's
332 the address itself that we assume is unique per-thread. */
335 x86_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
338 int use_64bit
= is_64bit_tdesc ();
343 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
345 *addr
= (CORE_ADDR
) (uintptr_t) base
;
354 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
355 struct thread_info
*thr
= get_lwp_thread (lwp
);
356 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
357 unsigned int desc
[4];
359 const int reg_thread_area
= 3; /* bits to scale down register value. */
362 collect_register_by_name (regcache
, "gs", &gs
);
364 idx
= gs
>> reg_thread_area
;
366 if (ptrace (PTRACE_GET_THREAD_AREA
,
368 (void *) (long) idx
, (unsigned long) &desc
) < 0)
379 x86_target::low_cannot_store_register (int regno
)
382 if (is_64bit_tdesc ())
386 return regno
>= I386_NUM_REGS
;
390 x86_target::low_cannot_fetch_register (int regno
)
393 if (is_64bit_tdesc ())
397 return regno
>= I386_NUM_REGS
;
401 collect_register_i386 (struct regcache
*regcache
, int regno
, void *buf
)
403 collect_register (regcache
, regno
, buf
);
406 /* In case of x86_64 -m32, collect_register only writes 4 bytes, but the
407 space reserved in buf for the register is 8 bytes. Make sure the entire
408 reserved space is initialized. */
410 gdb_assert (register_size (regcache
->tdesc
, regno
) == 4);
414 /* Sign extend EAX value to avoid potential syscall restart
417 See amd64_linux_collect_native_gregset() in
418 gdb/amd64-linux-nat.c for a detailed explanation. */
419 *(int64_t *) buf
= *(int32_t *) buf
;
424 *(uint64_t *) buf
= *(uint32_t *) buf
;
430 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
435 if (register_size (regcache
->tdesc
, 0) == 8)
437 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
438 if (x86_64_regmap
[i
] != -1)
439 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
445 for (i
= 0; i
< I386_NUM_REGS
; i
++)
446 collect_register_i386 (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
448 /* Handle ORIG_EAX, which is not in i386_regmap. */
449 collect_register_i386 (regcache
, find_regno (regcache
->tdesc
, "orig_eax"),
450 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
454 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
459 if (register_size (regcache
->tdesc
, 0) == 8)
461 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
462 if (x86_64_regmap
[i
] != -1)
463 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
469 for (i
= 0; i
< I386_NUM_REGS
; i
++)
470 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
472 supply_register_by_name (regcache
, "orig_eax",
473 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
477 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
480 i387_cache_to_fxsave (regcache
, buf
);
482 i387_cache_to_fsave (regcache
, buf
);
487 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
490 i387_fxsave_to_cache (regcache
, buf
);
492 i387_fsave_to_cache (regcache
, buf
);
499 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
501 i387_cache_to_fxsave (regcache
, buf
);
505 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
507 i387_fxsave_to_cache (regcache
, buf
);
513 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
515 i387_cache_to_xsave (regcache
, buf
);
519 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
521 i387_xsave_to_cache (regcache
, buf
);
524 /* ??? The non-biarch i386 case stores all the i387 regs twice.
525 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
526 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
527 doesn't work. IWBN to avoid the duplication in the case where it
528 does work. Maybe the arch_setup routine could check whether it works
529 and update the supported regsets accordingly. */
531 static struct regset_info x86_regsets
[] =
533 #ifdef HAVE_PTRACE_GETREGS
534 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
536 x86_fill_gregset
, x86_store_gregset
},
537 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
538 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
540 # ifdef HAVE_PTRACE_GETFPXREGS
541 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
543 x86_fill_fpxregset
, x86_store_fpxregset
},
546 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
548 x86_fill_fpregset
, x86_store_fpregset
},
549 #endif /* HAVE_PTRACE_GETREGS */
554 x86_target::low_supports_breakpoints ()
560 x86_target::low_get_pc (regcache
*regcache
)
562 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
568 collect_register_by_name (regcache
, "rip", &pc
);
569 return (CORE_ADDR
) pc
;
575 collect_register_by_name (regcache
, "eip", &pc
);
576 return (CORE_ADDR
) pc
;
581 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
583 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
589 supply_register_by_name (regcache
, "rip", &newpc
);
595 supply_register_by_name (regcache
, "eip", &newpc
);
600 x86_target::low_decr_pc_after_break ()
606 static const gdb_byte x86_breakpoint
[] = { 0xCC };
607 #define x86_breakpoint_len 1
610 x86_target::low_breakpoint_at (CORE_ADDR pc
)
614 read_memory (pc
, &c
, 1);
621 /* Low-level function vector. */
622 struct x86_dr_low_type x86_dr_low
=
624 x86_linux_dr_set_control
,
625 x86_linux_dr_set_addr
,
626 x86_linux_dr_get_addr
,
627 x86_linux_dr_get_status
,
628 x86_linux_dr_get_control
,
632 /* Breakpoint/Watchpoint support. */
635 x86_target::supports_z_point_type (char z_type
)
641 case Z_PACKET_WRITE_WP
:
642 case Z_PACKET_ACCESS_WP
:
650 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
651 int size
, raw_breakpoint
*bp
)
653 struct process_info
*proc
= current_process ();
657 case raw_bkpt_type_hw
:
658 case raw_bkpt_type_write_wp
:
659 case raw_bkpt_type_access_wp
:
661 enum target_hw_bp_type hw_type
662 = raw_bkpt_type_to_target_hw_bp_type (type
);
663 struct x86_debug_reg_state
*state
664 = &proc
->priv
->arch_private
->debug_reg_state
;
666 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
676 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
677 int size
, raw_breakpoint
*bp
)
679 struct process_info
*proc
= current_process ();
683 case raw_bkpt_type_hw
:
684 case raw_bkpt_type_write_wp
:
685 case raw_bkpt_type_access_wp
:
687 enum target_hw_bp_type hw_type
688 = raw_bkpt_type_to_target_hw_bp_type (type
);
689 struct x86_debug_reg_state
*state
690 = &proc
->priv
->arch_private
->debug_reg_state
;
692 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
701 x86_target::low_stopped_by_watchpoint ()
703 struct process_info
*proc
= current_process ();
704 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
708 x86_target::low_stopped_data_address ()
710 struct process_info
*proc
= current_process ();
712 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
718 /* Called when a new process is created. */
721 x86_target::low_new_process ()
723 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
725 x86_low_init_dregs (&info
->debug_reg_state
);
730 /* Called when a process is being deleted. */
733 x86_target::low_delete_process (arch_process_info
*info
)
739 x86_target::low_new_thread (lwp_info
*lwp
)
741 /* This comes from nat/. */
742 x86_linux_new_thread (lwp
);
746 x86_target::low_delete_thread (arch_lwp_info
*alwp
)
748 /* This comes from nat/. */
749 x86_linux_delete_thread (alwp
);
752 /* Target routine for new_fork. */
755 x86_target::low_new_fork (process_info
*parent
, process_info
*child
)
757 /* These are allocated by linux_add_process. */
758 gdb_assert (parent
->priv
!= NULL
759 && parent
->priv
->arch_private
!= NULL
);
760 gdb_assert (child
->priv
!= NULL
761 && child
->priv
->arch_private
!= NULL
);
763 /* Linux kernel before 2.6.33 commit
764 72f674d203cd230426437cdcf7dd6f681dad8b0d
765 will inherit hardware debug registers from parent
766 on fork/vfork/clone. Newer Linux kernels create such tasks with
767 zeroed debug registers.
769 GDB core assumes the child inherits the watchpoints/hw
770 breakpoints of the parent, and will remove them all from the
771 forked off process. Copy the debug registers mirrors into the
772 new process so that all breakpoints and watchpoints can be
773 removed together. The debug registers mirror will become zeroed
774 in the end before detaching the forked off process, thus making
775 this compatible with older Linux kernels too. */
777 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
781 x86_target::low_prepare_to_resume (lwp_info
*lwp
)
783 /* This comes from nat/. */
784 x86_linux_prepare_to_resume (lwp
);
787 /* See nat/x86-dregs.h. */
789 struct x86_debug_reg_state
*
790 x86_debug_reg_state (pid_t pid
)
792 struct process_info
*proc
= find_process_pid (pid
);
794 return &proc
->priv
->arch_private
->debug_reg_state
;
797 /* When GDBSERVER is built as a 64-bit application on linux, the
798 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
799 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
800 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
801 conversion in-place ourselves. */
803 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
804 layout of the inferiors' architecture. Returns true if any
805 conversion was done; false otherwise. If DIRECTION is 1, then copy
806 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
810 x86_target::low_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
813 unsigned int machine
;
814 int tid
= lwpid_of (current_thread
);
815 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
817 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
818 if (!is_64bit_tdesc ())
819 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
821 /* No fixup for native x32 GDB. */
822 else if (!is_elf64
&& sizeof (void *) == 8)
823 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
832 /* Format of XSAVE extended state is:
836 sw_usable_bytes[464..511]
837 xstate_hdr_bytes[512..575]
842 Same memory layout will be used for the coredump NT_X86_XSTATE
843 representing the XSAVE extended state registers.
845 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
846 extended state mask, which is the same as the extended control register
847 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
848 together with the mask saved in the xstate_hdr_bytes to determine what
849 states the processor/OS supports and what state, used or initialized,
850 the process/thread is in. */
851 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
853 /* Does the current host support the GETFPXREGS request? The header
854 file may or may not define it, and even if it is defined, the
855 kernel will return EIO if it's running on a pre-SSE processor. */
856 int have_ptrace_getfpxregs
=
857 #ifdef HAVE_PTRACE_GETFPXREGS
864 /* Get Linux/x86 target description from running target. */
866 static const struct target_desc
*
867 x86_linux_read_description (void)
869 unsigned int machine
;
873 static uint64_t xcr0
;
874 struct regset_info
*regset
;
876 tid
= lwpid_of (current_thread
);
878 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
880 if (sizeof (void *) == 4)
883 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
885 else if (machine
== EM_X86_64
)
886 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
890 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
891 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
893 elf_fpxregset_t fpxregs
;
895 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
897 have_ptrace_getfpxregs
= 0;
898 have_ptrace_getregset
= 0;
899 return i386_linux_read_description (X86_XSTATE_X87
);
902 have_ptrace_getfpxregs
= 1;
908 x86_xcr0
= X86_XSTATE_SSE_MASK
;
912 if (machine
== EM_X86_64
)
913 return tdesc_amd64_linux_no_xml
.get ();
916 return tdesc_i386_linux_no_xml
.get ();
919 if (have_ptrace_getregset
== -1)
921 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
924 iov
.iov_base
= xstateregs
;
925 iov
.iov_len
= sizeof (xstateregs
);
927 /* Check if PTRACE_GETREGSET works. */
928 if (ptrace (PTRACE_GETREGSET
, tid
,
929 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
930 have_ptrace_getregset
= 0;
933 have_ptrace_getregset
= 1;
935 /* Get XCR0 from XSAVE extended state. */
936 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
937 / sizeof (uint64_t))];
939 /* Use PTRACE_GETREGSET if it is available. */
940 for (regset
= x86_regsets
;
941 regset
->fill_function
!= NULL
; regset
++)
942 if (regset
->get_request
== PTRACE_GETREGSET
)
943 regset
->size
= X86_XSTATE_SIZE (xcr0
);
944 else if (regset
->type
!= GENERAL_REGS
)
949 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
950 xcr0_features
= (have_ptrace_getregset
951 && (xcr0
& X86_XSTATE_ALL_MASK
));
956 if (machine
== EM_X86_64
)
959 const target_desc
*tdesc
= NULL
;
963 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
968 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
974 const target_desc
*tdesc
= NULL
;
977 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
980 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
985 gdb_assert_not_reached ("failed to return tdesc");
988 /* Update all the target description of all processes; a new GDB
989 connected, and it may or not support xml target descriptions. */
992 x86_target::update_xmltarget ()
994 scoped_restore_current_thread restore_thread
;
996 /* Before changing the register cache's internal layout, flush the
997 contents of the current valid caches back to the threads, and
998 release the current regcache objects. */
1001 for_each_process ([this] (process_info
*proc
) {
1002 int pid
= proc
->pid
;
1004 /* Look up any thread of this process. */
1005 switch_to_thread (find_any_thread_of_pid (pid
));
1011 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
1012 PTRACE_GETREGSET. */
1015 x86_target::process_qsupported (gdb::array_view
<const char * const> features
)
1017 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1018 with "i386" in qSupported query, it supports x86 XML target
1022 for (const char *feature
: features
)
1024 if (startswith (feature
, "xmlRegisters="))
1026 char *copy
= xstrdup (feature
+ 13);
1029 for (char *p
= strtok_r (copy
, ",", &saveptr
);
1031 p
= strtok_r (NULL
, ",", &saveptr
))
1033 if (strcmp (p
, "i386") == 0)
1044 update_xmltarget ();
1047 /* Common for x86/x86-64. */
1049 static struct regsets_info x86_regsets_info
=
1051 x86_regsets
, /* regsets */
1052 0, /* num_regsets */
1053 NULL
, /* disabled_regsets */
1057 static struct regs_info amd64_linux_regs_info
=
1059 NULL
, /* regset_bitmap */
1060 NULL
, /* usrregs_info */
1064 static struct usrregs_info i386_linux_usrregs_info
=
1070 static struct regs_info i386_linux_regs_info
=
1072 NULL
, /* regset_bitmap */
1073 &i386_linux_usrregs_info
,
1078 x86_target::get_regs_info ()
1081 if (is_64bit_tdesc ())
1082 return &amd64_linux_regs_info
;
1085 return &i386_linux_regs_info
;
1088 /* Initialize the target description for the architecture of the
1092 x86_target::low_arch_setup ()
1094 current_process ()->tdesc
= x86_linux_read_description ();
1098 x86_target::low_supports_catch_syscall ()
1103 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1104 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1107 x86_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
1109 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1115 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1116 *sysno
= (int) l_sysno
;
1119 collect_register_by_name (regcache
, "orig_eax", sysno
);
1123 x86_target::supports_tracepoints ()
1129 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1131 target_write_memory (*to
, buf
, len
);
1136 push_opcode (unsigned char *buf
, const char *op
)
1138 unsigned char *buf_org
= buf
;
1143 unsigned long ul
= strtoul (op
, &endptr
, 16);
1152 return buf
- buf_org
;
1157 /* Build a jump pad that saves registers and calls a collection
1158 function. Writes a jump instruction to the jump pad to
1159 JJUMPAD_INSN. The caller is responsible to write it in at the
1160 tracepoint address. */
1163 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1164 CORE_ADDR collector
,
1167 CORE_ADDR
*jump_entry
,
1168 CORE_ADDR
*trampoline
,
1169 ULONGEST
*trampoline_size
,
1170 unsigned char *jjump_pad_insn
,
1171 ULONGEST
*jjump_pad_insn_size
,
1172 CORE_ADDR
*adjusted_insn_addr
,
1173 CORE_ADDR
*adjusted_insn_addr_end
,
1176 unsigned char buf
[40];
1180 CORE_ADDR buildaddr
= *jump_entry
;
1182 /* Build the jump pad. */
1184 /* First, do tracepoint data collection. Save registers. */
1186 /* Need to ensure stack pointer saved first. */
1187 buf
[i
++] = 0x54; /* push %rsp */
1188 buf
[i
++] = 0x55; /* push %rbp */
1189 buf
[i
++] = 0x57; /* push %rdi */
1190 buf
[i
++] = 0x56; /* push %rsi */
1191 buf
[i
++] = 0x52; /* push %rdx */
1192 buf
[i
++] = 0x51; /* push %rcx */
1193 buf
[i
++] = 0x53; /* push %rbx */
1194 buf
[i
++] = 0x50; /* push %rax */
1195 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1196 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1197 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1198 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1199 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1200 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1201 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1202 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1203 buf
[i
++] = 0x9c; /* pushfq */
1204 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1206 memcpy (buf
+ i
, &tpaddr
, 8);
1208 buf
[i
++] = 0x57; /* push %rdi */
1209 append_insns (&buildaddr
, i
, buf
);
1211 /* Stack space for the collecting_t object. */
1213 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1214 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1215 memcpy (buf
+ i
, &tpoint
, 8);
1217 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1218 i
+= push_opcode (&buf
[i
],
1219 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1220 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1221 append_insns (&buildaddr
, i
, buf
);
1225 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1226 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1228 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1229 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1230 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1231 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1232 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1233 append_insns (&buildaddr
, i
, buf
);
1235 /* Set up the gdb_collect call. */
1236 /* At this point, (stack pointer + 0x18) is the base of our saved
1240 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1241 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1243 /* tpoint address may be 64-bit wide. */
1244 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1245 memcpy (buf
+ i
, &tpoint
, 8);
1247 append_insns (&buildaddr
, i
, buf
);
1249 /* The collector function being in the shared library, may be
1250 >31-bits away off the jump pad. */
1252 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1253 memcpy (buf
+ i
, &collector
, 8);
1255 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1256 append_insns (&buildaddr
, i
, buf
);
1258 /* Clear the spin-lock. */
1260 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1261 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1262 memcpy (buf
+ i
, &lockaddr
, 8);
1264 append_insns (&buildaddr
, i
, buf
);
1266 /* Remove stack that had been used for the collect_t object. */
1268 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1269 append_insns (&buildaddr
, i
, buf
);
1271 /* Restore register state. */
1273 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1277 buf
[i
++] = 0x9d; /* popfq */
1278 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1279 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1280 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1281 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1282 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1283 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1284 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1285 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1286 buf
[i
++] = 0x58; /* pop %rax */
1287 buf
[i
++] = 0x5b; /* pop %rbx */
1288 buf
[i
++] = 0x59; /* pop %rcx */
1289 buf
[i
++] = 0x5a; /* pop %rdx */
1290 buf
[i
++] = 0x5e; /* pop %rsi */
1291 buf
[i
++] = 0x5f; /* pop %rdi */
1292 buf
[i
++] = 0x5d; /* pop %rbp */
1293 buf
[i
++] = 0x5c; /* pop %rsp */
1294 append_insns (&buildaddr
, i
, buf
);
1296 /* Now, adjust the original instruction to execute in the jump
1298 *adjusted_insn_addr
= buildaddr
;
1299 relocate_instruction (&buildaddr
, tpaddr
);
1300 *adjusted_insn_addr_end
= buildaddr
;
1302 /* Finally, write a jump back to the program. */
1304 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1305 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1308 "E.Jump back from jump pad too far from tracepoint "
1309 "(offset 0x%" PRIx64
" > int32).", loffset
);
1313 offset
= (int) loffset
;
1314 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1315 memcpy (buf
+ 1, &offset
, 4);
1316 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1318 /* The jump pad is now built. Wire in a jump to our jump pad. This
1319 is always done last (by our caller actually), so that we can
1320 install fast tracepoints with threads running. This relies on
1321 the agent's atomic write support. */
1322 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1323 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1326 "E.Jump pad too far from tracepoint "
1327 "(offset 0x%" PRIx64
" > int32).", loffset
);
1331 offset
= (int) loffset
;
1333 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1334 memcpy (buf
+ 1, &offset
, 4);
1335 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1336 *jjump_pad_insn_size
= sizeof (jump_insn
);
1338 /* Return the end address of our pad. */
1339 *jump_entry
= buildaddr
;
1344 #endif /* __x86_64__ */
1346 /* Build a jump pad that saves registers and calls a collection
1347 function. Writes a jump instruction to the jump pad to
1348 JJUMPAD_INSN. The caller is responsible to write it in at the
1349 tracepoint address. */
1352 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1353 CORE_ADDR collector
,
1356 CORE_ADDR
*jump_entry
,
1357 CORE_ADDR
*trampoline
,
1358 ULONGEST
*trampoline_size
,
1359 unsigned char *jjump_pad_insn
,
1360 ULONGEST
*jjump_pad_insn_size
,
1361 CORE_ADDR
*adjusted_insn_addr
,
1362 CORE_ADDR
*adjusted_insn_addr_end
,
1365 unsigned char buf
[0x100];
1367 CORE_ADDR buildaddr
= *jump_entry
;
1369 /* Build the jump pad. */
1371 /* First, do tracepoint data collection. Save registers. */
1373 buf
[i
++] = 0x60; /* pushad */
1374 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1375 *((int *)(buf
+ i
)) = (int) tpaddr
;
1377 buf
[i
++] = 0x9c; /* pushf */
1378 buf
[i
++] = 0x1e; /* push %ds */
1379 buf
[i
++] = 0x06; /* push %es */
1380 buf
[i
++] = 0x0f; /* push %fs */
1382 buf
[i
++] = 0x0f; /* push %gs */
1384 buf
[i
++] = 0x16; /* push %ss */
1385 buf
[i
++] = 0x0e; /* push %cs */
1386 append_insns (&buildaddr
, i
, buf
);
1388 /* Stack space for the collecting_t object. */
1390 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1392 /* Build the object. */
1393 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1394 memcpy (buf
+ i
, &tpoint
, 4);
1396 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1398 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1399 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1400 append_insns (&buildaddr
, i
, buf
);
1402 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1403 If we cared for it, this could be using xchg alternatively. */
1406 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1407 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1409 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1411 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1412 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1413 append_insns (&buildaddr
, i
, buf
);
1416 /* Set up arguments to the gdb_collect call. */
1418 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1419 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1420 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1421 append_insns (&buildaddr
, i
, buf
);
1424 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1425 append_insns (&buildaddr
, i
, buf
);
1428 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1429 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1431 append_insns (&buildaddr
, i
, buf
);
1433 buf
[0] = 0xe8; /* call <reladdr> */
1434 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1435 memcpy (buf
+ 1, &offset
, 4);
1436 append_insns (&buildaddr
, 5, buf
);
1437 /* Clean up after the call. */
1438 buf
[0] = 0x83; /* add $0x8,%esp */
1441 append_insns (&buildaddr
, 3, buf
);
1444 /* Clear the spin-lock. This would need the LOCK prefix on older
1447 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1448 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1449 memcpy (buf
+ i
, &lockaddr
, 4);
1451 append_insns (&buildaddr
, i
, buf
);
1454 /* Remove stack that had been used for the collect_t object. */
1456 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1457 append_insns (&buildaddr
, i
, buf
);
1460 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1463 buf
[i
++] = 0x17; /* pop %ss */
1464 buf
[i
++] = 0x0f; /* pop %gs */
1466 buf
[i
++] = 0x0f; /* pop %fs */
1468 buf
[i
++] = 0x07; /* pop %es */
1469 buf
[i
++] = 0x1f; /* pop %ds */
1470 buf
[i
++] = 0x9d; /* popf */
1471 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1474 buf
[i
++] = 0x61; /* popad */
1475 append_insns (&buildaddr
, i
, buf
);
1477 /* Now, adjust the original instruction to execute in the jump
1479 *adjusted_insn_addr
= buildaddr
;
1480 relocate_instruction (&buildaddr
, tpaddr
);
1481 *adjusted_insn_addr_end
= buildaddr
;
1483 /* Write the jump back to the program. */
1484 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1485 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1486 memcpy (buf
+ 1, &offset
, 4);
1487 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1489 /* The jump pad is now built. Wire in a jump to our jump pad. This
1490 is always done last (by our caller actually), so that we can
1491 install fast tracepoints with threads running. This relies on
1492 the agent's atomic write support. */
1495 /* Create a trampoline. */
1496 *trampoline_size
= sizeof (jump_insn
);
1497 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1499 /* No trampoline space available. */
1501 "E.Cannot allocate trampoline space needed for fast "
1502 "tracepoints on 4-byte instructions.");
1506 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1507 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1508 memcpy (buf
+ 1, &offset
, 4);
1509 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1511 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1512 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1513 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1514 memcpy (buf
+ 2, &offset
, 2);
1515 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1516 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1520 /* Else use a 32-bit relative jump instruction. */
1521 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1522 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1523 memcpy (buf
+ 1, &offset
, 4);
1524 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1525 *jjump_pad_insn_size
= sizeof (jump_insn
);
1528 /* Return the end address of our pad. */
1529 *jump_entry
= buildaddr
;
1535 x86_target::supports_fast_tracepoints ()
1541 x86_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1543 CORE_ADDR collector
,
1546 CORE_ADDR
*jump_entry
,
1547 CORE_ADDR
*trampoline
,
1548 ULONGEST
*trampoline_size
,
1549 unsigned char *jjump_pad_insn
,
1550 ULONGEST
*jjump_pad_insn_size
,
1551 CORE_ADDR
*adjusted_insn_addr
,
1552 CORE_ADDR
*adjusted_insn_addr_end
,
1556 if (is_64bit_tdesc ())
1557 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1558 collector
, lockaddr
,
1559 orig_size
, jump_entry
,
1560 trampoline
, trampoline_size
,
1562 jjump_pad_insn_size
,
1564 adjusted_insn_addr_end
,
1568 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1569 collector
, lockaddr
,
1570 orig_size
, jump_entry
,
1571 trampoline
, trampoline_size
,
1573 jjump_pad_insn_size
,
1575 adjusted_insn_addr_end
,
1579 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1583 x86_target::get_min_fast_tracepoint_insn_len ()
1585 static int warned_about_fast_tracepoints
= 0;
1588 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1589 used for fast tracepoints. */
1590 if (is_64bit_tdesc ())
1594 if (agent_loaded_p ())
1596 char errbuf
[IPA_BUFSIZ
];
1600 /* On x86, if trampolines are available, then 4-byte jump instructions
1601 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1602 with a 4-byte offset are used instead. */
1603 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1607 /* GDB has no channel to explain to user why a shorter fast
1608 tracepoint is not possible, but at least make GDBserver
1609 mention that something has gone awry. */
1610 if (!warned_about_fast_tracepoints
)
1612 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1613 warned_about_fast_tracepoints
= 1;
1620 /* Indicate that the minimum length is currently unknown since the IPA
1621 has not loaded yet. */
1627 add_insns (unsigned char *start
, int len
)
1629 CORE_ADDR buildaddr
= current_insn_ptr
;
1632 debug_printf ("Adding %d bytes of insn at %s\n",
1633 len
, paddress (buildaddr
));
1635 append_insns (&buildaddr
, len
, start
);
1636 current_insn_ptr
= buildaddr
;
1639 /* Our general strategy for emitting code is to avoid specifying raw
1640 bytes whenever possible, and instead copy a block of inline asm
1641 that is embedded in the function. This is a little messy, because
1642 we need to keep the compiler from discarding what looks like dead
1643 code, plus suppress various warnings. */
1645 #define EMIT_ASM(NAME, INSNS) \
1648 extern unsigned char start_ ## NAME, end_ ## NAME; \
1649 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1650 __asm__ ("jmp end_" #NAME "\n" \
1651 "\t" "start_" #NAME ":" \
1653 "\t" "end_" #NAME ":"); \
1658 #define EMIT_ASM32(NAME,INSNS) \
1661 extern unsigned char start_ ## NAME, end_ ## NAME; \
1662 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1663 __asm__ (".code32\n" \
1664 "\t" "jmp end_" #NAME "\n" \
1665 "\t" "start_" #NAME ":\n" \
1667 "\t" "end_" #NAME ":\n" \
1673 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1680 amd64_emit_prologue (void)
1682 EMIT_ASM (amd64_prologue
,
1684 "movq %rsp,%rbp\n\t"
1685 "sub $0x20,%rsp\n\t"
1686 "movq %rdi,-8(%rbp)\n\t"
1687 "movq %rsi,-16(%rbp)");
1692 amd64_emit_epilogue (void)
1694 EMIT_ASM (amd64_epilogue
,
1695 "movq -16(%rbp),%rdi\n\t"
1696 "movq %rax,(%rdi)\n\t"
1703 amd64_emit_add (void)
1705 EMIT_ASM (amd64_add
,
1706 "add (%rsp),%rax\n\t"
1707 "lea 0x8(%rsp),%rsp");
1711 amd64_emit_sub (void)
1713 EMIT_ASM (amd64_sub
,
1714 "sub %rax,(%rsp)\n\t"
1719 amd64_emit_mul (void)
1725 amd64_emit_lsh (void)
1731 amd64_emit_rsh_signed (void)
1737 amd64_emit_rsh_unsigned (void)
1743 amd64_emit_ext (int arg
)
1748 EMIT_ASM (amd64_ext_8
,
1754 EMIT_ASM (amd64_ext_16
,
1759 EMIT_ASM (amd64_ext_32
,
1768 amd64_emit_log_not (void)
1770 EMIT_ASM (amd64_log_not
,
1771 "test %rax,%rax\n\t"
1777 amd64_emit_bit_and (void)
1779 EMIT_ASM (amd64_and
,
1780 "and (%rsp),%rax\n\t"
1781 "lea 0x8(%rsp),%rsp");
1785 amd64_emit_bit_or (void)
1788 "or (%rsp),%rax\n\t"
1789 "lea 0x8(%rsp),%rsp");
1793 amd64_emit_bit_xor (void)
1795 EMIT_ASM (amd64_xor
,
1796 "xor (%rsp),%rax\n\t"
1797 "lea 0x8(%rsp),%rsp");
1801 amd64_emit_bit_not (void)
1803 EMIT_ASM (amd64_bit_not
,
1804 "xorq $0xffffffffffffffff,%rax");
1808 amd64_emit_equal (void)
1810 EMIT_ASM (amd64_equal
,
1811 "cmp %rax,(%rsp)\n\t"
1812 "je .Lamd64_equal_true\n\t"
1814 "jmp .Lamd64_equal_end\n\t"
1815 ".Lamd64_equal_true:\n\t"
1817 ".Lamd64_equal_end:\n\t"
1818 "lea 0x8(%rsp),%rsp");
1822 amd64_emit_less_signed (void)
1824 EMIT_ASM (amd64_less_signed
,
1825 "cmp %rax,(%rsp)\n\t"
1826 "jl .Lamd64_less_signed_true\n\t"
1828 "jmp .Lamd64_less_signed_end\n\t"
1829 ".Lamd64_less_signed_true:\n\t"
1831 ".Lamd64_less_signed_end:\n\t"
1832 "lea 0x8(%rsp),%rsp");
1836 amd64_emit_less_unsigned (void)
1838 EMIT_ASM (amd64_less_unsigned
,
1839 "cmp %rax,(%rsp)\n\t"
1840 "jb .Lamd64_less_unsigned_true\n\t"
1842 "jmp .Lamd64_less_unsigned_end\n\t"
1843 ".Lamd64_less_unsigned_true:\n\t"
1845 ".Lamd64_less_unsigned_end:\n\t"
1846 "lea 0x8(%rsp),%rsp");
1850 amd64_emit_ref (int size
)
1855 EMIT_ASM (amd64_ref1
,
1859 EMIT_ASM (amd64_ref2
,
1863 EMIT_ASM (amd64_ref4
,
1864 "movl (%rax),%eax");
1867 EMIT_ASM (amd64_ref8
,
1868 "movq (%rax),%rax");
1874 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1876 EMIT_ASM (amd64_if_goto
,
1880 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1888 amd64_emit_goto (int *offset_p
, int *size_p
)
1890 EMIT_ASM (amd64_goto
,
1891 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1899 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1901 int diff
= (to
- (from
+ size
));
1902 unsigned char buf
[sizeof (int)];
1910 memcpy (buf
, &diff
, sizeof (int));
1911 target_write_memory (from
, buf
, sizeof (int));
1915 amd64_emit_const (LONGEST num
)
1917 unsigned char buf
[16];
1919 CORE_ADDR buildaddr
= current_insn_ptr
;
1922 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1923 memcpy (&buf
[i
], &num
, sizeof (num
));
1925 append_insns (&buildaddr
, i
, buf
);
1926 current_insn_ptr
= buildaddr
;
1930 amd64_emit_call (CORE_ADDR fn
)
1932 unsigned char buf
[16];
1934 CORE_ADDR buildaddr
;
1937 /* The destination function being in the shared library, may be
1938 >31-bits away off the compiled code pad. */
1940 buildaddr
= current_insn_ptr
;
1942 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1946 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1948 /* Offset is too large for a call. Use callq, but that requires
1949 a register, so avoid it if possible. Use r10, since it is
1950 call-clobbered, we don't have to push/pop it. */
1951 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1953 memcpy (buf
+ i
, &fn
, 8);
1955 buf
[i
++] = 0xff; /* callq *%r10 */
1960 int offset32
= offset64
; /* we know we can't overflow here. */
1962 buf
[i
++] = 0xe8; /* call <reladdr> */
1963 memcpy (buf
+ i
, &offset32
, 4);
1967 append_insns (&buildaddr
, i
, buf
);
1968 current_insn_ptr
= buildaddr
;
1972 amd64_emit_reg (int reg
)
1974 unsigned char buf
[16];
1976 CORE_ADDR buildaddr
;
1978 /* Assume raw_regs is still in %rdi. */
1979 buildaddr
= current_insn_ptr
;
1981 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1982 memcpy (&buf
[i
], ®
, sizeof (reg
));
1984 append_insns (&buildaddr
, i
, buf
);
1985 current_insn_ptr
= buildaddr
;
1986 amd64_emit_call (get_raw_reg_func_addr ());
1990 amd64_emit_pop (void)
1992 EMIT_ASM (amd64_pop
,
1997 amd64_emit_stack_flush (void)
1999 EMIT_ASM (amd64_stack_flush
,
2004 amd64_emit_zero_ext (int arg
)
2009 EMIT_ASM (amd64_zero_ext_8
,
2013 EMIT_ASM (amd64_zero_ext_16
,
2014 "and $0xffff,%rax");
2017 EMIT_ASM (amd64_zero_ext_32
,
2018 "mov $0xffffffff,%rcx\n\t"
2027 amd64_emit_swap (void)
2029 EMIT_ASM (amd64_swap
,
2036 amd64_emit_stack_adjust (int n
)
2038 unsigned char buf
[16];
2040 CORE_ADDR buildaddr
= current_insn_ptr
;
2043 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
2047 /* This only handles adjustments up to 16, but we don't expect any more. */
2049 append_insns (&buildaddr
, i
, buf
);
2050 current_insn_ptr
= buildaddr
;
2053 /* FN's prototype is `LONGEST(*fn)(int)'. */
2056 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2058 unsigned char buf
[16];
2060 CORE_ADDR buildaddr
;
2062 buildaddr
= current_insn_ptr
;
2064 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2065 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2067 append_insns (&buildaddr
, i
, buf
);
2068 current_insn_ptr
= buildaddr
;
2069 amd64_emit_call (fn
);
2072 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2075 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2077 unsigned char buf
[16];
2079 CORE_ADDR buildaddr
;
2081 buildaddr
= current_insn_ptr
;
2083 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2084 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2086 append_insns (&buildaddr
, i
, buf
);
2087 current_insn_ptr
= buildaddr
;
2088 EMIT_ASM (amd64_void_call_2_a
,
2089 /* Save away a copy of the stack top. */
2091 /* Also pass top as the second argument. */
2093 amd64_emit_call (fn
);
2094 EMIT_ASM (amd64_void_call_2_b
,
2095 /* Restore the stack top, %rax may have been trashed. */
2100 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2103 "cmp %rax,(%rsp)\n\t"
2104 "jne .Lamd64_eq_fallthru\n\t"
2105 "lea 0x8(%rsp),%rsp\n\t"
2107 /* jmp, but don't trust the assembler to choose the right jump */
2108 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2109 ".Lamd64_eq_fallthru:\n\t"
2110 "lea 0x8(%rsp),%rsp\n\t"
2120 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2123 "cmp %rax,(%rsp)\n\t"
2124 "je .Lamd64_ne_fallthru\n\t"
2125 "lea 0x8(%rsp),%rsp\n\t"
2127 /* jmp, but don't trust the assembler to choose the right jump */
2128 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2129 ".Lamd64_ne_fallthru:\n\t"
2130 "lea 0x8(%rsp),%rsp\n\t"
2140 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2143 "cmp %rax,(%rsp)\n\t"
2144 "jnl .Lamd64_lt_fallthru\n\t"
2145 "lea 0x8(%rsp),%rsp\n\t"
2147 /* jmp, but don't trust the assembler to choose the right jump */
2148 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2149 ".Lamd64_lt_fallthru:\n\t"
2150 "lea 0x8(%rsp),%rsp\n\t"
2160 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2163 "cmp %rax,(%rsp)\n\t"
2164 "jnle .Lamd64_le_fallthru\n\t"
2165 "lea 0x8(%rsp),%rsp\n\t"
2167 /* jmp, but don't trust the assembler to choose the right jump */
2168 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2169 ".Lamd64_le_fallthru:\n\t"
2170 "lea 0x8(%rsp),%rsp\n\t"
2180 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2183 "cmp %rax,(%rsp)\n\t"
2184 "jng .Lamd64_gt_fallthru\n\t"
2185 "lea 0x8(%rsp),%rsp\n\t"
2187 /* jmp, but don't trust the assembler to choose the right jump */
2188 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2189 ".Lamd64_gt_fallthru:\n\t"
2190 "lea 0x8(%rsp),%rsp\n\t"
2200 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2203 "cmp %rax,(%rsp)\n\t"
2204 "jnge .Lamd64_ge_fallthru\n\t"
2205 ".Lamd64_ge_jump:\n\t"
2206 "lea 0x8(%rsp),%rsp\n\t"
2208 /* jmp, but don't trust the assembler to choose the right jump */
2209 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2210 ".Lamd64_ge_fallthru:\n\t"
2211 "lea 0x8(%rsp),%rsp\n\t"
2220 static emit_ops amd64_emit_ops
=
2222 amd64_emit_prologue
,
2223 amd64_emit_epilogue
,
2228 amd64_emit_rsh_signed
,
2229 amd64_emit_rsh_unsigned
,
2237 amd64_emit_less_signed
,
2238 amd64_emit_less_unsigned
,
2242 amd64_write_goto_address
,
2247 amd64_emit_stack_flush
,
2248 amd64_emit_zero_ext
,
2250 amd64_emit_stack_adjust
,
2251 amd64_emit_int_call_1
,
2252 amd64_emit_void_call_2
,
2261 #endif /* __x86_64__ */
2264 i386_emit_prologue (void)
2266 EMIT_ASM32 (i386_prologue
,
2270 /* At this point, the raw regs base address is at 8(%ebp), and the
2271 value pointer is at 12(%ebp). */
2275 i386_emit_epilogue (void)
2277 EMIT_ASM32 (i386_epilogue
,
2278 "mov 12(%ebp),%ecx\n\t"
2279 "mov %eax,(%ecx)\n\t"
2280 "mov %ebx,0x4(%ecx)\n\t"
2288 i386_emit_add (void)
2290 EMIT_ASM32 (i386_add
,
2291 "add (%esp),%eax\n\t"
2292 "adc 0x4(%esp),%ebx\n\t"
2293 "lea 0x8(%esp),%esp");
2297 i386_emit_sub (void)
2299 EMIT_ASM32 (i386_sub
,
2300 "subl %eax,(%esp)\n\t"
2301 "sbbl %ebx,4(%esp)\n\t"
2307 i386_emit_mul (void)
2313 i386_emit_lsh (void)
2319 i386_emit_rsh_signed (void)
2325 i386_emit_rsh_unsigned (void)
2331 i386_emit_ext (int arg
)
2336 EMIT_ASM32 (i386_ext_8
,
2339 "movl %eax,%ebx\n\t"
2343 EMIT_ASM32 (i386_ext_16
,
2345 "movl %eax,%ebx\n\t"
2349 EMIT_ASM32 (i386_ext_32
,
2350 "movl %eax,%ebx\n\t"
2359 i386_emit_log_not (void)
2361 EMIT_ASM32 (i386_log_not
,
2363 "test %eax,%eax\n\t"
2370 i386_emit_bit_and (void)
2372 EMIT_ASM32 (i386_and
,
2373 "and (%esp),%eax\n\t"
2374 "and 0x4(%esp),%ebx\n\t"
2375 "lea 0x8(%esp),%esp");
2379 i386_emit_bit_or (void)
2381 EMIT_ASM32 (i386_or
,
2382 "or (%esp),%eax\n\t"
2383 "or 0x4(%esp),%ebx\n\t"
2384 "lea 0x8(%esp),%esp");
2388 i386_emit_bit_xor (void)
2390 EMIT_ASM32 (i386_xor
,
2391 "xor (%esp),%eax\n\t"
2392 "xor 0x4(%esp),%ebx\n\t"
2393 "lea 0x8(%esp),%esp");
2397 i386_emit_bit_not (void)
2399 EMIT_ASM32 (i386_bit_not
,
2400 "xor $0xffffffff,%eax\n\t"
2401 "xor $0xffffffff,%ebx\n\t");
2405 i386_emit_equal (void)
2407 EMIT_ASM32 (i386_equal
,
2408 "cmpl %ebx,4(%esp)\n\t"
2409 "jne .Li386_equal_false\n\t"
2410 "cmpl %eax,(%esp)\n\t"
2411 "je .Li386_equal_true\n\t"
2412 ".Li386_equal_false:\n\t"
2414 "jmp .Li386_equal_end\n\t"
2415 ".Li386_equal_true:\n\t"
2417 ".Li386_equal_end:\n\t"
2419 "lea 0x8(%esp),%esp");
2423 i386_emit_less_signed (void)
2425 EMIT_ASM32 (i386_less_signed
,
2426 "cmpl %ebx,4(%esp)\n\t"
2427 "jl .Li386_less_signed_true\n\t"
2428 "jne .Li386_less_signed_false\n\t"
2429 "cmpl %eax,(%esp)\n\t"
2430 "jl .Li386_less_signed_true\n\t"
2431 ".Li386_less_signed_false:\n\t"
2433 "jmp .Li386_less_signed_end\n\t"
2434 ".Li386_less_signed_true:\n\t"
2436 ".Li386_less_signed_end:\n\t"
2438 "lea 0x8(%esp),%esp");
2442 i386_emit_less_unsigned (void)
2444 EMIT_ASM32 (i386_less_unsigned
,
2445 "cmpl %ebx,4(%esp)\n\t"
2446 "jb .Li386_less_unsigned_true\n\t"
2447 "jne .Li386_less_unsigned_false\n\t"
2448 "cmpl %eax,(%esp)\n\t"
2449 "jb .Li386_less_unsigned_true\n\t"
2450 ".Li386_less_unsigned_false:\n\t"
2452 "jmp .Li386_less_unsigned_end\n\t"
2453 ".Li386_less_unsigned_true:\n\t"
2455 ".Li386_less_unsigned_end:\n\t"
2457 "lea 0x8(%esp),%esp");
2461 i386_emit_ref (int size
)
2466 EMIT_ASM32 (i386_ref1
,
2470 EMIT_ASM32 (i386_ref2
,
2474 EMIT_ASM32 (i386_ref4
,
2475 "movl (%eax),%eax");
2478 EMIT_ASM32 (i386_ref8
,
2479 "movl 4(%eax),%ebx\n\t"
2480 "movl (%eax),%eax");
2486 i386_emit_if_goto (int *offset_p
, int *size_p
)
2488 EMIT_ASM32 (i386_if_goto
,
2494 /* Don't trust the assembler to choose the right jump */
2495 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2498 *offset_p
= 11; /* be sure that this matches the sequence above */
2504 i386_emit_goto (int *offset_p
, int *size_p
)
2506 EMIT_ASM32 (i386_goto
,
2507 /* Don't trust the assembler to choose the right jump */
2508 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2516 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2518 int diff
= (to
- (from
+ size
));
2519 unsigned char buf
[sizeof (int)];
2521 /* We're only doing 4-byte sizes at the moment. */
2528 memcpy (buf
, &diff
, sizeof (int));
2529 target_write_memory (from
, buf
, sizeof (int));
2533 i386_emit_const (LONGEST num
)
2535 unsigned char buf
[16];
2537 CORE_ADDR buildaddr
= current_insn_ptr
;
2540 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2541 lo
= num
& 0xffffffff;
2542 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2544 hi
= ((num
>> 32) & 0xffffffff);
2547 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2548 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2553 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2555 append_insns (&buildaddr
, i
, buf
);
2556 current_insn_ptr
= buildaddr
;
2560 i386_emit_call (CORE_ADDR fn
)
2562 unsigned char buf
[16];
2564 CORE_ADDR buildaddr
;
2566 buildaddr
= current_insn_ptr
;
2568 buf
[i
++] = 0xe8; /* call <reladdr> */
2569 offset
= ((int) fn
) - (buildaddr
+ 5);
2570 memcpy (buf
+ 1, &offset
, 4);
2571 append_insns (&buildaddr
, 5, buf
);
2572 current_insn_ptr
= buildaddr
;
2576 i386_emit_reg (int reg
)
2578 unsigned char buf
[16];
2580 CORE_ADDR buildaddr
;
2582 EMIT_ASM32 (i386_reg_a
,
2584 buildaddr
= current_insn_ptr
;
2586 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2587 memcpy (&buf
[i
], ®
, sizeof (reg
));
2589 append_insns (&buildaddr
, i
, buf
);
2590 current_insn_ptr
= buildaddr
;
2591 EMIT_ASM32 (i386_reg_b
,
2592 "mov %eax,4(%esp)\n\t"
2593 "mov 8(%ebp),%eax\n\t"
2595 i386_emit_call (get_raw_reg_func_addr ());
2596 EMIT_ASM32 (i386_reg_c
,
2598 "lea 0x8(%esp),%esp");
2602 i386_emit_pop (void)
2604 EMIT_ASM32 (i386_pop
,
2610 i386_emit_stack_flush (void)
2612 EMIT_ASM32 (i386_stack_flush
,
2618 i386_emit_zero_ext (int arg
)
2623 EMIT_ASM32 (i386_zero_ext_8
,
2624 "and $0xff,%eax\n\t"
2628 EMIT_ASM32 (i386_zero_ext_16
,
2629 "and $0xffff,%eax\n\t"
2633 EMIT_ASM32 (i386_zero_ext_32
,
2642 i386_emit_swap (void)
2644 EMIT_ASM32 (i386_swap
,
2654 i386_emit_stack_adjust (int n
)
2656 unsigned char buf
[16];
2658 CORE_ADDR buildaddr
= current_insn_ptr
;
2661 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2665 append_insns (&buildaddr
, i
, buf
);
2666 current_insn_ptr
= buildaddr
;
2669 /* FN's prototype is `LONGEST(*fn)(int)'. */
2672 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2674 unsigned char buf
[16];
2676 CORE_ADDR buildaddr
;
2678 EMIT_ASM32 (i386_int_call_1_a
,
2679 /* Reserve a bit of stack space. */
2681 /* Put the one argument on the stack. */
2682 buildaddr
= current_insn_ptr
;
2684 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2687 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2689 append_insns (&buildaddr
, i
, buf
);
2690 current_insn_ptr
= buildaddr
;
2691 i386_emit_call (fn
);
2692 EMIT_ASM32 (i386_int_call_1_c
,
2694 "lea 0x8(%esp),%esp");
2697 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2700 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2702 unsigned char buf
[16];
2704 CORE_ADDR buildaddr
;
2706 EMIT_ASM32 (i386_void_call_2_a
,
2707 /* Preserve %eax only; we don't have to worry about %ebx. */
2709 /* Reserve a bit of stack space for arguments. */
2710 "sub $0x10,%esp\n\t"
2711 /* Copy "top" to the second argument position. (Note that
2712 we can't assume function won't scribble on its
2713 arguments, so don't try to restore from this.) */
2714 "mov %eax,4(%esp)\n\t"
2715 "mov %ebx,8(%esp)");
2716 /* Put the first argument on the stack. */
2717 buildaddr
= current_insn_ptr
;
2719 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2722 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2724 append_insns (&buildaddr
, i
, buf
);
2725 current_insn_ptr
= buildaddr
;
2726 i386_emit_call (fn
);
2727 EMIT_ASM32 (i386_void_call_2_b
,
2728 "lea 0x10(%esp),%esp\n\t"
2729 /* Restore original stack top. */
2735 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2738 /* Check low half first, more likely to be decider */
2739 "cmpl %eax,(%esp)\n\t"
2740 "jne .Leq_fallthru\n\t"
2741 "cmpl %ebx,4(%esp)\n\t"
2742 "jne .Leq_fallthru\n\t"
2743 "lea 0x8(%esp),%esp\n\t"
2746 /* jmp, but don't trust the assembler to choose the right jump */
2747 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2748 ".Leq_fallthru:\n\t"
2749 "lea 0x8(%esp),%esp\n\t"
2760 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2763 /* Check low half first, more likely to be decider */
2764 "cmpl %eax,(%esp)\n\t"
2766 "cmpl %ebx,4(%esp)\n\t"
2767 "je .Lne_fallthru\n\t"
2769 "lea 0x8(%esp),%esp\n\t"
2772 /* jmp, but don't trust the assembler to choose the right jump */
2773 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2774 ".Lne_fallthru:\n\t"
2775 "lea 0x8(%esp),%esp\n\t"
2786 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2789 "cmpl %ebx,4(%esp)\n\t"
2791 "jne .Llt_fallthru\n\t"
2792 "cmpl %eax,(%esp)\n\t"
2793 "jnl .Llt_fallthru\n\t"
2795 "lea 0x8(%esp),%esp\n\t"
2798 /* jmp, but don't trust the assembler to choose the right jump */
2799 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2800 ".Llt_fallthru:\n\t"
2801 "lea 0x8(%esp),%esp\n\t"
2812 i386_emit_le_goto (int *offset_p
, int *size_p
)
2815 "cmpl %ebx,4(%esp)\n\t"
2817 "jne .Lle_fallthru\n\t"
2818 "cmpl %eax,(%esp)\n\t"
2819 "jnle .Lle_fallthru\n\t"
2821 "lea 0x8(%esp),%esp\n\t"
2824 /* jmp, but don't trust the assembler to choose the right jump */
2825 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2826 ".Lle_fallthru:\n\t"
2827 "lea 0x8(%esp),%esp\n\t"
2838 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2841 "cmpl %ebx,4(%esp)\n\t"
2843 "jne .Lgt_fallthru\n\t"
2844 "cmpl %eax,(%esp)\n\t"
2845 "jng .Lgt_fallthru\n\t"
2847 "lea 0x8(%esp),%esp\n\t"
2850 /* jmp, but don't trust the assembler to choose the right jump */
2851 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2852 ".Lgt_fallthru:\n\t"
2853 "lea 0x8(%esp),%esp\n\t"
2864 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2867 "cmpl %ebx,4(%esp)\n\t"
2869 "jne .Lge_fallthru\n\t"
2870 "cmpl %eax,(%esp)\n\t"
2871 "jnge .Lge_fallthru\n\t"
2873 "lea 0x8(%esp),%esp\n\t"
2876 /* jmp, but don't trust the assembler to choose the right jump */
2877 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2878 ".Lge_fallthru:\n\t"
2879 "lea 0x8(%esp),%esp\n\t"
2889 static emit_ops i386_emit_ops
=
2897 i386_emit_rsh_signed
,
2898 i386_emit_rsh_unsigned
,
2906 i386_emit_less_signed
,
2907 i386_emit_less_unsigned
,
2911 i386_write_goto_address
,
2916 i386_emit_stack_flush
,
2919 i386_emit_stack_adjust
,
2920 i386_emit_int_call_1
,
2921 i386_emit_void_call_2
,
2932 x86_target::emit_ops ()
2935 if (is_64bit_tdesc ())
2936 return &amd64_emit_ops
;
2939 return &i386_emit_ops
;
2942 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2945 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2947 *size
= x86_breakpoint_len
;
2948 return x86_breakpoint
;
2952 x86_target::low_supports_range_stepping ()
2958 x86_target::get_ipa_tdesc_idx ()
2960 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2961 const struct target_desc
*tdesc
= regcache
->tdesc
;
2964 return amd64_get_ipa_tdesc_idx (tdesc
);
2967 if (tdesc
== tdesc_i386_linux_no_xml
.get ())
2968 return X86_TDESC_SSE
;
2970 return i386_get_ipa_tdesc_idx (tdesc
);
2973 /* The linux target ops object. */
2975 linux_process_target
*the_linux_target
= &the_x86_target
;
2978 initialize_low_arch (void)
2980 /* Initialize the Linux target descriptions. */
2982 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2983 copy_target_description (tdesc_amd64_linux_no_xml
.get (),
2984 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2986 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2989 tdesc_i386_linux_no_xml
= allocate_target_description ();
2990 copy_target_description (tdesc_i386_linux_no_xml
.get (),
2991 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2992 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2994 initialize_regsets_info (&x86_regsets_info
);