4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
31 #include "exec-memory.h"
36 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 # define PIIX4_DPRINTF(format, ...) do { } while (0)
41 #define ACPI_DBG_IO_ADDR 0xb044
43 #define GPE_BASE 0xafe0
45 #define PCI_UP_BASE 0xae00
46 #define PCI_DOWN_BASE 0xae04
47 #define PCI_EJ_BASE 0xae08
48 #define PCI_RMV_BASE 0xae0c
50 #define PIIX4_PCI_HOTPLUG_STATUS 2
53 uint32_t up
; /* deprecated, maintained for migration compatibility */
57 typedef struct PIIX4PMState
{
70 Notifier machine_ready
;
71 Notifier powerdown_notifier
;
74 struct pci_status pci0_status
;
75 uint32_t pci0_hotplug_enable
;
76 uint32_t pci0_slot_device_present
;
83 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
);
85 #define ACPI_ENABLE 0xf1
86 #define ACPI_DISABLE 0xf0
88 static void pm_update_sci(PIIX4PMState
*s
)
92 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
93 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
94 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
95 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
96 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
97 ACPI_BITMASK_TIMER_ENABLE
)) != 0) ||
98 (((s
->ar
.gpe
.sts
[0] & s
->ar
.gpe
.en
[0])
99 & PIIX4_PCI_HOTPLUG_STATUS
) != 0);
101 qemu_set_irq(s
->irq
, sci_level
);
102 /* schedule a timer interruption if needed */
103 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
104 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
107 static void pm_tmr_timer(ACPIREGS
*ar
)
109 PIIX4PMState
*s
= container_of(ar
, PIIX4PMState
, ar
);
113 static void pm_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
117 PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
118 (unsigned)addr
, width
, (unsigned)val
);
125 PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr
,
129 static uint64_t pm_ioport_read(void *opaque
, hwaddr addr
, unsigned width
)
138 PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr
, val
);
142 static const MemoryRegionOps pm_io_ops
= {
143 .read
= pm_ioport_read
,
144 .write
= pm_ioport_write
,
145 .valid
.min_access_size
= 1,
146 .valid
.max_access_size
= 4,
147 .impl
.min_access_size
= 1,
148 .impl
.max_access_size
= 4,
149 .endianness
= DEVICE_LITTLE_ENDIAN
,
152 static void apm_ctrl_changed(uint32_t val
, void *arg
)
154 PIIX4PMState
*s
= arg
;
156 /* ACPI specs 3.0, 4.7.2.5 */
157 acpi_pm1_cnt_update(&s
->ar
, val
== ACPI_ENABLE
, val
== ACPI_DISABLE
);
159 if (s
->dev
.config
[0x5b] & (1 << 1)) {
161 qemu_irq_raise(s
->smi_irq
);
166 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
168 PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val
);
171 static void pm_io_space_update(PIIX4PMState
*s
)
175 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
176 pm_io_base
&= 0xffc0;
178 memory_region_transaction_begin();
179 memory_region_set_enabled(&s
->io
, s
->dev
.config
[0x80] & 1);
180 memory_region_set_address(&s
->io
, pm_io_base
);
181 memory_region_transaction_commit();
184 static void pm_write_config(PCIDevice
*d
,
185 uint32_t address
, uint32_t val
, int len
)
187 pci_default_write_config(d
, address
, val
, len
);
188 if (range_covers_byte(address
, len
, 0x80))
189 pm_io_space_update((PIIX4PMState
*)d
);
192 static void vmstate_pci_status_pre_save(void *opaque
)
194 struct pci_status
*pci0_status
= opaque
;
195 PIIX4PMState
*s
= container_of(pci0_status
, PIIX4PMState
, pci0_status
);
197 /* We no longer track up, so build a safe value for migrating
198 * to a version that still does... of course these might get lost
199 * by an old buggy implementation, but we try. */
200 pci0_status
->up
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
203 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
205 PIIX4PMState
*s
= opaque
;
207 pm_io_space_update(s
);
211 #define VMSTATE_GPE_ARRAY(_field, _state) \
213 .name = (stringify(_field)), \
215 .info = &vmstate_info_uint16, \
216 .size = sizeof(uint16_t), \
217 .flags = VMS_SINGLE | VMS_POINTER, \
218 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
221 static const VMStateDescription vmstate_gpe
= {
224 .minimum_version_id
= 1,
225 .minimum_version_id_old
= 1,
226 .fields
= (VMStateField
[]) {
227 VMSTATE_GPE_ARRAY(sts
, ACPIGPE
),
228 VMSTATE_GPE_ARRAY(en
, ACPIGPE
),
229 VMSTATE_END_OF_LIST()
233 static const VMStateDescription vmstate_pci_status
= {
234 .name
= "pci_status",
236 .minimum_version_id
= 1,
237 .minimum_version_id_old
= 1,
238 .pre_save
= vmstate_pci_status_pre_save
,
239 .fields
= (VMStateField
[]) {
240 VMSTATE_UINT32(up
, struct pci_status
),
241 VMSTATE_UINT32(down
, struct pci_status
),
242 VMSTATE_END_OF_LIST()
246 static int acpi_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
248 PIIX4PMState
*s
= opaque
;
252 ret
= pci_device_load(&s
->dev
, f
);
256 qemu_get_be16s(f
, &s
->ar
.pm1
.evt
.sts
);
257 qemu_get_be16s(f
, &s
->ar
.pm1
.evt
.en
);
258 qemu_get_be16s(f
, &s
->ar
.pm1
.cnt
.cnt
);
260 ret
= vmstate_load_state(f
, &vmstate_apm
, opaque
, 1);
265 qemu_get_timer(f
, s
->ar
.tmr
.timer
);
266 qemu_get_sbe64s(f
, &s
->ar
.tmr
.overflow_time
);
268 qemu_get_be16s(f
, (uint16_t *)s
->ar
.gpe
.sts
);
269 for (i
= 0; i
< 3; i
++) {
270 qemu_get_be16s(f
, &temp
);
273 qemu_get_be16s(f
, (uint16_t *)s
->ar
.gpe
.en
);
274 for (i
= 0; i
< 3; i
++) {
275 qemu_get_be16s(f
, &temp
);
278 ret
= vmstate_load_state(f
, &vmstate_pci_status
, opaque
, 1);
282 /* qemu-kvm 1.2 uses version 3 but advertised as 2
283 * To support incoming qemu-kvm 1.2 migration, change version_id
284 * and minimum_version_id to 2 below (which breaks migration from
288 static const VMStateDescription vmstate_acpi
= {
291 .minimum_version_id
= 3,
292 .minimum_version_id_old
= 1,
293 .load_state_old
= acpi_load_old
,
294 .post_load
= vmstate_acpi_post_load
,
295 .fields
= (VMStateField
[]) {
296 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
297 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, PIIX4PMState
),
298 VMSTATE_UINT16(ar
.pm1
.evt
.en
, PIIX4PMState
),
299 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, PIIX4PMState
),
300 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
301 VMSTATE_TIMER(ar
.tmr
.timer
, PIIX4PMState
),
302 VMSTATE_INT64(ar
.tmr
.overflow_time
, PIIX4PMState
),
303 VMSTATE_STRUCT(ar
.gpe
, PIIX4PMState
, 2, vmstate_gpe
, ACPIGPE
),
304 VMSTATE_STRUCT(pci0_status
, PIIX4PMState
, 2, vmstate_pci_status
,
306 VMSTATE_END_OF_LIST()
310 static void acpi_piix_eject_slot(PIIX4PMState
*s
, unsigned slots
)
312 BusChild
*kid
, *next
;
313 BusState
*bus
= qdev_get_parent_bus(&s
->dev
.qdev
);
314 int slot
= ffs(slots
) - 1;
315 bool slot_free
= true;
317 /* Mark request as complete */
318 s
->pci0_status
.down
&= ~(1U << slot
);
320 QTAILQ_FOREACH_SAFE(kid
, &bus
->children
, sibling
, next
) {
321 DeviceState
*qdev
= kid
->child
;
322 PCIDevice
*dev
= PCI_DEVICE(qdev
);
323 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
324 if (PCI_SLOT(dev
->devfn
) == slot
) {
325 if (pc
->no_hotplug
) {
333 s
->pci0_slot_device_present
&= ~(1U << slot
);
337 static void piix4_update_hotplug(PIIX4PMState
*s
)
339 PCIDevice
*dev
= &s
->dev
;
340 BusState
*bus
= qdev_get_parent_bus(&dev
->qdev
);
341 BusChild
*kid
, *next
;
343 /* Execute any pending removes during reset */
344 while (s
->pci0_status
.down
) {
345 acpi_piix_eject_slot(s
, s
->pci0_status
.down
);
348 s
->pci0_hotplug_enable
= ~0;
349 s
->pci0_slot_device_present
= 0;
351 QTAILQ_FOREACH_SAFE(kid
, &bus
->children
, sibling
, next
) {
352 DeviceState
*qdev
= kid
->child
;
353 PCIDevice
*pdev
= PCI_DEVICE(qdev
);
354 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pdev
);
355 int slot
= PCI_SLOT(pdev
->devfn
);
357 if (pc
->no_hotplug
) {
358 s
->pci0_hotplug_enable
&= ~(1U << slot
);
361 s
->pci0_slot_device_present
|= (1U << slot
);
365 static void piix4_reset(void *opaque
)
367 PIIX4PMState
*s
= opaque
;
368 uint8_t *pci_conf
= s
->dev
.config
;
375 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
378 if (s
->kvm_enabled
) {
379 /* Mark SMM as already inited (until KVM supports SMM). */
380 pci_conf
[0x5B] = 0x02;
382 piix4_update_hotplug(s
);
385 static void piix4_pm_powerdown_req(Notifier
*n
, void *opaque
)
387 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, powerdown_notifier
);
390 acpi_pm1_evt_power_down(&s
->ar
);
393 static void piix4_pm_machine_ready(Notifier
*n
, void *opaque
)
395 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, machine_ready
);
398 pci_conf
= s
->dev
.config
;
399 pci_conf
[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
400 pci_conf
[0x63] = 0x60;
401 pci_conf
[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
402 (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
406 static int piix4_pm_initfn(PCIDevice
*dev
)
408 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
411 pci_conf
= s
->dev
.config
;
412 pci_conf
[0x06] = 0x80;
413 pci_conf
[0x07] = 0x02;
414 pci_conf
[0x09] = 0x00;
415 pci_conf
[0x3d] = 0x01; // interrupt pin 1
418 apm_init(&s
->apm
, apm_ctrl_changed
, s
);
420 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
422 if (s
->kvm_enabled
) {
423 /* Mark SMM as already inited to prevent SMM from running. KVM does not
424 * support SMM mode. */
425 pci_conf
[0x5B] = 0x02;
428 /* XXX: which specification is used ? The i82731AB has different
430 pci_conf
[0x90] = s
->smb_io_base
| 1;
431 pci_conf
[0x91] = s
->smb_io_base
>> 8;
432 pci_conf
[0xd2] = 0x09;
433 register_ioport_write(s
->smb_io_base
, 64, 1, smb_ioport_writeb
, &s
->smb
);
434 register_ioport_read(s
->smb_io_base
, 64, 1, smb_ioport_readb
, &s
->smb
);
436 memory_region_init_io(&s
->io
, &pm_io_ops
, s
, "piix4-pm", 64);
437 memory_region_set_enabled(&s
->io
, false);
438 memory_region_add_subregion(get_system_io(), 0, &s
->io
);
440 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
441 acpi_pm1_evt_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
442 acpi_pm1_cnt_init(&s
->ar
, &s
->io
);
443 acpi_gpe_init(&s
->ar
, GPE_LEN
);
445 s
->powerdown_notifier
.notify
= piix4_pm_powerdown_req
;
446 qemu_register_powerdown_notifier(&s
->powerdown_notifier
);
448 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
449 s
->machine_ready
.notify
= piix4_pm_machine_ready
;
450 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
451 qemu_register_reset(piix4_reset
, s
);
452 piix4_acpi_system_hot_add_init(dev
->bus
, s
);
457 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
458 qemu_irq sci_irq
, qemu_irq smi_irq
,
459 int kvm_enabled
, void *fw_cfg
)
464 dev
= pci_create(bus
, devfn
, "PIIX4_PM");
465 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
467 s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
469 s
->smi_irq
= smi_irq
;
470 s
->kvm_enabled
= kvm_enabled
;
472 qdev_init_nofail(&dev
->qdev
);
475 uint8_t suspend
[6] = {128, 0, 0, 129, 128, 128};
476 suspend
[3] = 1 | ((!s
->disable_s3
) << 7);
477 suspend
[4] = s
->s4_val
| ((!s
->disable_s4
) << 7);
479 fw_cfg_add_file(fw_cfg
, "etc/system-states", g_memdup(suspend
, 6), 6);
485 static Property piix4_pm_properties
[] = {
486 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
487 DEFINE_PROP_UINT8("disable_s3", PIIX4PMState
, disable_s3
, 0),
488 DEFINE_PROP_UINT8("disable_s4", PIIX4PMState
, disable_s4
, 0),
489 DEFINE_PROP_UINT8("s4_val", PIIX4PMState
, s4_val
, 2),
490 DEFINE_PROP_END_OF_LIST(),
493 static void piix4_pm_class_init(ObjectClass
*klass
, void *data
)
495 DeviceClass
*dc
= DEVICE_CLASS(klass
);
496 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
499 k
->init
= piix4_pm_initfn
;
500 k
->config_write
= pm_write_config
;
501 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
502 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_3
;
504 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
507 dc
->vmsd
= &vmstate_acpi
;
508 dc
->props
= piix4_pm_properties
;
511 static TypeInfo piix4_pm_info
= {
513 .parent
= TYPE_PCI_DEVICE
,
514 .instance_size
= sizeof(PIIX4PMState
),
515 .class_init
= piix4_pm_class_init
,
518 static void piix4_pm_register_types(void)
520 type_register_static(&piix4_pm_info
);
523 type_init(piix4_pm_register_types
)
525 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
527 PIIX4PMState
*s
= opaque
;
528 uint32_t val
= acpi_gpe_ioport_readb(&s
->ar
, addr
);
530 PIIX4_DPRINTF("gpe read %x == %x\n", addr
, val
);
534 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
536 PIIX4PMState
*s
= opaque
;
538 acpi_gpe_ioport_writeb(&s
->ar
, addr
, val
);
541 PIIX4_DPRINTF("gpe write %x <== %d\n", addr
, val
);
544 static uint32_t pci_up_read(void *opaque
, uint32_t addr
)
546 PIIX4PMState
*s
= opaque
;
549 /* Manufacture an "up" value to cause a device check on any hotplug
550 * slot with a device. Extra device checks are harmless. */
551 val
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
553 PIIX4_DPRINTF("pci_up_read %x\n", val
);
557 static uint32_t pci_down_read(void *opaque
, uint32_t addr
)
559 PIIX4PMState
*s
= opaque
;
560 uint32_t val
= s
->pci0_status
.down
;
562 PIIX4_DPRINTF("pci_down_read %x\n", val
);
566 static uint32_t pci_features_read(void *opaque
, uint32_t addr
)
568 /* No feature defined yet */
569 PIIX4_DPRINTF("pci_features_read %x\n", 0);
573 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
575 acpi_piix_eject_slot(opaque
, val
);
577 PIIX4_DPRINTF("pciej write %x <== %d\n", addr
, val
);
580 static uint32_t pcirmv_read(void *opaque
, uint32_t addr
)
582 PIIX4PMState
*s
= opaque
;
584 return s
->pci0_hotplug_enable
;
587 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
588 PCIHotplugState state
);
590 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
)
593 register_ioport_write(GPE_BASE
, GPE_LEN
, 1, gpe_writeb
, s
);
594 register_ioport_read(GPE_BASE
, GPE_LEN
, 1, gpe_readb
, s
);
595 acpi_gpe_blk(&s
->ar
, GPE_BASE
);
597 register_ioport_read(PCI_UP_BASE
, 4, 4, pci_up_read
, s
);
598 register_ioport_read(PCI_DOWN_BASE
, 4, 4, pci_down_read
, s
);
600 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, s
);
601 register_ioport_read(PCI_EJ_BASE
, 4, 4, pci_features_read
, s
);
603 register_ioport_read(PCI_RMV_BASE
, 4, 4, pcirmv_read
, s
);
605 pci_bus_hotplug(bus
, piix4_device_hotplug
, &s
->dev
.qdev
);
608 static void enable_device(PIIX4PMState
*s
, int slot
)
610 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
611 s
->pci0_slot_device_present
|= (1U << slot
);
614 static void disable_device(PIIX4PMState
*s
, int slot
)
616 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
617 s
->pci0_status
.down
|= (1U << slot
);
620 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
621 PCIHotplugState state
)
623 int slot
= PCI_SLOT(dev
->devfn
);
624 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
,
627 /* Don't send event when device is enabled during qemu machine creation:
628 * it is present on boot, no hotplug event is necessary. We do send an
629 * event when the device is disabled later. */
630 if (state
== PCI_COLDPLUG_ENABLED
) {
631 s
->pci0_slot_device_present
|= (1U << slot
);
635 if (state
== PCI_HOTPLUG_ENABLED
) {
636 enable_device(s
, slot
);
638 disable_device(s
, slot
);