2 * TI OMAP processors emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/error-report.h"
22 #include "qemu/main-loop.h"
23 #include "qapi/error.h"
24 #include "qemu-common.h"
26 #include "hw/boards.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/arm/boot.h"
31 #include "hw/arm/omap.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/arm/soc_dma.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "qemu/range.h"
37 #include "hw/sysbus.h"
38 #include "qemu/cutils.h"
41 static inline void omap_log_badwidth(const char *funcname
, hwaddr addr
, int sz
)
43 qemu_log_mask(LOG_GUEST_ERROR
, "%s: %d-bit register %#08" HWADDR_PRIx
"\n",
44 funcname
, 8 * sz
, addr
);
47 /* Should signal the TCMI/GPMC */
48 uint32_t omap_badwidth_read8(void *opaque
, hwaddr addr
)
52 omap_log_badwidth(__func__
, addr
, 1);
53 cpu_physical_memory_read(addr
, &ret
, 1);
57 void omap_badwidth_write8(void *opaque
, hwaddr addr
,
62 omap_log_badwidth(__func__
, addr
, 1);
63 cpu_physical_memory_write(addr
, &val8
, 1);
66 uint32_t omap_badwidth_read16(void *opaque
, hwaddr addr
)
70 omap_log_badwidth(__func__
, addr
, 2);
71 cpu_physical_memory_read(addr
, &ret
, 2);
75 void omap_badwidth_write16(void *opaque
, hwaddr addr
,
78 uint16_t val16
= value
;
80 omap_log_badwidth(__func__
, addr
, 2);
81 cpu_physical_memory_write(addr
, &val16
, 2);
84 uint32_t omap_badwidth_read32(void *opaque
, hwaddr addr
)
88 omap_log_badwidth(__func__
, addr
, 4);
89 cpu_physical_memory_read(addr
, &ret
, 4);
93 void omap_badwidth_write32(void *opaque
, hwaddr addr
,
96 omap_log_badwidth(__func__
, addr
, 4);
97 cpu_physical_memory_write(addr
, &value
, 4);
101 struct omap_mpu_timer_s
{
119 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s
*timer
)
121 uint64_t distance
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - timer
->time
;
123 if (timer
->st
&& timer
->enable
&& timer
->rate
)
124 return timer
->val
- muldiv64(distance
>> (timer
->ptv
+ 1),
125 timer
->rate
, NANOSECONDS_PER_SECOND
);
130 static inline void omap_timer_sync(struct omap_mpu_timer_s
*timer
)
132 timer
->val
= omap_timer_read(timer
);
133 timer
->time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
136 static inline void omap_timer_update(struct omap_mpu_timer_s
*timer
)
140 if (timer
->enable
&& timer
->st
&& timer
->rate
) {
141 timer
->val
= timer
->reset_val
; /* Should skip this on clk enable */
142 expires
= muldiv64((uint64_t) timer
->val
<< (timer
->ptv
+ 1),
143 NANOSECONDS_PER_SECOND
, timer
->rate
);
145 /* If timer expiry would be sooner than in about 1 ms and
146 * auto-reload isn't set, then fire immediately. This is a hack
147 * to make systems like PalmOS run in acceptable time. PalmOS
148 * sets the interval to a very low value and polls the status bit
149 * in a busy loop when it wants to sleep just a couple of CPU
151 if (expires
> (NANOSECONDS_PER_SECOND
>> 10) || timer
->ar
) {
152 timer_mod(timer
->timer
, timer
->time
+ expires
);
154 qemu_bh_schedule(timer
->tick
);
157 timer_del(timer
->timer
);
160 static void omap_timer_fire(void *opaque
)
162 struct omap_mpu_timer_s
*timer
= opaque
;
170 /* Edge-triggered irq */
171 qemu_irq_pulse(timer
->irq
);
174 static void omap_timer_tick(void *opaque
)
176 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
178 omap_timer_sync(timer
);
179 omap_timer_fire(timer
);
180 omap_timer_update(timer
);
183 static void omap_timer_clk_update(void *opaque
, int line
, int on
)
185 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
187 omap_timer_sync(timer
);
188 timer
->rate
= on
? omap_clk_getrate(timer
->clk
) : 0;
189 omap_timer_update(timer
);
192 static void omap_timer_clk_setup(struct omap_mpu_timer_s
*timer
)
194 omap_clk_adduser(timer
->clk
,
195 qemu_allocate_irq(omap_timer_clk_update
, timer
, 0));
196 timer
->rate
= omap_clk_getrate(timer
->clk
);
199 static uint64_t omap_mpu_timer_read(void *opaque
, hwaddr addr
,
202 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
205 return omap_badwidth_read32(opaque
, addr
);
209 case 0x00: /* CNTL_TIMER */
210 return (s
->enable
<< 5) | (s
->ptv
<< 2) | (s
->ar
<< 1) | s
->st
;
212 case 0x04: /* LOAD_TIM */
215 case 0x08: /* READ_TIM */
216 return omap_timer_read(s
);
223 static void omap_mpu_timer_write(void *opaque
, hwaddr addr
,
224 uint64_t value
, unsigned size
)
226 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
229 omap_badwidth_write32(opaque
, addr
, value
);
234 case 0x00: /* CNTL_TIMER */
236 s
->enable
= (value
>> 5) & 1;
237 s
->ptv
= (value
>> 2) & 7;
238 s
->ar
= (value
>> 1) & 1;
240 omap_timer_update(s
);
243 case 0x04: /* LOAD_TIM */
244 s
->reset_val
= value
;
247 case 0x08: /* READ_TIM */
256 static const MemoryRegionOps omap_mpu_timer_ops
= {
257 .read
= omap_mpu_timer_read
,
258 .write
= omap_mpu_timer_write
,
259 .endianness
= DEVICE_LITTLE_ENDIAN
,
262 static void omap_mpu_timer_reset(struct omap_mpu_timer_s
*s
)
266 s
->reset_val
= 31337;
274 static struct omap_mpu_timer_s
*omap_mpu_timer_init(MemoryRegion
*system_memory
,
276 qemu_irq irq
, omap_clk clk
)
278 struct omap_mpu_timer_s
*s
= g_new0(struct omap_mpu_timer_s
, 1);
282 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, s
);
283 s
->tick
= qemu_bh_new(omap_timer_fire
, s
);
284 omap_mpu_timer_reset(s
);
285 omap_timer_clk_setup(s
);
287 memory_region_init_io(&s
->iomem
, NULL
, &omap_mpu_timer_ops
, s
,
288 "omap-mpu-timer", 0x100);
290 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
296 struct omap_watchdog_timer_s
{
297 struct omap_mpu_timer_s timer
;
305 static uint64_t omap_wd_timer_read(void *opaque
, hwaddr addr
,
308 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
311 return omap_badwidth_read16(opaque
, addr
);
315 case 0x00: /* CNTL_TIMER */
316 return (s
->timer
.ptv
<< 9) | (s
->timer
.ar
<< 8) |
317 (s
->timer
.st
<< 7) | (s
->free
<< 1);
319 case 0x04: /* READ_TIMER */
320 return omap_timer_read(&s
->timer
);
322 case 0x08: /* TIMER_MODE */
323 return s
->mode
<< 15;
330 static void omap_wd_timer_write(void *opaque
, hwaddr addr
,
331 uint64_t value
, unsigned size
)
333 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
336 omap_badwidth_write16(opaque
, addr
, value
);
341 case 0x00: /* CNTL_TIMER */
342 omap_timer_sync(&s
->timer
);
343 s
->timer
.ptv
= (value
>> 9) & 7;
344 s
->timer
.ar
= (value
>> 8) & 1;
345 s
->timer
.st
= (value
>> 7) & 1;
346 s
->free
= (value
>> 1) & 1;
347 omap_timer_update(&s
->timer
);
350 case 0x04: /* LOAD_TIMER */
351 s
->timer
.reset_val
= value
& 0xffff;
354 case 0x08: /* TIMER_MODE */
355 if (!s
->mode
&& ((value
>> 15) & 1))
356 omap_clk_get(s
->timer
.clk
);
357 s
->mode
|= (value
>> 15) & 1;
358 if (s
->last_wr
== 0xf5) {
359 if ((value
& 0xff) == 0xa0) {
362 omap_clk_put(s
->timer
.clk
);
365 /* XXX: on T|E hardware somehow this has no effect,
366 * on Zire 71 it works as specified. */
368 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
371 s
->last_wr
= value
& 0xff;
379 static const MemoryRegionOps omap_wd_timer_ops
= {
380 .read
= omap_wd_timer_read
,
381 .write
= omap_wd_timer_write
,
382 .endianness
= DEVICE_NATIVE_ENDIAN
,
385 static void omap_wd_timer_reset(struct omap_watchdog_timer_s
*s
)
387 timer_del(s
->timer
.timer
);
389 omap_clk_get(s
->timer
.clk
);
395 s
->timer
.reset_val
= 0xffff;
400 omap_timer_update(&s
->timer
);
403 static struct omap_watchdog_timer_s
*omap_wd_timer_init(MemoryRegion
*memory
,
405 qemu_irq irq
, omap_clk clk
)
407 struct omap_watchdog_timer_s
*s
= g_new0(struct omap_watchdog_timer_s
, 1);
411 s
->timer
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, &s
->timer
);
412 omap_wd_timer_reset(s
);
413 omap_timer_clk_setup(&s
->timer
);
415 memory_region_init_io(&s
->iomem
, NULL
, &omap_wd_timer_ops
, s
,
416 "omap-wd-timer", 0x100);
417 memory_region_add_subregion(memory
, base
, &s
->iomem
);
423 struct omap_32khz_timer_s
{
424 struct omap_mpu_timer_s timer
;
428 static uint64_t omap_os_timer_read(void *opaque
, hwaddr addr
,
431 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
432 int offset
= addr
& OMAP_MPUI_REG_MASK
;
435 return omap_badwidth_read32(opaque
, addr
);
440 return s
->timer
.reset_val
;
443 return omap_timer_read(&s
->timer
);
446 return (s
->timer
.ar
<< 3) | (s
->timer
.it_ena
<< 2) | s
->timer
.st
;
455 static void omap_os_timer_write(void *opaque
, hwaddr addr
,
456 uint64_t value
, unsigned size
)
458 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
459 int offset
= addr
& OMAP_MPUI_REG_MASK
;
462 omap_badwidth_write32(opaque
, addr
, value
);
468 s
->timer
.reset_val
= value
& 0x00ffffff;
476 s
->timer
.ar
= (value
>> 3) & 1;
477 s
->timer
.it_ena
= (value
>> 2) & 1;
478 if (s
->timer
.st
!= (value
& 1) || (value
& 2)) {
479 omap_timer_sync(&s
->timer
);
480 s
->timer
.enable
= value
& 1;
481 s
->timer
.st
= value
& 1;
482 omap_timer_update(&s
->timer
);
491 static const MemoryRegionOps omap_os_timer_ops
= {
492 .read
= omap_os_timer_read
,
493 .write
= omap_os_timer_write
,
494 .endianness
= DEVICE_NATIVE_ENDIAN
,
497 static void omap_os_timer_reset(struct omap_32khz_timer_s
*s
)
499 timer_del(s
->timer
.timer
);
502 s
->timer
.reset_val
= 0x00ffffff;
509 static struct omap_32khz_timer_s
*omap_os_timer_init(MemoryRegion
*memory
,
511 qemu_irq irq
, omap_clk clk
)
513 struct omap_32khz_timer_s
*s
= g_new0(struct omap_32khz_timer_s
, 1);
517 s
->timer
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, &s
->timer
);
518 omap_os_timer_reset(s
);
519 omap_timer_clk_setup(&s
->timer
);
521 memory_region_init_io(&s
->iomem
, NULL
, &omap_os_timer_ops
, s
,
522 "omap-os-timer", 0x800);
523 memory_region_add_subregion(memory
, base
, &s
->iomem
);
528 /* Ultra Low-Power Device Module */
529 static uint64_t omap_ulpd_pm_read(void *opaque
, hwaddr addr
,
532 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
536 return omap_badwidth_read16(opaque
, addr
);
540 case 0x14: /* IT_STATUS */
541 ret
= s
->ulpd_pm_regs
[addr
>> 2];
542 s
->ulpd_pm_regs
[addr
>> 2] = 0;
543 qemu_irq_lower(qdev_get_gpio_in(s
->ih
[1], OMAP_INT_GAUGE_32K
));
546 case 0x18: /* Reserved */
547 case 0x1c: /* Reserved */
548 case 0x20: /* Reserved */
549 case 0x28: /* Reserved */
550 case 0x2c: /* Reserved */
553 case 0x00: /* COUNTER_32_LSB */
554 case 0x04: /* COUNTER_32_MSB */
555 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
556 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
557 case 0x10: /* GAUGING_CTRL */
558 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
559 case 0x30: /* CLOCK_CTRL */
560 case 0x34: /* SOFT_REQ */
561 case 0x38: /* COUNTER_32_FIQ */
562 case 0x3c: /* DPLL_CTRL */
563 case 0x40: /* STATUS_REQ */
564 /* XXX: check clk::usecount state for every clock */
565 case 0x48: /* LOCL_TIME */
566 case 0x4c: /* APLL_CTRL */
567 case 0x50: /* POWER_CTRL */
568 return s
->ulpd_pm_regs
[addr
>> 2];
575 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s
*s
,
576 uint16_t diff
, uint16_t value
)
578 if (diff
& (1 << 4)) /* USB_MCLK_EN */
579 omap_clk_onoff(omap_findclk(s
, "usb_clk0"), (value
>> 4) & 1);
580 if (diff
& (1 << 5)) /* DIS_USB_PVCI_CLK */
581 omap_clk_onoff(omap_findclk(s
, "usb_w2fc_ck"), (~value
>> 5) & 1);
584 static inline void omap_ulpd_req_update(struct omap_mpu_state_s
*s
,
585 uint16_t diff
, uint16_t value
)
587 if (diff
& (1 << 0)) /* SOFT_DPLL_REQ */
588 omap_clk_canidle(omap_findclk(s
, "dpll4"), (~value
>> 0) & 1);
589 if (diff
& (1 << 1)) /* SOFT_COM_REQ */
590 omap_clk_canidle(omap_findclk(s
, "com_mclk_out"), (~value
>> 1) & 1);
591 if (diff
& (1 << 2)) /* SOFT_SDW_REQ */
592 omap_clk_canidle(omap_findclk(s
, "bt_mclk_out"), (~value
>> 2) & 1);
593 if (diff
& (1 << 3)) /* SOFT_USB_REQ */
594 omap_clk_canidle(omap_findclk(s
, "usb_clk0"), (~value
>> 3) & 1);
597 static void omap_ulpd_pm_write(void *opaque
, hwaddr addr
,
598 uint64_t value
, unsigned size
)
600 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
603 static const int bypass_div
[4] = { 1, 2, 4, 4 };
607 omap_badwidth_write16(opaque
, addr
, value
);
612 case 0x00: /* COUNTER_32_LSB */
613 case 0x04: /* COUNTER_32_MSB */
614 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
615 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
616 case 0x14: /* IT_STATUS */
617 case 0x40: /* STATUS_REQ */
621 case 0x10: /* GAUGING_CTRL */
622 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
623 if ((s
->ulpd_pm_regs
[addr
>> 2] ^ value
) & 1) {
624 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
627 s
->ulpd_gauge_start
= now
;
629 now
-= s
->ulpd_gauge_start
;
632 ticks
= muldiv64(now
, 32768, NANOSECONDS_PER_SECOND
);
633 s
->ulpd_pm_regs
[0x00 >> 2] = (ticks
>> 0) & 0xffff;
634 s
->ulpd_pm_regs
[0x04 >> 2] = (ticks
>> 16) & 0xffff;
635 if (ticks
>> 32) /* OVERFLOW_32K */
636 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 2;
638 /* High frequency ticks */
639 ticks
= muldiv64(now
, 12000000, NANOSECONDS_PER_SECOND
);
640 s
->ulpd_pm_regs
[0x08 >> 2] = (ticks
>> 0) & 0xffff;
641 s
->ulpd_pm_regs
[0x0c >> 2] = (ticks
>> 16) & 0xffff;
642 if (ticks
>> 32) /* OVERFLOW_HI_FREQ */
643 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 1;
645 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
646 qemu_irq_raise(qdev_get_gpio_in(s
->ih
[1], OMAP_INT_GAUGE_32K
));
649 s
->ulpd_pm_regs
[addr
>> 2] = value
;
652 case 0x18: /* Reserved */
653 case 0x1c: /* Reserved */
654 case 0x20: /* Reserved */
655 case 0x28: /* Reserved */
656 case 0x2c: /* Reserved */
659 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
660 case 0x38: /* COUNTER_32_FIQ */
661 case 0x48: /* LOCL_TIME */
662 case 0x50: /* POWER_CTRL */
663 s
->ulpd_pm_regs
[addr
>> 2] = value
;
666 case 0x30: /* CLOCK_CTRL */
667 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
668 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x3f;
669 omap_ulpd_clk_update(s
, diff
, value
);
672 case 0x34: /* SOFT_REQ */
673 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
674 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x1f;
675 omap_ulpd_req_update(s
, diff
, value
);
678 case 0x3c: /* DPLL_CTRL */
679 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
680 * omitted altogether, probably a typo. */
681 /* This register has identical semantics with DPLL(1:3) control
682 * registers, see omap_dpll_write() */
683 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
684 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x2fff;
685 if (diff
& (0x3ff << 2)) {
686 if (value
& (1 << 4)) { /* PLL_ENABLE */
687 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
688 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
690 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
693 omap_clk_setrate(omap_findclk(s
, "dpll4"), div
, mult
);
696 /* Enter the desired mode. */
697 s
->ulpd_pm_regs
[addr
>> 2] =
698 (s
->ulpd_pm_regs
[addr
>> 2] & 0xfffe) |
699 ((s
->ulpd_pm_regs
[addr
>> 2] >> 4) & 1);
701 /* Act as if the lock is restored. */
702 s
->ulpd_pm_regs
[addr
>> 2] |= 2;
705 case 0x4c: /* APLL_CTRL */
706 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
707 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0xf;
708 if (diff
& (1 << 0)) /* APLL_NDPLL_SWITCH */
709 omap_clk_reparent(omap_findclk(s
, "ck_48m"), omap_findclk(s
,
710 (value
& (1 << 0)) ? "apll" : "dpll4"));
718 static const MemoryRegionOps omap_ulpd_pm_ops
= {
719 .read
= omap_ulpd_pm_read
,
720 .write
= omap_ulpd_pm_write
,
721 .endianness
= DEVICE_NATIVE_ENDIAN
,
724 static void omap_ulpd_pm_reset(struct omap_mpu_state_s
*mpu
)
726 mpu
->ulpd_pm_regs
[0x00 >> 2] = 0x0001;
727 mpu
->ulpd_pm_regs
[0x04 >> 2] = 0x0000;
728 mpu
->ulpd_pm_regs
[0x08 >> 2] = 0x0001;
729 mpu
->ulpd_pm_regs
[0x0c >> 2] = 0x0000;
730 mpu
->ulpd_pm_regs
[0x10 >> 2] = 0x0000;
731 mpu
->ulpd_pm_regs
[0x18 >> 2] = 0x01;
732 mpu
->ulpd_pm_regs
[0x1c >> 2] = 0x01;
733 mpu
->ulpd_pm_regs
[0x20 >> 2] = 0x01;
734 mpu
->ulpd_pm_regs
[0x24 >> 2] = 0x03ff;
735 mpu
->ulpd_pm_regs
[0x28 >> 2] = 0x01;
736 mpu
->ulpd_pm_regs
[0x2c >> 2] = 0x01;
737 omap_ulpd_clk_update(mpu
, mpu
->ulpd_pm_regs
[0x30 >> 2], 0x0000);
738 mpu
->ulpd_pm_regs
[0x30 >> 2] = 0x0000;
739 omap_ulpd_req_update(mpu
, mpu
->ulpd_pm_regs
[0x34 >> 2], 0x0000);
740 mpu
->ulpd_pm_regs
[0x34 >> 2] = 0x0000;
741 mpu
->ulpd_pm_regs
[0x38 >> 2] = 0x0001;
742 mpu
->ulpd_pm_regs
[0x3c >> 2] = 0x2211;
743 mpu
->ulpd_pm_regs
[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
744 mpu
->ulpd_pm_regs
[0x48 >> 2] = 0x960;
745 mpu
->ulpd_pm_regs
[0x4c >> 2] = 0x08;
746 mpu
->ulpd_pm_regs
[0x50 >> 2] = 0x08;
747 omap_clk_setrate(omap_findclk(mpu
, "dpll4"), 1, 4);
748 omap_clk_reparent(omap_findclk(mpu
, "ck_48m"), omap_findclk(mpu
, "dpll4"));
751 static void omap_ulpd_pm_init(MemoryRegion
*system_memory
,
753 struct omap_mpu_state_s
*mpu
)
755 memory_region_init_io(&mpu
->ulpd_pm_iomem
, NULL
, &omap_ulpd_pm_ops
, mpu
,
756 "omap-ulpd-pm", 0x800);
757 memory_region_add_subregion(system_memory
, base
, &mpu
->ulpd_pm_iomem
);
758 omap_ulpd_pm_reset(mpu
);
761 /* OMAP Pin Configuration */
762 static uint64_t omap_pin_cfg_read(void *opaque
, hwaddr addr
,
765 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
768 return omap_badwidth_read32(opaque
, addr
);
772 case 0x00: /* FUNC_MUX_CTRL_0 */
773 case 0x04: /* FUNC_MUX_CTRL_1 */
774 case 0x08: /* FUNC_MUX_CTRL_2 */
775 return s
->func_mux_ctrl
[addr
>> 2];
777 case 0x0c: /* COMP_MODE_CTRL_0 */
778 return s
->comp_mode_ctrl
[0];
780 case 0x10: /* FUNC_MUX_CTRL_3 */
781 case 0x14: /* FUNC_MUX_CTRL_4 */
782 case 0x18: /* FUNC_MUX_CTRL_5 */
783 case 0x1c: /* FUNC_MUX_CTRL_6 */
784 case 0x20: /* FUNC_MUX_CTRL_7 */
785 case 0x24: /* FUNC_MUX_CTRL_8 */
786 case 0x28: /* FUNC_MUX_CTRL_9 */
787 case 0x2c: /* FUNC_MUX_CTRL_A */
788 case 0x30: /* FUNC_MUX_CTRL_B */
789 case 0x34: /* FUNC_MUX_CTRL_C */
790 case 0x38: /* FUNC_MUX_CTRL_D */
791 return s
->func_mux_ctrl
[(addr
>> 2) - 1];
793 case 0x40: /* PULL_DWN_CTRL_0 */
794 case 0x44: /* PULL_DWN_CTRL_1 */
795 case 0x48: /* PULL_DWN_CTRL_2 */
796 case 0x4c: /* PULL_DWN_CTRL_3 */
797 return s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2];
799 case 0x50: /* GATE_INH_CTRL_0 */
800 return s
->gate_inh_ctrl
[0];
802 case 0x60: /* VOLTAGE_CTRL_0 */
803 return s
->voltage_ctrl
[0];
805 case 0x70: /* TEST_DBG_CTRL_0 */
806 return s
->test_dbg_ctrl
[0];
808 case 0x80: /* MOD_CONF_CTRL_0 */
809 return s
->mod_conf_ctrl
[0];
816 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s
*s
,
817 uint32_t diff
, uint32_t value
)
820 if (diff
& (1 << 9)) /* BLUETOOTH */
821 omap_clk_onoff(omap_findclk(s
, "bt_mclk_out"),
823 if (diff
& (1 << 7)) /* USB.CLKO */
824 omap_clk_onoff(omap_findclk(s
, "usb.clko"),
829 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s
*s
,
830 uint32_t diff
, uint32_t value
)
833 if (diff
& (1U << 31)) {
834 /* MCBSP3_CLK_HIZ_DI */
835 omap_clk_onoff(omap_findclk(s
, "mcbsp3.clkx"), (value
>> 31) & 1);
837 if (diff
& (1 << 1)) {
839 omap_clk_onoff(omap_findclk(s
, "clk32k_out"), (~value
>> 1) & 1);
844 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s
*s
,
845 uint32_t diff
, uint32_t value
)
847 if (diff
& (1U << 31)) {
848 /* CONF_MOD_UART3_CLK_MODE_R */
849 omap_clk_reparent(omap_findclk(s
, "uart3_ck"),
850 omap_findclk(s
, ((value
>> 31) & 1) ?
851 "ck_48m" : "armper_ck"));
853 if (diff
& (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
854 omap_clk_reparent(omap_findclk(s
, "uart2_ck"),
855 omap_findclk(s
, ((value
>> 30) & 1) ?
856 "ck_48m" : "armper_ck"));
857 if (diff
& (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
858 omap_clk_reparent(omap_findclk(s
, "uart1_ck"),
859 omap_findclk(s
, ((value
>> 29) & 1) ?
860 "ck_48m" : "armper_ck"));
861 if (diff
& (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
862 omap_clk_reparent(omap_findclk(s
, "mmc_ck"),
863 omap_findclk(s
, ((value
>> 23) & 1) ?
864 "ck_48m" : "armper_ck"));
865 if (diff
& (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
866 omap_clk_reparent(omap_findclk(s
, "com_mclk_out"),
867 omap_findclk(s
, ((value
>> 12) & 1) ?
868 "ck_48m" : "armper_ck"));
869 if (diff
& (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
870 omap_clk_onoff(omap_findclk(s
, "usb_hhc_ck"), (value
>> 9) & 1);
873 static void omap_pin_cfg_write(void *opaque
, hwaddr addr
,
874 uint64_t value
, unsigned size
)
876 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
880 omap_badwidth_write32(opaque
, addr
, value
);
885 case 0x00: /* FUNC_MUX_CTRL_0 */
886 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
887 s
->func_mux_ctrl
[addr
>> 2] = value
;
888 omap_pin_funcmux0_update(s
, diff
, value
);
891 case 0x04: /* FUNC_MUX_CTRL_1 */
892 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
893 s
->func_mux_ctrl
[addr
>> 2] = value
;
894 omap_pin_funcmux1_update(s
, diff
, value
);
897 case 0x08: /* FUNC_MUX_CTRL_2 */
898 s
->func_mux_ctrl
[addr
>> 2] = value
;
901 case 0x0c: /* COMP_MODE_CTRL_0 */
902 s
->comp_mode_ctrl
[0] = value
;
903 s
->compat1509
= (value
!= 0x0000eaef);
904 omap_pin_funcmux0_update(s
, ~0, s
->func_mux_ctrl
[0]);
905 omap_pin_funcmux1_update(s
, ~0, s
->func_mux_ctrl
[1]);
908 case 0x10: /* FUNC_MUX_CTRL_3 */
909 case 0x14: /* FUNC_MUX_CTRL_4 */
910 case 0x18: /* FUNC_MUX_CTRL_5 */
911 case 0x1c: /* FUNC_MUX_CTRL_6 */
912 case 0x20: /* FUNC_MUX_CTRL_7 */
913 case 0x24: /* FUNC_MUX_CTRL_8 */
914 case 0x28: /* FUNC_MUX_CTRL_9 */
915 case 0x2c: /* FUNC_MUX_CTRL_A */
916 case 0x30: /* FUNC_MUX_CTRL_B */
917 case 0x34: /* FUNC_MUX_CTRL_C */
918 case 0x38: /* FUNC_MUX_CTRL_D */
919 s
->func_mux_ctrl
[(addr
>> 2) - 1] = value
;
922 case 0x40: /* PULL_DWN_CTRL_0 */
923 case 0x44: /* PULL_DWN_CTRL_1 */
924 case 0x48: /* PULL_DWN_CTRL_2 */
925 case 0x4c: /* PULL_DWN_CTRL_3 */
926 s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2] = value
;
929 case 0x50: /* GATE_INH_CTRL_0 */
930 s
->gate_inh_ctrl
[0] = value
;
933 case 0x60: /* VOLTAGE_CTRL_0 */
934 s
->voltage_ctrl
[0] = value
;
937 case 0x70: /* TEST_DBG_CTRL_0 */
938 s
->test_dbg_ctrl
[0] = value
;
941 case 0x80: /* MOD_CONF_CTRL_0 */
942 diff
= s
->mod_conf_ctrl
[0] ^ value
;
943 s
->mod_conf_ctrl
[0] = value
;
944 omap_pin_modconf1_update(s
, diff
, value
);
952 static const MemoryRegionOps omap_pin_cfg_ops
= {
953 .read
= omap_pin_cfg_read
,
954 .write
= omap_pin_cfg_write
,
955 .endianness
= DEVICE_NATIVE_ENDIAN
,
958 static void omap_pin_cfg_reset(struct omap_mpu_state_s
*mpu
)
960 /* Start in Compatibility Mode. */
962 omap_pin_funcmux0_update(mpu
, mpu
->func_mux_ctrl
[0], 0);
963 omap_pin_funcmux1_update(mpu
, mpu
->func_mux_ctrl
[1], 0);
964 omap_pin_modconf1_update(mpu
, mpu
->mod_conf_ctrl
[0], 0);
965 memset(mpu
->func_mux_ctrl
, 0, sizeof(mpu
->func_mux_ctrl
));
966 memset(mpu
->comp_mode_ctrl
, 0, sizeof(mpu
->comp_mode_ctrl
));
967 memset(mpu
->pull_dwn_ctrl
, 0, sizeof(mpu
->pull_dwn_ctrl
));
968 memset(mpu
->gate_inh_ctrl
, 0, sizeof(mpu
->gate_inh_ctrl
));
969 memset(mpu
->voltage_ctrl
, 0, sizeof(mpu
->voltage_ctrl
));
970 memset(mpu
->test_dbg_ctrl
, 0, sizeof(mpu
->test_dbg_ctrl
));
971 memset(mpu
->mod_conf_ctrl
, 0, sizeof(mpu
->mod_conf_ctrl
));
974 static void omap_pin_cfg_init(MemoryRegion
*system_memory
,
976 struct omap_mpu_state_s
*mpu
)
978 memory_region_init_io(&mpu
->pin_cfg_iomem
, NULL
, &omap_pin_cfg_ops
, mpu
,
979 "omap-pin-cfg", 0x800);
980 memory_region_add_subregion(system_memory
, base
, &mpu
->pin_cfg_iomem
);
981 omap_pin_cfg_reset(mpu
);
984 /* Device Identification, Die Identification */
985 static uint64_t omap_id_read(void *opaque
, hwaddr addr
,
988 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
991 return omap_badwidth_read32(opaque
, addr
);
995 case 0xfffe1800: /* DIE_ID_LSB */
997 case 0xfffe1804: /* DIE_ID_MSB */
1000 case 0xfffe2000: /* PRODUCT_ID_LSB */
1002 case 0xfffe2004: /* PRODUCT_ID_MSB */
1005 case 0xfffed400: /* JTAG_ID_LSB */
1006 switch (s
->mpu_model
) {
1012 hw_error("%s: bad mpu model\n", __func__
);
1016 case 0xfffed404: /* JTAG_ID_MSB */
1017 switch (s
->mpu_model
) {
1023 hw_error("%s: bad mpu model\n", __func__
);
1032 static void omap_id_write(void *opaque
, hwaddr addr
,
1033 uint64_t value
, unsigned size
)
1036 omap_badwidth_write32(opaque
, addr
, value
);
1043 static const MemoryRegionOps omap_id_ops
= {
1044 .read
= omap_id_read
,
1045 .write
= omap_id_write
,
1046 .endianness
= DEVICE_NATIVE_ENDIAN
,
1049 static void omap_id_init(MemoryRegion
*memory
, struct omap_mpu_state_s
*mpu
)
1051 memory_region_init_io(&mpu
->id_iomem
, NULL
, &omap_id_ops
, mpu
,
1052 "omap-id", 0x100000000ULL
);
1053 memory_region_init_alias(&mpu
->id_iomem_e18
, NULL
, "omap-id-e18", &mpu
->id_iomem
,
1055 memory_region_add_subregion(memory
, 0xfffe1800, &mpu
->id_iomem_e18
);
1056 memory_region_init_alias(&mpu
->id_iomem_ed4
, NULL
, "omap-id-ed4", &mpu
->id_iomem
,
1058 memory_region_add_subregion(memory
, 0xfffed400, &mpu
->id_iomem_ed4
);
1059 if (!cpu_is_omap15xx(mpu
)) {
1060 memory_region_init_alias(&mpu
->id_iomem_ed4
, NULL
, "omap-id-e20",
1061 &mpu
->id_iomem
, 0xfffe2000, 0x800);
1062 memory_region_add_subregion(memory
, 0xfffe2000, &mpu
->id_iomem_e20
);
1066 /* MPUI Control (Dummy) */
1067 static uint64_t omap_mpui_read(void *opaque
, hwaddr addr
,
1070 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1073 return omap_badwidth_read32(opaque
, addr
);
1077 case 0x00: /* CTRL */
1078 return s
->mpui_ctrl
;
1079 case 0x04: /* DEBUG_ADDR */
1081 case 0x08: /* DEBUG_DATA */
1083 case 0x0c: /* DEBUG_FLAG */
1085 case 0x10: /* STATUS */
1088 /* Not in OMAP310 */
1089 case 0x14: /* DSP_STATUS */
1090 case 0x18: /* DSP_BOOT_CONFIG */
1092 case 0x1c: /* DSP_MPUI_CONFIG */
1100 static void omap_mpui_write(void *opaque
, hwaddr addr
,
1101 uint64_t value
, unsigned size
)
1103 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1106 omap_badwidth_write32(opaque
, addr
, value
);
1111 case 0x00: /* CTRL */
1112 s
->mpui_ctrl
= value
& 0x007fffff;
1115 case 0x04: /* DEBUG_ADDR */
1116 case 0x08: /* DEBUG_DATA */
1117 case 0x0c: /* DEBUG_FLAG */
1118 case 0x10: /* STATUS */
1119 /* Not in OMAP310 */
1120 case 0x14: /* DSP_STATUS */
1123 case 0x18: /* DSP_BOOT_CONFIG */
1124 case 0x1c: /* DSP_MPUI_CONFIG */
1132 static const MemoryRegionOps omap_mpui_ops
= {
1133 .read
= omap_mpui_read
,
1134 .write
= omap_mpui_write
,
1135 .endianness
= DEVICE_NATIVE_ENDIAN
,
1138 static void omap_mpui_reset(struct omap_mpu_state_s
*s
)
1140 s
->mpui_ctrl
= 0x0003ff1b;
1143 static void omap_mpui_init(MemoryRegion
*memory
, hwaddr base
,
1144 struct omap_mpu_state_s
*mpu
)
1146 memory_region_init_io(&mpu
->mpui_iomem
, NULL
, &omap_mpui_ops
, mpu
,
1147 "omap-mpui", 0x100);
1148 memory_region_add_subregion(memory
, base
, &mpu
->mpui_iomem
);
1150 omap_mpui_reset(mpu
);
1154 struct omap_tipb_bridge_s
{
1162 uint16_t enh_control
;
1165 static uint64_t omap_tipb_bridge_read(void *opaque
, hwaddr addr
,
1168 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1171 return omap_badwidth_read16(opaque
, addr
);
1175 case 0x00: /* TIPB_CNTL */
1177 case 0x04: /* TIPB_BUS_ALLOC */
1179 case 0x08: /* MPU_TIPB_CNTL */
1181 case 0x0c: /* ENHANCED_TIPB_CNTL */
1182 return s
->enh_control
;
1183 case 0x10: /* ADDRESS_DBG */
1184 case 0x14: /* DATA_DEBUG_LOW */
1185 case 0x18: /* DATA_DEBUG_HIGH */
1187 case 0x1c: /* DEBUG_CNTR_SIG */
1195 static void omap_tipb_bridge_write(void *opaque
, hwaddr addr
,
1196 uint64_t value
, unsigned size
)
1198 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1201 omap_badwidth_write16(opaque
, addr
, value
);
1206 case 0x00: /* TIPB_CNTL */
1207 s
->control
= value
& 0xffff;
1210 case 0x04: /* TIPB_BUS_ALLOC */
1211 s
->alloc
= value
& 0x003f;
1214 case 0x08: /* MPU_TIPB_CNTL */
1215 s
->buffer
= value
& 0x0003;
1218 case 0x0c: /* ENHANCED_TIPB_CNTL */
1219 s
->width_intr
= !(value
& 2);
1220 s
->enh_control
= value
& 0x000f;
1223 case 0x10: /* ADDRESS_DBG */
1224 case 0x14: /* DATA_DEBUG_LOW */
1225 case 0x18: /* DATA_DEBUG_HIGH */
1226 case 0x1c: /* DEBUG_CNTR_SIG */
1235 static const MemoryRegionOps omap_tipb_bridge_ops
= {
1236 .read
= omap_tipb_bridge_read
,
1237 .write
= omap_tipb_bridge_write
,
1238 .endianness
= DEVICE_NATIVE_ENDIAN
,
1241 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s
*s
)
1243 s
->control
= 0xffff;
1246 s
->enh_control
= 0x000f;
1249 static struct omap_tipb_bridge_s
*omap_tipb_bridge_init(
1250 MemoryRegion
*memory
, hwaddr base
,
1251 qemu_irq abort_irq
, omap_clk clk
)
1253 struct omap_tipb_bridge_s
*s
= g_new0(struct omap_tipb_bridge_s
, 1);
1255 s
->abort
= abort_irq
;
1256 omap_tipb_bridge_reset(s
);
1258 memory_region_init_io(&s
->iomem
, NULL
, &omap_tipb_bridge_ops
, s
,
1259 "omap-tipb-bridge", 0x100);
1260 memory_region_add_subregion(memory
, base
, &s
->iomem
);
1265 /* Dummy Traffic Controller's Memory Interface */
1266 static uint64_t omap_tcmi_read(void *opaque
, hwaddr addr
,
1269 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1273 return omap_badwidth_read32(opaque
, addr
);
1277 case 0x00: /* IMIF_PRIO */
1278 case 0x04: /* EMIFS_PRIO */
1279 case 0x08: /* EMIFF_PRIO */
1280 case 0x0c: /* EMIFS_CONFIG */
1281 case 0x10: /* EMIFS_CS0_CONFIG */
1282 case 0x14: /* EMIFS_CS1_CONFIG */
1283 case 0x18: /* EMIFS_CS2_CONFIG */
1284 case 0x1c: /* EMIFS_CS3_CONFIG */
1285 case 0x24: /* EMIFF_MRS */
1286 case 0x28: /* TIMEOUT1 */
1287 case 0x2c: /* TIMEOUT2 */
1288 case 0x30: /* TIMEOUT3 */
1289 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1290 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1291 return s
->tcmi_regs
[addr
>> 2];
1293 case 0x20: /* EMIFF_SDRAM_CONFIG */
1294 ret
= s
->tcmi_regs
[addr
>> 2];
1295 s
->tcmi_regs
[addr
>> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1296 /* XXX: We can try using the VGA_DIRTY flag for this */
1304 static void omap_tcmi_write(void *opaque
, hwaddr addr
,
1305 uint64_t value
, unsigned size
)
1307 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1310 omap_badwidth_write32(opaque
, addr
, value
);
1315 case 0x00: /* IMIF_PRIO */
1316 case 0x04: /* EMIFS_PRIO */
1317 case 0x08: /* EMIFF_PRIO */
1318 case 0x10: /* EMIFS_CS0_CONFIG */
1319 case 0x14: /* EMIFS_CS1_CONFIG */
1320 case 0x18: /* EMIFS_CS2_CONFIG */
1321 case 0x1c: /* EMIFS_CS3_CONFIG */
1322 case 0x20: /* EMIFF_SDRAM_CONFIG */
1323 case 0x24: /* EMIFF_MRS */
1324 case 0x28: /* TIMEOUT1 */
1325 case 0x2c: /* TIMEOUT2 */
1326 case 0x30: /* TIMEOUT3 */
1327 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1328 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1329 s
->tcmi_regs
[addr
>> 2] = value
;
1331 case 0x0c: /* EMIFS_CONFIG */
1332 s
->tcmi_regs
[addr
>> 2] = (value
& 0xf) | (1 << 4);
1340 static const MemoryRegionOps omap_tcmi_ops
= {
1341 .read
= omap_tcmi_read
,
1342 .write
= omap_tcmi_write
,
1343 .endianness
= DEVICE_NATIVE_ENDIAN
,
1346 static void omap_tcmi_reset(struct omap_mpu_state_s
*mpu
)
1348 mpu
->tcmi_regs
[0x00 >> 2] = 0x00000000;
1349 mpu
->tcmi_regs
[0x04 >> 2] = 0x00000000;
1350 mpu
->tcmi_regs
[0x08 >> 2] = 0x00000000;
1351 mpu
->tcmi_regs
[0x0c >> 2] = 0x00000010;
1352 mpu
->tcmi_regs
[0x10 >> 2] = 0x0010fffb;
1353 mpu
->tcmi_regs
[0x14 >> 2] = 0x0010fffb;
1354 mpu
->tcmi_regs
[0x18 >> 2] = 0x0010fffb;
1355 mpu
->tcmi_regs
[0x1c >> 2] = 0x0010fffb;
1356 mpu
->tcmi_regs
[0x20 >> 2] = 0x00618800;
1357 mpu
->tcmi_regs
[0x24 >> 2] = 0x00000037;
1358 mpu
->tcmi_regs
[0x28 >> 2] = 0x00000000;
1359 mpu
->tcmi_regs
[0x2c >> 2] = 0x00000000;
1360 mpu
->tcmi_regs
[0x30 >> 2] = 0x00000000;
1361 mpu
->tcmi_regs
[0x3c >> 2] = 0x00000003;
1362 mpu
->tcmi_regs
[0x40 >> 2] = 0x00000000;
1365 static void omap_tcmi_init(MemoryRegion
*memory
, hwaddr base
,
1366 struct omap_mpu_state_s
*mpu
)
1368 memory_region_init_io(&mpu
->tcmi_iomem
, NULL
, &omap_tcmi_ops
, mpu
,
1369 "omap-tcmi", 0x100);
1370 memory_region_add_subregion(memory
, base
, &mpu
->tcmi_iomem
);
1371 omap_tcmi_reset(mpu
);
1374 /* Digital phase-locked loops control */
1381 static uint64_t omap_dpll_read(void *opaque
, hwaddr addr
,
1384 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1387 return omap_badwidth_read16(opaque
, addr
);
1390 if (addr
== 0x00) /* CTL_REG */
1397 static void omap_dpll_write(void *opaque
, hwaddr addr
,
1398 uint64_t value
, unsigned size
)
1400 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1402 static const int bypass_div
[4] = { 1, 2, 4, 4 };
1406 omap_badwidth_write16(opaque
, addr
, value
);
1410 if (addr
== 0x00) { /* CTL_REG */
1411 /* See omap_ulpd_pm_write() too */
1412 diff
= s
->mode
& value
;
1413 s
->mode
= value
& 0x2fff;
1414 if (diff
& (0x3ff << 2)) {
1415 if (value
& (1 << 4)) { /* PLL_ENABLE */
1416 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
1417 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
1419 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
1422 omap_clk_setrate(s
->dpll
, div
, mult
);
1425 /* Enter the desired mode. */
1426 s
->mode
= (s
->mode
& 0xfffe) | ((s
->mode
>> 4) & 1);
1428 /* Act as if the lock is restored. */
1435 static const MemoryRegionOps omap_dpll_ops
= {
1436 .read
= omap_dpll_read
,
1437 .write
= omap_dpll_write
,
1438 .endianness
= DEVICE_NATIVE_ENDIAN
,
1441 static void omap_dpll_reset(struct dpll_ctl_s
*s
)
1444 omap_clk_setrate(s
->dpll
, 1, 1);
1447 static struct dpll_ctl_s
*omap_dpll_init(MemoryRegion
*memory
,
1448 hwaddr base
, omap_clk clk
)
1450 struct dpll_ctl_s
*s
= g_malloc0(sizeof(*s
));
1451 memory_region_init_io(&s
->iomem
, NULL
, &omap_dpll_ops
, s
, "omap-dpll", 0x100);
1456 memory_region_add_subregion(memory
, base
, &s
->iomem
);
1460 /* MPU Clock/Reset/Power Mode Control */
1461 static uint64_t omap_clkm_read(void *opaque
, hwaddr addr
,
1464 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1467 return omap_badwidth_read16(opaque
, addr
);
1471 case 0x00: /* ARM_CKCTL */
1472 return s
->clkm
.arm_ckctl
;
1474 case 0x04: /* ARM_IDLECT1 */
1475 return s
->clkm
.arm_idlect1
;
1477 case 0x08: /* ARM_IDLECT2 */
1478 return s
->clkm
.arm_idlect2
;
1480 case 0x0c: /* ARM_EWUPCT */
1481 return s
->clkm
.arm_ewupct
;
1483 case 0x10: /* ARM_RSTCT1 */
1484 return s
->clkm
.arm_rstct1
;
1486 case 0x14: /* ARM_RSTCT2 */
1487 return s
->clkm
.arm_rstct2
;
1489 case 0x18: /* ARM_SYSST */
1490 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
;
1492 case 0x1c: /* ARM_CKOUT1 */
1493 return s
->clkm
.arm_ckout1
;
1495 case 0x20: /* ARM_CKOUT2 */
1503 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s
*s
,
1504 uint16_t diff
, uint16_t value
)
1508 if (diff
& (1 << 14)) { /* ARM_INTHCK_SEL */
1509 if (value
& (1 << 14))
1512 clk
= omap_findclk(s
, "arminth_ck");
1513 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
1516 if (diff
& (1 << 12)) { /* ARM_TIMXO */
1517 clk
= omap_findclk(s
, "armtim_ck");
1518 if (value
& (1 << 12))
1519 omap_clk_reparent(clk
, omap_findclk(s
, "clkin"));
1521 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
1524 if (diff
& (3 << 10)) { /* DSPMMUDIV */
1525 clk
= omap_findclk(s
, "dspmmu_ck");
1526 omap_clk_setrate(clk
, 1 << ((value
>> 10) & 3), 1);
1528 if (diff
& (3 << 8)) { /* TCDIV */
1529 clk
= omap_findclk(s
, "tc_ck");
1530 omap_clk_setrate(clk
, 1 << ((value
>> 8) & 3), 1);
1532 if (diff
& (3 << 6)) { /* DSPDIV */
1533 clk
= omap_findclk(s
, "dsp_ck");
1534 omap_clk_setrate(clk
, 1 << ((value
>> 6) & 3), 1);
1536 if (diff
& (3 << 4)) { /* ARMDIV */
1537 clk
= omap_findclk(s
, "arm_ck");
1538 omap_clk_setrate(clk
, 1 << ((value
>> 4) & 3), 1);
1540 if (diff
& (3 << 2)) { /* LCDDIV */
1541 clk
= omap_findclk(s
, "lcd_ck");
1542 omap_clk_setrate(clk
, 1 << ((value
>> 2) & 3), 1);
1544 if (diff
& (3 << 0)) { /* PERDIV */
1545 clk
= omap_findclk(s
, "armper_ck");
1546 omap_clk_setrate(clk
, 1 << ((value
>> 0) & 3), 1);
1550 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s
*s
,
1551 uint16_t diff
, uint16_t value
)
1555 if (value
& (1 << 11)) { /* SETARM_IDLE */
1556 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
1558 if (!(value
& (1 << 10))) { /* WKUP_MODE */
1559 /* XXX: disable wakeup from IRQ */
1560 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
1563 #define SET_CANIDLE(clock, bit) \
1564 if (diff & (1 << bit)) { \
1565 clk = omap_findclk(s, clock); \
1566 omap_clk_canidle(clk, (value >> bit) & 1); \
1568 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1569 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1570 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1571 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1572 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1573 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1574 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1575 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1576 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1577 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1578 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1579 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1580 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1581 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1584 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s
*s
,
1585 uint16_t diff
, uint16_t value
)
1589 #define SET_ONOFF(clock, bit) \
1590 if (diff & (1 << bit)) { \
1591 clk = omap_findclk(s, clock); \
1592 omap_clk_onoff(clk, (value >> bit) & 1); \
1594 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1595 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1596 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1597 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1598 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1599 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1600 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1601 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1602 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1603 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1604 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1607 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s
*s
,
1608 uint16_t diff
, uint16_t value
)
1612 if (diff
& (3 << 4)) { /* TCLKOUT */
1613 clk
= omap_findclk(s
, "tclk_out");
1614 switch ((value
>> 4) & 3) {
1616 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen3"));
1617 omap_clk_onoff(clk
, 1);
1620 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
1621 omap_clk_onoff(clk
, 1);
1624 omap_clk_onoff(clk
, 0);
1627 if (diff
& (3 << 2)) { /* DCLKOUT */
1628 clk
= omap_findclk(s
, "dclk_out");
1629 switch ((value
>> 2) & 3) {
1631 omap_clk_reparent(clk
, omap_findclk(s
, "dspmmu_ck"));
1634 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen2"));
1637 omap_clk_reparent(clk
, omap_findclk(s
, "dsp_ck"));
1640 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
1644 if (diff
& (3 << 0)) { /* ACLKOUT */
1645 clk
= omap_findclk(s
, "aclk_out");
1646 switch ((value
>> 0) & 3) {
1648 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
1649 omap_clk_onoff(clk
, 1);
1652 omap_clk_reparent(clk
, omap_findclk(s
, "arm_ck"));
1653 omap_clk_onoff(clk
, 1);
1656 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
1657 omap_clk_onoff(clk
, 1);
1660 omap_clk_onoff(clk
, 0);
1665 static void omap_clkm_write(void *opaque
, hwaddr addr
,
1666 uint64_t value
, unsigned size
)
1668 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1671 static const char *clkschemename
[8] = {
1672 "fully synchronous", "fully asynchronous", "synchronous scalable",
1673 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1677 omap_badwidth_write16(opaque
, addr
, value
);
1682 case 0x00: /* ARM_CKCTL */
1683 diff
= s
->clkm
.arm_ckctl
^ value
;
1684 s
->clkm
.arm_ckctl
= value
& 0x7fff;
1685 omap_clkm_ckctl_update(s
, diff
, value
);
1688 case 0x04: /* ARM_IDLECT1 */
1689 diff
= s
->clkm
.arm_idlect1
^ value
;
1690 s
->clkm
.arm_idlect1
= value
& 0x0fff;
1691 omap_clkm_idlect1_update(s
, diff
, value
);
1694 case 0x08: /* ARM_IDLECT2 */
1695 diff
= s
->clkm
.arm_idlect2
^ value
;
1696 s
->clkm
.arm_idlect2
= value
& 0x07ff;
1697 omap_clkm_idlect2_update(s
, diff
, value
);
1700 case 0x0c: /* ARM_EWUPCT */
1701 s
->clkm
.arm_ewupct
= value
& 0x003f;
1704 case 0x10: /* ARM_RSTCT1 */
1705 diff
= s
->clkm
.arm_rstct1
^ value
;
1706 s
->clkm
.arm_rstct1
= value
& 0x0007;
1708 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
1709 s
->clkm
.cold_start
= 0xa;
1711 if (diff
& ~value
& 4) { /* DSP_RST */
1713 omap_tipb_bridge_reset(s
->private_tipb
);
1714 omap_tipb_bridge_reset(s
->public_tipb
);
1716 if (diff
& 2) { /* DSP_EN */
1717 clk
= omap_findclk(s
, "dsp_ck");
1718 omap_clk_canidle(clk
, (~value
>> 1) & 1);
1722 case 0x14: /* ARM_RSTCT2 */
1723 s
->clkm
.arm_rstct2
= value
& 0x0001;
1726 case 0x18: /* ARM_SYSST */
1727 if ((s
->clkm
.clocking_scheme
^ (value
>> 11)) & 7) {
1728 s
->clkm
.clocking_scheme
= (value
>> 11) & 7;
1729 printf("%s: clocking scheme set to %s\n", __func__
,
1730 clkschemename
[s
->clkm
.clocking_scheme
]);
1732 s
->clkm
.cold_start
&= value
& 0x3f;
1735 case 0x1c: /* ARM_CKOUT1 */
1736 diff
= s
->clkm
.arm_ckout1
^ value
;
1737 s
->clkm
.arm_ckout1
= value
& 0x003f;
1738 omap_clkm_ckout1_update(s
, diff
, value
);
1741 case 0x20: /* ARM_CKOUT2 */
1747 static const MemoryRegionOps omap_clkm_ops
= {
1748 .read
= omap_clkm_read
,
1749 .write
= omap_clkm_write
,
1750 .endianness
= DEVICE_NATIVE_ENDIAN
,
1753 static uint64_t omap_clkdsp_read(void *opaque
, hwaddr addr
,
1756 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1757 CPUState
*cpu
= CPU(s
->cpu
);
1760 return omap_badwidth_read16(opaque
, addr
);
1764 case 0x04: /* DSP_IDLECT1 */
1765 return s
->clkm
.dsp_idlect1
;
1767 case 0x08: /* DSP_IDLECT2 */
1768 return s
->clkm
.dsp_idlect2
;
1770 case 0x14: /* DSP_RSTCT2 */
1771 return s
->clkm
.dsp_rstct2
;
1773 case 0x18: /* DSP_SYSST */
1775 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
|
1776 (cpu
->halted
<< 6); /* Quite useless... */
1783 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s
*s
,
1784 uint16_t diff
, uint16_t value
)
1788 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1791 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s
*s
,
1792 uint16_t diff
, uint16_t value
)
1796 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1799 static void omap_clkdsp_write(void *opaque
, hwaddr addr
,
1800 uint64_t value
, unsigned size
)
1802 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1806 omap_badwidth_write16(opaque
, addr
, value
);
1811 case 0x04: /* DSP_IDLECT1 */
1812 diff
= s
->clkm
.dsp_idlect1
^ value
;
1813 s
->clkm
.dsp_idlect1
= value
& 0x01f7;
1814 omap_clkdsp_idlect1_update(s
, diff
, value
);
1817 case 0x08: /* DSP_IDLECT2 */
1818 s
->clkm
.dsp_idlect2
= value
& 0x0037;
1819 diff
= s
->clkm
.dsp_idlect1
^ value
;
1820 omap_clkdsp_idlect2_update(s
, diff
, value
);
1823 case 0x14: /* DSP_RSTCT2 */
1824 s
->clkm
.dsp_rstct2
= value
& 0x0001;
1827 case 0x18: /* DSP_SYSST */
1828 s
->clkm
.cold_start
&= value
& 0x3f;
1836 static const MemoryRegionOps omap_clkdsp_ops
= {
1837 .read
= omap_clkdsp_read
,
1838 .write
= omap_clkdsp_write
,
1839 .endianness
= DEVICE_NATIVE_ENDIAN
,
1842 static void omap_clkm_reset(struct omap_mpu_state_s
*s
)
1844 if (s
->wdt
&& s
->wdt
->reset
)
1845 s
->clkm
.cold_start
= 0x6;
1846 s
->clkm
.clocking_scheme
= 0;
1847 omap_clkm_ckctl_update(s
, ~0, 0x3000);
1848 s
->clkm
.arm_ckctl
= 0x3000;
1849 omap_clkm_idlect1_update(s
, s
->clkm
.arm_idlect1
^ 0x0400, 0x0400);
1850 s
->clkm
.arm_idlect1
= 0x0400;
1851 omap_clkm_idlect2_update(s
, s
->clkm
.arm_idlect2
^ 0x0100, 0x0100);
1852 s
->clkm
.arm_idlect2
= 0x0100;
1853 s
->clkm
.arm_ewupct
= 0x003f;
1854 s
->clkm
.arm_rstct1
= 0x0000;
1855 s
->clkm
.arm_rstct2
= 0x0000;
1856 s
->clkm
.arm_ckout1
= 0x0015;
1857 s
->clkm
.dpll1_mode
= 0x2002;
1858 omap_clkdsp_idlect1_update(s
, s
->clkm
.dsp_idlect1
^ 0x0040, 0x0040);
1859 s
->clkm
.dsp_idlect1
= 0x0040;
1860 omap_clkdsp_idlect2_update(s
, ~0, 0x0000);
1861 s
->clkm
.dsp_idlect2
= 0x0000;
1862 s
->clkm
.dsp_rstct2
= 0x0000;
1865 static void omap_clkm_init(MemoryRegion
*memory
, hwaddr mpu_base
,
1866 hwaddr dsp_base
, struct omap_mpu_state_s
*s
)
1868 memory_region_init_io(&s
->clkm_iomem
, NULL
, &omap_clkm_ops
, s
,
1869 "omap-clkm", 0x100);
1870 memory_region_init_io(&s
->clkdsp_iomem
, NULL
, &omap_clkdsp_ops
, s
,
1871 "omap-clkdsp", 0x1000);
1873 s
->clkm
.arm_idlect1
= 0x03ff;
1874 s
->clkm
.arm_idlect2
= 0x0100;
1875 s
->clkm
.dsp_idlect1
= 0x0002;
1877 s
->clkm
.cold_start
= 0x3a;
1879 memory_region_add_subregion(memory
, mpu_base
, &s
->clkm_iomem
);
1880 memory_region_add_subregion(memory
, dsp_base
, &s
->clkdsp_iomem
);
1884 struct omap_mpuio_s
{
1888 qemu_irq handler
[16];
1910 static void omap_mpuio_set(void *opaque
, int line
, int level
)
1912 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1913 uint16_t prev
= s
->inputs
;
1916 s
->inputs
|= 1 << line
;
1918 s
->inputs
&= ~(1 << line
);
1920 if (((1 << line
) & s
->dir
& ~s
->mask
) && s
->clk
) {
1921 if ((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) {
1922 s
->ints
|= 1 << line
;
1923 qemu_irq_raise(s
->irq
);
1926 if ((s
->event
& (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1927 (s
->event
>> 1) == line
) /* PIN_SELECT */
1928 s
->latch
= s
->inputs
;
1932 static void omap_mpuio_kbd_update(struct omap_mpuio_s
*s
)
1935 uint8_t *row
, rows
= 0, cols
= ~s
->cols
;
1937 for (row
= s
->buttons
+ 4, i
= 1 << 4; i
; row
--, i
>>= 1)
1941 qemu_set_irq(s
->kbd_irq
, rows
&& !s
->kbd_mask
&& s
->clk
);
1942 s
->row_latch
= ~rows
;
1945 static uint64_t omap_mpuio_read(void *opaque
, hwaddr addr
,
1948 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1949 int offset
= addr
& OMAP_MPUI_REG_MASK
;
1953 return omap_badwidth_read16(opaque
, addr
);
1957 case 0x00: /* INPUT_LATCH */
1960 case 0x04: /* OUTPUT_REG */
1963 case 0x08: /* IO_CNTL */
1966 case 0x10: /* KBR_LATCH */
1967 return s
->row_latch
;
1969 case 0x14: /* KBC_REG */
1972 case 0x18: /* GPIO_EVENT_MODE_REG */
1975 case 0x1c: /* GPIO_INT_EDGE_REG */
1978 case 0x20: /* KBD_INT */
1979 return (~s
->row_latch
& 0x1f) && !s
->kbd_mask
;
1981 case 0x24: /* GPIO_INT */
1985 qemu_irq_lower(s
->irq
);
1988 case 0x28: /* KBD_MASKIT */
1991 case 0x2c: /* GPIO_MASKIT */
1994 case 0x30: /* GPIO_DEBOUNCING_REG */
1997 case 0x34: /* GPIO_LATCH_REG */
2005 static void omap_mpuio_write(void *opaque
, hwaddr addr
,
2006 uint64_t value
, unsigned size
)
2008 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2009 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2014 omap_badwidth_write16(opaque
, addr
, value
);
2019 case 0x04: /* OUTPUT_REG */
2020 diff
= (s
->outputs
^ value
) & ~s
->dir
;
2022 while ((ln
= ctz32(diff
)) != 32) {
2024 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2029 case 0x08: /* IO_CNTL */
2030 diff
= s
->outputs
& (s
->dir
^ value
);
2033 value
= s
->outputs
& ~s
->dir
;
2034 while ((ln
= ctz32(diff
)) != 32) {
2036 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2041 case 0x14: /* KBC_REG */
2043 omap_mpuio_kbd_update(s
);
2046 case 0x18: /* GPIO_EVENT_MODE_REG */
2047 s
->event
= value
& 0x1f;
2050 case 0x1c: /* GPIO_INT_EDGE_REG */
2054 case 0x28: /* KBD_MASKIT */
2055 s
->kbd_mask
= value
& 1;
2056 omap_mpuio_kbd_update(s
);
2059 case 0x2c: /* GPIO_MASKIT */
2063 case 0x30: /* GPIO_DEBOUNCING_REG */
2064 s
->debounce
= value
& 0x1ff;
2067 case 0x00: /* INPUT_LATCH */
2068 case 0x10: /* KBR_LATCH */
2069 case 0x20: /* KBD_INT */
2070 case 0x24: /* GPIO_INT */
2071 case 0x34: /* GPIO_LATCH_REG */
2081 static const MemoryRegionOps omap_mpuio_ops
= {
2082 .read
= omap_mpuio_read
,
2083 .write
= omap_mpuio_write
,
2084 .endianness
= DEVICE_NATIVE_ENDIAN
,
2087 static void omap_mpuio_reset(struct omap_mpuio_s
*s
)
2099 s
->row_latch
= 0x1f;
2103 static void omap_mpuio_onoff(void *opaque
, int line
, int on
)
2105 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2109 omap_mpuio_kbd_update(s
);
2112 static struct omap_mpuio_s
*omap_mpuio_init(MemoryRegion
*memory
,
2114 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
2117 struct omap_mpuio_s
*s
= g_new0(struct omap_mpuio_s
, 1);
2120 s
->kbd_irq
= kbd_int
;
2122 s
->in
= qemu_allocate_irqs(omap_mpuio_set
, s
, 16);
2123 omap_mpuio_reset(s
);
2125 memory_region_init_io(&s
->iomem
, NULL
, &omap_mpuio_ops
, s
,
2126 "omap-mpuio", 0x800);
2127 memory_region_add_subregion(memory
, base
, &s
->iomem
);
2129 omap_clk_adduser(clk
, qemu_allocate_irq(omap_mpuio_onoff
, s
, 0));
2134 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
)
2139 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
)
2141 if (line
>= 16 || line
< 0)
2142 hw_error("%s: No GPIO line %i\n", __func__
, line
);
2143 s
->handler
[line
] = handler
;
2146 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
)
2148 if (row
>= 5 || row
< 0)
2149 hw_error("%s: No key %i-%i\n", __func__
, col
, row
);
2152 s
->buttons
[row
] |= 1 << col
;
2154 s
->buttons
[row
] &= ~(1 << col
);
2156 omap_mpuio_kbd_update(s
);
2159 /* MicroWire Interface */
2160 struct omap_uwire_s
{
2171 uWireSlave
*chip
[4];
2174 static void omap_uwire_transfer_start(struct omap_uwire_s
*s
)
2176 int chipselect
= (s
->control
>> 10) & 3; /* INDEX */
2177 uWireSlave
*slave
= s
->chip
[chipselect
];
2179 if ((s
->control
>> 5) & 0x1f) { /* NB_BITS_WR */
2180 if (s
->control
& (1 << 12)) /* CS_CMD */
2181 if (slave
&& slave
->send
)
2182 slave
->send(slave
->opaque
,
2183 s
->txbuf
>> (16 - ((s
->control
>> 5) & 0x1f)));
2184 s
->control
&= ~(1 << 14); /* CSRB */
2185 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2186 * a DRQ. When is the level IRQ supposed to be reset? */
2189 if ((s
->control
>> 0) & 0x1f) { /* NB_BITS_RD */
2190 if (s
->control
& (1 << 12)) /* CS_CMD */
2191 if (slave
&& slave
->receive
)
2192 s
->rxbuf
= slave
->receive(slave
->opaque
);
2193 s
->control
|= 1 << 15; /* RDRB */
2194 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2195 * a DRQ. When is the level IRQ supposed to be reset? */
2199 static uint64_t omap_uwire_read(void *opaque
, hwaddr addr
,
2202 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
2203 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2206 return omap_badwidth_read16(opaque
, addr
);
2210 case 0x00: /* RDR */
2211 s
->control
&= ~(1 << 15); /* RDRB */
2214 case 0x04: /* CSR */
2217 case 0x08: /* SR1 */
2219 case 0x0c: /* SR2 */
2221 case 0x10: /* SR3 */
2223 case 0x14: /* SR4 */
2225 case 0x18: /* SR5 */
2233 static void omap_uwire_write(void *opaque
, hwaddr addr
,
2234 uint64_t value
, unsigned size
)
2236 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
2237 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2240 omap_badwidth_write16(opaque
, addr
, value
);
2245 case 0x00: /* TDR */
2246 s
->txbuf
= value
; /* TD */
2247 if ((s
->setup
[4] & (1 << 2)) && /* AUTO_TX_EN */
2248 ((s
->setup
[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2249 (s
->control
& (1 << 12)))) { /* CS_CMD */
2250 s
->control
|= 1 << 14; /* CSRB */
2251 omap_uwire_transfer_start(s
);
2255 case 0x04: /* CSR */
2256 s
->control
= value
& 0x1fff;
2257 if (value
& (1 << 13)) /* START */
2258 omap_uwire_transfer_start(s
);
2261 case 0x08: /* SR1 */
2262 s
->setup
[0] = value
& 0x003f;
2265 case 0x0c: /* SR2 */
2266 s
->setup
[1] = value
& 0x0fc0;
2269 case 0x10: /* SR3 */
2270 s
->setup
[2] = value
& 0x0003;
2273 case 0x14: /* SR4 */
2274 s
->setup
[3] = value
& 0x0001;
2277 case 0x18: /* SR5 */
2278 s
->setup
[4] = value
& 0x000f;
2287 static const MemoryRegionOps omap_uwire_ops
= {
2288 .read
= omap_uwire_read
,
2289 .write
= omap_uwire_write
,
2290 .endianness
= DEVICE_NATIVE_ENDIAN
,
2293 static void omap_uwire_reset(struct omap_uwire_s
*s
)
2303 static struct omap_uwire_s
*omap_uwire_init(MemoryRegion
*system_memory
,
2305 qemu_irq txirq
, qemu_irq rxirq
,
2309 struct omap_uwire_s
*s
= g_new0(struct omap_uwire_s
, 1);
2314 omap_uwire_reset(s
);
2316 memory_region_init_io(&s
->iomem
, NULL
, &omap_uwire_ops
, s
, "omap-uwire", 0x800);
2317 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2322 void omap_uwire_attach(struct omap_uwire_s
*s
,
2323 uWireSlave
*slave
, int chipselect
)
2325 if (chipselect
< 0 || chipselect
> 3) {
2326 error_report("%s: Bad chipselect %i", __func__
, chipselect
);
2330 s
->chip
[chipselect
] = slave
;
2333 /* Pseudonoise Pulse-Width Light Modulator */
2342 static void omap_pwl_update(struct omap_pwl_s
*s
)
2344 int output
= (s
->clk
&& s
->enable
) ? s
->level
: 0;
2346 if (output
!= s
->output
) {
2348 printf("%s: Backlight now at %i/256\n", __func__
, output
);
2352 static uint64_t omap_pwl_read(void *opaque
, hwaddr addr
,
2355 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2356 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2359 return omap_badwidth_read8(opaque
, addr
);
2363 case 0x00: /* PWL_LEVEL */
2365 case 0x04: /* PWL_CTRL */
2372 static void omap_pwl_write(void *opaque
, hwaddr addr
,
2373 uint64_t value
, unsigned size
)
2375 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2376 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2379 omap_badwidth_write8(opaque
, addr
, value
);
2384 case 0x00: /* PWL_LEVEL */
2388 case 0x04: /* PWL_CTRL */
2389 s
->enable
= value
& 1;
2398 static const MemoryRegionOps omap_pwl_ops
= {
2399 .read
= omap_pwl_read
,
2400 .write
= omap_pwl_write
,
2401 .endianness
= DEVICE_NATIVE_ENDIAN
,
2404 static void omap_pwl_reset(struct omap_pwl_s
*s
)
2413 static void omap_pwl_clk_update(void *opaque
, int line
, int on
)
2415 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2421 static struct omap_pwl_s
*omap_pwl_init(MemoryRegion
*system_memory
,
2425 struct omap_pwl_s
*s
= g_malloc0(sizeof(*s
));
2429 memory_region_init_io(&s
->iomem
, NULL
, &omap_pwl_ops
, s
,
2431 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2433 omap_clk_adduser(clk
, qemu_allocate_irq(omap_pwl_clk_update
, s
, 0));
2437 /* Pulse-Width Tone module */
2446 static uint64_t omap_pwt_read(void *opaque
, hwaddr addr
,
2449 struct omap_pwt_s
*s
= (struct omap_pwt_s
*) opaque
;
2450 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2453 return omap_badwidth_read8(opaque
, addr
);
2457 case 0x00: /* FRC */
2459 case 0x04: /* VCR */
2461 case 0x08: /* GCR */
2468 static void omap_pwt_write(void *opaque
, hwaddr addr
,
2469 uint64_t value
, unsigned size
)
2471 struct omap_pwt_s
*s
= (struct omap_pwt_s
*) opaque
;
2472 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2475 omap_badwidth_write8(opaque
, addr
, value
);
2480 case 0x00: /* FRC */
2481 s
->frc
= value
& 0x3f;
2483 case 0x04: /* VRC */
2484 if ((value
^ s
->vrc
) & 1) {
2486 printf("%s: %iHz buzz on\n", __func__
, (int)
2487 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2488 ((omap_clk_getrate(s
->clk
) >> 3) /
2489 /* Pre-multiplexer divider */
2490 ((s
->gcr
& 2) ? 1 : 154) /
2491 /* Octave multiplexer */
2492 (2 << (value
& 3)) *
2493 /* 101/107 divider */
2494 ((value
& (1 << 2)) ? 101 : 107) *
2496 ((value
& (1 << 3)) ? 49 : 55) *
2498 ((value
& (1 << 4)) ? 50 : 63) *
2499 /* 80/127 divider */
2500 ((value
& (1 << 5)) ? 80 : 127) /
2501 (107 * 55 * 63 * 127)));
2503 printf("%s: silence!\n", __func__
);
2505 s
->vrc
= value
& 0x7f;
2507 case 0x08: /* GCR */
2516 static const MemoryRegionOps omap_pwt_ops
= {
2517 .read
=omap_pwt_read
,
2518 .write
= omap_pwt_write
,
2519 .endianness
= DEVICE_NATIVE_ENDIAN
,
2522 static void omap_pwt_reset(struct omap_pwt_s
*s
)
2529 static struct omap_pwt_s
*omap_pwt_init(MemoryRegion
*system_memory
,
2533 struct omap_pwt_s
*s
= g_malloc0(sizeof(*s
));
2537 memory_region_init_io(&s
->iomem
, NULL
, &omap_pwt_ops
, s
,
2539 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2543 /* Real-time Clock module */
2560 struct tm current_tm
;
2565 static void omap_rtc_interrupts_update(struct omap_rtc_s
*s
)
2567 /* s->alarm is level-triggered */
2568 qemu_set_irq(s
->alarm
, (s
->status
>> 6) & 1);
2571 static void omap_rtc_alarm_update(struct omap_rtc_s
*s
)
2573 s
->alarm_ti
= mktimegm(&s
->alarm_tm
);
2574 if (s
->alarm_ti
== -1)
2575 printf("%s: conversion failed\n", __func__
);
2578 static uint64_t omap_rtc_read(void *opaque
, hwaddr addr
,
2581 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
2582 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2586 return omap_badwidth_read8(opaque
, addr
);
2590 case 0x00: /* SECONDS_REG */
2591 return to_bcd(s
->current_tm
.tm_sec
);
2593 case 0x04: /* MINUTES_REG */
2594 return to_bcd(s
->current_tm
.tm_min
);
2596 case 0x08: /* HOURS_REG */
2598 return ((s
->current_tm
.tm_hour
> 11) << 7) |
2599 to_bcd(((s
->current_tm
.tm_hour
- 1) % 12) + 1);
2601 return to_bcd(s
->current_tm
.tm_hour
);
2603 case 0x0c: /* DAYS_REG */
2604 return to_bcd(s
->current_tm
.tm_mday
);
2606 case 0x10: /* MONTHS_REG */
2607 return to_bcd(s
->current_tm
.tm_mon
+ 1);
2609 case 0x14: /* YEARS_REG */
2610 return to_bcd(s
->current_tm
.tm_year
% 100);
2612 case 0x18: /* WEEK_REG */
2613 return s
->current_tm
.tm_wday
;
2615 case 0x20: /* ALARM_SECONDS_REG */
2616 return to_bcd(s
->alarm_tm
.tm_sec
);
2618 case 0x24: /* ALARM_MINUTES_REG */
2619 return to_bcd(s
->alarm_tm
.tm_min
);
2621 case 0x28: /* ALARM_HOURS_REG */
2623 return ((s
->alarm_tm
.tm_hour
> 11) << 7) |
2624 to_bcd(((s
->alarm_tm
.tm_hour
- 1) % 12) + 1);
2626 return to_bcd(s
->alarm_tm
.tm_hour
);
2628 case 0x2c: /* ALARM_DAYS_REG */
2629 return to_bcd(s
->alarm_tm
.tm_mday
);
2631 case 0x30: /* ALARM_MONTHS_REG */
2632 return to_bcd(s
->alarm_tm
.tm_mon
+ 1);
2634 case 0x34: /* ALARM_YEARS_REG */
2635 return to_bcd(s
->alarm_tm
.tm_year
% 100);
2637 case 0x40: /* RTC_CTRL_REG */
2638 return (s
->pm_am
<< 3) | (s
->auto_comp
<< 2) |
2639 (s
->round
<< 1) | s
->running
;
2641 case 0x44: /* RTC_STATUS_REG */
2646 case 0x48: /* RTC_INTERRUPTS_REG */
2647 return s
->interrupts
;
2649 case 0x4c: /* RTC_COMP_LSB_REG */
2650 return ((uint16_t) s
->comp_reg
) & 0xff;
2652 case 0x50: /* RTC_COMP_MSB_REG */
2653 return ((uint16_t) s
->comp_reg
) >> 8;
2660 static void omap_rtc_write(void *opaque
, hwaddr addr
,
2661 uint64_t value
, unsigned size
)
2663 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
2664 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2669 omap_badwidth_write8(opaque
, addr
, value
);
2674 case 0x00: /* SECONDS_REG */
2676 printf("RTC SEC_REG <-- %02x\n", value
);
2678 s
->ti
-= s
->current_tm
.tm_sec
;
2679 s
->ti
+= from_bcd(value
);
2682 case 0x04: /* MINUTES_REG */
2684 printf("RTC MIN_REG <-- %02x\n", value
);
2686 s
->ti
-= s
->current_tm
.tm_min
* 60;
2687 s
->ti
+= from_bcd(value
) * 60;
2690 case 0x08: /* HOURS_REG */
2692 printf("RTC HRS_REG <-- %02x\n", value
);
2694 s
->ti
-= s
->current_tm
.tm_hour
* 3600;
2696 s
->ti
+= (from_bcd(value
& 0x3f) & 12) * 3600;
2697 s
->ti
+= ((value
>> 7) & 1) * 43200;
2699 s
->ti
+= from_bcd(value
& 0x3f) * 3600;
2702 case 0x0c: /* DAYS_REG */
2704 printf("RTC DAY_REG <-- %02x\n", value
);
2706 s
->ti
-= s
->current_tm
.tm_mday
* 86400;
2707 s
->ti
+= from_bcd(value
) * 86400;
2710 case 0x10: /* MONTHS_REG */
2712 printf("RTC MTH_REG <-- %02x\n", value
);
2714 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
2715 new_tm
.tm_mon
= from_bcd(value
);
2716 ti
[0] = mktimegm(&s
->current_tm
);
2717 ti
[1] = mktimegm(&new_tm
);
2719 if (ti
[0] != -1 && ti
[1] != -1) {
2723 /* A less accurate version */
2724 s
->ti
-= s
->current_tm
.tm_mon
* 2592000;
2725 s
->ti
+= from_bcd(value
) * 2592000;
2729 case 0x14: /* YEARS_REG */
2731 printf("RTC YRS_REG <-- %02x\n", value
);
2733 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
2734 new_tm
.tm_year
+= from_bcd(value
) - (new_tm
.tm_year
% 100);
2735 ti
[0] = mktimegm(&s
->current_tm
);
2736 ti
[1] = mktimegm(&new_tm
);
2738 if (ti
[0] != -1 && ti
[1] != -1) {
2742 /* A less accurate version */
2743 s
->ti
-= (time_t)(s
->current_tm
.tm_year
% 100) * 31536000;
2744 s
->ti
+= (time_t)from_bcd(value
) * 31536000;
2748 case 0x18: /* WEEK_REG */
2749 return; /* Ignored */
2751 case 0x20: /* ALARM_SECONDS_REG */
2753 printf("ALM SEC_REG <-- %02x\n", value
);
2755 s
->alarm_tm
.tm_sec
= from_bcd(value
);
2756 omap_rtc_alarm_update(s
);
2759 case 0x24: /* ALARM_MINUTES_REG */
2761 printf("ALM MIN_REG <-- %02x\n", value
);
2763 s
->alarm_tm
.tm_min
= from_bcd(value
);
2764 omap_rtc_alarm_update(s
);
2767 case 0x28: /* ALARM_HOURS_REG */
2769 printf("ALM HRS_REG <-- %02x\n", value
);
2772 s
->alarm_tm
.tm_hour
=
2773 ((from_bcd(value
& 0x3f)) % 12) +
2774 ((value
>> 7) & 1) * 12;
2776 s
->alarm_tm
.tm_hour
= from_bcd(value
);
2777 omap_rtc_alarm_update(s
);
2780 case 0x2c: /* ALARM_DAYS_REG */
2782 printf("ALM DAY_REG <-- %02x\n", value
);
2784 s
->alarm_tm
.tm_mday
= from_bcd(value
);
2785 omap_rtc_alarm_update(s
);
2788 case 0x30: /* ALARM_MONTHS_REG */
2790 printf("ALM MON_REG <-- %02x\n", value
);
2792 s
->alarm_tm
.tm_mon
= from_bcd(value
);
2793 omap_rtc_alarm_update(s
);
2796 case 0x34: /* ALARM_YEARS_REG */
2798 printf("ALM YRS_REG <-- %02x\n", value
);
2800 s
->alarm_tm
.tm_year
= from_bcd(value
);
2801 omap_rtc_alarm_update(s
);
2804 case 0x40: /* RTC_CTRL_REG */
2806 printf("RTC CONTROL <-- %02x\n", value
);
2808 s
->pm_am
= (value
>> 3) & 1;
2809 s
->auto_comp
= (value
>> 2) & 1;
2810 s
->round
= (value
>> 1) & 1;
2811 s
->running
= value
& 1;
2813 s
->status
|= s
->running
<< 1;
2816 case 0x44: /* RTC_STATUS_REG */
2818 printf("RTC STATUSL <-- %02x\n", value
);
2820 s
->status
&= ~((value
& 0xc0) ^ 0x80);
2821 omap_rtc_interrupts_update(s
);
2824 case 0x48: /* RTC_INTERRUPTS_REG */
2826 printf("RTC INTRS <-- %02x\n", value
);
2828 s
->interrupts
= value
;
2831 case 0x4c: /* RTC_COMP_LSB_REG */
2833 printf("RTC COMPLSB <-- %02x\n", value
);
2835 s
->comp_reg
&= 0xff00;
2836 s
->comp_reg
|= 0x00ff & value
;
2839 case 0x50: /* RTC_COMP_MSB_REG */
2841 printf("RTC COMPMSB <-- %02x\n", value
);
2843 s
->comp_reg
&= 0x00ff;
2844 s
->comp_reg
|= 0xff00 & (value
<< 8);
2853 static const MemoryRegionOps omap_rtc_ops
= {
2854 .read
= omap_rtc_read
,
2855 .write
= omap_rtc_write
,
2856 .endianness
= DEVICE_NATIVE_ENDIAN
,
2859 static void omap_rtc_tick(void *opaque
)
2861 struct omap_rtc_s
*s
= opaque
;
2864 /* Round to nearest full minute. */
2865 if (s
->current_tm
.tm_sec
< 30)
2866 s
->ti
-= s
->current_tm
.tm_sec
;
2868 s
->ti
+= 60 - s
->current_tm
.tm_sec
;
2873 localtime_r(&s
->ti
, &s
->current_tm
);
2875 if ((s
->interrupts
& 0x08) && s
->ti
== s
->alarm_ti
) {
2877 omap_rtc_interrupts_update(s
);
2880 if (s
->interrupts
& 0x04)
2881 switch (s
->interrupts
& 3) {
2884 qemu_irq_pulse(s
->irq
);
2887 if (s
->current_tm
.tm_sec
)
2890 qemu_irq_pulse(s
->irq
);
2893 if (s
->current_tm
.tm_sec
|| s
->current_tm
.tm_min
)
2896 qemu_irq_pulse(s
->irq
);
2899 if (s
->current_tm
.tm_sec
||
2900 s
->current_tm
.tm_min
|| s
->current_tm
.tm_hour
)
2903 qemu_irq_pulse(s
->irq
);
2913 * Every full hour add a rough approximation of the compensation
2914 * register to the 32kHz Timer (which drives the RTC) value.
2916 if (s
->auto_comp
&& !s
->current_tm
.tm_sec
&& !s
->current_tm
.tm_min
)
2917 s
->tick
+= s
->comp_reg
* 1000 / 32768;
2919 timer_mod(s
->clk
, s
->tick
);
2922 static void omap_rtc_reset(struct omap_rtc_s
*s
)
2932 s
->tick
= qemu_clock_get_ms(rtc_clock
);
2933 memset(&s
->alarm_tm
, 0, sizeof(s
->alarm_tm
));
2934 s
->alarm_tm
.tm_mday
= 0x01;
2936 qemu_get_timedate(&tm
, 0);
2937 s
->ti
= mktimegm(&tm
);
2939 omap_rtc_alarm_update(s
);
2943 static struct omap_rtc_s
*omap_rtc_init(MemoryRegion
*system_memory
,
2945 qemu_irq timerirq
, qemu_irq alarmirq
,
2948 struct omap_rtc_s
*s
= g_new0(struct omap_rtc_s
, 1);
2951 s
->alarm
= alarmirq
;
2952 s
->clk
= timer_new_ms(rtc_clock
, omap_rtc_tick
, s
);
2956 memory_region_init_io(&s
->iomem
, NULL
, &omap_rtc_ops
, s
,
2958 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2963 /* Multi-channel Buffered Serial Port interfaces */
2964 struct omap_mcbsp_s
{
2985 QEMUTimer
*source_timer
;
2986 QEMUTimer
*sink_timer
;
2989 static void omap_mcbsp_intr_update(struct omap_mcbsp_s
*s
)
2993 switch ((s
->spcr
[0] >> 4) & 3) { /* RINTM */
2995 irq
= (s
->spcr
[0] >> 1) & 1; /* RRDY */
2998 irq
= (s
->spcr
[0] >> 3) & 1; /* RSYNCERR */
3006 qemu_irq_pulse(s
->rxirq
);
3008 switch ((s
->spcr
[1] >> 4) & 3) { /* XINTM */
3010 irq
= (s
->spcr
[1] >> 1) & 1; /* XRDY */
3013 irq
= (s
->spcr
[1] >> 3) & 1; /* XSYNCERR */
3021 qemu_irq_pulse(s
->txirq
);
3024 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s
*s
)
3026 if ((s
->spcr
[0] >> 1) & 1) /* RRDY */
3027 s
->spcr
[0] |= 1 << 2; /* RFULL */
3028 s
->spcr
[0] |= 1 << 1; /* RRDY */
3029 qemu_irq_raise(s
->rxdrq
);
3030 omap_mcbsp_intr_update(s
);
3033 static void omap_mcbsp_source_tick(void *opaque
)
3035 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3036 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3041 printf("%s: Rx FIFO overrun\n", __func__
);
3043 s
->rx_req
= s
->rx_rate
<< bps
[(s
->rcr
[0] >> 5) & 7];
3045 omap_mcbsp_rx_newdata(s
);
3046 timer_mod(s
->source_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
3047 NANOSECONDS_PER_SECOND
);
3050 static void omap_mcbsp_rx_start(struct omap_mcbsp_s
*s
)
3052 if (!s
->codec
|| !s
->codec
->rts
)
3053 omap_mcbsp_source_tick(s
);
3054 else if (s
->codec
->in
.len
) {
3055 s
->rx_req
= s
->codec
->in
.len
;
3056 omap_mcbsp_rx_newdata(s
);
3060 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s
*s
)
3062 timer_del(s
->source_timer
);
3065 static void omap_mcbsp_rx_done(struct omap_mcbsp_s
*s
)
3067 s
->spcr
[0] &= ~(1 << 1); /* RRDY */
3068 qemu_irq_lower(s
->rxdrq
);
3069 omap_mcbsp_intr_update(s
);
3072 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s
*s
)
3074 s
->spcr
[1] |= 1 << 1; /* XRDY */
3075 qemu_irq_raise(s
->txdrq
);
3076 omap_mcbsp_intr_update(s
);
3079 static void omap_mcbsp_sink_tick(void *opaque
)
3081 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3082 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3087 printf("%s: Tx FIFO underrun\n", __func__
);
3089 s
->tx_req
= s
->tx_rate
<< bps
[(s
->xcr
[0] >> 5) & 7];
3091 omap_mcbsp_tx_newdata(s
);
3092 timer_mod(s
->sink_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
3093 NANOSECONDS_PER_SECOND
);
3096 static void omap_mcbsp_tx_start(struct omap_mcbsp_s
*s
)
3098 if (!s
->codec
|| !s
->codec
->cts
)
3099 omap_mcbsp_sink_tick(s
);
3100 else if (s
->codec
->out
.size
) {
3101 s
->tx_req
= s
->codec
->out
.size
;
3102 omap_mcbsp_tx_newdata(s
);
3106 static void omap_mcbsp_tx_done(struct omap_mcbsp_s
*s
)
3108 s
->spcr
[1] &= ~(1 << 1); /* XRDY */
3109 qemu_irq_lower(s
->txdrq
);
3110 omap_mcbsp_intr_update(s
);
3111 if (s
->codec
&& s
->codec
->cts
)
3112 s
->codec
->tx_swallow(s
->codec
->opaque
);
3115 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s
*s
)
3118 omap_mcbsp_tx_done(s
);
3119 timer_del(s
->sink_timer
);
3122 static void omap_mcbsp_req_update(struct omap_mcbsp_s
*s
)
3124 int prev_rx_rate
, prev_tx_rate
;
3125 int rx_rate
= 0, tx_rate
= 0;
3126 int cpu_rate
= 1500000; /* XXX */
3128 /* TODO: check CLKSTP bit */
3129 if (s
->spcr
[1] & (1 << 6)) { /* GRST */
3130 if (s
->spcr
[0] & (1 << 0)) { /* RRST */
3131 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3132 (s
->pcr
& (1 << 8))) { /* CLKRM */
3133 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3134 rx_rate
= cpu_rate
/
3135 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3138 rx_rate
= s
->codec
->rx_rate
;
3141 if (s
->spcr
[1] & (1 << 0)) { /* XRST */
3142 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3143 (s
->pcr
& (1 << 9))) { /* CLKXM */
3144 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3145 tx_rate
= cpu_rate
/
3146 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3149 tx_rate
= s
->codec
->tx_rate
;
3152 prev_tx_rate
= s
->tx_rate
;
3153 prev_rx_rate
= s
->rx_rate
;
3154 s
->tx_rate
= tx_rate
;
3155 s
->rx_rate
= rx_rate
;
3158 s
->codec
->set_rate(s
->codec
->opaque
, rx_rate
, tx_rate
);
3160 if (!prev_tx_rate
&& tx_rate
)
3161 omap_mcbsp_tx_start(s
);
3162 else if (s
->tx_rate
&& !tx_rate
)
3163 omap_mcbsp_tx_stop(s
);
3165 if (!prev_rx_rate
&& rx_rate
)
3166 omap_mcbsp_rx_start(s
);
3167 else if (prev_tx_rate
&& !tx_rate
)
3168 omap_mcbsp_rx_stop(s
);
3171 static uint64_t omap_mcbsp_read(void *opaque
, hwaddr addr
,
3174 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3175 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3179 return omap_badwidth_read16(opaque
, addr
);
3183 case 0x00: /* DRR2 */
3184 if (((s
->rcr
[0] >> 5) & 7) < 3) /* RWDLEN1 */
3187 case 0x02: /* DRR1 */
3188 if (s
->rx_req
< 2) {
3189 printf("%s: Rx FIFO underrun\n", __func__
);
3190 omap_mcbsp_rx_done(s
);
3193 if (s
->codec
&& s
->codec
->in
.len
>= 2) {
3194 ret
= s
->codec
->in
.fifo
[s
->codec
->in
.start
++] << 8;
3195 ret
|= s
->codec
->in
.fifo
[s
->codec
->in
.start
++];
3196 s
->codec
->in
.len
-= 2;
3200 omap_mcbsp_rx_done(s
);
3205 case 0x04: /* DXR2 */
3206 case 0x06: /* DXR1 */
3209 case 0x08: /* SPCR2 */
3211 case 0x0a: /* SPCR1 */
3213 case 0x0c: /* RCR2 */
3215 case 0x0e: /* RCR1 */
3217 case 0x10: /* XCR2 */
3219 case 0x12: /* XCR1 */
3221 case 0x14: /* SRGR2 */
3223 case 0x16: /* SRGR1 */
3225 case 0x18: /* MCR2 */
3227 case 0x1a: /* MCR1 */
3229 case 0x1c: /* RCERA */
3231 case 0x1e: /* RCERB */
3233 case 0x20: /* XCERA */
3235 case 0x22: /* XCERB */
3237 case 0x24: /* PCR0 */
3239 case 0x26: /* RCERC */
3241 case 0x28: /* RCERD */
3243 case 0x2a: /* XCERC */
3245 case 0x2c: /* XCERD */
3247 case 0x2e: /* RCERE */
3249 case 0x30: /* RCERF */
3251 case 0x32: /* XCERE */
3253 case 0x34: /* XCERF */
3255 case 0x36: /* RCERG */
3257 case 0x38: /* RCERH */
3259 case 0x3a: /* XCERG */
3261 case 0x3c: /* XCERH */
3269 static void omap_mcbsp_writeh(void *opaque
, hwaddr addr
,
3272 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3273 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3276 case 0x00: /* DRR2 */
3277 case 0x02: /* DRR1 */
3281 case 0x04: /* DXR2 */
3282 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
3285 case 0x06: /* DXR1 */
3286 if (s
->tx_req
> 1) {
3288 if (s
->codec
&& s
->codec
->cts
) {
3289 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 8) & 0xff;
3290 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 0) & 0xff;
3293 omap_mcbsp_tx_done(s
);
3295 printf("%s: Tx FIFO overrun\n", __func__
);
3298 case 0x08: /* SPCR2 */
3299 s
->spcr
[1] &= 0x0002;
3300 s
->spcr
[1] |= 0x03f9 & value
;
3301 s
->spcr
[1] |= 0x0004 & (value
<< 2); /* XEMPTY := XRST */
3302 if (~value
& 1) /* XRST */
3304 omap_mcbsp_req_update(s
);
3306 case 0x0a: /* SPCR1 */
3307 s
->spcr
[0] &= 0x0006;
3308 s
->spcr
[0] |= 0xf8f9 & value
;
3309 if (value
& (1 << 15)) /* DLB */
3310 printf("%s: Digital Loopback mode enable attempt\n", __func__
);
3311 if (~value
& 1) { /* RRST */
3314 omap_mcbsp_rx_done(s
);
3316 omap_mcbsp_req_update(s
);
3319 case 0x0c: /* RCR2 */
3320 s
->rcr
[1] = value
& 0xffff;
3322 case 0x0e: /* RCR1 */
3323 s
->rcr
[0] = value
& 0x7fe0;
3325 case 0x10: /* XCR2 */
3326 s
->xcr
[1] = value
& 0xffff;
3328 case 0x12: /* XCR1 */
3329 s
->xcr
[0] = value
& 0x7fe0;
3331 case 0x14: /* SRGR2 */
3332 s
->srgr
[1] = value
& 0xffff;
3333 omap_mcbsp_req_update(s
);
3335 case 0x16: /* SRGR1 */
3336 s
->srgr
[0] = value
& 0xffff;
3337 omap_mcbsp_req_update(s
);
3339 case 0x18: /* MCR2 */
3340 s
->mcr
[1] = value
& 0x03e3;
3341 if (value
& 3) /* XMCM */
3342 printf("%s: Tx channel selection mode enable attempt\n", __func__
);
3344 case 0x1a: /* MCR1 */
3345 s
->mcr
[0] = value
& 0x03e1;
3346 if (value
& 1) /* RMCM */
3347 printf("%s: Rx channel selection mode enable attempt\n", __func__
);
3349 case 0x1c: /* RCERA */
3350 s
->rcer
[0] = value
& 0xffff;
3352 case 0x1e: /* RCERB */
3353 s
->rcer
[1] = value
& 0xffff;
3355 case 0x20: /* XCERA */
3356 s
->xcer
[0] = value
& 0xffff;
3358 case 0x22: /* XCERB */
3359 s
->xcer
[1] = value
& 0xffff;
3361 case 0x24: /* PCR0 */
3362 s
->pcr
= value
& 0x7faf;
3364 case 0x26: /* RCERC */
3365 s
->rcer
[2] = value
& 0xffff;
3367 case 0x28: /* RCERD */
3368 s
->rcer
[3] = value
& 0xffff;
3370 case 0x2a: /* XCERC */
3371 s
->xcer
[2] = value
& 0xffff;
3373 case 0x2c: /* XCERD */
3374 s
->xcer
[3] = value
& 0xffff;
3376 case 0x2e: /* RCERE */
3377 s
->rcer
[4] = value
& 0xffff;
3379 case 0x30: /* RCERF */
3380 s
->rcer
[5] = value
& 0xffff;
3382 case 0x32: /* XCERE */
3383 s
->xcer
[4] = value
& 0xffff;
3385 case 0x34: /* XCERF */
3386 s
->xcer
[5] = value
& 0xffff;
3388 case 0x36: /* RCERG */
3389 s
->rcer
[6] = value
& 0xffff;
3391 case 0x38: /* RCERH */
3392 s
->rcer
[7] = value
& 0xffff;
3394 case 0x3a: /* XCERG */
3395 s
->xcer
[6] = value
& 0xffff;
3397 case 0x3c: /* XCERH */
3398 s
->xcer
[7] = value
& 0xffff;
3405 static void omap_mcbsp_writew(void *opaque
, hwaddr addr
,
3408 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3409 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3411 if (offset
== 0x04) { /* DXR */
3412 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
3414 if (s
->tx_req
> 3) {
3416 if (s
->codec
&& s
->codec
->cts
) {
3417 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3418 (value
>> 24) & 0xff;
3419 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3420 (value
>> 16) & 0xff;
3421 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3422 (value
>> 8) & 0xff;
3423 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3424 (value
>> 0) & 0xff;
3427 omap_mcbsp_tx_done(s
);
3429 printf("%s: Tx FIFO overrun\n", __func__
);
3433 omap_badwidth_write16(opaque
, addr
, value
);
3436 static void omap_mcbsp_write(void *opaque
, hwaddr addr
,
3437 uint64_t value
, unsigned size
)
3441 omap_mcbsp_writeh(opaque
, addr
, value
);
3444 omap_mcbsp_writew(opaque
, addr
, value
);
3447 omap_badwidth_write16(opaque
, addr
, value
);
3451 static const MemoryRegionOps omap_mcbsp_ops
= {
3452 .read
= omap_mcbsp_read
,
3453 .write
= omap_mcbsp_write
,
3454 .endianness
= DEVICE_NATIVE_ENDIAN
,
3457 static void omap_mcbsp_reset(struct omap_mcbsp_s
*s
)
3459 memset(&s
->spcr
, 0, sizeof(s
->spcr
));
3460 memset(&s
->rcr
, 0, sizeof(s
->rcr
));
3461 memset(&s
->xcr
, 0, sizeof(s
->xcr
));
3462 s
->srgr
[0] = 0x0001;
3463 s
->srgr
[1] = 0x2000;
3464 memset(&s
->mcr
, 0, sizeof(s
->mcr
));
3465 memset(&s
->pcr
, 0, sizeof(s
->pcr
));
3466 memset(&s
->rcer
, 0, sizeof(s
->rcer
));
3467 memset(&s
->xcer
, 0, sizeof(s
->xcer
));
3472 timer_del(s
->source_timer
);
3473 timer_del(s
->sink_timer
);
3476 static struct omap_mcbsp_s
*omap_mcbsp_init(MemoryRegion
*system_memory
,
3478 qemu_irq txirq
, qemu_irq rxirq
,
3479 qemu_irq
*dma
, omap_clk clk
)
3481 struct omap_mcbsp_s
*s
= g_new0(struct omap_mcbsp_s
, 1);
3487 s
->sink_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_mcbsp_sink_tick
, s
);
3488 s
->source_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_mcbsp_source_tick
, s
);
3489 omap_mcbsp_reset(s
);
3491 memory_region_init_io(&s
->iomem
, NULL
, &omap_mcbsp_ops
, s
, "omap-mcbsp", 0x800);
3492 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
3497 static void omap_mcbsp_i2s_swallow(void *opaque
, int line
, int level
)
3499 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3502 s
->rx_req
= s
->codec
->in
.len
;
3503 omap_mcbsp_rx_newdata(s
);
3507 static void omap_mcbsp_i2s_start(void *opaque
, int line
, int level
)
3509 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3512 s
->tx_req
= s
->codec
->out
.size
;
3513 omap_mcbsp_tx_newdata(s
);
3517 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, I2SCodec
*slave
)
3520 slave
->rx_swallow
= qemu_allocate_irq(omap_mcbsp_i2s_swallow
, s
, 0);
3521 slave
->tx_start
= qemu_allocate_irq(omap_mcbsp_i2s_start
, s
, 0);
3524 /* LED Pulse Generators */
3537 static void omap_lpg_tick(void *opaque
)
3539 struct omap_lpg_s
*s
= opaque
;
3542 timer_mod(s
->tm
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + s
->period
- s
->on
);
3544 timer_mod(s
->tm
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + s
->on
);
3546 s
->cycle
= !s
->cycle
;
3547 printf("%s: LED is %s\n", __func__
, s
->cycle
? "on" : "off");
3550 static void omap_lpg_update(struct omap_lpg_s
*s
)
3552 int64_t on
, period
= 1, ticks
= 1000;
3553 static const int per
[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3555 if (~s
->control
& (1 << 6)) /* LPGRES */
3557 else if (s
->control
& (1 << 7)) /* PERM_ON */
3560 period
= muldiv64(ticks
, per
[s
->control
& 7], /* PERCTRL */
3562 on
= (s
->clk
&& s
->power
) ? muldiv64(ticks
,
3563 per
[(s
->control
>> 3) & 7], 256) : 0; /* ONCTRL */
3567 if (on
== period
&& s
->on
< s
->period
)
3568 printf("%s: LED is on\n", __func__
);
3569 else if (on
== 0 && s
->on
)
3570 printf("%s: LED is off\n", __func__
);
3571 else if (on
&& (on
!= s
->on
|| period
!= s
->period
)) {
3583 static void omap_lpg_reset(struct omap_lpg_s
*s
)
3591 static uint64_t omap_lpg_read(void *opaque
, hwaddr addr
,
3594 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3595 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3598 return omap_badwidth_read8(opaque
, addr
);
3602 case 0x00: /* LCR */
3605 case 0x04: /* PMR */
3613 static void omap_lpg_write(void *opaque
, hwaddr addr
,
3614 uint64_t value
, unsigned size
)
3616 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3617 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3620 omap_badwidth_write8(opaque
, addr
, value
);
3625 case 0x00: /* LCR */
3626 if (~value
& (1 << 6)) /* LPGRES */
3628 s
->control
= value
& 0xff;
3632 case 0x04: /* PMR */
3633 s
->power
= value
& 0x01;
3643 static const MemoryRegionOps omap_lpg_ops
= {
3644 .read
= omap_lpg_read
,
3645 .write
= omap_lpg_write
,
3646 .endianness
= DEVICE_NATIVE_ENDIAN
,
3649 static void omap_lpg_clk_update(void *opaque
, int line
, int on
)
3651 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3657 static struct omap_lpg_s
*omap_lpg_init(MemoryRegion
*system_memory
,
3658 hwaddr base
, omap_clk clk
)
3660 struct omap_lpg_s
*s
= g_new0(struct omap_lpg_s
, 1);
3662 s
->tm
= timer_new_ms(QEMU_CLOCK_VIRTUAL
, omap_lpg_tick
, s
);
3666 memory_region_init_io(&s
->iomem
, NULL
, &omap_lpg_ops
, s
, "omap-lpg", 0x800);
3667 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
3669 omap_clk_adduser(clk
, qemu_allocate_irq(omap_lpg_clk_update
, s
, 0));
3674 /* MPUI Peripheral Bridge configuration */
3675 static uint64_t omap_mpui_io_read(void *opaque
, hwaddr addr
,
3679 return omap_badwidth_read16(opaque
, addr
);
3682 if (addr
== OMAP_MPUI_BASE
) /* CMR */
3689 static void omap_mpui_io_write(void *opaque
, hwaddr addr
,
3690 uint64_t value
, unsigned size
)
3692 /* FIXME: infinite loop */
3693 omap_badwidth_write16(opaque
, addr
, value
);
3696 static const MemoryRegionOps omap_mpui_io_ops
= {
3697 .read
= omap_mpui_io_read
,
3698 .write
= omap_mpui_io_write
,
3699 .endianness
= DEVICE_NATIVE_ENDIAN
,
3702 static void omap_setup_mpui_io(MemoryRegion
*system_memory
,
3703 struct omap_mpu_state_s
*mpu
)
3705 memory_region_init_io(&mpu
->mpui_io_iomem
, NULL
, &omap_mpui_io_ops
, mpu
,
3706 "omap-mpui-io", 0x7fff);
3707 memory_region_add_subregion(system_memory
, OMAP_MPUI_BASE
,
3708 &mpu
->mpui_io_iomem
);
3711 /* General chip reset */
3712 static void omap1_mpu_reset(void *opaque
)
3714 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
3716 omap_dma_reset(mpu
->dma
);
3717 omap_mpu_timer_reset(mpu
->timer
[0]);
3718 omap_mpu_timer_reset(mpu
->timer
[1]);
3719 omap_mpu_timer_reset(mpu
->timer
[2]);
3720 omap_wd_timer_reset(mpu
->wdt
);
3721 omap_os_timer_reset(mpu
->os_timer
);
3722 omap_lcdc_reset(mpu
->lcd
);
3723 omap_ulpd_pm_reset(mpu
);
3724 omap_pin_cfg_reset(mpu
);
3725 omap_mpui_reset(mpu
);
3726 omap_tipb_bridge_reset(mpu
->private_tipb
);
3727 omap_tipb_bridge_reset(mpu
->public_tipb
);
3728 omap_dpll_reset(mpu
->dpll
[0]);
3729 omap_dpll_reset(mpu
->dpll
[1]);
3730 omap_dpll_reset(mpu
->dpll
[2]);
3731 omap_uart_reset(mpu
->uart
[0]);
3732 omap_uart_reset(mpu
->uart
[1]);
3733 omap_uart_reset(mpu
->uart
[2]);
3734 omap_mmc_reset(mpu
->mmc
);
3735 omap_mpuio_reset(mpu
->mpuio
);
3736 omap_uwire_reset(mpu
->microwire
);
3737 omap_pwl_reset(mpu
->pwl
);
3738 omap_pwt_reset(mpu
->pwt
);
3739 omap_rtc_reset(mpu
->rtc
);
3740 omap_mcbsp_reset(mpu
->mcbsp1
);
3741 omap_mcbsp_reset(mpu
->mcbsp2
);
3742 omap_mcbsp_reset(mpu
->mcbsp3
);
3743 omap_lpg_reset(mpu
->led
[0]);
3744 omap_lpg_reset(mpu
->led
[1]);
3745 omap_clkm_reset(mpu
);
3746 cpu_reset(CPU(mpu
->cpu
));
3749 static const struct omap_map_s
{
3754 } omap15xx_dsp_mm
[] = {
3756 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3757 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3758 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3759 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3760 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3761 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3762 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3763 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3764 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3765 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3766 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3767 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3768 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3769 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3770 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3771 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3772 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3774 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3779 static void omap_setup_dsp_mapping(MemoryRegion
*system_memory
,
3780 const struct omap_map_s
*map
)
3784 for (; map
->phys_dsp
; map
++) {
3785 io
= g_new(MemoryRegion
, 1);
3786 memory_region_init_alias(io
, NULL
, map
->name
,
3787 system_memory
, map
->phys_mpu
, map
->size
);
3788 memory_region_add_subregion(system_memory
, map
->phys_dsp
, io
);
3792 void omap_mpu_wakeup(void *opaque
, int irq
, int req
)
3794 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
3795 CPUState
*cpu
= CPU(mpu
->cpu
);
3798 cpu_interrupt(cpu
, CPU_INTERRUPT_EXITTB
);
3802 static const struct dma_irq_map omap1_dma_irq_map
[] = {
3803 { 0, OMAP_INT_DMA_CH0_6
},
3804 { 0, OMAP_INT_DMA_CH1_7
},
3805 { 0, OMAP_INT_DMA_CH2_8
},
3806 { 0, OMAP_INT_DMA_CH3
},
3807 { 0, OMAP_INT_DMA_CH4
},
3808 { 0, OMAP_INT_DMA_CH5
},
3809 { 1, OMAP_INT_1610_DMA_CH6
},
3810 { 1, OMAP_INT_1610_DMA_CH7
},
3811 { 1, OMAP_INT_1610_DMA_CH8
},
3812 { 1, OMAP_INT_1610_DMA_CH9
},
3813 { 1, OMAP_INT_1610_DMA_CH10
},
3814 { 1, OMAP_INT_1610_DMA_CH11
},
3815 { 1, OMAP_INT_1610_DMA_CH12
},
3816 { 1, OMAP_INT_1610_DMA_CH13
},
3817 { 1, OMAP_INT_1610_DMA_CH14
},
3818 { 1, OMAP_INT_1610_DMA_CH15
}
3821 /* DMA ports for OMAP1 */
3822 static int omap_validate_emiff_addr(struct omap_mpu_state_s
*s
,
3825 return range_covers_byte(OMAP_EMIFF_BASE
, s
->sdram_size
, addr
);
3828 static int omap_validate_emifs_addr(struct omap_mpu_state_s
*s
,
3831 return range_covers_byte(OMAP_EMIFS_BASE
, OMAP_EMIFF_BASE
- OMAP_EMIFS_BASE
,
3835 static int omap_validate_imif_addr(struct omap_mpu_state_s
*s
,
3838 return range_covers_byte(OMAP_IMIF_BASE
, s
->sram_size
, addr
);
3841 static int omap_validate_tipb_addr(struct omap_mpu_state_s
*s
,
3844 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr
);
3847 static int omap_validate_local_addr(struct omap_mpu_state_s
*s
,
3850 return range_covers_byte(OMAP_LOCALBUS_BASE
, 0x1000000, addr
);
3853 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s
*s
,
3856 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr
);
3859 struct omap_mpu_state_s
*omap310_mpu_init(MemoryRegion
*system_memory
,
3860 unsigned long sdram_size
,
3861 const char *cpu_type
)
3864 struct omap_mpu_state_s
*s
= g_new0(struct omap_mpu_state_s
, 1);
3865 qemu_irq dma_irqs
[6];
3867 SysBusDevice
*busdev
;
3870 s
->mpu_model
= omap310
;
3871 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
3872 s
->sdram_size
= sdram_size
;
3873 s
->sram_size
= OMAP15XX_SRAM_SIZE
;
3875 s
->wakeup
= qemu_allocate_irq(omap_mpu_wakeup
, s
, 0);
3880 /* Memory-mapped stuff */
3881 memory_region_allocate_system_memory(&s
->emiff_ram
, NULL
, "omap1.dram",
3883 memory_region_add_subregion(system_memory
, OMAP_EMIFF_BASE
, &s
->emiff_ram
);
3884 memory_region_init_ram(&s
->imif_ram
, NULL
, "omap1.sram", s
->sram_size
,
3886 memory_region_add_subregion(system_memory
, OMAP_IMIF_BASE
, &s
->imif_ram
);
3888 omap_clkm_init(system_memory
, 0xfffece00, 0xe1008000, s
);
3890 s
->ih
[0] = qdev_create(NULL
, "omap-intc");
3891 qdev_prop_set_uint32(s
->ih
[0], "size", 0x100);
3892 qdev_prop_set_ptr(s
->ih
[0], "clk", omap_findclk(s
, "arminth_ck"));
3893 qdev_init_nofail(s
->ih
[0]);
3894 busdev
= SYS_BUS_DEVICE(s
->ih
[0]);
3895 sysbus_connect_irq(busdev
, 0,
3896 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
));
3897 sysbus_connect_irq(busdev
, 1,
3898 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
));
3899 sysbus_mmio_map(busdev
, 0, 0xfffecb00);
3900 s
->ih
[1] = qdev_create(NULL
, "omap-intc");
3901 qdev_prop_set_uint32(s
->ih
[1], "size", 0x800);
3902 qdev_prop_set_ptr(s
->ih
[1], "clk", omap_findclk(s
, "arminth_ck"));
3903 qdev_init_nofail(s
->ih
[1]);
3904 busdev
= SYS_BUS_DEVICE(s
->ih
[1]);
3905 sysbus_connect_irq(busdev
, 0,
3906 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_15XX_IH2_IRQ
));
3907 /* The second interrupt controller's FIQ output is not wired up */
3908 sysbus_mmio_map(busdev
, 0, 0xfffe0000);
3910 for (i
= 0; i
< 6; i
++) {
3911 dma_irqs
[i
] = qdev_get_gpio_in(s
->ih
[omap1_dma_irq_map
[i
].ih
],
3912 omap1_dma_irq_map
[i
].intr
);
3914 s
->dma
= omap_dma_init(0xfffed800, dma_irqs
, system_memory
,
3915 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_DMA_LCD
),
3916 s
, omap_findclk(s
, "dma_ck"), omap_dma_3_1
);
3918 s
->port
[emiff
].addr_valid
= omap_validate_emiff_addr
;
3919 s
->port
[emifs
].addr_valid
= omap_validate_emifs_addr
;
3920 s
->port
[imif
].addr_valid
= omap_validate_imif_addr
;
3921 s
->port
[tipb
].addr_valid
= omap_validate_tipb_addr
;
3922 s
->port
[local
].addr_valid
= omap_validate_local_addr
;
3923 s
->port
[tipb_mpui
].addr_valid
= omap_validate_tipb_mpui_addr
;
3925 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3926 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->emiff_ram
),
3927 OMAP_EMIFF_BASE
, s
->sdram_size
);
3928 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->imif_ram
),
3929 OMAP_IMIF_BASE
, s
->sram_size
);
3931 s
->timer
[0] = omap_mpu_timer_init(system_memory
, 0xfffec500,
3932 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER1
),
3933 omap_findclk(s
, "mputim_ck"));
3934 s
->timer
[1] = omap_mpu_timer_init(system_memory
, 0xfffec600,
3935 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER2
),
3936 omap_findclk(s
, "mputim_ck"));
3937 s
->timer
[2] = omap_mpu_timer_init(system_memory
, 0xfffec700,
3938 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER3
),
3939 omap_findclk(s
, "mputim_ck"));
3941 s
->wdt
= omap_wd_timer_init(system_memory
, 0xfffec800,
3942 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_WD_TIMER
),
3943 omap_findclk(s
, "armwdt_ck"));
3945 s
->os_timer
= omap_os_timer_init(system_memory
, 0xfffb9000,
3946 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_OS_TIMER
),
3947 omap_findclk(s
, "clk32-kHz"));
3949 s
->lcd
= omap_lcdc_init(system_memory
, 0xfffec000,
3950 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_LCD_CTRL
),
3951 omap_dma_get_lcdch(s
->dma
),
3952 omap_findclk(s
, "lcd_ck"));
3954 omap_ulpd_pm_init(system_memory
, 0xfffe0800, s
);
3955 omap_pin_cfg_init(system_memory
, 0xfffe1000, s
);
3956 omap_id_init(system_memory
, s
);
3958 omap_mpui_init(system_memory
, 0xfffec900, s
);
3960 s
->private_tipb
= omap_tipb_bridge_init(system_memory
, 0xfffeca00,
3961 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_BRIDGE_PRIV
),
3962 omap_findclk(s
, "tipb_ck"));
3963 s
->public_tipb
= omap_tipb_bridge_init(system_memory
, 0xfffed300,
3964 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_BRIDGE_PUB
),
3965 omap_findclk(s
, "tipb_ck"));
3967 omap_tcmi_init(system_memory
, 0xfffecc00, s
);
3969 s
->uart
[0] = omap_uart_init(0xfffb0000,
3970 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_UART1
),
3971 omap_findclk(s
, "uart1_ck"),
3972 omap_findclk(s
, "uart1_ck"),
3973 s
->drq
[OMAP_DMA_UART1_TX
], s
->drq
[OMAP_DMA_UART1_RX
],
3976 s
->uart
[1] = omap_uart_init(0xfffb0800,
3977 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_UART2
),
3978 omap_findclk(s
, "uart2_ck"),
3979 omap_findclk(s
, "uart2_ck"),
3980 s
->drq
[OMAP_DMA_UART2_TX
], s
->drq
[OMAP_DMA_UART2_RX
],
3982 serial_hd(0) ? serial_hd(1) : NULL
);
3983 s
->uart
[2] = omap_uart_init(0xfffb9800,
3984 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_UART3
),
3985 omap_findclk(s
, "uart3_ck"),
3986 omap_findclk(s
, "uart3_ck"),
3987 s
->drq
[OMAP_DMA_UART3_TX
], s
->drq
[OMAP_DMA_UART3_RX
],
3989 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL
);
3991 s
->dpll
[0] = omap_dpll_init(system_memory
, 0xfffecf00,
3992 omap_findclk(s
, "dpll1"));
3993 s
->dpll
[1] = omap_dpll_init(system_memory
, 0xfffed000,
3994 omap_findclk(s
, "dpll2"));
3995 s
->dpll
[2] = omap_dpll_init(system_memory
, 0xfffed100,
3996 omap_findclk(s
, "dpll3"));
3998 dinfo
= drive_get(IF_SD
, 0, 0);
3999 if (!dinfo
&& !qtest_enabled()) {
4000 warn_report("missing SecureDigital device");
4002 s
->mmc
= omap_mmc_init(0xfffb7800, system_memory
,
4003 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
4004 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_OQN
),
4005 &s
->drq
[OMAP_DMA_MMC_TX
],
4006 omap_findclk(s
, "mmc_ck"));
4008 s
->mpuio
= omap_mpuio_init(system_memory
, 0xfffb5000,
4009 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_KEYBOARD
),
4010 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_MPUIO
),
4011 s
->wakeup
, omap_findclk(s
, "clk32-kHz"));
4013 s
->gpio
= qdev_create(NULL
, "omap-gpio");
4014 qdev_prop_set_int32(s
->gpio
, "mpu_model", s
->mpu_model
);
4015 qdev_prop_set_ptr(s
->gpio
, "clk", omap_findclk(s
, "arm_gpio_ck"));
4016 qdev_init_nofail(s
->gpio
);
4017 sysbus_connect_irq(SYS_BUS_DEVICE(s
->gpio
), 0,
4018 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_GPIO_BANK1
));
4019 sysbus_mmio_map(SYS_BUS_DEVICE(s
->gpio
), 0, 0xfffce000);
4021 s
->microwire
= omap_uwire_init(system_memory
, 0xfffb3000,
4022 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_uWireTX
),
4023 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_uWireRX
),
4024 s
->drq
[OMAP_DMA_UWIRE_TX
], omap_findclk(s
, "mpuper_ck"));
4026 s
->pwl
= omap_pwl_init(system_memory
, 0xfffb5800,
4027 omap_findclk(s
, "armxor_ck"));
4028 s
->pwt
= omap_pwt_init(system_memory
, 0xfffb6000,
4029 omap_findclk(s
, "armxor_ck"));
4031 s
->i2c
[0] = qdev_create(NULL
, "omap_i2c");
4032 qdev_prop_set_uint8(s
->i2c
[0], "revision", 0x11);
4033 qdev_prop_set_ptr(s
->i2c
[0], "fclk", omap_findclk(s
, "mpuper_ck"));
4034 qdev_init_nofail(s
->i2c
[0]);
4035 busdev
= SYS_BUS_DEVICE(s
->i2c
[0]);
4036 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(s
->ih
[1], OMAP_INT_I2C
));
4037 sysbus_connect_irq(busdev
, 1, s
->drq
[OMAP_DMA_I2C_TX
]);
4038 sysbus_connect_irq(busdev
, 2, s
->drq
[OMAP_DMA_I2C_RX
]);
4039 sysbus_mmio_map(busdev
, 0, 0xfffb3800);
4041 s
->rtc
= omap_rtc_init(system_memory
, 0xfffb4800,
4042 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_RTC_TIMER
),
4043 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_RTC_ALARM
),
4044 omap_findclk(s
, "clk32-kHz"));
4046 s
->mcbsp1
= omap_mcbsp_init(system_memory
, 0xfffb1800,
4047 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP1TX
),
4048 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP1RX
),
4049 &s
->drq
[OMAP_DMA_MCBSP1_TX
], omap_findclk(s
, "dspxor_ck"));
4050 s
->mcbsp2
= omap_mcbsp_init(system_memory
, 0xfffb1000,
4051 qdev_get_gpio_in(s
->ih
[0],
4052 OMAP_INT_310_McBSP2_TX
),
4053 qdev_get_gpio_in(s
->ih
[0],
4054 OMAP_INT_310_McBSP2_RX
),
4055 &s
->drq
[OMAP_DMA_MCBSP2_TX
], omap_findclk(s
, "mpuper_ck"));
4056 s
->mcbsp3
= omap_mcbsp_init(system_memory
, 0xfffb7000,
4057 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP3TX
),
4058 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP3RX
),
4059 &s
->drq
[OMAP_DMA_MCBSP3_TX
], omap_findclk(s
, "dspxor_ck"));
4061 s
->led
[0] = omap_lpg_init(system_memory
,
4062 0xfffbd000, omap_findclk(s
, "clk32-kHz"));
4063 s
->led
[1] = omap_lpg_init(system_memory
,
4064 0xfffbd800, omap_findclk(s
, "clk32-kHz"));
4066 /* Register mappings not currenlty implemented:
4067 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4068 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4069 * USB W2FC fffb4000 - fffb47ff
4070 * Camera Interface fffb6800 - fffb6fff
4071 * USB Host fffba000 - fffba7ff
4072 * FAC fffba800 - fffbafff
4073 * HDQ/1-Wire fffbc000 - fffbc7ff
4074 * TIPB switches fffbc800 - fffbcfff
4075 * Mailbox fffcf000 - fffcf7ff
4076 * Local bus IF fffec100 - fffec1ff
4077 * Local bus MMU fffec200 - fffec2ff
4078 * DSP MMU fffed200 - fffed2ff
4081 omap_setup_dsp_mapping(system_memory
, omap15xx_dsp_mm
);
4082 omap_setup_mpui_io(system_memory
, s
);
4084 qemu_register_reset(omap1_mpu_reset
, s
);