2 * TI OMAP processors emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/error-report.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
25 #include "hw/boards.h"
27 #include "hw/arm/boot.h"
28 #include "hw/arm/omap.h"
29 #include "sysemu/sysemu.h"
30 #include "hw/arm/soc_dma.h"
31 #include "sysemu/qtest.h"
32 #include "sysemu/reset.h"
33 #include "qemu/range.h"
34 #include "hw/sysbus.h"
35 #include "qemu/cutils.h"
38 static inline void omap_log_badwidth(const char *funcname
, hwaddr addr
, int sz
)
40 qemu_log_mask(LOG_GUEST_ERROR
, "%s: %d-bit register %#08" HWADDR_PRIx
"\n",
41 funcname
, 8 * sz
, addr
);
44 /* Should signal the TCMI/GPMC */
45 uint32_t omap_badwidth_read8(void *opaque
, hwaddr addr
)
49 omap_log_badwidth(__func__
, addr
, 1);
50 cpu_physical_memory_read(addr
, &ret
, 1);
54 void omap_badwidth_write8(void *opaque
, hwaddr addr
,
59 omap_log_badwidth(__func__
, addr
, 1);
60 cpu_physical_memory_write(addr
, &val8
, 1);
63 uint32_t omap_badwidth_read16(void *opaque
, hwaddr addr
)
67 omap_log_badwidth(__func__
, addr
, 2);
68 cpu_physical_memory_read(addr
, &ret
, 2);
72 void omap_badwidth_write16(void *opaque
, hwaddr addr
,
75 uint16_t val16
= value
;
77 omap_log_badwidth(__func__
, addr
, 2);
78 cpu_physical_memory_write(addr
, &val16
, 2);
81 uint32_t omap_badwidth_read32(void *opaque
, hwaddr addr
)
85 omap_log_badwidth(__func__
, addr
, 4);
86 cpu_physical_memory_read(addr
, &ret
, 4);
90 void omap_badwidth_write32(void *opaque
, hwaddr addr
,
93 omap_log_badwidth(__func__
, addr
, 4);
94 cpu_physical_memory_write(addr
, &value
, 4);
98 struct omap_mpu_timer_s
{
116 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s
*timer
)
118 uint64_t distance
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - timer
->time
;
120 if (timer
->st
&& timer
->enable
&& timer
->rate
)
121 return timer
->val
- muldiv64(distance
>> (timer
->ptv
+ 1),
122 timer
->rate
, NANOSECONDS_PER_SECOND
);
127 static inline void omap_timer_sync(struct omap_mpu_timer_s
*timer
)
129 timer
->val
= omap_timer_read(timer
);
130 timer
->time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
133 static inline void omap_timer_update(struct omap_mpu_timer_s
*timer
)
137 if (timer
->enable
&& timer
->st
&& timer
->rate
) {
138 timer
->val
= timer
->reset_val
; /* Should skip this on clk enable */
139 expires
= muldiv64((uint64_t) timer
->val
<< (timer
->ptv
+ 1),
140 NANOSECONDS_PER_SECOND
, timer
->rate
);
142 /* If timer expiry would be sooner than in about 1 ms and
143 * auto-reload isn't set, then fire immediately. This is a hack
144 * to make systems like PalmOS run in acceptable time. PalmOS
145 * sets the interval to a very low value and polls the status bit
146 * in a busy loop when it wants to sleep just a couple of CPU
148 if (expires
> (NANOSECONDS_PER_SECOND
>> 10) || timer
->ar
) {
149 timer_mod(timer
->timer
, timer
->time
+ expires
);
151 qemu_bh_schedule(timer
->tick
);
154 timer_del(timer
->timer
);
157 static void omap_timer_fire(void *opaque
)
159 struct omap_mpu_timer_s
*timer
= opaque
;
167 /* Edge-triggered irq */
168 qemu_irq_pulse(timer
->irq
);
171 static void omap_timer_tick(void *opaque
)
173 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
175 omap_timer_sync(timer
);
176 omap_timer_fire(timer
);
177 omap_timer_update(timer
);
180 static void omap_timer_clk_update(void *opaque
, int line
, int on
)
182 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
184 omap_timer_sync(timer
);
185 timer
->rate
= on
? omap_clk_getrate(timer
->clk
) : 0;
186 omap_timer_update(timer
);
189 static void omap_timer_clk_setup(struct omap_mpu_timer_s
*timer
)
191 omap_clk_adduser(timer
->clk
,
192 qemu_allocate_irq(omap_timer_clk_update
, timer
, 0));
193 timer
->rate
= omap_clk_getrate(timer
->clk
);
196 static uint64_t omap_mpu_timer_read(void *opaque
, hwaddr addr
,
199 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
202 return omap_badwidth_read32(opaque
, addr
);
206 case 0x00: /* CNTL_TIMER */
207 return (s
->enable
<< 5) | (s
->ptv
<< 2) | (s
->ar
<< 1) | s
->st
;
209 case 0x04: /* LOAD_TIM */
212 case 0x08: /* READ_TIM */
213 return omap_timer_read(s
);
220 static void omap_mpu_timer_write(void *opaque
, hwaddr addr
,
221 uint64_t value
, unsigned size
)
223 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
226 omap_badwidth_write32(opaque
, addr
, value
);
231 case 0x00: /* CNTL_TIMER */
233 s
->enable
= (value
>> 5) & 1;
234 s
->ptv
= (value
>> 2) & 7;
235 s
->ar
= (value
>> 1) & 1;
237 omap_timer_update(s
);
240 case 0x04: /* LOAD_TIM */
241 s
->reset_val
= value
;
244 case 0x08: /* READ_TIM */
253 static const MemoryRegionOps omap_mpu_timer_ops
= {
254 .read
= omap_mpu_timer_read
,
255 .write
= omap_mpu_timer_write
,
256 .endianness
= DEVICE_LITTLE_ENDIAN
,
259 static void omap_mpu_timer_reset(struct omap_mpu_timer_s
*s
)
263 s
->reset_val
= 31337;
271 static struct omap_mpu_timer_s
*omap_mpu_timer_init(MemoryRegion
*system_memory
,
273 qemu_irq irq
, omap_clk clk
)
275 struct omap_mpu_timer_s
*s
= g_new0(struct omap_mpu_timer_s
, 1);
279 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, s
);
280 s
->tick
= qemu_bh_new(omap_timer_fire
, s
);
281 omap_mpu_timer_reset(s
);
282 omap_timer_clk_setup(s
);
284 memory_region_init_io(&s
->iomem
, NULL
, &omap_mpu_timer_ops
, s
,
285 "omap-mpu-timer", 0x100);
287 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
293 struct omap_watchdog_timer_s
{
294 struct omap_mpu_timer_s timer
;
302 static uint64_t omap_wd_timer_read(void *opaque
, hwaddr addr
,
305 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
308 return omap_badwidth_read16(opaque
, addr
);
312 case 0x00: /* CNTL_TIMER */
313 return (s
->timer
.ptv
<< 9) | (s
->timer
.ar
<< 8) |
314 (s
->timer
.st
<< 7) | (s
->free
<< 1);
316 case 0x04: /* READ_TIMER */
317 return omap_timer_read(&s
->timer
);
319 case 0x08: /* TIMER_MODE */
320 return s
->mode
<< 15;
327 static void omap_wd_timer_write(void *opaque
, hwaddr addr
,
328 uint64_t value
, unsigned size
)
330 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
333 omap_badwidth_write16(opaque
, addr
, value
);
338 case 0x00: /* CNTL_TIMER */
339 omap_timer_sync(&s
->timer
);
340 s
->timer
.ptv
= (value
>> 9) & 7;
341 s
->timer
.ar
= (value
>> 8) & 1;
342 s
->timer
.st
= (value
>> 7) & 1;
343 s
->free
= (value
>> 1) & 1;
344 omap_timer_update(&s
->timer
);
347 case 0x04: /* LOAD_TIMER */
348 s
->timer
.reset_val
= value
& 0xffff;
351 case 0x08: /* TIMER_MODE */
352 if (!s
->mode
&& ((value
>> 15) & 1))
353 omap_clk_get(s
->timer
.clk
);
354 s
->mode
|= (value
>> 15) & 1;
355 if (s
->last_wr
== 0xf5) {
356 if ((value
& 0xff) == 0xa0) {
359 omap_clk_put(s
->timer
.clk
);
362 /* XXX: on T|E hardware somehow this has no effect,
363 * on Zire 71 it works as specified. */
365 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
368 s
->last_wr
= value
& 0xff;
376 static const MemoryRegionOps omap_wd_timer_ops
= {
377 .read
= omap_wd_timer_read
,
378 .write
= omap_wd_timer_write
,
379 .endianness
= DEVICE_NATIVE_ENDIAN
,
382 static void omap_wd_timer_reset(struct omap_watchdog_timer_s
*s
)
384 timer_del(s
->timer
.timer
);
386 omap_clk_get(s
->timer
.clk
);
392 s
->timer
.reset_val
= 0xffff;
397 omap_timer_update(&s
->timer
);
400 static struct omap_watchdog_timer_s
*omap_wd_timer_init(MemoryRegion
*memory
,
402 qemu_irq irq
, omap_clk clk
)
404 struct omap_watchdog_timer_s
*s
= g_new0(struct omap_watchdog_timer_s
, 1);
408 s
->timer
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, &s
->timer
);
409 omap_wd_timer_reset(s
);
410 omap_timer_clk_setup(&s
->timer
);
412 memory_region_init_io(&s
->iomem
, NULL
, &omap_wd_timer_ops
, s
,
413 "omap-wd-timer", 0x100);
414 memory_region_add_subregion(memory
, base
, &s
->iomem
);
420 struct omap_32khz_timer_s
{
421 struct omap_mpu_timer_s timer
;
425 static uint64_t omap_os_timer_read(void *opaque
, hwaddr addr
,
428 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
429 int offset
= addr
& OMAP_MPUI_REG_MASK
;
432 return omap_badwidth_read32(opaque
, addr
);
437 return s
->timer
.reset_val
;
440 return omap_timer_read(&s
->timer
);
443 return (s
->timer
.ar
<< 3) | (s
->timer
.it_ena
<< 2) | s
->timer
.st
;
452 static void omap_os_timer_write(void *opaque
, hwaddr addr
,
453 uint64_t value
, unsigned size
)
455 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
456 int offset
= addr
& OMAP_MPUI_REG_MASK
;
459 omap_badwidth_write32(opaque
, addr
, value
);
465 s
->timer
.reset_val
= value
& 0x00ffffff;
473 s
->timer
.ar
= (value
>> 3) & 1;
474 s
->timer
.it_ena
= (value
>> 2) & 1;
475 if (s
->timer
.st
!= (value
& 1) || (value
& 2)) {
476 omap_timer_sync(&s
->timer
);
477 s
->timer
.enable
= value
& 1;
478 s
->timer
.st
= value
& 1;
479 omap_timer_update(&s
->timer
);
488 static const MemoryRegionOps omap_os_timer_ops
= {
489 .read
= omap_os_timer_read
,
490 .write
= omap_os_timer_write
,
491 .endianness
= DEVICE_NATIVE_ENDIAN
,
494 static void omap_os_timer_reset(struct omap_32khz_timer_s
*s
)
496 timer_del(s
->timer
.timer
);
499 s
->timer
.reset_val
= 0x00ffffff;
506 static struct omap_32khz_timer_s
*omap_os_timer_init(MemoryRegion
*memory
,
508 qemu_irq irq
, omap_clk clk
)
510 struct omap_32khz_timer_s
*s
= g_new0(struct omap_32khz_timer_s
, 1);
514 s
->timer
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, &s
->timer
);
515 omap_os_timer_reset(s
);
516 omap_timer_clk_setup(&s
->timer
);
518 memory_region_init_io(&s
->iomem
, NULL
, &omap_os_timer_ops
, s
,
519 "omap-os-timer", 0x800);
520 memory_region_add_subregion(memory
, base
, &s
->iomem
);
525 /* Ultra Low-Power Device Module */
526 static uint64_t omap_ulpd_pm_read(void *opaque
, hwaddr addr
,
529 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
533 return omap_badwidth_read16(opaque
, addr
);
537 case 0x14: /* IT_STATUS */
538 ret
= s
->ulpd_pm_regs
[addr
>> 2];
539 s
->ulpd_pm_regs
[addr
>> 2] = 0;
540 qemu_irq_lower(qdev_get_gpio_in(s
->ih
[1], OMAP_INT_GAUGE_32K
));
543 case 0x18: /* Reserved */
544 case 0x1c: /* Reserved */
545 case 0x20: /* Reserved */
546 case 0x28: /* Reserved */
547 case 0x2c: /* Reserved */
550 case 0x00: /* COUNTER_32_LSB */
551 case 0x04: /* COUNTER_32_MSB */
552 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
553 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
554 case 0x10: /* GAUGING_CTRL */
555 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
556 case 0x30: /* CLOCK_CTRL */
557 case 0x34: /* SOFT_REQ */
558 case 0x38: /* COUNTER_32_FIQ */
559 case 0x3c: /* DPLL_CTRL */
560 case 0x40: /* STATUS_REQ */
561 /* XXX: check clk::usecount state for every clock */
562 case 0x48: /* LOCL_TIME */
563 case 0x4c: /* APLL_CTRL */
564 case 0x50: /* POWER_CTRL */
565 return s
->ulpd_pm_regs
[addr
>> 2];
572 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s
*s
,
573 uint16_t diff
, uint16_t value
)
575 if (diff
& (1 << 4)) /* USB_MCLK_EN */
576 omap_clk_onoff(omap_findclk(s
, "usb_clk0"), (value
>> 4) & 1);
577 if (diff
& (1 << 5)) /* DIS_USB_PVCI_CLK */
578 omap_clk_onoff(omap_findclk(s
, "usb_w2fc_ck"), (~value
>> 5) & 1);
581 static inline void omap_ulpd_req_update(struct omap_mpu_state_s
*s
,
582 uint16_t diff
, uint16_t value
)
584 if (diff
& (1 << 0)) /* SOFT_DPLL_REQ */
585 omap_clk_canidle(omap_findclk(s
, "dpll4"), (~value
>> 0) & 1);
586 if (diff
& (1 << 1)) /* SOFT_COM_REQ */
587 omap_clk_canidle(omap_findclk(s
, "com_mclk_out"), (~value
>> 1) & 1);
588 if (diff
& (1 << 2)) /* SOFT_SDW_REQ */
589 omap_clk_canidle(omap_findclk(s
, "bt_mclk_out"), (~value
>> 2) & 1);
590 if (diff
& (1 << 3)) /* SOFT_USB_REQ */
591 omap_clk_canidle(omap_findclk(s
, "usb_clk0"), (~value
>> 3) & 1);
594 static void omap_ulpd_pm_write(void *opaque
, hwaddr addr
,
595 uint64_t value
, unsigned size
)
597 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
600 static const int bypass_div
[4] = { 1, 2, 4, 4 };
604 omap_badwidth_write16(opaque
, addr
, value
);
609 case 0x00: /* COUNTER_32_LSB */
610 case 0x04: /* COUNTER_32_MSB */
611 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
612 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
613 case 0x14: /* IT_STATUS */
614 case 0x40: /* STATUS_REQ */
618 case 0x10: /* GAUGING_CTRL */
619 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
620 if ((s
->ulpd_pm_regs
[addr
>> 2] ^ value
) & 1) {
621 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
624 s
->ulpd_gauge_start
= now
;
626 now
-= s
->ulpd_gauge_start
;
629 ticks
= muldiv64(now
, 32768, NANOSECONDS_PER_SECOND
);
630 s
->ulpd_pm_regs
[0x00 >> 2] = (ticks
>> 0) & 0xffff;
631 s
->ulpd_pm_regs
[0x04 >> 2] = (ticks
>> 16) & 0xffff;
632 if (ticks
>> 32) /* OVERFLOW_32K */
633 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 2;
635 /* High frequency ticks */
636 ticks
= muldiv64(now
, 12000000, NANOSECONDS_PER_SECOND
);
637 s
->ulpd_pm_regs
[0x08 >> 2] = (ticks
>> 0) & 0xffff;
638 s
->ulpd_pm_regs
[0x0c >> 2] = (ticks
>> 16) & 0xffff;
639 if (ticks
>> 32) /* OVERFLOW_HI_FREQ */
640 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 1;
642 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
643 qemu_irq_raise(qdev_get_gpio_in(s
->ih
[1], OMAP_INT_GAUGE_32K
));
646 s
->ulpd_pm_regs
[addr
>> 2] = value
;
649 case 0x18: /* Reserved */
650 case 0x1c: /* Reserved */
651 case 0x20: /* Reserved */
652 case 0x28: /* Reserved */
653 case 0x2c: /* Reserved */
656 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
657 case 0x38: /* COUNTER_32_FIQ */
658 case 0x48: /* LOCL_TIME */
659 case 0x50: /* POWER_CTRL */
660 s
->ulpd_pm_regs
[addr
>> 2] = value
;
663 case 0x30: /* CLOCK_CTRL */
664 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
665 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x3f;
666 omap_ulpd_clk_update(s
, diff
, value
);
669 case 0x34: /* SOFT_REQ */
670 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
671 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x1f;
672 omap_ulpd_req_update(s
, diff
, value
);
675 case 0x3c: /* DPLL_CTRL */
676 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
677 * omitted altogether, probably a typo. */
678 /* This register has identical semantics with DPLL(1:3) control
679 * registers, see omap_dpll_write() */
680 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
681 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x2fff;
682 if (diff
& (0x3ff << 2)) {
683 if (value
& (1 << 4)) { /* PLL_ENABLE */
684 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
685 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
687 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
690 omap_clk_setrate(omap_findclk(s
, "dpll4"), div
, mult
);
693 /* Enter the desired mode. */
694 s
->ulpd_pm_regs
[addr
>> 2] =
695 (s
->ulpd_pm_regs
[addr
>> 2] & 0xfffe) |
696 ((s
->ulpd_pm_regs
[addr
>> 2] >> 4) & 1);
698 /* Act as if the lock is restored. */
699 s
->ulpd_pm_regs
[addr
>> 2] |= 2;
702 case 0x4c: /* APLL_CTRL */
703 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
704 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0xf;
705 if (diff
& (1 << 0)) /* APLL_NDPLL_SWITCH */
706 omap_clk_reparent(omap_findclk(s
, "ck_48m"), omap_findclk(s
,
707 (value
& (1 << 0)) ? "apll" : "dpll4"));
715 static const MemoryRegionOps omap_ulpd_pm_ops
= {
716 .read
= omap_ulpd_pm_read
,
717 .write
= omap_ulpd_pm_write
,
718 .endianness
= DEVICE_NATIVE_ENDIAN
,
721 static void omap_ulpd_pm_reset(struct omap_mpu_state_s
*mpu
)
723 mpu
->ulpd_pm_regs
[0x00 >> 2] = 0x0001;
724 mpu
->ulpd_pm_regs
[0x04 >> 2] = 0x0000;
725 mpu
->ulpd_pm_regs
[0x08 >> 2] = 0x0001;
726 mpu
->ulpd_pm_regs
[0x0c >> 2] = 0x0000;
727 mpu
->ulpd_pm_regs
[0x10 >> 2] = 0x0000;
728 mpu
->ulpd_pm_regs
[0x18 >> 2] = 0x01;
729 mpu
->ulpd_pm_regs
[0x1c >> 2] = 0x01;
730 mpu
->ulpd_pm_regs
[0x20 >> 2] = 0x01;
731 mpu
->ulpd_pm_regs
[0x24 >> 2] = 0x03ff;
732 mpu
->ulpd_pm_regs
[0x28 >> 2] = 0x01;
733 mpu
->ulpd_pm_regs
[0x2c >> 2] = 0x01;
734 omap_ulpd_clk_update(mpu
, mpu
->ulpd_pm_regs
[0x30 >> 2], 0x0000);
735 mpu
->ulpd_pm_regs
[0x30 >> 2] = 0x0000;
736 omap_ulpd_req_update(mpu
, mpu
->ulpd_pm_regs
[0x34 >> 2], 0x0000);
737 mpu
->ulpd_pm_regs
[0x34 >> 2] = 0x0000;
738 mpu
->ulpd_pm_regs
[0x38 >> 2] = 0x0001;
739 mpu
->ulpd_pm_regs
[0x3c >> 2] = 0x2211;
740 mpu
->ulpd_pm_regs
[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
741 mpu
->ulpd_pm_regs
[0x48 >> 2] = 0x960;
742 mpu
->ulpd_pm_regs
[0x4c >> 2] = 0x08;
743 mpu
->ulpd_pm_regs
[0x50 >> 2] = 0x08;
744 omap_clk_setrate(omap_findclk(mpu
, "dpll4"), 1, 4);
745 omap_clk_reparent(omap_findclk(mpu
, "ck_48m"), omap_findclk(mpu
, "dpll4"));
748 static void omap_ulpd_pm_init(MemoryRegion
*system_memory
,
750 struct omap_mpu_state_s
*mpu
)
752 memory_region_init_io(&mpu
->ulpd_pm_iomem
, NULL
, &omap_ulpd_pm_ops
, mpu
,
753 "omap-ulpd-pm", 0x800);
754 memory_region_add_subregion(system_memory
, base
, &mpu
->ulpd_pm_iomem
);
755 omap_ulpd_pm_reset(mpu
);
758 /* OMAP Pin Configuration */
759 static uint64_t omap_pin_cfg_read(void *opaque
, hwaddr addr
,
762 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
765 return omap_badwidth_read32(opaque
, addr
);
769 case 0x00: /* FUNC_MUX_CTRL_0 */
770 case 0x04: /* FUNC_MUX_CTRL_1 */
771 case 0x08: /* FUNC_MUX_CTRL_2 */
772 return s
->func_mux_ctrl
[addr
>> 2];
774 case 0x0c: /* COMP_MODE_CTRL_0 */
775 return s
->comp_mode_ctrl
[0];
777 case 0x10: /* FUNC_MUX_CTRL_3 */
778 case 0x14: /* FUNC_MUX_CTRL_4 */
779 case 0x18: /* FUNC_MUX_CTRL_5 */
780 case 0x1c: /* FUNC_MUX_CTRL_6 */
781 case 0x20: /* FUNC_MUX_CTRL_7 */
782 case 0x24: /* FUNC_MUX_CTRL_8 */
783 case 0x28: /* FUNC_MUX_CTRL_9 */
784 case 0x2c: /* FUNC_MUX_CTRL_A */
785 case 0x30: /* FUNC_MUX_CTRL_B */
786 case 0x34: /* FUNC_MUX_CTRL_C */
787 case 0x38: /* FUNC_MUX_CTRL_D */
788 return s
->func_mux_ctrl
[(addr
>> 2) - 1];
790 case 0x40: /* PULL_DWN_CTRL_0 */
791 case 0x44: /* PULL_DWN_CTRL_1 */
792 case 0x48: /* PULL_DWN_CTRL_2 */
793 case 0x4c: /* PULL_DWN_CTRL_3 */
794 return s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2];
796 case 0x50: /* GATE_INH_CTRL_0 */
797 return s
->gate_inh_ctrl
[0];
799 case 0x60: /* VOLTAGE_CTRL_0 */
800 return s
->voltage_ctrl
[0];
802 case 0x70: /* TEST_DBG_CTRL_0 */
803 return s
->test_dbg_ctrl
[0];
805 case 0x80: /* MOD_CONF_CTRL_0 */
806 return s
->mod_conf_ctrl
[0];
813 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s
*s
,
814 uint32_t diff
, uint32_t value
)
817 if (diff
& (1 << 9)) /* BLUETOOTH */
818 omap_clk_onoff(omap_findclk(s
, "bt_mclk_out"),
820 if (diff
& (1 << 7)) /* USB.CLKO */
821 omap_clk_onoff(omap_findclk(s
, "usb.clko"),
826 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s
*s
,
827 uint32_t diff
, uint32_t value
)
830 if (diff
& (1U << 31)) {
831 /* MCBSP3_CLK_HIZ_DI */
832 omap_clk_onoff(omap_findclk(s
, "mcbsp3.clkx"), (value
>> 31) & 1);
834 if (diff
& (1 << 1)) {
836 omap_clk_onoff(omap_findclk(s
, "clk32k_out"), (~value
>> 1) & 1);
841 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s
*s
,
842 uint32_t diff
, uint32_t value
)
844 if (diff
& (1U << 31)) {
845 /* CONF_MOD_UART3_CLK_MODE_R */
846 omap_clk_reparent(omap_findclk(s
, "uart3_ck"),
847 omap_findclk(s
, ((value
>> 31) & 1) ?
848 "ck_48m" : "armper_ck"));
850 if (diff
& (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
851 omap_clk_reparent(omap_findclk(s
, "uart2_ck"),
852 omap_findclk(s
, ((value
>> 30) & 1) ?
853 "ck_48m" : "armper_ck"));
854 if (diff
& (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
855 omap_clk_reparent(omap_findclk(s
, "uart1_ck"),
856 omap_findclk(s
, ((value
>> 29) & 1) ?
857 "ck_48m" : "armper_ck"));
858 if (diff
& (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
859 omap_clk_reparent(omap_findclk(s
, "mmc_ck"),
860 omap_findclk(s
, ((value
>> 23) & 1) ?
861 "ck_48m" : "armper_ck"));
862 if (diff
& (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
863 omap_clk_reparent(omap_findclk(s
, "com_mclk_out"),
864 omap_findclk(s
, ((value
>> 12) & 1) ?
865 "ck_48m" : "armper_ck"));
866 if (diff
& (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
867 omap_clk_onoff(omap_findclk(s
, "usb_hhc_ck"), (value
>> 9) & 1);
870 static void omap_pin_cfg_write(void *opaque
, hwaddr addr
,
871 uint64_t value
, unsigned size
)
873 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
877 omap_badwidth_write32(opaque
, addr
, value
);
882 case 0x00: /* FUNC_MUX_CTRL_0 */
883 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
884 s
->func_mux_ctrl
[addr
>> 2] = value
;
885 omap_pin_funcmux0_update(s
, diff
, value
);
888 case 0x04: /* FUNC_MUX_CTRL_1 */
889 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
890 s
->func_mux_ctrl
[addr
>> 2] = value
;
891 omap_pin_funcmux1_update(s
, diff
, value
);
894 case 0x08: /* FUNC_MUX_CTRL_2 */
895 s
->func_mux_ctrl
[addr
>> 2] = value
;
898 case 0x0c: /* COMP_MODE_CTRL_0 */
899 s
->comp_mode_ctrl
[0] = value
;
900 s
->compat1509
= (value
!= 0x0000eaef);
901 omap_pin_funcmux0_update(s
, ~0, s
->func_mux_ctrl
[0]);
902 omap_pin_funcmux1_update(s
, ~0, s
->func_mux_ctrl
[1]);
905 case 0x10: /* FUNC_MUX_CTRL_3 */
906 case 0x14: /* FUNC_MUX_CTRL_4 */
907 case 0x18: /* FUNC_MUX_CTRL_5 */
908 case 0x1c: /* FUNC_MUX_CTRL_6 */
909 case 0x20: /* FUNC_MUX_CTRL_7 */
910 case 0x24: /* FUNC_MUX_CTRL_8 */
911 case 0x28: /* FUNC_MUX_CTRL_9 */
912 case 0x2c: /* FUNC_MUX_CTRL_A */
913 case 0x30: /* FUNC_MUX_CTRL_B */
914 case 0x34: /* FUNC_MUX_CTRL_C */
915 case 0x38: /* FUNC_MUX_CTRL_D */
916 s
->func_mux_ctrl
[(addr
>> 2) - 1] = value
;
919 case 0x40: /* PULL_DWN_CTRL_0 */
920 case 0x44: /* PULL_DWN_CTRL_1 */
921 case 0x48: /* PULL_DWN_CTRL_2 */
922 case 0x4c: /* PULL_DWN_CTRL_3 */
923 s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2] = value
;
926 case 0x50: /* GATE_INH_CTRL_0 */
927 s
->gate_inh_ctrl
[0] = value
;
930 case 0x60: /* VOLTAGE_CTRL_0 */
931 s
->voltage_ctrl
[0] = value
;
934 case 0x70: /* TEST_DBG_CTRL_0 */
935 s
->test_dbg_ctrl
[0] = value
;
938 case 0x80: /* MOD_CONF_CTRL_0 */
939 diff
= s
->mod_conf_ctrl
[0] ^ value
;
940 s
->mod_conf_ctrl
[0] = value
;
941 omap_pin_modconf1_update(s
, diff
, value
);
949 static const MemoryRegionOps omap_pin_cfg_ops
= {
950 .read
= omap_pin_cfg_read
,
951 .write
= omap_pin_cfg_write
,
952 .endianness
= DEVICE_NATIVE_ENDIAN
,
955 static void omap_pin_cfg_reset(struct omap_mpu_state_s
*mpu
)
957 /* Start in Compatibility Mode. */
959 omap_pin_funcmux0_update(mpu
, mpu
->func_mux_ctrl
[0], 0);
960 omap_pin_funcmux1_update(mpu
, mpu
->func_mux_ctrl
[1], 0);
961 omap_pin_modconf1_update(mpu
, mpu
->mod_conf_ctrl
[0], 0);
962 memset(mpu
->func_mux_ctrl
, 0, sizeof(mpu
->func_mux_ctrl
));
963 memset(mpu
->comp_mode_ctrl
, 0, sizeof(mpu
->comp_mode_ctrl
));
964 memset(mpu
->pull_dwn_ctrl
, 0, sizeof(mpu
->pull_dwn_ctrl
));
965 memset(mpu
->gate_inh_ctrl
, 0, sizeof(mpu
->gate_inh_ctrl
));
966 memset(mpu
->voltage_ctrl
, 0, sizeof(mpu
->voltage_ctrl
));
967 memset(mpu
->test_dbg_ctrl
, 0, sizeof(mpu
->test_dbg_ctrl
));
968 memset(mpu
->mod_conf_ctrl
, 0, sizeof(mpu
->mod_conf_ctrl
));
971 static void omap_pin_cfg_init(MemoryRegion
*system_memory
,
973 struct omap_mpu_state_s
*mpu
)
975 memory_region_init_io(&mpu
->pin_cfg_iomem
, NULL
, &omap_pin_cfg_ops
, mpu
,
976 "omap-pin-cfg", 0x800);
977 memory_region_add_subregion(system_memory
, base
, &mpu
->pin_cfg_iomem
);
978 omap_pin_cfg_reset(mpu
);
981 /* Device Identification, Die Identification */
982 static uint64_t omap_id_read(void *opaque
, hwaddr addr
,
985 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
988 return omap_badwidth_read32(opaque
, addr
);
992 case 0xfffe1800: /* DIE_ID_LSB */
994 case 0xfffe1804: /* DIE_ID_MSB */
997 case 0xfffe2000: /* PRODUCT_ID_LSB */
999 case 0xfffe2004: /* PRODUCT_ID_MSB */
1002 case 0xfffed400: /* JTAG_ID_LSB */
1003 switch (s
->mpu_model
) {
1009 hw_error("%s: bad mpu model\n", __func__
);
1013 case 0xfffed404: /* JTAG_ID_MSB */
1014 switch (s
->mpu_model
) {
1020 hw_error("%s: bad mpu model\n", __func__
);
1029 static void omap_id_write(void *opaque
, hwaddr addr
,
1030 uint64_t value
, unsigned size
)
1033 omap_badwidth_write32(opaque
, addr
, value
);
1040 static const MemoryRegionOps omap_id_ops
= {
1041 .read
= omap_id_read
,
1042 .write
= omap_id_write
,
1043 .endianness
= DEVICE_NATIVE_ENDIAN
,
1046 static void omap_id_init(MemoryRegion
*memory
, struct omap_mpu_state_s
*mpu
)
1048 memory_region_init_io(&mpu
->id_iomem
, NULL
, &omap_id_ops
, mpu
,
1049 "omap-id", 0x100000000ULL
);
1050 memory_region_init_alias(&mpu
->id_iomem_e18
, NULL
, "omap-id-e18", &mpu
->id_iomem
,
1052 memory_region_add_subregion(memory
, 0xfffe1800, &mpu
->id_iomem_e18
);
1053 memory_region_init_alias(&mpu
->id_iomem_ed4
, NULL
, "omap-id-ed4", &mpu
->id_iomem
,
1055 memory_region_add_subregion(memory
, 0xfffed400, &mpu
->id_iomem_ed4
);
1056 if (!cpu_is_omap15xx(mpu
)) {
1057 memory_region_init_alias(&mpu
->id_iomem_ed4
, NULL
, "omap-id-e20",
1058 &mpu
->id_iomem
, 0xfffe2000, 0x800);
1059 memory_region_add_subregion(memory
, 0xfffe2000, &mpu
->id_iomem_e20
);
1063 /* MPUI Control (Dummy) */
1064 static uint64_t omap_mpui_read(void *opaque
, hwaddr addr
,
1067 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1070 return omap_badwidth_read32(opaque
, addr
);
1074 case 0x00: /* CTRL */
1075 return s
->mpui_ctrl
;
1076 case 0x04: /* DEBUG_ADDR */
1078 case 0x08: /* DEBUG_DATA */
1080 case 0x0c: /* DEBUG_FLAG */
1082 case 0x10: /* STATUS */
1085 /* Not in OMAP310 */
1086 case 0x14: /* DSP_STATUS */
1087 case 0x18: /* DSP_BOOT_CONFIG */
1089 case 0x1c: /* DSP_MPUI_CONFIG */
1097 static void omap_mpui_write(void *opaque
, hwaddr addr
,
1098 uint64_t value
, unsigned size
)
1100 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1103 omap_badwidth_write32(opaque
, addr
, value
);
1108 case 0x00: /* CTRL */
1109 s
->mpui_ctrl
= value
& 0x007fffff;
1112 case 0x04: /* DEBUG_ADDR */
1113 case 0x08: /* DEBUG_DATA */
1114 case 0x0c: /* DEBUG_FLAG */
1115 case 0x10: /* STATUS */
1116 /* Not in OMAP310 */
1117 case 0x14: /* DSP_STATUS */
1120 case 0x18: /* DSP_BOOT_CONFIG */
1121 case 0x1c: /* DSP_MPUI_CONFIG */
1129 static const MemoryRegionOps omap_mpui_ops
= {
1130 .read
= omap_mpui_read
,
1131 .write
= omap_mpui_write
,
1132 .endianness
= DEVICE_NATIVE_ENDIAN
,
1135 static void omap_mpui_reset(struct omap_mpu_state_s
*s
)
1137 s
->mpui_ctrl
= 0x0003ff1b;
1140 static void omap_mpui_init(MemoryRegion
*memory
, hwaddr base
,
1141 struct omap_mpu_state_s
*mpu
)
1143 memory_region_init_io(&mpu
->mpui_iomem
, NULL
, &omap_mpui_ops
, mpu
,
1144 "omap-mpui", 0x100);
1145 memory_region_add_subregion(memory
, base
, &mpu
->mpui_iomem
);
1147 omap_mpui_reset(mpu
);
1151 struct omap_tipb_bridge_s
{
1159 uint16_t enh_control
;
1162 static uint64_t omap_tipb_bridge_read(void *opaque
, hwaddr addr
,
1165 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1168 return omap_badwidth_read16(opaque
, addr
);
1172 case 0x00: /* TIPB_CNTL */
1174 case 0x04: /* TIPB_BUS_ALLOC */
1176 case 0x08: /* MPU_TIPB_CNTL */
1178 case 0x0c: /* ENHANCED_TIPB_CNTL */
1179 return s
->enh_control
;
1180 case 0x10: /* ADDRESS_DBG */
1181 case 0x14: /* DATA_DEBUG_LOW */
1182 case 0x18: /* DATA_DEBUG_HIGH */
1184 case 0x1c: /* DEBUG_CNTR_SIG */
1192 static void omap_tipb_bridge_write(void *opaque
, hwaddr addr
,
1193 uint64_t value
, unsigned size
)
1195 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1198 omap_badwidth_write16(opaque
, addr
, value
);
1203 case 0x00: /* TIPB_CNTL */
1204 s
->control
= value
& 0xffff;
1207 case 0x04: /* TIPB_BUS_ALLOC */
1208 s
->alloc
= value
& 0x003f;
1211 case 0x08: /* MPU_TIPB_CNTL */
1212 s
->buffer
= value
& 0x0003;
1215 case 0x0c: /* ENHANCED_TIPB_CNTL */
1216 s
->width_intr
= !(value
& 2);
1217 s
->enh_control
= value
& 0x000f;
1220 case 0x10: /* ADDRESS_DBG */
1221 case 0x14: /* DATA_DEBUG_LOW */
1222 case 0x18: /* DATA_DEBUG_HIGH */
1223 case 0x1c: /* DEBUG_CNTR_SIG */
1232 static const MemoryRegionOps omap_tipb_bridge_ops
= {
1233 .read
= omap_tipb_bridge_read
,
1234 .write
= omap_tipb_bridge_write
,
1235 .endianness
= DEVICE_NATIVE_ENDIAN
,
1238 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s
*s
)
1240 s
->control
= 0xffff;
1243 s
->enh_control
= 0x000f;
1246 static struct omap_tipb_bridge_s
*omap_tipb_bridge_init(
1247 MemoryRegion
*memory
, hwaddr base
,
1248 qemu_irq abort_irq
, omap_clk clk
)
1250 struct omap_tipb_bridge_s
*s
= g_new0(struct omap_tipb_bridge_s
, 1);
1252 s
->abort
= abort_irq
;
1253 omap_tipb_bridge_reset(s
);
1255 memory_region_init_io(&s
->iomem
, NULL
, &omap_tipb_bridge_ops
, s
,
1256 "omap-tipb-bridge", 0x100);
1257 memory_region_add_subregion(memory
, base
, &s
->iomem
);
1262 /* Dummy Traffic Controller's Memory Interface */
1263 static uint64_t omap_tcmi_read(void *opaque
, hwaddr addr
,
1266 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1270 return omap_badwidth_read32(opaque
, addr
);
1274 case 0x00: /* IMIF_PRIO */
1275 case 0x04: /* EMIFS_PRIO */
1276 case 0x08: /* EMIFF_PRIO */
1277 case 0x0c: /* EMIFS_CONFIG */
1278 case 0x10: /* EMIFS_CS0_CONFIG */
1279 case 0x14: /* EMIFS_CS1_CONFIG */
1280 case 0x18: /* EMIFS_CS2_CONFIG */
1281 case 0x1c: /* EMIFS_CS3_CONFIG */
1282 case 0x24: /* EMIFF_MRS */
1283 case 0x28: /* TIMEOUT1 */
1284 case 0x2c: /* TIMEOUT2 */
1285 case 0x30: /* TIMEOUT3 */
1286 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1287 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1288 return s
->tcmi_regs
[addr
>> 2];
1290 case 0x20: /* EMIFF_SDRAM_CONFIG */
1291 ret
= s
->tcmi_regs
[addr
>> 2];
1292 s
->tcmi_regs
[addr
>> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1293 /* XXX: We can try using the VGA_DIRTY flag for this */
1301 static void omap_tcmi_write(void *opaque
, hwaddr addr
,
1302 uint64_t value
, unsigned size
)
1304 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1307 omap_badwidth_write32(opaque
, addr
, value
);
1312 case 0x00: /* IMIF_PRIO */
1313 case 0x04: /* EMIFS_PRIO */
1314 case 0x08: /* EMIFF_PRIO */
1315 case 0x10: /* EMIFS_CS0_CONFIG */
1316 case 0x14: /* EMIFS_CS1_CONFIG */
1317 case 0x18: /* EMIFS_CS2_CONFIG */
1318 case 0x1c: /* EMIFS_CS3_CONFIG */
1319 case 0x20: /* EMIFF_SDRAM_CONFIG */
1320 case 0x24: /* EMIFF_MRS */
1321 case 0x28: /* TIMEOUT1 */
1322 case 0x2c: /* TIMEOUT2 */
1323 case 0x30: /* TIMEOUT3 */
1324 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1325 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1326 s
->tcmi_regs
[addr
>> 2] = value
;
1328 case 0x0c: /* EMIFS_CONFIG */
1329 s
->tcmi_regs
[addr
>> 2] = (value
& 0xf) | (1 << 4);
1337 static const MemoryRegionOps omap_tcmi_ops
= {
1338 .read
= omap_tcmi_read
,
1339 .write
= omap_tcmi_write
,
1340 .endianness
= DEVICE_NATIVE_ENDIAN
,
1343 static void omap_tcmi_reset(struct omap_mpu_state_s
*mpu
)
1345 mpu
->tcmi_regs
[0x00 >> 2] = 0x00000000;
1346 mpu
->tcmi_regs
[0x04 >> 2] = 0x00000000;
1347 mpu
->tcmi_regs
[0x08 >> 2] = 0x00000000;
1348 mpu
->tcmi_regs
[0x0c >> 2] = 0x00000010;
1349 mpu
->tcmi_regs
[0x10 >> 2] = 0x0010fffb;
1350 mpu
->tcmi_regs
[0x14 >> 2] = 0x0010fffb;
1351 mpu
->tcmi_regs
[0x18 >> 2] = 0x0010fffb;
1352 mpu
->tcmi_regs
[0x1c >> 2] = 0x0010fffb;
1353 mpu
->tcmi_regs
[0x20 >> 2] = 0x00618800;
1354 mpu
->tcmi_regs
[0x24 >> 2] = 0x00000037;
1355 mpu
->tcmi_regs
[0x28 >> 2] = 0x00000000;
1356 mpu
->tcmi_regs
[0x2c >> 2] = 0x00000000;
1357 mpu
->tcmi_regs
[0x30 >> 2] = 0x00000000;
1358 mpu
->tcmi_regs
[0x3c >> 2] = 0x00000003;
1359 mpu
->tcmi_regs
[0x40 >> 2] = 0x00000000;
1362 static void omap_tcmi_init(MemoryRegion
*memory
, hwaddr base
,
1363 struct omap_mpu_state_s
*mpu
)
1365 memory_region_init_io(&mpu
->tcmi_iomem
, NULL
, &omap_tcmi_ops
, mpu
,
1366 "omap-tcmi", 0x100);
1367 memory_region_add_subregion(memory
, base
, &mpu
->tcmi_iomem
);
1368 omap_tcmi_reset(mpu
);
1371 /* Digital phase-locked loops control */
1378 static uint64_t omap_dpll_read(void *opaque
, hwaddr addr
,
1381 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1384 return omap_badwidth_read16(opaque
, addr
);
1387 if (addr
== 0x00) /* CTL_REG */
1394 static void omap_dpll_write(void *opaque
, hwaddr addr
,
1395 uint64_t value
, unsigned size
)
1397 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1399 static const int bypass_div
[4] = { 1, 2, 4, 4 };
1403 omap_badwidth_write16(opaque
, addr
, value
);
1407 if (addr
== 0x00) { /* CTL_REG */
1408 /* See omap_ulpd_pm_write() too */
1409 diff
= s
->mode
& value
;
1410 s
->mode
= value
& 0x2fff;
1411 if (diff
& (0x3ff << 2)) {
1412 if (value
& (1 << 4)) { /* PLL_ENABLE */
1413 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
1414 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
1416 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
1419 omap_clk_setrate(s
->dpll
, div
, mult
);
1422 /* Enter the desired mode. */
1423 s
->mode
= (s
->mode
& 0xfffe) | ((s
->mode
>> 4) & 1);
1425 /* Act as if the lock is restored. */
1432 static const MemoryRegionOps omap_dpll_ops
= {
1433 .read
= omap_dpll_read
,
1434 .write
= omap_dpll_write
,
1435 .endianness
= DEVICE_NATIVE_ENDIAN
,
1438 static void omap_dpll_reset(struct dpll_ctl_s
*s
)
1441 omap_clk_setrate(s
->dpll
, 1, 1);
1444 static struct dpll_ctl_s
*omap_dpll_init(MemoryRegion
*memory
,
1445 hwaddr base
, omap_clk clk
)
1447 struct dpll_ctl_s
*s
= g_malloc0(sizeof(*s
));
1448 memory_region_init_io(&s
->iomem
, NULL
, &omap_dpll_ops
, s
, "omap-dpll", 0x100);
1453 memory_region_add_subregion(memory
, base
, &s
->iomem
);
1457 /* MPU Clock/Reset/Power Mode Control */
1458 static uint64_t omap_clkm_read(void *opaque
, hwaddr addr
,
1461 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1464 return omap_badwidth_read16(opaque
, addr
);
1468 case 0x00: /* ARM_CKCTL */
1469 return s
->clkm
.arm_ckctl
;
1471 case 0x04: /* ARM_IDLECT1 */
1472 return s
->clkm
.arm_idlect1
;
1474 case 0x08: /* ARM_IDLECT2 */
1475 return s
->clkm
.arm_idlect2
;
1477 case 0x0c: /* ARM_EWUPCT */
1478 return s
->clkm
.arm_ewupct
;
1480 case 0x10: /* ARM_RSTCT1 */
1481 return s
->clkm
.arm_rstct1
;
1483 case 0x14: /* ARM_RSTCT2 */
1484 return s
->clkm
.arm_rstct2
;
1486 case 0x18: /* ARM_SYSST */
1487 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
;
1489 case 0x1c: /* ARM_CKOUT1 */
1490 return s
->clkm
.arm_ckout1
;
1492 case 0x20: /* ARM_CKOUT2 */
1500 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s
*s
,
1501 uint16_t diff
, uint16_t value
)
1505 if (diff
& (1 << 14)) { /* ARM_INTHCK_SEL */
1506 if (value
& (1 << 14))
1509 clk
= omap_findclk(s
, "arminth_ck");
1510 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
1513 if (diff
& (1 << 12)) { /* ARM_TIMXO */
1514 clk
= omap_findclk(s
, "armtim_ck");
1515 if (value
& (1 << 12))
1516 omap_clk_reparent(clk
, omap_findclk(s
, "clkin"));
1518 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
1521 if (diff
& (3 << 10)) { /* DSPMMUDIV */
1522 clk
= omap_findclk(s
, "dspmmu_ck");
1523 omap_clk_setrate(clk
, 1 << ((value
>> 10) & 3), 1);
1525 if (diff
& (3 << 8)) { /* TCDIV */
1526 clk
= omap_findclk(s
, "tc_ck");
1527 omap_clk_setrate(clk
, 1 << ((value
>> 8) & 3), 1);
1529 if (diff
& (3 << 6)) { /* DSPDIV */
1530 clk
= omap_findclk(s
, "dsp_ck");
1531 omap_clk_setrate(clk
, 1 << ((value
>> 6) & 3), 1);
1533 if (diff
& (3 << 4)) { /* ARMDIV */
1534 clk
= omap_findclk(s
, "arm_ck");
1535 omap_clk_setrate(clk
, 1 << ((value
>> 4) & 3), 1);
1537 if (diff
& (3 << 2)) { /* LCDDIV */
1538 clk
= omap_findclk(s
, "lcd_ck");
1539 omap_clk_setrate(clk
, 1 << ((value
>> 2) & 3), 1);
1541 if (diff
& (3 << 0)) { /* PERDIV */
1542 clk
= omap_findclk(s
, "armper_ck");
1543 omap_clk_setrate(clk
, 1 << ((value
>> 0) & 3), 1);
1547 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s
*s
,
1548 uint16_t diff
, uint16_t value
)
1552 if (value
& (1 << 11)) { /* SETARM_IDLE */
1553 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
1555 if (!(value
& (1 << 10))) { /* WKUP_MODE */
1556 /* XXX: disable wakeup from IRQ */
1557 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
1560 #define SET_CANIDLE(clock, bit) \
1561 if (diff & (1 << bit)) { \
1562 clk = omap_findclk(s, clock); \
1563 omap_clk_canidle(clk, (value >> bit) & 1); \
1565 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1566 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1567 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1568 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1569 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1570 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1571 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1572 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1573 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1574 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1575 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1576 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1577 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1578 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1581 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s
*s
,
1582 uint16_t diff
, uint16_t value
)
1586 #define SET_ONOFF(clock, bit) \
1587 if (diff & (1 << bit)) { \
1588 clk = omap_findclk(s, clock); \
1589 omap_clk_onoff(clk, (value >> bit) & 1); \
1591 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1592 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1593 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1594 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1595 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1596 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1597 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1598 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1599 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1600 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1601 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1604 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s
*s
,
1605 uint16_t diff
, uint16_t value
)
1609 if (diff
& (3 << 4)) { /* TCLKOUT */
1610 clk
= omap_findclk(s
, "tclk_out");
1611 switch ((value
>> 4) & 3) {
1613 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen3"));
1614 omap_clk_onoff(clk
, 1);
1617 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
1618 omap_clk_onoff(clk
, 1);
1621 omap_clk_onoff(clk
, 0);
1624 if (diff
& (3 << 2)) { /* DCLKOUT */
1625 clk
= omap_findclk(s
, "dclk_out");
1626 switch ((value
>> 2) & 3) {
1628 omap_clk_reparent(clk
, omap_findclk(s
, "dspmmu_ck"));
1631 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen2"));
1634 omap_clk_reparent(clk
, omap_findclk(s
, "dsp_ck"));
1637 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
1641 if (diff
& (3 << 0)) { /* ACLKOUT */
1642 clk
= omap_findclk(s
, "aclk_out");
1643 switch ((value
>> 0) & 3) {
1645 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
1646 omap_clk_onoff(clk
, 1);
1649 omap_clk_reparent(clk
, omap_findclk(s
, "arm_ck"));
1650 omap_clk_onoff(clk
, 1);
1653 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
1654 omap_clk_onoff(clk
, 1);
1657 omap_clk_onoff(clk
, 0);
1662 static void omap_clkm_write(void *opaque
, hwaddr addr
,
1663 uint64_t value
, unsigned size
)
1665 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1668 static const char *clkschemename
[8] = {
1669 "fully synchronous", "fully asynchronous", "synchronous scalable",
1670 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1674 omap_badwidth_write16(opaque
, addr
, value
);
1679 case 0x00: /* ARM_CKCTL */
1680 diff
= s
->clkm
.arm_ckctl
^ value
;
1681 s
->clkm
.arm_ckctl
= value
& 0x7fff;
1682 omap_clkm_ckctl_update(s
, diff
, value
);
1685 case 0x04: /* ARM_IDLECT1 */
1686 diff
= s
->clkm
.arm_idlect1
^ value
;
1687 s
->clkm
.arm_idlect1
= value
& 0x0fff;
1688 omap_clkm_idlect1_update(s
, diff
, value
);
1691 case 0x08: /* ARM_IDLECT2 */
1692 diff
= s
->clkm
.arm_idlect2
^ value
;
1693 s
->clkm
.arm_idlect2
= value
& 0x07ff;
1694 omap_clkm_idlect2_update(s
, diff
, value
);
1697 case 0x0c: /* ARM_EWUPCT */
1698 s
->clkm
.arm_ewupct
= value
& 0x003f;
1701 case 0x10: /* ARM_RSTCT1 */
1702 diff
= s
->clkm
.arm_rstct1
^ value
;
1703 s
->clkm
.arm_rstct1
= value
& 0x0007;
1705 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
1706 s
->clkm
.cold_start
= 0xa;
1708 if (diff
& ~value
& 4) { /* DSP_RST */
1710 omap_tipb_bridge_reset(s
->private_tipb
);
1711 omap_tipb_bridge_reset(s
->public_tipb
);
1713 if (diff
& 2) { /* DSP_EN */
1714 clk
= omap_findclk(s
, "dsp_ck");
1715 omap_clk_canidle(clk
, (~value
>> 1) & 1);
1719 case 0x14: /* ARM_RSTCT2 */
1720 s
->clkm
.arm_rstct2
= value
& 0x0001;
1723 case 0x18: /* ARM_SYSST */
1724 if ((s
->clkm
.clocking_scheme
^ (value
>> 11)) & 7) {
1725 s
->clkm
.clocking_scheme
= (value
>> 11) & 7;
1726 printf("%s: clocking scheme set to %s\n", __func__
,
1727 clkschemename
[s
->clkm
.clocking_scheme
]);
1729 s
->clkm
.cold_start
&= value
& 0x3f;
1732 case 0x1c: /* ARM_CKOUT1 */
1733 diff
= s
->clkm
.arm_ckout1
^ value
;
1734 s
->clkm
.arm_ckout1
= value
& 0x003f;
1735 omap_clkm_ckout1_update(s
, diff
, value
);
1738 case 0x20: /* ARM_CKOUT2 */
1744 static const MemoryRegionOps omap_clkm_ops
= {
1745 .read
= omap_clkm_read
,
1746 .write
= omap_clkm_write
,
1747 .endianness
= DEVICE_NATIVE_ENDIAN
,
1750 static uint64_t omap_clkdsp_read(void *opaque
, hwaddr addr
,
1753 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1754 CPUState
*cpu
= CPU(s
->cpu
);
1757 return omap_badwidth_read16(opaque
, addr
);
1761 case 0x04: /* DSP_IDLECT1 */
1762 return s
->clkm
.dsp_idlect1
;
1764 case 0x08: /* DSP_IDLECT2 */
1765 return s
->clkm
.dsp_idlect2
;
1767 case 0x14: /* DSP_RSTCT2 */
1768 return s
->clkm
.dsp_rstct2
;
1770 case 0x18: /* DSP_SYSST */
1772 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
|
1773 (cpu
->halted
<< 6); /* Quite useless... */
1780 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s
*s
,
1781 uint16_t diff
, uint16_t value
)
1785 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1788 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s
*s
,
1789 uint16_t diff
, uint16_t value
)
1793 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1796 static void omap_clkdsp_write(void *opaque
, hwaddr addr
,
1797 uint64_t value
, unsigned size
)
1799 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1803 omap_badwidth_write16(opaque
, addr
, value
);
1808 case 0x04: /* DSP_IDLECT1 */
1809 diff
= s
->clkm
.dsp_idlect1
^ value
;
1810 s
->clkm
.dsp_idlect1
= value
& 0x01f7;
1811 omap_clkdsp_idlect1_update(s
, diff
, value
);
1814 case 0x08: /* DSP_IDLECT2 */
1815 s
->clkm
.dsp_idlect2
= value
& 0x0037;
1816 diff
= s
->clkm
.dsp_idlect1
^ value
;
1817 omap_clkdsp_idlect2_update(s
, diff
, value
);
1820 case 0x14: /* DSP_RSTCT2 */
1821 s
->clkm
.dsp_rstct2
= value
& 0x0001;
1824 case 0x18: /* DSP_SYSST */
1825 s
->clkm
.cold_start
&= value
& 0x3f;
1833 static const MemoryRegionOps omap_clkdsp_ops
= {
1834 .read
= omap_clkdsp_read
,
1835 .write
= omap_clkdsp_write
,
1836 .endianness
= DEVICE_NATIVE_ENDIAN
,
1839 static void omap_clkm_reset(struct omap_mpu_state_s
*s
)
1841 if (s
->wdt
&& s
->wdt
->reset
)
1842 s
->clkm
.cold_start
= 0x6;
1843 s
->clkm
.clocking_scheme
= 0;
1844 omap_clkm_ckctl_update(s
, ~0, 0x3000);
1845 s
->clkm
.arm_ckctl
= 0x3000;
1846 omap_clkm_idlect1_update(s
, s
->clkm
.arm_idlect1
^ 0x0400, 0x0400);
1847 s
->clkm
.arm_idlect1
= 0x0400;
1848 omap_clkm_idlect2_update(s
, s
->clkm
.arm_idlect2
^ 0x0100, 0x0100);
1849 s
->clkm
.arm_idlect2
= 0x0100;
1850 s
->clkm
.arm_ewupct
= 0x003f;
1851 s
->clkm
.arm_rstct1
= 0x0000;
1852 s
->clkm
.arm_rstct2
= 0x0000;
1853 s
->clkm
.arm_ckout1
= 0x0015;
1854 s
->clkm
.dpll1_mode
= 0x2002;
1855 omap_clkdsp_idlect1_update(s
, s
->clkm
.dsp_idlect1
^ 0x0040, 0x0040);
1856 s
->clkm
.dsp_idlect1
= 0x0040;
1857 omap_clkdsp_idlect2_update(s
, ~0, 0x0000);
1858 s
->clkm
.dsp_idlect2
= 0x0000;
1859 s
->clkm
.dsp_rstct2
= 0x0000;
1862 static void omap_clkm_init(MemoryRegion
*memory
, hwaddr mpu_base
,
1863 hwaddr dsp_base
, struct omap_mpu_state_s
*s
)
1865 memory_region_init_io(&s
->clkm_iomem
, NULL
, &omap_clkm_ops
, s
,
1866 "omap-clkm", 0x100);
1867 memory_region_init_io(&s
->clkdsp_iomem
, NULL
, &omap_clkdsp_ops
, s
,
1868 "omap-clkdsp", 0x1000);
1870 s
->clkm
.arm_idlect1
= 0x03ff;
1871 s
->clkm
.arm_idlect2
= 0x0100;
1872 s
->clkm
.dsp_idlect1
= 0x0002;
1874 s
->clkm
.cold_start
= 0x3a;
1876 memory_region_add_subregion(memory
, mpu_base
, &s
->clkm_iomem
);
1877 memory_region_add_subregion(memory
, dsp_base
, &s
->clkdsp_iomem
);
1881 struct omap_mpuio_s
{
1885 qemu_irq handler
[16];
1907 static void omap_mpuio_set(void *opaque
, int line
, int level
)
1909 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1910 uint16_t prev
= s
->inputs
;
1913 s
->inputs
|= 1 << line
;
1915 s
->inputs
&= ~(1 << line
);
1917 if (((1 << line
) & s
->dir
& ~s
->mask
) && s
->clk
) {
1918 if ((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) {
1919 s
->ints
|= 1 << line
;
1920 qemu_irq_raise(s
->irq
);
1923 if ((s
->event
& (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1924 (s
->event
>> 1) == line
) /* PIN_SELECT */
1925 s
->latch
= s
->inputs
;
1929 static void omap_mpuio_kbd_update(struct omap_mpuio_s
*s
)
1932 uint8_t *row
, rows
= 0, cols
= ~s
->cols
;
1934 for (row
= s
->buttons
+ 4, i
= 1 << 4; i
; row
--, i
>>= 1)
1938 qemu_set_irq(s
->kbd_irq
, rows
&& !s
->kbd_mask
&& s
->clk
);
1939 s
->row_latch
= ~rows
;
1942 static uint64_t omap_mpuio_read(void *opaque
, hwaddr addr
,
1945 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1946 int offset
= addr
& OMAP_MPUI_REG_MASK
;
1950 return omap_badwidth_read16(opaque
, addr
);
1954 case 0x00: /* INPUT_LATCH */
1957 case 0x04: /* OUTPUT_REG */
1960 case 0x08: /* IO_CNTL */
1963 case 0x10: /* KBR_LATCH */
1964 return s
->row_latch
;
1966 case 0x14: /* KBC_REG */
1969 case 0x18: /* GPIO_EVENT_MODE_REG */
1972 case 0x1c: /* GPIO_INT_EDGE_REG */
1975 case 0x20: /* KBD_INT */
1976 return (~s
->row_latch
& 0x1f) && !s
->kbd_mask
;
1978 case 0x24: /* GPIO_INT */
1982 qemu_irq_lower(s
->irq
);
1985 case 0x28: /* KBD_MASKIT */
1988 case 0x2c: /* GPIO_MASKIT */
1991 case 0x30: /* GPIO_DEBOUNCING_REG */
1994 case 0x34: /* GPIO_LATCH_REG */
2002 static void omap_mpuio_write(void *opaque
, hwaddr addr
,
2003 uint64_t value
, unsigned size
)
2005 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2006 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2011 omap_badwidth_write16(opaque
, addr
, value
);
2016 case 0x04: /* OUTPUT_REG */
2017 diff
= (s
->outputs
^ value
) & ~s
->dir
;
2019 while ((ln
= ctz32(diff
)) != 32) {
2021 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2026 case 0x08: /* IO_CNTL */
2027 diff
= s
->outputs
& (s
->dir
^ value
);
2030 value
= s
->outputs
& ~s
->dir
;
2031 while ((ln
= ctz32(diff
)) != 32) {
2033 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2038 case 0x14: /* KBC_REG */
2040 omap_mpuio_kbd_update(s
);
2043 case 0x18: /* GPIO_EVENT_MODE_REG */
2044 s
->event
= value
& 0x1f;
2047 case 0x1c: /* GPIO_INT_EDGE_REG */
2051 case 0x28: /* KBD_MASKIT */
2052 s
->kbd_mask
= value
& 1;
2053 omap_mpuio_kbd_update(s
);
2056 case 0x2c: /* GPIO_MASKIT */
2060 case 0x30: /* GPIO_DEBOUNCING_REG */
2061 s
->debounce
= value
& 0x1ff;
2064 case 0x00: /* INPUT_LATCH */
2065 case 0x10: /* KBR_LATCH */
2066 case 0x20: /* KBD_INT */
2067 case 0x24: /* GPIO_INT */
2068 case 0x34: /* GPIO_LATCH_REG */
2078 static const MemoryRegionOps omap_mpuio_ops
= {
2079 .read
= omap_mpuio_read
,
2080 .write
= omap_mpuio_write
,
2081 .endianness
= DEVICE_NATIVE_ENDIAN
,
2084 static void omap_mpuio_reset(struct omap_mpuio_s
*s
)
2096 s
->row_latch
= 0x1f;
2100 static void omap_mpuio_onoff(void *opaque
, int line
, int on
)
2102 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2106 omap_mpuio_kbd_update(s
);
2109 static struct omap_mpuio_s
*omap_mpuio_init(MemoryRegion
*memory
,
2111 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
2114 struct omap_mpuio_s
*s
= g_new0(struct omap_mpuio_s
, 1);
2117 s
->kbd_irq
= kbd_int
;
2119 s
->in
= qemu_allocate_irqs(omap_mpuio_set
, s
, 16);
2120 omap_mpuio_reset(s
);
2122 memory_region_init_io(&s
->iomem
, NULL
, &omap_mpuio_ops
, s
,
2123 "omap-mpuio", 0x800);
2124 memory_region_add_subregion(memory
, base
, &s
->iomem
);
2126 omap_clk_adduser(clk
, qemu_allocate_irq(omap_mpuio_onoff
, s
, 0));
2131 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
)
2136 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
)
2138 if (line
>= 16 || line
< 0)
2139 hw_error("%s: No GPIO line %i\n", __func__
, line
);
2140 s
->handler
[line
] = handler
;
2143 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
)
2145 if (row
>= 5 || row
< 0)
2146 hw_error("%s: No key %i-%i\n", __func__
, col
, row
);
2149 s
->buttons
[row
] |= 1 << col
;
2151 s
->buttons
[row
] &= ~(1 << col
);
2153 omap_mpuio_kbd_update(s
);
2156 /* MicroWire Interface */
2157 struct omap_uwire_s
{
2168 uWireSlave
*chip
[4];
2171 static void omap_uwire_transfer_start(struct omap_uwire_s
*s
)
2173 int chipselect
= (s
->control
>> 10) & 3; /* INDEX */
2174 uWireSlave
*slave
= s
->chip
[chipselect
];
2176 if ((s
->control
>> 5) & 0x1f) { /* NB_BITS_WR */
2177 if (s
->control
& (1 << 12)) /* CS_CMD */
2178 if (slave
&& slave
->send
)
2179 slave
->send(slave
->opaque
,
2180 s
->txbuf
>> (16 - ((s
->control
>> 5) & 0x1f)));
2181 s
->control
&= ~(1 << 14); /* CSRB */
2182 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2183 * a DRQ. When is the level IRQ supposed to be reset? */
2186 if ((s
->control
>> 0) & 0x1f) { /* NB_BITS_RD */
2187 if (s
->control
& (1 << 12)) /* CS_CMD */
2188 if (slave
&& slave
->receive
)
2189 s
->rxbuf
= slave
->receive(slave
->opaque
);
2190 s
->control
|= 1 << 15; /* RDRB */
2191 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2192 * a DRQ. When is the level IRQ supposed to be reset? */
2196 static uint64_t omap_uwire_read(void *opaque
, hwaddr addr
,
2199 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
2200 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2203 return omap_badwidth_read16(opaque
, addr
);
2207 case 0x00: /* RDR */
2208 s
->control
&= ~(1 << 15); /* RDRB */
2211 case 0x04: /* CSR */
2214 case 0x08: /* SR1 */
2216 case 0x0c: /* SR2 */
2218 case 0x10: /* SR3 */
2220 case 0x14: /* SR4 */
2222 case 0x18: /* SR5 */
2230 static void omap_uwire_write(void *opaque
, hwaddr addr
,
2231 uint64_t value
, unsigned size
)
2233 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
2234 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2237 omap_badwidth_write16(opaque
, addr
, value
);
2242 case 0x00: /* TDR */
2243 s
->txbuf
= value
; /* TD */
2244 if ((s
->setup
[4] & (1 << 2)) && /* AUTO_TX_EN */
2245 ((s
->setup
[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2246 (s
->control
& (1 << 12)))) { /* CS_CMD */
2247 s
->control
|= 1 << 14; /* CSRB */
2248 omap_uwire_transfer_start(s
);
2252 case 0x04: /* CSR */
2253 s
->control
= value
& 0x1fff;
2254 if (value
& (1 << 13)) /* START */
2255 omap_uwire_transfer_start(s
);
2258 case 0x08: /* SR1 */
2259 s
->setup
[0] = value
& 0x003f;
2262 case 0x0c: /* SR2 */
2263 s
->setup
[1] = value
& 0x0fc0;
2266 case 0x10: /* SR3 */
2267 s
->setup
[2] = value
& 0x0003;
2270 case 0x14: /* SR4 */
2271 s
->setup
[3] = value
& 0x0001;
2274 case 0x18: /* SR5 */
2275 s
->setup
[4] = value
& 0x000f;
2284 static const MemoryRegionOps omap_uwire_ops
= {
2285 .read
= omap_uwire_read
,
2286 .write
= omap_uwire_write
,
2287 .endianness
= DEVICE_NATIVE_ENDIAN
,
2290 static void omap_uwire_reset(struct omap_uwire_s
*s
)
2300 static struct omap_uwire_s
*omap_uwire_init(MemoryRegion
*system_memory
,
2302 qemu_irq txirq
, qemu_irq rxirq
,
2306 struct omap_uwire_s
*s
= g_new0(struct omap_uwire_s
, 1);
2311 omap_uwire_reset(s
);
2313 memory_region_init_io(&s
->iomem
, NULL
, &omap_uwire_ops
, s
, "omap-uwire", 0x800);
2314 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2319 void omap_uwire_attach(struct omap_uwire_s
*s
,
2320 uWireSlave
*slave
, int chipselect
)
2322 if (chipselect
< 0 || chipselect
> 3) {
2323 error_report("%s: Bad chipselect %i", __func__
, chipselect
);
2327 s
->chip
[chipselect
] = slave
;
2330 /* Pseudonoise Pulse-Width Light Modulator */
2339 static void omap_pwl_update(struct omap_pwl_s
*s
)
2341 int output
= (s
->clk
&& s
->enable
) ? s
->level
: 0;
2343 if (output
!= s
->output
) {
2345 printf("%s: Backlight now at %i/256\n", __func__
, output
);
2349 static uint64_t omap_pwl_read(void *opaque
, hwaddr addr
,
2352 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2353 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2356 return omap_badwidth_read8(opaque
, addr
);
2360 case 0x00: /* PWL_LEVEL */
2362 case 0x04: /* PWL_CTRL */
2369 static void omap_pwl_write(void *opaque
, hwaddr addr
,
2370 uint64_t value
, unsigned size
)
2372 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2373 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2376 omap_badwidth_write8(opaque
, addr
, value
);
2381 case 0x00: /* PWL_LEVEL */
2385 case 0x04: /* PWL_CTRL */
2386 s
->enable
= value
& 1;
2395 static const MemoryRegionOps omap_pwl_ops
= {
2396 .read
= omap_pwl_read
,
2397 .write
= omap_pwl_write
,
2398 .endianness
= DEVICE_NATIVE_ENDIAN
,
2401 static void omap_pwl_reset(struct omap_pwl_s
*s
)
2410 static void omap_pwl_clk_update(void *opaque
, int line
, int on
)
2412 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2418 static struct omap_pwl_s
*omap_pwl_init(MemoryRegion
*system_memory
,
2422 struct omap_pwl_s
*s
= g_malloc0(sizeof(*s
));
2426 memory_region_init_io(&s
->iomem
, NULL
, &omap_pwl_ops
, s
,
2428 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2430 omap_clk_adduser(clk
, qemu_allocate_irq(omap_pwl_clk_update
, s
, 0));
2434 /* Pulse-Width Tone module */
2443 static uint64_t omap_pwt_read(void *opaque
, hwaddr addr
,
2446 struct omap_pwt_s
*s
= (struct omap_pwt_s
*) opaque
;
2447 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2450 return omap_badwidth_read8(opaque
, addr
);
2454 case 0x00: /* FRC */
2456 case 0x04: /* VCR */
2458 case 0x08: /* GCR */
2465 static void omap_pwt_write(void *opaque
, hwaddr addr
,
2466 uint64_t value
, unsigned size
)
2468 struct omap_pwt_s
*s
= (struct omap_pwt_s
*) opaque
;
2469 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2472 omap_badwidth_write8(opaque
, addr
, value
);
2477 case 0x00: /* FRC */
2478 s
->frc
= value
& 0x3f;
2480 case 0x04: /* VRC */
2481 if ((value
^ s
->vrc
) & 1) {
2483 printf("%s: %iHz buzz on\n", __func__
, (int)
2484 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2485 ((omap_clk_getrate(s
->clk
) >> 3) /
2486 /* Pre-multiplexer divider */
2487 ((s
->gcr
& 2) ? 1 : 154) /
2488 /* Octave multiplexer */
2489 (2 << (value
& 3)) *
2490 /* 101/107 divider */
2491 ((value
& (1 << 2)) ? 101 : 107) *
2493 ((value
& (1 << 3)) ? 49 : 55) *
2495 ((value
& (1 << 4)) ? 50 : 63) *
2496 /* 80/127 divider */
2497 ((value
& (1 << 5)) ? 80 : 127) /
2498 (107 * 55 * 63 * 127)));
2500 printf("%s: silence!\n", __func__
);
2502 s
->vrc
= value
& 0x7f;
2504 case 0x08: /* GCR */
2513 static const MemoryRegionOps omap_pwt_ops
= {
2514 .read
=omap_pwt_read
,
2515 .write
= omap_pwt_write
,
2516 .endianness
= DEVICE_NATIVE_ENDIAN
,
2519 static void omap_pwt_reset(struct omap_pwt_s
*s
)
2526 static struct omap_pwt_s
*omap_pwt_init(MemoryRegion
*system_memory
,
2530 struct omap_pwt_s
*s
= g_malloc0(sizeof(*s
));
2534 memory_region_init_io(&s
->iomem
, NULL
, &omap_pwt_ops
, s
,
2536 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2540 /* Real-time Clock module */
2557 struct tm current_tm
;
2562 static void omap_rtc_interrupts_update(struct omap_rtc_s
*s
)
2564 /* s->alarm is level-triggered */
2565 qemu_set_irq(s
->alarm
, (s
->status
>> 6) & 1);
2568 static void omap_rtc_alarm_update(struct omap_rtc_s
*s
)
2570 s
->alarm_ti
= mktimegm(&s
->alarm_tm
);
2571 if (s
->alarm_ti
== -1)
2572 printf("%s: conversion failed\n", __func__
);
2575 static uint64_t omap_rtc_read(void *opaque
, hwaddr addr
,
2578 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
2579 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2583 return omap_badwidth_read8(opaque
, addr
);
2587 case 0x00: /* SECONDS_REG */
2588 return to_bcd(s
->current_tm
.tm_sec
);
2590 case 0x04: /* MINUTES_REG */
2591 return to_bcd(s
->current_tm
.tm_min
);
2593 case 0x08: /* HOURS_REG */
2595 return ((s
->current_tm
.tm_hour
> 11) << 7) |
2596 to_bcd(((s
->current_tm
.tm_hour
- 1) % 12) + 1);
2598 return to_bcd(s
->current_tm
.tm_hour
);
2600 case 0x0c: /* DAYS_REG */
2601 return to_bcd(s
->current_tm
.tm_mday
);
2603 case 0x10: /* MONTHS_REG */
2604 return to_bcd(s
->current_tm
.tm_mon
+ 1);
2606 case 0x14: /* YEARS_REG */
2607 return to_bcd(s
->current_tm
.tm_year
% 100);
2609 case 0x18: /* WEEK_REG */
2610 return s
->current_tm
.tm_wday
;
2612 case 0x20: /* ALARM_SECONDS_REG */
2613 return to_bcd(s
->alarm_tm
.tm_sec
);
2615 case 0x24: /* ALARM_MINUTES_REG */
2616 return to_bcd(s
->alarm_tm
.tm_min
);
2618 case 0x28: /* ALARM_HOURS_REG */
2620 return ((s
->alarm_tm
.tm_hour
> 11) << 7) |
2621 to_bcd(((s
->alarm_tm
.tm_hour
- 1) % 12) + 1);
2623 return to_bcd(s
->alarm_tm
.tm_hour
);
2625 case 0x2c: /* ALARM_DAYS_REG */
2626 return to_bcd(s
->alarm_tm
.tm_mday
);
2628 case 0x30: /* ALARM_MONTHS_REG */
2629 return to_bcd(s
->alarm_tm
.tm_mon
+ 1);
2631 case 0x34: /* ALARM_YEARS_REG */
2632 return to_bcd(s
->alarm_tm
.tm_year
% 100);
2634 case 0x40: /* RTC_CTRL_REG */
2635 return (s
->pm_am
<< 3) | (s
->auto_comp
<< 2) |
2636 (s
->round
<< 1) | s
->running
;
2638 case 0x44: /* RTC_STATUS_REG */
2643 case 0x48: /* RTC_INTERRUPTS_REG */
2644 return s
->interrupts
;
2646 case 0x4c: /* RTC_COMP_LSB_REG */
2647 return ((uint16_t) s
->comp_reg
) & 0xff;
2649 case 0x50: /* RTC_COMP_MSB_REG */
2650 return ((uint16_t) s
->comp_reg
) >> 8;
2657 static void omap_rtc_write(void *opaque
, hwaddr addr
,
2658 uint64_t value
, unsigned size
)
2660 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
2661 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2666 omap_badwidth_write8(opaque
, addr
, value
);
2671 case 0x00: /* SECONDS_REG */
2673 printf("RTC SEC_REG <-- %02x\n", value
);
2675 s
->ti
-= s
->current_tm
.tm_sec
;
2676 s
->ti
+= from_bcd(value
);
2679 case 0x04: /* MINUTES_REG */
2681 printf("RTC MIN_REG <-- %02x\n", value
);
2683 s
->ti
-= s
->current_tm
.tm_min
* 60;
2684 s
->ti
+= from_bcd(value
) * 60;
2687 case 0x08: /* HOURS_REG */
2689 printf("RTC HRS_REG <-- %02x\n", value
);
2691 s
->ti
-= s
->current_tm
.tm_hour
* 3600;
2693 s
->ti
+= (from_bcd(value
& 0x3f) & 12) * 3600;
2694 s
->ti
+= ((value
>> 7) & 1) * 43200;
2696 s
->ti
+= from_bcd(value
& 0x3f) * 3600;
2699 case 0x0c: /* DAYS_REG */
2701 printf("RTC DAY_REG <-- %02x\n", value
);
2703 s
->ti
-= s
->current_tm
.tm_mday
* 86400;
2704 s
->ti
+= from_bcd(value
) * 86400;
2707 case 0x10: /* MONTHS_REG */
2709 printf("RTC MTH_REG <-- %02x\n", value
);
2711 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
2712 new_tm
.tm_mon
= from_bcd(value
);
2713 ti
[0] = mktimegm(&s
->current_tm
);
2714 ti
[1] = mktimegm(&new_tm
);
2716 if (ti
[0] != -1 && ti
[1] != -1) {
2720 /* A less accurate version */
2721 s
->ti
-= s
->current_tm
.tm_mon
* 2592000;
2722 s
->ti
+= from_bcd(value
) * 2592000;
2726 case 0x14: /* YEARS_REG */
2728 printf("RTC YRS_REG <-- %02x\n", value
);
2730 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
2731 new_tm
.tm_year
+= from_bcd(value
) - (new_tm
.tm_year
% 100);
2732 ti
[0] = mktimegm(&s
->current_tm
);
2733 ti
[1] = mktimegm(&new_tm
);
2735 if (ti
[0] != -1 && ti
[1] != -1) {
2739 /* A less accurate version */
2740 s
->ti
-= (time_t)(s
->current_tm
.tm_year
% 100) * 31536000;
2741 s
->ti
+= (time_t)from_bcd(value
) * 31536000;
2745 case 0x18: /* WEEK_REG */
2746 return; /* Ignored */
2748 case 0x20: /* ALARM_SECONDS_REG */
2750 printf("ALM SEC_REG <-- %02x\n", value
);
2752 s
->alarm_tm
.tm_sec
= from_bcd(value
);
2753 omap_rtc_alarm_update(s
);
2756 case 0x24: /* ALARM_MINUTES_REG */
2758 printf("ALM MIN_REG <-- %02x\n", value
);
2760 s
->alarm_tm
.tm_min
= from_bcd(value
);
2761 omap_rtc_alarm_update(s
);
2764 case 0x28: /* ALARM_HOURS_REG */
2766 printf("ALM HRS_REG <-- %02x\n", value
);
2769 s
->alarm_tm
.tm_hour
=
2770 ((from_bcd(value
& 0x3f)) % 12) +
2771 ((value
>> 7) & 1) * 12;
2773 s
->alarm_tm
.tm_hour
= from_bcd(value
);
2774 omap_rtc_alarm_update(s
);
2777 case 0x2c: /* ALARM_DAYS_REG */
2779 printf("ALM DAY_REG <-- %02x\n", value
);
2781 s
->alarm_tm
.tm_mday
= from_bcd(value
);
2782 omap_rtc_alarm_update(s
);
2785 case 0x30: /* ALARM_MONTHS_REG */
2787 printf("ALM MON_REG <-- %02x\n", value
);
2789 s
->alarm_tm
.tm_mon
= from_bcd(value
);
2790 omap_rtc_alarm_update(s
);
2793 case 0x34: /* ALARM_YEARS_REG */
2795 printf("ALM YRS_REG <-- %02x\n", value
);
2797 s
->alarm_tm
.tm_year
= from_bcd(value
);
2798 omap_rtc_alarm_update(s
);
2801 case 0x40: /* RTC_CTRL_REG */
2803 printf("RTC CONTROL <-- %02x\n", value
);
2805 s
->pm_am
= (value
>> 3) & 1;
2806 s
->auto_comp
= (value
>> 2) & 1;
2807 s
->round
= (value
>> 1) & 1;
2808 s
->running
= value
& 1;
2810 s
->status
|= s
->running
<< 1;
2813 case 0x44: /* RTC_STATUS_REG */
2815 printf("RTC STATUSL <-- %02x\n", value
);
2817 s
->status
&= ~((value
& 0xc0) ^ 0x80);
2818 omap_rtc_interrupts_update(s
);
2821 case 0x48: /* RTC_INTERRUPTS_REG */
2823 printf("RTC INTRS <-- %02x\n", value
);
2825 s
->interrupts
= value
;
2828 case 0x4c: /* RTC_COMP_LSB_REG */
2830 printf("RTC COMPLSB <-- %02x\n", value
);
2832 s
->comp_reg
&= 0xff00;
2833 s
->comp_reg
|= 0x00ff & value
;
2836 case 0x50: /* RTC_COMP_MSB_REG */
2838 printf("RTC COMPMSB <-- %02x\n", value
);
2840 s
->comp_reg
&= 0x00ff;
2841 s
->comp_reg
|= 0xff00 & (value
<< 8);
2850 static const MemoryRegionOps omap_rtc_ops
= {
2851 .read
= omap_rtc_read
,
2852 .write
= omap_rtc_write
,
2853 .endianness
= DEVICE_NATIVE_ENDIAN
,
2856 static void omap_rtc_tick(void *opaque
)
2858 struct omap_rtc_s
*s
= opaque
;
2861 /* Round to nearest full minute. */
2862 if (s
->current_tm
.tm_sec
< 30)
2863 s
->ti
-= s
->current_tm
.tm_sec
;
2865 s
->ti
+= 60 - s
->current_tm
.tm_sec
;
2870 localtime_r(&s
->ti
, &s
->current_tm
);
2872 if ((s
->interrupts
& 0x08) && s
->ti
== s
->alarm_ti
) {
2874 omap_rtc_interrupts_update(s
);
2877 if (s
->interrupts
& 0x04)
2878 switch (s
->interrupts
& 3) {
2881 qemu_irq_pulse(s
->irq
);
2884 if (s
->current_tm
.tm_sec
)
2887 qemu_irq_pulse(s
->irq
);
2890 if (s
->current_tm
.tm_sec
|| s
->current_tm
.tm_min
)
2893 qemu_irq_pulse(s
->irq
);
2896 if (s
->current_tm
.tm_sec
||
2897 s
->current_tm
.tm_min
|| s
->current_tm
.tm_hour
)
2900 qemu_irq_pulse(s
->irq
);
2910 * Every full hour add a rough approximation of the compensation
2911 * register to the 32kHz Timer (which drives the RTC) value.
2913 if (s
->auto_comp
&& !s
->current_tm
.tm_sec
&& !s
->current_tm
.tm_min
)
2914 s
->tick
+= s
->comp_reg
* 1000 / 32768;
2916 timer_mod(s
->clk
, s
->tick
);
2919 static void omap_rtc_reset(struct omap_rtc_s
*s
)
2929 s
->tick
= qemu_clock_get_ms(rtc_clock
);
2930 memset(&s
->alarm_tm
, 0, sizeof(s
->alarm_tm
));
2931 s
->alarm_tm
.tm_mday
= 0x01;
2933 qemu_get_timedate(&tm
, 0);
2934 s
->ti
= mktimegm(&tm
);
2936 omap_rtc_alarm_update(s
);
2940 static struct omap_rtc_s
*omap_rtc_init(MemoryRegion
*system_memory
,
2942 qemu_irq timerirq
, qemu_irq alarmirq
,
2945 struct omap_rtc_s
*s
= g_new0(struct omap_rtc_s
, 1);
2948 s
->alarm
= alarmirq
;
2949 s
->clk
= timer_new_ms(rtc_clock
, omap_rtc_tick
, s
);
2953 memory_region_init_io(&s
->iomem
, NULL
, &omap_rtc_ops
, s
,
2955 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2960 /* Multi-channel Buffered Serial Port interfaces */
2961 struct omap_mcbsp_s
{
2982 QEMUTimer
*source_timer
;
2983 QEMUTimer
*sink_timer
;
2986 static void omap_mcbsp_intr_update(struct omap_mcbsp_s
*s
)
2990 switch ((s
->spcr
[0] >> 4) & 3) { /* RINTM */
2992 irq
= (s
->spcr
[0] >> 1) & 1; /* RRDY */
2995 irq
= (s
->spcr
[0] >> 3) & 1; /* RSYNCERR */
3003 qemu_irq_pulse(s
->rxirq
);
3005 switch ((s
->spcr
[1] >> 4) & 3) { /* XINTM */
3007 irq
= (s
->spcr
[1] >> 1) & 1; /* XRDY */
3010 irq
= (s
->spcr
[1] >> 3) & 1; /* XSYNCERR */
3018 qemu_irq_pulse(s
->txirq
);
3021 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s
*s
)
3023 if ((s
->spcr
[0] >> 1) & 1) /* RRDY */
3024 s
->spcr
[0] |= 1 << 2; /* RFULL */
3025 s
->spcr
[0] |= 1 << 1; /* RRDY */
3026 qemu_irq_raise(s
->rxdrq
);
3027 omap_mcbsp_intr_update(s
);
3030 static void omap_mcbsp_source_tick(void *opaque
)
3032 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3033 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3038 printf("%s: Rx FIFO overrun\n", __func__
);
3040 s
->rx_req
= s
->rx_rate
<< bps
[(s
->rcr
[0] >> 5) & 7];
3042 omap_mcbsp_rx_newdata(s
);
3043 timer_mod(s
->source_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
3044 NANOSECONDS_PER_SECOND
);
3047 static void omap_mcbsp_rx_start(struct omap_mcbsp_s
*s
)
3049 if (!s
->codec
|| !s
->codec
->rts
)
3050 omap_mcbsp_source_tick(s
);
3051 else if (s
->codec
->in
.len
) {
3052 s
->rx_req
= s
->codec
->in
.len
;
3053 omap_mcbsp_rx_newdata(s
);
3057 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s
*s
)
3059 timer_del(s
->source_timer
);
3062 static void omap_mcbsp_rx_done(struct omap_mcbsp_s
*s
)
3064 s
->spcr
[0] &= ~(1 << 1); /* RRDY */
3065 qemu_irq_lower(s
->rxdrq
);
3066 omap_mcbsp_intr_update(s
);
3069 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s
*s
)
3071 s
->spcr
[1] |= 1 << 1; /* XRDY */
3072 qemu_irq_raise(s
->txdrq
);
3073 omap_mcbsp_intr_update(s
);
3076 static void omap_mcbsp_sink_tick(void *opaque
)
3078 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3079 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3084 printf("%s: Tx FIFO underrun\n", __func__
);
3086 s
->tx_req
= s
->tx_rate
<< bps
[(s
->xcr
[0] >> 5) & 7];
3088 omap_mcbsp_tx_newdata(s
);
3089 timer_mod(s
->sink_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
3090 NANOSECONDS_PER_SECOND
);
3093 static void omap_mcbsp_tx_start(struct omap_mcbsp_s
*s
)
3095 if (!s
->codec
|| !s
->codec
->cts
)
3096 omap_mcbsp_sink_tick(s
);
3097 else if (s
->codec
->out
.size
) {
3098 s
->tx_req
= s
->codec
->out
.size
;
3099 omap_mcbsp_tx_newdata(s
);
3103 static void omap_mcbsp_tx_done(struct omap_mcbsp_s
*s
)
3105 s
->spcr
[1] &= ~(1 << 1); /* XRDY */
3106 qemu_irq_lower(s
->txdrq
);
3107 omap_mcbsp_intr_update(s
);
3108 if (s
->codec
&& s
->codec
->cts
)
3109 s
->codec
->tx_swallow(s
->codec
->opaque
);
3112 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s
*s
)
3115 omap_mcbsp_tx_done(s
);
3116 timer_del(s
->sink_timer
);
3119 static void omap_mcbsp_req_update(struct omap_mcbsp_s
*s
)
3121 int prev_rx_rate
, prev_tx_rate
;
3122 int rx_rate
= 0, tx_rate
= 0;
3123 int cpu_rate
= 1500000; /* XXX */
3125 /* TODO: check CLKSTP bit */
3126 if (s
->spcr
[1] & (1 << 6)) { /* GRST */
3127 if (s
->spcr
[0] & (1 << 0)) { /* RRST */
3128 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3129 (s
->pcr
& (1 << 8))) { /* CLKRM */
3130 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3131 rx_rate
= cpu_rate
/
3132 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3135 rx_rate
= s
->codec
->rx_rate
;
3138 if (s
->spcr
[1] & (1 << 0)) { /* XRST */
3139 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3140 (s
->pcr
& (1 << 9))) { /* CLKXM */
3141 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3142 tx_rate
= cpu_rate
/
3143 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3146 tx_rate
= s
->codec
->tx_rate
;
3149 prev_tx_rate
= s
->tx_rate
;
3150 prev_rx_rate
= s
->rx_rate
;
3151 s
->tx_rate
= tx_rate
;
3152 s
->rx_rate
= rx_rate
;
3155 s
->codec
->set_rate(s
->codec
->opaque
, rx_rate
, tx_rate
);
3157 if (!prev_tx_rate
&& tx_rate
)
3158 omap_mcbsp_tx_start(s
);
3159 else if (s
->tx_rate
&& !tx_rate
)
3160 omap_mcbsp_tx_stop(s
);
3162 if (!prev_rx_rate
&& rx_rate
)
3163 omap_mcbsp_rx_start(s
);
3164 else if (prev_tx_rate
&& !tx_rate
)
3165 omap_mcbsp_rx_stop(s
);
3168 static uint64_t omap_mcbsp_read(void *opaque
, hwaddr addr
,
3171 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3172 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3176 return omap_badwidth_read16(opaque
, addr
);
3180 case 0x00: /* DRR2 */
3181 if (((s
->rcr
[0] >> 5) & 7) < 3) /* RWDLEN1 */
3184 case 0x02: /* DRR1 */
3185 if (s
->rx_req
< 2) {
3186 printf("%s: Rx FIFO underrun\n", __func__
);
3187 omap_mcbsp_rx_done(s
);
3190 if (s
->codec
&& s
->codec
->in
.len
>= 2) {
3191 ret
= s
->codec
->in
.fifo
[s
->codec
->in
.start
++] << 8;
3192 ret
|= s
->codec
->in
.fifo
[s
->codec
->in
.start
++];
3193 s
->codec
->in
.len
-= 2;
3197 omap_mcbsp_rx_done(s
);
3202 case 0x04: /* DXR2 */
3203 case 0x06: /* DXR1 */
3206 case 0x08: /* SPCR2 */
3208 case 0x0a: /* SPCR1 */
3210 case 0x0c: /* RCR2 */
3212 case 0x0e: /* RCR1 */
3214 case 0x10: /* XCR2 */
3216 case 0x12: /* XCR1 */
3218 case 0x14: /* SRGR2 */
3220 case 0x16: /* SRGR1 */
3222 case 0x18: /* MCR2 */
3224 case 0x1a: /* MCR1 */
3226 case 0x1c: /* RCERA */
3228 case 0x1e: /* RCERB */
3230 case 0x20: /* XCERA */
3232 case 0x22: /* XCERB */
3234 case 0x24: /* PCR0 */
3236 case 0x26: /* RCERC */
3238 case 0x28: /* RCERD */
3240 case 0x2a: /* XCERC */
3242 case 0x2c: /* XCERD */
3244 case 0x2e: /* RCERE */
3246 case 0x30: /* RCERF */
3248 case 0x32: /* XCERE */
3250 case 0x34: /* XCERF */
3252 case 0x36: /* RCERG */
3254 case 0x38: /* RCERH */
3256 case 0x3a: /* XCERG */
3258 case 0x3c: /* XCERH */
3266 static void omap_mcbsp_writeh(void *opaque
, hwaddr addr
,
3269 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3270 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3273 case 0x00: /* DRR2 */
3274 case 0x02: /* DRR1 */
3278 case 0x04: /* DXR2 */
3279 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
3282 case 0x06: /* DXR1 */
3283 if (s
->tx_req
> 1) {
3285 if (s
->codec
&& s
->codec
->cts
) {
3286 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 8) & 0xff;
3287 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 0) & 0xff;
3290 omap_mcbsp_tx_done(s
);
3292 printf("%s: Tx FIFO overrun\n", __func__
);
3295 case 0x08: /* SPCR2 */
3296 s
->spcr
[1] &= 0x0002;
3297 s
->spcr
[1] |= 0x03f9 & value
;
3298 s
->spcr
[1] |= 0x0004 & (value
<< 2); /* XEMPTY := XRST */
3299 if (~value
& 1) /* XRST */
3301 omap_mcbsp_req_update(s
);
3303 case 0x0a: /* SPCR1 */
3304 s
->spcr
[0] &= 0x0006;
3305 s
->spcr
[0] |= 0xf8f9 & value
;
3306 if (value
& (1 << 15)) /* DLB */
3307 printf("%s: Digital Loopback mode enable attempt\n", __func__
);
3308 if (~value
& 1) { /* RRST */
3311 omap_mcbsp_rx_done(s
);
3313 omap_mcbsp_req_update(s
);
3316 case 0x0c: /* RCR2 */
3317 s
->rcr
[1] = value
& 0xffff;
3319 case 0x0e: /* RCR1 */
3320 s
->rcr
[0] = value
& 0x7fe0;
3322 case 0x10: /* XCR2 */
3323 s
->xcr
[1] = value
& 0xffff;
3325 case 0x12: /* XCR1 */
3326 s
->xcr
[0] = value
& 0x7fe0;
3328 case 0x14: /* SRGR2 */
3329 s
->srgr
[1] = value
& 0xffff;
3330 omap_mcbsp_req_update(s
);
3332 case 0x16: /* SRGR1 */
3333 s
->srgr
[0] = value
& 0xffff;
3334 omap_mcbsp_req_update(s
);
3336 case 0x18: /* MCR2 */
3337 s
->mcr
[1] = value
& 0x03e3;
3338 if (value
& 3) /* XMCM */
3339 printf("%s: Tx channel selection mode enable attempt\n", __func__
);
3341 case 0x1a: /* MCR1 */
3342 s
->mcr
[0] = value
& 0x03e1;
3343 if (value
& 1) /* RMCM */
3344 printf("%s: Rx channel selection mode enable attempt\n", __func__
);
3346 case 0x1c: /* RCERA */
3347 s
->rcer
[0] = value
& 0xffff;
3349 case 0x1e: /* RCERB */
3350 s
->rcer
[1] = value
& 0xffff;
3352 case 0x20: /* XCERA */
3353 s
->xcer
[0] = value
& 0xffff;
3355 case 0x22: /* XCERB */
3356 s
->xcer
[1] = value
& 0xffff;
3358 case 0x24: /* PCR0 */
3359 s
->pcr
= value
& 0x7faf;
3361 case 0x26: /* RCERC */
3362 s
->rcer
[2] = value
& 0xffff;
3364 case 0x28: /* RCERD */
3365 s
->rcer
[3] = value
& 0xffff;
3367 case 0x2a: /* XCERC */
3368 s
->xcer
[2] = value
& 0xffff;
3370 case 0x2c: /* XCERD */
3371 s
->xcer
[3] = value
& 0xffff;
3373 case 0x2e: /* RCERE */
3374 s
->rcer
[4] = value
& 0xffff;
3376 case 0x30: /* RCERF */
3377 s
->rcer
[5] = value
& 0xffff;
3379 case 0x32: /* XCERE */
3380 s
->xcer
[4] = value
& 0xffff;
3382 case 0x34: /* XCERF */
3383 s
->xcer
[5] = value
& 0xffff;
3385 case 0x36: /* RCERG */
3386 s
->rcer
[6] = value
& 0xffff;
3388 case 0x38: /* RCERH */
3389 s
->rcer
[7] = value
& 0xffff;
3391 case 0x3a: /* XCERG */
3392 s
->xcer
[6] = value
& 0xffff;
3394 case 0x3c: /* XCERH */
3395 s
->xcer
[7] = value
& 0xffff;
3402 static void omap_mcbsp_writew(void *opaque
, hwaddr addr
,
3405 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3406 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3408 if (offset
== 0x04) { /* DXR */
3409 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
3411 if (s
->tx_req
> 3) {
3413 if (s
->codec
&& s
->codec
->cts
) {
3414 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3415 (value
>> 24) & 0xff;
3416 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3417 (value
>> 16) & 0xff;
3418 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3419 (value
>> 8) & 0xff;
3420 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3421 (value
>> 0) & 0xff;
3424 omap_mcbsp_tx_done(s
);
3426 printf("%s: Tx FIFO overrun\n", __func__
);
3430 omap_badwidth_write16(opaque
, addr
, value
);
3433 static void omap_mcbsp_write(void *opaque
, hwaddr addr
,
3434 uint64_t value
, unsigned size
)
3438 omap_mcbsp_writeh(opaque
, addr
, value
);
3441 omap_mcbsp_writew(opaque
, addr
, value
);
3444 omap_badwidth_write16(opaque
, addr
, value
);
3448 static const MemoryRegionOps omap_mcbsp_ops
= {
3449 .read
= omap_mcbsp_read
,
3450 .write
= omap_mcbsp_write
,
3451 .endianness
= DEVICE_NATIVE_ENDIAN
,
3454 static void omap_mcbsp_reset(struct omap_mcbsp_s
*s
)
3456 memset(&s
->spcr
, 0, sizeof(s
->spcr
));
3457 memset(&s
->rcr
, 0, sizeof(s
->rcr
));
3458 memset(&s
->xcr
, 0, sizeof(s
->xcr
));
3459 s
->srgr
[0] = 0x0001;
3460 s
->srgr
[1] = 0x2000;
3461 memset(&s
->mcr
, 0, sizeof(s
->mcr
));
3462 memset(&s
->pcr
, 0, sizeof(s
->pcr
));
3463 memset(&s
->rcer
, 0, sizeof(s
->rcer
));
3464 memset(&s
->xcer
, 0, sizeof(s
->xcer
));
3469 timer_del(s
->source_timer
);
3470 timer_del(s
->sink_timer
);
3473 static struct omap_mcbsp_s
*omap_mcbsp_init(MemoryRegion
*system_memory
,
3475 qemu_irq txirq
, qemu_irq rxirq
,
3476 qemu_irq
*dma
, omap_clk clk
)
3478 struct omap_mcbsp_s
*s
= g_new0(struct omap_mcbsp_s
, 1);
3484 s
->sink_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_mcbsp_sink_tick
, s
);
3485 s
->source_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_mcbsp_source_tick
, s
);
3486 omap_mcbsp_reset(s
);
3488 memory_region_init_io(&s
->iomem
, NULL
, &omap_mcbsp_ops
, s
, "omap-mcbsp", 0x800);
3489 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
3494 static void omap_mcbsp_i2s_swallow(void *opaque
, int line
, int level
)
3496 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3499 s
->rx_req
= s
->codec
->in
.len
;
3500 omap_mcbsp_rx_newdata(s
);
3504 static void omap_mcbsp_i2s_start(void *opaque
, int line
, int level
)
3506 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3509 s
->tx_req
= s
->codec
->out
.size
;
3510 omap_mcbsp_tx_newdata(s
);
3514 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, I2SCodec
*slave
)
3517 slave
->rx_swallow
= qemu_allocate_irq(omap_mcbsp_i2s_swallow
, s
, 0);
3518 slave
->tx_start
= qemu_allocate_irq(omap_mcbsp_i2s_start
, s
, 0);
3521 /* LED Pulse Generators */
3534 static void omap_lpg_tick(void *opaque
)
3536 struct omap_lpg_s
*s
= opaque
;
3539 timer_mod(s
->tm
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + s
->period
- s
->on
);
3541 timer_mod(s
->tm
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + s
->on
);
3543 s
->cycle
= !s
->cycle
;
3544 printf("%s: LED is %s\n", __func__
, s
->cycle
? "on" : "off");
3547 static void omap_lpg_update(struct omap_lpg_s
*s
)
3549 int64_t on
, period
= 1, ticks
= 1000;
3550 static const int per
[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3552 if (~s
->control
& (1 << 6)) /* LPGRES */
3554 else if (s
->control
& (1 << 7)) /* PERM_ON */
3557 period
= muldiv64(ticks
, per
[s
->control
& 7], /* PERCTRL */
3559 on
= (s
->clk
&& s
->power
) ? muldiv64(ticks
,
3560 per
[(s
->control
>> 3) & 7], 256) : 0; /* ONCTRL */
3564 if (on
== period
&& s
->on
< s
->period
)
3565 printf("%s: LED is on\n", __func__
);
3566 else if (on
== 0 && s
->on
)
3567 printf("%s: LED is off\n", __func__
);
3568 else if (on
&& (on
!= s
->on
|| period
!= s
->period
)) {
3580 static void omap_lpg_reset(struct omap_lpg_s
*s
)
3588 static uint64_t omap_lpg_read(void *opaque
, hwaddr addr
,
3591 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3592 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3595 return omap_badwidth_read8(opaque
, addr
);
3599 case 0x00: /* LCR */
3602 case 0x04: /* PMR */
3610 static void omap_lpg_write(void *opaque
, hwaddr addr
,
3611 uint64_t value
, unsigned size
)
3613 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3614 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3617 omap_badwidth_write8(opaque
, addr
, value
);
3622 case 0x00: /* LCR */
3623 if (~value
& (1 << 6)) /* LPGRES */
3625 s
->control
= value
& 0xff;
3629 case 0x04: /* PMR */
3630 s
->power
= value
& 0x01;
3640 static const MemoryRegionOps omap_lpg_ops
= {
3641 .read
= omap_lpg_read
,
3642 .write
= omap_lpg_write
,
3643 .endianness
= DEVICE_NATIVE_ENDIAN
,
3646 static void omap_lpg_clk_update(void *opaque
, int line
, int on
)
3648 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3654 static struct omap_lpg_s
*omap_lpg_init(MemoryRegion
*system_memory
,
3655 hwaddr base
, omap_clk clk
)
3657 struct omap_lpg_s
*s
= g_new0(struct omap_lpg_s
, 1);
3659 s
->tm
= timer_new_ms(QEMU_CLOCK_VIRTUAL
, omap_lpg_tick
, s
);
3663 memory_region_init_io(&s
->iomem
, NULL
, &omap_lpg_ops
, s
, "omap-lpg", 0x800);
3664 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
3666 omap_clk_adduser(clk
, qemu_allocate_irq(omap_lpg_clk_update
, s
, 0));
3671 /* MPUI Peripheral Bridge configuration */
3672 static uint64_t omap_mpui_io_read(void *opaque
, hwaddr addr
,
3676 return omap_badwidth_read16(opaque
, addr
);
3679 if (addr
== OMAP_MPUI_BASE
) /* CMR */
3686 static void omap_mpui_io_write(void *opaque
, hwaddr addr
,
3687 uint64_t value
, unsigned size
)
3689 /* FIXME: infinite loop */
3690 omap_badwidth_write16(opaque
, addr
, value
);
3693 static const MemoryRegionOps omap_mpui_io_ops
= {
3694 .read
= omap_mpui_io_read
,
3695 .write
= omap_mpui_io_write
,
3696 .endianness
= DEVICE_NATIVE_ENDIAN
,
3699 static void omap_setup_mpui_io(MemoryRegion
*system_memory
,
3700 struct omap_mpu_state_s
*mpu
)
3702 memory_region_init_io(&mpu
->mpui_io_iomem
, NULL
, &omap_mpui_io_ops
, mpu
,
3703 "omap-mpui-io", 0x7fff);
3704 memory_region_add_subregion(system_memory
, OMAP_MPUI_BASE
,
3705 &mpu
->mpui_io_iomem
);
3708 /* General chip reset */
3709 static void omap1_mpu_reset(void *opaque
)
3711 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
3713 omap_dma_reset(mpu
->dma
);
3714 omap_mpu_timer_reset(mpu
->timer
[0]);
3715 omap_mpu_timer_reset(mpu
->timer
[1]);
3716 omap_mpu_timer_reset(mpu
->timer
[2]);
3717 omap_wd_timer_reset(mpu
->wdt
);
3718 omap_os_timer_reset(mpu
->os_timer
);
3719 omap_lcdc_reset(mpu
->lcd
);
3720 omap_ulpd_pm_reset(mpu
);
3721 omap_pin_cfg_reset(mpu
);
3722 omap_mpui_reset(mpu
);
3723 omap_tipb_bridge_reset(mpu
->private_tipb
);
3724 omap_tipb_bridge_reset(mpu
->public_tipb
);
3725 omap_dpll_reset(mpu
->dpll
[0]);
3726 omap_dpll_reset(mpu
->dpll
[1]);
3727 omap_dpll_reset(mpu
->dpll
[2]);
3728 omap_uart_reset(mpu
->uart
[0]);
3729 omap_uart_reset(mpu
->uart
[1]);
3730 omap_uart_reset(mpu
->uart
[2]);
3731 omap_mmc_reset(mpu
->mmc
);
3732 omap_mpuio_reset(mpu
->mpuio
);
3733 omap_uwire_reset(mpu
->microwire
);
3734 omap_pwl_reset(mpu
->pwl
);
3735 omap_pwt_reset(mpu
->pwt
);
3736 omap_rtc_reset(mpu
->rtc
);
3737 omap_mcbsp_reset(mpu
->mcbsp1
);
3738 omap_mcbsp_reset(mpu
->mcbsp2
);
3739 omap_mcbsp_reset(mpu
->mcbsp3
);
3740 omap_lpg_reset(mpu
->led
[0]);
3741 omap_lpg_reset(mpu
->led
[1]);
3742 omap_clkm_reset(mpu
);
3743 cpu_reset(CPU(mpu
->cpu
));
3746 static const struct omap_map_s
{
3751 } omap15xx_dsp_mm
[] = {
3753 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3754 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3755 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3756 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3757 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3758 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3759 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3760 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3761 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3762 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3763 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3764 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3765 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3766 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3767 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3768 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3769 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3771 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3776 static void omap_setup_dsp_mapping(MemoryRegion
*system_memory
,
3777 const struct omap_map_s
*map
)
3781 for (; map
->phys_dsp
; map
++) {
3782 io
= g_new(MemoryRegion
, 1);
3783 memory_region_init_alias(io
, NULL
, map
->name
,
3784 system_memory
, map
->phys_mpu
, map
->size
);
3785 memory_region_add_subregion(system_memory
, map
->phys_dsp
, io
);
3789 void omap_mpu_wakeup(void *opaque
, int irq
, int req
)
3791 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
3792 CPUState
*cpu
= CPU(mpu
->cpu
);
3795 cpu_interrupt(cpu
, CPU_INTERRUPT_EXITTB
);
3799 static const struct dma_irq_map omap1_dma_irq_map
[] = {
3800 { 0, OMAP_INT_DMA_CH0_6
},
3801 { 0, OMAP_INT_DMA_CH1_7
},
3802 { 0, OMAP_INT_DMA_CH2_8
},
3803 { 0, OMAP_INT_DMA_CH3
},
3804 { 0, OMAP_INT_DMA_CH4
},
3805 { 0, OMAP_INT_DMA_CH5
},
3806 { 1, OMAP_INT_1610_DMA_CH6
},
3807 { 1, OMAP_INT_1610_DMA_CH7
},
3808 { 1, OMAP_INT_1610_DMA_CH8
},
3809 { 1, OMAP_INT_1610_DMA_CH9
},
3810 { 1, OMAP_INT_1610_DMA_CH10
},
3811 { 1, OMAP_INT_1610_DMA_CH11
},
3812 { 1, OMAP_INT_1610_DMA_CH12
},
3813 { 1, OMAP_INT_1610_DMA_CH13
},
3814 { 1, OMAP_INT_1610_DMA_CH14
},
3815 { 1, OMAP_INT_1610_DMA_CH15
}
3818 /* DMA ports for OMAP1 */
3819 static int omap_validate_emiff_addr(struct omap_mpu_state_s
*s
,
3822 return range_covers_byte(OMAP_EMIFF_BASE
, s
->sdram_size
, addr
);
3825 static int omap_validate_emifs_addr(struct omap_mpu_state_s
*s
,
3828 return range_covers_byte(OMAP_EMIFS_BASE
, OMAP_EMIFF_BASE
- OMAP_EMIFS_BASE
,
3832 static int omap_validate_imif_addr(struct omap_mpu_state_s
*s
,
3835 return range_covers_byte(OMAP_IMIF_BASE
, s
->sram_size
, addr
);
3838 static int omap_validate_tipb_addr(struct omap_mpu_state_s
*s
,
3841 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr
);
3844 static int omap_validate_local_addr(struct omap_mpu_state_s
*s
,
3847 return range_covers_byte(OMAP_LOCALBUS_BASE
, 0x1000000, addr
);
3850 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s
*s
,
3853 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr
);
3856 struct omap_mpu_state_s
*omap310_mpu_init(MemoryRegion
*system_memory
,
3857 unsigned long sdram_size
,
3858 const char *cpu_type
)
3861 struct omap_mpu_state_s
*s
= g_new0(struct omap_mpu_state_s
, 1);
3862 qemu_irq dma_irqs
[6];
3864 SysBusDevice
*busdev
;
3867 s
->mpu_model
= omap310
;
3868 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
3869 s
->sdram_size
= sdram_size
;
3870 s
->sram_size
= OMAP15XX_SRAM_SIZE
;
3872 s
->wakeup
= qemu_allocate_irq(omap_mpu_wakeup
, s
, 0);
3877 /* Memory-mapped stuff */
3878 memory_region_allocate_system_memory(&s
->emiff_ram
, NULL
, "omap1.dram",
3880 memory_region_add_subregion(system_memory
, OMAP_EMIFF_BASE
, &s
->emiff_ram
);
3881 memory_region_init_ram(&s
->imif_ram
, NULL
, "omap1.sram", s
->sram_size
,
3883 memory_region_add_subregion(system_memory
, OMAP_IMIF_BASE
, &s
->imif_ram
);
3885 omap_clkm_init(system_memory
, 0xfffece00, 0xe1008000, s
);
3887 s
->ih
[0] = qdev_create(NULL
, "omap-intc");
3888 qdev_prop_set_uint32(s
->ih
[0], "size", 0x100);
3889 qdev_prop_set_ptr(s
->ih
[0], "clk", omap_findclk(s
, "arminth_ck"));
3890 qdev_init_nofail(s
->ih
[0]);
3891 busdev
= SYS_BUS_DEVICE(s
->ih
[0]);
3892 sysbus_connect_irq(busdev
, 0,
3893 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
));
3894 sysbus_connect_irq(busdev
, 1,
3895 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
));
3896 sysbus_mmio_map(busdev
, 0, 0xfffecb00);
3897 s
->ih
[1] = qdev_create(NULL
, "omap-intc");
3898 qdev_prop_set_uint32(s
->ih
[1], "size", 0x800);
3899 qdev_prop_set_ptr(s
->ih
[1], "clk", omap_findclk(s
, "arminth_ck"));
3900 qdev_init_nofail(s
->ih
[1]);
3901 busdev
= SYS_BUS_DEVICE(s
->ih
[1]);
3902 sysbus_connect_irq(busdev
, 0,
3903 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_15XX_IH2_IRQ
));
3904 /* The second interrupt controller's FIQ output is not wired up */
3905 sysbus_mmio_map(busdev
, 0, 0xfffe0000);
3907 for (i
= 0; i
< 6; i
++) {
3908 dma_irqs
[i
] = qdev_get_gpio_in(s
->ih
[omap1_dma_irq_map
[i
].ih
],
3909 omap1_dma_irq_map
[i
].intr
);
3911 s
->dma
= omap_dma_init(0xfffed800, dma_irqs
, system_memory
,
3912 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_DMA_LCD
),
3913 s
, omap_findclk(s
, "dma_ck"), omap_dma_3_1
);
3915 s
->port
[emiff
].addr_valid
= omap_validate_emiff_addr
;
3916 s
->port
[emifs
].addr_valid
= omap_validate_emifs_addr
;
3917 s
->port
[imif
].addr_valid
= omap_validate_imif_addr
;
3918 s
->port
[tipb
].addr_valid
= omap_validate_tipb_addr
;
3919 s
->port
[local
].addr_valid
= omap_validate_local_addr
;
3920 s
->port
[tipb_mpui
].addr_valid
= omap_validate_tipb_mpui_addr
;
3922 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3923 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->emiff_ram
),
3924 OMAP_EMIFF_BASE
, s
->sdram_size
);
3925 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->imif_ram
),
3926 OMAP_IMIF_BASE
, s
->sram_size
);
3928 s
->timer
[0] = omap_mpu_timer_init(system_memory
, 0xfffec500,
3929 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER1
),
3930 omap_findclk(s
, "mputim_ck"));
3931 s
->timer
[1] = omap_mpu_timer_init(system_memory
, 0xfffec600,
3932 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER2
),
3933 omap_findclk(s
, "mputim_ck"));
3934 s
->timer
[2] = omap_mpu_timer_init(system_memory
, 0xfffec700,
3935 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER3
),
3936 omap_findclk(s
, "mputim_ck"));
3938 s
->wdt
= omap_wd_timer_init(system_memory
, 0xfffec800,
3939 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_WD_TIMER
),
3940 omap_findclk(s
, "armwdt_ck"));
3942 s
->os_timer
= omap_os_timer_init(system_memory
, 0xfffb9000,
3943 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_OS_TIMER
),
3944 omap_findclk(s
, "clk32-kHz"));
3946 s
->lcd
= omap_lcdc_init(system_memory
, 0xfffec000,
3947 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_LCD_CTRL
),
3948 omap_dma_get_lcdch(s
->dma
),
3949 omap_findclk(s
, "lcd_ck"));
3951 omap_ulpd_pm_init(system_memory
, 0xfffe0800, s
);
3952 omap_pin_cfg_init(system_memory
, 0xfffe1000, s
);
3953 omap_id_init(system_memory
, s
);
3955 omap_mpui_init(system_memory
, 0xfffec900, s
);
3957 s
->private_tipb
= omap_tipb_bridge_init(system_memory
, 0xfffeca00,
3958 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_BRIDGE_PRIV
),
3959 omap_findclk(s
, "tipb_ck"));
3960 s
->public_tipb
= omap_tipb_bridge_init(system_memory
, 0xfffed300,
3961 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_BRIDGE_PUB
),
3962 omap_findclk(s
, "tipb_ck"));
3964 omap_tcmi_init(system_memory
, 0xfffecc00, s
);
3966 s
->uart
[0] = omap_uart_init(0xfffb0000,
3967 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_UART1
),
3968 omap_findclk(s
, "uart1_ck"),
3969 omap_findclk(s
, "uart1_ck"),
3970 s
->drq
[OMAP_DMA_UART1_TX
], s
->drq
[OMAP_DMA_UART1_RX
],
3973 s
->uart
[1] = omap_uart_init(0xfffb0800,
3974 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_UART2
),
3975 omap_findclk(s
, "uart2_ck"),
3976 omap_findclk(s
, "uart2_ck"),
3977 s
->drq
[OMAP_DMA_UART2_TX
], s
->drq
[OMAP_DMA_UART2_RX
],
3979 serial_hd(0) ? serial_hd(1) : NULL
);
3980 s
->uart
[2] = omap_uart_init(0xfffb9800,
3981 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_UART3
),
3982 omap_findclk(s
, "uart3_ck"),
3983 omap_findclk(s
, "uart3_ck"),
3984 s
->drq
[OMAP_DMA_UART3_TX
], s
->drq
[OMAP_DMA_UART3_RX
],
3986 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL
);
3988 s
->dpll
[0] = omap_dpll_init(system_memory
, 0xfffecf00,
3989 omap_findclk(s
, "dpll1"));
3990 s
->dpll
[1] = omap_dpll_init(system_memory
, 0xfffed000,
3991 omap_findclk(s
, "dpll2"));
3992 s
->dpll
[2] = omap_dpll_init(system_memory
, 0xfffed100,
3993 omap_findclk(s
, "dpll3"));
3995 dinfo
= drive_get(IF_SD
, 0, 0);
3996 if (!dinfo
&& !qtest_enabled()) {
3997 warn_report("missing SecureDigital device");
3999 s
->mmc
= omap_mmc_init(0xfffb7800, system_memory
,
4000 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
4001 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_OQN
),
4002 &s
->drq
[OMAP_DMA_MMC_TX
],
4003 omap_findclk(s
, "mmc_ck"));
4005 s
->mpuio
= omap_mpuio_init(system_memory
, 0xfffb5000,
4006 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_KEYBOARD
),
4007 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_MPUIO
),
4008 s
->wakeup
, omap_findclk(s
, "clk32-kHz"));
4010 s
->gpio
= qdev_create(NULL
, "omap-gpio");
4011 qdev_prop_set_int32(s
->gpio
, "mpu_model", s
->mpu_model
);
4012 qdev_prop_set_ptr(s
->gpio
, "clk", omap_findclk(s
, "arm_gpio_ck"));
4013 qdev_init_nofail(s
->gpio
);
4014 sysbus_connect_irq(SYS_BUS_DEVICE(s
->gpio
), 0,
4015 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_GPIO_BANK1
));
4016 sysbus_mmio_map(SYS_BUS_DEVICE(s
->gpio
), 0, 0xfffce000);
4018 s
->microwire
= omap_uwire_init(system_memory
, 0xfffb3000,
4019 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_uWireTX
),
4020 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_uWireRX
),
4021 s
->drq
[OMAP_DMA_UWIRE_TX
], omap_findclk(s
, "mpuper_ck"));
4023 s
->pwl
= omap_pwl_init(system_memory
, 0xfffb5800,
4024 omap_findclk(s
, "armxor_ck"));
4025 s
->pwt
= omap_pwt_init(system_memory
, 0xfffb6000,
4026 omap_findclk(s
, "armxor_ck"));
4028 s
->i2c
[0] = qdev_create(NULL
, "omap_i2c");
4029 qdev_prop_set_uint8(s
->i2c
[0], "revision", 0x11);
4030 qdev_prop_set_ptr(s
->i2c
[0], "fclk", omap_findclk(s
, "mpuper_ck"));
4031 qdev_init_nofail(s
->i2c
[0]);
4032 busdev
= SYS_BUS_DEVICE(s
->i2c
[0]);
4033 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(s
->ih
[1], OMAP_INT_I2C
));
4034 sysbus_connect_irq(busdev
, 1, s
->drq
[OMAP_DMA_I2C_TX
]);
4035 sysbus_connect_irq(busdev
, 2, s
->drq
[OMAP_DMA_I2C_RX
]);
4036 sysbus_mmio_map(busdev
, 0, 0xfffb3800);
4038 s
->rtc
= omap_rtc_init(system_memory
, 0xfffb4800,
4039 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_RTC_TIMER
),
4040 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_RTC_ALARM
),
4041 omap_findclk(s
, "clk32-kHz"));
4043 s
->mcbsp1
= omap_mcbsp_init(system_memory
, 0xfffb1800,
4044 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP1TX
),
4045 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP1RX
),
4046 &s
->drq
[OMAP_DMA_MCBSP1_TX
], omap_findclk(s
, "dspxor_ck"));
4047 s
->mcbsp2
= omap_mcbsp_init(system_memory
, 0xfffb1000,
4048 qdev_get_gpio_in(s
->ih
[0],
4049 OMAP_INT_310_McBSP2_TX
),
4050 qdev_get_gpio_in(s
->ih
[0],
4051 OMAP_INT_310_McBSP2_RX
),
4052 &s
->drq
[OMAP_DMA_MCBSP2_TX
], omap_findclk(s
, "mpuper_ck"));
4053 s
->mcbsp3
= omap_mcbsp_init(system_memory
, 0xfffb7000,
4054 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP3TX
),
4055 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP3RX
),
4056 &s
->drq
[OMAP_DMA_MCBSP3_TX
], omap_findclk(s
, "dspxor_ck"));
4058 s
->led
[0] = omap_lpg_init(system_memory
,
4059 0xfffbd000, omap_findclk(s
, "clk32-kHz"));
4060 s
->led
[1] = omap_lpg_init(system_memory
,
4061 0xfffbd800, omap_findclk(s
, "clk32-kHz"));
4063 /* Register mappings not currenlty implemented:
4064 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4065 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4066 * USB W2FC fffb4000 - fffb47ff
4067 * Camera Interface fffb6800 - fffb6fff
4068 * USB Host fffba000 - fffba7ff
4069 * FAC fffba800 - fffbafff
4070 * HDQ/1-Wire fffbc000 - fffbc7ff
4071 * TIPB switches fffbc800 - fffbcfff
4072 * Mailbox fffcf000 - fffcf7ff
4073 * Local bus IF fffec100 - fffec1ff
4074 * Local bus MMU fffec200 - fffec2ff
4075 * DSP MMU fffed200 - fffed2ff
4078 omap_setup_dsp_mapping(system_memory
, omap15xx_dsp_mm
);
4079 omap_setup_mpui_io(system_memory
, s
);
4081 qemu_register_reset(omap1_mpu_reset
, s
);