2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/datadir.h"
34 #include "qemu/units.h"
35 #include "qemu/option.h"
36 #include "monitor/qdev.h"
37 #include "qapi/error.h"
38 #include "hw/sysbus.h"
39 #include "hw/arm/boot.h"
40 #include "hw/arm/primecell.h"
41 #include "hw/arm/virt.h"
42 #include "hw/block/flash.h"
43 #include "hw/vfio/vfio-calxeda-xgmac.h"
44 #include "hw/vfio/vfio-amd-xgbe.h"
45 #include "hw/display/ramfb.h"
47 #include "sysemu/device_tree.h"
48 #include "sysemu/numa.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/tpm.h"
51 #include "sysemu/kvm.h"
52 #include "hw/loader.h"
53 #include "qemu/bitops.h"
54 #include "qemu/error-report.h"
55 #include "qemu/module.h"
56 #include "hw/pci-host/gpex.h"
57 #include "hw/virtio/virtio-pci.h"
58 #include "hw/arm/sysbus-fdt.h"
59 #include "hw/platform-bus.h"
60 #include "hw/qdev-properties.h"
61 #include "hw/arm/fdt.h"
62 #include "hw/intc/arm_gic.h"
63 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/firmware/smbios.h"
67 #include "qapi/visitor.h"
68 #include "qapi/qapi-visit-common.h"
69 #include "standard-headers/linux/input.h"
70 #include "hw/arm/smmuv3.h"
71 #include "hw/acpi/acpi.h"
72 #include "target/arm/internals.h"
73 #include "hw/mem/pc-dimm.h"
74 #include "hw/mem/nvdimm.h"
75 #include "hw/acpi/generic_event_device.h"
76 #include "hw/virtio/virtio-iommu.h"
77 #include "hw/char/pl011.h"
78 #include "qemu/guest-random.h"
80 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
81 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
84 MachineClass *mc = MACHINE_CLASS(oc); \
85 virt_machine_##major##_##minor##_options(mc); \
86 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
91 static const TypeInfo machvirt_##major##_##minor##_info = { \
92 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
93 .parent = TYPE_VIRT_MACHINE, \
94 .class_init = virt_##major##_##minor##_class_init, \
96 static void machvirt_machine_##major##_##minor##_init(void) \
98 type_register_static(&machvirt_##major##_##minor##_info); \
100 type_init(machvirt_machine_##major##_##minor##_init);
102 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
103 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
104 #define DEFINE_VIRT_MACHINE(major, minor) \
105 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
108 /* Number of external interrupt lines to configure the GIC with */
111 #define PLATFORM_BUS_NUM_IRQS 64
113 /* Legacy RAM limit in GB (< version 4.0) */
114 #define LEGACY_RAMLIMIT_GB 255
115 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
117 /* Addresses and sizes of our components.
118 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
119 * 128MB..256MB is used for miscellaneous device I/O.
120 * 256MB..1GB is reserved for possible future PCI support (ie where the
121 * PCI memory window will go if we add a PCI host controller).
122 * 1GB and up is RAM (which may happily spill over into the
123 * high memory region beyond 4GB).
124 * This represents a compromise between how much RAM can be given to
125 * a 32 bit VM and leaving space for expansion and in particular for PCI.
126 * Note that devices should generally be placed at multiples of 0x10000,
127 * to accommodate guests using 64K pages.
129 static const MemMapEntry base_memmap
[] = {
130 /* Space up to 0x8000000 is reserved for a boot ROM */
131 [VIRT_FLASH
] = { 0, 0x08000000 },
132 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
133 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
134 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
135 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
136 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
137 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
138 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
139 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
140 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
141 /* This redistributor space allows up to 2*64kB*123 CPUs */
142 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
143 [VIRT_UART
] = { 0x09000000, 0x00001000 },
144 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
145 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
146 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
147 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
148 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
149 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
150 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
151 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
152 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
153 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
154 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
155 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
156 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
157 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
158 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
159 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
160 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
161 /* Actual RAM size depends on initial RAM and device memory settings */
162 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
166 * Highmem IO Regions: This memory map is floating, located after the RAM.
167 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
168 * top of the RAM, so that its base get the same alignment as the size,
169 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
170 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
171 * Note the extended_memmap is sized so that it eventually also includes the
172 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
173 * index of base_memmap).
175 static MemMapEntry extended_memmap
[] = {
176 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
177 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
178 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
179 /* Second PCIe window */
180 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
183 static const int a15irqmap
[] = {
186 [VIRT_PCIE
] = 3, /* ... to 6 */
188 [VIRT_SECURE_UART
] = 8,
190 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
191 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
192 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
193 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
196 static const char *valid_cpus
[] = {
197 ARM_CPU_TYPE_NAME("cortex-a7"),
198 ARM_CPU_TYPE_NAME("cortex-a15"),
199 ARM_CPU_TYPE_NAME("cortex-a53"),
200 ARM_CPU_TYPE_NAME("cortex-a57"),
201 ARM_CPU_TYPE_NAME("cortex-a72"),
202 ARM_CPU_TYPE_NAME("host"),
203 ARM_CPU_TYPE_NAME("max"),
206 static bool cpu_type_valid(const char *cpu
)
210 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
211 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
218 static void create_kaslr_seed(MachineState
*ms
, const char *node
)
222 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
225 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
);
228 static void create_fdt(VirtMachineState
*vms
)
230 MachineState
*ms
= MACHINE(vms
);
231 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
232 void *fdt
= create_device_tree(&vms
->fdt_size
);
235 error_report("create_device_tree() failed");
242 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
243 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
244 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
246 /* /chosen must exist for load_dtb to fill in necessary properties later */
247 qemu_fdt_add_subnode(fdt
, "/chosen");
248 create_kaslr_seed(ms
, "/chosen");
251 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
252 create_kaslr_seed(ms
, "/secure-chosen");
255 /* Clock node, for the benefit of the UART. The kernel device tree
256 * binding documentation claims the PL011 node clock properties are
257 * optional but in practice if you omit them the kernel refuses to
258 * probe for the device.
260 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
261 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
262 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
263 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
264 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
265 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
267 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
269 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
270 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
271 uint32_t *matrix
= g_malloc0(size
);
274 for (i
= 0; i
< nb_numa_nodes
; i
++) {
275 for (j
= 0; j
< nb_numa_nodes
; j
++) {
276 idx
= (i
* nb_numa_nodes
+ j
) * 3;
277 matrix
[idx
+ 0] = cpu_to_be32(i
);
278 matrix
[idx
+ 1] = cpu_to_be32(j
);
280 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
284 qemu_fdt_add_subnode(fdt
, "/distance-map");
285 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
286 "numa-distance-map-v1");
287 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
293 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
295 /* On real hardware these interrupts are level-triggered.
296 * On KVM they were edge-triggered before host kernel version 4.4,
297 * and level-triggered afterwards.
298 * On emulated QEMU they are level-triggered.
300 * Getting the DTB info about them wrong is awkward for some
302 * pre-4.8 ignore the DT and leave the interrupt configured
303 * with whatever the GIC reset value (or the bootloader) left it at
304 * 4.8 before rc6 honour the incorrect data by programming it back
305 * into the GIC, causing problems
306 * 4.8rc6 and later ignore the DT and always write "level triggered"
309 * For backwards-compatibility, virt-2.8 and earlier will continue
310 * to say these are edge-triggered, but later machines will report
311 * the correct information.
314 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
315 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
316 MachineState
*ms
= MACHINE(vms
);
318 if (vmc
->claim_edge_triggered_timers
) {
319 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
322 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
323 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
324 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
325 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
328 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
330 armcpu
= ARM_CPU(qemu_get_cpu(0));
331 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
332 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
333 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
334 compat
, sizeof(compat
));
336 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
339 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
340 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
341 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
342 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
343 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
344 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
347 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
351 const MachineState
*ms
= MACHINE(vms
);
352 int smp_cpus
= ms
->smp
.cpus
;
355 * From Documentation/devicetree/bindings/arm/cpus.txt
356 * On ARM v8 64-bit systems value should be set to 2,
357 * that corresponds to the MPIDR_EL1 register size.
358 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
359 * in the system, #address-cells can be set to 1, since
360 * MPIDR_EL1[63:32] bits are not used for CPUs
363 * Here we actually don't know whether our system is 32- or 64-bit one.
364 * The simplest way to go is to examine affinity IDs of all our CPUs. If
365 * at least one of them has Aff3 populated, we set #address-cells to 2.
367 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
368 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
370 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
376 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
377 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
378 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
380 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
381 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
382 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
383 CPUState
*cs
= CPU(armcpu
);
385 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
386 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
387 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
388 armcpu
->dtb_compatible
);
390 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
391 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
392 "enable-method", "psci");
395 if (addr_cells
== 2) {
396 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
397 armcpu
->mp_affinity
);
399 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
400 armcpu
->mp_affinity
);
403 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
404 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
405 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
412 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
415 MachineState
*ms
= MACHINE(vms
);
417 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
418 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
419 vms
->memmap
[VIRT_GIC_ITS
].base
);
420 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
421 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
423 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
424 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
425 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
426 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
427 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
431 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
433 MachineState
*ms
= MACHINE(vms
);
436 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
437 vms
->memmap
[VIRT_GIC_V2M
].base
);
438 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
439 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
440 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
441 "arm,gic-v2m-frame");
442 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
443 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
444 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
445 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
446 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
450 static void fdt_add_gic_node(VirtMachineState
*vms
)
452 MachineState
*ms
= MACHINE(vms
);
455 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
456 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
458 nodename
= g_strdup_printf("/intc@%" PRIx64
,
459 vms
->memmap
[VIRT_GIC_DIST
].base
);
460 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
461 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
462 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
463 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
464 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
465 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
466 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
467 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
469 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
472 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
473 "#redistributor-regions", nb_redist_regions
);
475 if (nb_redist_regions
== 1) {
476 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
477 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
478 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
479 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
480 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
482 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
483 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
484 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
485 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
486 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
487 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
488 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
492 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
493 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
494 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
497 /* 'cortex-a15-gic' means 'GIC v2' */
498 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
499 "arm,cortex-a15-gic");
501 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
502 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
503 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
504 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
505 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
507 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
508 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
509 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
510 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
511 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
512 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
513 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
514 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
515 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
516 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
517 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
518 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
522 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
526 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
528 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
529 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
530 MachineState
*ms
= MACHINE(vms
);
532 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
533 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
537 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
538 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
539 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
540 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
543 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
544 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
545 const char compat
[] = "arm,armv8-pmuv3";
546 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
547 compat
, sizeof(compat
));
548 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
549 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
553 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
556 MachineState
*ms
= MACHINE(vms
);
557 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
558 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
561 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
564 if (ms
->nvdimms_state
->is_enabled
) {
565 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
568 dev
= qdev_new(TYPE_ACPI_GED
);
569 qdev_prop_set_uint32(dev
, "ged-event", event
);
571 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
572 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
573 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
575 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
580 static void create_its(VirtMachineState
*vms
)
582 const char *itsclass
= its_class_name();
586 /* Do nothing if not supported */
590 dev
= qdev_new(itsclass
);
592 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
594 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
595 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
597 fdt_add_its_gic_node(vms
);
598 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
601 static void create_v2m(VirtMachineState
*vms
)
604 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
607 dev
= qdev_new("arm-gicv2m");
608 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
609 qdev_prop_set_uint32(dev
, "base-spi", irq
);
610 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
611 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
613 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
614 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
615 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
618 fdt_add_v2m_gic_node(vms
);
619 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
622 static void create_gic(VirtMachineState
*vms
)
624 MachineState
*ms
= MACHINE(vms
);
625 /* We create a standalone GIC */
626 SysBusDevice
*gicbusdev
;
628 int type
= vms
->gic_version
, i
;
629 unsigned int smp_cpus
= ms
->smp
.cpus
;
630 uint32_t nb_redist_regions
= 0;
632 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
634 vms
->gic
= qdev_new(gictype
);
635 qdev_prop_set_uint32(vms
->gic
, "revision", type
);
636 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
637 /* Note that the num-irq property counts both internal and external
638 * interrupts; there are always 32 of the former (mandated by GIC spec).
640 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
641 if (!kvm_irqchip_in_kernel()) {
642 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
646 uint32_t redist0_capacity
=
647 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
648 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
650 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
652 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
654 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
656 if (nb_redist_regions
== 2) {
657 uint32_t redist1_capacity
=
658 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
660 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
661 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
664 if (!kvm_irqchip_in_kernel()) {
665 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
669 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
670 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
671 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
673 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
674 if (nb_redist_regions
== 2) {
675 sysbus_mmio_map(gicbusdev
, 2,
676 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
679 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
681 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
682 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
686 /* Wire the outputs from each CPU's generic timer and the GICv3
687 * maintenance interrupt signal to the appropriate GIC PPI inputs,
688 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
690 for (i
= 0; i
< smp_cpus
; i
++) {
691 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
692 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
694 /* Mapping from the output timer irq lines from the CPU to the
695 * GIC PPI inputs we use for the virt board.
697 const int timer_irq
[] = {
698 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
699 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
700 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
701 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
704 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
705 qdev_connect_gpio_out(cpudev
, irq
,
706 qdev_get_gpio_in(vms
->gic
,
707 ppibase
+ timer_irq
[irq
]));
711 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
712 ppibase
+ ARCH_GIC_MAINT_IRQ
);
713 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
715 } else if (vms
->virt
) {
716 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
717 ppibase
+ ARCH_GIC_MAINT_IRQ
);
718 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
721 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
722 qdev_get_gpio_in(vms
->gic
, ppibase
725 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
726 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
727 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
728 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
729 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
730 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
731 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
734 fdt_add_gic_node(vms
);
736 if (type
== 3 && vms
->its
) {
738 } else if (type
== 2) {
743 static void create_uart(const VirtMachineState
*vms
, int uart
,
744 MemoryRegion
*mem
, Chardev
*chr
)
747 hwaddr base
= vms
->memmap
[uart
].base
;
748 hwaddr size
= vms
->memmap
[uart
].size
;
749 int irq
= vms
->irqmap
[uart
];
750 const char compat
[] = "arm,pl011\0arm,primecell";
751 const char clocknames
[] = "uartclk\0apb_pclk";
752 DeviceState
*dev
= qdev_new(TYPE_PL011
);
753 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
754 MachineState
*ms
= MACHINE(vms
);
756 qdev_prop_set_chr(dev
, "chardev", chr
);
757 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
758 memory_region_add_subregion(mem
, base
,
759 sysbus_mmio_get_region(s
, 0));
760 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
762 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
763 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
764 /* Note that we can't use setprop_string because of the embedded NUL */
765 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
766 compat
, sizeof(compat
));
767 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
769 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
770 GIC_FDT_IRQ_TYPE_SPI
, irq
,
771 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
772 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
773 vms
->clock_phandle
, vms
->clock_phandle
);
774 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
775 clocknames
, sizeof(clocknames
));
777 if (uart
== VIRT_UART
) {
778 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
780 /* Mark as not usable by the normal world */
781 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
782 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
784 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
791 static void create_rtc(const VirtMachineState
*vms
)
794 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
795 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
796 int irq
= vms
->irqmap
[VIRT_RTC
];
797 const char compat
[] = "arm,pl031\0arm,primecell";
798 MachineState
*ms
= MACHINE(vms
);
800 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
802 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
803 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
804 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
805 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
807 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
808 GIC_FDT_IRQ_TYPE_SPI
, irq
,
809 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
810 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
811 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
815 static DeviceState
*gpio_key_dev
;
816 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
818 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
821 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
823 /* use gpio Pin 3 for power button event */
824 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
828 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
831 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
832 qdev_get_gpio_in(pl061_dev
, 3));
834 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
835 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
836 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#size-cells", 0);
837 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#address-cells", 1);
839 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
840 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
841 "label", "GPIO Key Poweroff");
842 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
844 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
845 "gpios", phandle
, 3, 0);
848 #define SECURE_GPIO_POWEROFF 0
849 #define SECURE_GPIO_RESET 1
851 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
854 DeviceState
*gpio_pwr_dev
;
857 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
859 /* connect secure pl061 to gpio-pwr */
860 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
861 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
862 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
863 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
865 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
866 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
868 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
869 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
870 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
871 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
874 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
875 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
877 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
878 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
879 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
880 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
884 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
888 DeviceState
*pl061_dev
;
889 hwaddr base
= vms
->memmap
[gpio
].base
;
890 hwaddr size
= vms
->memmap
[gpio
].size
;
891 int irq
= vms
->irqmap
[gpio
];
892 const char compat
[] = "arm,pl061\0arm,primecell";
894 MachineState
*ms
= MACHINE(vms
);
896 pl061_dev
= qdev_new("pl061");
897 s
= SYS_BUS_DEVICE(pl061_dev
);
898 sysbus_realize_and_unref(s
, &error_fatal
);
899 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
900 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
902 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
903 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
904 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
905 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
907 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
908 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
909 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
910 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
911 GIC_FDT_IRQ_TYPE_SPI
, irq
,
912 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
913 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
914 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
915 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
917 if (gpio
!= VIRT_GPIO
) {
918 /* Mark as not usable by the normal world */
919 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
920 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
924 /* Child gpio devices */
925 if (gpio
== VIRT_GPIO
) {
926 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
928 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
932 static void create_virtio_devices(const VirtMachineState
*vms
)
935 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
936 MachineState
*ms
= MACHINE(vms
);
938 /* We create the transports in forwards order. Since qbus_realize()
939 * prepends (not appends) new child buses, the incrementing loop below will
940 * create a list of virtio-mmio buses with decreasing base addresses.
942 * When a -device option is processed from the command line,
943 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
944 * order. The upshot is that -device options in increasing command line
945 * order are mapped to virtio-mmio buses with decreasing base addresses.
947 * When this code was originally written, that arrangement ensured that the
948 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
949 * the first -device on the command line. (The end-to-end order is a
950 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
951 * guest kernel's name-to-address assignment strategy.)
953 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
954 * the message, if not necessarily the code, of commit 70161ff336.
955 * Therefore the loop now establishes the inverse of the original intent.
957 * Unfortunately, we can't counteract the kernel change by reversing the
958 * loop; it would break existing command lines.
960 * In any case, the kernel makes no guarantee about the stability of
961 * enumeration order of virtio devices (as demonstrated by it changing
962 * between kernel versions). For reliable and stable identification
963 * of disks users must use UUIDs or similar mechanisms.
965 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
966 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
967 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
969 sysbus_create_simple("virtio-mmio", base
,
970 qdev_get_gpio_in(vms
->gic
, irq
));
973 /* We add dtb nodes in reverse order so that they appear in the finished
974 * device tree lowest address first.
976 * Note that this mapping is independent of the loop above. The previous
977 * loop influences virtio device to virtio transport assignment, whereas
978 * this loop controls how virtio transports are laid out in the dtb.
980 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
982 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
983 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
985 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
986 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
987 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
988 "compatible", "virtio,mmio");
989 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
991 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
992 GIC_FDT_IRQ_TYPE_SPI
, irq
,
993 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
994 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
999 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1001 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1003 const char *alias_prop_name
)
1006 * Create a single flash device. We use the same parameters as
1007 * the flash devices on the Versatile Express board.
1009 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1011 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1012 qdev_prop_set_uint8(dev
, "width", 4);
1013 qdev_prop_set_uint8(dev
, "device-width", 2);
1014 qdev_prop_set_bit(dev
, "big-endian", false);
1015 qdev_prop_set_uint16(dev
, "id0", 0x89);
1016 qdev_prop_set_uint16(dev
, "id1", 0x18);
1017 qdev_prop_set_uint16(dev
, "id2", 0x00);
1018 qdev_prop_set_uint16(dev
, "id3", 0x00);
1019 qdev_prop_set_string(dev
, "name", name
);
1020 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1021 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1022 OBJECT(dev
), "drive");
1023 return PFLASH_CFI01(dev
);
1026 static void virt_flash_create(VirtMachineState
*vms
)
1028 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1029 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1032 static void virt_flash_map1(PFlashCFI01
*flash
,
1033 hwaddr base
, hwaddr size
,
1034 MemoryRegion
*sysmem
)
1036 DeviceState
*dev
= DEVICE(flash
);
1038 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1039 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1040 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1041 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1043 memory_region_add_subregion(sysmem
, base
,
1044 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1048 static void virt_flash_map(VirtMachineState
*vms
,
1049 MemoryRegion
*sysmem
,
1050 MemoryRegion
*secure_sysmem
)
1053 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1054 * sysmem is the system memory space. secure_sysmem is the secure view
1055 * of the system, and the first flash device should be made visible only
1056 * there. The second flash device is visible to both secure and nonsecure.
1057 * If sysmem == secure_sysmem this means there is no separate Secure
1058 * address space and both flash devices are generally visible.
1060 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1061 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1063 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1065 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1069 static void virt_flash_fdt(VirtMachineState
*vms
,
1070 MemoryRegion
*sysmem
,
1071 MemoryRegion
*secure_sysmem
)
1073 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1074 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1075 MachineState
*ms
= MACHINE(vms
);
1078 if (sysmem
== secure_sysmem
) {
1079 /* Report both flash devices as a single node in the DT */
1080 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1081 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1082 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1083 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1084 2, flashbase
, 2, flashsize
,
1085 2, flashbase
+ flashsize
, 2, flashsize
);
1086 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1090 * Report the devices as separate nodes so we can mark one as
1091 * only visible to the secure world.
1093 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1094 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1095 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1096 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1097 2, flashbase
, 2, flashsize
);
1098 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1099 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1100 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1103 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1104 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1105 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1106 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1107 2, flashbase
+ flashsize
, 2, flashsize
);
1108 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1113 static bool virt_firmware_init(VirtMachineState
*vms
,
1114 MemoryRegion
*sysmem
,
1115 MemoryRegion
*secure_sysmem
)
1118 const char *bios_name
;
1119 BlockBackend
*pflash_blk0
;
1121 /* Map legacy -drive if=pflash to machine properties */
1122 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1123 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1124 drive_get(IF_PFLASH
, 0, i
));
1127 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1129 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1131 bios_name
= MACHINE(vms
)->firmware
;
1138 error_report("The contents of the first flash device may be "
1139 "specified with -bios or with -drive if=pflash... "
1140 "but you cannot use both options at once");
1144 /* Fall back to -bios */
1146 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1148 error_report("Could not find ROM image '%s'", bios_name
);
1151 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1152 image_size
= load_image_mr(fname
, mr
);
1154 if (image_size
< 0) {
1155 error_report("Could not load ROM image '%s'", bios_name
);
1160 return pflash_blk0
|| bios_name
;
1163 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1165 MachineState
*ms
= MACHINE(vms
);
1166 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1167 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1171 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1172 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1174 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1175 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1176 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1177 "compatible", "qemu,fw-cfg-mmio");
1178 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1180 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1185 static void create_pcie_irq_map(const MachineState
*ms
,
1186 uint32_t gic_phandle
,
1187 int first_irq
, const char *nodename
)
1190 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1191 uint32_t *irq_map
= full_irq_map
;
1193 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1194 for (pin
= 0; pin
< 4; pin
++) {
1195 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1196 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1197 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1201 devfn
<< 8, 0, 0, /* devfn */
1202 pin
+ 1, /* PCI pin */
1203 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1205 /* Convert map to big endian */
1206 for (i
= 0; i
< 10; i
++) {
1207 irq_map
[i
] = cpu_to_be32(map
[i
]);
1213 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1214 full_irq_map
, sizeof(full_irq_map
));
1216 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1217 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1222 static void create_smmu(const VirtMachineState
*vms
,
1226 const char compat
[] = "arm,smmu-v3";
1227 int irq
= vms
->irqmap
[VIRT_SMMU
];
1229 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1230 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1231 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1233 MachineState
*ms
= MACHINE(vms
);
1235 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1239 dev
= qdev_new("arm-smmuv3");
1241 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1243 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1244 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1245 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1246 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1247 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1250 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1251 qemu_fdt_add_subnode(ms
->fdt
, node
);
1252 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1253 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1255 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1256 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1257 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1258 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1259 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1261 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1264 qemu_fdt_setprop_cell(ms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1265 qemu_fdt_setprop_string(ms
->fdt
, node
, "clock-names", "apb_pclk");
1266 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1268 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1270 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1274 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1276 const char compat
[] = "virtio,pci-iommu";
1277 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1278 MachineState
*ms
= MACHINE(vms
);
1281 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1283 node
= g_strdup_printf("%s/virtio_iommu@%d", vms
->pciehb_nodename
, bdf
);
1284 qemu_fdt_add_subnode(ms
->fdt
, node
);
1285 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1286 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1287 1, bdf
<< 8, 1, 0, 1, 0,
1290 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1291 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1294 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1295 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1296 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1299 static void create_pcie(VirtMachineState
*vms
)
1301 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1302 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1303 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1304 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1305 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1306 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1307 hwaddr base_ecam
, size_ecam
;
1308 hwaddr base
= base_mmio
;
1310 int irq
= vms
->irqmap
[VIRT_PCIE
];
1311 MemoryRegion
*mmio_alias
;
1312 MemoryRegion
*mmio_reg
;
1313 MemoryRegion
*ecam_alias
;
1314 MemoryRegion
*ecam_reg
;
1319 MachineState
*ms
= MACHINE(vms
);
1321 dev
= qdev_new(TYPE_GPEX_HOST
);
1322 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1324 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1325 base_ecam
= vms
->memmap
[ecam_id
].base
;
1326 size_ecam
= vms
->memmap
[ecam_id
].size
;
1327 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1328 /* Map only the first size_ecam bytes of ECAM space */
1329 ecam_alias
= g_new0(MemoryRegion
, 1);
1330 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1331 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1332 ecam_reg
, 0, size_ecam
);
1333 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1335 /* Map the MMIO window into system address space so as to expose
1336 * the section of PCI MMIO space which starts at the same base address
1337 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1340 mmio_alias
= g_new0(MemoryRegion
, 1);
1341 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1342 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1343 mmio_reg
, base_mmio
, size_mmio
);
1344 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1347 /* Map high MMIO space */
1348 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1350 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1351 mmio_reg
, base_mmio_high
, size_mmio_high
);
1352 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1356 /* Map IO port space */
1357 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1359 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1360 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1361 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1362 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1365 pci
= PCI_HOST_BRIDGE(dev
);
1366 vms
->bus
= pci
->bus
;
1368 for (i
= 0; i
< nb_nics
; i
++) {
1369 NICInfo
*nd
= &nd_table
[i
];
1372 nd
->model
= g_strdup("virtio");
1375 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1379 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1380 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1381 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1382 "compatible", "pci-host-ecam-generic");
1383 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1384 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1385 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1386 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1387 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1389 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1391 if (vms
->msi_phandle
) {
1392 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-parent",
1396 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1397 2, base_ecam
, 2, size_ecam
);
1400 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1401 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1402 2, base_pio
, 2, size_pio
,
1403 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1404 2, base_mmio
, 2, size_mmio
,
1405 1, FDT_PCI_RANGE_MMIO_64BIT
,
1407 2, base_mmio_high
, 2, size_mmio_high
);
1409 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1410 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1411 2, base_pio
, 2, size_pio
,
1412 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1413 2, base_mmio
, 2, size_mmio
);
1416 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1417 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1420 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1422 switch (vms
->iommu
) {
1423 case VIRT_IOMMU_SMMUV3
:
1424 create_smmu(vms
, vms
->bus
);
1425 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1426 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1429 g_assert_not_reached();
1434 static void create_platform_bus(VirtMachineState
*vms
)
1439 MemoryRegion
*sysmem
= get_system_memory();
1441 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1442 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1443 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1444 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1445 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1446 vms
->platform_bus_dev
= dev
;
1448 s
= SYS_BUS_DEVICE(dev
);
1449 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1450 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1451 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1454 memory_region_add_subregion(sysmem
,
1455 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1456 sysbus_mmio_get_region(s
, 0));
1459 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1460 hwaddr base
, hwaddr size
,
1463 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1465 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1466 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1469 static void create_secure_ram(VirtMachineState
*vms
,
1470 MemoryRegion
*secure_sysmem
,
1471 MemoryRegion
*secure_tag_sysmem
)
1473 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1475 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1476 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1477 MachineState
*ms
= MACHINE(vms
);
1479 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1481 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1483 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1484 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1485 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1486 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1487 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1488 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1490 if (secure_tag_sysmem
) {
1491 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1497 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1499 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1501 MachineState
*ms
= MACHINE(board
);
1504 *fdt_size
= board
->fdt_size
;
1508 static void virt_build_smbios(VirtMachineState
*vms
)
1510 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1511 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1512 uint8_t *smbios_tables
, *smbios_anchor
;
1513 size_t smbios_tables_len
, smbios_anchor_len
;
1514 const char *product
= "QEMU Virtual Machine";
1516 if (kvm_enabled()) {
1517 product
= "KVM Virtual Machine";
1520 smbios_set_defaults("QEMU", product
,
1521 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1522 true, SMBIOS_ENTRY_POINT_30
);
1524 smbios_get_tables(MACHINE(vms
), NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1525 &smbios_anchor
, &smbios_anchor_len
);
1527 if (smbios_anchor
) {
1528 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1529 smbios_tables
, smbios_tables_len
);
1530 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1531 smbios_anchor
, smbios_anchor_len
);
1536 void virt_machine_done(Notifier
*notifier
, void *data
)
1538 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1540 MachineState
*ms
= MACHINE(vms
);
1541 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1542 struct arm_boot_info
*info
= &vms
->bootinfo
;
1543 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1546 * If the user provided a dtb, we assume the dynamic sysbus nodes
1547 * already are integrated there. This corresponds to a use case where
1548 * the dynamic sysbus nodes are complex and their generation is not yet
1549 * supported. In that case the user can take charge of the guest dt
1550 * while qemu takes charge of the qom stuff.
1552 if (info
->dtb_filename
== NULL
) {
1553 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1554 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1555 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1556 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1558 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1562 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1564 virt_acpi_setup(vms
);
1565 virt_build_smbios(vms
);
1568 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1570 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1571 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1573 if (!vmc
->disallow_affinity_adjustment
) {
1574 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1575 * GIC's target-list limitations. 32-bit KVM hosts currently
1576 * always create clusters of 4 CPUs, but that is expected to
1577 * change when they gain support for gicv3. When KVM is enabled
1578 * it will override the changes we make here, therefore our
1579 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1580 * and to improve SGI efficiency.
1582 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1583 clustersz
= GICV3_TARGETLIST_BITS
;
1585 clustersz
= GIC_TARGETLIST_BITS
;
1588 return arm_cpu_mp_affinity(idx
, clustersz
);
1591 static void virt_set_memmap(VirtMachineState
*vms
)
1593 MachineState
*ms
= MACHINE(vms
);
1594 hwaddr base
, device_memory_base
, device_memory_size
;
1597 vms
->memmap
= extended_memmap
;
1599 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1600 vms
->memmap
[i
] = base_memmap
[i
];
1603 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1604 error_report("unsupported number of memory slots: %"PRIu64
,
1610 * We compute the base of the high IO region depending on the
1611 * amount of initial and device memory. The device memory start/size
1612 * is aligned on 1GiB. We never put the high IO region below 256GiB
1613 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1614 * The device region size assumes 1GiB page max alignment per slot.
1616 device_memory_base
=
1617 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1618 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1620 /* Base address of the high IO region */
1621 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1622 if (base
< device_memory_base
) {
1623 error_report("maxmem/slots too huge");
1626 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1627 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1630 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1631 hwaddr size
= extended_memmap
[i
].size
;
1633 base
= ROUND_UP(base
, size
);
1634 vms
->memmap
[i
].base
= base
;
1635 vms
->memmap
[i
].size
= size
;
1638 vms
->highest_gpa
= base
- 1;
1639 if (device_memory_size
> 0) {
1640 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1641 ms
->device_memory
->base
= device_memory_base
;
1642 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1643 "device-memory", device_memory_size
);
1648 * finalize_gic_version - Determines the final gic_version
1649 * according to the gic-version property
1651 * Default GIC type is v2
1653 static void finalize_gic_version(VirtMachineState
*vms
)
1655 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1657 if (kvm_enabled()) {
1660 if (!kvm_irqchip_in_kernel()) {
1661 switch (vms
->gic_version
) {
1662 case VIRT_GIC_VERSION_HOST
:
1664 "gic-version=host not relevant with kernel-irqchip=off "
1665 "as only userspace GICv2 is supported. Using v2 ...");
1667 case VIRT_GIC_VERSION_MAX
:
1668 case VIRT_GIC_VERSION_NOSEL
:
1669 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1671 case VIRT_GIC_VERSION_2
:
1673 case VIRT_GIC_VERSION_3
:
1675 "gic-version=3 is not supported with kernel-irqchip=off");
1680 probe_bitmap
= kvm_arm_vgic_probe();
1681 if (!probe_bitmap
) {
1682 error_report("Unable to determine GIC version supported by host");
1686 switch (vms
->gic_version
) {
1687 case VIRT_GIC_VERSION_HOST
:
1688 case VIRT_GIC_VERSION_MAX
:
1689 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1690 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1692 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1695 case VIRT_GIC_VERSION_NOSEL
:
1696 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1697 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1698 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1700 * in case the host does not support v2 in-kernel emulation or
1701 * the end-user requested more than 8 VCPUs we now default
1702 * to v3. In any case defaulting to v2 would be broken.
1704 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1705 } else if (max_cpus
> GIC_NCPU
) {
1706 error_report("host only supports in-kernel GICv2 emulation "
1707 "but more than 8 vcpus are requested");
1711 case VIRT_GIC_VERSION_2
:
1712 case VIRT_GIC_VERSION_3
:
1716 /* Check chosen version is effectively supported by the host */
1717 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1718 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1719 error_report("host does not support in-kernel GICv2 emulation");
1721 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1722 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1723 error_report("host does not support in-kernel GICv3 emulation");
1730 switch (vms
->gic_version
) {
1731 case VIRT_GIC_VERSION_NOSEL
:
1732 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1734 case VIRT_GIC_VERSION_MAX
:
1735 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1737 case VIRT_GIC_VERSION_HOST
:
1738 error_report("gic-version=host requires KVM");
1740 case VIRT_GIC_VERSION_2
:
1741 case VIRT_GIC_VERSION_3
:
1747 * virt_cpu_post_init() must be called after the CPUs have
1748 * been realized and the GIC has been created.
1750 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1752 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1753 bool aarch64
, pmu
, steal_time
;
1756 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1757 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1758 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1759 "kvm-steal-time", NULL
);
1761 if (kvm_enabled()) {
1762 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1763 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1766 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1767 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1769 /* The memory region size must be a multiple of host page size. */
1770 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1772 if (pvtime_size
> pvtime_reg_size
) {
1773 error_report("pvtime requires a %" HWADDR_PRId
1774 " byte memory region for %d CPUs,"
1775 " but only %" HWADDR_PRId
" has been reserved",
1776 pvtime_size
, max_cpus
, pvtime_reg_size
);
1780 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1781 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1786 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1787 if (kvm_irqchip_in_kernel()) {
1788 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1790 kvm_arm_pmu_init(cpu
);
1793 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1794 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1798 if (aarch64
&& vms
->highmem
) {
1799 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1800 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1802 if (pamax
< requested_pa_size
) {
1803 error_report("VCPU supports less PA bits (%d) than "
1804 "requested by the memory map (%d)",
1805 pamax
, requested_pa_size
);
1812 static void machvirt_init(MachineState
*machine
)
1814 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1815 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1816 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1817 const CPUArchIdList
*possible_cpus
;
1818 MemoryRegion
*sysmem
= get_system_memory();
1819 MemoryRegion
*secure_sysmem
= NULL
;
1820 MemoryRegion
*tag_sysmem
= NULL
;
1821 MemoryRegion
*secure_tag_sysmem
= NULL
;
1822 int n
, virt_max_cpus
;
1823 bool firmware_loaded
;
1824 bool aarch64
= true;
1825 bool has_ged
= !vmc
->no_ged
;
1826 unsigned int smp_cpus
= machine
->smp
.cpus
;
1827 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1830 * In accelerated mode, the memory map is computed earlier in kvm_type()
1831 * to create a VM with the right number of IPA bits.
1834 virt_set_memmap(vms
);
1837 /* We can probe only here because during property set
1838 * KVM is not available yet
1840 finalize_gic_version(vms
);
1842 if (!cpu_type_valid(machine
->cpu_type
)) {
1843 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1848 if (kvm_enabled()) {
1849 error_report("mach-virt: KVM does not support Security extensions");
1854 * The Secure view of the world is the same as the NonSecure,
1855 * but with a few extra devices. Create it as a container region
1856 * containing the system memory at low priority; any secure-only
1857 * devices go in at higher priority and take precedence.
1859 secure_sysmem
= g_new(MemoryRegion
, 1);
1860 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1862 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1865 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
1866 secure_sysmem
?: sysmem
);
1868 /* If we have an EL3 boot ROM then the assumption is that it will
1869 * implement PSCI itself, so disable QEMU's internal implementation
1870 * so it doesn't get in the way. Instead of starting secondary
1871 * CPUs in PSCI powerdown state we will start them all running and
1872 * let the boot ROM sort them out.
1873 * The usual case is that we do use QEMU's PSCI implementation;
1874 * if the guest has EL2 then we will use SMC as the conduit,
1875 * and otherwise we will use HVC (for backwards compatibility and
1876 * because if we're using KVM then we must use HVC).
1878 if (vms
->secure
&& firmware_loaded
) {
1879 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1880 } else if (vms
->virt
) {
1881 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1883 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1886 /* The maximum number of CPUs depends on the GIC version, or on how
1887 * many redistributors we can fit into the memory map.
1889 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1891 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1893 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1895 virt_max_cpus
= GIC_NCPU
;
1898 if (max_cpus
> virt_max_cpus
) {
1899 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1900 "supported by machine 'mach-virt' (%d)",
1901 max_cpus
, virt_max_cpus
);
1905 if (vms
->virt
&& kvm_enabled()) {
1906 error_report("mach-virt: KVM does not support providing "
1907 "Virtualization extensions to the guest CPU");
1911 if (vms
->mte
&& kvm_enabled()) {
1912 error_report("mach-virt: KVM does not support providing "
1913 "MTE to the guest CPU");
1919 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1920 assert(possible_cpus
->len
== max_cpus
);
1921 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1925 if (n
>= smp_cpus
) {
1929 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1930 object_property_set_int(cpuobj
, "mp-affinity",
1931 possible_cpus
->cpus
[n
].arch_id
, NULL
);
1936 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1939 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1942 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
1945 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
1946 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
1949 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1950 object_property_set_int(cpuobj
, "psci-conduit", vms
->psci_conduit
,
1953 /* Secondary CPUs start in PSCI powered-down state */
1955 object_property_set_bool(cpuobj
, "start-powered-off", true,
1960 if (vmc
->kvm_no_adjvtime
&&
1961 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
1962 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
1965 if (vmc
->no_kvm_steal_time
&&
1966 object_property_find(cpuobj
, "kvm-steal-time")) {
1967 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
1970 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
1971 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
1974 if (object_property_find(cpuobj
, "reset-cbar")) {
1975 object_property_set_int(cpuobj
, "reset-cbar",
1976 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1980 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
1983 object_property_set_link(cpuobj
, "secure-memory",
1984 OBJECT(secure_sysmem
), &error_abort
);
1988 /* Create the memory region only once, but link to all cpus. */
1991 * The property exists only if MemTag is supported.
1992 * If it is, we must allocate the ram to back that up.
1994 if (!object_property_find(cpuobj
, "tag-memory")) {
1995 error_report("MTE requested, but not supported "
1996 "by the guest CPU");
2000 tag_sysmem
= g_new(MemoryRegion
, 1);
2001 memory_region_init(tag_sysmem
, OBJECT(machine
),
2002 "tag-memory", UINT64_MAX
/ 32);
2005 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2006 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2007 "secure-tag-memory", UINT64_MAX
/ 32);
2009 /* As with ram, secure-tag takes precedence over tag. */
2010 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2015 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2018 object_property_set_link(cpuobj
, "secure-tag-memory",
2019 OBJECT(secure_tag_sysmem
),
2024 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2025 object_unref(cpuobj
);
2027 fdt_add_timer_nodes(vms
);
2028 fdt_add_cpu_nodes(vms
);
2030 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2032 if (machine
->device_memory
) {
2033 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2034 &machine
->device_memory
->mr
);
2037 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2041 virt_cpu_post_init(vms
, sysmem
);
2043 fdt_add_pmu_nodes(vms
);
2045 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2048 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2049 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2053 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2054 machine
->ram_size
, "mach-virt.tag");
2057 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
2063 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2064 vms
->acpi_dev
= create_acpi_ged(vms
);
2066 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2069 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2070 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2073 /* connect powerdown request */
2074 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2075 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2077 /* Create mmio transports, so the user can create virtio backends
2078 * (which will be automatically plugged in to the transports). If
2079 * no backend is created the transport will just sit harmlessly idle.
2081 create_virtio_devices(vms
);
2083 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2084 rom_set_fw(vms
->fw_cfg
);
2086 create_platform_bus(vms
);
2088 if (machine
->nvdimms_state
->is_enabled
) {
2089 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2090 .space_id
= AML_AS_SYSTEM_MEMORY
,
2091 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2092 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2095 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2096 arm_virt_nvdimm_acpi_dsmio
,
2097 vms
->fw_cfg
, OBJECT(vms
));
2100 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2101 vms
->bootinfo
.nb_cpus
= smp_cpus
;
2102 vms
->bootinfo
.board_id
= -1;
2103 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2104 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2105 vms
->bootinfo
.skip_dtb_autoload
= true;
2106 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2107 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2109 vms
->machine_done
.notify
= virt_machine_done
;
2110 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2113 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2115 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2120 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2122 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2124 vms
->secure
= value
;
2127 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2129 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2134 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2136 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2141 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2143 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2145 return vms
->highmem
;
2148 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2150 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2152 vms
->highmem
= value
;
2155 static bool virt_get_its(Object
*obj
, Error
**errp
)
2157 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2162 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2164 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2169 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2171 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2173 return g_strdup(vms
->oem_id
);
2176 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2178 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2179 size_t len
= strlen(value
);
2183 "User specified oem-id value is bigger than 6 bytes in size");
2187 strncpy(vms
->oem_id
, value
, 6);
2190 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2192 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2194 return g_strdup(vms
->oem_table_id
);
2197 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2200 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2201 size_t len
= strlen(value
);
2205 "User specified oem-table-id value is bigger than 8 bytes in size");
2208 strncpy(vms
->oem_table_id
, value
, 8);
2212 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2214 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2220 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2221 void *opaque
, Error
**errp
)
2223 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2224 OnOffAuto acpi
= vms
->acpi
;
2226 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2229 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2230 void *opaque
, Error
**errp
)
2232 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2234 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2237 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2239 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2244 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2246 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2251 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2253 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2258 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2260 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2265 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2267 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2268 const char *val
= vms
->gic_version
== VIRT_GIC_VERSION_3
? "3" : "2";
2270 return g_strdup(val
);
2273 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2275 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2277 if (!strcmp(value
, "3")) {
2278 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2279 } else if (!strcmp(value
, "2")) {
2280 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2281 } else if (!strcmp(value
, "host")) {
2282 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2283 } else if (!strcmp(value
, "max")) {
2284 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2286 error_setg(errp
, "Invalid gic-version value");
2287 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2291 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2293 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2295 switch (vms
->iommu
) {
2296 case VIRT_IOMMU_NONE
:
2297 return g_strdup("none");
2298 case VIRT_IOMMU_SMMUV3
:
2299 return g_strdup("smmuv3");
2301 g_assert_not_reached();
2305 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2307 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2309 if (!strcmp(value
, "smmuv3")) {
2310 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2311 } else if (!strcmp(value
, "none")) {
2312 vms
->iommu
= VIRT_IOMMU_NONE
;
2314 error_setg(errp
, "Invalid iommu value");
2315 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2319 static CpuInstanceProperties
2320 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2322 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2323 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2325 assert(cpu_index
< possible_cpus
->len
);
2326 return possible_cpus
->cpus
[cpu_index
].props
;
2329 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2331 return idx
% ms
->numa_state
->num_nodes
;
2334 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2337 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2338 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2340 if (ms
->possible_cpus
) {
2341 assert(ms
->possible_cpus
->len
== max_cpus
);
2342 return ms
->possible_cpus
;
2345 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2346 sizeof(CPUArchId
) * max_cpus
);
2347 ms
->possible_cpus
->len
= max_cpus
;
2348 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2349 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2350 ms
->possible_cpus
->cpus
[n
].arch_id
=
2351 virt_cpu_mp_affinity(vms
, n
);
2352 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2353 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
2355 return ms
->possible_cpus
;
2358 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2361 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2362 const MachineState
*ms
= MACHINE(hotplug_dev
);
2363 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2365 if (!vms
->acpi_dev
) {
2367 "memory hotplug is not enabled: missing acpi-ged device");
2372 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2376 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2377 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2381 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2384 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2385 DeviceState
*dev
, Error
**errp
)
2387 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2388 MachineState
*ms
= MACHINE(hotplug_dev
);
2389 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2391 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2394 nvdimm_plug(ms
->nvdimms_state
);
2397 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2401 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2402 DeviceState
*dev
, Error
**errp
)
2404 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2406 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2407 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2408 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2409 hwaddr db_start
= 0, db_end
= 0;
2410 char *resv_prop_str
;
2412 switch (vms
->msi_controller
) {
2413 case VIRT_MSI_CTRL_NONE
:
2415 case VIRT_MSI_CTRL_ITS
:
2416 /* GITS_TRANSLATER page */
2417 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2418 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2419 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2421 case VIRT_MSI_CTRL_GICV2M
:
2422 /* MSI_SETSPI_NS page */
2423 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2424 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2427 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2429 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2431 qdev_prop_set_uint32(dev
, "len-reserved-regions", 1);
2432 qdev_prop_set_string(dev
, "reserved-regions[0]", resv_prop_str
);
2433 g_free(resv_prop_str
);
2437 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2438 DeviceState
*dev
, Error
**errp
)
2440 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2442 if (vms
->platform_bus_dev
) {
2443 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2445 if (device_is_dynamic_sysbus(mc
, dev
)) {
2446 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2447 SYS_BUS_DEVICE(dev
));
2450 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2451 virt_memory_plug(hotplug_dev
, dev
, errp
);
2453 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2454 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2456 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2457 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2458 create_virtio_iommu_dt_bindings(vms
);
2462 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2463 DeviceState
*dev
, Error
**errp
)
2465 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2466 Error
*local_err
= NULL
;
2468 if (!vms
->acpi_dev
) {
2469 error_setg(&local_err
,
2470 "memory hotplug is not enabled: missing acpi-ged device");
2474 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2475 error_setg(&local_err
,
2476 "nvdimm device hot unplug is not supported yet.");
2480 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2483 error_propagate(errp
, local_err
);
2486 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2487 DeviceState
*dev
, Error
**errp
)
2489 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2490 Error
*local_err
= NULL
;
2492 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2497 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2498 qdev_unrealize(dev
);
2501 error_propagate(errp
, local_err
);
2504 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2505 DeviceState
*dev
, Error
**errp
)
2507 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2508 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2510 error_setg(errp
, "device unplug request for unsupported device"
2511 " type: %s", object_get_typename(OBJECT(dev
)));
2515 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2516 DeviceState
*dev
, Error
**errp
)
2518 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2519 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2521 error_setg(errp
, "virt: device unplug for unsupported device"
2522 " type: %s", object_get_typename(OBJECT(dev
)));
2526 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2529 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2531 if (device_is_dynamic_sysbus(mc
, dev
) ||
2532 (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
))) {
2533 return HOTPLUG_HANDLER(machine
);
2535 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2536 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2538 if (!vms
->bootinfo
.firmware_loaded
|| !virt_is_acpi_enabled(vms
)) {
2539 return HOTPLUG_HANDLER(machine
);
2546 * for arm64 kvm_type [7-0] encodes the requested number of bits
2547 * in the IPA address space
2549 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2551 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2552 int max_vm_pa_size
, requested_pa_size
;
2555 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2557 /* we freeze the memory map to compute the highest gpa */
2558 virt_set_memmap(vms
);
2560 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2563 * KVM requires the IPA size to be at least 32 bits.
2565 if (requested_pa_size
< 32) {
2566 requested_pa_size
= 32;
2569 if (requested_pa_size
> max_vm_pa_size
) {
2570 error_report("-m and ,maxmem option values "
2571 "require an IPA range (%d bits) larger than "
2572 "the one supported by the host (%d bits)",
2573 requested_pa_size
, max_vm_pa_size
);
2577 * We return the requested PA log size, unless KVM only supports
2578 * the implicit legacy 40b IPA setting, in which case the kvm_type
2581 return fixed_ipa
? 0 : requested_pa_size
;
2584 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2586 MachineClass
*mc
= MACHINE_CLASS(oc
);
2587 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2589 mc
->init
= machvirt_init
;
2590 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2591 * The value may be reduced later when we have more information about the
2592 * configuration of the particular instance.
2595 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2596 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2597 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2598 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2599 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2600 mc
->block_default_type
= IF_VIRTIO
;
2602 mc
->pci_allow_0_address
= true;
2603 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2604 mc
->minimum_page_bits
= 12;
2605 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2606 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2607 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2608 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2609 mc
->kvm_type
= virt_kvm_type
;
2610 assert(!mc
->get_hotplug_handler
);
2611 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2612 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2613 hc
->plug
= virt_machine_device_plug_cb
;
2614 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2615 hc
->unplug
= virt_machine_device_unplug_cb
;
2616 mc
->nvdimm_supported
= true;
2617 mc
->auto_enable_numa_with_memhp
= true;
2618 mc
->auto_enable_numa_with_memdev
= true;
2619 mc
->default_ram_id
= "mach-virt.ram";
2621 object_class_property_add(oc
, "acpi", "OnOffAuto",
2622 virt_get_acpi
, virt_set_acpi
,
2624 object_class_property_set_description(oc
, "acpi",
2626 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2628 object_class_property_set_description(oc
, "secure",
2629 "Set on/off to enable/disable the ARM "
2630 "Security Extensions (TrustZone)");
2632 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2634 object_class_property_set_description(oc
, "virtualization",
2635 "Set on/off to enable/disable emulating a "
2636 "guest CPU which implements the ARM "
2637 "Virtualization Extensions");
2639 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2641 object_class_property_set_description(oc
, "highmem",
2642 "Set on/off to enable/disable using "
2643 "physical address space above 32 bits");
2645 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
2646 virt_set_gic_version
);
2647 object_class_property_set_description(oc
, "gic-version",
2649 "Valid values are 2, 3, host and max");
2651 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
2652 object_class_property_set_description(oc
, "iommu",
2653 "Set the IOMMU type. "
2654 "Valid values are none and smmuv3");
2656 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
2658 object_class_property_set_description(oc
, "ras",
2659 "Set on/off to enable/disable reporting host memory errors "
2660 "to a KVM guest using ACPI and guest external abort exceptions");
2662 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
2663 object_class_property_set_description(oc
, "mte",
2664 "Set on/off to enable/disable emulating a "
2665 "guest CPU which implements the ARM "
2666 "Memory Tagging Extension");
2668 object_class_property_add_bool(oc
, "its", virt_get_its
,
2670 object_class_property_set_description(oc
, "its",
2671 "Set on/off to enable/disable "
2672 "ITS instantiation");
2674 object_class_property_add_str(oc
, "x-oem-id",
2677 object_class_property_set_description(oc
, "x-oem-id",
2678 "Override the default value of field OEMID "
2679 "in ACPI table header."
2680 "The string may be up to 6 bytes in size");
2683 object_class_property_add_str(oc
, "x-oem-table-id",
2684 virt_get_oem_table_id
,
2685 virt_set_oem_table_id
);
2686 object_class_property_set_description(oc
, "x-oem-table-id",
2687 "Override the default value of field OEM Table ID "
2688 "in ACPI table header."
2689 "The string may be up to 8 bytes in size");
2693 static void virt_instance_init(Object
*obj
)
2695 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2696 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
2698 /* EL3 is disabled by default on virt: this makes us consistent
2699 * between KVM and TCG for this board, and it also allows us to
2700 * boot UEFI blobs which assume no TrustZone support.
2702 vms
->secure
= false;
2704 /* EL2 is also disabled by default, for similar reasons */
2707 /* High memory is enabled by default */
2708 vms
->highmem
= true;
2709 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
2711 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2716 /* Default allows ITS instantiation */
2720 /* Default disallows iommu instantiation */
2721 vms
->iommu
= VIRT_IOMMU_NONE
;
2723 /* Default disallows RAS instantiation */
2726 /* MTE is disabled by default. */
2729 vms
->irqmap
= a15irqmap
;
2731 virt_flash_create(vms
);
2733 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
2734 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
2737 static const TypeInfo virt_machine_info
= {
2738 .name
= TYPE_VIRT_MACHINE
,
2739 .parent
= TYPE_MACHINE
,
2741 .instance_size
= sizeof(VirtMachineState
),
2742 .class_size
= sizeof(VirtMachineClass
),
2743 .class_init
= virt_machine_class_init
,
2744 .instance_init
= virt_instance_init
,
2745 .interfaces
= (InterfaceInfo
[]) {
2746 { TYPE_HOTPLUG_HANDLER
},
2751 static void machvirt_machine_init(void)
2753 type_register_static(&virt_machine_info
);
2755 type_init(machvirt_machine_init
);
2757 static void virt_machine_6_1_options(MachineClass
*mc
)
2760 DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
2762 static void virt_machine_6_0_options(MachineClass
*mc
)
2765 DEFINE_VIRT_MACHINE(6, 0)
2767 static void virt_machine_5_2_options(MachineClass
*mc
)
2769 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2771 virt_machine_6_0_options(mc
);
2772 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
2773 vmc
->no_secure_gpio
= true;
2775 DEFINE_VIRT_MACHINE(5, 2)
2777 static void virt_machine_5_1_options(MachineClass
*mc
)
2779 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2781 virt_machine_5_2_options(mc
);
2782 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
2783 vmc
->no_kvm_steal_time
= true;
2785 DEFINE_VIRT_MACHINE(5, 1)
2787 static void virt_machine_5_0_options(MachineClass
*mc
)
2789 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2791 virt_machine_5_1_options(mc
);
2792 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
2793 mc
->numa_mem_supported
= true;
2794 vmc
->acpi_expose_flash
= true;
2795 mc
->auto_enable_numa_with_memdev
= false;
2797 DEFINE_VIRT_MACHINE(5, 0)
2799 static void virt_machine_4_2_options(MachineClass
*mc
)
2801 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2803 virt_machine_5_0_options(mc
);
2804 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
2805 vmc
->kvm_no_adjvtime
= true;
2807 DEFINE_VIRT_MACHINE(4, 2)
2809 static void virt_machine_4_1_options(MachineClass
*mc
)
2811 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2813 virt_machine_4_2_options(mc
);
2814 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
2816 mc
->auto_enable_numa_with_memhp
= false;
2818 DEFINE_VIRT_MACHINE(4, 1)
2820 static void virt_machine_4_0_options(MachineClass
*mc
)
2822 virt_machine_4_1_options(mc
);
2823 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
2825 DEFINE_VIRT_MACHINE(4, 0)
2827 static void virt_machine_3_1_options(MachineClass
*mc
)
2829 virt_machine_4_0_options(mc
);
2830 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
2832 DEFINE_VIRT_MACHINE(3, 1)
2834 static void virt_machine_3_0_options(MachineClass
*mc
)
2836 virt_machine_3_1_options(mc
);
2837 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
2839 DEFINE_VIRT_MACHINE(3, 0)
2841 static void virt_machine_2_12_options(MachineClass
*mc
)
2843 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2845 virt_machine_3_0_options(mc
);
2846 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2847 vmc
->no_highmem_ecam
= true;
2850 DEFINE_VIRT_MACHINE(2, 12)
2852 static void virt_machine_2_11_options(MachineClass
*mc
)
2854 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2856 virt_machine_2_12_options(mc
);
2857 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2858 vmc
->smbios_old_sys_ver
= true;
2860 DEFINE_VIRT_MACHINE(2, 11)
2862 static void virt_machine_2_10_options(MachineClass
*mc
)
2864 virt_machine_2_11_options(mc
);
2865 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2866 /* before 2.11 we never faulted accesses to bad addresses */
2867 mc
->ignore_memory_transaction_failures
= true;
2869 DEFINE_VIRT_MACHINE(2, 10)
2871 static void virt_machine_2_9_options(MachineClass
*mc
)
2873 virt_machine_2_10_options(mc
);
2874 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2876 DEFINE_VIRT_MACHINE(2, 9)
2878 static void virt_machine_2_8_options(MachineClass
*mc
)
2880 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2882 virt_machine_2_9_options(mc
);
2883 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2884 /* For 2.8 and earlier we falsely claimed in the DT that
2885 * our timers were edge-triggered, not level-triggered.
2887 vmc
->claim_edge_triggered_timers
= true;
2889 DEFINE_VIRT_MACHINE(2, 8)
2891 static void virt_machine_2_7_options(MachineClass
*mc
)
2893 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2895 virt_machine_2_8_options(mc
);
2896 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2897 /* ITS was introduced with 2.8 */
2899 /* Stick with 1K pages for migration compatibility */
2900 mc
->minimum_page_bits
= 0;
2902 DEFINE_VIRT_MACHINE(2, 7)
2904 static void virt_machine_2_6_options(MachineClass
*mc
)
2906 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2908 virt_machine_2_7_options(mc
);
2909 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2910 vmc
->disallow_affinity_adjustment
= true;
2911 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2914 DEFINE_VIRT_MACHINE(2, 6)