hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "hw/boards.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/kvm.h"
  27 #include "sysemu/sysemu.h"
  28 #include "kvm_arm.h"
  29
  30 #define GIC_NUM_SPI_INTR 160
  31
  32 #define ARM_PHYS_TIMER_PPI  30
  33 #define ARM_VIRT_TIMER_PPI  27
  34 #define ARM_HYP_TIMER_PPI   26
  35 #define ARM_SEC_TIMER_PPI   29
  36 #define GIC_MAINTENANCE_PPI 25
  37
  38 #define GEM_REVISION        0x40070106
  39
  40 #define GIC_BASE_ADDR       0xf9000000
  41 #define GIC_DIST_ADDR       0xf9010000
  42 #define GIC_CPU_ADDR        0xf9020000
  43 #define GIC_VIFACE_ADDR     0xf9040000
  44 #define GIC_VCPU_ADDR       0xf9060000
  45
  46 #define SATA_INTR           133
  47 #define SATA_ADDR           0xFD0C0000
  48 #define SATA_NUM_PORTS      2
  49
  50 #define QSPI_ADDR           0xff0f0000
  51 #define LQSPI_ADDR          0xc0000000
  52 #define QSPI_IRQ            15
  53
  54 #define DP_ADDR             0xfd4a0000
  55 #define DP_IRQ              113
  56
  57 #define DPDMA_ADDR          0xfd4c0000
  58 #define DPDMA_IRQ           116
  59
  60 #define IPI_ADDR            0xFF300000
  61 #define IPI_IRQ             64
  62
  63 #define RTC_ADDR            0xffa60000
  64 #define RTC_IRQ             26
  65
  66 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  67
  68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  69     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  70 };
  71
  72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  73     57, 59, 61, 63,
  74 };
  75
  76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  77     0xFF000000, 0xFF010000,
  78 };
  79
  80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  81     21, 22,
  82 };
  83
  84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  85     0xFF160000, 0xFF170000,
  86 };
  87
  88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  89     48, 49,
  90 };
  91
  92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  93     0xFF040000, 0xFF050000,
  94 };
  95
  96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  97     19, 20,
  98 };
  99
 100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 101     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
 102     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
 103 };
 104
 105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 106     124, 125, 126, 127, 128, 129, 130, 131
 107 };
 108
 109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 110     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
 111     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
 112 };
 113
 114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 115     77, 78, 79, 80, 81, 82, 83, 84
 116 };
 117
 118 typedef struct XlnxZynqMPGICRegion {
 119     int region_index;
 120     uint32_t address;
 121     uint32_t offset;
 122     bool virt;
 123 } XlnxZynqMPGICRegion;
 124
 125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
 126     /* Distributor */
 127     {
 128         .region_index = 0,
 129         .address = GIC_DIST_ADDR,
 130         .offset = 0,
 131         .virt = false
 132     },
 133
 134     /* CPU interface */
 135     {
 136         .region_index = 1,
 137         .address = GIC_CPU_ADDR,
 138         .offset = 0,
 139         .virt = false
 140     },
 141     {
 142         .region_index = 1,
 143         .address = GIC_CPU_ADDR + 0x10000,
 144         .offset = 0x1000,
 145         .virt = false
 146     },
 147
 148     /* Virtual interface */
 149     {
 150         .region_index = 2,
 151         .address = GIC_VIFACE_ADDR,
 152         .offset = 0,
 153         .virt = true
 154     },
 155
 156     /* Virtual CPU interface */
 157     {
 158         .region_index = 3,
 159         .address = GIC_VCPU_ADDR,
 160         .offset = 0,
 161         .virt = true
 162     },
 163     {
 164         .region_index = 3,
 165         .address = GIC_VCPU_ADDR + 0x10000,
 166         .offset = 0x1000,
 167         .virt = true
 168     },
 169 };
 170
 171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
 172 {
 173     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 174 }
 175
 176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
 177                                    const char *boot_cpu, Error **errp)
 178 {
 179     int i;
 180     int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
 181                        XLNX_ZYNQMP_NUM_RPU_CPUS);
 182
 183     if (num_rpus <= 0) {
 184         /* Don't create rpu-cluster object if there's nothing to put in it */
 185         return;
 186     }
 187
 188     object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
 189                             TYPE_CPU_CLUSTER);
 190     qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
 191
 192     for (i = 0; i < num_rpus; i++) {
 193         const char *name;
 194
 195         object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
 196                                 &s->rpu_cpu[i],
 197                                 ARM_CPU_TYPE_NAME("cortex-r5f"));
 198
 199         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 200         if (strcmp(name, boot_cpu)) {
 201             /* Secondary CPUs start in PSCI powered-down state */
 202             object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
 203                                      "start-powered-off", true, &error_abort);
 204         } else {
 205             s->boot_cpu_ptr = &s->rpu_cpu[i];
 206         }
 207
 208         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
 209                                  &error_abort);
 210         if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
 211             return;
 212         }
 213     }
 214
 215     qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
 216 }
 217
 218 static void xlnx_zynqmp_init(Object *obj)
 219 {
 220     MachineState *ms = MACHINE(qdev_get_machine());
 221     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 222     int i;
 223     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 224
 225     object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
 226                             TYPE_CPU_CLUSTER);
 227     qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
 228
 229     for (i = 0; i < num_apus; i++) {
 230         object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
 231                                 &s->apu_cpu[i],
 232                                 ARM_CPU_TYPE_NAME("cortex-a53"));
 233     }
 234
 235     object_initialize_child(obj, "gic", &s->gic, gic_class_name());
 236
 237     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 238         object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
 239     }
 240
 241     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 242         object_initialize_child(obj, "uart[*]", &s->uart[i],
 243                                 TYPE_CADENCE_UART);
 244     }
 245
 246     object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
 247
 248     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 249         object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
 250                                 TYPE_SYSBUS_SDHCI);
 251     }
 252
 253     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 254         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
 255     }
 256
 257     object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
 258
 259     object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
 260
 261     object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
 262
 263     object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
 264
 265     object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
 266
 267     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 268         object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
 269     }
 270
 271     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 272         object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
 273     }
 274 }
 275
 276 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 277 {
 278     MachineState *ms = MACHINE(qdev_get_machine());
 279     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 280     MemoryRegion *system_memory = get_system_memory();
 281     uint8_t i;
 282     uint64_t ram_size;
 283     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 284     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 285     ram_addr_t ddr_low_size, ddr_high_size;
 286     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 287     Error *err = NULL;
 288
 289     ram_size = memory_region_size(s->ddr_ram);
 290
 291     /* Create the DDR Memory Regions. User friendly checks should happen at
 292      * the board level
 293      */
 294     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 295         /* The RAM size is above the maximum available for the low DDR.
 296          * Create the high DDR memory region as well.
 297          */
 298         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 299         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 300         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 301
 302         memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
 303                                  "ddr-ram-high", s->ddr_ram, ddr_low_size,
 304                                  ddr_high_size);
 305         memory_region_add_subregion(get_system_memory(),
 306                                     XLNX_ZYNQMP_HIGH_RAM_START,
 307                                     &s->ddr_ram_high);
 308     } else {
 309         /* RAM must be non-zero */
 310         assert(ram_size);
 311         ddr_low_size = ram_size;
 312     }
 313
 314     memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
 315                              s->ddr_ram, 0, ddr_low_size);
 316     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 317
 318     /* Create the four OCM banks */
 319     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 320         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 321
 322         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 323                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 324         memory_region_add_subregion(get_system_memory(),
 325                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 326                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 327                                     &s->ocm_ram[i]);
 328
 329         g_free(ocm_name);
 330     }
 331
 332     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 333     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 334     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 335     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
 336     qdev_prop_set_bit(DEVICE(&s->gic),
 337                       "has-virtualization-extensions", s->virt);
 338
 339     qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
 340
 341     /* Realize APUs before realizing the GIC. KVM requires this.  */
 342     for (i = 0; i < num_apus; i++) {
 343         const char *name;
 344
 345         object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit",
 346                                 QEMU_PSCI_CONDUIT_SMC, &error_abort);
 347
 348         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 349         if (strcmp(name, boot_cpu)) {
 350             /* Secondary CPUs start in PSCI powered-down state */
 351             object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 352                                      "start-powered-off", true, &error_abort);
 353         } else {
 354             s->boot_cpu_ptr = &s->apu_cpu[i];
 355         }
 356
 357         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
 358                                  NULL);
 359         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
 360                                  NULL);
 361         object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
 362                                 GIC_BASE_ADDR, &error_abort);
 363         object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
 364                                 num_apus, &error_abort);
 365         if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
 366             return;
 367         }
 368     }
 369
 370     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
 371         return;
 372     }
 373
 374     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 375     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 376         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 377         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 378         MemoryRegion *mr;
 379         uint32_t addr = r->address;
 380         int j;
 381
 382         if (r->virt && !s->virt) {
 383             continue;
 384         }
 385
 386         mr = sysbus_mmio_get_region(gic, r->region_index);
 387         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 388             MemoryRegion *alias = &s->gic_mr[i][j];
 389
 390             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 391                                      r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
 392             memory_region_add_subregion(system_memory, addr, alias);
 393
 394             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 395         }
 396     }
 397
 398     for (i = 0; i < num_apus; i++) {
 399         qemu_irq irq;
 400
 401         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 402                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 403                                             ARM_CPU_IRQ));
 404         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
 405                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 406                                             ARM_CPU_FIQ));
 407         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
 408                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 409                                             ARM_CPU_VIRQ));
 410         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
 411                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 412                                             ARM_CPU_VFIQ));
 413         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 414                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 415         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
 416         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 417                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 418         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
 419         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 420                                arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
 421         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
 422         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 423                                arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
 424         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
 425
 426         if (s->virt) {
 427             irq = qdev_get_gpio_in(DEVICE(&s->gic),
 428                                    arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
 429             sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
 430         }
 431     }
 432
 433     if (s->has_rpu) {
 434         info_report("The 'has_rpu' property is no longer required, to use the "
 435                     "RPUs just use -smp 6.");
 436     }
 437
 438     xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
 439     if (err) {
 440         error_propagate(errp, err);
 441         return;
 442     }
 443
 444     if (!s->boot_cpu_ptr) {
 445         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 446         return;
 447     }
 448
 449     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 450         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 451     }
 452
 453     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 454         NICInfo *nd = &nd_table[i];
 455
 456         /* FIXME use qdev NIC properties instead of nd_table[] */
 457         if (nd->used) {
 458             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 459             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 460         }
 461         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
 462                                 &error_abort);
 463         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
 464                                 &error_abort);
 465         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
 466             return;
 467         }
 468         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 469         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 470                            gic_spi[gem_intr[i]]);
 471     }
 472
 473     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 474         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 475         if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
 476             return;
 477         }
 478         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 479         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 480                            gic_spi[uart_intr[i]]);
 481     }
 482
 483     object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
 484                             &error_abort);
 485     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
 486         return;
 487     }
 488
 489     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 490     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 491
 492     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 493         char *bus_name;
 494         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
 495         Object *sdhci = OBJECT(&s->sdhci[i]);
 496
 497         /* Compatible with:
 498          * - SD Host Controller Specification Version 3.00
 499          * - SDIO Specification Version 3.0
 500          * - eMMC Specification Version 4.51
 501          */
 502         if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
 503             return;
 504         }
 505         if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
 506                                       errp)) {
 507             return;
 508         }
 509         if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
 510             return;
 511         }
 512         if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
 513             return;
 514         }
 515         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
 516         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
 517
 518         /* Alias controller SD bus to the SoC itself */
 519         bus_name = g_strdup_printf("sd-bus%d", i);
 520         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
 521         g_free(bus_name);
 522     }
 523
 524     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 525         gchar *bus_name;
 526
 527         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 528             return;
 529         }
 530
 531         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 532         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 533                            gic_spi[spi_intr[i]]);
 534
 535         /* Alias controller SPI bus to the SoC itself */
 536         bus_name = g_strdup_printf("spi%d", i);
 537         object_property_add_alias(OBJECT(s), bus_name,
 538                                   OBJECT(&s->spi[i]), "spi0");
 539         g_free(bus_name);
 540     }
 541
 542     if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
 543         return;
 544     }
 545     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 546     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 547     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 548
 549     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 550         gchar *bus_name;
 551         gchar *target_bus;
 552
 553         /* Alias controller SPI bus to the SoC itself */
 554         bus_name = g_strdup_printf("qspi%d", i);
 555         target_bus = g_strdup_printf("spi%d", i);
 556         object_property_add_alias(OBJECT(s), bus_name,
 557                                   OBJECT(&s->qspi), target_bus);
 558         g_free(bus_name);
 559         g_free(target_bus);
 560     }
 561
 562     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
 563         return;
 564     }
 565     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 566     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 567
 568     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
 569         return;
 570     }
 571     object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
 572                              &error_abort);
 573     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 574     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 575
 576     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
 577         return;
 578     }
 579     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 580     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 581
 582     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
 583         return;
 584     }
 585     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
 586     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
 587
 588     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 589         if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
 590                                       errp)) {
 591             return;
 592         }
 593         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
 594             return;
 595         }
 596
 597         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
 598         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
 599                            gic_spi[gdma_ch_intr[i]]);
 600     }
 601
 602     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 603         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
 604             return;
 605         }
 606
 607         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
 608         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
 609                            gic_spi[adma_ch_intr[i]]);
 610     }
 611 }
 612
 613 static Property xlnx_zynqmp_props[] = {
 614     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 615     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 616     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 617     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 618     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 619                      MemoryRegion *),
 620     DEFINE_PROP_END_OF_LIST()
 621 };
 622
 623 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 624 {
 625     DeviceClass *dc = DEVICE_CLASS(oc);
 626
 627     device_class_set_props(dc, xlnx_zynqmp_props);
 628     dc->realize = xlnx_zynqmp_realize;
 629     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 630     dc->user_creatable = false;
 631 }
 632
 633 static const TypeInfo xlnx_zynqmp_type_info = {
 634     .name = TYPE_XLNX_ZYNQMP,
 635     .parent = TYPE_DEVICE,
 636     .instance_size = sizeof(XlnxZynqMPState),
 637     .instance_init = xlnx_zynqmp_init,
 638     .class_init = xlnx_zynqmp_class_init,
 639 };
 640
 641 static void xlnx_zynqmp_register_types(void)
 642 {
 643     type_register_static(&xlnx_zynqmp_type_info);
 644 }
 645
 646 type_init(xlnx_zynqmp_register_types)