2 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29 #include "migration/vmstate.h"
30 #include "qemu/module.h"
31 #include "hw/char/escc.h"
32 #include "ui/console.h"
37 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
38 * http://www.zilog.com/docs/serial/scc_escc_um.pdf
40 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
41 * (Slave I/O), also produced as NCR89C105. See
42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
44 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
45 * mouse and keyboard ports don't implement all functions and they are
46 * only asynchronous. There is no DMA.
48 * Z85C30 is also used on PowerMacs. There are some small differences
49 * between Sparc version (sunzilog) and PowerMac (pmac):
50 * Offset between control and data registers
51 * There is some kind of lockup bug, but we can ignore it
53 * DMA on pmac using DBDMA chip
54 * pmac can do IRDA and faster rates, sunzilog can only do 38400
55 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
60 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
62 * Implemented serial mouse protocol.
64 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
67 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a')
73 #define CMD_PTR_MASK 0x07
74 #define CMD_CMD_MASK 0x38
76 #define CMD_CLR_TXINT 0x28
77 #define CMD_CLR_IUS 0x38
79 #define INTR_INTALL 0x01
80 #define INTR_TXINT 0x02
81 #define INTR_RXMODEMSK 0x18
82 #define INTR_RXINT1ST 0x08
83 #define INTR_RXINTALL 0x10
86 #define RXCTRL_RXEN 0x01
88 #define TXCTRL1_PAREN 0x01
89 #define TXCTRL1_PAREV 0x02
90 #define TXCTRL1_1STOP 0x04
91 #define TXCTRL1_1HSTOP 0x08
92 #define TXCTRL1_2STOP 0x0c
93 #define TXCTRL1_STPMSK 0x0c
94 #define TXCTRL1_CLK1X 0x00
95 #define TXCTRL1_CLK16X 0x40
96 #define TXCTRL1_CLK32X 0x80
97 #define TXCTRL1_CLK64X 0xc0
98 #define TXCTRL1_CLKMSK 0xc0
100 #define TXCTRL2_TXEN 0x08
101 #define TXCTRL2_BITMSK 0x60
102 #define TXCTRL2_5BITS 0x00
103 #define TXCTRL2_7BITS 0x20
104 #define TXCTRL2_6BITS 0x40
105 #define TXCTRL2_8BITS 0x60
110 #define MINTR_STATUSHI 0x10
111 #define MINTR_RST_MASK 0xc0
112 #define MINTR_RST_B 0x40
113 #define MINTR_RST_A 0x80
114 #define MINTR_RST_ALL 0xc0
117 #define CLOCK_TRXC 0x08
121 #define MISC2_PLLDIS 0x30
123 #define EXTINT_DCD 0x08
124 #define EXTINT_SYNCINT 0x10
125 #define EXTINT_CTSINT 0x20
126 #define EXTINT_TXUNDRN 0x40
127 #define EXTINT_BRKINT 0x80
130 #define STATUS_RXAV 0x01
131 #define STATUS_ZERO 0x02
132 #define STATUS_TXEMPTY 0x04
133 #define STATUS_DCD 0x08
134 #define STATUS_SYNC 0x10
135 #define STATUS_CTS 0x20
136 #define STATUS_TXUNDRN 0x40
137 #define STATUS_BRK 0x80
139 #define SPEC_ALLSENT 0x01
140 #define SPEC_BITS8 0x06
142 #define IVEC_TXINTB 0x00
143 #define IVEC_LONOINT 0x06
144 #define IVEC_LORXINTA 0x0c
145 #define IVEC_LORXINTB 0x04
146 #define IVEC_LOTXINTA 0x08
147 #define IVEC_HINOINT 0x60
148 #define IVEC_HIRXINTA 0x30
149 #define IVEC_HIRXINTB 0x20
150 #define IVEC_HITXINTA 0x10
152 #define INTR_EXTINTB 0x01
153 #define INTR_TXINTB 0x02
154 #define INTR_RXINTB 0x04
155 #define INTR_EXTINTA 0x08
156 #define INTR_TXINTA 0x10
157 #define INTR_RXINTA 0x20
171 static void handle_kbd_command(ESCCChannelState
*s
, int val
);
172 static int serial_can_receive(void *opaque
);
173 static void serial_receive_byte(ESCCChannelState
*s
, int ch
);
175 static void clear_queue(void *opaque
)
177 ESCCChannelState
*s
= opaque
;
178 ESCCSERIOQueue
*q
= &s
->queue
;
179 q
->rptr
= q
->wptr
= q
->count
= 0;
182 static void put_queue(void *opaque
, int b
)
184 ESCCChannelState
*s
= opaque
;
185 ESCCSERIOQueue
*q
= &s
->queue
;
187 trace_escc_put_queue(CHN_C(s
), b
);
188 if (q
->count
>= ESCC_SERIO_QUEUE_SIZE
) {
191 q
->data
[q
->wptr
] = b
;
192 if (++q
->wptr
== ESCC_SERIO_QUEUE_SIZE
) {
196 serial_receive_byte(s
, 0);
199 static uint32_t get_queue(void *opaque
)
201 ESCCChannelState
*s
= opaque
;
202 ESCCSERIOQueue
*q
= &s
->queue
;
208 val
= q
->data
[q
->rptr
];
209 if (++q
->rptr
== ESCC_SERIO_QUEUE_SIZE
) {
214 trace_escc_get_queue(CHN_C(s
), val
);
216 serial_receive_byte(s
, 0);
220 static int escc_update_irq_chn(ESCCChannelState
*s
)
222 if ((((s
->wregs
[W_INTR
] & INTR_TXINT
) && (s
->txint
== 1)) ||
223 // tx ints enabled, pending
224 ((((s
->wregs
[W_INTR
] & INTR_RXMODEMSK
) == INTR_RXINT1ST
) ||
225 ((s
->wregs
[W_INTR
] & INTR_RXMODEMSK
) == INTR_RXINTALL
)) &&
226 s
->rxint
== 1) || // rx ints enabled, pending
227 ((s
->wregs
[W_EXTINT
] & EXTINT_BRKINT
) &&
228 (s
->rregs
[R_STATUS
] & STATUS_BRK
)))) { // break int e&p
234 static void escc_update_irq(ESCCChannelState
*s
)
238 irq
= escc_update_irq_chn(s
);
239 irq
|= escc_update_irq_chn(s
->otherchn
);
241 trace_escc_update_irq(irq
);
242 qemu_set_irq(s
->irq
, irq
);
245 static void escc_reset_chn(ESCCChannelState
*s
)
250 for (i
= 0; i
< ESCC_SERIAL_REGS
; i
++) {
254 s
->wregs
[W_TXCTRL1
] = TXCTRL1_1STOP
; // 1X divisor, 1 stop bit, no parity
255 s
->wregs
[W_MINTR
] = MINTR_RST_ALL
;
256 s
->wregs
[W_CLOCK
] = CLOCK_TRXC
; // Synch mode tx clock = TRxC
257 s
->wregs
[W_MISC2
] = MISC2_PLLDIS
; // PLL disabled
258 s
->wregs
[W_EXTINT
] = EXTINT_DCD
| EXTINT_SYNCINT
| EXTINT_CTSINT
|
259 EXTINT_TXUNDRN
| EXTINT_BRKINT
; // Enable most interrupts
261 s
->rregs
[R_STATUS
] = STATUS_TXEMPTY
| STATUS_DCD
| STATUS_SYNC
|
262 STATUS_CTS
| STATUS_TXUNDRN
;
264 s
->rregs
[R_STATUS
] = STATUS_TXEMPTY
| STATUS_TXUNDRN
;
265 s
->rregs
[R_SPEC
] = SPEC_BITS8
| SPEC_ALLSENT
;
268 s
->rxint
= s
->txint
= 0;
269 s
->rxint_under_svc
= s
->txint_under_svc
= 0;
270 s
->e0_mode
= s
->led_mode
= s
->caps_lock_mode
= s
->num_lock_mode
= 0;
274 static void escc_reset(DeviceState
*d
)
276 ESCCState
*s
= ESCC(d
);
278 escc_reset_chn(&s
->chn
[0]);
279 escc_reset_chn(&s
->chn
[1]);
282 static inline void set_rxint(ESCCChannelState
*s
)
285 /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower priority
286 than chn_a rx/tx/special_condition service*/
287 s
->rxint_under_svc
= 1;
288 if (s
->chn
== escc_chn_a
) {
289 s
->rregs
[R_INTR
] |= INTR_RXINTA
;
290 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
291 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HIRXINTA
;
293 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LORXINTA
;
295 s
->otherchn
->rregs
[R_INTR
] |= INTR_RXINTB
;
296 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
297 s
->rregs
[R_IVEC
] = IVEC_HIRXINTB
;
299 s
->rregs
[R_IVEC
] = IVEC_LORXINTB
;
304 static inline void set_txint(ESCCChannelState
*s
)
307 if (!s
->rxint_under_svc
) {
308 s
->txint_under_svc
= 1;
309 if (s
->chn
== escc_chn_a
) {
310 if (s
->wregs
[W_INTR
] & INTR_TXINT
) {
311 s
->rregs
[R_INTR
] |= INTR_TXINTA
;
313 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
314 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HITXINTA
;
316 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LOTXINTA
;
318 s
->rregs
[R_IVEC
] = IVEC_TXINTB
;
319 if (s
->wregs
[W_INTR
] & INTR_TXINT
) {
320 s
->otherchn
->rregs
[R_INTR
] |= INTR_TXINTB
;
327 static inline void clr_rxint(ESCCChannelState
*s
)
330 s
->rxint_under_svc
= 0;
331 if (s
->chn
== escc_chn_a
) {
332 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
333 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HINOINT
;
335 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LONOINT
;
336 s
->rregs
[R_INTR
] &= ~INTR_RXINTA
;
338 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
339 s
->rregs
[R_IVEC
] = IVEC_HINOINT
;
341 s
->rregs
[R_IVEC
] = IVEC_LONOINT
;
342 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_RXINTB
;
349 static inline void clr_txint(ESCCChannelState
*s
)
352 s
->txint_under_svc
= 0;
353 if (s
->chn
== escc_chn_a
) {
354 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
355 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HINOINT
;
357 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LONOINT
;
358 s
->rregs
[R_INTR
] &= ~INTR_TXINTA
;
360 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_TXINTB
;
361 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
362 s
->rregs
[R_IVEC
] = IVEC_HINOINT
;
364 s
->rregs
[R_IVEC
] = IVEC_LONOINT
;
365 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_TXINTB
;
372 static void escc_update_parameters(ESCCChannelState
*s
)
374 int speed
, parity
, data_bits
, stop_bits
;
375 QEMUSerialSetParams ssp
;
377 if (!qemu_chr_fe_backend_connected(&s
->chr
) || s
->type
!= escc_serial
)
380 if (s
->wregs
[W_TXCTRL1
] & TXCTRL1_PAREN
) {
381 if (s
->wregs
[W_TXCTRL1
] & TXCTRL1_PAREV
)
388 if ((s
->wregs
[W_TXCTRL1
] & TXCTRL1_STPMSK
) == TXCTRL1_2STOP
)
392 switch (s
->wregs
[W_TXCTRL2
] & TXCTRL2_BITMSK
) {
407 speed
= s
->clock
/ ((s
->wregs
[W_BRGLO
] | (s
->wregs
[W_BRGHI
] << 8)) + 2);
408 switch (s
->wregs
[W_TXCTRL1
] & TXCTRL1_CLKMSK
) {
424 ssp
.data_bits
= data_bits
;
425 ssp
.stop_bits
= stop_bits
;
426 trace_escc_update_parameters(CHN_C(s
), speed
, parity
, data_bits
, stop_bits
);
427 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
430 static void escc_mem_write(void *opaque
, hwaddr addr
,
431 uint64_t val
, unsigned size
)
433 ESCCState
*serial
= opaque
;
439 saddr
= (addr
>> serial
->it_shift
) & 1;
440 channel
= (addr
>> (serial
->it_shift
+ 1)) & 1;
441 s
= &serial
->chn
[channel
];
444 trace_escc_mem_writeb_ctrl(CHN_C(s
), s
->reg
, val
& 0xff);
448 newreg
= val
& CMD_PTR_MASK
;
458 if (s
->rxint_under_svc
) {
459 s
->rxint_under_svc
= 0;
463 } else if (s
->txint_under_svc
) {
464 s
->txint_under_svc
= 0;
472 case W_INTR
... W_RXCTRL
:
473 case W_SYNC1
... W_TXBUF
:
474 case W_MISC1
... W_CLOCK
:
475 case W_MISC2
... W_EXTINT
:
476 s
->wregs
[s
->reg
] = val
;
480 s
->wregs
[s
->reg
] = val
;
481 escc_update_parameters(s
);
485 s
->wregs
[s
->reg
] = val
;
486 s
->rregs
[s
->reg
] = val
;
487 escc_update_parameters(s
);
490 switch (val
& MINTR_RST_MASK
) {
495 escc_reset_chn(&serial
->chn
[0]);
498 escc_reset_chn(&serial
->chn
[1]);
501 escc_reset(DEVICE(serial
));
514 trace_escc_mem_writeb_data(CHN_C(s
), val
);
516 * Lower the irq when data is written to the Tx buffer and no other
517 * interrupts are currently pending. The irq will be raised again once
518 * the Tx buffer becomes empty below.
523 if (s
->wregs
[W_TXCTRL2
] & TXCTRL2_TXEN
) { // tx enabled
524 if (qemu_chr_fe_backend_connected(&s
->chr
)) {
525 /* XXX this blocks entire thread. Rewrite to use
526 * qemu_chr_fe_write and background I/O callbacks */
527 qemu_chr_fe_write_all(&s
->chr
, &s
->tx
, 1);
528 } else if (s
->type
== escc_kbd
&& !s
->disabled
) {
529 handle_kbd_command(s
, val
);
532 s
->rregs
[R_STATUS
] |= STATUS_TXEMPTY
; // Tx buffer empty
533 s
->rregs
[R_SPEC
] |= SPEC_ALLSENT
; // All sent
541 static uint64_t escc_mem_read(void *opaque
, hwaddr addr
,
544 ESCCState
*serial
= opaque
;
550 saddr
= (addr
>> serial
->it_shift
) & 1;
551 channel
= (addr
>> (serial
->it_shift
+ 1)) & 1;
552 s
= &serial
->chn
[channel
];
555 trace_escc_mem_readb_ctrl(CHN_C(s
), s
->reg
, s
->rregs
[s
->reg
]);
556 ret
= s
->rregs
[s
->reg
];
560 s
->rregs
[R_STATUS
] &= ~STATUS_RXAV
;
562 if (s
->type
== escc_kbd
|| s
->type
== escc_mouse
) {
567 trace_escc_mem_readb_data(CHN_C(s
), ret
);
568 qemu_chr_fe_accept_input(&s
->chr
);
576 static const MemoryRegionOps escc_mem_ops
= {
577 .read
= escc_mem_read
,
578 .write
= escc_mem_write
,
579 .endianness
= DEVICE_NATIVE_ENDIAN
,
581 .min_access_size
= 1,
582 .max_access_size
= 1,
586 static int serial_can_receive(void *opaque
)
588 ESCCChannelState
*s
= opaque
;
591 if (((s
->wregs
[W_RXCTRL
] & RXCTRL_RXEN
) == 0) // Rx not enabled
592 || ((s
->rregs
[R_STATUS
] & STATUS_RXAV
) == STATUS_RXAV
))
593 // char already available
600 static void serial_receive_byte(ESCCChannelState
*s
, int ch
)
602 trace_escc_serial_receive_byte(CHN_C(s
), ch
);
603 s
->rregs
[R_STATUS
] |= STATUS_RXAV
;
608 static void serial_receive_break(ESCCChannelState
*s
)
610 s
->rregs
[R_STATUS
] |= STATUS_BRK
;
614 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
616 ESCCChannelState
*s
= opaque
;
617 serial_receive_byte(s
, buf
[0]);
620 static void serial_event(void *opaque
, int event
)
622 ESCCChannelState
*s
= opaque
;
623 if (event
== CHR_EVENT_BREAK
)
624 serial_receive_break(s
);
627 static const VMStateDescription vmstate_escc_chn
= {
630 .minimum_version_id
= 1,
631 .fields
= (VMStateField
[]) {
632 VMSTATE_UINT32(vmstate_dummy
, ESCCChannelState
),
633 VMSTATE_UINT32(reg
, ESCCChannelState
),
634 VMSTATE_UINT32(rxint
, ESCCChannelState
),
635 VMSTATE_UINT32(txint
, ESCCChannelState
),
636 VMSTATE_UINT32(rxint_under_svc
, ESCCChannelState
),
637 VMSTATE_UINT32(txint_under_svc
, ESCCChannelState
),
638 VMSTATE_UINT8(rx
, ESCCChannelState
),
639 VMSTATE_UINT8(tx
, ESCCChannelState
),
640 VMSTATE_BUFFER(wregs
, ESCCChannelState
),
641 VMSTATE_BUFFER(rregs
, ESCCChannelState
),
642 VMSTATE_END_OF_LIST()
646 static const VMStateDescription vmstate_escc
= {
649 .minimum_version_id
= 1,
650 .fields
= (VMStateField
[]) {
651 VMSTATE_STRUCT_ARRAY(chn
, ESCCState
, 2, 2, vmstate_escc_chn
,
653 VMSTATE_END_OF_LIST()
657 static void sunkbd_handle_event(DeviceState
*dev
, QemuConsole
*src
,
660 ESCCChannelState
*s
= (ESCCChannelState
*)dev
;
664 assert(evt
->type
== INPUT_EVENT_KIND_KEY
);
665 key
= evt
->u
.key
.data
;
666 qcode
= qemu_input_key_value_to_qcode(key
->key
);
667 trace_escc_sunkbd_event_in(qcode
, QKeyCode_str(qcode
),
670 if (qcode
== Q_KEY_CODE_CAPS_LOCK
) {
672 s
->caps_lock_mode
^= 1;
673 if (s
->caps_lock_mode
== 2) {
674 return; /* Drop second press */
677 s
->caps_lock_mode
^= 2;
678 if (s
->caps_lock_mode
== 3) {
679 return; /* Drop first release */
684 if (qcode
== Q_KEY_CODE_NUM_LOCK
) {
686 s
->num_lock_mode
^= 1;
687 if (s
->num_lock_mode
== 2) {
688 return; /* Drop second press */
691 s
->num_lock_mode
^= 2;
692 if (s
->num_lock_mode
== 3) {
693 return; /* Drop first release */
698 if (qcode
> qemu_input_map_qcode_to_sun_len
) {
702 keycode
= qemu_input_map_qcode_to_sun
[qcode
];
706 trace_escc_sunkbd_event_out(keycode
);
707 put_queue(s
, keycode
);
710 static QemuInputHandler sunkbd_handler
= {
711 .name
= "sun keyboard",
712 .mask
= INPUT_EVENT_MASK_KEY
,
713 .event
= sunkbd_handle_event
,
716 static void handle_kbd_command(ESCCChannelState
*s
, int val
)
718 trace_escc_kbd_command(val
);
719 if (s
->led_mode
) { // Ignore led byte
724 case 1: // Reset, return type code
727 put_queue(s
, 4); // Type 4
730 case 0xe: // Set leds
733 case 7: // Query layout
737 put_queue(s
, 0x21); /* en-us layout */
744 static void sunmouse_event(void *opaque
,
745 int dx
, int dy
, int dz
, int buttons_state
)
747 ESCCChannelState
*s
= opaque
;
750 trace_escc_sunmouse_event(dx
, dy
, buttons_state
);
751 ch
= 0x80 | 0x7; /* protocol start byte, no buttons pressed */
753 if (buttons_state
& MOUSE_EVENT_LBUTTON
)
755 if (buttons_state
& MOUSE_EVENT_MBUTTON
)
757 if (buttons_state
& MOUSE_EVENT_RBUTTON
)
769 put_queue(s
, ch
& 0xff);
778 put_queue(s
, ch
& 0xff);
780 // MSC protocol specify two extra motion bytes
786 static void escc_init1(Object
*obj
)
788 ESCCState
*s
= ESCC(obj
);
789 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
792 for (i
= 0; i
< 2; i
++) {
793 sysbus_init_irq(dev
, &s
->chn
[i
].irq
);
794 s
->chn
[i
].chn
= 1 - i
;
796 s
->chn
[0].otherchn
= &s
->chn
[1];
797 s
->chn
[1].otherchn
= &s
->chn
[0];
799 sysbus_init_mmio(dev
, &s
->mmio
);
802 static void escc_realize(DeviceState
*dev
, Error
**errp
)
804 ESCCState
*s
= ESCC(dev
);
807 s
->chn
[0].disabled
= s
->disabled
;
808 s
->chn
[1].disabled
= s
->disabled
;
810 memory_region_init_io(&s
->mmio
, OBJECT(dev
), &escc_mem_ops
, s
, "escc",
811 ESCC_SIZE
<< s
->it_shift
);
813 for (i
= 0; i
< 2; i
++) {
814 if (qemu_chr_fe_backend_connected(&s
->chn
[i
].chr
)) {
815 s
->chn
[i
].clock
= s
->frequency
/ 2;
816 qemu_chr_fe_set_handlers(&s
->chn
[i
].chr
, serial_can_receive
,
817 serial_receive1
, serial_event
, NULL
,
818 &s
->chn
[i
], NULL
, true);
822 if (s
->chn
[0].type
== escc_mouse
) {
823 qemu_add_mouse_event_handler(sunmouse_event
, &s
->chn
[0], 0,
826 if (s
->chn
[1].type
== escc_kbd
) {
827 s
->chn
[1].hs
= qemu_input_handler_register((DeviceState
*)(&s
->chn
[1]),
832 static Property escc_properties
[] = {
833 DEFINE_PROP_UINT32("frequency", ESCCState
, frequency
, 0),
834 DEFINE_PROP_UINT32("it_shift", ESCCState
, it_shift
, 0),
835 DEFINE_PROP_UINT32("disabled", ESCCState
, disabled
, 0),
836 DEFINE_PROP_UINT32("chnBtype", ESCCState
, chn
[0].type
, 0),
837 DEFINE_PROP_UINT32("chnAtype", ESCCState
, chn
[1].type
, 0),
838 DEFINE_PROP_CHR("chrB", ESCCState
, chn
[0].chr
),
839 DEFINE_PROP_CHR("chrA", ESCCState
, chn
[1].chr
),
840 DEFINE_PROP_END_OF_LIST(),
843 static void escc_class_init(ObjectClass
*klass
, void *data
)
845 DeviceClass
*dc
= DEVICE_CLASS(klass
);
847 dc
->reset
= escc_reset
;
848 dc
->realize
= escc_realize
;
849 dc
->vmsd
= &vmstate_escc
;
850 dc
->props
= escc_properties
;
851 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
854 static const TypeInfo escc_info
= {
856 .parent
= TYPE_SYS_BUS_DEVICE
,
857 .instance_size
= sizeof(ESCCState
),
858 .instance_init
= escc_init1
,
859 .class_init
= escc_class_init
,
862 static void escc_register_types(void)
864 type_register_static(&escc_info
);
867 type_init(escc_register_types
)