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[thirdparty/qemu.git] / hw / display / pxa2xx_lcd.c
1 /*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "qemu/osdep.h"
14 #include "hw/hw.h"
15 #include "hw/irq.h"
16 #include "ui/console.h"
17 #include "hw/arm/pxa.h"
18 #include "ui/pixel_ops.h"
19 /* FIXME: For graphic_rotate. Should probably be done in common code. */
20 #include "sysemu/sysemu.h"
21 #include "framebuffer.h"
22
23 struct DMAChannel {
24 uint32_t branch;
25 uint8_t up;
26 uint8_t palette[1024];
27 uint8_t pbuffer[1024];
28 void (*redraw)(PXA2xxLCDState *s, hwaddr addr,
29 int *miny, int *maxy);
30
31 uint32_t descriptor;
32 uint32_t source;
33 uint32_t id;
34 uint32_t command;
35 };
36
37 struct PXA2xxLCDState {
38 MemoryRegion *sysmem;
39 MemoryRegion iomem;
40 MemoryRegionSection fbsection;
41 qemu_irq irq;
42 int irqlevel;
43
44 int invalidated;
45 QemuConsole *con;
46 drawfn *line_fn[2];
47 int dest_width;
48 int xres, yres;
49 int pal_for;
50 int transp;
51 enum {
52 pxa_lcdc_2bpp = 1,
53 pxa_lcdc_4bpp = 2,
54 pxa_lcdc_8bpp = 3,
55 pxa_lcdc_16bpp = 4,
56 pxa_lcdc_18bpp = 5,
57 pxa_lcdc_18pbpp = 6,
58 pxa_lcdc_19bpp = 7,
59 pxa_lcdc_19pbpp = 8,
60 pxa_lcdc_24bpp = 9,
61 pxa_lcdc_25bpp = 10,
62 } bpp;
63
64 uint32_t control[6];
65 uint32_t status[2];
66 uint32_t ovl1c[2];
67 uint32_t ovl2c[2];
68 uint32_t ccr;
69 uint32_t cmdcr;
70 uint32_t trgbr;
71 uint32_t tcr;
72 uint32_t liidr;
73 uint8_t bscntr;
74
75 struct DMAChannel dma_ch[7];
76
77 qemu_irq vsync_cb;
78 int orientation;
79 };
80
81 typedef struct QEMU_PACKED {
82 uint32_t fdaddr;
83 uint32_t fsaddr;
84 uint32_t fidr;
85 uint32_t ldcmd;
86 } PXAFrameDescriptor;
87
88 #define LCCR0 0x000 /* LCD Controller Control register 0 */
89 #define LCCR1 0x004 /* LCD Controller Control register 1 */
90 #define LCCR2 0x008 /* LCD Controller Control register 2 */
91 #define LCCR3 0x00c /* LCD Controller Control register 3 */
92 #define LCCR4 0x010 /* LCD Controller Control register 4 */
93 #define LCCR5 0x014 /* LCD Controller Control register 5 */
94
95 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
96 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
97 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
98 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
99 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
100 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
101 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
102
103 #define LCSR1 0x034 /* LCD Controller Status register 1 */
104 #define LCSR0 0x038 /* LCD Controller Status register 0 */
105 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
106
107 #define TRGBR 0x040 /* TMED RGB Seed register */
108 #define TCR 0x044 /* TMED Control register */
109
110 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
111 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
112 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
113 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
114 #define CCR 0x090 /* Cursor Control register */
115
116 #define CMDCR 0x100 /* Command Control register */
117 #define PRSR 0x104 /* Panel Read Status register */
118
119 #define PXA_LCDDMA_CHANS 7
120 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
121 #define DMA_FSADR 0x04 /* Frame Source Address register */
122 #define DMA_FIDR 0x08 /* Frame ID register */
123 #define DMA_LDCMD 0x0c /* Command register */
124
125 /* LCD Buffer Strength Control register */
126 #define BSCNTR 0x04000054
127
128 /* Bitfield masks */
129 #define LCCR0_ENB (1 << 0)
130 #define LCCR0_CMS (1 << 1)
131 #define LCCR0_SDS (1 << 2)
132 #define LCCR0_LDM (1 << 3)
133 #define LCCR0_SOFM0 (1 << 4)
134 #define LCCR0_IUM (1 << 5)
135 #define LCCR0_EOFM0 (1 << 6)
136 #define LCCR0_PAS (1 << 7)
137 #define LCCR0_DPD (1 << 9)
138 #define LCCR0_DIS (1 << 10)
139 #define LCCR0_QDM (1 << 11)
140 #define LCCR0_PDD (0xff << 12)
141 #define LCCR0_BSM0 (1 << 20)
142 #define LCCR0_OUM (1 << 21)
143 #define LCCR0_LCDT (1 << 22)
144 #define LCCR0_RDSTM (1 << 23)
145 #define LCCR0_CMDIM (1 << 24)
146 #define LCCR0_OUC (1 << 25)
147 #define LCCR0_LDDALT (1 << 26)
148 #define LCCR1_PPL(x) ((x) & 0x3ff)
149 #define LCCR2_LPP(x) ((x) & 0x3ff)
150 #define LCCR3_API (15 << 16)
151 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
152 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
153 #define LCCR4_K1(x) (((x) >> 0) & 7)
154 #define LCCR4_K2(x) (((x) >> 3) & 7)
155 #define LCCR4_K3(x) (((x) >> 6) & 7)
156 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
157 #define LCCR5_SOFM(ch) (1 << (ch - 1))
158 #define LCCR5_EOFM(ch) (1 << (ch + 7))
159 #define LCCR5_BSM(ch) (1 << (ch + 15))
160 #define LCCR5_IUM(ch) (1 << (ch + 23))
161 #define OVLC1_EN (1 << 31)
162 #define CCR_CEN (1 << 31)
163 #define FBR_BRA (1 << 0)
164 #define FBR_BINT (1 << 1)
165 #define FBR_SRCADDR (0xfffffff << 4)
166 #define LCSR0_LDD (1 << 0)
167 #define LCSR0_SOF0 (1 << 1)
168 #define LCSR0_BER (1 << 2)
169 #define LCSR0_ABC (1 << 3)
170 #define LCSR0_IU0 (1 << 4)
171 #define LCSR0_IU1 (1 << 5)
172 #define LCSR0_OU (1 << 6)
173 #define LCSR0_QD (1 << 7)
174 #define LCSR0_EOF0 (1 << 8)
175 #define LCSR0_BS0 (1 << 9)
176 #define LCSR0_SINT (1 << 10)
177 #define LCSR0_RDST (1 << 11)
178 #define LCSR0_CMDINT (1 << 12)
179 #define LCSR0_BERCH(x) (((x) & 7) << 28)
180 #define LCSR1_SOF(ch) (1 << (ch - 1))
181 #define LCSR1_EOF(ch) (1 << (ch + 7))
182 #define LCSR1_BS(ch) (1 << (ch + 15))
183 #define LCSR1_IU(ch) (1 << (ch + 23))
184 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
185 #define LDCMD_EOFINT (1 << 21)
186 #define LDCMD_SOFINT (1 << 22)
187 #define LDCMD_PAL (1 << 26)
188
189 /* Route internal interrupt lines to the global IC */
190 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
191 {
192 int level = 0;
193 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
194 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
195 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
196 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
197 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
198 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
199 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
200 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
201 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
202 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
203 level |= (s->status[1] & ~s->control[5]);
204
205 qemu_set_irq(s->irq, !!level);
206 s->irqlevel = level;
207 }
208
209 /* Set Branch Status interrupt high and poke associated registers */
210 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
211 {
212 int unmasked;
213 if (ch == 0) {
214 s->status[0] |= LCSR0_BS0;
215 unmasked = !(s->control[0] & LCCR0_BSM0);
216 } else {
217 s->status[1] |= LCSR1_BS(ch);
218 unmasked = !(s->control[5] & LCCR5_BSM(ch));
219 }
220
221 if (unmasked) {
222 if (s->irqlevel)
223 s->status[0] |= LCSR0_SINT;
224 else
225 s->liidr = s->dma_ch[ch].id;
226 }
227 }
228
229 /* Set Start Of Frame Status interrupt high and poke associated registers */
230 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
231 {
232 int unmasked;
233 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
234 return;
235
236 if (ch == 0) {
237 s->status[0] |= LCSR0_SOF0;
238 unmasked = !(s->control[0] & LCCR0_SOFM0);
239 } else {
240 s->status[1] |= LCSR1_SOF(ch);
241 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
242 }
243
244 if (unmasked) {
245 if (s->irqlevel)
246 s->status[0] |= LCSR0_SINT;
247 else
248 s->liidr = s->dma_ch[ch].id;
249 }
250 }
251
252 /* Set End Of Frame Status interrupt high and poke associated registers */
253 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
254 {
255 int unmasked;
256 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
257 return;
258
259 if (ch == 0) {
260 s->status[0] |= LCSR0_EOF0;
261 unmasked = !(s->control[0] & LCCR0_EOFM0);
262 } else {
263 s->status[1] |= LCSR1_EOF(ch);
264 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
265 }
266
267 if (unmasked) {
268 if (s->irqlevel)
269 s->status[0] |= LCSR0_SINT;
270 else
271 s->liidr = s->dma_ch[ch].id;
272 }
273 }
274
275 /* Set Bus Error Status interrupt high and poke associated registers */
276 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
277 {
278 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
279 if (s->irqlevel)
280 s->status[0] |= LCSR0_SINT;
281 else
282 s->liidr = s->dma_ch[ch].id;
283 }
284
285 /* Load new Frame Descriptors from DMA */
286 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
287 {
288 PXAFrameDescriptor desc;
289 hwaddr descptr;
290 int i;
291
292 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
293 s->dma_ch[i].source = 0;
294
295 if (!s->dma_ch[i].up)
296 continue;
297
298 if (s->dma_ch[i].branch & FBR_BRA) {
299 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
300 if (s->dma_ch[i].branch & FBR_BINT)
301 pxa2xx_dma_bs_set(s, i);
302 s->dma_ch[i].branch &= ~FBR_BRA;
303 } else
304 descptr = s->dma_ch[i].descriptor;
305
306 if (!((descptr >= PXA2XX_SDRAM_BASE && descptr +
307 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size) ||
308 (descptr >= PXA2XX_INTERNAL_BASE && descptr + sizeof(desc) <=
309 PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
310 continue;
311 }
312
313 cpu_physical_memory_read(descptr, &desc, sizeof(desc));
314 s->dma_ch[i].descriptor = le32_to_cpu(desc.fdaddr);
315 s->dma_ch[i].source = le32_to_cpu(desc.fsaddr);
316 s->dma_ch[i].id = le32_to_cpu(desc.fidr);
317 s->dma_ch[i].command = le32_to_cpu(desc.ldcmd);
318 }
319 }
320
321 static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
322 unsigned size)
323 {
324 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
325 int ch;
326
327 switch (offset) {
328 case LCCR0:
329 return s->control[0];
330 case LCCR1:
331 return s->control[1];
332 case LCCR2:
333 return s->control[2];
334 case LCCR3:
335 return s->control[3];
336 case LCCR4:
337 return s->control[4];
338 case LCCR5:
339 return s->control[5];
340
341 case OVL1C1:
342 return s->ovl1c[0];
343 case OVL1C2:
344 return s->ovl1c[1];
345 case OVL2C1:
346 return s->ovl2c[0];
347 case OVL2C2:
348 return s->ovl2c[1];
349
350 case CCR:
351 return s->ccr;
352
353 case CMDCR:
354 return s->cmdcr;
355
356 case TRGBR:
357 return s->trgbr;
358 case TCR:
359 return s->tcr;
360
361 case 0x200 ... 0x1000: /* DMA per-channel registers */
362 ch = (offset - 0x200) >> 4;
363 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
364 goto fail;
365
366 switch (offset & 0xf) {
367 case DMA_FDADR:
368 return s->dma_ch[ch].descriptor;
369 case DMA_FSADR:
370 return s->dma_ch[ch].source;
371 case DMA_FIDR:
372 return s->dma_ch[ch].id;
373 case DMA_LDCMD:
374 return s->dma_ch[ch].command;
375 default:
376 goto fail;
377 }
378
379 case FBR0:
380 return s->dma_ch[0].branch;
381 case FBR1:
382 return s->dma_ch[1].branch;
383 case FBR2:
384 return s->dma_ch[2].branch;
385 case FBR3:
386 return s->dma_ch[3].branch;
387 case FBR4:
388 return s->dma_ch[4].branch;
389 case FBR5:
390 return s->dma_ch[5].branch;
391 case FBR6:
392 return s->dma_ch[6].branch;
393
394 case BSCNTR:
395 return s->bscntr;
396
397 case PRSR:
398 return 0;
399
400 case LCSR0:
401 return s->status[0];
402 case LCSR1:
403 return s->status[1];
404 case LIIDR:
405 return s->liidr;
406
407 default:
408 fail:
409 hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
410 }
411
412 return 0;
413 }
414
415 static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
416 uint64_t value, unsigned size)
417 {
418 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
419 int ch;
420
421 switch (offset) {
422 case LCCR0:
423 /* ACK Quick Disable done */
424 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
425 s->status[0] |= LCSR0_QD;
426
427 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
428 printf("%s: internal frame buffer unsupported\n", __func__);
429
430 if ((s->control[3] & LCCR3_API) &&
431 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
432 s->status[0] |= LCSR0_ABC;
433
434 s->control[0] = value & 0x07ffffff;
435 pxa2xx_lcdc_int_update(s);
436
437 s->dma_ch[0].up = !!(value & LCCR0_ENB);
438 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
439 break;
440
441 case LCCR1:
442 s->control[1] = value;
443 break;
444
445 case LCCR2:
446 s->control[2] = value;
447 break;
448
449 case LCCR3:
450 s->control[3] = value & 0xefffffff;
451 s->bpp = LCCR3_BPP(value);
452 break;
453
454 case LCCR4:
455 s->control[4] = value & 0x83ff81ff;
456 break;
457
458 case LCCR5:
459 s->control[5] = value & 0x3f3f3f3f;
460 break;
461
462 case OVL1C1:
463 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
464 printf("%s: Overlay 1 not supported\n", __func__);
465
466 s->ovl1c[0] = value & 0x80ffffff;
467 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
468 break;
469
470 case OVL1C2:
471 s->ovl1c[1] = value & 0x000fffff;
472 break;
473
474 case OVL2C1:
475 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
476 printf("%s: Overlay 2 not supported\n", __func__);
477
478 s->ovl2c[0] = value & 0x80ffffff;
479 s->dma_ch[2].up = !!(value & OVLC1_EN);
480 s->dma_ch[3].up = !!(value & OVLC1_EN);
481 s->dma_ch[4].up = !!(value & OVLC1_EN);
482 break;
483
484 case OVL2C2:
485 s->ovl2c[1] = value & 0x007fffff;
486 break;
487
488 case CCR:
489 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
490 printf("%s: Hardware cursor unimplemented\n", __func__);
491
492 s->ccr = value & 0x81ffffe7;
493 s->dma_ch[5].up = !!(value & CCR_CEN);
494 break;
495
496 case CMDCR:
497 s->cmdcr = value & 0xff;
498 break;
499
500 case TRGBR:
501 s->trgbr = value & 0x00ffffff;
502 break;
503
504 case TCR:
505 s->tcr = value & 0x7fff;
506 break;
507
508 case 0x200 ... 0x1000: /* DMA per-channel registers */
509 ch = (offset - 0x200) >> 4;
510 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
511 goto fail;
512
513 switch (offset & 0xf) {
514 case DMA_FDADR:
515 s->dma_ch[ch].descriptor = value & 0xfffffff0;
516 break;
517
518 default:
519 goto fail;
520 }
521 break;
522
523 case FBR0:
524 s->dma_ch[0].branch = value & 0xfffffff3;
525 break;
526 case FBR1:
527 s->dma_ch[1].branch = value & 0xfffffff3;
528 break;
529 case FBR2:
530 s->dma_ch[2].branch = value & 0xfffffff3;
531 break;
532 case FBR3:
533 s->dma_ch[3].branch = value & 0xfffffff3;
534 break;
535 case FBR4:
536 s->dma_ch[4].branch = value & 0xfffffff3;
537 break;
538 case FBR5:
539 s->dma_ch[5].branch = value & 0xfffffff3;
540 break;
541 case FBR6:
542 s->dma_ch[6].branch = value & 0xfffffff3;
543 break;
544
545 case BSCNTR:
546 s->bscntr = value & 0xf;
547 break;
548
549 case PRSR:
550 break;
551
552 case LCSR0:
553 s->status[0] &= ~(value & 0xfff);
554 if (value & LCSR0_BER)
555 s->status[0] &= ~LCSR0_BERCH(7);
556 break;
557
558 case LCSR1:
559 s->status[1] &= ~(value & 0x3e3f3f);
560 break;
561
562 default:
563 fail:
564 hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
565 }
566 }
567
568 static const MemoryRegionOps pxa2xx_lcdc_ops = {
569 .read = pxa2xx_lcdc_read,
570 .write = pxa2xx_lcdc_write,
571 .endianness = DEVICE_NATIVE_ENDIAN,
572 };
573
574 /* Load new palette for a given DMA channel, convert to internal format */
575 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
576 {
577 DisplaySurface *surface = qemu_console_surface(s->con);
578 int i, n, format, r, g, b, alpha;
579 uint32_t *dest;
580 uint8_t *src;
581 s->pal_for = LCCR4_PALFOR(s->control[4]);
582 format = s->pal_for;
583
584 switch (bpp) {
585 case pxa_lcdc_2bpp:
586 n = 4;
587 break;
588 case pxa_lcdc_4bpp:
589 n = 16;
590 break;
591 case pxa_lcdc_8bpp:
592 n = 256;
593 break;
594 default:
595 format = 0;
596 return;
597 }
598
599 src = (uint8_t *) s->dma_ch[ch].pbuffer;
600 dest = (uint32_t *) s->dma_ch[ch].palette;
601 alpha = r = g = b = 0;
602
603 for (i = 0; i < n; i ++) {
604 switch (format) {
605 case 0: /* 16 bpp, no transparency */
606 alpha = 0;
607 if (s->control[0] & LCCR0_CMS) {
608 r = g = b = *(uint16_t *) src & 0xff;
609 }
610 else {
611 r = (*(uint16_t *) src & 0xf800) >> 8;
612 g = (*(uint16_t *) src & 0x07e0) >> 3;
613 b = (*(uint16_t *) src & 0x001f) << 3;
614 }
615 src += 2;
616 break;
617 case 1: /* 16 bpp plus transparency */
618 alpha = *(uint32_t *) src & (1 << 24);
619 if (s->control[0] & LCCR0_CMS)
620 r = g = b = *(uint32_t *) src & 0xff;
621 else {
622 r = (*(uint32_t *) src & 0xf80000) >> 16;
623 g = (*(uint32_t *) src & 0x00fc00) >> 8;
624 b = (*(uint32_t *) src & 0x0000f8);
625 }
626 src += 4;
627 break;
628 case 2: /* 18 bpp plus transparency */
629 alpha = *(uint32_t *) src & (1 << 24);
630 if (s->control[0] & LCCR0_CMS)
631 r = g = b = *(uint32_t *) src & 0xff;
632 else {
633 r = (*(uint32_t *) src & 0xfc0000) >> 16;
634 g = (*(uint32_t *) src & 0x00fc00) >> 8;
635 b = (*(uint32_t *) src & 0x0000fc);
636 }
637 src += 4;
638 break;
639 case 3: /* 24 bpp plus transparency */
640 alpha = *(uint32_t *) src & (1 << 24);
641 if (s->control[0] & LCCR0_CMS)
642 r = g = b = *(uint32_t *) src & 0xff;
643 else {
644 r = (*(uint32_t *) src & 0xff0000) >> 16;
645 g = (*(uint32_t *) src & 0x00ff00) >> 8;
646 b = (*(uint32_t *) src & 0x0000ff);
647 }
648 src += 4;
649 break;
650 }
651 switch (surface_bits_per_pixel(surface)) {
652 case 8:
653 *dest = rgb_to_pixel8(r, g, b) | alpha;
654 break;
655 case 15:
656 *dest = rgb_to_pixel15(r, g, b) | alpha;
657 break;
658 case 16:
659 *dest = rgb_to_pixel16(r, g, b) | alpha;
660 break;
661 case 24:
662 *dest = rgb_to_pixel24(r, g, b) | alpha;
663 break;
664 case 32:
665 *dest = rgb_to_pixel32(r, g, b) | alpha;
666 break;
667 }
668 dest ++;
669 }
670 }
671
672 static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
673 hwaddr addr, int *miny, int *maxy)
674 {
675 DisplaySurface *surface = qemu_console_surface(s->con);
676 int src_width, dest_width;
677 drawfn fn = NULL;
678 if (s->dest_width)
679 fn = s->line_fn[s->transp][s->bpp];
680 if (!fn)
681 return;
682
683 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
684 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
685 src_width *= 3;
686 else if (s->bpp > pxa_lcdc_16bpp)
687 src_width *= 4;
688 else if (s->bpp > pxa_lcdc_8bpp)
689 src_width *= 2;
690
691 dest_width = s->xres * s->dest_width;
692 *miny = 0;
693 if (s->invalidated) {
694 framebuffer_update_memory_section(&s->fbsection, s->sysmem,
695 addr, s->yres, src_width);
696 }
697 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
698 src_width, dest_width, s->dest_width,
699 s->invalidated,
700 fn, s->dma_ch[0].palette, miny, maxy);
701 }
702
703 static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
704 hwaddr addr, int *miny, int *maxy)
705 {
706 DisplaySurface *surface = qemu_console_surface(s->con);
707 int src_width, dest_width;
708 drawfn fn = NULL;
709 if (s->dest_width)
710 fn = s->line_fn[s->transp][s->bpp];
711 if (!fn)
712 return;
713
714 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
715 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
716 src_width *= 3;
717 else if (s->bpp > pxa_lcdc_16bpp)
718 src_width *= 4;
719 else if (s->bpp > pxa_lcdc_8bpp)
720 src_width *= 2;
721
722 dest_width = s->yres * s->dest_width;
723 *miny = 0;
724 if (s->invalidated) {
725 framebuffer_update_memory_section(&s->fbsection, s->sysmem,
726 addr, s->yres, src_width);
727 }
728 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
729 src_width, s->dest_width, -dest_width,
730 s->invalidated,
731 fn, s->dma_ch[0].palette,
732 miny, maxy);
733 }
734
735 static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
736 hwaddr addr, int *miny, int *maxy)
737 {
738 DisplaySurface *surface = qemu_console_surface(s->con);
739 int src_width, dest_width;
740 drawfn fn = NULL;
741 if (s->dest_width) {
742 fn = s->line_fn[s->transp][s->bpp];
743 }
744 if (!fn) {
745 return;
746 }
747
748 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
749 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
750 src_width *= 3;
751 } else if (s->bpp > pxa_lcdc_16bpp) {
752 src_width *= 4;
753 } else if (s->bpp > pxa_lcdc_8bpp) {
754 src_width *= 2;
755 }
756
757 dest_width = s->xres * s->dest_width;
758 *miny = 0;
759 if (s->invalidated) {
760 framebuffer_update_memory_section(&s->fbsection, s->sysmem,
761 addr, s->yres, src_width);
762 }
763 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
764 src_width, -dest_width, -s->dest_width,
765 s->invalidated,
766 fn, s->dma_ch[0].palette, miny, maxy);
767 }
768
769 static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
770 hwaddr addr, int *miny, int *maxy)
771 {
772 DisplaySurface *surface = qemu_console_surface(s->con);
773 int src_width, dest_width;
774 drawfn fn = NULL;
775 if (s->dest_width) {
776 fn = s->line_fn[s->transp][s->bpp];
777 }
778 if (!fn) {
779 return;
780 }
781
782 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
783 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
784 src_width *= 3;
785 } else if (s->bpp > pxa_lcdc_16bpp) {
786 src_width *= 4;
787 } else if (s->bpp > pxa_lcdc_8bpp) {
788 src_width *= 2;
789 }
790
791 dest_width = s->yres * s->dest_width;
792 *miny = 0;
793 if (s->invalidated) {
794 framebuffer_update_memory_section(&s->fbsection, s->sysmem,
795 addr, s->yres, src_width);
796 }
797 framebuffer_update_display(surface, &s->fbsection, s->xres, s->yres,
798 src_width, -s->dest_width, dest_width,
799 s->invalidated,
800 fn, s->dma_ch[0].palette,
801 miny, maxy);
802 }
803
804 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
805 {
806 int width, height;
807 if (!(s->control[0] & LCCR0_ENB))
808 return;
809
810 width = LCCR1_PPL(s->control[1]) + 1;
811 height = LCCR2_LPP(s->control[2]) + 1;
812
813 if (width != s->xres || height != s->yres) {
814 if (s->orientation == 90 || s->orientation == 270) {
815 qemu_console_resize(s->con, height, width);
816 } else {
817 qemu_console_resize(s->con, width, height);
818 }
819 s->invalidated = 1;
820 s->xres = width;
821 s->yres = height;
822 }
823 }
824
825 static void pxa2xx_update_display(void *opaque)
826 {
827 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
828 hwaddr fbptr;
829 int miny, maxy;
830 int ch;
831 if (!(s->control[0] & LCCR0_ENB))
832 return;
833
834 pxa2xx_descriptor_load(s);
835
836 pxa2xx_lcdc_resize(s);
837 miny = s->yres;
838 maxy = 0;
839 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
840 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
841 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
842 if (s->dma_ch[ch].up) {
843 if (!s->dma_ch[ch].source) {
844 pxa2xx_dma_ber_set(s, ch);
845 continue;
846 }
847 fbptr = s->dma_ch[ch].source;
848 if (!((fbptr >= PXA2XX_SDRAM_BASE &&
849 fbptr <= PXA2XX_SDRAM_BASE + ram_size) ||
850 (fbptr >= PXA2XX_INTERNAL_BASE &&
851 fbptr <= PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
852 pxa2xx_dma_ber_set(s, ch);
853 continue;
854 }
855
856 if (s->dma_ch[ch].command & LDCMD_PAL) {
857 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
858 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
859 sizeof(s->dma_ch[ch].pbuffer)));
860 pxa2xx_palette_parse(s, ch, s->bpp);
861 } else {
862 /* Do we need to reparse palette */
863 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
864 pxa2xx_palette_parse(s, ch, s->bpp);
865
866 /* ACK frame start */
867 pxa2xx_dma_sof_set(s, ch);
868
869 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
870 s->invalidated = 0;
871
872 /* ACK frame completed */
873 pxa2xx_dma_eof_set(s, ch);
874 }
875 }
876
877 if (s->control[0] & LCCR0_DIS) {
878 /* ACK last frame completed */
879 s->control[0] &= ~LCCR0_ENB;
880 s->status[0] |= LCSR0_LDD;
881 }
882
883 if (miny >= 0) {
884 switch (s->orientation) {
885 case 0:
886 dpy_gfx_update(s->con, 0, miny, s->xres, maxy - miny + 1);
887 break;
888 case 90:
889 dpy_gfx_update(s->con, miny, 0, maxy - miny + 1, s->xres);
890 break;
891 case 180:
892 maxy = s->yres - maxy - 1;
893 miny = s->yres - miny - 1;
894 dpy_gfx_update(s->con, 0, maxy, s->xres, miny - maxy + 1);
895 break;
896 case 270:
897 maxy = s->yres - maxy - 1;
898 miny = s->yres - miny - 1;
899 dpy_gfx_update(s->con, maxy, 0, miny - maxy + 1, s->xres);
900 break;
901 }
902 }
903 pxa2xx_lcdc_int_update(s);
904
905 qemu_irq_raise(s->vsync_cb);
906 }
907
908 static void pxa2xx_invalidate_display(void *opaque)
909 {
910 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
911 s->invalidated = 1;
912 }
913
914 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
915 {
916 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
917
918 switch (angle) {
919 case 0:
920 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
921 break;
922 case 90:
923 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
924 break;
925 case 180:
926 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
927 break;
928 case 270:
929 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
930 break;
931 }
932
933 s->orientation = angle;
934 s->xres = s->yres = -1;
935 pxa2xx_lcdc_resize(s);
936 }
937
938 static const VMStateDescription vmstate_dma_channel = {
939 .name = "dma_channel",
940 .version_id = 0,
941 .minimum_version_id = 0,
942 .fields = (VMStateField[]) {
943 VMSTATE_UINT32(branch, struct DMAChannel),
944 VMSTATE_UINT8(up, struct DMAChannel),
945 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
946 VMSTATE_UINT32(descriptor, struct DMAChannel),
947 VMSTATE_UINT32(source, struct DMAChannel),
948 VMSTATE_UINT32(id, struct DMAChannel),
949 VMSTATE_UINT32(command, struct DMAChannel),
950 VMSTATE_END_OF_LIST()
951 }
952 };
953
954 static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
955 {
956 PXA2xxLCDState *s = opaque;
957
958 s->bpp = LCCR3_BPP(s->control[3]);
959 s->xres = s->yres = s->pal_for = -1;
960
961 return 0;
962 }
963
964 static const VMStateDescription vmstate_pxa2xx_lcdc = {
965 .name = "pxa2xx_lcdc",
966 .version_id = 0,
967 .minimum_version_id = 0,
968 .post_load = pxa2xx_lcdc_post_load,
969 .fields = (VMStateField[]) {
970 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
971 VMSTATE_INT32(transp, PXA2xxLCDState),
972 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
973 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
974 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
975 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
976 VMSTATE_UINT32(ccr, PXA2xxLCDState),
977 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
978 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
979 VMSTATE_UINT32(tcr, PXA2xxLCDState),
980 VMSTATE_UINT32(liidr, PXA2xxLCDState),
981 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
982 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
983 vmstate_dma_channel, struct DMAChannel),
984 VMSTATE_END_OF_LIST()
985 }
986 };
987
988 #define BITS 8
989 #include "pxa2xx_template.h"
990 #define BITS 15
991 #include "pxa2xx_template.h"
992 #define BITS 16
993 #include "pxa2xx_template.h"
994 #define BITS 24
995 #include "pxa2xx_template.h"
996 #define BITS 32
997 #include "pxa2xx_template.h"
998
999 static const GraphicHwOps pxa2xx_ops = {
1000 .invalidate = pxa2xx_invalidate_display,
1001 .gfx_update = pxa2xx_update_display,
1002 };
1003
1004 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
1005 hwaddr base, qemu_irq irq)
1006 {
1007 PXA2xxLCDState *s;
1008 DisplaySurface *surface;
1009
1010 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
1011 s->invalidated = 1;
1012 s->irq = irq;
1013 s->sysmem = sysmem;
1014
1015 pxa2xx_lcdc_orientation(s, graphic_rotate);
1016
1017 memory_region_init_io(&s->iomem, NULL, &pxa2xx_lcdc_ops, s,
1018 "pxa2xx-lcd-controller", 0x00100000);
1019 memory_region_add_subregion(sysmem, base, &s->iomem);
1020
1021 s->con = graphic_console_init(NULL, 0, &pxa2xx_ops, s);
1022 surface = qemu_console_surface(s->con);
1023
1024 switch (surface_bits_per_pixel(surface)) {
1025 case 0:
1026 s->dest_width = 0;
1027 break;
1028 case 8:
1029 s->line_fn[0] = pxa2xx_draw_fn_8;
1030 s->line_fn[1] = pxa2xx_draw_fn_8t;
1031 s->dest_width = 1;
1032 break;
1033 case 15:
1034 s->line_fn[0] = pxa2xx_draw_fn_15;
1035 s->line_fn[1] = pxa2xx_draw_fn_15t;
1036 s->dest_width = 2;
1037 break;
1038 case 16:
1039 s->line_fn[0] = pxa2xx_draw_fn_16;
1040 s->line_fn[1] = pxa2xx_draw_fn_16t;
1041 s->dest_width = 2;
1042 break;
1043 case 24:
1044 s->line_fn[0] = pxa2xx_draw_fn_24;
1045 s->line_fn[1] = pxa2xx_draw_fn_24t;
1046 s->dest_width = 3;
1047 break;
1048 case 32:
1049 s->line_fn[0] = pxa2xx_draw_fn_32;
1050 s->line_fn[1] = pxa2xx_draw_fn_32t;
1051 s->dest_width = 4;
1052 break;
1053 default:
1054 fprintf(stderr, "%s: Bad color depth\n", __func__);
1055 exit(1);
1056 }
1057
1058 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
1059
1060 return s;
1061 }
1062
1063 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
1064 {
1065 s->vsync_cb = handler;
1066 }
Mirror of https://git.qemu.org/git/qemu.git